2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
42 static int hclge_update_led_status(struct hclge_dev
*hdev
);
44 static struct hnae3_ae_algo ae_algo
;
46 static const struct pci_device_id ae_algo_pci_tbl
[] = {
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
53 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
54 /* required last entry */
58 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
60 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
62 "Serdes Loopback test",
66 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
67 {"igu_rx_oversize_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
69 {"igu_rx_undersize_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
71 {"igu_rx_out_all_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
78 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
79 {"egu_tx_out_all_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
86 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
87 {"ssu_ppp_mac_key_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
89 {"ssu_ppp_host_key_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
91 {"ppp_ssu_mac_rlt_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
93 {"ppp_ssu_host_rlt_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
102 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
105 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
108 {"igu_rx_no_eof_pkt",
109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
110 {"igu_rx_no_sof_pkt",
111 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
113 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
114 {"ssu_full_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
116 {"ssu_part_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
121 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
123 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
125 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
130 {"qcn_fb_invaild_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
132 {"rx_packet_tc0_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
134 {"rx_packet_tc1_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
136 {"rx_packet_tc2_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
138 {"rx_packet_tc3_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
140 {"rx_packet_tc4_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
142 {"rx_packet_tc5_in_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
144 {"rx_packet_tc6_in_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
146 {"rx_packet_tc7_in_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
148 {"rx_packet_tc0_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
150 {"rx_packet_tc1_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
152 {"rx_packet_tc2_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
154 {"rx_packet_tc3_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
156 {"rx_packet_tc4_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
158 {"rx_packet_tc5_out_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
160 {"rx_packet_tc6_out_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
162 {"rx_packet_tc7_out_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
164 {"tx_packet_tc0_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
166 {"tx_packet_tc1_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
168 {"tx_packet_tc2_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
170 {"tx_packet_tc3_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
172 {"tx_packet_tc4_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
174 {"tx_packet_tc5_in_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
176 {"tx_packet_tc6_in_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
178 {"tx_packet_tc7_in_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
180 {"tx_packet_tc0_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
182 {"tx_packet_tc1_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
184 {"tx_packet_tc2_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
186 {"tx_packet_tc3_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
188 {"tx_packet_tc4_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
190 {"tx_packet_tc5_out_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
192 {"tx_packet_tc6_out_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
194 {"tx_packet_tc7_out_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
196 {"pkt_curr_buf_tc0_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
198 {"pkt_curr_buf_tc1_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
200 {"pkt_curr_buf_tc2_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
202 {"pkt_curr_buf_tc3_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
204 {"pkt_curr_buf_tc4_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
206 {"pkt_curr_buf_tc5_cnt",
207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
208 {"pkt_curr_buf_tc6_cnt",
209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
210 {"pkt_curr_buf_tc7_cnt",
211 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
213 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
214 {"lo_pri_unicast_rlt_drop_num",
215 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
216 {"hi_pri_multicast_rlt_drop_num",
217 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
218 {"lo_pri_multicast_rlt_drop_num",
219 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
220 {"rx_oq_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
222 {"tx_oq_drop_pkt_cnt",
223 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
224 {"nic_l2_err_drop_pkt_cnt",
225 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
226 {"roc_l2_err_drop_pkt_cnt",
227 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
230 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
231 {"mac_tx_mac_pause_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
233 {"mac_rx_mac_pause_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
235 {"mac_tx_pfc_pri0_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
237 {"mac_tx_pfc_pri1_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
239 {"mac_tx_pfc_pri2_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
241 {"mac_tx_pfc_pri3_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
243 {"mac_tx_pfc_pri4_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
245 {"mac_tx_pfc_pri5_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
247 {"mac_tx_pfc_pri6_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
249 {"mac_tx_pfc_pri7_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
251 {"mac_rx_pfc_pri0_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
253 {"mac_rx_pfc_pri1_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
255 {"mac_rx_pfc_pri2_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
257 {"mac_rx_pfc_pri3_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
259 {"mac_rx_pfc_pri4_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
261 {"mac_rx_pfc_pri5_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
263 {"mac_rx_pfc_pri6_pkt_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
265 {"mac_rx_pfc_pri7_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
267 {"mac_tx_total_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
269 {"mac_tx_total_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
271 {"mac_tx_good_pkt_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
273 {"mac_tx_bad_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
275 {"mac_tx_good_oct_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
277 {"mac_tx_bad_oct_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
279 {"mac_tx_uni_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
281 {"mac_tx_multi_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
283 {"mac_tx_broad_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
285 {"mac_tx_undersize_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
287 {"mac_tx_oversize_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
289 {"mac_tx_64_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
291 {"mac_tx_65_127_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
293 {"mac_tx_128_255_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
295 {"mac_tx_256_511_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
297 {"mac_tx_512_1023_oct_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
299 {"mac_tx_1024_1518_oct_pkt_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
301 {"mac_tx_1519_2047_oct_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
303 {"mac_tx_2048_4095_oct_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
305 {"mac_tx_4096_8191_oct_pkt_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
307 {"mac_tx_8192_12287_oct_pkt_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num
)},
309 {"mac_tx_8192_9216_oct_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
311 {"mac_tx_9217_12287_oct_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
313 {"mac_tx_12288_16383_oct_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
315 {"mac_tx_1519_max_good_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
317 {"mac_tx_1519_max_bad_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
319 {"mac_rx_total_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
321 {"mac_rx_total_oct_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
323 {"mac_rx_good_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
325 {"mac_rx_bad_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
327 {"mac_rx_good_oct_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
329 {"mac_rx_bad_oct_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
331 {"mac_rx_uni_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
333 {"mac_rx_multi_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
335 {"mac_rx_broad_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
337 {"mac_rx_undersize_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
339 {"mac_rx_oversize_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
341 {"mac_rx_64_oct_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
343 {"mac_rx_65_127_oct_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
345 {"mac_rx_128_255_oct_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
347 {"mac_rx_256_511_oct_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
349 {"mac_rx_512_1023_oct_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
351 {"mac_rx_1024_1518_oct_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
353 {"mac_rx_1519_2047_oct_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
355 {"mac_rx_2048_4095_oct_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
357 {"mac_rx_4096_8191_oct_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
359 {"mac_rx_8192_12287_oct_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num
)},
361 {"mac_rx_8192_9216_oct_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
363 {"mac_rx_9217_12287_oct_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
365 {"mac_rx_12288_16383_oct_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
367 {"mac_rx_1519_max_good_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
369 {"mac_rx_1519_max_bad_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
372 {"mac_tx_fragment_pkt_num",
373 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
374 {"mac_tx_undermin_pkt_num",
375 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
376 {"mac_tx_jabber_pkt_num",
377 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
378 {"mac_tx_err_all_pkt_num",
379 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
380 {"mac_tx_from_app_good_pkt_num",
381 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
382 {"mac_tx_from_app_bad_pkt_num",
383 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
384 {"mac_rx_fragment_pkt_num",
385 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
386 {"mac_rx_undermin_pkt_num",
387 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
388 {"mac_rx_jabber_pkt_num",
389 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
390 {"mac_rx_fcs_err_pkt_num",
391 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
392 {"mac_rx_send_app_good_pkt_num",
393 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
394 {"mac_rx_send_app_bad_pkt_num",
395 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
398 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
400 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
401 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
402 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
403 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
404 .i_port_bitmap
= 0x1,
408 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
410 #define HCLGE_64_BIT_CMD_NUM 5
411 #define HCLGE_64_BIT_RTN_DATANUM 4
412 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
413 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
418 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
419 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
421 dev_err(&hdev
->pdev
->dev
,
422 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
426 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
427 if (unlikely(i
== 0)) {
428 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
429 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
431 desc_data
= (__le64
*)(&desc
[i
]);
432 n
= HCLGE_64_BIT_RTN_DATANUM
;
434 for (k
= 0; k
< n
; k
++) {
435 *data
++ += le64_to_cpu(*desc_data
);
443 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
445 stats
->pkt_curr_buf_cnt
= 0;
446 stats
->pkt_curr_buf_tc0_cnt
= 0;
447 stats
->pkt_curr_buf_tc1_cnt
= 0;
448 stats
->pkt_curr_buf_tc2_cnt
= 0;
449 stats
->pkt_curr_buf_tc3_cnt
= 0;
450 stats
->pkt_curr_buf_tc4_cnt
= 0;
451 stats
->pkt_curr_buf_tc5_cnt
= 0;
452 stats
->pkt_curr_buf_tc6_cnt
= 0;
453 stats
->pkt_curr_buf_tc7_cnt
= 0;
456 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
458 #define HCLGE_32_BIT_CMD_NUM 8
459 #define HCLGE_32_BIT_RTN_DATANUM 8
461 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
462 struct hclge_32_bit_stats
*all_32_bit_stats
;
468 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
469 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
471 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
472 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
474 dev_err(&hdev
->pdev
->dev
,
475 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
480 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
481 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
482 if (unlikely(i
== 0)) {
483 __le16
*desc_data_16bit
;
485 all_32_bit_stats
->igu_rx_err_pkt
+=
486 le32_to_cpu(desc
[i
].data
[0]);
488 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
489 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
490 le16_to_cpu(*desc_data_16bit
);
493 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
494 le16_to_cpu(*desc_data_16bit
);
496 desc_data
= &desc
[i
].data
[2];
497 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
499 desc_data
= (__le32
*)&desc
[i
];
500 n
= HCLGE_32_BIT_RTN_DATANUM
;
502 for (k
= 0; k
< n
; k
++) {
503 *data
++ += le32_to_cpu(*desc_data
);
511 static int hclge_mac_get_traffic_stats(struct hclge_dev
*hdev
)
513 struct hclge_mac_stats
*mac_stats
= &hdev
->hw_stats
.mac_stats
;
514 struct hclge_desc desc
;
518 /* for fiber port, need to query the total rx/tx packets statstics,
519 * used for data transferring checking.
521 if (hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
524 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
527 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_STATS_MAC_TRAFFIC
, true);
528 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
530 dev_err(&hdev
->pdev
->dev
,
531 "Get MAC total pkt stats fail, ret = %d\n", ret
);
536 desc_data
= (__le64
*)(&desc
.data
[0]);
537 mac_stats
->mac_tx_total_pkt_num
+= le64_to_cpu(*desc_data
++);
538 mac_stats
->mac_rx_total_pkt_num
+= le64_to_cpu(*desc_data
);
543 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
545 #define HCLGE_MAC_CMD_NUM 21
546 #define HCLGE_RTN_DATA_NUM 4
548 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
549 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
554 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
555 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
557 dev_err(&hdev
->pdev
->dev
,
558 "Get MAC pkt stats fail, status = %d.\n", ret
);
563 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
564 if (unlikely(i
== 0)) {
565 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
566 n
= HCLGE_RTN_DATA_NUM
- 2;
568 desc_data
= (__le64
*)(&desc
[i
]);
569 n
= HCLGE_RTN_DATA_NUM
;
571 for (k
= 0; k
< n
; k
++) {
572 *data
++ += le64_to_cpu(*desc_data
);
580 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
582 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
583 struct hclge_vport
*vport
= hclge_get_vport(handle
);
584 struct hclge_dev
*hdev
= vport
->back
;
585 struct hnae3_queue
*queue
;
586 struct hclge_desc desc
[1];
587 struct hclge_tqp
*tqp
;
590 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
591 queue
= handle
->kinfo
.tqp
[i
];
592 tqp
= container_of(queue
, struct hclge_tqp
, q
);
593 /* command : HCLGE_OPC_QUERY_IGU_STAT */
594 hclge_cmd_setup_basic_desc(&desc
[0],
595 HCLGE_OPC_QUERY_RX_STATUS
,
598 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
599 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
601 dev_err(&hdev
->pdev
->dev
,
602 "Query tqp stat fail, status = %d,queue = %d\n",
606 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
607 le32_to_cpu(desc
[0].data
[1]);
610 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
611 queue
= handle
->kinfo
.tqp
[i
];
612 tqp
= container_of(queue
, struct hclge_tqp
, q
);
613 /* command : HCLGE_OPC_QUERY_IGU_STAT */
614 hclge_cmd_setup_basic_desc(&desc
[0],
615 HCLGE_OPC_QUERY_TX_STATUS
,
618 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
619 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
621 dev_err(&hdev
->pdev
->dev
,
622 "Query tqp stat fail, status = %d,queue = %d\n",
626 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
627 le32_to_cpu(desc
[0].data
[1]);
633 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
635 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
636 struct hclge_tqp
*tqp
;
640 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
641 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
642 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
645 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
646 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
647 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
653 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
655 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
657 return kinfo
->num_tqps
* (2);
660 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
662 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
666 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
667 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
668 struct hclge_tqp
, q
);
669 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
671 buff
= buff
+ ETH_GSTRING_LEN
;
674 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
675 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
676 struct hclge_tqp
, q
);
677 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
679 buff
= buff
+ ETH_GSTRING_LEN
;
685 static u64
*hclge_comm_get_stats(void *comm_stats
,
686 const struct hclge_comm_stats_str strs
[],
692 for (i
= 0; i
< size
; i
++)
693 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
698 static u8
*hclge_comm_get_strings(u32 stringset
,
699 const struct hclge_comm_stats_str strs
[],
702 char *buff
= (char *)data
;
705 if (stringset
!= ETH_SS_STATS
)
708 for (i
= 0; i
< size
; i
++) {
709 snprintf(buff
, ETH_GSTRING_LEN
,
711 buff
= buff
+ ETH_GSTRING_LEN
;
717 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
718 struct net_device_stats
*net_stats
)
720 net_stats
->tx_dropped
= 0;
721 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
722 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
723 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
725 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
726 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
727 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
728 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
729 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
731 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
732 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
734 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
735 net_stats
->rx_length_errors
=
736 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
737 net_stats
->rx_length_errors
+=
738 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
739 net_stats
->rx_over_errors
=
740 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
743 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
745 struct hnae3_handle
*handle
;
748 handle
= &hdev
->vport
[0].nic
;
749 if (handle
->client
) {
750 status
= hclge_tqps_update_stats(handle
);
752 dev_err(&hdev
->pdev
->dev
,
753 "Update TQPS stats fail, status = %d.\n",
758 status
= hclge_mac_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update MAC stats fail, status = %d.\n", status
);
763 status
= hclge_32_bit_update_stats(hdev
);
765 dev_err(&hdev
->pdev
->dev
,
766 "Update 32 bit stats fail, status = %d.\n",
769 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
772 static void hclge_update_stats(struct hnae3_handle
*handle
,
773 struct net_device_stats
*net_stats
)
775 struct hclge_vport
*vport
= hclge_get_vport(handle
);
776 struct hclge_dev
*hdev
= vport
->back
;
777 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
780 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
783 status
= hclge_mac_update_stats(hdev
);
785 dev_err(&hdev
->pdev
->dev
,
786 "Update MAC stats fail, status = %d.\n",
789 status
= hclge_32_bit_update_stats(hdev
);
791 dev_err(&hdev
->pdev
->dev
,
792 "Update 32 bit stats fail, status = %d.\n",
795 status
= hclge_64_bit_update_stats(hdev
);
797 dev_err(&hdev
->pdev
->dev
,
798 "Update 64 bit stats fail, status = %d.\n",
801 status
= hclge_tqps_update_stats(handle
);
803 dev_err(&hdev
->pdev
->dev
,
804 "Update TQPS stats fail, status = %d.\n",
807 hclge_update_netstat(hw_stats
, net_stats
);
809 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
812 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
814 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
816 struct hclge_vport
*vport
= hclge_get_vport(handle
);
817 struct hclge_dev
*hdev
= vport
->back
;
820 /* Loopback test support rules:
821 * mac: only GE mode support
822 * serdes: all mac mode will support include GE/XGE/LGE/CGE
823 * phy: only support when phy device exist on board
825 if (stringset
== ETH_SS_TEST
) {
826 /* clear loopback bit flags at first */
827 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
828 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
829 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
830 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
832 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
836 } else if (stringset
== ETH_SS_STATS
) {
837 count
= ARRAY_SIZE(g_mac_stats_string
) +
838 ARRAY_SIZE(g_all_32bit_stats_string
) +
839 ARRAY_SIZE(g_all_64bit_stats_string
) +
840 hclge_tqps_get_sset_count(handle
, stringset
);
846 static void hclge_get_strings(struct hnae3_handle
*handle
,
850 u8
*p
= (char *)data
;
853 if (stringset
== ETH_SS_STATS
) {
854 size
= ARRAY_SIZE(g_mac_stats_string
);
855 p
= hclge_comm_get_strings(stringset
,
859 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
860 p
= hclge_comm_get_strings(stringset
,
861 g_all_32bit_stats_string
,
864 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
865 p
= hclge_comm_get_strings(stringset
,
866 g_all_64bit_stats_string
,
869 p
= hclge_tqps_get_strings(handle
, p
);
870 } else if (stringset
== ETH_SS_TEST
) {
871 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
873 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
875 p
+= ETH_GSTRING_LEN
;
877 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
879 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
881 p
+= ETH_GSTRING_LEN
;
883 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
885 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
887 p
+= ETH_GSTRING_LEN
;
892 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
894 struct hclge_vport
*vport
= hclge_get_vport(handle
);
895 struct hclge_dev
*hdev
= vport
->back
;
898 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
900 ARRAY_SIZE(g_mac_stats_string
),
902 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
903 g_all_32bit_stats_string
,
904 ARRAY_SIZE(g_all_32bit_stats_string
),
906 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
907 g_all_64bit_stats_string
,
908 ARRAY_SIZE(g_all_64bit_stats_string
),
910 p
= hclge_tqps_get_stats(handle
, p
);
913 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
914 struct hclge_func_status_cmd
*status
)
916 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
919 /* Set the pf to main pf */
920 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
921 hdev
->flag
|= HCLGE_FLAG_MAIN
;
923 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
928 static int hclge_query_function_status(struct hclge_dev
*hdev
)
930 struct hclge_func_status_cmd
*req
;
931 struct hclge_desc desc
;
935 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
936 req
= (struct hclge_func_status_cmd
*)desc
.data
;
939 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
941 dev_err(&hdev
->pdev
->dev
,
942 "query function status failed %d.\n",
948 /* Check pf reset is done */
951 usleep_range(1000, 2000);
952 } while (timeout
++ < 5);
954 ret
= hclge_parse_func_status(hdev
, req
);
959 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
961 struct hclge_pf_res_cmd
*req
;
962 struct hclge_desc desc
;
965 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
966 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
968 dev_err(&hdev
->pdev
->dev
,
969 "query pf resource failed %d.\n", ret
);
973 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
974 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
975 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
977 if (hnae3_dev_roce_supported(hdev
)) {
979 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
980 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
982 /* PF should have NIC vectors and Roce vectors,
983 * NIC vectors are queued before Roce vectors.
985 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
988 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
989 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
995 static int hclge_parse_speed(int speed_cmd
, int *speed
)
999 *speed
= HCLGE_MAC_SPEED_10M
;
1002 *speed
= HCLGE_MAC_SPEED_100M
;
1005 *speed
= HCLGE_MAC_SPEED_1G
;
1008 *speed
= HCLGE_MAC_SPEED_10G
;
1011 *speed
= HCLGE_MAC_SPEED_25G
;
1014 *speed
= HCLGE_MAC_SPEED_40G
;
1017 *speed
= HCLGE_MAC_SPEED_50G
;
1020 *speed
= HCLGE_MAC_SPEED_100G
;
1029 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
1032 unsigned long *supported
= hdev
->hw
.mac
.supported
;
1034 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
1035 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1038 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1039 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1042 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1043 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1046 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1047 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1050 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1051 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1054 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1055 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1058 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1060 u8 media_type
= hdev
->hw
.mac
.media_type
;
1062 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1065 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1068 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1070 struct hclge_cfg_param_cmd
*req
;
1071 u64 mac_addr_tmp_high
;
1075 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1077 /* get the configuration */
1078 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1081 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1082 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1083 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1084 HCLGE_CFG_TQP_DESC_N_M
,
1085 HCLGE_CFG_TQP_DESC_N_S
);
1087 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1088 HCLGE_CFG_PHY_ADDR_M
,
1089 HCLGE_CFG_PHY_ADDR_S
);
1090 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1091 HCLGE_CFG_MEDIA_TP_M
,
1092 HCLGE_CFG_MEDIA_TP_S
);
1093 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1094 HCLGE_CFG_RX_BUF_LEN_M
,
1095 HCLGE_CFG_RX_BUF_LEN_S
);
1096 /* get mac_address */
1097 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1098 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1099 HCLGE_CFG_MAC_ADDR_H_M
,
1100 HCLGE_CFG_MAC_ADDR_H_S
);
1102 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1104 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1105 HCLGE_CFG_DEFAULT_SPEED_M
,
1106 HCLGE_CFG_DEFAULT_SPEED_S
);
1107 cfg
->rss_size_max
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1108 HCLGE_CFG_RSS_SIZE_M
,
1109 HCLGE_CFG_RSS_SIZE_S
);
1111 for (i
= 0; i
< ETH_ALEN
; i
++)
1112 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1114 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1115 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1117 cfg
->speed_ability
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1118 HCLGE_CFG_SPEED_ABILITY_M
,
1119 HCLGE_CFG_SPEED_ABILITY_S
);
1122 /* hclge_get_cfg: query the static parameter from flash
1123 * @hdev: pointer to struct hclge_dev
1124 * @hcfg: the config structure to be getted
1126 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1128 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1129 struct hclge_cfg_param_cmd
*req
;
1132 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1135 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1136 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1138 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1139 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1140 /* Len should be united by 4 bytes when send to hardware */
1141 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1142 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1143 req
->offset
= cpu_to_le32(offset
);
1146 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1148 dev_err(&hdev
->pdev
->dev
,
1149 "get config failed %d.\n", ret
);
1153 hclge_parse_cfg(hcfg
, desc
);
1157 static int hclge_get_cap(struct hclge_dev
*hdev
)
1161 ret
= hclge_query_function_status(hdev
);
1163 dev_err(&hdev
->pdev
->dev
,
1164 "query function status error %d.\n", ret
);
1168 /* get pf resource */
1169 ret
= hclge_query_pf_resource(hdev
);
1171 dev_err(&hdev
->pdev
->dev
,
1172 "query pf resource error %d.\n", ret
);
1179 static int hclge_configure(struct hclge_dev
*hdev
)
1181 struct hclge_cfg cfg
;
1184 ret
= hclge_get_cfg(hdev
, &cfg
);
1186 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1190 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1191 hdev
->base_tqp_pid
= 0;
1192 hdev
->rss_size_max
= cfg
.rss_size_max
;
1193 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1194 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1195 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1196 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1197 hdev
->num_desc
= cfg
.tqp_desc_num
;
1198 hdev
->tm_info
.num_pg
= 1;
1199 hdev
->tc_max
= cfg
.tc_num
;
1200 hdev
->tm_info
.hw_pfc_map
= 0;
1202 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1204 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1208 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1210 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1211 (hdev
->tc_max
< 1)) {
1212 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1217 /* Dev does not support DCB */
1218 if (!hnae3_dev_dcb_supported(hdev
)) {
1222 hdev
->pfc_max
= hdev
->tc_max
;
1225 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1227 /* Currently not support uncontiuous tc */
1228 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1229 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1231 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1236 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1239 struct hclge_cfg_tso_status_cmd
*req
;
1240 struct hclge_desc desc
;
1243 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1245 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1248 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1249 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1250 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1253 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1254 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1255 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1257 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1260 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1262 struct hclge_tqp
*tqp
;
1265 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1266 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1272 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1273 tqp
->dev
= &hdev
->pdev
->dev
;
1276 tqp
->q
.ae_algo
= &ae_algo
;
1277 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1278 tqp
->q
.desc_num
= hdev
->num_desc
;
1279 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1280 i
* HCLGE_TQP_REG_SIZE
;
1288 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1289 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1291 struct hclge_tqp_map_cmd
*req
;
1292 struct hclge_desc desc
;
1295 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1297 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1298 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1299 req
->tqp_vf
= func_id
;
1300 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1301 1 << HCLGE_TQP_MAP_EN_B
;
1302 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1304 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1306 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1314 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1315 struct hnae3_queue
**tqp
, u16 num_tqps
)
1317 struct hclge_dev
*hdev
= vport
->back
;
1320 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1321 alloced
< num_tqps
; i
++) {
1322 if (!hdev
->htqp
[i
].alloced
) {
1323 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1324 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1325 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1326 hdev
->htqp
[i
].alloced
= true;
1330 vport
->alloc_tqps
= num_tqps
;
1335 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1337 struct hnae3_handle
*nic
= &vport
->nic
;
1338 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1339 struct hclge_dev
*hdev
= vport
->back
;
1342 kinfo
->num_desc
= hdev
->num_desc
;
1343 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1344 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1346 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1347 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1349 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1350 if (hdev
->hw_tc_map
& BIT(i
)) {
1351 kinfo
->tc_info
[i
].enable
= true;
1352 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1353 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1354 kinfo
->tc_info
[i
].tc
= i
;
1356 /* Set to default queue if TC is disable */
1357 kinfo
->tc_info
[i
].enable
= false;
1358 kinfo
->tc_info
[i
].tqp_offset
= 0;
1359 kinfo
->tc_info
[i
].tqp_count
= 1;
1360 kinfo
->tc_info
[i
].tc
= 0;
1364 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1365 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1369 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1371 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1378 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1379 struct hclge_vport
*vport
)
1381 struct hnae3_handle
*nic
= &vport
->nic
;
1382 struct hnae3_knic_private_info
*kinfo
;
1385 kinfo
= &nic
->kinfo
;
1386 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1387 struct hclge_tqp
*q
=
1388 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1392 is_pf
= !(vport
->vport_id
);
1393 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1402 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1404 struct hclge_vport
*vport
= hdev
->vport
;
1407 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1408 for (i
= 0; i
< num_vport
; i
++) {
1411 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1421 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1423 /* this would be initialized later */
1426 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1428 struct hnae3_handle
*nic
= &vport
->nic
;
1429 struct hclge_dev
*hdev
= vport
->back
;
1432 nic
->pdev
= hdev
->pdev
;
1433 nic
->ae_algo
= &ae_algo
;
1434 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1436 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1437 ret
= hclge_knic_setup(vport
, num_tqps
);
1439 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1444 hclge_unic_setup(vport
, num_tqps
);
1450 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1452 struct pci_dev
*pdev
= hdev
->pdev
;
1453 struct hclge_vport
*vport
;
1459 /* We need to alloc a vport for main NIC of PF */
1460 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1462 if (hdev
->num_tqps
< num_vport
)
1463 num_vport
= hdev
->num_tqps
;
1465 /* Alloc the same number of TQPs for every vport */
1466 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1467 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1469 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1474 hdev
->vport
= vport
;
1475 hdev
->num_alloc_vport
= num_vport
;
1477 #ifdef CONFIG_PCI_IOV
1479 if (hdev
->num_req_vfs
) {
1480 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1482 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1484 hdev
->num_alloc_vfs
= 0;
1485 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1490 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1493 for (i
= 0; i
< num_vport
; i
++) {
1495 vport
->vport_id
= i
;
1498 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1500 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1503 "vport setup failed for vport %d, %d\n",
1514 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1515 struct hclge_pkt_buf_alloc
*buf_alloc
)
1517 /* TX buffer size is unit by 128 byte */
1518 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1519 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1520 struct hclge_tx_buff_alloc_cmd
*req
;
1521 struct hclge_desc desc
;
1525 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1527 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1528 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1529 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1531 req
->tx_pkt_buff
[i
] =
1532 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1533 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1536 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1538 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1546 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1547 struct hclge_pkt_buf_alloc
*buf_alloc
)
1549 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1552 dev_err(&hdev
->pdev
->dev
,
1553 "tx buffer alloc failed %d\n", ret
);
1560 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1564 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1565 if (hdev
->hw_tc_map
& BIT(i
))
1570 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1574 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1575 if (hdev
->hw_tc_map
& BIT(i
) &&
1576 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1581 /* Get the number of pfc enabled TCs, which have private buffer */
1582 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1583 struct hclge_pkt_buf_alloc
*buf_alloc
)
1585 struct hclge_priv_buf
*priv
;
1588 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1589 priv
= &buf_alloc
->priv_buf
[i
];
1590 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1598 /* Get the number of pfc disabled TCs, which have private buffer */
1599 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1600 struct hclge_pkt_buf_alloc
*buf_alloc
)
1602 struct hclge_priv_buf
*priv
;
1605 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1606 priv
= &buf_alloc
->priv_buf
[i
];
1607 if (hdev
->hw_tc_map
& BIT(i
) &&
1608 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1616 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1618 struct hclge_priv_buf
*priv
;
1622 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1623 priv
= &buf_alloc
->priv_buf
[i
];
1625 rx_priv
+= priv
->buf_size
;
1630 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1632 u32 i
, total_tx_size
= 0;
1634 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1635 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1637 return total_tx_size
;
1640 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1641 struct hclge_pkt_buf_alloc
*buf_alloc
,
1644 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1645 int tc_num
, pfc_enable_num
;
1650 tc_num
= hclge_get_tc_num(hdev
);
1651 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1653 if (hnae3_dev_dcb_supported(hdev
))
1654 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1656 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1658 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1659 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1661 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1663 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1664 if (rx_all
<= rx_priv
+ shared_std
)
1667 shared_buf
= rx_all
- rx_priv
;
1668 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1669 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1670 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1672 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1673 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1674 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1675 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1676 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1678 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1679 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1686 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1687 struct hclge_pkt_buf_alloc
*buf_alloc
)
1691 total_size
= hdev
->pkt_buf_size
;
1693 /* alloc tx buffer for all enabled tc */
1694 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1695 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1697 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1700 if (hdev
->hw_tc_map
& BIT(i
))
1701 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1703 priv
->tx_buf_size
= 0;
1705 total_size
-= priv
->tx_buf_size
;
1711 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1712 * @hdev: pointer to struct hclge_dev
1713 * @buf_alloc: pointer to buffer calculation data
1714 * @return: 0: calculate sucessful, negative: fail
1716 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1717 struct hclge_pkt_buf_alloc
*buf_alloc
)
1719 u32 rx_all
= hdev
->pkt_buf_size
;
1720 int no_pfc_priv_num
, pfc_priv_num
;
1721 struct hclge_priv_buf
*priv
;
1724 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1726 /* When DCB is not supported, rx private
1727 * buffer is not allocated.
1729 if (!hnae3_dev_dcb_supported(hdev
)) {
1730 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1736 /* step 1, try to alloc private buffer for all enabled tc */
1737 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1738 priv
= &buf_alloc
->priv_buf
[i
];
1739 if (hdev
->hw_tc_map
& BIT(i
)) {
1741 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1742 priv
->wl
.low
= hdev
->mps
;
1743 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1744 priv
->buf_size
= priv
->wl
.high
+
1748 priv
->wl
.high
= 2 * hdev
->mps
;
1749 priv
->buf_size
= priv
->wl
.high
;
1759 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1762 /* step 2, try to decrease the buffer size of
1763 * no pfc TC's private buffer
1765 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1766 priv
= &buf_alloc
->priv_buf
[i
];
1773 if (!(hdev
->hw_tc_map
& BIT(i
)))
1778 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1780 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1781 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1784 priv
->wl
.high
= hdev
->mps
;
1785 priv
->buf_size
= priv
->wl
.high
;
1789 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1792 /* step 3, try to reduce the number of pfc disabled TCs,
1793 * which have private buffer
1795 /* get the total no pfc enable TC number, which have private buffer */
1796 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1798 /* let the last to be cleared first */
1799 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1800 priv
= &buf_alloc
->priv_buf
[i
];
1802 if (hdev
->hw_tc_map
& BIT(i
) &&
1803 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1804 /* Clear the no pfc TC private buffer */
1812 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1813 no_pfc_priv_num
== 0)
1817 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1820 /* step 4, try to reduce the number of pfc enabled TCs
1821 * which have private buffer.
1823 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1825 /* let the last to be cleared first */
1826 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1827 priv
= &buf_alloc
->priv_buf
[i
];
1829 if (hdev
->hw_tc_map
& BIT(i
) &&
1830 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1831 /* Reduce the number of pfc TC with private buffer */
1839 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1843 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1849 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1850 struct hclge_pkt_buf_alloc
*buf_alloc
)
1852 struct hclge_rx_priv_buff_cmd
*req
;
1853 struct hclge_desc desc
;
1857 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1858 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1860 /* Alloc private buffer TCs */
1861 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1862 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1865 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1867 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1871 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1872 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1874 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1876 dev_err(&hdev
->pdev
->dev
,
1877 "rx private buffer alloc cmd failed %d\n", ret
);
1884 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1886 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1887 struct hclge_pkt_buf_alloc
*buf_alloc
)
1889 struct hclge_rx_priv_wl_buf
*req
;
1890 struct hclge_priv_buf
*priv
;
1891 struct hclge_desc desc
[2];
1895 for (i
= 0; i
< 2; i
++) {
1896 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1898 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1900 /* The first descriptor set the NEXT bit to 1 */
1902 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1904 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1906 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1907 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1909 priv
= &buf_alloc
->priv_buf
[idx
];
1910 req
->tc_wl
[j
].high
=
1911 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1912 req
->tc_wl
[j
].high
|=
1913 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1914 HCLGE_RX_PRIV_EN_B
);
1916 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1917 req
->tc_wl
[j
].low
|=
1918 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1919 HCLGE_RX_PRIV_EN_B
);
1923 /* Send 2 descriptor at one time */
1924 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1926 dev_err(&hdev
->pdev
->dev
,
1927 "rx private waterline config cmd failed %d\n",
1934 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1935 struct hclge_pkt_buf_alloc
*buf_alloc
)
1937 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1938 struct hclge_rx_com_thrd
*req
;
1939 struct hclge_desc desc
[2];
1940 struct hclge_tc_thrd
*tc
;
1944 for (i
= 0; i
< 2; i
++) {
1945 hclge_cmd_setup_basic_desc(&desc
[i
],
1946 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1947 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1949 /* The first descriptor set the NEXT bit to 1 */
1951 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1953 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1955 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1956 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1958 req
->com_thrd
[j
].high
=
1959 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1960 req
->com_thrd
[j
].high
|=
1961 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1962 HCLGE_RX_PRIV_EN_B
);
1963 req
->com_thrd
[j
].low
=
1964 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1965 req
->com_thrd
[j
].low
|=
1966 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1967 HCLGE_RX_PRIV_EN_B
);
1971 /* Send 2 descriptors at one time */
1972 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1974 dev_err(&hdev
->pdev
->dev
,
1975 "common threshold config cmd failed %d\n", ret
);
1981 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1982 struct hclge_pkt_buf_alloc
*buf_alloc
)
1984 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1985 struct hclge_rx_com_wl
*req
;
1986 struct hclge_desc desc
;
1989 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1991 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1992 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1994 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1995 HCLGE_RX_PRIV_EN_B
);
1997 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1999 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
2000 HCLGE_RX_PRIV_EN_B
);
2002 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2004 dev_err(&hdev
->pdev
->dev
,
2005 "common waterline config cmd failed %d\n", ret
);
2012 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
2014 struct hclge_pkt_buf_alloc
*pkt_buf
;
2017 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
2021 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
2023 dev_err(&hdev
->pdev
->dev
,
2024 "could not calc tx buffer size for all TCs %d\n", ret
);
2028 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
2030 dev_err(&hdev
->pdev
->dev
,
2031 "could not alloc tx buffers %d\n", ret
);
2035 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
2037 dev_err(&hdev
->pdev
->dev
,
2038 "could not calc rx priv buffer size for all TCs %d\n",
2043 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
2045 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
2050 if (hnae3_dev_dcb_supported(hdev
)) {
2051 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
2053 dev_err(&hdev
->pdev
->dev
,
2054 "could not configure rx private waterline %d\n",
2059 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
2061 dev_err(&hdev
->pdev
->dev
,
2062 "could not configure common threshold %d\n",
2068 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2070 dev_err(&hdev
->pdev
->dev
,
2071 "could not configure common waterline %d\n", ret
);
2078 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2080 struct hnae3_handle
*roce
= &vport
->roce
;
2081 struct hnae3_handle
*nic
= &vport
->nic
;
2083 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2085 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2086 vport
->back
->num_msi_left
== 0)
2089 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2091 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2092 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2094 roce
->pdev
= nic
->pdev
;
2095 roce
->ae_algo
= nic
->ae_algo
;
2096 roce
->numa_node_mask
= nic
->numa_node_mask
;
2101 static int hclge_init_msi(struct hclge_dev
*hdev
)
2103 struct pci_dev
*pdev
= hdev
->pdev
;
2107 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2108 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2111 "failed(%d) to allocate MSI/MSI-X vectors\n",
2115 if (vectors
< hdev
->num_msi
)
2116 dev_warn(&hdev
->pdev
->dev
,
2117 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2118 hdev
->num_msi
, vectors
);
2120 hdev
->num_msi
= vectors
;
2121 hdev
->num_msi_left
= vectors
;
2122 hdev
->base_msi_vector
= pdev
->irq
;
2123 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2124 HCLGE_ROCE_VECTOR_OFFSET
;
2126 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2127 sizeof(u16
), GFP_KERNEL
);
2128 if (!hdev
->vector_status
) {
2129 pci_free_irq_vectors(pdev
);
2133 for (i
= 0; i
< hdev
->num_msi
; i
++)
2134 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2136 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2137 sizeof(int), GFP_KERNEL
);
2138 if (!hdev
->vector_irq
) {
2139 pci_free_irq_vectors(pdev
);
2146 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2148 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2150 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2151 mac
->duplex
= (u8
)duplex
;
2153 mac
->duplex
= HCLGE_MAC_FULL
;
2158 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2160 struct hclge_config_mac_speed_dup_cmd
*req
;
2161 struct hclge_desc desc
;
2164 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2166 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2168 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2171 case HCLGE_MAC_SPEED_10M
:
2172 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2173 HCLGE_CFG_SPEED_S
, 6);
2175 case HCLGE_MAC_SPEED_100M
:
2176 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2177 HCLGE_CFG_SPEED_S
, 7);
2179 case HCLGE_MAC_SPEED_1G
:
2180 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2181 HCLGE_CFG_SPEED_S
, 0);
2183 case HCLGE_MAC_SPEED_10G
:
2184 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2185 HCLGE_CFG_SPEED_S
, 1);
2187 case HCLGE_MAC_SPEED_25G
:
2188 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2189 HCLGE_CFG_SPEED_S
, 2);
2191 case HCLGE_MAC_SPEED_40G
:
2192 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2193 HCLGE_CFG_SPEED_S
, 3);
2195 case HCLGE_MAC_SPEED_50G
:
2196 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2197 HCLGE_CFG_SPEED_S
, 4);
2199 case HCLGE_MAC_SPEED_100G
:
2200 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2201 HCLGE_CFG_SPEED_S
, 5);
2204 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2208 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2211 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2213 dev_err(&hdev
->pdev
->dev
,
2214 "mac speed/duplex config cmd failed %d.\n", ret
);
2218 hclge_check_speed_dup(hdev
, duplex
, speed
);
2223 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2226 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2227 struct hclge_dev
*hdev
= vport
->back
;
2229 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2232 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2235 struct hclge_query_an_speed_dup_cmd
*req
;
2236 struct hclge_desc desc
;
2240 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2242 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2243 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2245 dev_err(&hdev
->pdev
->dev
,
2246 "mac speed/autoneg/duplex query cmd failed %d\n",
2251 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2252 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2253 HCLGE_QUERY_SPEED_S
);
2255 ret
= hclge_parse_speed(speed_tmp
, speed
);
2257 dev_err(&hdev
->pdev
->dev
,
2258 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2265 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2267 struct hclge_config_auto_neg_cmd
*req
;
2268 struct hclge_desc desc
;
2272 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2274 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2275 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2276 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2278 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2280 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2288 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2290 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2291 struct hclge_dev
*hdev
= vport
->back
;
2293 return hclge_set_autoneg_en(hdev
, enable
);
2296 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2298 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2299 struct hclge_dev
*hdev
= vport
->back
;
2300 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2303 return phydev
->autoneg
;
2305 return hdev
->hw
.mac
.autoneg
;
2308 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2312 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2313 struct hclge_desc desc
;
2316 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2317 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2319 hnae_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2321 ether_addr_copy(req
->mac_mask
, mac_mask
);
2323 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2325 dev_err(&hdev
->pdev
->dev
,
2326 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2332 static int hclge_mac_init(struct hclge_dev
*hdev
)
2334 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2335 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2336 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2337 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2341 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2343 dev_err(&hdev
->pdev
->dev
,
2344 "Config mac speed dup fail ret=%d\n", ret
);
2350 /* Initialize the MTA table work mode */
2351 hdev
->accept_mta_mc
= true;
2352 hdev
->enable_mta
= true;
2353 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2355 ret
= hclge_set_mta_filter_mode(hdev
,
2356 hdev
->mta_mac_sel_type
,
2359 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2364 ret
= hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2366 dev_err(&hdev
->pdev
->dev
,
2367 "set mta filter mode fail ret=%d\n", ret
);
2371 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2373 dev_err(&hdev
->pdev
->dev
,
2374 "set default mac_vlan_mask fail ret=%d\n", ret
);
2383 ret
= hclge_set_mtu(handle
, mtu
);
2385 dev_err(&hdev
->pdev
->dev
,
2386 "set mtu failed ret=%d\n", ret
);
2393 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2395 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2396 schedule_work(&hdev
->mbx_service_task
);
2399 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2401 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2402 schedule_work(&hdev
->rst_service_task
);
2405 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2407 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2408 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2409 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2410 (void)schedule_work(&hdev
->service_task
);
2413 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2415 struct hclge_link_status_cmd
*req
;
2416 struct hclge_desc desc
;
2420 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2421 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2423 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2428 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2429 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2431 return !!link_status
;
2434 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2439 mac_state
= hclge_get_mac_link_status(hdev
);
2441 if (hdev
->hw
.mac
.phydev
) {
2442 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2443 link_stat
= mac_state
&
2444 hdev
->hw
.mac
.phydev
->link
;
2449 link_stat
= mac_state
;
2455 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2457 struct hnae3_client
*client
= hdev
->nic_client
;
2458 struct hnae3_handle
*handle
;
2464 state
= hclge_get_mac_phy_link(hdev
);
2465 if (state
!= hdev
->hw
.mac
.link
) {
2466 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2467 handle
= &hdev
->vport
[i
].nic
;
2468 client
->ops
->link_status_change(handle
, state
);
2470 hdev
->hw
.mac
.link
= state
;
2474 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2476 struct hclge_mac mac
= hdev
->hw
.mac
;
2481 /* get the speed and duplex as autoneg'result from mac cmd when phy
2484 if (mac
.phydev
|| !mac
.autoneg
)
2487 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2489 dev_err(&hdev
->pdev
->dev
,
2490 "mac autoneg/speed/duplex query failed %d\n", ret
);
2494 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2495 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2497 dev_err(&hdev
->pdev
->dev
,
2498 "mac speed/duplex config failed %d\n", ret
);
2506 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2508 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2509 struct hclge_dev
*hdev
= vport
->back
;
2511 return hclge_update_speed_duplex(hdev
);
2514 static int hclge_get_status(struct hnae3_handle
*handle
)
2516 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2517 struct hclge_dev
*hdev
= vport
->back
;
2519 hclge_update_link_status(hdev
);
2521 return hdev
->hw
.mac
.link
;
2524 static void hclge_service_timer(struct timer_list
*t
)
2526 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2528 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2529 hdev
->hw_stats
.stats_timer
++;
2530 hclge_task_schedule(hdev
);
2533 static void hclge_service_complete(struct hclge_dev
*hdev
)
2535 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2537 /* Flush memory before next watchdog */
2538 smp_mb__before_atomic();
2539 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2542 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2547 /* fetch the events from their corresponding regs */
2548 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2549 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2551 /* Assumption: If by any chance reset and mailbox events are reported
2552 * together then we will only process reset event in this go and will
2553 * defer the processing of the mailbox events. Since, we would have not
2554 * cleared RX CMDQ event this time we would receive again another
2555 * interrupt from H/W just for the mailbox.
2558 /* check for vector0 reset event sources */
2559 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2560 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2561 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2562 return HCLGE_VECTOR0_EVENT_RST
;
2565 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2566 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2567 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2568 return HCLGE_VECTOR0_EVENT_RST
;
2571 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2572 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2573 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2574 return HCLGE_VECTOR0_EVENT_RST
;
2577 /* check for vector0 mailbox(=CMDQ RX) event source */
2578 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2579 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2580 *clearval
= cmdq_src_reg
;
2581 return HCLGE_VECTOR0_EVENT_MBX
;
2584 return HCLGE_VECTOR0_EVENT_OTHER
;
2587 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2590 switch (event_type
) {
2591 case HCLGE_VECTOR0_EVENT_RST
:
2592 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2594 case HCLGE_VECTOR0_EVENT_MBX
:
2595 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2600 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2602 writel(enable
? 1 : 0, vector
->addr
);
2605 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2607 struct hclge_dev
*hdev
= data
;
2611 hclge_enable_vector(&hdev
->misc_vector
, false);
2612 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2614 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2615 switch (event_cause
) {
2616 case HCLGE_VECTOR0_EVENT_RST
:
2617 hclge_reset_task_schedule(hdev
);
2619 case HCLGE_VECTOR0_EVENT_MBX
:
2620 /* If we are here then,
2621 * 1. Either we are not handling any mbx task and we are not
2624 * 2. We could be handling a mbx task but nothing more is
2626 * In both cases, we should schedule mbx task as there are more
2627 * mbx messages reported by this interrupt.
2629 hclge_mbx_task_schedule(hdev
);
2632 dev_dbg(&hdev
->pdev
->dev
,
2633 "received unknown or unhandled event of vector0\n");
2637 /* we should clear the source of interrupt */
2638 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2639 hclge_enable_vector(&hdev
->misc_vector
, true);
2644 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2646 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2647 hdev
->num_msi_left
+= 1;
2648 hdev
->num_msi_used
-= 1;
2651 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2653 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2655 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2657 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2658 hdev
->vector_status
[0] = 0;
2660 hdev
->num_msi_left
-= 1;
2661 hdev
->num_msi_used
+= 1;
2664 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2668 hclge_get_misc_vector(hdev
);
2670 /* this would be explicitly freed in the end */
2671 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2672 0, "hclge_misc", hdev
);
2674 hclge_free_vector(hdev
, 0);
2675 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2676 hdev
->misc_vector
.vector_irq
);
2682 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2684 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2685 hclge_free_vector(hdev
, 0);
2688 static int hclge_notify_client(struct hclge_dev
*hdev
,
2689 enum hnae3_reset_notify_type type
)
2691 struct hnae3_client
*client
= hdev
->nic_client
;
2694 if (!client
->ops
->reset_notify
)
2697 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2698 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2701 ret
= client
->ops
->reset_notify(handle
, type
);
2709 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2711 #define HCLGE_RESET_WATI_MS 100
2712 #define HCLGE_RESET_WAIT_CNT 5
2713 u32 val
, reg
, reg_bit
;
2716 switch (hdev
->reset_type
) {
2717 case HNAE3_GLOBAL_RESET
:
2718 reg
= HCLGE_GLOBAL_RESET_REG
;
2719 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2721 case HNAE3_CORE_RESET
:
2722 reg
= HCLGE_GLOBAL_RESET_REG
;
2723 reg_bit
= HCLGE_CORE_RESET_BIT
;
2725 case HNAE3_FUNC_RESET
:
2726 reg
= HCLGE_FUN_RST_ING
;
2727 reg_bit
= HCLGE_FUN_RST_ING_B
;
2730 dev_err(&hdev
->pdev
->dev
,
2731 "Wait for unsupported reset type: %d\n",
2736 val
= hclge_read_dev(&hdev
->hw
, reg
);
2737 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2738 msleep(HCLGE_RESET_WATI_MS
);
2739 val
= hclge_read_dev(&hdev
->hw
, reg
);
2743 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2744 dev_warn(&hdev
->pdev
->dev
,
2745 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2752 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2754 struct hclge_desc desc
;
2755 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2758 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2759 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_MAC_B
, 0);
2760 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2761 req
->fun_reset_vfid
= func_id
;
2763 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2765 dev_err(&hdev
->pdev
->dev
,
2766 "send function reset cmd fail, status =%d\n", ret
);
2771 static void hclge_do_reset(struct hclge_dev
*hdev
)
2773 struct pci_dev
*pdev
= hdev
->pdev
;
2776 switch (hdev
->reset_type
) {
2777 case HNAE3_GLOBAL_RESET
:
2778 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2779 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2780 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2781 dev_info(&pdev
->dev
, "Global Reset requested\n");
2783 case HNAE3_CORE_RESET
:
2784 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2785 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2786 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2787 dev_info(&pdev
->dev
, "Core Reset requested\n");
2789 case HNAE3_FUNC_RESET
:
2790 dev_info(&pdev
->dev
, "PF Reset requested\n");
2791 hclge_func_reset_cmd(hdev
, 0);
2792 /* schedule again to check later */
2793 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2794 hclge_reset_task_schedule(hdev
);
2797 dev_warn(&pdev
->dev
,
2798 "Unsupported reset type: %d\n", hdev
->reset_type
);
2803 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2804 unsigned long *addr
)
2806 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2808 /* return the highest priority reset level amongst all */
2809 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2810 rst_level
= HNAE3_GLOBAL_RESET
;
2811 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2812 rst_level
= HNAE3_CORE_RESET
;
2813 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2814 rst_level
= HNAE3_IMP_RESET
;
2815 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2816 rst_level
= HNAE3_FUNC_RESET
;
2818 /* now, clear all other resets */
2819 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2820 clear_bit(HNAE3_CORE_RESET
, addr
);
2821 clear_bit(HNAE3_IMP_RESET
, addr
);
2822 clear_bit(HNAE3_FUNC_RESET
, addr
);
2827 static void hclge_reset(struct hclge_dev
*hdev
)
2829 /* perform reset of the stack & ae device for a client */
2831 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2833 if (!hclge_reset_wait(hdev
)) {
2835 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2836 hclge_reset_ae_dev(hdev
->ae_dev
);
2837 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2840 /* schedule again to check pending resets later */
2841 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2842 hclge_reset_task_schedule(hdev
);
2845 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2848 static void hclge_reset_event(struct hnae3_handle
*handle
)
2850 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2851 struct hclge_dev
*hdev
= vport
->back
;
2853 /* check if this is a new reset request and we are not here just because
2854 * last reset attempt did not succeed and watchdog hit us again. We will
2855 * know this if last reset request did not occur very recently (watchdog
2856 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2857 * In case of new request we reset the "reset level" to PF reset.
2859 if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2860 handle
->reset_level
= HNAE3_FUNC_RESET
;
2862 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2863 handle
->reset_level
);
2865 /* request reset & schedule reset task */
2866 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2867 hclge_reset_task_schedule(hdev
);
2869 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2870 handle
->reset_level
++;
2872 handle
->last_reset_time
= jiffies
;
2875 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2877 /* check if there is any ongoing reset in the hardware. This status can
2878 * be checked from reset_pending. If there is then, we need to wait for
2879 * hardware to complete reset.
2880 * a. If we are able to figure out in reasonable time that hardware
2881 * has fully resetted then, we can proceed with driver, client
2883 * b. else, we can come back later to check this status so re-sched
2886 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2887 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2890 /* check if we got any *new* reset requests to be honored */
2891 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2892 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2893 hclge_do_reset(hdev
);
2895 hdev
->reset_type
= HNAE3_NONE_RESET
;
2898 static void hclge_reset_service_task(struct work_struct
*work
)
2900 struct hclge_dev
*hdev
=
2901 container_of(work
, struct hclge_dev
, rst_service_task
);
2903 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2906 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2908 hclge_reset_subtask(hdev
);
2910 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2913 static void hclge_mailbox_service_task(struct work_struct
*work
)
2915 struct hclge_dev
*hdev
=
2916 container_of(work
, struct hclge_dev
, mbx_service_task
);
2918 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2921 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2923 hclge_mbx_handler(hdev
);
2925 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2928 static void hclge_service_task(struct work_struct
*work
)
2930 struct hclge_dev
*hdev
=
2931 container_of(work
, struct hclge_dev
, service_task
);
2933 /* The total rx/tx packets statstics are wanted to be updated
2934 * per second. Both hclge_update_stats_for_all() and
2935 * hclge_mac_get_traffic_stats() can do it.
2937 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2938 hclge_update_stats_for_all(hdev
);
2939 hdev
->hw_stats
.stats_timer
= 0;
2941 hclge_mac_get_traffic_stats(hdev
);
2944 hclge_update_speed_duplex(hdev
);
2945 hclge_update_link_status(hdev
);
2946 hclge_update_led_status(hdev
);
2947 hclge_service_complete(hdev
);
2950 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2952 /* If our VFs are assigned we cannot shut down SR-IOV
2953 * without causing issues, so just leave the hardware
2954 * available but disabled
2956 if (pci_vfs_assigned(hdev
->pdev
)) {
2957 dev_warn(&hdev
->pdev
->dev
,
2958 "disabling driver while VFs are assigned\n");
2962 pci_disable_sriov(hdev
->pdev
);
2965 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2967 /* VF handle has no client */
2968 if (!handle
->client
)
2969 return container_of(handle
, struct hclge_vport
, nic
);
2970 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2971 return container_of(handle
, struct hclge_vport
, roce
);
2973 return container_of(handle
, struct hclge_vport
, nic
);
2976 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2977 struct hnae3_vector_info
*vector_info
)
2979 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2980 struct hnae3_vector_info
*vector
= vector_info
;
2981 struct hclge_dev
*hdev
= vport
->back
;
2985 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2987 for (j
= 0; j
< vector_num
; j
++) {
2988 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2989 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2990 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2991 vector
->io_addr
= hdev
->hw
.io_base
+
2992 HCLGE_VECTOR_REG_BASE
+
2993 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2995 HCLGE_VECTOR_VF_OFFSET
;
2996 hdev
->vector_status
[i
] = vport
->vport_id
;
2997 hdev
->vector_irq
[i
] = vector
->vector
;
3006 hdev
->num_msi_left
-= alloc
;
3007 hdev
->num_msi_used
+= alloc
;
3012 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
3016 for (i
= 0; i
< hdev
->num_msi
; i
++)
3017 if (vector
== hdev
->vector_irq
[i
])
3023 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
3025 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3026 struct hclge_dev
*hdev
= vport
->back
;
3029 vector_id
= hclge_get_vector_index(hdev
, vector
);
3030 if (vector_id
< 0) {
3031 dev_err(&hdev
->pdev
->dev
,
3032 "Get vector index fail. vector_id =%d\n", vector_id
);
3036 hclge_free_vector(hdev
, vector_id
);
3041 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
3043 return HCLGE_RSS_KEY_SIZE
;
3046 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
3048 return HCLGE_RSS_IND_TBL_SIZE
;
3051 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3052 const u8 hfunc
, const u8
*key
)
3054 struct hclge_rss_config_cmd
*req
;
3055 struct hclge_desc desc
;
3060 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3062 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3063 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3066 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3067 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3069 if (key_offset
== 2)
3071 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3073 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3075 memcpy(req
->hash_key
,
3076 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3078 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3080 dev_err(&hdev
->pdev
->dev
,
3081 "Configure RSS config fail, status = %d\n",
3089 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3091 struct hclge_rss_indirection_table_cmd
*req
;
3092 struct hclge_desc desc
;
3096 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3098 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3099 hclge_cmd_setup_basic_desc
3100 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3102 req
->start_table_index
=
3103 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3104 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3106 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3107 req
->rss_result
[j
] =
3108 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3110 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3112 dev_err(&hdev
->pdev
->dev
,
3113 "Configure rss indir table fail,status = %d\n",
3121 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3122 u16
*tc_size
, u16
*tc_offset
)
3124 struct hclge_rss_tc_mode_cmd
*req
;
3125 struct hclge_desc desc
;
3129 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3130 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3132 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3135 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3136 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3137 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3138 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3139 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3141 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3144 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3146 dev_err(&hdev
->pdev
->dev
,
3147 "Configure rss tc mode fail, status = %d\n", ret
);
3154 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3156 struct hclge_rss_input_tuple_cmd
*req
;
3157 struct hclge_desc desc
;
3160 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3162 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3164 /* Get the tuple cfg from pf */
3165 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3166 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3167 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3168 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3169 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3170 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3171 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3172 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3173 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3175 dev_err(&hdev
->pdev
->dev
,
3176 "Configure rss input fail, status = %d\n", ret
);
3183 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3186 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3189 /* Get hash algorithm */
3191 *hfunc
= vport
->rss_algo
;
3193 /* Get the RSS Key required by the user */
3195 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3197 /* Get indirect table */
3199 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3200 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3205 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3206 const u8
*key
, const u8 hfunc
)
3208 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3209 struct hclge_dev
*hdev
= vport
->back
;
3213 /* Set the RSS Hash Key if specififed by the user */
3216 if (hfunc
== ETH_RSS_HASH_TOP
||
3217 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3218 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3221 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3225 /* Update the shadow RSS key with user specified qids */
3226 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3227 vport
->rss_algo
= hash_algo
;
3230 /* Update the shadow RSS table with user specified qids */
3231 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3232 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3234 /* Update the hardware */
3235 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3238 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3240 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3242 if (nfc
->data
& RXH_L4_B_2_3
)
3243 hash_sets
|= HCLGE_D_PORT_BIT
;
3245 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3247 if (nfc
->data
& RXH_IP_SRC
)
3248 hash_sets
|= HCLGE_S_IP_BIT
;
3250 hash_sets
&= ~HCLGE_S_IP_BIT
;
3252 if (nfc
->data
& RXH_IP_DST
)
3253 hash_sets
|= HCLGE_D_IP_BIT
;
3255 hash_sets
&= ~HCLGE_D_IP_BIT
;
3257 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3258 hash_sets
|= HCLGE_V_TAG_BIT
;
3263 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3264 struct ethtool_rxnfc
*nfc
)
3266 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3267 struct hclge_dev
*hdev
= vport
->back
;
3268 struct hclge_rss_input_tuple_cmd
*req
;
3269 struct hclge_desc desc
;
3273 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3274 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3277 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3278 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3280 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3281 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3282 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3283 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3284 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3285 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3286 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3287 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3289 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3290 switch (nfc
->flow_type
) {
3292 req
->ipv4_tcp_en
= tuple_sets
;
3295 req
->ipv6_tcp_en
= tuple_sets
;
3298 req
->ipv4_udp_en
= tuple_sets
;
3301 req
->ipv6_udp_en
= tuple_sets
;
3304 req
->ipv4_sctp_en
= tuple_sets
;
3307 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3308 (nfc
->data
& RXH_L4_B_2_3
))
3311 req
->ipv6_sctp_en
= tuple_sets
;
3314 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3317 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3323 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3325 dev_err(&hdev
->pdev
->dev
,
3326 "Set rss tuple fail, status = %d\n", ret
);
3330 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3331 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3332 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3333 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3334 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3335 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3336 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3337 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3341 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3342 struct ethtool_rxnfc
*nfc
)
3344 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3349 switch (nfc
->flow_type
) {
3351 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3354 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3357 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3360 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3363 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3366 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3370 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3379 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3380 nfc
->data
|= RXH_L4_B_2_3
;
3381 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3382 nfc
->data
|= RXH_L4_B_0_1
;
3383 if (tuple_sets
& HCLGE_D_IP_BIT
)
3384 nfc
->data
|= RXH_IP_DST
;
3385 if (tuple_sets
& HCLGE_S_IP_BIT
)
3386 nfc
->data
|= RXH_IP_SRC
;
3391 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3393 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3394 struct hclge_dev
*hdev
= vport
->back
;
3396 return hdev
->rss_size_max
;
3399 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3401 struct hclge_vport
*vport
= hdev
->vport
;
3402 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3403 u16 rss_size
= vport
[0].alloc_rss_size
;
3404 u8
*key
= vport
[0].rss_hash_key
;
3405 u8 hfunc
= vport
[0].rss_algo
;
3406 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3407 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3408 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3412 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3416 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3420 ret
= hclge_set_rss_input_tuple(hdev
);
3424 /* Each TC have the same queue size, and tc_size set to hardware is
3425 * the log2 of roundup power of two of rss_size, the acutal queue
3426 * size is limited by indirection table.
3428 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3429 dev_err(&hdev
->pdev
->dev
,
3430 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3435 roundup_size
= roundup_pow_of_two(rss_size
);
3436 roundup_size
= ilog2(roundup_size
);
3438 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3441 if (!(hdev
->hw_tc_map
& BIT(i
)))
3445 tc_size
[i
] = roundup_size
;
3446 tc_offset
[i
] = rss_size
* i
;
3449 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3452 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3454 struct hclge_vport
*vport
= hdev
->vport
;
3457 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3458 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3459 vport
[j
].rss_indirection_tbl
[i
] =
3460 i
% vport
[j
].alloc_rss_size
;
3464 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3466 struct hclge_vport
*vport
= hdev
->vport
;
3469 netdev_rss_key_fill(vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3471 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3472 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3473 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3474 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3475 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3476 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3477 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3478 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3479 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3480 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3481 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3482 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3483 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3484 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3485 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3486 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3487 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3489 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3492 hclge_rss_indir_init_cfg(hdev
);
3495 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3496 int vector_id
, bool en
,
3497 struct hnae3_ring_chain_node
*ring_chain
)
3499 struct hclge_dev
*hdev
= vport
->back
;
3500 struct hnae3_ring_chain_node
*node
;
3501 struct hclge_desc desc
;
3502 struct hclge_ctrl_vector_chain_cmd
*req
3503 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3504 enum hclge_cmd_status status
;
3505 enum hclge_opcode_type op
;
3506 u16 tqp_type_and_id
;
3509 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3510 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3511 req
->int_vector_id
= vector_id
;
3514 for (node
= ring_chain
; node
; node
= node
->next
) {
3515 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3516 hnae_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3518 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3519 hnae_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3520 HCLGE_TQP_ID_S
, node
->tqp_index
);
3521 hnae_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3523 hnae_get_field(node
->int_gl_idx
,
3524 HNAE3_RING_GL_IDX_M
,
3525 HNAE3_RING_GL_IDX_S
));
3526 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3527 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3528 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3529 req
->vfid
= vport
->vport_id
;
3531 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3533 dev_err(&hdev
->pdev
->dev
,
3534 "Map TQP fail, status is %d.\n",
3540 hclge_cmd_setup_basic_desc(&desc
,
3543 req
->int_vector_id
= vector_id
;
3548 req
->int_cause_num
= i
;
3549 req
->vfid
= vport
->vport_id
;
3550 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3552 dev_err(&hdev
->pdev
->dev
,
3553 "Map TQP fail, status is %d.\n", status
);
3561 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3563 struct hnae3_ring_chain_node
*ring_chain
)
3565 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3566 struct hclge_dev
*hdev
= vport
->back
;
3569 vector_id
= hclge_get_vector_index(hdev
, vector
);
3570 if (vector_id
< 0) {
3571 dev_err(&hdev
->pdev
->dev
,
3572 "Get vector index fail. vector_id =%d\n", vector_id
);
3576 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3579 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3581 struct hnae3_ring_chain_node
*ring_chain
)
3583 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3584 struct hclge_dev
*hdev
= vport
->back
;
3587 vector_id
= hclge_get_vector_index(hdev
, vector
);
3588 if (vector_id
< 0) {
3589 dev_err(&handle
->pdev
->dev
,
3590 "Get vector index fail. ret =%d\n", vector_id
);
3594 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3596 dev_err(&handle
->pdev
->dev
,
3597 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3604 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3605 struct hclge_promisc_param
*param
)
3607 struct hclge_promisc_cfg_cmd
*req
;
3608 struct hclge_desc desc
;
3611 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3613 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3614 req
->vf_id
= param
->vf_id
;
3615 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
3617 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3619 dev_err(&hdev
->pdev
->dev
,
3620 "Set promisc mode fail, status is %d.\n", ret
);
3626 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3627 bool en_mc
, bool en_bc
, int vport_id
)
3632 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3634 param
->enable
= HCLGE_PROMISC_EN_UC
;
3636 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3638 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3639 param
->vf_id
= vport_id
;
3642 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
3644 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3645 struct hclge_dev
*hdev
= vport
->back
;
3646 struct hclge_promisc_param param
;
3648 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
3649 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3652 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3654 struct hclge_desc desc
;
3655 struct hclge_config_mac_mode_cmd
*req
=
3656 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3660 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3661 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3662 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3663 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3664 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3665 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3666 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3667 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3668 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3669 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3670 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3671 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3672 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3673 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3674 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3675 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3677 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3679 dev_err(&hdev
->pdev
->dev
,
3680 "mac enable fail, ret =%d.\n", ret
);
3683 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3684 enum hnae3_loop loop_mode
, bool en
)
3686 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3687 struct hclge_config_mac_mode_cmd
*req
;
3688 struct hclge_dev
*hdev
= vport
->back
;
3689 struct hclge_desc desc
;
3693 switch (loop_mode
) {
3694 case HNAE3_MAC_INTER_LOOP_MAC
:
3695 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3696 /* 1 Read out the MAC mode config at first */
3697 hclge_cmd_setup_basic_desc(&desc
,
3698 HCLGE_OPC_CONFIG_MAC_MODE
,
3700 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3702 dev_err(&hdev
->pdev
->dev
,
3703 "mac loopback get fail, ret =%d.\n",
3708 /* 2 Then setup the loopback flag */
3709 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3711 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 1);
3713 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3715 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3717 /* 3 Config mac work mode with loopback flag
3718 * and its original configure parameters
3720 hclge_cmd_reuse_desc(&desc
, false);
3721 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3723 dev_err(&hdev
->pdev
->dev
,
3724 "mac loopback set fail, ret =%d.\n", ret
);
3728 dev_err(&hdev
->pdev
->dev
,
3729 "loop_mode %d is not supported\n", loop_mode
);
3736 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3737 int stream_id
, bool enable
)
3739 struct hclge_desc desc
;
3740 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3741 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3744 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3745 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3746 req
->stream_id
= cpu_to_le16(stream_id
);
3747 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3749 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3751 dev_err(&hdev
->pdev
->dev
,
3752 "Tqp enable fail, status =%d.\n", ret
);
3756 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3758 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3759 struct hnae3_queue
*queue
;
3760 struct hclge_tqp
*tqp
;
3763 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3764 queue
= handle
->kinfo
.tqp
[i
];
3765 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3766 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3770 static int hclge_ae_start(struct hnae3_handle
*handle
)
3772 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3773 struct hclge_dev
*hdev
= vport
->back
;
3776 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3777 hclge_tqp_enable(hdev
, i
, 0, true);
3780 hclge_cfg_mac_mode(hdev
, true);
3781 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3782 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3784 ret
= hclge_mac_start_phy(hdev
);
3788 /* reset tqp stats */
3789 hclge_reset_tqp_stats(handle
);
3794 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3796 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3797 struct hclge_dev
*hdev
= vport
->back
;
3800 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3801 hclge_tqp_enable(hdev
, i
, 0, false);
3804 hclge_cfg_mac_mode(hdev
, false);
3806 hclge_mac_stop_phy(hdev
);
3808 /* reset tqp stats */
3809 hclge_reset_tqp_stats(handle
);
3810 del_timer_sync(&hdev
->service_timer
);
3811 cancel_work_sync(&hdev
->service_task
);
3812 hclge_update_link_status(hdev
);
3815 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3816 u16 cmdq_resp
, u8 resp_code
,
3817 enum hclge_mac_vlan_tbl_opcode op
)
3819 struct hclge_dev
*hdev
= vport
->back
;
3820 int return_status
= -EIO
;
3823 dev_err(&hdev
->pdev
->dev
,
3824 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3829 if (op
== HCLGE_MAC_VLAN_ADD
) {
3830 if ((!resp_code
) || (resp_code
== 1)) {
3832 } else if (resp_code
== 2) {
3833 return_status
= -ENOSPC
;
3834 dev_err(&hdev
->pdev
->dev
,
3835 "add mac addr failed for uc_overflow.\n");
3836 } else if (resp_code
== 3) {
3837 return_status
= -ENOSPC
;
3838 dev_err(&hdev
->pdev
->dev
,
3839 "add mac addr failed for mc_overflow.\n");
3841 dev_err(&hdev
->pdev
->dev
,
3842 "add mac addr failed for undefined, code=%d.\n",
3845 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3848 } else if (resp_code
== 1) {
3849 return_status
= -ENOENT
;
3850 dev_dbg(&hdev
->pdev
->dev
,
3851 "remove mac addr failed for miss.\n");
3853 dev_err(&hdev
->pdev
->dev
,
3854 "remove mac addr failed for undefined, code=%d.\n",
3857 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3860 } else if (resp_code
== 1) {
3861 return_status
= -ENOENT
;
3862 dev_dbg(&hdev
->pdev
->dev
,
3863 "lookup mac addr failed for miss.\n");
3865 dev_err(&hdev
->pdev
->dev
,
3866 "lookup mac addr failed for undefined, code=%d.\n",
3870 return_status
= -EINVAL
;
3871 dev_err(&hdev
->pdev
->dev
,
3872 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3876 return return_status
;
3879 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3884 if (vfid
> 255 || vfid
< 0)
3887 if (vfid
>= 0 && vfid
<= 191) {
3888 word_num
= vfid
/ 32;
3889 bit_num
= vfid
% 32;
3891 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3893 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3895 word_num
= (vfid
- 192) / 32;
3896 bit_num
= vfid
% 32;
3898 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3900 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3906 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3908 #define HCLGE_DESC_NUMBER 3
3909 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3912 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3913 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3914 if (desc
[i
].data
[j
])
3920 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3923 const unsigned char *mac_addr
= addr
;
3924 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3925 (mac_addr
[0]) | (mac_addr
[1] << 8);
3926 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3928 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3929 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3932 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3935 u16 high_val
= addr
[1] | (addr
[0] << 8);
3936 struct hclge_dev
*hdev
= vport
->back
;
3937 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3938 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3943 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3944 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3947 struct hclge_mta_filter_mode_cmd
*req
;
3948 struct hclge_desc desc
;
3951 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3952 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3954 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3956 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3957 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3959 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3961 dev_err(&hdev
->pdev
->dev
,
3962 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3970 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3974 struct hclge_cfg_func_mta_filter_cmd
*req
;
3975 struct hclge_desc desc
;
3978 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3979 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3981 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3983 req
->function_id
= func_id
;
3985 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3987 dev_err(&hdev
->pdev
->dev
,
3988 "Config func_id enable failed for cmd_send, ret =%d.\n",
3996 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
4000 struct hclge_dev
*hdev
= vport
->back
;
4001 struct hclge_cfg_func_mta_item_cmd
*req
;
4002 struct hclge_desc desc
;
4006 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
4007 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
4008 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
4010 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
4011 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
4012 req
->item_idx
= cpu_to_le16(item_idx
);
4014 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4016 dev_err(&hdev
->pdev
->dev
,
4017 "Config mta table item failed for cmd_send, ret =%d.\n",
4025 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4026 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4028 struct hclge_dev
*hdev
= vport
->back
;
4029 struct hclge_desc desc
;
4034 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4036 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4038 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4040 dev_err(&hdev
->pdev
->dev
,
4041 "del mac addr failed for cmd_send, ret =%d.\n",
4045 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4046 retval
= le16_to_cpu(desc
.retval
);
4048 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4049 HCLGE_MAC_VLAN_REMOVE
);
4052 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4053 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4054 struct hclge_desc
*desc
,
4057 struct hclge_dev
*hdev
= vport
->back
;
4062 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4064 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4065 memcpy(desc
[0].data
,
4067 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4068 hclge_cmd_setup_basic_desc(&desc
[1],
4069 HCLGE_OPC_MAC_VLAN_ADD
,
4071 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4072 hclge_cmd_setup_basic_desc(&desc
[2],
4073 HCLGE_OPC_MAC_VLAN_ADD
,
4075 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4077 memcpy(desc
[0].data
,
4079 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4080 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4083 dev_err(&hdev
->pdev
->dev
,
4084 "lookup mac addr failed for cmd_send, ret =%d.\n",
4088 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4089 retval
= le16_to_cpu(desc
[0].retval
);
4091 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4092 HCLGE_MAC_VLAN_LKUP
);
4095 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4096 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4097 struct hclge_desc
*mc_desc
)
4099 struct hclge_dev
*hdev
= vport
->back
;
4106 struct hclge_desc desc
;
4108 hclge_cmd_setup_basic_desc(&desc
,
4109 HCLGE_OPC_MAC_VLAN_ADD
,
4111 memcpy(desc
.data
, req
,
4112 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4113 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4114 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4115 retval
= le16_to_cpu(desc
.retval
);
4117 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4119 HCLGE_MAC_VLAN_ADD
);
4121 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4122 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4123 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4124 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4125 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4126 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4127 memcpy(mc_desc
[0].data
, req
,
4128 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4129 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4130 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4131 retval
= le16_to_cpu(mc_desc
[0].retval
);
4133 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4135 HCLGE_MAC_VLAN_ADD
);
4139 dev_err(&hdev
->pdev
->dev
,
4140 "add mac addr failed for cmd_send, ret =%d.\n",
4148 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4149 const unsigned char *addr
)
4151 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4153 return hclge_add_uc_addr_common(vport
, addr
);
4156 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4157 const unsigned char *addr
)
4159 struct hclge_dev
*hdev
= vport
->back
;
4160 struct hclge_mac_vlan_tbl_entry_cmd req
;
4161 struct hclge_desc desc
;
4162 u16 egress_port
= 0;
4165 /* mac addr check */
4166 if (is_zero_ether_addr(addr
) ||
4167 is_broadcast_ether_addr(addr
) ||
4168 is_multicast_ether_addr(addr
)) {
4169 dev_err(&hdev
->pdev
->dev
,
4170 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4172 is_zero_ether_addr(addr
),
4173 is_broadcast_ether_addr(addr
),
4174 is_multicast_ether_addr(addr
));
4178 memset(&req
, 0, sizeof(req
));
4179 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4180 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4181 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
4182 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4184 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_SW_EN_B
, 0);
4185 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_TYPE_B
, 0);
4186 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4187 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4188 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_PFID_M
,
4189 HCLGE_MAC_EPORT_PFID_S
, 0);
4191 req
.egress_port
= cpu_to_le16(egress_port
);
4193 hclge_prepare_mac_addr(&req
, addr
);
4195 /* Lookup the mac address in the mac_vlan table, and add
4196 * it if the entry is inexistent. Repeated unicast entry
4197 * is not allowed in the mac vlan table.
4199 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4201 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4203 /* check if we just hit the duplicate */
4207 dev_err(&hdev
->pdev
->dev
,
4208 "PF failed to add unicast entry(%pM) in the MAC table\n",
4214 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4215 const unsigned char *addr
)
4217 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4219 return hclge_rm_uc_addr_common(vport
, addr
);
4222 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4223 const unsigned char *addr
)
4225 struct hclge_dev
*hdev
= vport
->back
;
4226 struct hclge_mac_vlan_tbl_entry_cmd req
;
4229 /* mac addr check */
4230 if (is_zero_ether_addr(addr
) ||
4231 is_broadcast_ether_addr(addr
) ||
4232 is_multicast_ether_addr(addr
)) {
4233 dev_dbg(&hdev
->pdev
->dev
,
4234 "Remove mac err! invalid mac:%pM.\n",
4239 memset(&req
, 0, sizeof(req
));
4240 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4241 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4242 hclge_prepare_mac_addr(&req
, addr
);
4243 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4248 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4249 const unsigned char *addr
)
4251 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4253 return hclge_add_mc_addr_common(vport
, addr
);
4256 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4257 const unsigned char *addr
)
4259 struct hclge_dev
*hdev
= vport
->back
;
4260 struct hclge_mac_vlan_tbl_entry_cmd req
;
4261 struct hclge_desc desc
[3];
4265 /* mac addr check */
4266 if (!is_multicast_ether_addr(addr
)) {
4267 dev_err(&hdev
->pdev
->dev
,
4268 "Add mc mac err! invalid mac:%pM.\n",
4272 memset(&req
, 0, sizeof(req
));
4273 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4274 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4275 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4276 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4277 hclge_prepare_mac_addr(&req
, addr
);
4278 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4280 /* This mac addr exist, update VFID for it */
4281 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4282 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4284 /* This mac addr do not exist, add new entry for it */
4285 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4286 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4287 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4288 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4289 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4292 /* Set MTA table for this MAC address */
4293 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4294 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4299 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4300 const unsigned char *addr
)
4302 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4304 return hclge_rm_mc_addr_common(vport
, addr
);
4307 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4308 const unsigned char *addr
)
4310 struct hclge_dev
*hdev
= vport
->back
;
4311 struct hclge_mac_vlan_tbl_entry_cmd req
;
4312 enum hclge_cmd_status status
;
4313 struct hclge_desc desc
[3];
4316 /* mac addr check */
4317 if (!is_multicast_ether_addr(addr
)) {
4318 dev_dbg(&hdev
->pdev
->dev
,
4319 "Remove mc mac err! invalid mac:%pM.\n",
4324 memset(&req
, 0, sizeof(req
));
4325 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4326 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4327 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4328 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4329 hclge_prepare_mac_addr(&req
, addr
);
4330 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4332 /* This mac addr exist, remove this handle's VFID for it */
4333 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4335 if (hclge_is_all_function_id_zero(desc
))
4336 /* All the vfid is zero, so need to delete this entry */
4337 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4339 /* Not all the vfid is zero, update the vfid */
4340 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4343 /* This mac addr do not exist, can't delete it */
4344 dev_err(&hdev
->pdev
->dev
,
4345 "Rm multicast mac addr failed, ret = %d.\n",
4350 /* Set MTB table for this MAC address */
4351 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4352 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
4357 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4358 u16 cmdq_resp
, u8 resp_code
)
4360 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4361 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4362 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4363 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4368 dev_err(&hdev
->pdev
->dev
,
4369 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4374 switch (resp_code
) {
4375 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4376 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4379 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4380 dev_err(&hdev
->pdev
->dev
,
4381 "add mac ethertype failed for manager table overflow.\n");
4382 return_status
= -EIO
;
4384 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4385 dev_err(&hdev
->pdev
->dev
,
4386 "add mac ethertype failed for key conflict.\n");
4387 return_status
= -EIO
;
4390 dev_err(&hdev
->pdev
->dev
,
4391 "add mac ethertype failed for undefined, code=%d.\n",
4393 return_status
= -EIO
;
4396 return return_status
;
4399 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4400 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4402 struct hclge_desc desc
;
4407 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4408 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4410 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4412 dev_err(&hdev
->pdev
->dev
,
4413 "add mac ethertype failed for cmd_send, ret =%d.\n",
4418 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4419 retval
= le16_to_cpu(desc
.retval
);
4421 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4424 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4429 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4430 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4432 dev_err(&hdev
->pdev
->dev
,
4433 "add mac ethertype failed, ret =%d.\n",
4442 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4444 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4445 struct hclge_dev
*hdev
= vport
->back
;
4447 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4450 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4453 const unsigned char *new_addr
= (const unsigned char *)p
;
4454 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4455 struct hclge_dev
*hdev
= vport
->back
;
4458 /* mac addr check */
4459 if (is_zero_ether_addr(new_addr
) ||
4460 is_broadcast_ether_addr(new_addr
) ||
4461 is_multicast_ether_addr(new_addr
)) {
4462 dev_err(&hdev
->pdev
->dev
,
4463 "Change uc mac err! invalid mac:%p.\n",
4468 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4469 dev_warn(&hdev
->pdev
->dev
,
4470 "remove old uc mac address fail.\n");
4472 ret
= hclge_add_uc_addr(handle
, new_addr
);
4474 dev_err(&hdev
->pdev
->dev
,
4475 "add uc mac address fail, ret =%d.\n",
4479 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4480 dev_err(&hdev
->pdev
->dev
,
4481 "restore uc mac address fail.\n");
4486 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4488 dev_err(&hdev
->pdev
->dev
,
4489 "configure mac pause address fail, ret =%d.\n",
4494 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4499 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4502 struct hclge_vlan_filter_ctrl_cmd
*req
;
4503 struct hclge_desc desc
;
4506 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4508 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4509 req
->vlan_type
= vlan_type
;
4510 req
->vlan_fe
= filter_en
;
4512 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4514 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4522 #define HCLGE_FILTER_TYPE_VF 0
4523 #define HCLGE_FILTER_TYPE_PORT 1
4525 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4527 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4528 struct hclge_dev
*hdev
= vport
->back
;
4530 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4533 int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4534 bool is_kill
, u16 vlan
, u8 qos
, __be16 proto
)
4536 #define HCLGE_MAX_VF_BYTES 16
4537 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4538 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4539 struct hclge_desc desc
[2];
4544 hclge_cmd_setup_basic_desc(&desc
[0],
4545 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4546 hclge_cmd_setup_basic_desc(&desc
[1],
4547 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4549 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4551 vf_byte_off
= vfid
/ 8;
4552 vf_byte_val
= 1 << (vfid
% 8);
4554 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4555 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4557 req0
->vlan_id
= cpu_to_le16(vlan
);
4558 req0
->vlan_cfg
= is_kill
;
4560 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4561 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4563 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4565 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4567 dev_err(&hdev
->pdev
->dev
,
4568 "Send vf vlan command fail, ret =%d.\n",
4574 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4577 dev_err(&hdev
->pdev
->dev
,
4578 "Add vf vlan filter fail, ret =%d.\n",
4581 if (!req0
->resp_code
)
4584 dev_err(&hdev
->pdev
->dev
,
4585 "Kill vf vlan filter fail, ret =%d.\n",
4592 static int hclge_set_port_vlan_filter(struct hnae3_handle
*handle
,
4593 __be16 proto
, u16 vlan_id
,
4596 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4597 struct hclge_dev
*hdev
= vport
->back
;
4598 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4599 struct hclge_desc desc
;
4600 u8 vlan_offset_byte_val
;
4601 u8 vlan_offset_byte
;
4605 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4607 vlan_offset_160
= vlan_id
/ 160;
4608 vlan_offset_byte
= (vlan_id
% 160) / 8;
4609 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4611 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4612 req
->vlan_offset
= vlan_offset_160
;
4613 req
->vlan_cfg
= is_kill
;
4614 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4616 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4618 dev_err(&hdev
->pdev
->dev
,
4619 "port vlan command, send fail, ret =%d.\n",
4624 ret
= hclge_set_vf_vlan_common(hdev
, 0, is_kill
, vlan_id
, 0, proto
);
4626 dev_err(&hdev
->pdev
->dev
,
4627 "Set pf vlan filter config fail, ret =%d.\n",
4635 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4636 u16 vlan
, u8 qos
, __be16 proto
)
4638 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4639 struct hclge_dev
*hdev
= vport
->back
;
4641 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4643 if (proto
!= htons(ETH_P_8021Q
))
4644 return -EPROTONOSUPPORT
;
4646 return hclge_set_vf_vlan_common(hdev
, vfid
, false, vlan
, qos
, proto
);
4649 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4651 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4652 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4653 struct hclge_dev
*hdev
= vport
->back
;
4654 struct hclge_desc desc
;
4657 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4659 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4660 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4661 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4662 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG_B
,
4663 vcfg
->accept_tag
? 1 : 0);
4664 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG_B
,
4665 vcfg
->accept_untag
? 1 : 0);
4666 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4667 vcfg
->insert_tag1_en
? 1 : 0);
4668 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4669 vcfg
->insert_tag2_en
? 1 : 0);
4670 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4672 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4673 req
->vf_bitmap
[req
->vf_offset
] =
4674 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4676 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4678 dev_err(&hdev
->pdev
->dev
,
4679 "Send port txvlan cfg command fail, ret =%d\n",
4685 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4687 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4688 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4689 struct hclge_dev
*hdev
= vport
->back
;
4690 struct hclge_desc desc
;
4693 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4695 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4696 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4697 vcfg
->strip_tag1_en
? 1 : 0);
4698 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4699 vcfg
->strip_tag2_en
? 1 : 0);
4700 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4701 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4702 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4703 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4705 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4706 req
->vf_bitmap
[req
->vf_offset
] =
4707 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4709 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4711 dev_err(&hdev
->pdev
->dev
,
4712 "Send port rxvlan cfg command fail, ret =%d\n",
4718 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4720 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4721 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4722 struct hclge_desc desc
;
4725 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4726 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4727 rx_req
->ot_fst_vlan_type
=
4728 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4729 rx_req
->ot_sec_vlan_type
=
4730 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4731 rx_req
->in_fst_vlan_type
=
4732 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4733 rx_req
->in_sec_vlan_type
=
4734 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4736 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4738 dev_err(&hdev
->pdev
->dev
,
4739 "Send rxvlan protocol type command fail, ret =%d\n",
4744 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4746 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4747 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4748 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4750 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4752 dev_err(&hdev
->pdev
->dev
,
4753 "Send txvlan protocol type command fail, ret =%d\n",
4759 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4761 #define HCLGE_DEF_VLAN_TYPE 0x8100
4763 struct hnae3_handle
*handle
;
4764 struct hclge_vport
*vport
;
4768 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4772 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4776 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4777 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4778 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4779 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4780 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4781 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4783 ret
= hclge_set_vlan_protocol_type(hdev
);
4787 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4788 vport
= &hdev
->vport
[i
];
4789 vport
->txvlan_cfg
.accept_tag
= true;
4790 vport
->txvlan_cfg
.accept_untag
= true;
4791 vport
->txvlan_cfg
.insert_tag1_en
= false;
4792 vport
->txvlan_cfg
.insert_tag2_en
= false;
4793 vport
->txvlan_cfg
.default_tag1
= 0;
4794 vport
->txvlan_cfg
.default_tag2
= 0;
4796 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4800 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4801 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4802 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4803 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4805 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4810 handle
= &hdev
->vport
[0].nic
;
4811 return hclge_set_port_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4814 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4816 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4818 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4819 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4820 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4821 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4823 return hclge_set_vlan_rx_offload_cfg(vport
);
4826 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
4828 struct hclge_config_max_frm_size_cmd
*req
;
4829 struct hclge_desc desc
;
4833 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
4835 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
4836 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
4839 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
4841 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4843 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4844 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
4846 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4848 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4852 hdev
->mps
= max_frm_size
;
4857 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4859 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4860 struct hclge_dev
*hdev
= vport
->back
;
4863 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
4865 dev_err(&hdev
->pdev
->dev
,
4866 "Change mtu fail, ret =%d\n", ret
);
4870 ret
= hclge_buffer_alloc(hdev
);
4872 dev_err(&hdev
->pdev
->dev
,
4873 "Allocate buffer fail, ret =%d\n", ret
);
4878 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
4881 struct hclge_reset_tqp_queue_cmd
*req
;
4882 struct hclge_desc desc
;
4885 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
4887 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4888 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4889 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
4891 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4893 dev_err(&hdev
->pdev
->dev
,
4894 "Send tqp reset cmd error, status =%d\n", ret
);
4901 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
4903 struct hclge_reset_tqp_queue_cmd
*req
;
4904 struct hclge_desc desc
;
4907 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
4909 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4910 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4912 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4914 dev_err(&hdev
->pdev
->dev
,
4915 "Get reset status error, status =%d\n", ret
);
4919 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
4922 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
4925 struct hnae3_queue
*queue
;
4926 struct hclge_tqp
*tqp
;
4928 queue
= handle
->kinfo
.tqp
[queue_id
];
4929 tqp
= container_of(queue
, struct hclge_tqp
, q
);
4934 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
4936 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4937 struct hclge_dev
*hdev
= vport
->back
;
4938 int reset_try_times
= 0;
4943 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
4945 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
4947 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
4951 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
4953 dev_warn(&hdev
->pdev
->dev
,
4954 "Send reset tqp cmd fail, ret = %d\n", ret
);
4958 reset_try_times
= 0;
4959 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
4960 /* Wait for tqp hw reset */
4962 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
4967 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
4968 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
4972 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
4974 dev_warn(&hdev
->pdev
->dev
,
4975 "Deassert the soft reset fail, ret = %d\n", ret
);
4980 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
4982 struct hclge_dev
*hdev
= vport
->back
;
4983 int reset_try_times
= 0;
4988 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
4990 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
4992 dev_warn(&hdev
->pdev
->dev
,
4993 "Send reset tqp cmd fail, ret = %d\n", ret
);
4997 reset_try_times
= 0;
4998 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
4999 /* Wait for tqp hw reset */
5001 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5006 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5007 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5011 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5013 dev_warn(&hdev
->pdev
->dev
,
5014 "Deassert the soft reset fail, ret = %d\n", ret
);
5017 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5019 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5020 struct hclge_dev
*hdev
= vport
->back
;
5022 return hdev
->fw_version
;
5025 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5028 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5029 struct hclge_dev
*hdev
= vport
->back
;
5030 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5035 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5036 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5039 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5041 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5046 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5049 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5052 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5055 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5060 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5061 else if (rx_en
&& !tx_en
)
5062 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5063 else if (!rx_en
&& tx_en
)
5064 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5066 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5068 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5071 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5073 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5078 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5083 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5085 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5086 u16 remote_advertising
= 0;
5087 u16 local_advertising
= 0;
5088 u32 rx_pause
, tx_pause
;
5091 if (!phydev
->link
|| !phydev
->autoneg
)
5094 if (phydev
->advertising
& ADVERTISED_Pause
)
5095 local_advertising
= ADVERTISE_PAUSE_CAP
;
5097 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5098 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5101 remote_advertising
= LPA_PAUSE_CAP
;
5103 if (phydev
->asym_pause
)
5104 remote_advertising
|= LPA_PAUSE_ASYM
;
5106 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5107 remote_advertising
);
5108 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5109 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5111 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5116 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5119 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5120 u32
*rx_en
, u32
*tx_en
)
5122 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5123 struct hclge_dev
*hdev
= vport
->back
;
5125 *auto_neg
= hclge_get_autoneg(handle
);
5127 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5133 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5136 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5139 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5148 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5149 u32 rx_en
, u32 tx_en
)
5151 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5152 struct hclge_dev
*hdev
= vport
->back
;
5153 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5156 /* Only support flow control negotiation for netdev with
5157 * phy attached for now.
5162 fc_autoneg
= hclge_get_autoneg(handle
);
5163 if (auto_neg
!= fc_autoneg
) {
5164 dev_info(&hdev
->pdev
->dev
,
5165 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5169 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5170 dev_info(&hdev
->pdev
->dev
,
5171 "Priority flow control enabled. Cannot set link flow control.\n");
5175 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5178 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5180 return phy_start_aneg(phydev
);
5183 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5184 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5186 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5187 struct hclge_dev
*hdev
= vport
->back
;
5190 *speed
= hdev
->hw
.mac
.speed
;
5192 *duplex
= hdev
->hw
.mac
.duplex
;
5194 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5197 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5199 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5200 struct hclge_dev
*hdev
= vport
->back
;
5203 *media_type
= hdev
->hw
.mac
.media_type
;
5206 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5207 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5209 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5210 struct hclge_dev
*hdev
= vport
->back
;
5211 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5212 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5215 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5216 *tp_mdix
= ETH_TP_MDI_INVALID
;
5220 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5222 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5223 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5224 HCLGE_PHY_MDIX_CTRL_S
);
5226 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5227 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5228 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5230 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5232 switch (mdix_ctrl
) {
5234 *tp_mdix_ctrl
= ETH_TP_MDI
;
5237 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5240 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5243 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5248 *tp_mdix
= ETH_TP_MDI_INVALID
;
5250 *tp_mdix
= ETH_TP_MDI_X
;
5252 *tp_mdix
= ETH_TP_MDI
;
5255 static int hclge_init_client_instance(struct hnae3_client
*client
,
5256 struct hnae3_ae_dev
*ae_dev
)
5258 struct hclge_dev
*hdev
= ae_dev
->priv
;
5259 struct hclge_vport
*vport
;
5262 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5263 vport
= &hdev
->vport
[i
];
5265 switch (client
->type
) {
5266 case HNAE3_CLIENT_KNIC
:
5268 hdev
->nic_client
= client
;
5269 vport
->nic
.client
= client
;
5270 ret
= client
->ops
->init_instance(&vport
->nic
);
5274 if (hdev
->roce_client
&&
5275 hnae3_dev_roce_supported(hdev
)) {
5276 struct hnae3_client
*rc
= hdev
->roce_client
;
5278 ret
= hclge_init_roce_base_info(vport
);
5282 ret
= rc
->ops
->init_instance(&vport
->roce
);
5288 case HNAE3_CLIENT_UNIC
:
5289 hdev
->nic_client
= client
;
5290 vport
->nic
.client
= client
;
5292 ret
= client
->ops
->init_instance(&vport
->nic
);
5297 case HNAE3_CLIENT_ROCE
:
5298 if (hnae3_dev_roce_supported(hdev
)) {
5299 hdev
->roce_client
= client
;
5300 vport
->roce
.client
= client
;
5303 if (hdev
->roce_client
&& hdev
->nic_client
) {
5304 ret
= hclge_init_roce_base_info(vport
);
5308 ret
= client
->ops
->init_instance(&vport
->roce
);
5320 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5321 struct hnae3_ae_dev
*ae_dev
)
5323 struct hclge_dev
*hdev
= ae_dev
->priv
;
5324 struct hclge_vport
*vport
;
5327 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5328 vport
= &hdev
->vport
[i
];
5329 if (hdev
->roce_client
) {
5330 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5332 hdev
->roce_client
= NULL
;
5333 vport
->roce
.client
= NULL
;
5335 if (client
->type
== HNAE3_CLIENT_ROCE
)
5337 if (client
->ops
->uninit_instance
) {
5338 client
->ops
->uninit_instance(&vport
->nic
, 0);
5339 hdev
->nic_client
= NULL
;
5340 vport
->nic
.client
= NULL
;
5345 static int hclge_pci_init(struct hclge_dev
*hdev
)
5347 struct pci_dev
*pdev
= hdev
->pdev
;
5348 struct hclge_hw
*hw
;
5351 ret
= pci_enable_device(pdev
);
5353 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5354 goto err_no_drvdata
;
5357 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5359 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5362 "can't set consistent PCI DMA");
5363 goto err_disable_device
;
5365 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5368 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5370 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5371 goto err_disable_device
;
5374 pci_set_master(pdev
);
5377 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5379 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5381 goto err_clr_master
;
5384 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5388 pci_clear_master(pdev
);
5389 pci_release_regions(pdev
);
5391 pci_disable_device(pdev
);
5393 pci_set_drvdata(pdev
, NULL
);
5398 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5400 struct pci_dev
*pdev
= hdev
->pdev
;
5402 pci_free_irq_vectors(pdev
);
5403 pci_clear_master(pdev
);
5404 pci_release_mem_regions(pdev
);
5405 pci_disable_device(pdev
);
5408 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5410 struct pci_dev
*pdev
= ae_dev
->pdev
;
5411 struct hclge_dev
*hdev
;
5414 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5421 hdev
->ae_dev
= ae_dev
;
5422 hdev
->reset_type
= HNAE3_NONE_RESET
;
5423 hdev
->reset_request
= 0;
5424 hdev
->reset_pending
= 0;
5425 ae_dev
->priv
= hdev
;
5427 ret
= hclge_pci_init(hdev
);
5429 dev_err(&pdev
->dev
, "PCI init failed\n");
5433 /* Firmware command queue initialize */
5434 ret
= hclge_cmd_queue_init(hdev
);
5436 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5440 /* Firmware command initialize */
5441 ret
= hclge_cmd_init(hdev
);
5445 ret
= hclge_get_cap(hdev
);
5447 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5452 ret
= hclge_configure(hdev
);
5454 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5458 ret
= hclge_init_msi(hdev
);
5460 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5464 ret
= hclge_misc_irq_init(hdev
);
5467 "Misc IRQ(vector0) init error, ret = %d.\n",
5472 ret
= hclge_alloc_tqps(hdev
);
5474 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5478 ret
= hclge_alloc_vport(hdev
);
5480 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5484 ret
= hclge_map_tqp(hdev
);
5486 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5490 ret
= hclge_mac_mdio_config(hdev
);
5492 dev_warn(&hdev
->pdev
->dev
,
5493 "mdio config fail ret=%d\n", ret
);
5497 ret
= hclge_mac_init(hdev
);
5499 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5503 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5505 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5509 ret
= hclge_init_vlan_config(hdev
);
5511 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5515 ret
= hclge_tm_schd_init(hdev
);
5517 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5521 hclge_rss_init_cfg(hdev
);
5522 ret
= hclge_rss_init_hw(hdev
);
5524 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5528 ret
= init_mgr_tbl(hdev
);
5530 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5534 hclge_dcb_ops_set(hdev
);
5536 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5537 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5538 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5539 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5541 /* Enable MISC vector(vector0) */
5542 hclge_enable_vector(&hdev
->misc_vector
, true);
5544 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5545 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5546 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5547 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5548 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5549 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5551 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5555 pci_release_regions(pdev
);
5557 pci_set_drvdata(pdev
, NULL
);
5562 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5564 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5567 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5569 struct hclge_dev
*hdev
= ae_dev
->priv
;
5570 struct pci_dev
*pdev
= ae_dev
->pdev
;
5573 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5575 hclge_stats_clear(hdev
);
5577 ret
= hclge_cmd_init(hdev
);
5579 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5583 ret
= hclge_get_cap(hdev
);
5585 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5590 ret
= hclge_configure(hdev
);
5592 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5596 ret
= hclge_map_tqp(hdev
);
5598 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5602 ret
= hclge_mac_init(hdev
);
5604 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5608 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5610 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5614 ret
= hclge_init_vlan_config(hdev
);
5616 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5620 ret
= hclge_tm_init_hw(hdev
);
5622 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5626 ret
= hclge_rss_init_hw(hdev
);
5628 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5632 /* Enable MISC vector(vector0) */
5633 hclge_enable_vector(&hdev
->misc_vector
, true);
5635 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5641 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5643 struct hclge_dev
*hdev
= ae_dev
->priv
;
5644 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5646 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5648 if (IS_ENABLED(CONFIG_PCI_IOV
))
5649 hclge_disable_sriov(hdev
);
5651 if (hdev
->service_timer
.function
)
5652 del_timer_sync(&hdev
->service_timer
);
5653 if (hdev
->service_task
.func
)
5654 cancel_work_sync(&hdev
->service_task
);
5655 if (hdev
->rst_service_task
.func
)
5656 cancel_work_sync(&hdev
->rst_service_task
);
5657 if (hdev
->mbx_service_task
.func
)
5658 cancel_work_sync(&hdev
->mbx_service_task
);
5661 mdiobus_unregister(mac
->mdio_bus
);
5663 /* Disable MISC vector(vector0) */
5664 hclge_enable_vector(&hdev
->misc_vector
, false);
5665 hclge_destroy_cmd_queue(&hdev
->hw
);
5666 hclge_misc_irq_uninit(hdev
);
5667 hclge_pci_uninit(hdev
);
5668 ae_dev
->priv
= NULL
;
5671 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5673 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5674 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5675 struct hclge_dev
*hdev
= vport
->back
;
5677 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5680 static void hclge_get_channels(struct hnae3_handle
*handle
,
5681 struct ethtool_channels
*ch
)
5683 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5685 ch
->max_combined
= hclge_get_max_channels(handle
);
5686 ch
->other_count
= 1;
5688 ch
->combined_count
= vport
->alloc_tqps
;
5691 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5692 u16
*free_tqps
, u16
*max_rss_size
)
5694 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5695 struct hclge_dev
*hdev
= vport
->back
;
5699 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5700 if (!hdev
->htqp
[i
].alloced
)
5703 *free_tqps
= temp_tqps
;
5704 *max_rss_size
= hdev
->rss_size_max
;
5707 static void hclge_release_tqp(struct hclge_vport
*vport
)
5709 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5710 struct hclge_dev
*hdev
= vport
->back
;
5713 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5714 struct hclge_tqp
*tqp
=
5715 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5717 tqp
->q
.handle
= NULL
;
5718 tqp
->q
.tqp_index
= 0;
5719 tqp
->alloced
= false;
5722 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5726 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5728 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5729 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5730 struct hclge_dev
*hdev
= vport
->back
;
5731 int cur_rss_size
= kinfo
->rss_size
;
5732 int cur_tqps
= kinfo
->num_tqps
;
5733 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5734 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5735 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5740 hclge_release_tqp(vport
);
5742 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5744 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5748 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5750 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5754 ret
= hclge_tm_schd_init(hdev
);
5756 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5760 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5761 roundup_size
= ilog2(roundup_size
);
5762 /* Set the RSS TC mode according to the new RSS size */
5763 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5766 if (!(hdev
->hw_tc_map
& BIT(i
)))
5770 tc_size
[i
] = roundup_size
;
5771 tc_offset
[i
] = kinfo
->rss_size
* i
;
5773 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5777 /* Reinitializes the rss indirect table according to the new RSS size */
5778 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5782 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5783 rss_indir
[i
] = i
% kinfo
->rss_size
;
5785 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5787 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5793 dev_info(&hdev
->pdev
->dev
,
5794 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5795 cur_rss_size
, kinfo
->rss_size
,
5796 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5801 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5802 u32
*regs_num_64_bit
)
5804 struct hclge_desc desc
;
5808 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
5809 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5811 dev_err(&hdev
->pdev
->dev
,
5812 "Query register number cmd failed, ret = %d.\n", ret
);
5816 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
5817 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
5819 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
5826 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5829 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
5831 struct hclge_desc
*desc
;
5832 u32
*reg_val
= data
;
5841 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
5842 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5846 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
5847 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5849 dev_err(&hdev
->pdev
->dev
,
5850 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
5855 for (i
= 0; i
< cmd_num
; i
++) {
5857 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
5858 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
5860 desc_data
= (__le32
*)(&desc
[i
]);
5861 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
5863 for (k
= 0; k
< n
; k
++) {
5864 *reg_val
++ = le32_to_cpu(*desc_data
++);
5876 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5879 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
5881 struct hclge_desc
*desc
;
5882 u64
*reg_val
= data
;
5891 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
5892 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5896 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
5897 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5899 dev_err(&hdev
->pdev
->dev
,
5900 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
5905 for (i
= 0; i
< cmd_num
; i
++) {
5907 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
5908 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
5910 desc_data
= (__le64
*)(&desc
[i
]);
5911 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
5913 for (k
= 0; k
< n
; k
++) {
5914 *reg_val
++ = le64_to_cpu(*desc_data
++);
5926 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
5928 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5929 struct hclge_dev
*hdev
= vport
->back
;
5930 u32 regs_num_32_bit
, regs_num_64_bit
;
5933 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
5935 dev_err(&hdev
->pdev
->dev
,
5936 "Get register number failed, ret = %d.\n", ret
);
5940 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
5943 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
5946 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5947 struct hclge_dev
*hdev
= vport
->back
;
5948 u32 regs_num_32_bit
, regs_num_64_bit
;
5951 *version
= hdev
->fw_version
;
5953 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
5955 dev_err(&hdev
->pdev
->dev
,
5956 "Get register number failed, ret = %d.\n", ret
);
5960 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
5962 dev_err(&hdev
->pdev
->dev
,
5963 "Get 32 bit register failed, ret = %d.\n", ret
);
5967 data
= (u32
*)data
+ regs_num_32_bit
;
5968 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
5971 dev_err(&hdev
->pdev
->dev
,
5972 "Get 64 bit register failed, ret = %d.\n", ret
);
5975 static int hclge_set_led_status_sfp(struct hclge_dev
*hdev
, u8 speed_led_status
,
5976 u8 act_led_status
, u8 link_led_status
,
5977 u8 locate_led_status
)
5979 struct hclge_set_led_state_cmd
*req
;
5980 struct hclge_desc desc
;
5983 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
5985 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
5986 hnae_set_field(req
->port_speed_led_config
, HCLGE_LED_PORT_SPEED_STATE_M
,
5987 HCLGE_LED_PORT_SPEED_STATE_S
, speed_led_status
);
5988 hnae_set_field(req
->link_led_config
, HCLGE_LED_ACTIVITY_STATE_M
,
5989 HCLGE_LED_ACTIVITY_STATE_S
, act_led_status
);
5990 hnae_set_field(req
->activity_led_config
, HCLGE_LED_LINK_STATE_M
,
5991 HCLGE_LED_LINK_STATE_S
, link_led_status
);
5992 hnae_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
5993 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
5995 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5997 dev_err(&hdev
->pdev
->dev
,
5998 "Send set led state cmd error, ret =%d\n", ret
);
6003 enum hclge_led_status
{
6006 HCLGE_LED_NO_CHANGE
= 0xFF,
6009 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6010 enum ethtool_phys_id_state status
)
6012 #define BLINK_FREQUENCY 2
6013 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6014 struct hclge_dev
*hdev
= vport
->back
;
6015 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
6018 if (phydev
|| hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
6022 case ETHTOOL_ID_ACTIVE
:
6023 ret
= hclge_set_led_status_sfp(hdev
,
6024 HCLGE_LED_NO_CHANGE
,
6025 HCLGE_LED_NO_CHANGE
,
6026 HCLGE_LED_NO_CHANGE
,
6029 case ETHTOOL_ID_INACTIVE
:
6030 ret
= hclge_set_led_status_sfp(hdev
,
6031 HCLGE_LED_NO_CHANGE
,
6032 HCLGE_LED_NO_CHANGE
,
6033 HCLGE_LED_NO_CHANGE
,
6044 enum hclge_led_port_speed
{
6045 HCLGE_SPEED_LED_FOR_1G
,
6046 HCLGE_SPEED_LED_FOR_10G
,
6047 HCLGE_SPEED_LED_FOR_25G
,
6048 HCLGE_SPEED_LED_FOR_40G
,
6049 HCLGE_SPEED_LED_FOR_50G
,
6050 HCLGE_SPEED_LED_FOR_100G
,
6053 static u8
hclge_led_get_speed_status(u32 speed
)
6058 case HCLGE_MAC_SPEED_1G
:
6059 speed_led
= HCLGE_SPEED_LED_FOR_1G
;
6061 case HCLGE_MAC_SPEED_10G
:
6062 speed_led
= HCLGE_SPEED_LED_FOR_10G
;
6064 case HCLGE_MAC_SPEED_25G
:
6065 speed_led
= HCLGE_SPEED_LED_FOR_25G
;
6067 case HCLGE_MAC_SPEED_40G
:
6068 speed_led
= HCLGE_SPEED_LED_FOR_40G
;
6070 case HCLGE_MAC_SPEED_50G
:
6071 speed_led
= HCLGE_SPEED_LED_FOR_50G
;
6073 case HCLGE_MAC_SPEED_100G
:
6074 speed_led
= HCLGE_SPEED_LED_FOR_100G
;
6077 speed_led
= HCLGE_LED_NO_CHANGE
;
6083 static int hclge_update_led_status(struct hclge_dev
*hdev
)
6085 u8 port_speed_status
, link_status
, activity_status
;
6086 u64 rx_pkts
, tx_pkts
;
6088 if (hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
6091 port_speed_status
= hclge_led_get_speed_status(hdev
->hw
.mac
.speed
);
6093 rx_pkts
= hdev
->hw_stats
.mac_stats
.mac_rx_total_pkt_num
;
6094 tx_pkts
= hdev
->hw_stats
.mac_stats
.mac_tx_total_pkt_num
;
6095 if (rx_pkts
!= hdev
->rx_pkts_for_led
||
6096 tx_pkts
!= hdev
->tx_pkts_for_led
)
6097 activity_status
= HCLGE_LED_ON
;
6099 activity_status
= HCLGE_LED_OFF
;
6100 hdev
->rx_pkts_for_led
= rx_pkts
;
6101 hdev
->tx_pkts_for_led
= tx_pkts
;
6103 if (hdev
->hw
.mac
.link
)
6104 link_status
= HCLGE_LED_ON
;
6106 link_status
= HCLGE_LED_OFF
;
6108 return hclge_set_led_status_sfp(hdev
, port_speed_status
,
6109 activity_status
, link_status
,
6110 HCLGE_LED_NO_CHANGE
);
6113 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6114 unsigned long *supported
,
6115 unsigned long *advertising
)
6117 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6118 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6119 struct hclge_dev
*hdev
= vport
->back
;
6120 unsigned int idx
= 0;
6122 for (; idx
< size
; idx
++) {
6123 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6124 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6128 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6131 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6132 struct hclge_dev
*hdev
= vport
->back
;
6133 u8 media_type
= hdev
->hw
.mac
.media_type
;
6135 switch (media_type
) {
6136 case HNAE3_MEDIA_TYPE_FIBER
:
6137 *port_type
= PORT_FIBRE
;
6139 case HNAE3_MEDIA_TYPE_COPPER
:
6140 *port_type
= PORT_TP
;
6142 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6144 *port_type
= PORT_OTHER
;
6149 static const struct hnae3_ae_ops hclge_ops
= {
6150 .init_ae_dev
= hclge_init_ae_dev
,
6151 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6152 .init_client_instance
= hclge_init_client_instance
,
6153 .uninit_client_instance
= hclge_uninit_client_instance
,
6154 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6155 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6156 .get_vector
= hclge_get_vector
,
6157 .put_vector
= hclge_put_vector
,
6158 .set_promisc_mode
= hclge_set_promisc_mode
,
6159 .set_loopback
= hclge_set_loopback
,
6160 .start
= hclge_ae_start
,
6161 .stop
= hclge_ae_stop
,
6162 .get_status
= hclge_get_status
,
6163 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6164 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6165 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6166 .get_media_type
= hclge_get_media_type
,
6167 .get_rss_key_size
= hclge_get_rss_key_size
,
6168 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6169 .get_rss
= hclge_get_rss
,
6170 .set_rss
= hclge_set_rss
,
6171 .set_rss_tuple
= hclge_set_rss_tuple
,
6172 .get_rss_tuple
= hclge_get_rss_tuple
,
6173 .get_tc_size
= hclge_get_tc_size
,
6174 .get_mac_addr
= hclge_get_mac_addr
,
6175 .set_mac_addr
= hclge_set_mac_addr
,
6176 .add_uc_addr
= hclge_add_uc_addr
,
6177 .rm_uc_addr
= hclge_rm_uc_addr
,
6178 .add_mc_addr
= hclge_add_mc_addr
,
6179 .rm_mc_addr
= hclge_rm_mc_addr
,
6180 .set_autoneg
= hclge_set_autoneg
,
6181 .get_autoneg
= hclge_get_autoneg
,
6182 .get_pauseparam
= hclge_get_pauseparam
,
6183 .set_pauseparam
= hclge_set_pauseparam
,
6184 .set_mtu
= hclge_set_mtu
,
6185 .reset_queue
= hclge_reset_tqp
,
6186 .get_stats
= hclge_get_stats
,
6187 .update_stats
= hclge_update_stats
,
6188 .get_strings
= hclge_get_strings
,
6189 .get_sset_count
= hclge_get_sset_count
,
6190 .get_fw_version
= hclge_get_fw_version
,
6191 .get_mdix_mode
= hclge_get_mdix_mode
,
6192 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6193 .set_vlan_filter
= hclge_set_port_vlan_filter
,
6194 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6195 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6196 .reset_event
= hclge_reset_event
,
6197 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6198 .set_channels
= hclge_set_channels
,
6199 .get_channels
= hclge_get_channels
,
6200 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6201 .get_regs_len
= hclge_get_regs_len
,
6202 .get_regs
= hclge_get_regs
,
6203 .set_led_id
= hclge_set_led_id
,
6204 .get_link_mode
= hclge_get_link_mode
,
6205 .get_port_type
= hclge_get_port_type
,
6208 static struct hnae3_ae_algo ae_algo
= {
6211 .pdev_id_table
= ae_algo_pci_tbl
,
6214 static int hclge_init(void)
6216 pr_info("%s is initializing\n", HCLGE_NAME
);
6218 return hnae3_register_ae_algo(&ae_algo
);
6221 static void hclge_exit(void)
6223 hnae3_unregister_ae_algo(&ae_algo
);
6225 module_init(hclge_init
);
6226 module_exit(hclge_exit
);
6228 MODULE_LICENSE("GPL");
6229 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6230 MODULE_DESCRIPTION("HCLGE Driver");
6231 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob