]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
UBUNTU: SAUCE: {topost} net: hns3: Add calling roce callback function when link statu...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/acpi.h>
5 #include <linux/device.h>
6 #include <linux/etherdevice.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/netdevice.h>
12 #include <linux/pci.h>
13 #include <linux/platform_device.h>
14 #include <linux/if_vlan.h>
15 #include <net/rtnetlink.h>
16 #include "hclge_cmd.h"
17 #include "hclge_dcb.h"
18 #include "hclge_main.h"
19 #include "hclge_mbx.h"
20 #include "hclge_mdio.h"
21 #include "hclge_tm.h"
22 #include "hnae3.h"
23
24 #define HCLGE_NAME "hclge"
25 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
27 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
28 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
29
30 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
31 enum hclge_mta_dmac_sel_type mta_mac_sel,
32 bool enable);
33 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
34 static int hclge_init_vlan_config(struct hclge_dev *hdev);
35 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
36
37 static struct hnae3_ae_algo ae_algo;
38
39 static const struct pci_device_id ae_algo_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
47 /* required last entry */
48 {0, }
49 };
50
51 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
52
53 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
54 "Mac Loopback test",
55 "Serdes Loopback test",
56 "Phy Loopback test"
57 };
58
59 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
66 {"igu_rx_uni_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
68 {"igu_rx_multi_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
70 {"igu_rx_broad_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
74 {"egu_tx_uni_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
76 {"egu_tx_multi_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
78 {"egu_tx_broad_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
88 {"ssu_tx_in_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
90 {"ssu_tx_out_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
92 {"ssu_rx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
94 {"ssu_rx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
96 };
97
98 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
99 {"igu_rx_err_pkt",
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
105 {"egu_tx_1588_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
111 {"ppp_key_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
113 {"ppp_rlt_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
115 {"ssu_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
117 {"pkt_curr_buf_cnt",
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
119 {"qcn_fb_rcv_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
121 {"qcn_fb_drop_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
205 {"mb_uncopy_num",
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
221 };
222
223 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
280 {"mac_tx_oversize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
294 {"mac_tx_1519_2047_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
296 {"mac_tx_2048_4095_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
298 {"mac_tx_4096_8191_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
300 {"mac_tx_8192_9216_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
302 {"mac_tx_9217_12287_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
304 {"mac_tx_12288_16383_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
306 {"mac_tx_1519_max_good_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
308 {"mac_tx_1519_max_bad_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
310 {"mac_rx_total_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
312 {"mac_rx_total_oct_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
314 {"mac_rx_good_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
316 {"mac_rx_bad_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
318 {"mac_rx_good_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
320 {"mac_rx_bad_oct_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
322 {"mac_rx_uni_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
324 {"mac_rx_multi_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
326 {"mac_rx_broad_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
328 {"mac_rx_undersize_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
330 {"mac_rx_oversize_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
332 {"mac_rx_64_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
334 {"mac_rx_65_127_oct_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
336 {"mac_rx_128_255_oct_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
338 {"mac_rx_256_511_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
340 {"mac_rx_512_1023_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
342 {"mac_rx_1024_1518_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
344 {"mac_rx_1519_2047_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
346 {"mac_rx_2048_4095_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
348 {"mac_rx_4096_8191_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
350 {"mac_rx_8192_9216_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
352 {"mac_rx_9217_12287_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
354 {"mac_rx_12288_16383_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
356 {"mac_rx_1519_max_good_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
358 {"mac_rx_1519_max_bad_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
360
361 {"mac_tx_fragment_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
363 {"mac_tx_undermin_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
365 {"mac_tx_jabber_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
367 {"mac_tx_err_all_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
369 {"mac_tx_from_app_good_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
371 {"mac_tx_from_app_bad_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
373 {"mac_rx_fragment_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
375 {"mac_rx_undermin_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
377 {"mac_rx_jabber_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
379 {"mac_rx_fcs_err_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
381 {"mac_rx_send_app_good_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
383 {"mac_rx_send_app_bad_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
385 };
386
387 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
388 {
389 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
390 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
391 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
392 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
393 .i_port_bitmap = 0x1,
394 },
395 };
396
397 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
398 {
399 #define HCLGE_64_BIT_CMD_NUM 5
400 #define HCLGE_64_BIT_RTN_DATANUM 4
401 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
402 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
403 __le64 *desc_data;
404 int i, k, n;
405 int ret;
406
407 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
408 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
409 if (ret) {
410 dev_err(&hdev->pdev->dev,
411 "Get 64 bit pkt stats fail, status = %d.\n", ret);
412 return ret;
413 }
414
415 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
416 if (unlikely(i == 0)) {
417 desc_data = (__le64 *)(&desc[i].data[0]);
418 n = HCLGE_64_BIT_RTN_DATANUM - 1;
419 } else {
420 desc_data = (__le64 *)(&desc[i]);
421 n = HCLGE_64_BIT_RTN_DATANUM;
422 }
423 for (k = 0; k < n; k++) {
424 *data++ += le64_to_cpu(*desc_data);
425 desc_data++;
426 }
427 }
428
429 return 0;
430 }
431
432 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
433 {
434 stats->pkt_curr_buf_cnt = 0;
435 stats->pkt_curr_buf_tc0_cnt = 0;
436 stats->pkt_curr_buf_tc1_cnt = 0;
437 stats->pkt_curr_buf_tc2_cnt = 0;
438 stats->pkt_curr_buf_tc3_cnt = 0;
439 stats->pkt_curr_buf_tc4_cnt = 0;
440 stats->pkt_curr_buf_tc5_cnt = 0;
441 stats->pkt_curr_buf_tc6_cnt = 0;
442 stats->pkt_curr_buf_tc7_cnt = 0;
443 }
444
445 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
446 {
447 #define HCLGE_32_BIT_CMD_NUM 8
448 #define HCLGE_32_BIT_RTN_DATANUM 8
449
450 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
451 struct hclge_32_bit_stats *all_32_bit_stats;
452 __le32 *desc_data;
453 int i, k, n;
454 u64 *data;
455 int ret;
456
457 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
458 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
459
460 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
461 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
462 if (ret) {
463 dev_err(&hdev->pdev->dev,
464 "Get 32 bit pkt stats fail, status = %d.\n", ret);
465
466 return ret;
467 }
468
469 hclge_reset_partial_32bit_counter(all_32_bit_stats);
470 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
471 if (unlikely(i == 0)) {
472 __le16 *desc_data_16bit;
473
474 all_32_bit_stats->igu_rx_err_pkt +=
475 le32_to_cpu(desc[i].data[0]);
476
477 desc_data_16bit = (__le16 *)&desc[i].data[1];
478 all_32_bit_stats->igu_rx_no_eof_pkt +=
479 le16_to_cpu(*desc_data_16bit);
480
481 desc_data_16bit++;
482 all_32_bit_stats->igu_rx_no_sof_pkt +=
483 le16_to_cpu(*desc_data_16bit);
484
485 desc_data = &desc[i].data[2];
486 n = HCLGE_32_BIT_RTN_DATANUM - 4;
487 } else {
488 desc_data = (__le32 *)&desc[i];
489 n = HCLGE_32_BIT_RTN_DATANUM;
490 }
491 for (k = 0; k < n; k++) {
492 *data++ += le32_to_cpu(*desc_data);
493 desc_data++;
494 }
495 }
496
497 return 0;
498 }
499
500 static int hclge_mac_update_stats(struct hclge_dev *hdev)
501 {
502 #define HCLGE_MAC_CMD_NUM 21
503 #define HCLGE_RTN_DATA_NUM 4
504
505 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
506 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
507 __le64 *desc_data;
508 int i, k, n;
509 int ret;
510
511 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
513 if (ret) {
514 dev_err(&hdev->pdev->dev,
515 "Get MAC pkt stats fail, status = %d.\n", ret);
516
517 return ret;
518 }
519
520 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
521 if (unlikely(i == 0)) {
522 desc_data = (__le64 *)(&desc[i].data[0]);
523 n = HCLGE_RTN_DATA_NUM - 2;
524 } else {
525 desc_data = (__le64 *)(&desc[i]);
526 n = HCLGE_RTN_DATA_NUM;
527 }
528 for (k = 0; k < n; k++) {
529 *data++ += le64_to_cpu(*desc_data);
530 desc_data++;
531 }
532 }
533
534 return 0;
535 }
536
537 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
538 {
539 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
540 struct hclge_vport *vport = hclge_get_vport(handle);
541 struct hclge_dev *hdev = vport->back;
542 struct hnae3_queue *queue;
543 struct hclge_desc desc[1];
544 struct hclge_tqp *tqp;
545 int ret, i;
546
547 for (i = 0; i < kinfo->num_tqps; i++) {
548 queue = handle->kinfo.tqp[i];
549 tqp = container_of(queue, struct hclge_tqp, q);
550 /* command : HCLGE_OPC_QUERY_IGU_STAT */
551 hclge_cmd_setup_basic_desc(&desc[0],
552 HCLGE_OPC_QUERY_RX_STATUS,
553 true);
554
555 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
556 ret = hclge_cmd_send(&hdev->hw, desc, 1);
557 if (ret) {
558 dev_err(&hdev->pdev->dev,
559 "Query tqp stat fail, status = %d,queue = %d\n",
560 ret, i);
561 return ret;
562 }
563 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
564 le32_to_cpu(desc[0].data[1]);
565 }
566
567 for (i = 0; i < kinfo->num_tqps; i++) {
568 queue = handle->kinfo.tqp[i];
569 tqp = container_of(queue, struct hclge_tqp, q);
570 /* command : HCLGE_OPC_QUERY_IGU_STAT */
571 hclge_cmd_setup_basic_desc(&desc[0],
572 HCLGE_OPC_QUERY_TX_STATUS,
573 true);
574
575 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
576 ret = hclge_cmd_send(&hdev->hw, desc, 1);
577 if (ret) {
578 dev_err(&hdev->pdev->dev,
579 "Query tqp stat fail, status = %d,queue = %d\n",
580 ret, i);
581 return ret;
582 }
583 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
584 le32_to_cpu(desc[0].data[1]);
585 }
586
587 return 0;
588 }
589
590 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
591 {
592 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
593 struct hclge_tqp *tqp;
594 u64 *buff = data;
595 int i;
596
597 for (i = 0; i < kinfo->num_tqps; i++) {
598 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
599 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
600 }
601
602 for (i = 0; i < kinfo->num_tqps; i++) {
603 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
604 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
605 }
606
607 return buff;
608 }
609
610 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
611 {
612 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
613
614 return kinfo->num_tqps * (2);
615 }
616
617 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
618 {
619 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
620 u8 *buff = data;
621 int i = 0;
622
623 for (i = 0; i < kinfo->num_tqps; i++) {
624 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
625 struct hclge_tqp, q);
626 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
627 tqp->index);
628 buff = buff + ETH_GSTRING_LEN;
629 }
630
631 for (i = 0; i < kinfo->num_tqps; i++) {
632 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
633 struct hclge_tqp, q);
634 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
635 tqp->index);
636 buff = buff + ETH_GSTRING_LEN;
637 }
638
639 return buff;
640 }
641
642 static u64 *hclge_comm_get_stats(void *comm_stats,
643 const struct hclge_comm_stats_str strs[],
644 int size, u64 *data)
645 {
646 u64 *buf = data;
647 u32 i;
648
649 for (i = 0; i < size; i++)
650 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
651
652 return buf + size;
653 }
654
655 static u8 *hclge_comm_get_strings(u32 stringset,
656 const struct hclge_comm_stats_str strs[],
657 int size, u8 *data)
658 {
659 char *buff = (char *)data;
660 u32 i;
661
662 if (stringset != ETH_SS_STATS)
663 return buff;
664
665 for (i = 0; i < size; i++) {
666 snprintf(buff, ETH_GSTRING_LEN,
667 strs[i].desc);
668 buff = buff + ETH_GSTRING_LEN;
669 }
670
671 return (u8 *)buff;
672 }
673
674 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
675 struct net_device_stats *net_stats)
676 {
677 net_stats->tx_dropped = 0;
678 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
679 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
680 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
681
682 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
683 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
684 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
685 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
686 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
687
688 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
689 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
690
691 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
692 net_stats->rx_length_errors =
693 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
694 net_stats->rx_length_errors +=
695 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
696 net_stats->rx_over_errors =
697 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
698 }
699
700 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
701 {
702 struct hnae3_handle *handle;
703 int status;
704
705 handle = &hdev->vport[0].nic;
706 if (handle->client) {
707 status = hclge_tqps_update_stats(handle);
708 if (status) {
709 dev_err(&hdev->pdev->dev,
710 "Update TQPS stats fail, status = %d.\n",
711 status);
712 }
713 }
714
715 status = hclge_mac_update_stats(hdev);
716 if (status)
717 dev_err(&hdev->pdev->dev,
718 "Update MAC stats fail, status = %d.\n", status);
719
720 status = hclge_32_bit_update_stats(hdev);
721 if (status)
722 dev_err(&hdev->pdev->dev,
723 "Update 32 bit stats fail, status = %d.\n",
724 status);
725
726 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
727 }
728
729 static void hclge_update_stats(struct hnae3_handle *handle,
730 struct net_device_stats *net_stats)
731 {
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
735 int status;
736
737 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
738 return;
739
740 status = hclge_mac_update_stats(hdev);
741 if (status)
742 dev_err(&hdev->pdev->dev,
743 "Update MAC stats fail, status = %d.\n",
744 status);
745
746 status = hclge_32_bit_update_stats(hdev);
747 if (status)
748 dev_err(&hdev->pdev->dev,
749 "Update 32 bit stats fail, status = %d.\n",
750 status);
751
752 status = hclge_64_bit_update_stats(hdev);
753 if (status)
754 dev_err(&hdev->pdev->dev,
755 "Update 64 bit stats fail, status = %d.\n",
756 status);
757
758 status = hclge_tqps_update_stats(handle);
759 if (status)
760 dev_err(&hdev->pdev->dev,
761 "Update TQPS stats fail, status = %d.\n",
762 status);
763
764 hclge_update_netstat(hw_stats, net_stats);
765
766 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
767 }
768
769 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
770 {
771 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
772
773 struct hclge_vport *vport = hclge_get_vport(handle);
774 struct hclge_dev *hdev = vport->back;
775 int count = 0;
776
777 /* Loopback test support rules:
778 * mac: only GE mode support
779 * serdes: all mac mode will support include GE/XGE/LGE/CGE
780 * phy: only support when phy device exist on board
781 */
782 if (stringset == ETH_SS_TEST) {
783 /* clear loopback bit flags at first */
784 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
785 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
786 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
787 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
788 count += 1;
789 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
790 }
791
792 count ++;
793 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
794 } else if (stringset == ETH_SS_STATS) {
795 count = ARRAY_SIZE(g_mac_stats_string) +
796 ARRAY_SIZE(g_all_32bit_stats_string) +
797 ARRAY_SIZE(g_all_64bit_stats_string) +
798 hclge_tqps_get_sset_count(handle, stringset);
799 }
800
801 return count;
802 }
803
804 static void hclge_get_strings(struct hnae3_handle *handle,
805 u32 stringset,
806 u8 *data)
807 {
808 u8 *p = (char *)data;
809 int size;
810
811 if (stringset == ETH_SS_STATS) {
812 size = ARRAY_SIZE(g_mac_stats_string);
813 p = hclge_comm_get_strings(stringset,
814 g_mac_stats_string,
815 size,
816 p);
817 size = ARRAY_SIZE(g_all_32bit_stats_string);
818 p = hclge_comm_get_strings(stringset,
819 g_all_32bit_stats_string,
820 size,
821 p);
822 size = ARRAY_SIZE(g_all_64bit_stats_string);
823 p = hclge_comm_get_strings(stringset,
824 g_all_64bit_stats_string,
825 size,
826 p);
827 p = hclge_tqps_get_strings(handle, p);
828 } else if (stringset == ETH_SS_TEST) {
829 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
830 memcpy(p,
831 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
832 ETH_GSTRING_LEN);
833 p += ETH_GSTRING_LEN;
834 }
835 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
836 memcpy(p,
837 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
838 ETH_GSTRING_LEN);
839 p += ETH_GSTRING_LEN;
840 }
841 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
842 memcpy(p,
843 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
844 ETH_GSTRING_LEN);
845 p += ETH_GSTRING_LEN;
846 }
847 }
848 }
849
850 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
851 {
852 struct hclge_vport *vport = hclge_get_vport(handle);
853 struct hclge_dev *hdev = vport->back;
854 u64 *p;
855
856 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
857 g_mac_stats_string,
858 ARRAY_SIZE(g_mac_stats_string),
859 data);
860 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
861 g_all_32bit_stats_string,
862 ARRAY_SIZE(g_all_32bit_stats_string),
863 p);
864 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
865 g_all_64bit_stats_string,
866 ARRAY_SIZE(g_all_64bit_stats_string),
867 p);
868 p = hclge_tqps_get_stats(handle, p);
869 }
870
871 static int hclge_parse_func_status(struct hclge_dev *hdev,
872 struct hclge_func_status_cmd *status)
873 {
874 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
875 return -EINVAL;
876
877 /* Set the pf to main pf */
878 if (status->pf_state & HCLGE_PF_STATE_MAIN)
879 hdev->flag |= HCLGE_FLAG_MAIN;
880 else
881 hdev->flag &= ~HCLGE_FLAG_MAIN;
882
883 return 0;
884 }
885
886 static int hclge_query_function_status(struct hclge_dev *hdev)
887 {
888 struct hclge_func_status_cmd *req;
889 struct hclge_desc desc;
890 int timeout = 0;
891 int ret;
892
893 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
894 req = (struct hclge_func_status_cmd *)desc.data;
895
896 do {
897 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
898 if (ret) {
899 dev_err(&hdev->pdev->dev,
900 "query function status failed %d.\n",
901 ret);
902
903 return ret;
904 }
905
906 /* Check pf reset is done */
907 if (req->pf_state)
908 break;
909 usleep_range(1000, 2000);
910 } while (timeout++ < 5);
911
912 ret = hclge_parse_func_status(hdev, req);
913
914 return ret;
915 }
916
917 static int hclge_query_pf_resource(struct hclge_dev *hdev)
918 {
919 struct hclge_pf_res_cmd *req;
920 struct hclge_desc desc;
921 int ret;
922
923 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
924 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
925 if (ret) {
926 dev_err(&hdev->pdev->dev,
927 "query pf resource failed %d.\n", ret);
928 return ret;
929 }
930
931 req = (struct hclge_pf_res_cmd *)desc.data;
932 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
933 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
934
935 if (hnae3_dev_roce_supported(hdev)) {
936 hdev->num_roce_msi =
937 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
938 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
939
940 /* PF should have NIC vectors and Roce vectors,
941 * NIC vectors are queued before Roce vectors.
942 */
943 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
944 } else {
945 hdev->num_msi =
946 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
947 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
948 }
949
950 return 0;
951 }
952
953 static int hclge_parse_speed(int speed_cmd, int *speed)
954 {
955 switch (speed_cmd) {
956 case 6:
957 *speed = HCLGE_MAC_SPEED_10M;
958 break;
959 case 7:
960 *speed = HCLGE_MAC_SPEED_100M;
961 break;
962 case 0:
963 *speed = HCLGE_MAC_SPEED_1G;
964 break;
965 case 1:
966 *speed = HCLGE_MAC_SPEED_10G;
967 break;
968 case 2:
969 *speed = HCLGE_MAC_SPEED_25G;
970 break;
971 case 3:
972 *speed = HCLGE_MAC_SPEED_40G;
973 break;
974 case 4:
975 *speed = HCLGE_MAC_SPEED_50G;
976 break;
977 case 5:
978 *speed = HCLGE_MAC_SPEED_100G;
979 break;
980 default:
981 return -EINVAL;
982 }
983
984 return 0;
985 }
986
987 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
988 u8 speed_ability)
989 {
990 unsigned long *supported = hdev->hw.mac.supported;
991
992 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
993 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
994 supported);
995
996 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
997 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
998 supported);
999
1000 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1001 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1002 supported);
1003
1004 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1005 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1006 supported);
1007
1008 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1009 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1010 supported);
1011
1012 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1013 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1014 }
1015
1016 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1017 {
1018 u8 media_type = hdev->hw.mac.media_type;
1019
1020 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1021 return;
1022
1023 hclge_parse_fiber_link_mode(hdev, speed_ability);
1024 }
1025
1026 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1027 {
1028 struct hclge_cfg_param_cmd *req;
1029 u64 mac_addr_tmp_high;
1030 u64 mac_addr_tmp;
1031 int i;
1032
1033 req = (struct hclge_cfg_param_cmd *)desc[0].data;
1034
1035 /* get the configuration */
1036 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1037 HCLGE_CFG_VMDQ_M,
1038 HCLGE_CFG_VMDQ_S);
1039 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1040 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1041 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1042 HCLGE_CFG_TQP_DESC_N_M,
1043 HCLGE_CFG_TQP_DESC_N_S);
1044
1045 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1046 HCLGE_CFG_PHY_ADDR_M,
1047 HCLGE_CFG_PHY_ADDR_S);
1048 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1049 HCLGE_CFG_MEDIA_TP_M,
1050 HCLGE_CFG_MEDIA_TP_S);
1051 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1052 HCLGE_CFG_RX_BUF_LEN_M,
1053 HCLGE_CFG_RX_BUF_LEN_S);
1054 /* get mac_address */
1055 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1056 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1057 HCLGE_CFG_MAC_ADDR_H_M,
1058 HCLGE_CFG_MAC_ADDR_H_S);
1059
1060 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1061
1062 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1063 HCLGE_CFG_DEFAULT_SPEED_M,
1064 HCLGE_CFG_DEFAULT_SPEED_S);
1065 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1066 HCLGE_CFG_RSS_SIZE_M,
1067 HCLGE_CFG_RSS_SIZE_S);
1068
1069 for (i = 0; i < ETH_ALEN; i++)
1070 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1071
1072 req = (struct hclge_cfg_param_cmd *)desc[1].data;
1073 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1074
1075 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1076 HCLGE_CFG_SPEED_ABILITY_M,
1077 HCLGE_CFG_SPEED_ABILITY_S);
1078 }
1079
1080 /* hclge_get_cfg: query the static parameter from flash
1081 * @hdev: pointer to struct hclge_dev
1082 * @hcfg: the config structure to be getted
1083 */
1084 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1085 {
1086 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1087 struct hclge_cfg_param_cmd *req;
1088 int i, ret;
1089
1090 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1091 u32 offset = 0;
1092
1093 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1094 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1095 true);
1096 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1097 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1098 /* Len should be united by 4 bytes when send to hardware */
1099 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1100 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1101 req->offset = cpu_to_le32(offset);
1102 }
1103
1104 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1105 if (ret) {
1106 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1107 return ret;
1108 }
1109
1110 hclge_parse_cfg(hcfg, desc);
1111
1112 return 0;
1113 }
1114
1115 static int hclge_get_cap(struct hclge_dev *hdev)
1116 {
1117 int ret;
1118
1119 ret = hclge_query_function_status(hdev);
1120 if (ret) {
1121 dev_err(&hdev->pdev->dev,
1122 "query function status error %d.\n", ret);
1123 return ret;
1124 }
1125
1126 /* get pf resource */
1127 ret = hclge_query_pf_resource(hdev);
1128 if (ret)
1129 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
1130
1131 return ret;
1132 }
1133
1134 static int hclge_configure(struct hclge_dev *hdev)
1135 {
1136 struct hclge_cfg cfg;
1137 int ret, i;
1138
1139 ret = hclge_get_cfg(hdev, &cfg);
1140 if (ret) {
1141 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1142 return ret;
1143 }
1144
1145 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1146 hdev->base_tqp_pid = 0;
1147 hdev->rss_size_max = cfg.rss_size_max;
1148 hdev->rx_buf_len = cfg.rx_buf_len;
1149 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1150 hdev->hw.mac.media_type = cfg.media_type;
1151 hdev->hw.mac.phy_addr = cfg.phy_addr;
1152 hdev->num_desc = cfg.tqp_desc_num;
1153 hdev->tm_info.num_pg = 1;
1154 hdev->tc_max = cfg.tc_num;
1155 hdev->tm_info.hw_pfc_map = 0;
1156
1157 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1158 if (ret) {
1159 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1160 return ret;
1161 }
1162
1163 hclge_parse_link_mode(hdev, cfg.speed_ability);
1164
1165 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1166 (hdev->tc_max < 1)) {
1167 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1168 hdev->tc_max);
1169 hdev->tc_max = 1;
1170 }
1171
1172 /* Dev does not support DCB */
1173 if (!hnae3_dev_dcb_supported(hdev)) {
1174 hdev->tc_max = 1;
1175 hdev->pfc_max = 0;
1176 } else {
1177 hdev->pfc_max = hdev->tc_max;
1178 }
1179
1180 hdev->tm_info.num_tc = hdev->tc_max;
1181
1182 /* Currently not support uncontiuous tc */
1183 for (i = 0; i < hdev->tm_info.num_tc; i++)
1184 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1185
1186 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1187
1188 return ret;
1189 }
1190
1191 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1192 int tso_mss_max)
1193 {
1194 struct hclge_cfg_tso_status_cmd *req;
1195 struct hclge_desc desc;
1196 u16 tso_mss;
1197
1198 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1199
1200 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1201
1202 tso_mss = 0;
1203 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1204 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1205 req->tso_mss_min = cpu_to_le16(tso_mss);
1206
1207 tso_mss = 0;
1208 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1209 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1210 req->tso_mss_max = cpu_to_le16(tso_mss);
1211
1212 return hclge_cmd_send(&hdev->hw, &desc, 1);
1213 }
1214
1215 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1216 {
1217 struct hclge_tqp *tqp;
1218 int i;
1219
1220 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1221 sizeof(struct hclge_tqp), GFP_KERNEL);
1222 if (!hdev->htqp)
1223 return -ENOMEM;
1224
1225 tqp = hdev->htqp;
1226
1227 for (i = 0; i < hdev->num_tqps; i++) {
1228 tqp->dev = &hdev->pdev->dev;
1229 tqp->index = i;
1230
1231 tqp->q.ae_algo = &ae_algo;
1232 tqp->q.buf_size = hdev->rx_buf_len;
1233 tqp->q.desc_num = hdev->num_desc;
1234 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1235 i * HCLGE_TQP_REG_SIZE;
1236
1237 tqp++;
1238 }
1239
1240 return 0;
1241 }
1242
1243 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1244 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1245 {
1246 struct hclge_tqp_map_cmd *req;
1247 struct hclge_desc desc;
1248 int ret;
1249
1250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1251
1252 req = (struct hclge_tqp_map_cmd *)desc.data;
1253 req->tqp_id = cpu_to_le16(tqp_pid);
1254 req->tqp_vf = func_id;
1255 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1256 1 << HCLGE_TQP_MAP_EN_B;
1257 req->tqp_vid = cpu_to_le16(tqp_vid);
1258
1259 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1260 if (ret)
1261 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1262
1263 return ret;
1264 }
1265
1266 static int hclge_assign_tqp(struct hclge_vport *vport,
1267 struct hnae3_queue **tqp, u16 num_tqps)
1268 {
1269 struct hclge_dev *hdev = vport->back;
1270 int i, alloced;
1271
1272 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1273 alloced < num_tqps; i++) {
1274 if (!hdev->htqp[i].alloced) {
1275 hdev->htqp[i].q.handle = &vport->nic;
1276 hdev->htqp[i].q.tqp_index = alloced;
1277 tqp[alloced] = &hdev->htqp[i].q;
1278 hdev->htqp[i].alloced = true;
1279 alloced++;
1280 }
1281 }
1282 vport->alloc_tqps = num_tqps;
1283
1284 return 0;
1285 }
1286
1287 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1288 {
1289 struct hnae3_handle *nic = &vport->nic;
1290 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1291 struct hclge_dev *hdev = vport->back;
1292 int i, ret;
1293
1294 kinfo->num_desc = hdev->num_desc;
1295 kinfo->rx_buf_len = hdev->rx_buf_len;
1296 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1297 kinfo->rss_size
1298 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1299 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1300
1301 for (i = 0; i < HNAE3_MAX_TC; i++) {
1302 if (hdev->hw_tc_map & BIT(i)) {
1303 kinfo->tc_info[i].enable = true;
1304 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1305 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1306 kinfo->tc_info[i].tc = i;
1307 } else {
1308 /* Set to default queue if TC is disable */
1309 kinfo->tc_info[i].enable = false;
1310 kinfo->tc_info[i].tqp_offset = 0;
1311 kinfo->tc_info[i].tqp_count = 1;
1312 kinfo->tc_info[i].tc = 0;
1313 }
1314 }
1315
1316 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1317 sizeof(struct hnae3_queue *), GFP_KERNEL);
1318 if (!kinfo->tqp)
1319 return -ENOMEM;
1320
1321 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1322 if (ret)
1323 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1324
1325 return ret;
1326 }
1327
1328 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1329 struct hclge_vport *vport)
1330 {
1331 struct hnae3_handle *nic = &vport->nic;
1332 struct hnae3_knic_private_info *kinfo;
1333 u16 i;
1334
1335 kinfo = &nic->kinfo;
1336 for (i = 0; i < kinfo->num_tqps; i++) {
1337 struct hclge_tqp *q =
1338 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1339 bool is_pf;
1340 int ret;
1341
1342 is_pf = !(vport->vport_id);
1343 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1344 i, is_pf);
1345 if (ret)
1346 return ret;
1347 }
1348
1349 return 0;
1350 }
1351
1352 static int hclge_map_tqp(struct hclge_dev *hdev)
1353 {
1354 struct hclge_vport *vport = hdev->vport;
1355 u16 i, num_vport;
1356
1357 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1358 for (i = 0; i < num_vport; i++) {
1359 int ret;
1360
1361 ret = hclge_map_tqp_to_vport(hdev, vport);
1362 if (ret)
1363 return ret;
1364
1365 vport++;
1366 }
1367
1368 return 0;
1369 }
1370
1371 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1372 {
1373 /* this would be initialized later */
1374 }
1375
1376 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1377 {
1378 struct hnae3_handle *nic = &vport->nic;
1379 struct hclge_dev *hdev = vport->back;
1380 int ret;
1381
1382 nic->pdev = hdev->pdev;
1383 nic->ae_algo = &ae_algo;
1384 nic->numa_node_mask = hdev->numa_node_mask;
1385
1386 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1387 ret = hclge_knic_setup(vport, num_tqps);
1388 if (ret) {
1389 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1390 ret);
1391 return ret;
1392 }
1393 } else {
1394 hclge_unic_setup(vport, num_tqps);
1395 }
1396
1397 return 0;
1398 }
1399
1400 static int hclge_alloc_vport(struct hclge_dev *hdev)
1401 {
1402 struct pci_dev *pdev = hdev->pdev;
1403 struct hclge_vport *vport;
1404 u32 tqp_main_vport;
1405 u32 tqp_per_vport;
1406 int num_vport, i;
1407 int ret;
1408
1409 /* We need to alloc a vport for main NIC of PF */
1410 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1411
1412 if (hdev->num_tqps < num_vport) {
1413 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1414 hdev->num_tqps, num_vport);
1415 return -EINVAL;
1416 }
1417
1418 /* Alloc the same number of TQPs for every vport */
1419 tqp_per_vport = hdev->num_tqps / num_vport;
1420 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1421
1422 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1423 GFP_KERNEL);
1424 if (!vport)
1425 return -ENOMEM;
1426
1427 hdev->vport = vport;
1428 hdev->num_alloc_vport = num_vport;
1429
1430 if (IS_ENABLED(CONFIG_PCI_IOV))
1431 hdev->num_alloc_vfs = hdev->num_req_vfs;
1432
1433 for (i = 0; i < num_vport; i++) {
1434 vport->back = hdev;
1435 vport->vport_id = i;
1436
1437 if (i == 0)
1438 ret = hclge_vport_setup(vport, tqp_main_vport);
1439 else
1440 ret = hclge_vport_setup(vport, tqp_per_vport);
1441 if (ret) {
1442 dev_err(&pdev->dev,
1443 "vport setup failed for vport %d, %d\n",
1444 i, ret);
1445 return ret;
1446 }
1447
1448 vport++;
1449 }
1450
1451 return 0;
1452 }
1453
1454 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1455 struct hclge_pkt_buf_alloc *buf_alloc)
1456 {
1457 /* TX buffer size is unit by 128 byte */
1458 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1459 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1460 struct hclge_tx_buff_alloc_cmd *req;
1461 struct hclge_desc desc;
1462 int ret;
1463 u8 i;
1464
1465 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1466
1467 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1468 for (i = 0; i < HCLGE_TC_NUM; i++) {
1469 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1470
1471 req->tx_pkt_buff[i] =
1472 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1473 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1474 }
1475
1476 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1477 if (ret)
1478 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1479 ret);
1480
1481 return ret;
1482 }
1483
1484 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1485 struct hclge_pkt_buf_alloc *buf_alloc)
1486 {
1487 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1488
1489 if (ret)
1490 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1491
1492 return ret;
1493 }
1494
1495 static int hclge_get_tc_num(struct hclge_dev *hdev)
1496 {
1497 int i, cnt = 0;
1498
1499 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1500 if (hdev->hw_tc_map & BIT(i))
1501 cnt++;
1502 return cnt;
1503 }
1504
1505 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1506 {
1507 int i, cnt = 0;
1508
1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1510 if (hdev->hw_tc_map & BIT(i) &&
1511 hdev->tm_info.hw_pfc_map & BIT(i))
1512 cnt++;
1513 return cnt;
1514 }
1515
1516 /* Get the number of pfc enabled TCs, which have private buffer */
1517 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1518 struct hclge_pkt_buf_alloc *buf_alloc)
1519 {
1520 struct hclge_priv_buf *priv;
1521 int i, cnt = 0;
1522
1523 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1524 priv = &buf_alloc->priv_buf[i];
1525 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1526 priv->enable)
1527 cnt++;
1528 }
1529
1530 return cnt;
1531 }
1532
1533 /* Get the number of pfc disabled TCs, which have private buffer */
1534 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1535 struct hclge_pkt_buf_alloc *buf_alloc)
1536 {
1537 struct hclge_priv_buf *priv;
1538 int i, cnt = 0;
1539
1540 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1541 priv = &buf_alloc->priv_buf[i];
1542 if (hdev->hw_tc_map & BIT(i) &&
1543 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1544 priv->enable)
1545 cnt++;
1546 }
1547
1548 return cnt;
1549 }
1550
1551 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1552 {
1553 struct hclge_priv_buf *priv;
1554 u32 rx_priv = 0;
1555 int i;
1556
1557 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1558 priv = &buf_alloc->priv_buf[i];
1559 if (priv->enable)
1560 rx_priv += priv->buf_size;
1561 }
1562 return rx_priv;
1563 }
1564
1565 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1566 {
1567 u32 i, total_tx_size = 0;
1568
1569 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1570 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1571
1572 return total_tx_size;
1573 }
1574
1575 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1576 struct hclge_pkt_buf_alloc *buf_alloc,
1577 u32 rx_all)
1578 {
1579 u32 shared_buf_min, shared_buf_tc, shared_std;
1580 int tc_num, pfc_enable_num;
1581 u32 shared_buf;
1582 u32 rx_priv;
1583 int i;
1584
1585 tc_num = hclge_get_tc_num(hdev);
1586 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1587
1588 if (hnae3_dev_dcb_supported(hdev))
1589 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1590 else
1591 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1592
1593 shared_buf_tc = pfc_enable_num * hdev->mps +
1594 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1595 hdev->mps;
1596 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1597
1598 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1599 if (rx_all <= rx_priv + shared_std)
1600 return false;
1601
1602 shared_buf = rx_all - rx_priv;
1603 buf_alloc->s_buf.buf_size = shared_buf;
1604 buf_alloc->s_buf.self.high = shared_buf;
1605 buf_alloc->s_buf.self.low = 2 * hdev->mps;
1606
1607 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1608 if ((hdev->hw_tc_map & BIT(i)) &&
1609 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1610 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1611 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1612 } else {
1613 buf_alloc->s_buf.tc_thrd[i].low = 0;
1614 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1615 }
1616 }
1617
1618 return true;
1619 }
1620
1621 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1622 struct hclge_pkt_buf_alloc *buf_alloc)
1623 {
1624 u32 i, total_size;
1625
1626 total_size = hdev->pkt_buf_size;
1627
1628 /* alloc tx buffer for all enabled tc */
1629 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1630 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1631
1632 if (total_size < HCLGE_DEFAULT_TX_BUF)
1633 return -ENOMEM;
1634
1635 if (hdev->hw_tc_map & BIT(i))
1636 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1637 else
1638 priv->tx_buf_size = 0;
1639
1640 total_size -= priv->tx_buf_size;
1641 }
1642
1643 return 0;
1644 }
1645
1646 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1647 * @hdev: pointer to struct hclge_dev
1648 * @buf_alloc: pointer to buffer calculation data
1649 * @return: 0: calculate sucessful, negative: fail
1650 */
1651 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1652 struct hclge_pkt_buf_alloc *buf_alloc)
1653 {
1654 u32 rx_all = hdev->pkt_buf_size;
1655 int no_pfc_priv_num, pfc_priv_num;
1656 struct hclge_priv_buf *priv;
1657 int i;
1658
1659 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1660
1661 /* When DCB is not supported, rx private
1662 * buffer is not allocated.
1663 */
1664 if (!hnae3_dev_dcb_supported(hdev)) {
1665 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1666 return -ENOMEM;
1667
1668 return 0;
1669 }
1670
1671 /* step 1, try to alloc private buffer for all enabled tc */
1672 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1673 priv = &buf_alloc->priv_buf[i];
1674 if (hdev->hw_tc_map & BIT(i)) {
1675 priv->enable = 1;
1676 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1677 priv->wl.low = hdev->mps;
1678 priv->wl.high = priv->wl.low + hdev->mps;
1679 priv->buf_size = priv->wl.high +
1680 HCLGE_DEFAULT_DV;
1681 } else {
1682 priv->wl.low = 0;
1683 priv->wl.high = 2 * hdev->mps;
1684 priv->buf_size = priv->wl.high;
1685 }
1686 } else {
1687 priv->enable = 0;
1688 priv->wl.low = 0;
1689 priv->wl.high = 0;
1690 priv->buf_size = 0;
1691 }
1692 }
1693
1694 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1695 return 0;
1696
1697 /* step 2, try to decrease the buffer size of
1698 * no pfc TC's private buffer
1699 */
1700 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1701 priv = &buf_alloc->priv_buf[i];
1702
1703 priv->enable = 0;
1704 priv->wl.low = 0;
1705 priv->wl.high = 0;
1706 priv->buf_size = 0;
1707
1708 if (!(hdev->hw_tc_map & BIT(i)))
1709 continue;
1710
1711 priv->enable = 1;
1712
1713 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1714 priv->wl.low = 128;
1715 priv->wl.high = priv->wl.low + hdev->mps;
1716 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1717 } else {
1718 priv->wl.low = 0;
1719 priv->wl.high = hdev->mps;
1720 priv->buf_size = priv->wl.high;
1721 }
1722 }
1723
1724 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1725 return 0;
1726
1727 /* step 3, try to reduce the number of pfc disabled TCs,
1728 * which have private buffer
1729 */
1730 /* get the total no pfc enable TC number, which have private buffer */
1731 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1732
1733 /* let the last to be cleared first */
1734 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1735 priv = &buf_alloc->priv_buf[i];
1736
1737 if (hdev->hw_tc_map & BIT(i) &&
1738 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1739 /* Clear the no pfc TC private buffer */
1740 priv->wl.low = 0;
1741 priv->wl.high = 0;
1742 priv->buf_size = 0;
1743 priv->enable = 0;
1744 no_pfc_priv_num--;
1745 }
1746
1747 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1748 no_pfc_priv_num == 0)
1749 break;
1750 }
1751
1752 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1753 return 0;
1754
1755 /* step 4, try to reduce the number of pfc enabled TCs
1756 * which have private buffer.
1757 */
1758 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1759
1760 /* let the last to be cleared first */
1761 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1762 priv = &buf_alloc->priv_buf[i];
1763
1764 if (hdev->hw_tc_map & BIT(i) &&
1765 hdev->tm_info.hw_pfc_map & BIT(i)) {
1766 /* Reduce the number of pfc TC with private buffer */
1767 priv->wl.low = 0;
1768 priv->enable = 0;
1769 priv->wl.high = 0;
1770 priv->buf_size = 0;
1771 pfc_priv_num--;
1772 }
1773
1774 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1775 pfc_priv_num == 0)
1776 break;
1777 }
1778 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1779 return 0;
1780
1781 return -ENOMEM;
1782 }
1783
1784 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1785 struct hclge_pkt_buf_alloc *buf_alloc)
1786 {
1787 struct hclge_rx_priv_buff_cmd *req;
1788 struct hclge_desc desc;
1789 int ret;
1790 int i;
1791
1792 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1793 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1794
1795 /* Alloc private buffer TCs */
1796 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1797 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1798
1799 req->buf_num[i] =
1800 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1801 req->buf_num[i] |=
1802 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1803 }
1804
1805 req->shared_buf =
1806 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1807 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1808
1809 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1810 if (ret)
1811 dev_err(&hdev->pdev->dev,
1812 "rx private buffer alloc cmd failed %d\n", ret);
1813
1814 return ret;
1815 }
1816
1817 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1818
1819 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1820 struct hclge_pkt_buf_alloc *buf_alloc)
1821 {
1822 struct hclge_rx_priv_wl_buf *req;
1823 struct hclge_priv_buf *priv;
1824 struct hclge_desc desc[2];
1825 int i, j;
1826 int ret;
1827
1828 for (i = 0; i < 2; i++) {
1829 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1830 false);
1831 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1832
1833 /* The first descriptor set the NEXT bit to 1 */
1834 if (i == 0)
1835 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1836 else
1837 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1838
1839 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1840 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1841
1842 priv = &buf_alloc->priv_buf[idx];
1843 req->tc_wl[j].high =
1844 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1845 req->tc_wl[j].high |=
1846 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1847 HCLGE_RX_PRIV_EN_B);
1848 req->tc_wl[j].low =
1849 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1850 req->tc_wl[j].low |=
1851 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1852 HCLGE_RX_PRIV_EN_B);
1853 }
1854 }
1855
1856 /* Send 2 descriptor at one time */
1857 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1858 if (ret)
1859 dev_err(&hdev->pdev->dev,
1860 "rx private waterline config cmd failed %d\n",
1861 ret);
1862 return ret;
1863 }
1864
1865 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1866 struct hclge_pkt_buf_alloc *buf_alloc)
1867 {
1868 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1869 struct hclge_rx_com_thrd *req;
1870 struct hclge_desc desc[2];
1871 struct hclge_tc_thrd *tc;
1872 int i, j;
1873 int ret;
1874
1875 for (i = 0; i < 2; i++) {
1876 hclge_cmd_setup_basic_desc(&desc[i],
1877 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1878 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1879
1880 /* The first descriptor set the NEXT bit to 1 */
1881 if (i == 0)
1882 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1883 else
1884 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1885
1886 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1887 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1888
1889 req->com_thrd[j].high =
1890 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1891 req->com_thrd[j].high |=
1892 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1893 HCLGE_RX_PRIV_EN_B);
1894 req->com_thrd[j].low =
1895 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1896 req->com_thrd[j].low |=
1897 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1898 HCLGE_RX_PRIV_EN_B);
1899 }
1900 }
1901
1902 /* Send 2 descriptors at one time */
1903 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1904 if (ret)
1905 dev_err(&hdev->pdev->dev,
1906 "common threshold config cmd failed %d\n", ret);
1907 return ret;
1908 }
1909
1910 static int hclge_common_wl_config(struct hclge_dev *hdev,
1911 struct hclge_pkt_buf_alloc *buf_alloc)
1912 {
1913 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1914 struct hclge_rx_com_wl *req;
1915 struct hclge_desc desc;
1916 int ret;
1917
1918 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1919
1920 req = (struct hclge_rx_com_wl *)desc.data;
1921 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1922 req->com_wl.high |=
1923 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1924 HCLGE_RX_PRIV_EN_B);
1925
1926 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1927 req->com_wl.low |=
1928 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1929 HCLGE_RX_PRIV_EN_B);
1930
1931 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1932 if (ret)
1933 dev_err(&hdev->pdev->dev,
1934 "common waterline config cmd failed %d\n", ret);
1935 return ret;
1936 }
1937
1938 int hclge_buffer_alloc(struct hclge_dev *hdev)
1939 {
1940 struct hclge_pkt_buf_alloc *pkt_buf;
1941 int ret;
1942
1943 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1944 if (!pkt_buf)
1945 return -ENOMEM;
1946
1947 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1948 if (ret) {
1949 dev_err(&hdev->pdev->dev,
1950 "could not calc tx buffer size for all TCs %d\n", ret);
1951 goto out;
1952 }
1953
1954 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1955 if (ret) {
1956 dev_err(&hdev->pdev->dev,
1957 "could not alloc tx buffers %d\n", ret);
1958 goto out;
1959 }
1960
1961 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1962 if (ret) {
1963 dev_err(&hdev->pdev->dev,
1964 "could not calc rx priv buffer size for all TCs %d\n",
1965 ret);
1966 goto out;
1967 }
1968
1969 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1970 if (ret) {
1971 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1972 ret);
1973 goto out;
1974 }
1975
1976 if (hnae3_dev_dcb_supported(hdev)) {
1977 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1978 if (ret) {
1979 dev_err(&hdev->pdev->dev,
1980 "could not configure rx private waterline %d\n",
1981 ret);
1982 goto out;
1983 }
1984
1985 ret = hclge_common_thrd_config(hdev, pkt_buf);
1986 if (ret) {
1987 dev_err(&hdev->pdev->dev,
1988 "could not configure common threshold %d\n",
1989 ret);
1990 goto out;
1991 }
1992 }
1993
1994 ret = hclge_common_wl_config(hdev, pkt_buf);
1995 if (ret)
1996 dev_err(&hdev->pdev->dev,
1997 "could not configure common waterline %d\n", ret);
1998
1999 out:
2000 kfree(pkt_buf);
2001 return ret;
2002 }
2003
2004 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2005 {
2006 struct hnae3_handle *roce = &vport->roce;
2007 struct hnae3_handle *nic = &vport->nic;
2008
2009 roce->rinfo.num_vectors = vport->back->num_roce_msi;
2010
2011 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2012 vport->back->num_msi_left == 0)
2013 return -EINVAL;
2014
2015 roce->rinfo.base_vector = vport->back->roce_base_vector;
2016
2017 roce->rinfo.netdev = nic->kinfo.netdev;
2018 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2019
2020 roce->pdev = nic->pdev;
2021 roce->ae_algo = nic->ae_algo;
2022 roce->numa_node_mask = nic->numa_node_mask;
2023
2024 return 0;
2025 }
2026
2027 static int hclge_init_msi(struct hclge_dev *hdev)
2028 {
2029 struct pci_dev *pdev = hdev->pdev;
2030 int vectors;
2031 int i;
2032
2033 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2034 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2035 if (vectors < 0) {
2036 dev_err(&pdev->dev,
2037 "failed(%d) to allocate MSI/MSI-X vectors\n",
2038 vectors);
2039 return vectors;
2040 }
2041 if (vectors < hdev->num_msi)
2042 dev_warn(&hdev->pdev->dev,
2043 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2044 hdev->num_msi, vectors);
2045
2046 hdev->num_msi = vectors;
2047 hdev->num_msi_left = vectors;
2048 hdev->base_msi_vector = pdev->irq;
2049 hdev->roce_base_vector = hdev->base_msi_vector +
2050 HCLGE_ROCE_VECTOR_OFFSET;
2051
2052 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2053 sizeof(u16), GFP_KERNEL);
2054 if (!hdev->vector_status) {
2055 pci_free_irq_vectors(pdev);
2056 return -ENOMEM;
2057 }
2058
2059 for (i = 0; i < hdev->num_msi; i++)
2060 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2061
2062 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2063 sizeof(int), GFP_KERNEL);
2064 if (!hdev->vector_irq) {
2065 pci_free_irq_vectors(pdev);
2066 return -ENOMEM;
2067 }
2068
2069 return 0;
2070 }
2071
2072 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2073 {
2074 struct hclge_mac *mac = &hdev->hw.mac;
2075
2076 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2077 mac->duplex = (u8)duplex;
2078 else
2079 mac->duplex = HCLGE_MAC_FULL;
2080
2081 mac->speed = speed;
2082 }
2083
2084 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2085 {
2086 struct hclge_config_mac_speed_dup_cmd *req;
2087 struct hclge_desc desc;
2088 int ret;
2089
2090 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2091
2092 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2093
2094 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2095
2096 switch (speed) {
2097 case HCLGE_MAC_SPEED_10M:
2098 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2099 HCLGE_CFG_SPEED_S, 6);
2100 break;
2101 case HCLGE_MAC_SPEED_100M:
2102 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2103 HCLGE_CFG_SPEED_S, 7);
2104 break;
2105 case HCLGE_MAC_SPEED_1G:
2106 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2107 HCLGE_CFG_SPEED_S, 0);
2108 break;
2109 case HCLGE_MAC_SPEED_10G:
2110 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2111 HCLGE_CFG_SPEED_S, 1);
2112 break;
2113 case HCLGE_MAC_SPEED_25G:
2114 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2115 HCLGE_CFG_SPEED_S, 2);
2116 break;
2117 case HCLGE_MAC_SPEED_40G:
2118 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2119 HCLGE_CFG_SPEED_S, 3);
2120 break;
2121 case HCLGE_MAC_SPEED_50G:
2122 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2123 HCLGE_CFG_SPEED_S, 4);
2124 break;
2125 case HCLGE_MAC_SPEED_100G:
2126 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2127 HCLGE_CFG_SPEED_S, 5);
2128 break;
2129 default:
2130 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2131 return -EINVAL;
2132 }
2133
2134 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2135 1);
2136
2137 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2138 if (ret) {
2139 dev_err(&hdev->pdev->dev,
2140 "mac speed/duplex config cmd failed %d.\n", ret);
2141 return ret;
2142 }
2143
2144 hclge_check_speed_dup(hdev, duplex, speed);
2145
2146 return 0;
2147 }
2148
2149 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2150 u8 duplex)
2151 {
2152 struct hclge_vport *vport = hclge_get_vport(handle);
2153 struct hclge_dev *hdev = vport->back;
2154
2155 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2156 }
2157
2158 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2159 u8 *duplex)
2160 {
2161 struct hclge_query_an_speed_dup_cmd *req;
2162 struct hclge_desc desc;
2163 int speed_tmp;
2164 int ret;
2165
2166 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2167
2168 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2169 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2170 if (ret) {
2171 dev_err(&hdev->pdev->dev,
2172 "mac speed/autoneg/duplex query cmd failed %d\n",
2173 ret);
2174 return ret;
2175 }
2176
2177 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2178 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2179 HCLGE_QUERY_SPEED_S);
2180
2181 ret = hclge_parse_speed(speed_tmp, speed);
2182 if (ret)
2183 dev_err(&hdev->pdev->dev,
2184 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2185
2186 return ret;
2187 }
2188
2189 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2190 {
2191 struct hclge_config_auto_neg_cmd *req;
2192 struct hclge_desc desc;
2193 u32 flag = 0;
2194 int ret;
2195
2196 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2197
2198 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2199 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2200 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2201
2202 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2203 if (ret)
2204 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2205 ret);
2206
2207 return ret;
2208 }
2209
2210 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2211 {
2212 struct hclge_vport *vport = hclge_get_vport(handle);
2213 struct hclge_dev *hdev = vport->back;
2214
2215 return hclge_set_autoneg_en(hdev, enable);
2216 }
2217
2218 static int hclge_get_autoneg(struct hnae3_handle *handle)
2219 {
2220 struct hclge_vport *vport = hclge_get_vport(handle);
2221 struct hclge_dev *hdev = vport->back;
2222 struct phy_device *phydev = hdev->hw.mac.phydev;
2223
2224 if (phydev)
2225 return phydev->autoneg;
2226
2227 return hdev->hw.mac.autoneg;
2228 }
2229
2230 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2231 bool mask_vlan,
2232 u8 *mac_mask)
2233 {
2234 struct hclge_mac_vlan_mask_entry_cmd *req;
2235 struct hclge_desc desc;
2236 int status;
2237
2238 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2239 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2240
2241 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2242 mask_vlan ? 1 : 0);
2243 ether_addr_copy(req->mac_mask, mac_mask);
2244
2245 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2246 if (status)
2247 dev_err(&hdev->pdev->dev,
2248 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2249 status);
2250
2251 return status;
2252 }
2253
2254 static int hclge_mac_init(struct hclge_dev *hdev)
2255 {
2256 struct hnae3_handle *handle = &hdev->vport[0].nic;
2257 struct net_device *netdev = handle->kinfo.netdev;
2258 struct hclge_mac *mac = &hdev->hw.mac;
2259 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2260 struct hclge_vport *vport;
2261 int mtu;
2262 int ret;
2263 int i;
2264
2265 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2266 if (ret) {
2267 dev_err(&hdev->pdev->dev,
2268 "Config mac speed dup fail ret=%d\n", ret);
2269 return ret;
2270 }
2271
2272 mac->link = 0;
2273
2274 /* Initialize the MTA table work mode */
2275 hdev->enable_mta = true;
2276 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2277
2278 ret = hclge_set_mta_filter_mode(hdev,
2279 hdev->mta_mac_sel_type,
2280 hdev->enable_mta);
2281 if (ret) {
2282 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2283 ret);
2284 return ret;
2285 }
2286
2287 for (i = 0; i < hdev->num_alloc_vport; i++) {
2288 vport = &hdev->vport[i];
2289 vport->accept_mta_mc = false;
2290
2291 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2292 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2293 if (ret) {
2294 dev_err(&hdev->pdev->dev,
2295 "set mta filter mode fail ret=%d\n", ret);
2296 return ret;
2297 }
2298 }
2299
2300 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2301 if (ret) {
2302 dev_err(&hdev->pdev->dev,
2303 "set default mac_vlan_mask fail ret=%d\n", ret);
2304 return ret;
2305 }
2306
2307 if (netdev)
2308 mtu = netdev->mtu;
2309 else
2310 mtu = ETH_DATA_LEN;
2311
2312 ret = hclge_set_mtu(handle, mtu);
2313 if (ret)
2314 dev_err(&hdev->pdev->dev,
2315 "set mtu failed ret=%d\n", ret);
2316
2317 return ret;
2318 }
2319
2320 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2321 {
2322 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2323 schedule_work(&hdev->mbx_service_task);
2324 }
2325
2326 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2327 {
2328 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2329 schedule_work(&hdev->rst_service_task);
2330 }
2331
2332 static void hclge_task_schedule(struct hclge_dev *hdev)
2333 {
2334 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2335 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2336 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2337 (void)schedule_work(&hdev->service_task);
2338 }
2339
2340 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2341 {
2342 struct hclge_link_status_cmd *req;
2343 struct hclge_desc desc;
2344 int link_status;
2345 int ret;
2346
2347 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2348 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2349 if (ret) {
2350 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2351 ret);
2352 return ret;
2353 }
2354
2355 req = (struct hclge_link_status_cmd *)desc.data;
2356 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2357
2358 return !!link_status;
2359 }
2360
2361 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2362 {
2363 int mac_state;
2364 int link_stat;
2365
2366 mac_state = hclge_get_mac_link_status(hdev);
2367
2368 if (hdev->hw.mac.phydev) {
2369 if (!genphy_read_status(hdev->hw.mac.phydev))
2370 link_stat = mac_state &
2371 hdev->hw.mac.phydev->link;
2372 else
2373 link_stat = 0;
2374
2375 } else {
2376 link_stat = mac_state;
2377 }
2378
2379 return !!link_stat;
2380 }
2381
2382 static void hclge_update_link_status(struct hclge_dev *hdev)
2383 {
2384 struct hnae3_client *rclient = hdev->roce_client;
2385 struct hnae3_client *client = hdev->nic_client;
2386 struct hnae3_handle *handle;
2387 int state;
2388 int i;
2389
2390 if (!client)
2391 return;
2392 state = hclge_get_mac_phy_link(hdev);
2393 if (state != hdev->hw.mac.link) {
2394 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2395 handle = &hdev->vport[i].nic;
2396 client->ops->link_status_change(handle, state);
2397 if (rclient && rclient->ops->link_status_change)
2398 rclient->ops->link_status_change(handle, state);
2399 }
2400 hdev->hw.mac.link = state;
2401 }
2402 }
2403
2404 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2405 {
2406 struct hclge_mac mac = hdev->hw.mac;
2407 u8 duplex;
2408 int speed;
2409 int ret;
2410
2411 /* get the speed and duplex as autoneg'result from mac cmd when phy
2412 * doesn't exit.
2413 */
2414 if (mac.phydev || !mac.autoneg)
2415 return 0;
2416
2417 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2418 if (ret) {
2419 dev_err(&hdev->pdev->dev,
2420 "mac autoneg/speed/duplex query failed %d\n", ret);
2421 return ret;
2422 }
2423
2424 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2425 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2426 if (ret) {
2427 dev_err(&hdev->pdev->dev,
2428 "mac speed/duplex config failed %d\n", ret);
2429 return ret;
2430 }
2431 }
2432
2433 return 0;
2434 }
2435
2436 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2437 {
2438 struct hclge_vport *vport = hclge_get_vport(handle);
2439 struct hclge_dev *hdev = vport->back;
2440
2441 return hclge_update_speed_duplex(hdev);
2442 }
2443
2444 static int hclge_get_status(struct hnae3_handle *handle)
2445 {
2446 struct hclge_vport *vport = hclge_get_vport(handle);
2447 struct hclge_dev *hdev = vport->back;
2448
2449 hclge_update_link_status(hdev);
2450
2451 return hdev->hw.mac.link;
2452 }
2453
2454 static void hclge_service_timer(struct timer_list *t)
2455 {
2456 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2457
2458 mod_timer(&hdev->service_timer, jiffies + HZ);
2459 hdev->hw_stats.stats_timer++;
2460 hclge_task_schedule(hdev);
2461 }
2462
2463 static void hclge_service_complete(struct hclge_dev *hdev)
2464 {
2465 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2466
2467 /* Flush memory before next watchdog */
2468 smp_mb__before_atomic();
2469 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2470 }
2471
2472 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2473 {
2474 u32 rst_src_reg;
2475 u32 cmdq_src_reg;
2476
2477 /* fetch the events from their corresponding regs */
2478 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2479 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2480
2481 /* Assumption: If by any chance reset and mailbox events are reported
2482 * together then we will only process reset event in this go and will
2483 * defer the processing of the mailbox events. Since, we would have not
2484 * cleared RX CMDQ event this time we would receive again another
2485 * interrupt from H/W just for the mailbox.
2486 */
2487
2488 /* check for vector0 reset event sources */
2489 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2490 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2491 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2492 return HCLGE_VECTOR0_EVENT_RST;
2493 }
2494
2495 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2496 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2497 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2498 return HCLGE_VECTOR0_EVENT_RST;
2499 }
2500
2501 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2502 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2503 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2504 return HCLGE_VECTOR0_EVENT_RST;
2505 }
2506
2507 /* check for vector0 mailbox(=CMDQ RX) event source */
2508 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2509 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2510 *clearval = cmdq_src_reg;
2511 return HCLGE_VECTOR0_EVENT_MBX;
2512 }
2513
2514 return HCLGE_VECTOR0_EVENT_OTHER;
2515 }
2516
2517 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2518 u32 regclr)
2519 {
2520 switch (event_type) {
2521 case HCLGE_VECTOR0_EVENT_RST:
2522 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2523 break;
2524 case HCLGE_VECTOR0_EVENT_MBX:
2525 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2526 break;
2527 }
2528 }
2529
2530 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2531 {
2532 writel(enable ? 1 : 0, vector->addr);
2533 }
2534
2535 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2536 {
2537 struct hclge_dev *hdev = data;
2538 u32 event_cause;
2539 u32 clearval;
2540
2541 hclge_enable_vector(&hdev->misc_vector, false);
2542 event_cause = hclge_check_event_cause(hdev, &clearval);
2543
2544 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2545 switch (event_cause) {
2546 case HCLGE_VECTOR0_EVENT_RST:
2547 hclge_reset_task_schedule(hdev);
2548 break;
2549 case HCLGE_VECTOR0_EVENT_MBX:
2550 /* If we are here then,
2551 * 1. Either we are not handling any mbx task and we are not
2552 * scheduled as well
2553 * OR
2554 * 2. We could be handling a mbx task but nothing more is
2555 * scheduled.
2556 * In both cases, we should schedule mbx task as there are more
2557 * mbx messages reported by this interrupt.
2558 */
2559 hclge_mbx_task_schedule(hdev);
2560 break;
2561 default:
2562 dev_warn(&hdev->pdev->dev,
2563 "received unknown or unhandled event of vector0\n");
2564 break;
2565 }
2566
2567 /* clear the source of interrupt if it is not cause by reset */
2568 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2569 hclge_clear_event_cause(hdev, event_cause, clearval);
2570 hclge_enable_vector(&hdev->misc_vector, true);
2571 }
2572
2573 return IRQ_HANDLED;
2574 }
2575
2576 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2577 {
2578 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2579 dev_warn(&hdev->pdev->dev,
2580 "vector(vector_id %d) has been freed.\n", vector_id);
2581 return;
2582 }
2583
2584 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2585 hdev->num_msi_left += 1;
2586 hdev->num_msi_used -= 1;
2587 }
2588
2589 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2590 {
2591 struct hclge_misc_vector *vector = &hdev->misc_vector;
2592
2593 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2594
2595 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2596 hdev->vector_status[0] = 0;
2597
2598 hdev->num_msi_left -= 1;
2599 hdev->num_msi_used += 1;
2600 }
2601
2602 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2603 {
2604 int ret;
2605
2606 hclge_get_misc_vector(hdev);
2607
2608 /* this would be explicitly freed in the end */
2609 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2610 0, "hclge_misc", hdev);
2611 if (ret) {
2612 hclge_free_vector(hdev, 0);
2613 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2614 hdev->misc_vector.vector_irq);
2615 }
2616
2617 return ret;
2618 }
2619
2620 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2621 {
2622 free_irq(hdev->misc_vector.vector_irq, hdev);
2623 hclge_free_vector(hdev, 0);
2624 }
2625
2626 static int hclge_notify_client(struct hclge_dev *hdev,
2627 enum hnae3_reset_notify_type type)
2628 {
2629 struct hnae3_client *rclient = hdev->roce_client;
2630 struct hnae3_client *client = hdev->nic_client;
2631 struct hnae3_handle *handle;
2632 int ret;
2633 u16 i;
2634
2635 if (!client->ops->reset_notify)
2636 return -EOPNOTSUPP;
2637
2638 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2639 handle = &hdev->vport[i].nic;
2640 ret = client->ops->reset_notify(handle, type);
2641 if (ret) {
2642 dev_err(&hdev->pdev->dev,
2643 "notify nic client failed %d", ret);
2644 return ret;
2645 }
2646
2647 if (rclient && rclient->ops->reset_notify) {
2648 handle = &hdev->vport[i].roce;
2649 ret = rclient->ops->reset_notify(handle, type);
2650 if (ret) {
2651 dev_err(&hdev->pdev->dev,
2652 "notify roce client failed %d", ret);
2653 return ret;
2654 }
2655 }
2656 }
2657
2658 return 0;
2659 }
2660
2661 static int hclge_reset_wait(struct hclge_dev *hdev)
2662 {
2663 #define HCLGE_RESET_WATI_MS 100
2664 #define HCLGE_RESET_WAIT_CNT 5
2665 u32 val, reg, reg_bit;
2666 u32 cnt = 0;
2667
2668 switch (hdev->reset_type) {
2669 case HNAE3_GLOBAL_RESET:
2670 reg = HCLGE_GLOBAL_RESET_REG;
2671 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2672 break;
2673 case HNAE3_CORE_RESET:
2674 reg = HCLGE_GLOBAL_RESET_REG;
2675 reg_bit = HCLGE_CORE_RESET_BIT;
2676 break;
2677 case HNAE3_FUNC_RESET:
2678 reg = HCLGE_FUN_RST_ING;
2679 reg_bit = HCLGE_FUN_RST_ING_B;
2680 break;
2681 default:
2682 dev_err(&hdev->pdev->dev,
2683 "Wait for unsupported reset type: %d\n",
2684 hdev->reset_type);
2685 return -EINVAL;
2686 }
2687
2688 val = hclge_read_dev(&hdev->hw, reg);
2689 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT &&
2690 test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
2691 msleep(HCLGE_RESET_WATI_MS);
2692 val = hclge_read_dev(&hdev->hw, reg);
2693 cnt++;
2694 }
2695
2696 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2697 dev_warn(&hdev->pdev->dev,
2698 "Wait for reset timeout: %d\n", hdev->reset_type);
2699 return -EBUSY;
2700 }
2701
2702 return 0;
2703 }
2704
2705 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2706 {
2707 struct hclge_desc desc;
2708 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2709 int ret;
2710
2711 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2712 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2713 req->fun_reset_vfid = func_id;
2714
2715 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2716 if (ret)
2717 dev_err(&hdev->pdev->dev,
2718 "send function reset cmd fail, status =%d\n", ret);
2719
2720 return ret;
2721 }
2722
2723 static void hclge_do_reset(struct hclge_dev *hdev)
2724 {
2725 struct pci_dev *pdev = hdev->pdev;
2726 u32 val;
2727
2728 switch (hdev->reset_type) {
2729 case HNAE3_GLOBAL_RESET:
2730 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2731 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2732 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2733 dev_info(&pdev->dev, "Global Reset requested\n");
2734 break;
2735 case HNAE3_CORE_RESET:
2736 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2737 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2738 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2739 dev_info(&pdev->dev, "Core Reset requested\n");
2740 break;
2741 case HNAE3_FUNC_RESET:
2742 dev_info(&pdev->dev, "PF Reset requested\n");
2743 hclge_func_reset_cmd(hdev, 0);
2744 /* schedule again to check later */
2745 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2746 hclge_reset_task_schedule(hdev);
2747 break;
2748 default:
2749 dev_warn(&pdev->dev,
2750 "Unsupported reset type: %d\n", hdev->reset_type);
2751 break;
2752 }
2753 }
2754
2755 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2756 unsigned long *addr)
2757 {
2758 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2759
2760 /* return the highest priority reset level amongst all */
2761 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2762 rst_level = HNAE3_GLOBAL_RESET;
2763 else if (test_bit(HNAE3_CORE_RESET, addr))
2764 rst_level = HNAE3_CORE_RESET;
2765 else if (test_bit(HNAE3_IMP_RESET, addr))
2766 rst_level = HNAE3_IMP_RESET;
2767 else if (test_bit(HNAE3_FUNC_RESET, addr))
2768 rst_level = HNAE3_FUNC_RESET;
2769
2770 /* now, clear all other resets */
2771 clear_bit(HNAE3_GLOBAL_RESET, addr);
2772 clear_bit(HNAE3_CORE_RESET, addr);
2773 clear_bit(HNAE3_IMP_RESET, addr);
2774 clear_bit(HNAE3_FUNC_RESET, addr);
2775
2776 return rst_level;
2777 }
2778
2779 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2780 {
2781 u32 clearval = 0;
2782
2783 switch (hdev->reset_type) {
2784 case HNAE3_IMP_RESET:
2785 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2786 break;
2787 case HNAE3_GLOBAL_RESET:
2788 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2789 break;
2790 case HNAE3_CORE_RESET:
2791 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2792 break;
2793 default:
2794 dev_warn(&hdev->pdev->dev, "Unsupported reset event to clear:%d",
2795 hdev->reset_type);
2796 break;
2797 }
2798
2799 if (!clearval)
2800 return;
2801
2802 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2803 hclge_enable_vector(&hdev->misc_vector, true);
2804 }
2805
2806 static void hclge_reset(struct hclge_dev *hdev)
2807 {
2808 /* perform reset of the stack & ae device for a client */
2809
2810 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2811
2812 if (!hclge_reset_wait(hdev)) {
2813 rtnl_lock();
2814 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2815 hclge_reset_ae_dev(hdev->ae_dev);
2816 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2817 rtnl_unlock();
2818
2819 hclge_clear_reset_cause(hdev);
2820 } else {
2821 /* schedule again to check pending resets later */
2822 set_bit(hdev->reset_type, &hdev->reset_pending);
2823 hclge_reset_task_schedule(hdev);
2824 }
2825
2826 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2827 }
2828
2829 static void hclge_reset_event(struct hnae3_handle *handle)
2830 {
2831 struct hclge_vport *vport = hclge_get_vport(handle);
2832 struct hclge_dev *hdev = vport->back;
2833
2834 /* check if this is a new reset request and we are not here just because
2835 * last reset attempt did not succeed and watchdog hit us again. We will
2836 * know this if last reset request did not occur very recently (watchdog
2837 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2838 * In case of new request we reset the "reset level" to PF reset.
2839 */
2840 if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2841 handle->reset_level = HNAE3_FUNC_RESET;
2842
2843 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2844 handle->reset_level);
2845
2846 /* request reset & schedule reset task */
2847 set_bit(handle->reset_level, &hdev->reset_request);
2848 hclge_reset_task_schedule(hdev);
2849
2850 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2851 handle->reset_level++;
2852
2853 handle->last_reset_time = jiffies;
2854 }
2855
2856 static void hclge_reset_subtask(struct hclge_dev *hdev)
2857 {
2858 /* check if there is any ongoing reset in the hardware. This status can
2859 * be checked from reset_pending. If there is then, we need to wait for
2860 * hardware to complete reset.
2861 * a. If we are able to figure out in reasonable time that hardware
2862 * has fully resetted then, we can proceed with driver, client
2863 * reset.
2864 * b. else, we can come back later to check this status so re-sched
2865 * now.
2866 */
2867 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2868 if (hdev->reset_type != HNAE3_NONE_RESET)
2869 hclge_reset(hdev);
2870
2871 /* check if we got any *new* reset requests to be honored */
2872 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2873 if (hdev->reset_type != HNAE3_NONE_RESET)
2874 hclge_do_reset(hdev);
2875
2876 hdev->reset_type = HNAE3_NONE_RESET;
2877 }
2878
2879 static void hclge_reset_service_task(struct work_struct *work)
2880 {
2881 struct hclge_dev *hdev =
2882 container_of(work, struct hclge_dev, rst_service_task);
2883
2884 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2885 return;
2886
2887 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2888
2889 hclge_reset_subtask(hdev);
2890
2891 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2892 }
2893
2894 static void hclge_mailbox_service_task(struct work_struct *work)
2895 {
2896 struct hclge_dev *hdev =
2897 container_of(work, struct hclge_dev, mbx_service_task);
2898
2899 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2900 return;
2901
2902 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2903
2904 hclge_mbx_handler(hdev);
2905
2906 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2907 }
2908
2909 static void hclge_service_task(struct work_struct *work)
2910 {
2911 struct hclge_dev *hdev =
2912 container_of(work, struct hclge_dev, service_task);
2913
2914 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2915 hclge_update_stats_for_all(hdev);
2916 hdev->hw_stats.stats_timer = 0;
2917 }
2918
2919 hclge_update_speed_duplex(hdev);
2920 hclge_update_link_status(hdev);
2921 hclge_service_complete(hdev);
2922 }
2923
2924 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2925 {
2926 /* VF handle has no client */
2927 if (!handle->client)
2928 return container_of(handle, struct hclge_vport, nic);
2929 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2930 return container_of(handle, struct hclge_vport, roce);
2931 else
2932 return container_of(handle, struct hclge_vport, nic);
2933 }
2934
2935 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2936 struct hnae3_vector_info *vector_info)
2937 {
2938 struct hclge_vport *vport = hclge_get_vport(handle);
2939 struct hnae3_vector_info *vector = vector_info;
2940 struct hclge_dev *hdev = vport->back;
2941 int alloc = 0;
2942 int i, j;
2943
2944 vector_num = min(hdev->num_msi_left, vector_num);
2945
2946 for (j = 0; j < vector_num; j++) {
2947 for (i = 1; i < hdev->num_msi; i++) {
2948 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2949 vector->vector = pci_irq_vector(hdev->pdev, i);
2950 vector->io_addr = hdev->hw.io_base +
2951 HCLGE_VECTOR_REG_BASE +
2952 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2953 vport->vport_id *
2954 HCLGE_VECTOR_VF_OFFSET;
2955 hdev->vector_status[i] = vport->vport_id;
2956 hdev->vector_irq[i] = vector->vector;
2957
2958 vector++;
2959 alloc++;
2960
2961 break;
2962 }
2963 }
2964 }
2965 hdev->num_msi_left -= alloc;
2966 hdev->num_msi_used += alloc;
2967
2968 return alloc;
2969 }
2970
2971 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2972 {
2973 int i;
2974
2975 for (i = 0; i < hdev->num_msi; i++)
2976 if (vector == hdev->vector_irq[i])
2977 return i;
2978
2979 return -EINVAL;
2980 }
2981
2982 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2983 {
2984 struct hclge_vport *vport = hclge_get_vport(handle);
2985 struct hclge_dev *hdev = vport->back;
2986 int vector_id;
2987
2988 vector_id = hclge_get_vector_index(hdev, vector);
2989 if (vector_id < 0) {
2990 dev_err(&hdev->pdev->dev,
2991 "Get vector index fail. vector_id =%d\n", vector_id);
2992 return vector_id;
2993 }
2994
2995 hclge_free_vector(hdev, vector_id);
2996
2997 return 0;
2998 }
2999
3000 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3001 {
3002 return HCLGE_RSS_KEY_SIZE;
3003 }
3004
3005 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3006 {
3007 return HCLGE_RSS_IND_TBL_SIZE;
3008 }
3009
3010 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3011 const u8 hfunc, const u8 *key)
3012 {
3013 struct hclge_rss_config_cmd *req;
3014 struct hclge_desc desc;
3015 int key_offset;
3016 int key_size;
3017 int ret;
3018
3019 req = (struct hclge_rss_config_cmd *)desc.data;
3020
3021 for (key_offset = 0; key_offset < 3; key_offset++) {
3022 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3023 false);
3024
3025 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3026 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3027
3028 if (key_offset == 2)
3029 key_size =
3030 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3031 else
3032 key_size = HCLGE_RSS_HASH_KEY_NUM;
3033
3034 memcpy(req->hash_key,
3035 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3036
3037 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3038 if (ret) {
3039 dev_err(&hdev->pdev->dev,
3040 "Configure RSS config fail, status = %d\n",
3041 ret);
3042 return ret;
3043 }
3044 }
3045 return 0;
3046 }
3047
3048 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
3049 {
3050 struct hclge_rss_indirection_table_cmd *req;
3051 struct hclge_desc desc;
3052 int i, j;
3053 int ret;
3054
3055 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
3056
3057 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3058 hclge_cmd_setup_basic_desc
3059 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3060
3061 req->start_table_index =
3062 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3063 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
3064
3065 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3066 req->rss_result[j] =
3067 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3068
3069 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3070 if (ret) {
3071 dev_err(&hdev->pdev->dev,
3072 "Configure rss indir table fail,status = %d\n",
3073 ret);
3074 return ret;
3075 }
3076 }
3077 return 0;
3078 }
3079
3080 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3081 u16 *tc_size, u16 *tc_offset)
3082 {
3083 struct hclge_rss_tc_mode_cmd *req;
3084 struct hclge_desc desc;
3085 int ret;
3086 int i;
3087
3088 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3089 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3090
3091 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3092 u16 mode = 0;
3093
3094 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3095 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3096 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3097 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3098 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3099
3100 req->rss_tc_mode[i] = cpu_to_le16(mode);
3101 }
3102
3103 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3104 if (ret)
3105 dev_err(&hdev->pdev->dev,
3106 "Configure rss tc mode fail, status = %d\n", ret);
3107
3108 return ret;
3109 }
3110
3111 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3112 {
3113 struct hclge_rss_input_tuple_cmd *req;
3114 struct hclge_desc desc;
3115 int ret;
3116
3117 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3118
3119 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3120
3121 /* Get the tuple cfg from pf */
3122 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3123 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3124 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3125 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3126 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3127 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3128 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3129 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
3130 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3131 if (ret)
3132 dev_err(&hdev->pdev->dev,
3133 "Configure rss input fail, status = %d\n", ret);
3134 return ret;
3135 }
3136
3137 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3138 u8 *key, u8 *hfunc)
3139 {
3140 struct hclge_vport *vport = hclge_get_vport(handle);
3141 int i;
3142
3143 /* Get hash algorithm */
3144 if (hfunc)
3145 *hfunc = vport->rss_algo;
3146
3147 /* Get the RSS Key required by the user */
3148 if (key)
3149 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3150
3151 /* Get indirect table */
3152 if (indir)
3153 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3154 indir[i] = vport->rss_indirection_tbl[i];
3155
3156 return 0;
3157 }
3158
3159 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3160 const u8 *key, const u8 hfunc)
3161 {
3162 struct hclge_vport *vport = hclge_get_vport(handle);
3163 struct hclge_dev *hdev = vport->back;
3164 u8 hash_algo;
3165 int ret, i;
3166
3167 /* Set the RSS Hash Key if specififed by the user */
3168 if (key) {
3169
3170 if (hfunc == ETH_RSS_HASH_TOP ||
3171 hfunc == ETH_RSS_HASH_NO_CHANGE)
3172 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3173 else
3174 return -EINVAL;
3175 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3176 if (ret)
3177 return ret;
3178
3179 /* Update the shadow RSS key with user specified qids */
3180 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3181 vport->rss_algo = hash_algo;
3182 }
3183
3184 /* Update the shadow RSS table with user specified qids */
3185 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3186 vport->rss_indirection_tbl[i] = indir[i];
3187
3188 /* Update the hardware */
3189 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
3190 }
3191
3192 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3193 {
3194 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3195
3196 if (nfc->data & RXH_L4_B_2_3)
3197 hash_sets |= HCLGE_D_PORT_BIT;
3198 else
3199 hash_sets &= ~HCLGE_D_PORT_BIT;
3200
3201 if (nfc->data & RXH_IP_SRC)
3202 hash_sets |= HCLGE_S_IP_BIT;
3203 else
3204 hash_sets &= ~HCLGE_S_IP_BIT;
3205
3206 if (nfc->data & RXH_IP_DST)
3207 hash_sets |= HCLGE_D_IP_BIT;
3208 else
3209 hash_sets &= ~HCLGE_D_IP_BIT;
3210
3211 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3212 hash_sets |= HCLGE_V_TAG_BIT;
3213
3214 return hash_sets;
3215 }
3216
3217 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3218 struct ethtool_rxnfc *nfc)
3219 {
3220 struct hclge_vport *vport = hclge_get_vport(handle);
3221 struct hclge_dev *hdev = vport->back;
3222 struct hclge_rss_input_tuple_cmd *req;
3223 struct hclge_desc desc;
3224 u8 tuple_sets;
3225 int ret;
3226
3227 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3228 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3229 return -EINVAL;
3230
3231 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3232 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3233
3234 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3235 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3236 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3237 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3238 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3239 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3240 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3241 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
3242
3243 tuple_sets = hclge_get_rss_hash_bits(nfc);
3244 switch (nfc->flow_type) {
3245 case TCP_V4_FLOW:
3246 req->ipv4_tcp_en = tuple_sets;
3247 break;
3248 case TCP_V6_FLOW:
3249 req->ipv6_tcp_en = tuple_sets;
3250 break;
3251 case UDP_V4_FLOW:
3252 req->ipv4_udp_en = tuple_sets;
3253 break;
3254 case UDP_V6_FLOW:
3255 req->ipv6_udp_en = tuple_sets;
3256 break;
3257 case SCTP_V4_FLOW:
3258 req->ipv4_sctp_en = tuple_sets;
3259 break;
3260 case SCTP_V6_FLOW:
3261 if ((nfc->data & RXH_L4_B_0_1) ||
3262 (nfc->data & RXH_L4_B_2_3))
3263 return -EINVAL;
3264
3265 req->ipv6_sctp_en = tuple_sets;
3266 break;
3267 case IPV4_FLOW:
3268 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3269 break;
3270 case IPV6_FLOW:
3271 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3272 break;
3273 default:
3274 return -EINVAL;
3275 }
3276
3277 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3278 if (ret) {
3279 dev_err(&hdev->pdev->dev,
3280 "Set rss tuple fail, status = %d\n", ret);
3281 return ret;
3282 }
3283
3284 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3285 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3286 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3287 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3288 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3289 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3290 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3291 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3292 return 0;
3293 }
3294
3295 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3296 struct ethtool_rxnfc *nfc)
3297 {
3298 struct hclge_vport *vport = hclge_get_vport(handle);
3299 u8 tuple_sets;
3300
3301 nfc->data = 0;
3302
3303 switch (nfc->flow_type) {
3304 case TCP_V4_FLOW:
3305 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3306 break;
3307 case UDP_V4_FLOW:
3308 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3309 break;
3310 case TCP_V6_FLOW:
3311 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3312 break;
3313 case UDP_V6_FLOW:
3314 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3315 break;
3316 case SCTP_V4_FLOW:
3317 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3318 break;
3319 case SCTP_V6_FLOW:
3320 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3321 break;
3322 case IPV4_FLOW:
3323 case IPV6_FLOW:
3324 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3325 break;
3326 default:
3327 return -EINVAL;
3328 }
3329
3330 if (!tuple_sets)
3331 return 0;
3332
3333 if (tuple_sets & HCLGE_D_PORT_BIT)
3334 nfc->data |= RXH_L4_B_2_3;
3335 if (tuple_sets & HCLGE_S_PORT_BIT)
3336 nfc->data |= RXH_L4_B_0_1;
3337 if (tuple_sets & HCLGE_D_IP_BIT)
3338 nfc->data |= RXH_IP_DST;
3339 if (tuple_sets & HCLGE_S_IP_BIT)
3340 nfc->data |= RXH_IP_SRC;
3341
3342 return 0;
3343 }
3344
3345 static int hclge_get_tc_size(struct hnae3_handle *handle)
3346 {
3347 struct hclge_vport *vport = hclge_get_vport(handle);
3348 struct hclge_dev *hdev = vport->back;
3349
3350 return hdev->rss_size_max;
3351 }
3352
3353 int hclge_rss_init_hw(struct hclge_dev *hdev)
3354 {
3355 struct hclge_vport *vport = hdev->vport;
3356 u8 *rss_indir = vport[0].rss_indirection_tbl;
3357 u16 rss_size = vport[0].alloc_rss_size;
3358 u8 *key = vport[0].rss_hash_key;
3359 u8 hfunc = vport[0].rss_algo;
3360 u16 tc_offset[HCLGE_MAX_TC_NUM];
3361 u16 tc_valid[HCLGE_MAX_TC_NUM];
3362 u16 tc_size[HCLGE_MAX_TC_NUM];
3363 u16 roundup_size;
3364 int i, ret;
3365
3366 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3367 if (ret)
3368 return ret;
3369
3370 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3371 if (ret)
3372 return ret;
3373
3374 ret = hclge_set_rss_input_tuple(hdev);
3375 if (ret)
3376 return ret;
3377
3378 /* Each TC have the same queue size, and tc_size set to hardware is
3379 * the log2 of roundup power of two of rss_size, the acutal queue
3380 * size is limited by indirection table.
3381 */
3382 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3383 dev_err(&hdev->pdev->dev,
3384 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3385 rss_size);
3386 return -EINVAL;
3387 }
3388
3389 roundup_size = roundup_pow_of_two(rss_size);
3390 roundup_size = ilog2(roundup_size);
3391
3392 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3393 tc_valid[i] = 0;
3394
3395 if (!(hdev->hw_tc_map & BIT(i)))
3396 continue;
3397
3398 tc_valid[i] = 1;
3399 tc_size[i] = roundup_size;
3400 tc_offset[i] = rss_size * i;
3401 }
3402
3403 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3404 }
3405
3406 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3407 {
3408 struct hclge_vport *vport = hdev->vport;
3409 int i, j;
3410
3411 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3412 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3413 vport[j].rss_indirection_tbl[i] =
3414 i % vport[j].alloc_rss_size;
3415 }
3416 }
3417
3418 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3419 {
3420 struct hclge_vport *vport = hdev->vport;
3421 int i;
3422
3423 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3424 vport[i].rss_tuple_sets.ipv4_tcp_en =
3425 HCLGE_RSS_INPUT_TUPLE_OTHER;
3426 vport[i].rss_tuple_sets.ipv4_udp_en =
3427 HCLGE_RSS_INPUT_TUPLE_OTHER;
3428 vport[i].rss_tuple_sets.ipv4_sctp_en =
3429 HCLGE_RSS_INPUT_TUPLE_SCTP;
3430 vport[i].rss_tuple_sets.ipv4_fragment_en =
3431 HCLGE_RSS_INPUT_TUPLE_OTHER;
3432 vport[i].rss_tuple_sets.ipv6_tcp_en =
3433 HCLGE_RSS_INPUT_TUPLE_OTHER;
3434 vport[i].rss_tuple_sets.ipv6_udp_en =
3435 HCLGE_RSS_INPUT_TUPLE_OTHER;
3436 vport[i].rss_tuple_sets.ipv6_sctp_en =
3437 HCLGE_RSS_INPUT_TUPLE_SCTP;
3438 vport[i].rss_tuple_sets.ipv6_fragment_en =
3439 HCLGE_RSS_INPUT_TUPLE_OTHER;
3440
3441 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3442
3443 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3444 }
3445
3446 hclge_rss_indir_init_cfg(hdev);
3447 }
3448
3449 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3450 int vector_id, bool en,
3451 struct hnae3_ring_chain_node *ring_chain)
3452 {
3453 struct hclge_dev *hdev = vport->back;
3454 struct hnae3_ring_chain_node *node;
3455 struct hclge_desc desc;
3456 struct hclge_ctrl_vector_chain_cmd *req
3457 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3458 enum hclge_cmd_status status;
3459 enum hclge_opcode_type op;
3460 u16 tqp_type_and_id;
3461 int i;
3462
3463 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3464 hclge_cmd_setup_basic_desc(&desc, op, false);
3465 req->int_vector_id = vector_id;
3466
3467 i = 0;
3468 for (node = ring_chain; node; node = node->next) {
3469 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3470 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3471 HCLGE_INT_TYPE_S,
3472 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3473 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3474 HCLGE_TQP_ID_S, node->tqp_index);
3475 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3476 HCLGE_INT_GL_IDX_S,
3477 hnae3_get_field(node->int_gl_idx,
3478 HNAE3_RING_GL_IDX_M,
3479 HNAE3_RING_GL_IDX_S));
3480 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3481 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3482 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3483 req->vfid = vport->vport_id;
3484
3485 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3486 if (status) {
3487 dev_err(&hdev->pdev->dev,
3488 "Map TQP fail, status is %d.\n",
3489 status);
3490 return -EIO;
3491 }
3492 i = 0;
3493
3494 hclge_cmd_setup_basic_desc(&desc,
3495 op,
3496 false);
3497 req->int_vector_id = vector_id;
3498 }
3499 }
3500
3501 if (i > 0) {
3502 req->int_cause_num = i;
3503 req->vfid = vport->vport_id;
3504 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3505 if (status) {
3506 dev_err(&hdev->pdev->dev,
3507 "Map TQP fail, status is %d.\n", status);
3508 return -EIO;
3509 }
3510 }
3511
3512 return 0;
3513 }
3514
3515 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3516 int vector,
3517 struct hnae3_ring_chain_node *ring_chain)
3518 {
3519 struct hclge_vport *vport = hclge_get_vport(handle);
3520 struct hclge_dev *hdev = vport->back;
3521 int vector_id;
3522
3523 vector_id = hclge_get_vector_index(hdev, vector);
3524 if (vector_id < 0) {
3525 dev_err(&hdev->pdev->dev,
3526 "Get vector index fail. vector_id =%d\n", vector_id);
3527 return vector_id;
3528 }
3529
3530 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3531 }
3532
3533 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3534 int vector,
3535 struct hnae3_ring_chain_node *ring_chain)
3536 {
3537 struct hclge_vport *vport = hclge_get_vport(handle);
3538 struct hclge_dev *hdev = vport->back;
3539 int vector_id, ret;
3540
3541 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3542 return 0;
3543
3544 vector_id = hclge_get_vector_index(hdev, vector);
3545 if (vector_id < 0) {
3546 dev_err(&handle->pdev->dev,
3547 "Get vector index fail. ret =%d\n", vector_id);
3548 return vector_id;
3549 }
3550
3551 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3552 if (ret)
3553 dev_err(&handle->pdev->dev,
3554 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3555 vector_id,
3556 ret);
3557
3558 return ret;
3559 }
3560
3561 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3562 struct hclge_promisc_param *param)
3563 {
3564 struct hclge_promisc_cfg_cmd *req;
3565 struct hclge_desc desc;
3566 int ret;
3567
3568 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3569
3570 req = (struct hclge_promisc_cfg_cmd *)desc.data;
3571 req->vf_id = param->vf_id;
3572
3573 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3574 * pdev revision(0x20), new revision support them. The
3575 * value of this two fields will not return error when driver
3576 * send command to fireware in revision(0x20).
3577 */
3578 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3579 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3580
3581 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3582 if (ret)
3583 dev_err(&hdev->pdev->dev,
3584 "Set promisc mode fail, status is %d.\n", ret);
3585
3586 return ret;
3587 }
3588
3589 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3590 bool en_mc, bool en_bc, int vport_id)
3591 {
3592 if (!param)
3593 return;
3594
3595 memset(param, 0, sizeof(struct hclge_promisc_param));
3596 if (en_uc)
3597 param->enable = HCLGE_PROMISC_EN_UC;
3598 if (en_mc)
3599 param->enable |= HCLGE_PROMISC_EN_MC;
3600 if (en_bc)
3601 param->enable |= HCLGE_PROMISC_EN_BC;
3602 param->vf_id = vport_id;
3603 }
3604
3605 static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3606 bool en_mc_pmc)
3607 {
3608 struct hclge_vport *vport = hclge_get_vport(handle);
3609 struct hclge_dev *hdev = vport->back;
3610 struct hclge_promisc_param param;
3611
3612 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3613 vport->vport_id);
3614 hclge_cmd_set_promisc_mode(hdev, &param);
3615 }
3616
3617 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3618 {
3619 struct hclge_desc desc;
3620 struct hclge_config_mac_mode_cmd *req =
3621 (struct hclge_config_mac_mode_cmd *)desc.data;
3622 u32 loop_en = 0;
3623 int ret;
3624
3625 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3626 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3627 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3628 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3629 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3630 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3631 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3632 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3633 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3634 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3635 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3636 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3637 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3638 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3639 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3640 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3641
3642 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3643 if (ret)
3644 dev_err(&hdev->pdev->dev,
3645 "mac enable fail, ret =%d.\n", ret);
3646 }
3647
3648 static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
3649 {
3650 struct hclge_config_mac_mode_cmd *req;
3651 struct hclge_desc desc;
3652 u32 loop_en;
3653 int ret;
3654
3655 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3656 /* 1 Read out the MAC mode config at first */
3657 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3658 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3659 if (ret) {
3660 dev_err(&hdev->pdev->dev,
3661 "mac loopback get fail, ret =%d.\n", ret);
3662 return ret;
3663 }
3664
3665 /* 2 Then setup the loopback flag */
3666 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3667 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
3668
3669 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3670
3671 /* 3 Config mac work mode with loopback flag
3672 * and its original configure parameters
3673 */
3674 hclge_cmd_reuse_desc(&desc, false);
3675 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3676 if (ret)
3677 dev_err(&hdev->pdev->dev,
3678 "mac loopback set fail, ret =%d.\n", ret);
3679 return ret;
3680 }
3681
3682 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3683 {
3684 #define HCLGE_SERDES_RETRY_MS 10
3685 #define HCLGE_SERDES_RETRY_NUM 100
3686 struct hclge_serdes_lb_cmd *req;
3687 struct hclge_desc desc;
3688 int ret, i = 0;
3689
3690 req = (struct hclge_serdes_lb_cmd *)&desc.data[0];
3691 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3692
3693 if (en) {
3694 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3695 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3696 } else {
3697 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3698 }
3699
3700 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3701 if (ret) {
3702 dev_err(&hdev->pdev->dev,
3703 "serdes loopback set fail, ret = %d\n", ret);
3704 return ret;
3705 }
3706
3707 do {
3708 msleep(HCLGE_SERDES_RETRY_MS);
3709 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3710 true);
3711 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3712 if (ret) {
3713 dev_err(&hdev->pdev->dev,
3714 "serdes loopback get, ret = %d\n", ret);
3715 return ret;
3716 }
3717 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3718 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3719
3720 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3721 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3722 return -EBUSY;
3723 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3724 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3725 return -EIO;
3726 }
3727
3728 return 0;
3729 }
3730
3731 static int hclge_set_loopback(struct hnae3_handle *handle,
3732 enum hnae3_loop loop_mode, bool en)
3733 {
3734 struct hclge_vport *vport = hclge_get_vport(handle);
3735 struct hclge_dev *hdev = vport->back;
3736 int ret;
3737
3738 switch (loop_mode) {
3739 case HNAE3_MAC_INTER_LOOP_MAC:
3740 ret = hclge_set_mac_loopback(hdev, en);
3741 break;
3742 case HNAE3_MAC_INTER_LOOP_SERDES:
3743 ret = hclge_set_serdes_loopback(hdev, en);
3744 break;
3745 default:
3746 ret = -ENOTSUPP;
3747 dev_err(&hdev->pdev->dev,
3748 "loop_mode %d is not supported\n", loop_mode);
3749 break;
3750 }
3751
3752 return ret;
3753 }
3754
3755 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3756 int stream_id, bool enable)
3757 {
3758 struct hclge_desc desc;
3759 struct hclge_cfg_com_tqp_queue_cmd *req =
3760 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3761 int ret;
3762
3763 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3764 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3765 req->stream_id = cpu_to_le16(stream_id);
3766 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3767
3768 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3769 if (ret)
3770 dev_err(&hdev->pdev->dev,
3771 "Tqp enable fail, status =%d.\n", ret);
3772 return ret;
3773 }
3774
3775 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3776 {
3777 struct hclge_vport *vport = hclge_get_vport(handle);
3778 struct hnae3_queue *queue;
3779 struct hclge_tqp *tqp;
3780 int i;
3781
3782 for (i = 0; i < vport->alloc_tqps; i++) {
3783 queue = handle->kinfo.tqp[i];
3784 tqp = container_of(queue, struct hclge_tqp, q);
3785 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3786 }
3787 }
3788
3789 static int hclge_ae_start(struct hnae3_handle *handle)
3790 {
3791 struct hclge_vport *vport = hclge_get_vport(handle);
3792 struct hclge_dev *hdev = vport->back;
3793 int i, ret;
3794
3795 for (i = 0; i < vport->alloc_tqps; i++)
3796 hclge_tqp_enable(hdev, i, 0, true);
3797
3798 /* mac enable */
3799 hclge_cfg_mac_mode(hdev, true);
3800 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3801 mod_timer(&hdev->service_timer, jiffies + HZ);
3802 hdev->hw.mac.link = 0;
3803
3804 /* reset tqp stats */
3805 hclge_reset_tqp_stats(handle);
3806
3807 ret = hclge_mac_start_phy(hdev);
3808 if (ret)
3809 return ret;
3810
3811 return 0;
3812 }
3813
3814 static void hclge_ae_stop(struct hnae3_handle *handle)
3815 {
3816 struct hclge_vport *vport = hclge_get_vport(handle);
3817 struct hclge_dev *hdev = vport->back;
3818 int i;
3819
3820 del_timer_sync(&hdev->service_timer);
3821 cancel_work_sync(&hdev->service_task);
3822 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
3823
3824 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3825 hclge_mac_stop_phy(hdev);
3826 return;
3827 }
3828
3829 for (i = 0; i < vport->alloc_tqps; i++)
3830 hclge_tqp_enable(hdev, i, 0, false);
3831
3832 /* Mac disable */
3833 hclge_cfg_mac_mode(hdev, false);
3834
3835 hclge_mac_stop_phy(hdev);
3836
3837 /* reset tqp stats */
3838 hclge_reset_tqp_stats(handle);
3839 del_timer_sync(&hdev->service_timer);
3840 cancel_work_sync(&hdev->service_task);
3841 hclge_update_link_status(hdev);
3842 }
3843
3844 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3845 u16 cmdq_resp, u8 resp_code,
3846 enum hclge_mac_vlan_tbl_opcode op)
3847 {
3848 struct hclge_dev *hdev = vport->back;
3849 int return_status = -EIO;
3850
3851 if (cmdq_resp) {
3852 dev_err(&hdev->pdev->dev,
3853 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3854 cmdq_resp);
3855 return -EIO;
3856 }
3857
3858 if (op == HCLGE_MAC_VLAN_ADD) {
3859 if ((!resp_code) || (resp_code == 1)) {
3860 return_status = 0;
3861 } else if (resp_code == 2) {
3862 return_status = -ENOSPC;
3863 dev_err(&hdev->pdev->dev,
3864 "add mac addr failed for uc_overflow.\n");
3865 } else if (resp_code == 3) {
3866 return_status = -ENOSPC;
3867 dev_err(&hdev->pdev->dev,
3868 "add mac addr failed for mc_overflow.\n");
3869 } else {
3870 dev_err(&hdev->pdev->dev,
3871 "add mac addr failed for undefined, code=%d.\n",
3872 resp_code);
3873 }
3874 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3875 if (!resp_code) {
3876 return_status = 0;
3877 } else if (resp_code == 1) {
3878 return_status = -ENOENT;
3879 dev_dbg(&hdev->pdev->dev,
3880 "remove mac addr failed for miss.\n");
3881 } else {
3882 dev_err(&hdev->pdev->dev,
3883 "remove mac addr failed for undefined, code=%d.\n",
3884 resp_code);
3885 }
3886 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3887 if (!resp_code) {
3888 return_status = 0;
3889 } else if (resp_code == 1) {
3890 return_status = -ENOENT;
3891 dev_dbg(&hdev->pdev->dev,
3892 "lookup mac addr failed for miss.\n");
3893 } else {
3894 dev_err(&hdev->pdev->dev,
3895 "lookup mac addr failed for undefined, code=%d.\n",
3896 resp_code);
3897 }
3898 } else {
3899 return_status = -EINVAL;
3900 dev_err(&hdev->pdev->dev,
3901 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3902 op);
3903 }
3904
3905 return return_status;
3906 }
3907
3908 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3909 {
3910 int word_num;
3911 int bit_num;
3912
3913 if (vfid > 255 || vfid < 0)
3914 return -EIO;
3915
3916 if (vfid >= 0 && vfid <= 191) {
3917 word_num = vfid / 32;
3918 bit_num = vfid % 32;
3919 if (clr)
3920 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3921 else
3922 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3923 } else {
3924 word_num = (vfid - 192) / 32;
3925 bit_num = vfid % 32;
3926 if (clr)
3927 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3928 else
3929 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3930 }
3931
3932 return 0;
3933 }
3934
3935 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3936 {
3937 #define HCLGE_DESC_NUMBER 3
3938 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3939 int i, j;
3940
3941 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3942 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3943 if (desc[i].data[j])
3944 return false;
3945
3946 return true;
3947 }
3948
3949 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3950 const u8 *addr)
3951 {
3952 const unsigned char *mac_addr = addr;
3953 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3954 (mac_addr[0]) | (mac_addr[1] << 8);
3955 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3956
3957 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3958 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3959 }
3960
3961 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3962 const u8 *addr)
3963 {
3964 u16 high_val = addr[1] | (addr[0] << 8);
3965 struct hclge_dev *hdev = vport->back;
3966 u32 rsh = 4 - hdev->mta_mac_sel_type;
3967 u16 ret_val = (high_val >> rsh) & 0xfff;
3968
3969 return ret_val;
3970 }
3971
3972 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3973 enum hclge_mta_dmac_sel_type mta_mac_sel,
3974 bool enable)
3975 {
3976 struct hclge_mta_filter_mode_cmd *req;
3977 struct hclge_desc desc;
3978 int ret;
3979
3980 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3981 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3982
3983 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3984 enable);
3985 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3986 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3987
3988 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3989 if (ret)
3990 dev_err(&hdev->pdev->dev,
3991 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3992 ret);
3993
3994 return ret;
3995 }
3996
3997 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3998 u8 func_id,
3999 bool enable)
4000 {
4001 struct hclge_cfg_func_mta_filter_cmd *req;
4002 struct hclge_desc desc;
4003 int ret;
4004
4005 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
4006 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
4007
4008 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
4009 enable);
4010 req->function_id = func_id;
4011
4012 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4013 if (ret)
4014 dev_err(&hdev->pdev->dev,
4015 "Config func_id enable failed for cmd_send, ret =%d.\n",
4016 ret);
4017
4018 return ret;
4019 }
4020
4021 static int hclge_set_mta_table_item(struct hclge_vport *vport,
4022 u16 idx,
4023 bool enable)
4024 {
4025 struct hclge_dev *hdev = vport->back;
4026 struct hclge_cfg_func_mta_item_cmd *req;
4027 struct hclge_desc desc;
4028 u16 item_idx = 0;
4029 int ret;
4030
4031 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
4032 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
4033 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
4034
4035 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4036 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
4037 req->item_idx = cpu_to_le16(item_idx);
4038
4039 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4040 if (ret) {
4041 dev_err(&hdev->pdev->dev,
4042 "Config mta table item failed for cmd_send, ret =%d.\n",
4043 ret);
4044 return ret;
4045 }
4046
4047 if (enable)
4048 set_bit(idx, vport->mta_shadow);
4049 else
4050 clear_bit(idx, vport->mta_shadow);
4051
4052 return 0;
4053 }
4054
4055 static int hclge_update_mta_status(struct hnae3_handle *handle)
4056 {
4057 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4058 struct hclge_vport *vport = hclge_get_vport(handle);
4059 struct net_device *netdev = handle->kinfo.netdev;
4060 struct netdev_hw_addr *ha;
4061 u16 tbl_idx;
4062
4063 memset(mta_status, 0, sizeof(mta_status));
4064
4065 /* update mta_status from mc addr list */
4066 netdev_for_each_mc_addr(ha, netdev) {
4067 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4068 set_bit(tbl_idx, mta_status);
4069 }
4070
4071 return hclge_update_mta_status_common(vport, mta_status,
4072 0, HCLGE_MTA_TBL_SIZE, true);
4073 }
4074
4075 int hclge_update_mta_status_common(struct hclge_vport *vport,
4076 unsigned long *status,
4077 u16 idx,
4078 u16 count,
4079 bool update_filter)
4080 {
4081 struct hclge_dev *hdev = vport->back;
4082 u16 update_max = idx + count;
4083 u16 check_max;
4084 int ret = 0;
4085 bool used;
4086 u16 i;
4087
4088 /* setup mta check range */
4089 if (update_filter) {
4090 i = 0;
4091 check_max = HCLGE_MTA_TBL_SIZE;
4092 } else {
4093 i = idx;
4094 check_max = update_max;
4095 }
4096
4097 used = false;
4098 /* check and update all mta item */
4099 for (; i < check_max; i++) {
4100 /* ignore unused item */
4101 if (!test_bit(i, vport->mta_shadow))
4102 continue;
4103
4104 /* if i in update range then update it */
4105 if (i >= idx && i < update_max)
4106 if (!test_bit(i - idx, status))
4107 hclge_set_mta_table_item(vport, i, false);
4108
4109 if (!used && test_bit(i, vport->mta_shadow))
4110 used = true;
4111 }
4112
4113 /* no longer use mta, disable it */
4114 if (vport->accept_mta_mc && update_filter && !used) {
4115 ret = hclge_cfg_func_mta_filter(hdev,
4116 vport->vport_id,
4117 false);
4118 if (ret)
4119 dev_err(&hdev->pdev->dev,
4120 "disable func mta filter fail ret=%d\n",
4121 ret);
4122 else
4123 vport->accept_mta_mc = false;
4124 }
4125
4126 return ret;
4127 }
4128
4129 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
4130 struct hclge_mac_vlan_tbl_entry_cmd *req)
4131 {
4132 struct hclge_dev *hdev = vport->back;
4133 struct hclge_desc desc;
4134 u8 resp_code;
4135 u16 retval;
4136 int ret;
4137
4138 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4139
4140 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4141
4142 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4143 if (ret) {
4144 dev_err(&hdev->pdev->dev,
4145 "del mac addr failed for cmd_send, ret =%d.\n",
4146 ret);
4147 return ret;
4148 }
4149 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4150 retval = le16_to_cpu(desc.retval);
4151
4152 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4153 HCLGE_MAC_VLAN_REMOVE);
4154 }
4155
4156 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
4157 struct hclge_mac_vlan_tbl_entry_cmd *req,
4158 struct hclge_desc *desc,
4159 bool is_mc)
4160 {
4161 struct hclge_dev *hdev = vport->back;
4162 u8 resp_code;
4163 u16 retval;
4164 int ret;
4165
4166 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4167 if (is_mc) {
4168 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4169 memcpy(desc[0].data,
4170 req,
4171 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4172 hclge_cmd_setup_basic_desc(&desc[1],
4173 HCLGE_OPC_MAC_VLAN_ADD,
4174 true);
4175 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4176 hclge_cmd_setup_basic_desc(&desc[2],
4177 HCLGE_OPC_MAC_VLAN_ADD,
4178 true);
4179 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4180 } else {
4181 memcpy(desc[0].data,
4182 req,
4183 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4184 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4185 }
4186 if (ret) {
4187 dev_err(&hdev->pdev->dev,
4188 "lookup mac addr failed for cmd_send, ret =%d.\n",
4189 ret);
4190 return ret;
4191 }
4192 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4193 retval = le16_to_cpu(desc[0].retval);
4194
4195 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4196 HCLGE_MAC_VLAN_LKUP);
4197 }
4198
4199 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
4200 struct hclge_mac_vlan_tbl_entry_cmd *req,
4201 struct hclge_desc *mc_desc)
4202 {
4203 struct hclge_dev *hdev = vport->back;
4204 int cfg_status;
4205 u8 resp_code;
4206 u16 retval;
4207 int ret;
4208
4209 if (!mc_desc) {
4210 struct hclge_desc desc;
4211
4212 hclge_cmd_setup_basic_desc(&desc,
4213 HCLGE_OPC_MAC_VLAN_ADD,
4214 false);
4215 memcpy(desc.data, req,
4216 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4217 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4218 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4219 retval = le16_to_cpu(desc.retval);
4220
4221 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4222 resp_code,
4223 HCLGE_MAC_VLAN_ADD);
4224 } else {
4225 hclge_cmd_reuse_desc(&mc_desc[0], false);
4226 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4227 hclge_cmd_reuse_desc(&mc_desc[1], false);
4228 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4229 hclge_cmd_reuse_desc(&mc_desc[2], false);
4230 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4231 memcpy(mc_desc[0].data, req,
4232 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4233 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
4234 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4235 retval = le16_to_cpu(mc_desc[0].retval);
4236
4237 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4238 resp_code,
4239 HCLGE_MAC_VLAN_ADD);
4240 }
4241
4242 if (ret) {
4243 dev_err(&hdev->pdev->dev,
4244 "add mac addr failed for cmd_send, ret =%d.\n",
4245 ret);
4246 return ret;
4247 }
4248
4249 return cfg_status;
4250 }
4251
4252 static int hclge_add_uc_addr(struct hnae3_handle *handle,
4253 const unsigned char *addr)
4254 {
4255 struct hclge_vport *vport = hclge_get_vport(handle);
4256
4257 return hclge_add_uc_addr_common(vport, addr);
4258 }
4259
4260 int hclge_add_uc_addr_common(struct hclge_vport *vport,
4261 const unsigned char *addr)
4262 {
4263 struct hclge_dev *hdev = vport->back;
4264 struct hclge_mac_vlan_tbl_entry_cmd req;
4265 struct hclge_desc desc;
4266 u16 egress_port = 0;
4267 int ret;
4268
4269 /* mac addr check */
4270 if (is_zero_ether_addr(addr) ||
4271 is_broadcast_ether_addr(addr) ||
4272 is_multicast_ether_addr(addr)) {
4273 dev_err(&hdev->pdev->dev,
4274 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4275 addr,
4276 is_zero_ether_addr(addr),
4277 is_broadcast_ether_addr(addr),
4278 is_multicast_ether_addr(addr));
4279 return -EINVAL;
4280 }
4281
4282 memset(&req, 0, sizeof(req));
4283 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4284
4285 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4286 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4287
4288 req.egress_port = cpu_to_le16(egress_port);
4289
4290 hclge_prepare_mac_addr(&req, addr);
4291
4292 /* Lookup the mac address in the mac_vlan table, and add
4293 * it if the entry is inexistent. Repeated unicast entry
4294 * is not allowed in the mac vlan table.
4295 */
4296 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4297 if (ret == -ENOENT)
4298 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4299
4300 /* check if we just hit the duplicate */
4301 if (!ret)
4302 ret = -EINVAL;
4303
4304 dev_err(&hdev->pdev->dev,
4305 "PF failed to add unicast entry(%pM) in the MAC table\n",
4306 addr);
4307
4308 return ret;
4309 }
4310
4311 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4312 const unsigned char *addr)
4313 {
4314 struct hclge_vport *vport = hclge_get_vport(handle);
4315
4316 return hclge_rm_uc_addr_common(vport, addr);
4317 }
4318
4319 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4320 const unsigned char *addr)
4321 {
4322 struct hclge_dev *hdev = vport->back;
4323 struct hclge_mac_vlan_tbl_entry_cmd req;
4324 int ret;
4325
4326 /* mac addr check */
4327 if (is_zero_ether_addr(addr) ||
4328 is_broadcast_ether_addr(addr) ||
4329 is_multicast_ether_addr(addr)) {
4330 dev_dbg(&hdev->pdev->dev,
4331 "Remove mac err! invalid mac:%pM.\n",
4332 addr);
4333 return -EINVAL;
4334 }
4335
4336 memset(&req, 0, sizeof(req));
4337 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4338 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4339 hclge_prepare_mac_addr(&req, addr);
4340 ret = hclge_remove_mac_vlan_tbl(vport, &req);
4341
4342 return ret;
4343 }
4344
4345 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4346 const unsigned char *addr)
4347 {
4348 struct hclge_vport *vport = hclge_get_vport(handle);
4349
4350 return hclge_add_mc_addr_common(vport, addr);
4351 }
4352
4353 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4354 const unsigned char *addr)
4355 {
4356 struct hclge_dev *hdev = vport->back;
4357 struct hclge_mac_vlan_tbl_entry_cmd req;
4358 struct hclge_desc desc[3];
4359 u16 tbl_idx;
4360 int status;
4361
4362 /* mac addr check */
4363 if (!is_multicast_ether_addr(addr)) {
4364 dev_err(&hdev->pdev->dev,
4365 "Add mc mac err! invalid mac:%pM.\n",
4366 addr);
4367 return -EINVAL;
4368 }
4369 memset(&req, 0, sizeof(req));
4370 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4371 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4372 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4373 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4374 hclge_prepare_mac_addr(&req, addr);
4375 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4376 if (!status) {
4377 /* This mac addr exist, update VFID for it */
4378 hclge_update_desc_vfid(desc, vport->vport_id, false);
4379 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4380 } else {
4381 /* This mac addr do not exist, add new entry for it */
4382 memset(desc[0].data, 0, sizeof(desc[0].data));
4383 memset(desc[1].data, 0, sizeof(desc[0].data));
4384 memset(desc[2].data, 0, sizeof(desc[0].data));
4385 hclge_update_desc_vfid(desc, vport->vport_id, false);
4386 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4387 }
4388
4389 /* If mc mac vlan table is full, use MTA table */
4390 if (status == -ENOSPC) {
4391 if (!vport->accept_mta_mc) {
4392 status = hclge_cfg_func_mta_filter(hdev,
4393 vport->vport_id,
4394 true);
4395 if (status) {
4396 dev_err(&hdev->pdev->dev,
4397 "set mta filter mode fail ret=%d\n",
4398 status);
4399 return status;
4400 }
4401 vport->accept_mta_mc = true;
4402 }
4403
4404 /* Set MTA table for this MAC address */
4405 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4406 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4407 }
4408
4409 return status;
4410 }
4411
4412 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4413 const unsigned char *addr)
4414 {
4415 struct hclge_vport *vport = hclge_get_vport(handle);
4416
4417 return hclge_rm_mc_addr_common(vport, addr);
4418 }
4419
4420 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4421 const unsigned char *addr)
4422 {
4423 struct hclge_dev *hdev = vport->back;
4424 struct hclge_mac_vlan_tbl_entry_cmd req;
4425 enum hclge_cmd_status status;
4426 struct hclge_desc desc[3];
4427
4428 /* mac addr check */
4429 if (!is_multicast_ether_addr(addr)) {
4430 dev_dbg(&hdev->pdev->dev,
4431 "Remove mc mac err! invalid mac:%pM.\n",
4432 addr);
4433 return -EINVAL;
4434 }
4435
4436 memset(&req, 0, sizeof(req));
4437 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4438 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4439 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4440 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4441 hclge_prepare_mac_addr(&req, addr);
4442 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4443 if (!status) {
4444 /* This mac addr exist, remove this handle's VFID for it */
4445 hclge_update_desc_vfid(desc, vport->vport_id, true);
4446
4447 if (hclge_is_all_function_id_zero(desc))
4448 /* All the vfid is zero, so need to delete this entry */
4449 status = hclge_remove_mac_vlan_tbl(vport, &req);
4450 else
4451 /* Not all the vfid is zero, update the vfid */
4452 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4453
4454 } else {
4455 /* Maybe this mac address is in mta table, but it cannot be
4456 * deleted here because an entry of mta represents an address
4457 * range rather than a specific address. the delete action to
4458 * all entries will take effect in update_mta_status called by
4459 * hns3_nic_set_rx_mode.
4460 */
4461 status = 0;
4462 }
4463
4464 return status;
4465 }
4466
4467 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4468 u16 cmdq_resp, u8 resp_code)
4469 {
4470 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4471 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4472 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4473 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4474
4475 int return_status;
4476
4477 if (cmdq_resp) {
4478 dev_err(&hdev->pdev->dev,
4479 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4480 cmdq_resp);
4481 return -EIO;
4482 }
4483
4484 switch (resp_code) {
4485 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4486 case HCLGE_ETHERTYPE_ALREADY_ADD:
4487 return_status = 0;
4488 break;
4489 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4490 dev_err(&hdev->pdev->dev,
4491 "add mac ethertype failed for manager table overflow.\n");
4492 return_status = -EIO;
4493 break;
4494 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4495 dev_err(&hdev->pdev->dev,
4496 "add mac ethertype failed for key conflict.\n");
4497 return_status = -EIO;
4498 break;
4499 default:
4500 dev_err(&hdev->pdev->dev,
4501 "add mac ethertype failed for undefined, code=%d.\n",
4502 resp_code);
4503 return_status = -EIO;
4504 }
4505
4506 return return_status;
4507 }
4508
4509 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4510 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4511 {
4512 struct hclge_desc desc;
4513 u8 resp_code;
4514 u16 retval;
4515 int ret;
4516
4517 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4518 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4519
4520 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4521 if (ret) {
4522 dev_err(&hdev->pdev->dev,
4523 "add mac ethertype failed for cmd_send, ret =%d.\n",
4524 ret);
4525 return ret;
4526 }
4527
4528 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4529 retval = le16_to_cpu(desc.retval);
4530
4531 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4532 }
4533
4534 static int init_mgr_tbl(struct hclge_dev *hdev)
4535 {
4536 int ret;
4537 int i;
4538
4539 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4540 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4541 if (ret) {
4542 dev_err(&hdev->pdev->dev,
4543 "add mac ethertype failed, ret =%d.\n",
4544 ret);
4545 return ret;
4546 }
4547 }
4548
4549 return 0;
4550 }
4551
4552 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4553 {
4554 struct hclge_vport *vport = hclge_get_vport(handle);
4555 struct hclge_dev *hdev = vport->back;
4556
4557 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4558 }
4559
4560 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4561 bool is_first)
4562 {
4563 const unsigned char *new_addr = (const unsigned char *)p;
4564 struct hclge_vport *vport = hclge_get_vport(handle);
4565 struct hclge_dev *hdev = vport->back;
4566 int ret;
4567
4568 /* mac addr check */
4569 if (is_zero_ether_addr(new_addr) ||
4570 is_broadcast_ether_addr(new_addr) ||
4571 is_multicast_ether_addr(new_addr)) {
4572 dev_err(&hdev->pdev->dev,
4573 "Change uc mac err! invalid mac:%p.\n",
4574 new_addr);
4575 return -EINVAL;
4576 }
4577
4578 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
4579 dev_warn(&hdev->pdev->dev,
4580 "remove old uc mac address fail.\n");
4581
4582 ret = hclge_add_uc_addr(handle, new_addr);
4583 if (ret) {
4584 dev_err(&hdev->pdev->dev,
4585 "add uc mac address fail, ret =%d.\n",
4586 ret);
4587
4588 if (!is_first &&
4589 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
4590 dev_err(&hdev->pdev->dev,
4591 "restore uc mac address fail.\n");
4592
4593 return -EIO;
4594 }
4595
4596 ret = hclge_pause_addr_cfg(hdev, new_addr);
4597 if (ret) {
4598 dev_err(&hdev->pdev->dev,
4599 "configure mac pause address fail, ret =%d.\n",
4600 ret);
4601 return -EIO;
4602 }
4603
4604 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4605
4606 return 0;
4607 }
4608
4609 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4610 bool filter_en)
4611 {
4612 struct hclge_vlan_filter_ctrl_cmd *req;
4613 struct hclge_desc desc;
4614 int ret;
4615
4616 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4617
4618 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4619 req->vlan_type = vlan_type;
4620 req->vlan_fe = filter_en;
4621
4622 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4623 if (ret)
4624 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4625 ret);
4626
4627 return ret;
4628 }
4629
4630 #define HCLGE_FILTER_TYPE_VF 0
4631 #define HCLGE_FILTER_TYPE_PORT 1
4632
4633 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4634 {
4635 struct hclge_vport *vport = hclge_get_vport(handle);
4636 struct hclge_dev *hdev = vport->back;
4637
4638 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4639 }
4640
4641 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4642 bool is_kill, u16 vlan, u8 qos,
4643 __be16 proto)
4644 {
4645 #define HCLGE_MAX_VF_BYTES 16
4646 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4647 struct hclge_vlan_filter_vf_cfg_cmd *req1;
4648 struct hclge_desc desc[2];
4649 u8 vf_byte_val;
4650 u8 vf_byte_off;
4651 int ret;
4652
4653 hclge_cmd_setup_basic_desc(&desc[0],
4654 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4655 hclge_cmd_setup_basic_desc(&desc[1],
4656 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4657
4658 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4659
4660 vf_byte_off = vfid / 8;
4661 vf_byte_val = 1 << (vfid % 8);
4662
4663 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4664 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4665
4666 req0->vlan_id = cpu_to_le16(vlan);
4667 req0->vlan_cfg = is_kill;
4668
4669 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4670 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4671 else
4672 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4673
4674 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4675 if (ret) {
4676 dev_err(&hdev->pdev->dev,
4677 "Send vf vlan command fail, ret =%d.\n",
4678 ret);
4679 return ret;
4680 }
4681
4682 if (!is_kill) {
4683 #define HCLGE_VF_VLAN_NO_ENTRY 2
4684 if (!req0->resp_code || req0->resp_code == 1)
4685 return 0;
4686
4687 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4688 dev_warn(&hdev->pdev->dev,
4689 "vf vlan table is full, vf vlan filter is disabled\n");
4690 return 0;
4691 }
4692
4693 dev_err(&hdev->pdev->dev,
4694 "Add vf vlan filter fail, ret =%d.\n",
4695 req0->resp_code);
4696 } else {
4697 if (!req0->resp_code)
4698 return 0;
4699
4700 dev_err(&hdev->pdev->dev,
4701 "Kill vf vlan filter fail, ret =%d.\n",
4702 req0->resp_code);
4703 }
4704
4705 return -EIO;
4706 }
4707
4708 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4709 u16 vlan_id, bool is_kill)
4710 {
4711 struct hclge_vlan_filter_pf_cfg_cmd *req;
4712 struct hclge_desc desc;
4713 u8 vlan_offset_byte_val;
4714 u8 vlan_offset_byte;
4715 u8 vlan_offset_160;
4716 int ret;
4717
4718 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4719
4720 vlan_offset_160 = vlan_id / 160;
4721 vlan_offset_byte = (vlan_id % 160) / 8;
4722 vlan_offset_byte_val = 1 << (vlan_id % 8);
4723
4724 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4725 req->vlan_offset = vlan_offset_160;
4726 req->vlan_cfg = is_kill;
4727 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4728
4729 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4730 if (ret)
4731 dev_err(&hdev->pdev->dev,
4732 "port vlan command, send fail, ret =%d.\n", ret);
4733 return ret;
4734 }
4735
4736 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4737 u16 vport_id, u16 vlan_id, u8 qos,
4738 bool is_kill)
4739 {
4740 u16 vport_idx, vport_num = 0;
4741 int ret;
4742
4743 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4744 0, proto);
4745 if (ret) {
4746 dev_err(&hdev->pdev->dev,
4747 "Set %d vport vlan filter config fail, ret =%d.\n",
4748 vport_id, ret);
4749 return ret;
4750 }
4751
4752 /* vlan 0 may be added twice when 8021q module is enabled */
4753 if (!is_kill && !vlan_id &&
4754 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4755 return 0;
4756
4757 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
4758 dev_err(&hdev->pdev->dev,
4759 "Add port vlan failed, vport %d is already in vlan %d\n",
4760 vport_id, vlan_id);
4761 return -EINVAL;
4762 }
4763
4764 if (is_kill &&
4765 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4766 dev_err(&hdev->pdev->dev,
4767 "Delete port vlan failed, vport %d is not in vlan %d\n",
4768 vport_id, vlan_id);
4769 return -EINVAL;
4770 }
4771
4772 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4773 vport_num++;
4774
4775 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4776 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4777 is_kill);
4778
4779 return ret;
4780 }
4781
4782 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4783 u16 vlan_id, bool is_kill)
4784 {
4785 struct hclge_vport *vport = hclge_get_vport(handle);
4786 struct hclge_dev *hdev = vport->back;
4787
4788 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4789 0, is_kill);
4790 }
4791
4792 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4793 u16 vlan, u8 qos, __be16 proto)
4794 {
4795 struct hclge_vport *vport = hclge_get_vport(handle);
4796 struct hclge_dev *hdev = vport->back;
4797
4798 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4799 return -EINVAL;
4800 if (proto != htons(ETH_P_8021Q))
4801 return -EPROTONOSUPPORT;
4802
4803 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
4804 }
4805
4806 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4807 {
4808 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4809 struct hclge_vport_vtag_tx_cfg_cmd *req;
4810 struct hclge_dev *hdev = vport->back;
4811 struct hclge_desc desc;
4812 int status;
4813
4814 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4815
4816 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4817 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4818 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4819 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4820 vcfg->accept_tag1 ? 1 : 0);
4821 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4822 vcfg->accept_untag1 ? 1 : 0);
4823 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4824 vcfg->accept_tag2 ? 1 : 0);
4825 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4826 vcfg->accept_untag2 ? 1 : 0);
4827 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4828 vcfg->insert_tag1_en ? 1 : 0);
4829 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4830 vcfg->insert_tag2_en ? 1 : 0);
4831 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4832
4833 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4834 req->vf_bitmap[req->vf_offset] =
4835 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4836
4837 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4838 if (status)
4839 dev_err(&hdev->pdev->dev,
4840 "Send port txvlan cfg command fail, ret =%d\n",
4841 status);
4842
4843 return status;
4844 }
4845
4846 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4847 {
4848 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4849 struct hclge_vport_vtag_rx_cfg_cmd *req;
4850 struct hclge_dev *hdev = vport->back;
4851 struct hclge_desc desc;
4852 int status;
4853
4854 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4855
4856 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4857 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4858 vcfg->strip_tag1_en ? 1 : 0);
4859 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4860 vcfg->strip_tag2_en ? 1 : 0);
4861 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4862 vcfg->vlan1_vlan_prionly ? 1 : 0);
4863 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4864 vcfg->vlan2_vlan_prionly ? 1 : 0);
4865
4866 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4867 req->vf_bitmap[req->vf_offset] =
4868 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4869
4870 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4871 if (status)
4872 dev_err(&hdev->pdev->dev,
4873 "Send port rxvlan cfg command fail, ret =%d\n",
4874 status);
4875
4876 return status;
4877 }
4878
4879 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4880 {
4881 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4882 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4883 struct hclge_desc desc;
4884 int status;
4885
4886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4887 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4888 rx_req->ot_fst_vlan_type =
4889 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4890 rx_req->ot_sec_vlan_type =
4891 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4892 rx_req->in_fst_vlan_type =
4893 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4894 rx_req->in_sec_vlan_type =
4895 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4896
4897 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4898 if (status) {
4899 dev_err(&hdev->pdev->dev,
4900 "Send rxvlan protocol type command fail, ret =%d\n",
4901 status);
4902 return status;
4903 }
4904
4905 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4906
4907 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4908 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4909 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4910
4911 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4912 if (status)
4913 dev_err(&hdev->pdev->dev,
4914 "Send txvlan protocol type command fail, ret =%d\n",
4915 status);
4916
4917 return status;
4918 }
4919
4920 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4921 {
4922 #define HCLGE_DEF_VLAN_TYPE 0x8100
4923
4924 struct hnae3_handle *handle;
4925 struct hclge_vport *vport;
4926 int ret;
4927 int i;
4928
4929 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4930 if (ret)
4931 return ret;
4932
4933 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
4934 if (ret)
4935 return ret;
4936
4937 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4938 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4939 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4940 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4941 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4942 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4943
4944 ret = hclge_set_vlan_protocol_type(hdev);
4945 if (ret)
4946 return ret;
4947
4948 for (i = 0; i < hdev->num_alloc_vport; i++) {
4949 vport = &hdev->vport[i];
4950 vport->txvlan_cfg.accept_tag1 = true;
4951 vport->txvlan_cfg.accept_untag1 = true;
4952
4953 /* accept_tag2 and accept_untag2 are not supported on
4954 * pdev revision(0x20), new revision support them. The
4955 * value of this two fields will not return error when driver
4956 * send command to fireware in revision(0x20).
4957 * This two fields can not configured by user.
4958 */
4959 vport->txvlan_cfg.accept_tag2 = true;
4960 vport->txvlan_cfg.accept_untag2 = true;
4961
4962 vport->txvlan_cfg.insert_tag1_en = false;
4963 vport->txvlan_cfg.insert_tag2_en = false;
4964 vport->txvlan_cfg.default_tag1 = 0;
4965 vport->txvlan_cfg.default_tag2 = 0;
4966
4967 ret = hclge_set_vlan_tx_offload_cfg(vport);
4968 if (ret)
4969 return ret;
4970
4971 vport->rxvlan_cfg.strip_tag1_en = false;
4972 vport->rxvlan_cfg.strip_tag2_en = true;
4973 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4974 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4975
4976 ret = hclge_set_vlan_rx_offload_cfg(vport);
4977 if (ret)
4978 return ret;
4979 }
4980
4981 handle = &hdev->vport[0].nic;
4982 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4983 }
4984
4985 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4986 {
4987 struct hclge_vport *vport = hclge_get_vport(handle);
4988
4989 vport->rxvlan_cfg.strip_tag1_en = false;
4990 vport->rxvlan_cfg.strip_tag2_en = enable;
4991 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4992 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4993
4994 return hclge_set_vlan_rx_offload_cfg(vport);
4995 }
4996
4997 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
4998 {
4999 struct hclge_config_max_frm_size_cmd *req;
5000 struct hclge_desc desc;
5001 int max_frm_size;
5002 int ret;
5003
5004 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5005
5006 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
5007 max_frm_size > HCLGE_MAC_MAX_FRAME)
5008 return -EINVAL;
5009
5010 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
5011
5012 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
5013
5014 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
5015 req->max_frm_size = cpu_to_le16(max_frm_size);
5016
5017 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5018 if (ret)
5019 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
5020 else
5021 hdev->mps = max_frm_size;
5022
5023 return ret;
5024 }
5025
5026 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5027 {
5028 struct hclge_vport *vport = hclge_get_vport(handle);
5029 struct hclge_dev *hdev = vport->back;
5030 int ret;
5031
5032 ret = hclge_set_mac_mtu(hdev, new_mtu);
5033 if (ret) {
5034 dev_err(&hdev->pdev->dev,
5035 "Change mtu fail, ret =%d\n", ret);
5036 return ret;
5037 }
5038
5039 ret = hclge_buffer_alloc(hdev);
5040 if (ret)
5041 dev_err(&hdev->pdev->dev,
5042 "Allocate buffer fail, ret =%d\n", ret);
5043
5044 return ret;
5045 }
5046
5047 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5048 bool enable)
5049 {
5050 struct hclge_reset_tqp_queue_cmd *req;
5051 struct hclge_desc desc;
5052 int ret;
5053
5054 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5055
5056 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
5057 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5058 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
5059
5060 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5061 if (ret) {
5062 dev_err(&hdev->pdev->dev,
5063 "Send tqp reset cmd error, status =%d\n", ret);
5064 return ret;
5065 }
5066
5067 return 0;
5068 }
5069
5070 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5071 {
5072 struct hclge_reset_tqp_queue_cmd *req;
5073 struct hclge_desc desc;
5074 int ret;
5075
5076 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5077
5078 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
5079 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5080
5081 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5082 if (ret) {
5083 dev_err(&hdev->pdev->dev,
5084 "Get reset status error, status =%d\n", ret);
5085 return ret;
5086 }
5087
5088 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
5089 }
5090
5091 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5092 u16 queue_id)
5093 {
5094 struct hnae3_queue *queue;
5095 struct hclge_tqp *tqp;
5096
5097 queue = handle->kinfo.tqp[queue_id];
5098 tqp = container_of(queue, struct hclge_tqp, q);
5099
5100 return tqp->index;
5101 }
5102
5103 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
5104 {
5105 struct hclge_vport *vport = hclge_get_vport(handle);
5106 struct hclge_dev *hdev = vport->back;
5107 int reset_try_times = 0;
5108 int reset_status;
5109 u16 queue_gid;
5110 int ret;
5111
5112 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5113 return;
5114
5115 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5116
5117 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5118 if (ret) {
5119 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5120 return;
5121 }
5122
5123 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5124 if (ret) {
5125 dev_warn(&hdev->pdev->dev,
5126 "Send reset tqp cmd fail, ret = %d\n", ret);
5127 return;
5128 }
5129
5130 reset_try_times = 0;
5131 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5132 /* Wait for tqp hw reset */
5133 msleep(20);
5134 reset_status = hclge_get_reset_status(hdev, queue_gid);
5135 if (reset_status)
5136 break;
5137 }
5138
5139 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5140 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5141 return;
5142 }
5143
5144 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5145 if (ret) {
5146 dev_warn(&hdev->pdev->dev,
5147 "Deassert the soft reset fail, ret = %d\n", ret);
5148 return;
5149 }
5150 }
5151
5152 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5153 {
5154 struct hclge_dev *hdev = vport->back;
5155 int reset_try_times = 0;
5156 int reset_status;
5157 u16 queue_gid;
5158 int ret;
5159
5160 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5161
5162 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5163 if (ret) {
5164 dev_warn(&hdev->pdev->dev,
5165 "Send reset tqp cmd fail, ret = %d\n", ret);
5166 return;
5167 }
5168
5169 reset_try_times = 0;
5170 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5171 /* Wait for tqp hw reset */
5172 msleep(20);
5173 reset_status = hclge_get_reset_status(hdev, queue_gid);
5174 if (reset_status)
5175 break;
5176 }
5177
5178 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5179 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5180 return;
5181 }
5182
5183 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5184 if (ret)
5185 dev_warn(&hdev->pdev->dev,
5186 "Deassert the soft reset fail, ret = %d\n", ret);
5187 }
5188
5189 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5190 {
5191 struct hclge_vport *vport = hclge_get_vport(handle);
5192 struct hclge_dev *hdev = vport->back;
5193
5194 return hdev->fw_version;
5195 }
5196
5197 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5198 u32 *flowctrl_adv)
5199 {
5200 struct hclge_vport *vport = hclge_get_vport(handle);
5201 struct hclge_dev *hdev = vport->back;
5202 struct phy_device *phydev = hdev->hw.mac.phydev;
5203
5204 if (!phydev)
5205 return;
5206
5207 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5208 (phydev->advertising & ADVERTISED_Asym_Pause);
5209 }
5210
5211 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5212 {
5213 struct phy_device *phydev = hdev->hw.mac.phydev;
5214
5215 if (!phydev)
5216 return;
5217
5218 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5219
5220 if (rx_en)
5221 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5222
5223 if (tx_en)
5224 phydev->advertising ^= ADVERTISED_Asym_Pause;
5225 }
5226
5227 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5228 {
5229 int ret;
5230
5231 if (rx_en && tx_en)
5232 hdev->fc_mode_last_time = HCLGE_FC_FULL;
5233 else if (rx_en && !tx_en)
5234 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
5235 else if (!rx_en && tx_en)
5236 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
5237 else
5238 hdev->fc_mode_last_time = HCLGE_FC_NONE;
5239
5240 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
5241 return 0;
5242
5243 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5244 if (ret) {
5245 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5246 ret);
5247 return ret;
5248 }
5249
5250 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
5251
5252 return 0;
5253 }
5254
5255 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5256 {
5257 struct phy_device *phydev = hdev->hw.mac.phydev;
5258 u16 remote_advertising = 0;
5259 u16 local_advertising = 0;
5260 u32 rx_pause, tx_pause;
5261 u8 flowctl;
5262
5263 if (!phydev->link || !phydev->autoneg)
5264 return 0;
5265
5266 if (phydev->advertising & ADVERTISED_Pause)
5267 local_advertising = ADVERTISE_PAUSE_CAP;
5268
5269 if (phydev->advertising & ADVERTISED_Asym_Pause)
5270 local_advertising |= ADVERTISE_PAUSE_ASYM;
5271
5272 if (phydev->pause)
5273 remote_advertising = LPA_PAUSE_CAP;
5274
5275 if (phydev->asym_pause)
5276 remote_advertising |= LPA_PAUSE_ASYM;
5277
5278 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5279 remote_advertising);
5280 tx_pause = flowctl & FLOW_CTRL_TX;
5281 rx_pause = flowctl & FLOW_CTRL_RX;
5282
5283 if (phydev->duplex == HCLGE_MAC_HALF) {
5284 tx_pause = 0;
5285 rx_pause = 0;
5286 }
5287
5288 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5289 }
5290
5291 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5292 u32 *rx_en, u32 *tx_en)
5293 {
5294 struct hclge_vport *vport = hclge_get_vport(handle);
5295 struct hclge_dev *hdev = vport->back;
5296
5297 *auto_neg = hclge_get_autoneg(handle);
5298
5299 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5300 *rx_en = 0;
5301 *tx_en = 0;
5302 return;
5303 }
5304
5305 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5306 *rx_en = 1;
5307 *tx_en = 0;
5308 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5309 *tx_en = 1;
5310 *rx_en = 0;
5311 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5312 *rx_en = 1;
5313 *tx_en = 1;
5314 } else {
5315 *rx_en = 0;
5316 *tx_en = 0;
5317 }
5318 }
5319
5320 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5321 u32 rx_en, u32 tx_en)
5322 {
5323 struct hclge_vport *vport = hclge_get_vport(handle);
5324 struct hclge_dev *hdev = vport->back;
5325 struct phy_device *phydev = hdev->hw.mac.phydev;
5326 u32 fc_autoneg;
5327
5328 fc_autoneg = hclge_get_autoneg(handle);
5329 if (auto_neg != fc_autoneg) {
5330 dev_info(&hdev->pdev->dev,
5331 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5332 return -EOPNOTSUPP;
5333 }
5334
5335 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5336 dev_info(&hdev->pdev->dev,
5337 "Priority flow control enabled. Cannot set link flow control.\n");
5338 return -EOPNOTSUPP;
5339 }
5340
5341 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5342
5343 if (!fc_autoneg)
5344 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5345
5346 /* Only support flow control negotiation for netdev with
5347 * phy attached for now.
5348 */
5349 if (!phydev)
5350 return -EOPNOTSUPP;
5351
5352 return phy_start_aneg(phydev);
5353 }
5354
5355 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5356 u8 *auto_neg, u32 *speed, u8 *duplex)
5357 {
5358 struct hclge_vport *vport = hclge_get_vport(handle);
5359 struct hclge_dev *hdev = vport->back;
5360
5361 if (speed)
5362 *speed = hdev->hw.mac.speed;
5363 if (duplex)
5364 *duplex = hdev->hw.mac.duplex;
5365 if (auto_neg)
5366 *auto_neg = hdev->hw.mac.autoneg;
5367 }
5368
5369 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5370 {
5371 struct hclge_vport *vport = hclge_get_vport(handle);
5372 struct hclge_dev *hdev = vport->back;
5373
5374 if (media_type)
5375 *media_type = hdev->hw.mac.media_type;
5376 }
5377
5378 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5379 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5380 {
5381 struct hclge_vport *vport = hclge_get_vport(handle);
5382 struct hclge_dev *hdev = vport->back;
5383 struct phy_device *phydev = hdev->hw.mac.phydev;
5384 int mdix_ctrl, mdix, retval, is_resolved;
5385
5386 if (!phydev) {
5387 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5388 *tp_mdix = ETH_TP_MDI_INVALID;
5389 return;
5390 }
5391
5392 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5393
5394 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5395 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5396 HCLGE_PHY_MDIX_CTRL_S);
5397
5398 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5399 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5400 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5401
5402 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5403
5404 switch (mdix_ctrl) {
5405 case 0x0:
5406 *tp_mdix_ctrl = ETH_TP_MDI;
5407 break;
5408 case 0x1:
5409 *tp_mdix_ctrl = ETH_TP_MDI_X;
5410 break;
5411 case 0x3:
5412 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5413 break;
5414 default:
5415 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5416 break;
5417 }
5418
5419 if (!is_resolved)
5420 *tp_mdix = ETH_TP_MDI_INVALID;
5421 else if (mdix)
5422 *tp_mdix = ETH_TP_MDI_X;
5423 else
5424 *tp_mdix = ETH_TP_MDI;
5425 }
5426
5427 static int hclge_init_client_instance(struct hnae3_client *client,
5428 struct hnae3_ae_dev *ae_dev)
5429 {
5430 struct hclge_dev *hdev = ae_dev->priv;
5431 struct hclge_vport *vport;
5432 int i, ret;
5433
5434 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5435 vport = &hdev->vport[i];
5436
5437 switch (client->type) {
5438 case HNAE3_CLIENT_KNIC:
5439
5440 hdev->nic_client = client;
5441 vport->nic.client = client;
5442 ret = client->ops->init_instance(&vport->nic);
5443 if (ret)
5444 return ret;
5445
5446 if (hdev->roce_client &&
5447 hnae3_dev_roce_supported(hdev)) {
5448 struct hnae3_client *rc = hdev->roce_client;
5449
5450 ret = hclge_init_roce_base_info(vport);
5451 if (ret)
5452 return ret;
5453
5454 ret = rc->ops->init_instance(&vport->roce);
5455 if (ret)
5456 return ret;
5457 }
5458
5459 break;
5460 case HNAE3_CLIENT_UNIC:
5461 hdev->nic_client = client;
5462 vport->nic.client = client;
5463
5464 ret = client->ops->init_instance(&vport->nic);
5465 if (ret)
5466 return ret;
5467
5468 break;
5469 case HNAE3_CLIENT_ROCE:
5470 if (hnae3_dev_roce_supported(hdev)) {
5471 hdev->roce_client = client;
5472 vport->roce.client = client;
5473 }
5474
5475 if (hdev->roce_client && hdev->nic_client) {
5476 ret = hclge_init_roce_base_info(vport);
5477 if (ret)
5478 return ret;
5479
5480 ret = client->ops->init_instance(&vport->roce);
5481 if (ret)
5482 return ret;
5483 }
5484 }
5485 }
5486
5487 return 0;
5488 }
5489
5490 static void hclge_uninit_client_instance(struct hnae3_client *client,
5491 struct hnae3_ae_dev *ae_dev)
5492 {
5493 struct hclge_dev *hdev = ae_dev->priv;
5494 struct hclge_vport *vport;
5495 int i;
5496
5497 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5498 vport = &hdev->vport[i];
5499 if (hdev->roce_client) {
5500 hdev->roce_client->ops->uninit_instance(&vport->roce,
5501 0);
5502 hdev->roce_client = NULL;
5503 vport->roce.client = NULL;
5504 }
5505 if (client->type == HNAE3_CLIENT_ROCE)
5506 return;
5507 if (client->ops->uninit_instance) {
5508 client->ops->uninit_instance(&vport->nic, 0);
5509 hdev->nic_client = NULL;
5510 vport->nic.client = NULL;
5511 }
5512 }
5513 }
5514
5515 static int hclge_pci_init(struct hclge_dev *hdev)
5516 {
5517 struct pci_dev *pdev = hdev->pdev;
5518 struct hclge_hw *hw;
5519 int ret;
5520
5521 ret = pci_enable_device(pdev);
5522 if (ret) {
5523 dev_err(&pdev->dev, "failed to enable PCI device\n");
5524 return ret;
5525 }
5526
5527 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5528 if (ret) {
5529 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5530 if (ret) {
5531 dev_err(&pdev->dev,
5532 "can't set consistent PCI DMA");
5533 goto err_disable_device;
5534 }
5535 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5536 }
5537
5538 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5539 if (ret) {
5540 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5541 goto err_disable_device;
5542 }
5543
5544 pci_set_master(pdev);
5545 hw = &hdev->hw;
5546 hw->io_base = pcim_iomap(pdev, 2, 0);
5547 if (!hw->io_base) {
5548 dev_err(&pdev->dev, "Can't map configuration register space\n");
5549 ret = -ENOMEM;
5550 goto err_clr_master;
5551 }
5552
5553 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5554
5555 return 0;
5556 err_clr_master:
5557 pci_clear_master(pdev);
5558 pci_release_regions(pdev);
5559 err_disable_device:
5560 pci_disable_device(pdev);
5561
5562 return ret;
5563 }
5564
5565 static void hclge_pci_uninit(struct hclge_dev *hdev)
5566 {
5567 struct pci_dev *pdev = hdev->pdev;
5568
5569 pcim_iounmap(pdev, hdev->hw.io_base);
5570 pci_free_irq_vectors(pdev);
5571 pci_clear_master(pdev);
5572 pci_release_mem_regions(pdev);
5573 pci_disable_device(pdev);
5574 }
5575
5576 static void hclge_state_init(struct hclge_dev *hdev)
5577 {
5578 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5579 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5580 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5581 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5582 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5583 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5584 }
5585
5586 static void hclge_state_uninit(struct hclge_dev *hdev)
5587 {
5588 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5589
5590 if (hdev->service_timer.function)
5591 del_timer_sync(&hdev->service_timer);
5592 if (hdev->service_task.func)
5593 cancel_work_sync(&hdev->service_task);
5594 if (hdev->rst_service_task.func)
5595 cancel_work_sync(&hdev->rst_service_task);
5596 if (hdev->mbx_service_task.func)
5597 cancel_work_sync(&hdev->mbx_service_task);
5598 }
5599
5600 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5601 {
5602 struct pci_dev *pdev = ae_dev->pdev;
5603 struct hclge_dev *hdev;
5604 int ret;
5605
5606 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5607 if (!hdev) {
5608 ret = -ENOMEM;
5609 goto out;
5610 }
5611
5612 hdev->pdev = pdev;
5613 hdev->ae_dev = ae_dev;
5614 hdev->reset_type = HNAE3_NONE_RESET;
5615 ae_dev->priv = hdev;
5616
5617 ret = hclge_pci_init(hdev);
5618 if (ret) {
5619 dev_err(&pdev->dev, "PCI init failed\n");
5620 goto out;
5621 }
5622
5623 /* Firmware command queue initialize */
5624 ret = hclge_cmd_queue_init(hdev);
5625 if (ret) {
5626 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5627 goto err_pci_uninit;
5628 }
5629
5630 /* Firmware command initialize */
5631 ret = hclge_cmd_init(hdev);
5632 if (ret)
5633 goto err_cmd_uninit;
5634
5635 ret = hclge_get_cap(hdev);
5636 if (ret) {
5637 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5638 ret);
5639 goto err_cmd_uninit;
5640 }
5641
5642 ret = hclge_configure(hdev);
5643 if (ret) {
5644 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5645 goto err_cmd_uninit;
5646 }
5647
5648 ret = hclge_init_msi(hdev);
5649 if (ret) {
5650 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
5651 goto err_cmd_uninit;
5652 }
5653
5654 ret = hclge_misc_irq_init(hdev);
5655 if (ret) {
5656 dev_err(&pdev->dev,
5657 "Misc IRQ(vector0) init error, ret = %d.\n",
5658 ret);
5659 goto err_msi_uninit;
5660 }
5661
5662 ret = hclge_alloc_tqps(hdev);
5663 if (ret) {
5664 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5665 goto err_msi_irq_uninit;
5666 }
5667
5668 ret = hclge_alloc_vport(hdev);
5669 if (ret) {
5670 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5671 goto err_msi_irq_uninit;
5672 }
5673
5674 ret = hclge_map_tqp(hdev);
5675 if (ret) {
5676 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5677 goto err_msi_irq_uninit;
5678 }
5679
5680 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5681 ret = hclge_mac_mdio_config(hdev);
5682 if (ret) {
5683 dev_err(&hdev->pdev->dev,
5684 "mdio config fail ret=%d\n", ret);
5685 goto err_msi_irq_uninit;
5686 }
5687 }
5688
5689 ret = hclge_mac_init(hdev);
5690 if (ret) {
5691 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5692 goto err_mdiobus_unreg;
5693 }
5694
5695 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5696 if (ret) {
5697 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5698 goto err_mdiobus_unreg;
5699 }
5700
5701 ret = hclge_init_vlan_config(hdev);
5702 if (ret) {
5703 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5704 goto err_mdiobus_unreg;
5705 }
5706
5707 ret = hclge_tm_schd_init(hdev);
5708 if (ret) {
5709 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5710 goto err_mdiobus_unreg;
5711 }
5712
5713 hclge_rss_init_cfg(hdev);
5714 ret = hclge_rss_init_hw(hdev);
5715 if (ret) {
5716 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5717 goto err_mdiobus_unreg;
5718 }
5719
5720 ret = init_mgr_tbl(hdev);
5721 if (ret) {
5722 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
5723 goto err_mdiobus_unreg;
5724 }
5725
5726 hclge_dcb_ops_set(hdev);
5727
5728 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
5729 INIT_WORK(&hdev->service_task, hclge_service_task);
5730 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5731 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5732
5733 /* Enable MISC vector(vector0) */
5734 hclge_enable_vector(&hdev->misc_vector, true);
5735
5736 hclge_state_init(hdev);
5737
5738 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5739 return 0;
5740
5741 err_mdiobus_unreg:
5742 if (hdev->hw.mac.phydev)
5743 mdiobus_unregister(hdev->hw.mac.mdio_bus);
5744 err_msi_irq_uninit:
5745 hclge_misc_irq_uninit(hdev);
5746 err_msi_uninit:
5747 pci_free_irq_vectors(pdev);
5748 err_cmd_uninit:
5749 hclge_destroy_cmd_queue(&hdev->hw);
5750 err_pci_uninit:
5751 pcim_iounmap(pdev, hdev->hw.io_base);
5752 pci_clear_master(pdev);
5753 pci_release_regions(pdev);
5754 pci_disable_device(pdev);
5755 out:
5756 return ret;
5757 }
5758
5759 static void hclge_stats_clear(struct hclge_dev *hdev)
5760 {
5761 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5762 }
5763
5764 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5765 {
5766 struct hclge_dev *hdev = ae_dev->priv;
5767 struct pci_dev *pdev = ae_dev->pdev;
5768 int ret;
5769
5770 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5771
5772 hclge_stats_clear(hdev);
5773 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
5774
5775 ret = hclge_cmd_init(hdev);
5776 if (ret) {
5777 dev_err(&pdev->dev, "Cmd queue init failed\n");
5778 return ret;
5779 }
5780
5781 ret = hclge_get_cap(hdev);
5782 if (ret) {
5783 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5784 ret);
5785 return ret;
5786 }
5787
5788 ret = hclge_configure(hdev);
5789 if (ret) {
5790 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5791 return ret;
5792 }
5793
5794 ret = hclge_map_tqp(hdev);
5795 if (ret) {
5796 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5797 return ret;
5798 }
5799
5800 ret = hclge_mac_init(hdev);
5801 if (ret) {
5802 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5803 return ret;
5804 }
5805
5806 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5807 if (ret) {
5808 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5809 return ret;
5810 }
5811
5812 ret = hclge_init_vlan_config(hdev);
5813 if (ret) {
5814 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5815 return ret;
5816 }
5817
5818 ret = hclge_tm_init_hw(hdev);
5819 if (ret) {
5820 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
5821 return ret;
5822 }
5823
5824 ret = hclge_rss_init_hw(hdev);
5825 if (ret) {
5826 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5827 return ret;
5828 }
5829
5830 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5831 HCLGE_DRIVER_NAME);
5832
5833 return 0;
5834 }
5835
5836 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5837 {
5838 struct hclge_dev *hdev = ae_dev->priv;
5839 struct hclge_mac *mac = &hdev->hw.mac;
5840
5841 hclge_state_uninit(hdev);
5842
5843 if (mac->phydev)
5844 mdiobus_unregister(mac->mdio_bus);
5845
5846 /* Disable MISC vector(vector0) */
5847 hclge_enable_vector(&hdev->misc_vector, false);
5848 hclge_destroy_cmd_queue(&hdev->hw);
5849 hclge_misc_irq_uninit(hdev);
5850 hclge_pci_uninit(hdev);
5851 ae_dev->priv = NULL;
5852 }
5853
5854 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5855 {
5856 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5857 struct hclge_vport *vport = hclge_get_vport(handle);
5858 struct hclge_dev *hdev = vport->back;
5859
5860 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5861 }
5862
5863 static void hclge_get_channels(struct hnae3_handle *handle,
5864 struct ethtool_channels *ch)
5865 {
5866 struct hclge_vport *vport = hclge_get_vport(handle);
5867
5868 ch->max_combined = hclge_get_max_channels(handle);
5869 ch->other_count = 1;
5870 ch->max_other = 1;
5871 ch->combined_count = vport->alloc_tqps;
5872 }
5873
5874 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5875 u16 *free_tqps, u16 *max_rss_size)
5876 {
5877 struct hclge_vport *vport = hclge_get_vport(handle);
5878 struct hclge_dev *hdev = vport->back;
5879 u16 temp_tqps = 0;
5880 int i;
5881
5882 for (i = 0; i < hdev->num_tqps; i++) {
5883 if (!hdev->htqp[i].alloced)
5884 temp_tqps++;
5885 }
5886 *free_tqps = temp_tqps;
5887 *max_rss_size = hdev->rss_size_max;
5888 }
5889
5890 static void hclge_release_tqp(struct hclge_vport *vport)
5891 {
5892 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5893 struct hclge_dev *hdev = vport->back;
5894 int i;
5895
5896 for (i = 0; i < kinfo->num_tqps; i++) {
5897 struct hclge_tqp *tqp =
5898 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5899
5900 tqp->q.handle = NULL;
5901 tqp->q.tqp_index = 0;
5902 tqp->alloced = false;
5903 }
5904
5905 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5906 kinfo->tqp = NULL;
5907 }
5908
5909 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5910 {
5911 struct hclge_vport *vport = hclge_get_vport(handle);
5912 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5913 struct hclge_dev *hdev = vport->back;
5914 int cur_rss_size = kinfo->rss_size;
5915 int cur_tqps = kinfo->num_tqps;
5916 u16 tc_offset[HCLGE_MAX_TC_NUM];
5917 u16 tc_valid[HCLGE_MAX_TC_NUM];
5918 u16 tc_size[HCLGE_MAX_TC_NUM];
5919 u16 roundup_size;
5920 u32 *rss_indir;
5921 int ret, i;
5922
5923 /* Free old tqps, and reallocate with new tqp number when nic setup */
5924 hclge_release_tqp(vport);
5925
5926 ret = hclge_knic_setup(vport, new_tqps_num);
5927 if (ret) {
5928 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5929 return ret;
5930 }
5931
5932 ret = hclge_map_tqp_to_vport(hdev, vport);
5933 if (ret) {
5934 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5935 return ret;
5936 }
5937
5938 ret = hclge_tm_schd_init(hdev);
5939 if (ret) {
5940 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5941 return ret;
5942 }
5943
5944 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5945 roundup_size = ilog2(roundup_size);
5946 /* Set the RSS TC mode according to the new RSS size */
5947 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5948 tc_valid[i] = 0;
5949
5950 if (!(hdev->hw_tc_map & BIT(i)))
5951 continue;
5952
5953 tc_valid[i] = 1;
5954 tc_size[i] = roundup_size;
5955 tc_offset[i] = kinfo->rss_size * i;
5956 }
5957 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5958 if (ret)
5959 return ret;
5960
5961 /* Reinitializes the rss indirect table according to the new RSS size */
5962 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5963 if (!rss_indir)
5964 return -ENOMEM;
5965
5966 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5967 rss_indir[i] = i % kinfo->rss_size;
5968
5969 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5970 if (ret)
5971 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5972 ret);
5973
5974 kfree(rss_indir);
5975
5976 if (!ret)
5977 dev_info(&hdev->pdev->dev,
5978 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5979 cur_rss_size, kinfo->rss_size,
5980 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5981
5982 return ret;
5983 }
5984
5985 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5986 u32 *regs_num_64_bit)
5987 {
5988 struct hclge_desc desc;
5989 u32 total_num;
5990 int ret;
5991
5992 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5993 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5994 if (ret) {
5995 dev_err(&hdev->pdev->dev,
5996 "Query register number cmd failed, ret = %d.\n", ret);
5997 return ret;
5998 }
5999
6000 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
6001 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
6002
6003 total_num = *regs_num_32_bit + *regs_num_64_bit;
6004 if (!total_num)
6005 return -EINVAL;
6006
6007 return 0;
6008 }
6009
6010 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6011 void *data)
6012 {
6013 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6014
6015 struct hclge_desc *desc;
6016 u32 *reg_val = data;
6017 __le32 *desc_data;
6018 int cmd_num;
6019 int i, k, n;
6020 int ret;
6021
6022 if (regs_num == 0)
6023 return 0;
6024
6025 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6026 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6027 if (!desc)
6028 return -ENOMEM;
6029
6030 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6031 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6032 if (ret) {
6033 dev_err(&hdev->pdev->dev,
6034 "Query 32 bit register cmd failed, ret = %d.\n", ret);
6035 kfree(desc);
6036 return ret;
6037 }
6038
6039 for (i = 0; i < cmd_num; i++) {
6040 if (i == 0) {
6041 desc_data = (__le32 *)(&desc[i].data[0]);
6042 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6043 } else {
6044 desc_data = (__le32 *)(&desc[i]);
6045 n = HCLGE_32_BIT_REG_RTN_DATANUM;
6046 }
6047 for (k = 0; k < n; k++) {
6048 *reg_val++ = le32_to_cpu(*desc_data++);
6049
6050 regs_num--;
6051 if (!regs_num)
6052 break;
6053 }
6054 }
6055
6056 kfree(desc);
6057 return 0;
6058 }
6059
6060 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6061 void *data)
6062 {
6063 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6064
6065 struct hclge_desc *desc;
6066 u64 *reg_val = data;
6067 __le64 *desc_data;
6068 int cmd_num;
6069 int i, k, n;
6070 int ret;
6071
6072 if (regs_num == 0)
6073 return 0;
6074
6075 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6076 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6077 if (!desc)
6078 return -ENOMEM;
6079
6080 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6081 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6082 if (ret) {
6083 dev_err(&hdev->pdev->dev,
6084 "Query 64 bit register cmd failed, ret = %d.\n", ret);
6085 kfree(desc);
6086 return ret;
6087 }
6088
6089 for (i = 0; i < cmd_num; i++) {
6090 if (i == 0) {
6091 desc_data = (__le64 *)(&desc[i].data[0]);
6092 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6093 } else {
6094 desc_data = (__le64 *)(&desc[i]);
6095 n = HCLGE_64_BIT_REG_RTN_DATANUM;
6096 }
6097 for (k = 0; k < n; k++) {
6098 *reg_val++ = le64_to_cpu(*desc_data++);
6099
6100 regs_num--;
6101 if (!regs_num)
6102 break;
6103 }
6104 }
6105
6106 kfree(desc);
6107 return 0;
6108 }
6109
6110 static int hclge_get_regs_len(struct hnae3_handle *handle)
6111 {
6112 struct hclge_vport *vport = hclge_get_vport(handle);
6113 struct hclge_dev *hdev = vport->back;
6114 u32 regs_num_32_bit, regs_num_64_bit;
6115 int ret;
6116
6117 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6118 if (ret) {
6119 dev_err(&hdev->pdev->dev,
6120 "Get register number failed, ret = %d.\n", ret);
6121 return -EOPNOTSUPP;
6122 }
6123
6124 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6125 }
6126
6127 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6128 void *data)
6129 {
6130 struct hclge_vport *vport = hclge_get_vport(handle);
6131 struct hclge_dev *hdev = vport->back;
6132 u32 regs_num_32_bit, regs_num_64_bit;
6133 int ret;
6134
6135 *version = hdev->fw_version;
6136
6137 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6138 if (ret) {
6139 dev_err(&hdev->pdev->dev,
6140 "Get register number failed, ret = %d.\n", ret);
6141 return;
6142 }
6143
6144 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6145 if (ret) {
6146 dev_err(&hdev->pdev->dev,
6147 "Get 32 bit register failed, ret = %d.\n", ret);
6148 return;
6149 }
6150
6151 data = (u32 *)data + regs_num_32_bit;
6152 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6153 data);
6154 if (ret)
6155 dev_err(&hdev->pdev->dev,
6156 "Get 64 bit register failed, ret = %d.\n", ret);
6157 }
6158
6159 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
6160 {
6161 struct hclge_set_led_state_cmd *req;
6162 struct hclge_desc desc;
6163 int ret;
6164
6165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6166
6167 req = (struct hclge_set_led_state_cmd *)desc.data;
6168 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
6169 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6170
6171 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6172 if (ret)
6173 dev_err(&hdev->pdev->dev,
6174 "Send set led state cmd error, ret =%d\n", ret);
6175
6176 return ret;
6177 }
6178
6179 enum hclge_led_status {
6180 HCLGE_LED_OFF,
6181 HCLGE_LED_ON,
6182 HCLGE_LED_NO_CHANGE = 0xFF,
6183 };
6184
6185 static int hclge_set_led_id(struct hnae3_handle *handle,
6186 enum ethtool_phys_id_state status)
6187 {
6188 struct hclge_vport *vport = hclge_get_vport(handle);
6189 struct hclge_dev *hdev = vport->back;
6190
6191 switch (status) {
6192 case ETHTOOL_ID_ACTIVE:
6193 return hclge_set_led_status(hdev, HCLGE_LED_ON);
6194 case ETHTOOL_ID_INACTIVE:
6195 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
6196 default:
6197 return -EINVAL;
6198 }
6199 }
6200
6201 static void hclge_get_link_mode(struct hnae3_handle *handle,
6202 unsigned long *supported,
6203 unsigned long *advertising)
6204 {
6205 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6206 struct hclge_vport *vport = hclge_get_vport(handle);
6207 struct hclge_dev *hdev = vport->back;
6208 unsigned int idx = 0;
6209
6210 for (; idx < size; idx++) {
6211 supported[idx] = hdev->hw.mac.supported[idx];
6212 advertising[idx] = hdev->hw.mac.advertising[idx];
6213 }
6214 }
6215
6216 static void hclge_get_port_type(struct hnae3_handle *handle,
6217 u8 *port_type)
6218 {
6219 struct hclge_vport *vport = hclge_get_vport(handle);
6220 struct hclge_dev *hdev = vport->back;
6221 u8 media_type = hdev->hw.mac.media_type;
6222
6223 switch (media_type) {
6224 case HNAE3_MEDIA_TYPE_FIBER:
6225 *port_type = PORT_FIBRE;
6226 break;
6227 case HNAE3_MEDIA_TYPE_COPPER:
6228 *port_type = PORT_TP;
6229 break;
6230 case HNAE3_MEDIA_TYPE_UNKNOWN:
6231 default:
6232 *port_type = PORT_OTHER;
6233 break;
6234 }
6235 }
6236
6237 static const struct hnae3_ae_ops hclge_ops = {
6238 .init_ae_dev = hclge_init_ae_dev,
6239 .uninit_ae_dev = hclge_uninit_ae_dev,
6240 .init_client_instance = hclge_init_client_instance,
6241 .uninit_client_instance = hclge_uninit_client_instance,
6242 .map_ring_to_vector = hclge_map_ring_to_vector,
6243 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
6244 .get_vector = hclge_get_vector,
6245 .put_vector = hclge_put_vector,
6246 .set_promisc_mode = hclge_set_promisc_mode,
6247 .set_loopback = hclge_set_loopback,
6248 .start = hclge_ae_start,
6249 .stop = hclge_ae_stop,
6250 .get_status = hclge_get_status,
6251 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6252 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6253 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6254 .get_media_type = hclge_get_media_type,
6255 .get_rss_key_size = hclge_get_rss_key_size,
6256 .get_rss_indir_size = hclge_get_rss_indir_size,
6257 .get_rss = hclge_get_rss,
6258 .set_rss = hclge_set_rss,
6259 .set_rss_tuple = hclge_set_rss_tuple,
6260 .get_rss_tuple = hclge_get_rss_tuple,
6261 .get_tc_size = hclge_get_tc_size,
6262 .get_mac_addr = hclge_get_mac_addr,
6263 .set_mac_addr = hclge_set_mac_addr,
6264 .add_uc_addr = hclge_add_uc_addr,
6265 .rm_uc_addr = hclge_rm_uc_addr,
6266 .add_mc_addr = hclge_add_mc_addr,
6267 .rm_mc_addr = hclge_rm_mc_addr,
6268 .update_mta_status = hclge_update_mta_status,
6269 .set_autoneg = hclge_set_autoneg,
6270 .get_autoneg = hclge_get_autoneg,
6271 .get_pauseparam = hclge_get_pauseparam,
6272 .set_pauseparam = hclge_set_pauseparam,
6273 .set_mtu = hclge_set_mtu,
6274 .reset_queue = hclge_reset_tqp,
6275 .get_stats = hclge_get_stats,
6276 .update_stats = hclge_update_stats,
6277 .get_strings = hclge_get_strings,
6278 .get_sset_count = hclge_get_sset_count,
6279 .get_fw_version = hclge_get_fw_version,
6280 .get_mdix_mode = hclge_get_mdix_mode,
6281 .enable_vlan_filter = hclge_enable_vlan_filter,
6282 .set_vlan_filter = hclge_set_vlan_filter,
6283 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
6284 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
6285 .reset_event = hclge_reset_event,
6286 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6287 .set_channels = hclge_set_channels,
6288 .get_channels = hclge_get_channels,
6289 .get_flowctrl_adv = hclge_get_flowctrl_adv,
6290 .get_regs_len = hclge_get_regs_len,
6291 .get_regs = hclge_get_regs,
6292 .set_led_id = hclge_set_led_id,
6293 .get_link_mode = hclge_get_link_mode,
6294 .get_port_type = hclge_get_port_type,
6295 };
6296
6297 static struct hnae3_ae_algo ae_algo = {
6298 .ops = &hclge_ops,
6299 .pdev_id_table = ae_algo_pci_tbl,
6300 };
6301
6302 static int hclge_init(void)
6303 {
6304 pr_info("%s is initializing\n", HCLGE_NAME);
6305
6306 hnae3_register_ae_algo(&ae_algo);
6307
6308 return 0;
6309 }
6310
6311 static void hclge_exit(void)
6312 {
6313 hnae3_unregister_ae_algo(&ae_algo);
6314 }
6315 module_init(hclge_init);
6316 module_exit(hclge_exit);
6317
6318 MODULE_LICENSE("GPL");
6319 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6320 MODULE_DESCRIPTION("HCLGE Driver");
6321 MODULE_VERSION(HCLGE_MOD_VERSION);
ubuntu-bionic-kernel mirror