2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
43 static struct hnae3_ae_algo ae_algo
;
45 static const struct pci_device_id ae_algo_pci_tbl
[] = {
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
53 /* required last entry */
57 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
59 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
61 "Serdes Loopback test",
65 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
104 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
229 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
393 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
395 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
396 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
397 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap
= 0x1,
403 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
405 #define HCLGE_64_BIT_CMD_NUM 5
406 #define HCLGE_64_BIT_RTN_DATANUM 4
407 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
408 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
413 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
414 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
416 dev_err(&hdev
->pdev
->dev
,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
421 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
422 if (unlikely(i
== 0)) {
423 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
424 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
426 desc_data
= (__le64
*)(&desc
[i
]);
427 n
= HCLGE_64_BIT_RTN_DATANUM
;
429 for (k
= 0; k
< n
; k
++) {
430 *data
++ += le64_to_cpu(*desc_data
);
438 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
440 stats
->pkt_curr_buf_cnt
= 0;
441 stats
->pkt_curr_buf_tc0_cnt
= 0;
442 stats
->pkt_curr_buf_tc1_cnt
= 0;
443 stats
->pkt_curr_buf_tc2_cnt
= 0;
444 stats
->pkt_curr_buf_tc3_cnt
= 0;
445 stats
->pkt_curr_buf_tc4_cnt
= 0;
446 stats
->pkt_curr_buf_tc5_cnt
= 0;
447 stats
->pkt_curr_buf_tc6_cnt
= 0;
448 stats
->pkt_curr_buf_tc7_cnt
= 0;
451 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
453 #define HCLGE_32_BIT_CMD_NUM 8
454 #define HCLGE_32_BIT_RTN_DATANUM 8
456 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
457 struct hclge_32_bit_stats
*all_32_bit_stats
;
463 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
464 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
466 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
467 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
469 dev_err(&hdev
->pdev
->dev
,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
475 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
476 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
477 if (unlikely(i
== 0)) {
478 __le16
*desc_data_16bit
;
480 all_32_bit_stats
->igu_rx_err_pkt
+=
481 le32_to_cpu(desc
[i
].data
[0]);
483 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
484 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
485 le16_to_cpu(*desc_data_16bit
);
488 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
489 le16_to_cpu(*desc_data_16bit
);
491 desc_data
= &desc
[i
].data
[2];
492 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
494 desc_data
= (__le32
*)&desc
[i
];
495 n
= HCLGE_32_BIT_RTN_DATANUM
;
497 for (k
= 0; k
< n
; k
++) {
498 *data
++ += le32_to_cpu(*desc_data
);
506 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
508 #define HCLGE_MAC_CMD_NUM 21
509 #define HCLGE_RTN_DATA_NUM 4
511 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
512 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
517 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
518 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
520 dev_err(&hdev
->pdev
->dev
,
521 "Get MAC pkt stats fail, status = %d.\n", ret
);
526 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
527 if (unlikely(i
== 0)) {
528 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
529 n
= HCLGE_RTN_DATA_NUM
- 2;
531 desc_data
= (__le64
*)(&desc
[i
]);
532 n
= HCLGE_RTN_DATA_NUM
;
534 for (k
= 0; k
< n
; k
++) {
535 *data
++ += le64_to_cpu(*desc_data
);
543 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
545 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
546 struct hclge_vport
*vport
= hclge_get_vport(handle
);
547 struct hclge_dev
*hdev
= vport
->back
;
548 struct hnae3_queue
*queue
;
549 struct hclge_desc desc
[1];
550 struct hclge_tqp
*tqp
;
553 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
554 queue
= handle
->kinfo
.tqp
[i
];
555 tqp
= container_of(queue
, struct hclge_tqp
, q
);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc
[0],
558 HCLGE_OPC_QUERY_RX_STATUS
,
561 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
562 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
564 dev_err(&hdev
->pdev
->dev
,
565 "Query tqp stat fail, status = %d,queue = %d\n",
569 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
570 le32_to_cpu(desc
[0].data
[1]);
573 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
574 queue
= handle
->kinfo
.tqp
[i
];
575 tqp
= container_of(queue
, struct hclge_tqp
, q
);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc
[0],
578 HCLGE_OPC_QUERY_TX_STATUS
,
581 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
582 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
584 dev_err(&hdev
->pdev
->dev
,
585 "Query tqp stat fail, status = %d,queue = %d\n",
589 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
590 le32_to_cpu(desc
[0].data
[1]);
596 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
598 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
599 struct hclge_tqp
*tqp
;
603 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
604 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
605 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
608 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
609 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
610 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
616 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
618 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
620 return kinfo
->num_tqps
* (2);
623 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
625 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
629 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
630 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
631 struct hclge_tqp
, q
);
632 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
634 buff
= buff
+ ETH_GSTRING_LEN
;
637 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
638 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
639 struct hclge_tqp
, q
);
640 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
642 buff
= buff
+ ETH_GSTRING_LEN
;
648 static u64
*hclge_comm_get_stats(void *comm_stats
,
649 const struct hclge_comm_stats_str strs
[],
655 for (i
= 0; i
< size
; i
++)
656 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
661 static u8
*hclge_comm_get_strings(u32 stringset
,
662 const struct hclge_comm_stats_str strs
[],
665 char *buff
= (char *)data
;
668 if (stringset
!= ETH_SS_STATS
)
671 for (i
= 0; i
< size
; i
++) {
672 snprintf(buff
, ETH_GSTRING_LEN
,
674 buff
= buff
+ ETH_GSTRING_LEN
;
680 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
681 struct net_device_stats
*net_stats
)
683 net_stats
->tx_dropped
= 0;
684 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
685 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
686 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
688 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
689 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
690 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
691 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
692 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
694 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
695 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
697 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
698 net_stats
->rx_length_errors
=
699 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
700 net_stats
->rx_length_errors
+=
701 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
702 net_stats
->rx_over_errors
=
703 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
706 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
708 struct hnae3_handle
*handle
;
711 handle
= &hdev
->vport
[0].nic
;
712 if (handle
->client
) {
713 status
= hclge_tqps_update_stats(handle
);
715 dev_err(&hdev
->pdev
->dev
,
716 "Update TQPS stats fail, status = %d.\n",
721 status
= hclge_mac_update_stats(hdev
);
723 dev_err(&hdev
->pdev
->dev
,
724 "Update MAC stats fail, status = %d.\n", status
);
726 status
= hclge_32_bit_update_stats(hdev
);
728 dev_err(&hdev
->pdev
->dev
,
729 "Update 32 bit stats fail, status = %d.\n",
732 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
735 static void hclge_update_stats(struct hnae3_handle
*handle
,
736 struct net_device_stats
*net_stats
)
738 struct hclge_vport
*vport
= hclge_get_vport(handle
);
739 struct hclge_dev
*hdev
= vport
->back
;
740 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
746 status
= hclge_mac_update_stats(hdev
);
748 dev_err(&hdev
->pdev
->dev
,
749 "Update MAC stats fail, status = %d.\n",
752 status
= hclge_32_bit_update_stats(hdev
);
754 dev_err(&hdev
->pdev
->dev
,
755 "Update 32 bit stats fail, status = %d.\n",
758 status
= hclge_64_bit_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update 64 bit stats fail, status = %d.\n",
764 status
= hclge_tqps_update_stats(handle
);
766 dev_err(&hdev
->pdev
->dev
,
767 "Update TQPS stats fail, status = %d.\n",
770 hclge_update_netstat(hw_stats
, net_stats
);
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
775 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
777 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
779 struct hclge_vport
*vport
= hclge_get_vport(handle
);
780 struct hclge_dev
*hdev
= vport
->back
;
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
788 if (stringset
== ETH_SS_TEST
) {
789 /* clear loopback bit flags at first */
790 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
791 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
792 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
793 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
795 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
799 handle
->flags
|= HNAE3_SUPPORT_SERDES_LOOPBACK
;
800 } else if (stringset
== ETH_SS_STATS
) {
801 count
= ARRAY_SIZE(g_mac_stats_string
) +
802 ARRAY_SIZE(g_all_32bit_stats_string
) +
803 ARRAY_SIZE(g_all_64bit_stats_string
) +
804 hclge_tqps_get_sset_count(handle
, stringset
);
810 static void hclge_get_strings(struct hnae3_handle
*handle
,
814 u8
*p
= (char *)data
;
817 if (stringset
== ETH_SS_STATS
) {
818 size
= ARRAY_SIZE(g_mac_stats_string
);
819 p
= hclge_comm_get_strings(stringset
,
823 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
824 p
= hclge_comm_get_strings(stringset
,
825 g_all_32bit_stats_string
,
828 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
829 p
= hclge_comm_get_strings(stringset
,
830 g_all_64bit_stats_string
,
833 p
= hclge_tqps_get_strings(handle
, p
);
834 } else if (stringset
== ETH_SS_TEST
) {
835 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
837 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
839 p
+= ETH_GSTRING_LEN
;
841 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
843 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
845 p
+= ETH_GSTRING_LEN
;
847 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
849 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
851 p
+= ETH_GSTRING_LEN
;
856 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
858 struct hclge_vport
*vport
= hclge_get_vport(handle
);
859 struct hclge_dev
*hdev
= vport
->back
;
862 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
864 ARRAY_SIZE(g_mac_stats_string
),
866 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
867 g_all_32bit_stats_string
,
868 ARRAY_SIZE(g_all_32bit_stats_string
),
870 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
871 g_all_64bit_stats_string
,
872 ARRAY_SIZE(g_all_64bit_stats_string
),
874 p
= hclge_tqps_get_stats(handle
, p
);
877 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
878 struct hclge_func_status_cmd
*status
)
880 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
883 /* Set the pf to main pf */
884 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
885 hdev
->flag
|= HCLGE_FLAG_MAIN
;
887 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
892 static int hclge_query_function_status(struct hclge_dev
*hdev
)
894 struct hclge_func_status_cmd
*req
;
895 struct hclge_desc desc
;
899 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
900 req
= (struct hclge_func_status_cmd
*)desc
.data
;
903 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
905 dev_err(&hdev
->pdev
->dev
,
906 "query function status failed %d.\n",
912 /* Check pf reset is done */
915 usleep_range(1000, 2000);
916 } while (timeout
++ < 5);
918 ret
= hclge_parse_func_status(hdev
, req
);
923 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
925 struct hclge_pf_res_cmd
*req
;
926 struct hclge_desc desc
;
929 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
930 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
932 dev_err(&hdev
->pdev
->dev
,
933 "query pf resource failed %d.\n", ret
);
937 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
938 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
939 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
941 if (hnae3_dev_roce_supported(hdev
)) {
943 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
944 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
946 /* PF should have NIC vectors and Roce vectors,
947 * NIC vectors are queued before Roce vectors.
949 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
952 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
953 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
959 static int hclge_parse_speed(int speed_cmd
, int *speed
)
963 *speed
= HCLGE_MAC_SPEED_10M
;
966 *speed
= HCLGE_MAC_SPEED_100M
;
969 *speed
= HCLGE_MAC_SPEED_1G
;
972 *speed
= HCLGE_MAC_SPEED_10G
;
975 *speed
= HCLGE_MAC_SPEED_25G
;
978 *speed
= HCLGE_MAC_SPEED_40G
;
981 *speed
= HCLGE_MAC_SPEED_50G
;
984 *speed
= HCLGE_MAC_SPEED_100G
;
993 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
996 unsigned long *supported
= hdev
->hw
.mac
.supported
;
998 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
999 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1002 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1003 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1006 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1007 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1010 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1011 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1014 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1015 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1018 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1019 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1022 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1024 u8 media_type
= hdev
->hw
.mac
.media_type
;
1026 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1029 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1032 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1034 struct hclge_cfg_param_cmd
*req
;
1035 u64 mac_addr_tmp_high
;
1039 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1041 /* get the configuration */
1042 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1045 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1046 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1047 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1048 HCLGE_CFG_TQP_DESC_N_M
,
1049 HCLGE_CFG_TQP_DESC_N_S
);
1051 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1052 HCLGE_CFG_PHY_ADDR_M
,
1053 HCLGE_CFG_PHY_ADDR_S
);
1054 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1055 HCLGE_CFG_MEDIA_TP_M
,
1056 HCLGE_CFG_MEDIA_TP_S
);
1057 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1058 HCLGE_CFG_RX_BUF_LEN_M
,
1059 HCLGE_CFG_RX_BUF_LEN_S
);
1060 /* get mac_address */
1061 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1062 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1063 HCLGE_CFG_MAC_ADDR_H_M
,
1064 HCLGE_CFG_MAC_ADDR_H_S
);
1066 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1068 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1069 HCLGE_CFG_DEFAULT_SPEED_M
,
1070 HCLGE_CFG_DEFAULT_SPEED_S
);
1071 cfg
->rss_size_max
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1072 HCLGE_CFG_RSS_SIZE_M
,
1073 HCLGE_CFG_RSS_SIZE_S
);
1075 for (i
= 0; i
< ETH_ALEN
; i
++)
1076 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1078 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1079 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1081 cfg
->speed_ability
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1082 HCLGE_CFG_SPEED_ABILITY_M
,
1083 HCLGE_CFG_SPEED_ABILITY_S
);
1086 /* hclge_get_cfg: query the static parameter from flash
1087 * @hdev: pointer to struct hclge_dev
1088 * @hcfg: the config structure to be getted
1090 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1092 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1093 struct hclge_cfg_param_cmd
*req
;
1096 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1099 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1100 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1102 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1103 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1104 /* Len should be united by 4 bytes when send to hardware */
1105 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1106 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1107 req
->offset
= cpu_to_le32(offset
);
1110 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1112 dev_err(&hdev
->pdev
->dev
,
1113 "get config failed %d.\n", ret
);
1117 hclge_parse_cfg(hcfg
, desc
);
1121 static int hclge_get_cap(struct hclge_dev
*hdev
)
1125 ret
= hclge_query_function_status(hdev
);
1127 dev_err(&hdev
->pdev
->dev
,
1128 "query function status error %d.\n", ret
);
1132 /* get pf resource */
1133 ret
= hclge_query_pf_resource(hdev
);
1135 dev_err(&hdev
->pdev
->dev
,
1136 "query pf resource error %d.\n", ret
);
1143 static int hclge_configure(struct hclge_dev
*hdev
)
1145 struct hclge_cfg cfg
;
1148 ret
= hclge_get_cfg(hdev
, &cfg
);
1150 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1154 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1155 hdev
->base_tqp_pid
= 0;
1156 hdev
->rss_size_max
= cfg
.rss_size_max
;
1157 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1158 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1159 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1160 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1161 hdev
->num_desc
= cfg
.tqp_desc_num
;
1162 hdev
->tm_info
.num_pg
= 1;
1163 hdev
->tc_max
= cfg
.tc_num
;
1164 hdev
->tm_info
.hw_pfc_map
= 0;
1166 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1168 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1172 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1174 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1175 (hdev
->tc_max
< 1)) {
1176 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1181 /* Dev does not support DCB */
1182 if (!hnae3_dev_dcb_supported(hdev
)) {
1186 hdev
->pfc_max
= hdev
->tc_max
;
1189 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1191 /* Currently not support uncontiuous tc */
1192 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1193 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1195 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1200 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1203 struct hclge_cfg_tso_status_cmd
*req
;
1204 struct hclge_desc desc
;
1207 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1209 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1212 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1213 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1214 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1217 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1218 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1219 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1221 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1224 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1226 struct hclge_tqp
*tqp
;
1229 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1230 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1236 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1237 tqp
->dev
= &hdev
->pdev
->dev
;
1240 tqp
->q
.ae_algo
= &ae_algo
;
1241 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1242 tqp
->q
.desc_num
= hdev
->num_desc
;
1243 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1244 i
* HCLGE_TQP_REG_SIZE
;
1252 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1253 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1255 struct hclge_tqp_map_cmd
*req
;
1256 struct hclge_desc desc
;
1259 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1261 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1262 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1263 req
->tqp_vf
= func_id
;
1264 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1265 1 << HCLGE_TQP_MAP_EN_B
;
1266 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1268 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1270 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1278 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1279 struct hnae3_queue
**tqp
, u16 num_tqps
)
1281 struct hclge_dev
*hdev
= vport
->back
;
1284 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1285 alloced
< num_tqps
; i
++) {
1286 if (!hdev
->htqp
[i
].alloced
) {
1287 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1288 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1289 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1290 hdev
->htqp
[i
].alloced
= true;
1294 vport
->alloc_tqps
= num_tqps
;
1299 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1301 struct hnae3_handle
*nic
= &vport
->nic
;
1302 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1303 struct hclge_dev
*hdev
= vport
->back
;
1306 kinfo
->num_desc
= hdev
->num_desc
;
1307 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1308 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1310 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1311 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1313 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1314 if (hdev
->hw_tc_map
& BIT(i
)) {
1315 kinfo
->tc_info
[i
].enable
= true;
1316 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1317 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1318 kinfo
->tc_info
[i
].tc
= i
;
1320 /* Set to default queue if TC is disable */
1321 kinfo
->tc_info
[i
].enable
= false;
1322 kinfo
->tc_info
[i
].tqp_offset
= 0;
1323 kinfo
->tc_info
[i
].tqp_count
= 1;
1324 kinfo
->tc_info
[i
].tc
= 0;
1328 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1329 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1333 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1335 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1342 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1343 struct hclge_vport
*vport
)
1345 struct hnae3_handle
*nic
= &vport
->nic
;
1346 struct hnae3_knic_private_info
*kinfo
;
1349 kinfo
= &nic
->kinfo
;
1350 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1351 struct hclge_tqp
*q
=
1352 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1356 is_pf
= !(vport
->vport_id
);
1357 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1366 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1368 struct hclge_vport
*vport
= hdev
->vport
;
1371 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1372 for (i
= 0; i
< num_vport
; i
++) {
1375 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1385 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1387 /* this would be initialized later */
1390 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1392 struct hnae3_handle
*nic
= &vport
->nic
;
1393 struct hclge_dev
*hdev
= vport
->back
;
1396 nic
->pdev
= hdev
->pdev
;
1397 nic
->ae_algo
= &ae_algo
;
1398 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1400 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1401 ret
= hclge_knic_setup(vport
, num_tqps
);
1403 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1408 hclge_unic_setup(vport
, num_tqps
);
1414 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1416 struct pci_dev
*pdev
= hdev
->pdev
;
1417 struct hclge_vport
*vport
;
1423 /* We need to alloc a vport for main NIC of PF */
1424 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1426 if (hdev
->num_tqps
< num_vport
) {
1427 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1428 hdev
->num_tqps
, num_vport
);
1432 /* Alloc the same number of TQPs for every vport */
1433 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1434 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1436 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1441 hdev
->vport
= vport
;
1442 hdev
->num_alloc_vport
= num_vport
;
1444 if (IS_ENABLED(CONFIG_PCI_IOV
))
1445 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1447 for (i
= 0; i
< num_vport
; i
++) {
1449 vport
->vport_id
= i
;
1452 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1454 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1457 "vport setup failed for vport %d, %d\n",
1468 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1469 struct hclge_pkt_buf_alloc
*buf_alloc
)
1471 /* TX buffer size is unit by 128 byte */
1472 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1473 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1474 struct hclge_tx_buff_alloc_cmd
*req
;
1475 struct hclge_desc desc
;
1479 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1481 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1482 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1483 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1485 req
->tx_pkt_buff
[i
] =
1486 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1487 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1490 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1492 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1500 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1501 struct hclge_pkt_buf_alloc
*buf_alloc
)
1503 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1506 dev_err(&hdev
->pdev
->dev
,
1507 "tx buffer alloc failed %d\n", ret
);
1514 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1518 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1519 if (hdev
->hw_tc_map
& BIT(i
))
1524 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1528 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1529 if (hdev
->hw_tc_map
& BIT(i
) &&
1530 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1535 /* Get the number of pfc enabled TCs, which have private buffer */
1536 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1537 struct hclge_pkt_buf_alloc
*buf_alloc
)
1539 struct hclge_priv_buf
*priv
;
1542 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1543 priv
= &buf_alloc
->priv_buf
[i
];
1544 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1552 /* Get the number of pfc disabled TCs, which have private buffer */
1553 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1554 struct hclge_pkt_buf_alloc
*buf_alloc
)
1556 struct hclge_priv_buf
*priv
;
1559 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1560 priv
= &buf_alloc
->priv_buf
[i
];
1561 if (hdev
->hw_tc_map
& BIT(i
) &&
1562 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1570 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1572 struct hclge_priv_buf
*priv
;
1576 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1577 priv
= &buf_alloc
->priv_buf
[i
];
1579 rx_priv
+= priv
->buf_size
;
1584 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1586 u32 i
, total_tx_size
= 0;
1588 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1589 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1591 return total_tx_size
;
1594 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1595 struct hclge_pkt_buf_alloc
*buf_alloc
,
1598 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1599 int tc_num
, pfc_enable_num
;
1604 tc_num
= hclge_get_tc_num(hdev
);
1605 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1607 if (hnae3_dev_dcb_supported(hdev
))
1608 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1610 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1612 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1613 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1615 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1617 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1618 if (rx_all
<= rx_priv
+ shared_std
)
1621 shared_buf
= rx_all
- rx_priv
;
1622 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1623 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1624 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1626 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1627 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1628 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1629 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1630 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1632 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1633 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1640 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1641 struct hclge_pkt_buf_alloc
*buf_alloc
)
1645 total_size
= hdev
->pkt_buf_size
;
1647 /* alloc tx buffer for all enabled tc */
1648 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1649 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1651 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1654 if (hdev
->hw_tc_map
& BIT(i
))
1655 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1657 priv
->tx_buf_size
= 0;
1659 total_size
-= priv
->tx_buf_size
;
1665 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1666 * @hdev: pointer to struct hclge_dev
1667 * @buf_alloc: pointer to buffer calculation data
1668 * @return: 0: calculate sucessful, negative: fail
1670 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1671 struct hclge_pkt_buf_alloc
*buf_alloc
)
1673 u32 rx_all
= hdev
->pkt_buf_size
;
1674 int no_pfc_priv_num
, pfc_priv_num
;
1675 struct hclge_priv_buf
*priv
;
1678 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1680 /* When DCB is not supported, rx private
1681 * buffer is not allocated.
1683 if (!hnae3_dev_dcb_supported(hdev
)) {
1684 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1690 /* step 1, try to alloc private buffer for all enabled tc */
1691 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1692 priv
= &buf_alloc
->priv_buf
[i
];
1693 if (hdev
->hw_tc_map
& BIT(i
)) {
1695 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1696 priv
->wl
.low
= hdev
->mps
;
1697 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1698 priv
->buf_size
= priv
->wl
.high
+
1702 priv
->wl
.high
= 2 * hdev
->mps
;
1703 priv
->buf_size
= priv
->wl
.high
;
1713 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1716 /* step 2, try to decrease the buffer size of
1717 * no pfc TC's private buffer
1719 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1720 priv
= &buf_alloc
->priv_buf
[i
];
1727 if (!(hdev
->hw_tc_map
& BIT(i
)))
1732 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1734 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1735 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1738 priv
->wl
.high
= hdev
->mps
;
1739 priv
->buf_size
= priv
->wl
.high
;
1743 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1746 /* step 3, try to reduce the number of pfc disabled TCs,
1747 * which have private buffer
1749 /* get the total no pfc enable TC number, which have private buffer */
1750 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1752 /* let the last to be cleared first */
1753 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1754 priv
= &buf_alloc
->priv_buf
[i
];
1756 if (hdev
->hw_tc_map
& BIT(i
) &&
1757 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1758 /* Clear the no pfc TC private buffer */
1766 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1767 no_pfc_priv_num
== 0)
1771 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1774 /* step 4, try to reduce the number of pfc enabled TCs
1775 * which have private buffer.
1777 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1779 /* let the last to be cleared first */
1780 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1781 priv
= &buf_alloc
->priv_buf
[i
];
1783 if (hdev
->hw_tc_map
& BIT(i
) &&
1784 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1785 /* Reduce the number of pfc TC with private buffer */
1793 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1797 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1803 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1804 struct hclge_pkt_buf_alloc
*buf_alloc
)
1806 struct hclge_rx_priv_buff_cmd
*req
;
1807 struct hclge_desc desc
;
1811 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1812 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1814 /* Alloc private buffer TCs */
1815 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1816 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1819 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1821 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1825 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1826 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1828 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1830 dev_err(&hdev
->pdev
->dev
,
1831 "rx private buffer alloc cmd failed %d\n", ret
);
1838 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1840 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1841 struct hclge_pkt_buf_alloc
*buf_alloc
)
1843 struct hclge_rx_priv_wl_buf
*req
;
1844 struct hclge_priv_buf
*priv
;
1845 struct hclge_desc desc
[2];
1849 for (i
= 0; i
< 2; i
++) {
1850 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1852 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1854 /* The first descriptor set the NEXT bit to 1 */
1856 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1858 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1860 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1861 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1863 priv
= &buf_alloc
->priv_buf
[idx
];
1864 req
->tc_wl
[j
].high
=
1865 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1866 req
->tc_wl
[j
].high
|=
1867 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1868 HCLGE_RX_PRIV_EN_B
);
1870 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1871 req
->tc_wl
[j
].low
|=
1872 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1873 HCLGE_RX_PRIV_EN_B
);
1877 /* Send 2 descriptor at one time */
1878 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1880 dev_err(&hdev
->pdev
->dev
,
1881 "rx private waterline config cmd failed %d\n",
1888 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1889 struct hclge_pkt_buf_alloc
*buf_alloc
)
1891 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1892 struct hclge_rx_com_thrd
*req
;
1893 struct hclge_desc desc
[2];
1894 struct hclge_tc_thrd
*tc
;
1898 for (i
= 0; i
< 2; i
++) {
1899 hclge_cmd_setup_basic_desc(&desc
[i
],
1900 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1901 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1903 /* The first descriptor set the NEXT bit to 1 */
1905 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1907 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1909 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1910 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1912 req
->com_thrd
[j
].high
=
1913 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1914 req
->com_thrd
[j
].high
|=
1915 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1916 HCLGE_RX_PRIV_EN_B
);
1917 req
->com_thrd
[j
].low
=
1918 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1919 req
->com_thrd
[j
].low
|=
1920 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1921 HCLGE_RX_PRIV_EN_B
);
1925 /* Send 2 descriptors at one time */
1926 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1928 dev_err(&hdev
->pdev
->dev
,
1929 "common threshold config cmd failed %d\n", ret
);
1935 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1936 struct hclge_pkt_buf_alloc
*buf_alloc
)
1938 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1939 struct hclge_rx_com_wl
*req
;
1940 struct hclge_desc desc
;
1943 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1945 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1946 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1948 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1949 HCLGE_RX_PRIV_EN_B
);
1951 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1953 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1954 HCLGE_RX_PRIV_EN_B
);
1956 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1958 dev_err(&hdev
->pdev
->dev
,
1959 "common waterline config cmd failed %d\n", ret
);
1966 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1968 struct hclge_pkt_buf_alloc
*pkt_buf
;
1971 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1975 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1977 dev_err(&hdev
->pdev
->dev
,
1978 "could not calc tx buffer size for all TCs %d\n", ret
);
1982 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1984 dev_err(&hdev
->pdev
->dev
,
1985 "could not alloc tx buffers %d\n", ret
);
1989 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1991 dev_err(&hdev
->pdev
->dev
,
1992 "could not calc rx priv buffer size for all TCs %d\n",
1997 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1999 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
2004 if (hnae3_dev_dcb_supported(hdev
)) {
2005 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
2007 dev_err(&hdev
->pdev
->dev
,
2008 "could not configure rx private waterline %d\n",
2013 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
2015 dev_err(&hdev
->pdev
->dev
,
2016 "could not configure common threshold %d\n",
2022 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2024 dev_err(&hdev
->pdev
->dev
,
2025 "could not configure common waterline %d\n", ret
);
2032 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2034 struct hnae3_handle
*roce
= &vport
->roce
;
2035 struct hnae3_handle
*nic
= &vport
->nic
;
2037 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2039 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2040 vport
->back
->num_msi_left
== 0)
2043 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2045 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2046 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2048 roce
->pdev
= nic
->pdev
;
2049 roce
->ae_algo
= nic
->ae_algo
;
2050 roce
->numa_node_mask
= nic
->numa_node_mask
;
2055 static int hclge_init_msi(struct hclge_dev
*hdev
)
2057 struct pci_dev
*pdev
= hdev
->pdev
;
2061 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2062 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2065 "failed(%d) to allocate MSI/MSI-X vectors\n",
2069 if (vectors
< hdev
->num_msi
)
2070 dev_warn(&hdev
->pdev
->dev
,
2071 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2072 hdev
->num_msi
, vectors
);
2074 hdev
->num_msi
= vectors
;
2075 hdev
->num_msi_left
= vectors
;
2076 hdev
->base_msi_vector
= pdev
->irq
;
2077 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2078 HCLGE_ROCE_VECTOR_OFFSET
;
2080 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2081 sizeof(u16
), GFP_KERNEL
);
2082 if (!hdev
->vector_status
) {
2083 pci_free_irq_vectors(pdev
);
2087 for (i
= 0; i
< hdev
->num_msi
; i
++)
2088 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2090 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2091 sizeof(int), GFP_KERNEL
);
2092 if (!hdev
->vector_irq
) {
2093 pci_free_irq_vectors(pdev
);
2100 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2102 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2104 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2105 mac
->duplex
= (u8
)duplex
;
2107 mac
->duplex
= HCLGE_MAC_FULL
;
2112 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2114 struct hclge_config_mac_speed_dup_cmd
*req
;
2115 struct hclge_desc desc
;
2118 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2120 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2122 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2125 case HCLGE_MAC_SPEED_10M
:
2126 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2127 HCLGE_CFG_SPEED_S
, 6);
2129 case HCLGE_MAC_SPEED_100M
:
2130 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2131 HCLGE_CFG_SPEED_S
, 7);
2133 case HCLGE_MAC_SPEED_1G
:
2134 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2135 HCLGE_CFG_SPEED_S
, 0);
2137 case HCLGE_MAC_SPEED_10G
:
2138 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2139 HCLGE_CFG_SPEED_S
, 1);
2141 case HCLGE_MAC_SPEED_25G
:
2142 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2143 HCLGE_CFG_SPEED_S
, 2);
2145 case HCLGE_MAC_SPEED_40G
:
2146 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2147 HCLGE_CFG_SPEED_S
, 3);
2149 case HCLGE_MAC_SPEED_50G
:
2150 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2151 HCLGE_CFG_SPEED_S
, 4);
2153 case HCLGE_MAC_SPEED_100G
:
2154 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2155 HCLGE_CFG_SPEED_S
, 5);
2158 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2162 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2165 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2167 dev_err(&hdev
->pdev
->dev
,
2168 "mac speed/duplex config cmd failed %d.\n", ret
);
2172 hclge_check_speed_dup(hdev
, duplex
, speed
);
2177 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2180 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2181 struct hclge_dev
*hdev
= vport
->back
;
2183 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2186 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2189 struct hclge_query_an_speed_dup_cmd
*req
;
2190 struct hclge_desc desc
;
2194 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2196 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2197 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2199 dev_err(&hdev
->pdev
->dev
,
2200 "mac speed/autoneg/duplex query cmd failed %d\n",
2205 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2206 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2207 HCLGE_QUERY_SPEED_S
);
2209 ret
= hclge_parse_speed(speed_tmp
, speed
);
2211 dev_err(&hdev
->pdev
->dev
,
2212 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2219 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2221 struct hclge_config_auto_neg_cmd
*req
;
2222 struct hclge_desc desc
;
2226 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2228 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2229 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2230 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2232 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2234 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2242 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2244 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2245 struct hclge_dev
*hdev
= vport
->back
;
2247 return hclge_set_autoneg_en(hdev
, enable
);
2250 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2252 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2253 struct hclge_dev
*hdev
= vport
->back
;
2254 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2257 return phydev
->autoneg
;
2259 return hdev
->hw
.mac
.autoneg
;
2262 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2266 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2267 struct hclge_desc desc
;
2270 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2271 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2273 hnae_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2275 ether_addr_copy(req
->mac_mask
, mac_mask
);
2277 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2279 dev_err(&hdev
->pdev
->dev
,
2280 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2286 static int hclge_mac_init(struct hclge_dev
*hdev
)
2288 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2289 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2290 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2291 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2292 struct hclge_vport
*vport
;
2297 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2299 dev_err(&hdev
->pdev
->dev
,
2300 "Config mac speed dup fail ret=%d\n", ret
);
2306 /* Initialize the MTA table work mode */
2307 hdev
->enable_mta
= true;
2308 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2310 ret
= hclge_set_mta_filter_mode(hdev
,
2311 hdev
->mta_mac_sel_type
,
2314 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2319 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
2320 vport
= &hdev
->vport
[i
];
2321 vport
->accept_mta_mc
= false;
2323 memset(vport
->mta_shadow
, 0, sizeof(vport
->mta_shadow
));
2324 ret
= hclge_cfg_func_mta_filter(hdev
, vport
->vport_id
, false);
2326 dev_err(&hdev
->pdev
->dev
,
2327 "set mta filter mode fail ret=%d\n", ret
);
2332 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2334 dev_err(&hdev
->pdev
->dev
,
2335 "set default mac_vlan_mask fail ret=%d\n", ret
);
2344 ret
= hclge_set_mtu(handle
, mtu
);
2346 dev_err(&hdev
->pdev
->dev
,
2347 "set mtu failed ret=%d\n", ret
);
2354 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2356 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2357 schedule_work(&hdev
->mbx_service_task
);
2360 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2362 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2363 schedule_work(&hdev
->rst_service_task
);
2366 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2368 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2369 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2370 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2371 (void)schedule_work(&hdev
->service_task
);
2374 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2376 struct hclge_link_status_cmd
*req
;
2377 struct hclge_desc desc
;
2381 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2382 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2384 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2389 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2390 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2392 return !!link_status
;
2395 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2400 mac_state
= hclge_get_mac_link_status(hdev
);
2402 if (hdev
->hw
.mac
.phydev
) {
2403 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2404 link_stat
= mac_state
&
2405 hdev
->hw
.mac
.phydev
->link
;
2410 link_stat
= mac_state
;
2416 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2418 struct hnae3_client
*rclient
= hdev
->roce_client
;
2419 struct hnae3_client
*client
= hdev
->nic_client
;
2420 struct hnae3_handle
*rhandle
;
2421 struct hnae3_handle
*handle
;
2427 state
= hclge_get_mac_phy_link(hdev
);
2428 if (state
!= hdev
->hw
.mac
.link
) {
2429 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2430 handle
= &hdev
->vport
[i
].nic
;
2431 client
->ops
->link_status_change(handle
, state
);
2432 rhandle
= &hdev
->vport
[i
].roce
;
2433 if (rclient
&& rclient
->ops
->link_status_change
)
2434 rclient
->ops
->link_status_change(rhandle
,
2437 hdev
->hw
.mac
.link
= state
;
2441 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2443 struct hclge_mac mac
= hdev
->hw
.mac
;
2448 /* get the speed and duplex as autoneg'result from mac cmd when phy
2451 if (mac
.phydev
|| !mac
.autoneg
)
2454 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2456 dev_err(&hdev
->pdev
->dev
,
2457 "mac autoneg/speed/duplex query failed %d\n", ret
);
2461 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2462 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2464 dev_err(&hdev
->pdev
->dev
,
2465 "mac speed/duplex config failed %d\n", ret
);
2473 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2475 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2476 struct hclge_dev
*hdev
= vport
->back
;
2478 return hclge_update_speed_duplex(hdev
);
2481 static int hclge_get_status(struct hnae3_handle
*handle
)
2483 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2484 struct hclge_dev
*hdev
= vport
->back
;
2486 hclge_update_link_status(hdev
);
2488 return hdev
->hw
.mac
.link
;
2491 static void hclge_service_timer(struct timer_list
*t
)
2493 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2495 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2496 hdev
->hw_stats
.stats_timer
++;
2497 hclge_task_schedule(hdev
);
2500 static void hclge_service_complete(struct hclge_dev
*hdev
)
2502 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2504 /* Flush memory before next watchdog */
2505 smp_mb__before_atomic();
2506 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2509 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2514 /* fetch the events from their corresponding regs */
2515 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2516 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2518 /* Assumption: If by any chance reset and mailbox events are reported
2519 * together then we will only process reset event in this go and will
2520 * defer the processing of the mailbox events. Since, we would have not
2521 * cleared RX CMDQ event this time we would receive again another
2522 * interrupt from H/W just for the mailbox.
2525 /* check for vector0 reset event sources */
2526 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2527 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2528 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2529 return HCLGE_VECTOR0_EVENT_RST
;
2532 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2533 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2534 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2535 return HCLGE_VECTOR0_EVENT_RST
;
2538 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2539 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2540 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2541 return HCLGE_VECTOR0_EVENT_RST
;
2544 /* check for vector0 mailbox(=CMDQ RX) event source */
2545 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2546 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2547 *clearval
= cmdq_src_reg
;
2548 return HCLGE_VECTOR0_EVENT_MBX
;
2551 return HCLGE_VECTOR0_EVENT_OTHER
;
2554 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2557 switch (event_type
) {
2558 case HCLGE_VECTOR0_EVENT_RST
:
2559 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2561 case HCLGE_VECTOR0_EVENT_MBX
:
2562 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2567 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2569 writel(enable
? 1 : 0, vector
->addr
);
2572 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2574 struct hclge_dev
*hdev
= data
;
2578 hclge_enable_vector(&hdev
->misc_vector
, false);
2579 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2581 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2582 switch (event_cause
) {
2583 case HCLGE_VECTOR0_EVENT_RST
:
2584 hclge_reset_task_schedule(hdev
);
2586 case HCLGE_VECTOR0_EVENT_MBX
:
2587 /* If we are here then,
2588 * 1. Either we are not handling any mbx task and we are not
2591 * 2. We could be handling a mbx task but nothing more is
2593 * In both cases, we should schedule mbx task as there are more
2594 * mbx messages reported by this interrupt.
2596 hclge_mbx_task_schedule(hdev
);
2599 dev_warn(&hdev
->pdev
->dev
,
2600 "received unknown or unhandled event of vector0\n");
2604 /* clear the source of interrupt if it is not cause by reset */
2605 if (event_cause
!= HCLGE_VECTOR0_EVENT_RST
) {
2606 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2607 hclge_enable_vector(&hdev
->misc_vector
, true);
2613 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2615 if (hdev
->vector_status
[vector_id
] == HCLGE_INVALID_VPORT
) {
2616 dev_warn(&hdev
->pdev
->dev
,
2617 "vector(vector_id %d) has been freed.\n", vector_id
);
2621 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2622 hdev
->num_msi_left
+= 1;
2623 hdev
->num_msi_used
-= 1;
2626 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2628 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2630 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2632 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2633 hdev
->vector_status
[0] = 0;
2635 hdev
->num_msi_left
-= 1;
2636 hdev
->num_msi_used
+= 1;
2639 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2643 hclge_get_misc_vector(hdev
);
2645 /* this would be explicitly freed in the end */
2646 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2647 0, "hclge_misc", hdev
);
2649 hclge_free_vector(hdev
, 0);
2650 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2651 hdev
->misc_vector
.vector_irq
);
2657 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2659 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2660 hclge_free_vector(hdev
, 0);
2663 static int hclge_notify_client(struct hclge_dev
*hdev
,
2664 enum hnae3_reset_notify_type type
)
2666 struct hnae3_client
*rclient
= hdev
->roce_client
;
2667 struct hnae3_client
*client
= hdev
->nic_client
;
2668 struct hnae3_handle
*handle
;
2672 if (!client
->ops
->reset_notify
)
2675 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2676 handle
= &hdev
->vport
[i
].nic
;
2677 ret
= client
->ops
->reset_notify(handle
, type
);
2679 dev_err(&hdev
->pdev
->dev
,
2680 "notify nic client failed %d", ret
);
2684 if (rclient
&& rclient
->ops
->reset_notify
) {
2685 handle
= &hdev
->vport
[i
].roce
;
2686 ret
= rclient
->ops
->reset_notify(handle
, type
);
2688 dev_err(&hdev
->pdev
->dev
,
2689 "notify roce client failed %d", ret
);
2698 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2700 #define HCLGE_RESET_WATI_MS 100
2701 #define HCLGE_RESET_WAIT_CNT 5
2702 u32 val
, reg
, reg_bit
;
2705 switch (hdev
->reset_type
) {
2706 case HNAE3_GLOBAL_RESET
:
2707 reg
= HCLGE_GLOBAL_RESET_REG
;
2708 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2710 case HNAE3_CORE_RESET
:
2711 reg
= HCLGE_GLOBAL_RESET_REG
;
2712 reg_bit
= HCLGE_CORE_RESET_BIT
;
2714 case HNAE3_FUNC_RESET
:
2715 reg
= HCLGE_FUN_RST_ING
;
2716 reg_bit
= HCLGE_FUN_RST_ING_B
;
2719 dev_err(&hdev
->pdev
->dev
,
2720 "Wait for unsupported reset type: %d\n",
2725 val
= hclge_read_dev(&hdev
->hw
, reg
);
2726 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2727 msleep(HCLGE_RESET_WATI_MS
);
2728 val
= hclge_read_dev(&hdev
->hw
, reg
);
2732 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2733 dev_warn(&hdev
->pdev
->dev
,
2734 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2741 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2743 struct hclge_desc desc
;
2744 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2747 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2748 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2749 req
->fun_reset_vfid
= func_id
;
2751 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2753 dev_err(&hdev
->pdev
->dev
,
2754 "send function reset cmd fail, status =%d\n", ret
);
2759 static void hclge_do_reset(struct hclge_dev
*hdev
)
2761 struct pci_dev
*pdev
= hdev
->pdev
;
2764 switch (hdev
->reset_type
) {
2765 case HNAE3_GLOBAL_RESET
:
2766 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2767 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2768 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2769 dev_info(&pdev
->dev
, "Global Reset requested\n");
2771 case HNAE3_CORE_RESET
:
2772 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2773 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2774 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2775 dev_info(&pdev
->dev
, "Core Reset requested\n");
2777 case HNAE3_FUNC_RESET
:
2778 dev_info(&pdev
->dev
, "PF Reset requested\n");
2779 hclge_func_reset_cmd(hdev
, 0);
2780 /* schedule again to check later */
2781 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2782 hclge_reset_task_schedule(hdev
);
2785 dev_warn(&pdev
->dev
,
2786 "Unsupported reset type: %d\n", hdev
->reset_type
);
2791 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2792 unsigned long *addr
)
2794 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2796 /* return the highest priority reset level amongst all */
2797 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2798 rst_level
= HNAE3_GLOBAL_RESET
;
2799 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2800 rst_level
= HNAE3_CORE_RESET
;
2801 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2802 rst_level
= HNAE3_IMP_RESET
;
2803 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2804 rst_level
= HNAE3_FUNC_RESET
;
2806 /* now, clear all other resets */
2807 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2808 clear_bit(HNAE3_CORE_RESET
, addr
);
2809 clear_bit(HNAE3_IMP_RESET
, addr
);
2810 clear_bit(HNAE3_FUNC_RESET
, addr
);
2815 static void hclge_clear_reset_cause(struct hclge_dev
*hdev
)
2819 switch (hdev
->reset_type
) {
2820 case HNAE3_IMP_RESET
:
2821 clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2823 case HNAE3_GLOBAL_RESET
:
2824 clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2826 case HNAE3_CORE_RESET
:
2827 clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2830 dev_warn(&hdev
->pdev
->dev
, "Unsupported reset event to clear:%d",
2838 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, clearval
);
2839 hclge_enable_vector(&hdev
->misc_vector
, true);
2842 static void hclge_reset(struct hclge_dev
*hdev
)
2844 /* perform reset of the stack & ae device for a client */
2846 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2848 if (!hclge_reset_wait(hdev
)) {
2850 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2851 hclge_reset_ae_dev(hdev
->ae_dev
);
2852 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2855 hclge_clear_reset_cause(hdev
);
2857 /* schedule again to check pending resets later */
2858 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2859 hclge_reset_task_schedule(hdev
);
2862 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2865 static void hclge_reset_event(struct hnae3_handle
*handle
)
2867 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2868 struct hclge_dev
*hdev
= vport
->back
;
2870 /* check if this is a new reset request and we are not here just because
2871 * last reset attempt did not succeed and watchdog hit us again. We will
2872 * know this if last reset request did not occur very recently (watchdog
2873 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2874 * In case of new request we reset the "reset level" to PF reset.
2876 if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2877 handle
->reset_level
= HNAE3_FUNC_RESET
;
2879 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2880 handle
->reset_level
);
2882 /* request reset & schedule reset task */
2883 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2884 hclge_reset_task_schedule(hdev
);
2886 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2887 handle
->reset_level
++;
2889 handle
->last_reset_time
= jiffies
;
2892 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2894 /* check if there is any ongoing reset in the hardware. This status can
2895 * be checked from reset_pending. If there is then, we need to wait for
2896 * hardware to complete reset.
2897 * a. If we are able to figure out in reasonable time that hardware
2898 * has fully resetted then, we can proceed with driver, client
2900 * b. else, we can come back later to check this status so re-sched
2903 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2904 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2907 /* check if we got any *new* reset requests to be honored */
2908 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2909 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2910 hclge_do_reset(hdev
);
2912 hdev
->reset_type
= HNAE3_NONE_RESET
;
2915 static void hclge_reset_service_task(struct work_struct
*work
)
2917 struct hclge_dev
*hdev
=
2918 container_of(work
, struct hclge_dev
, rst_service_task
);
2920 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2923 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2925 hclge_reset_subtask(hdev
);
2927 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2930 static void hclge_mailbox_service_task(struct work_struct
*work
)
2932 struct hclge_dev
*hdev
=
2933 container_of(work
, struct hclge_dev
, mbx_service_task
);
2935 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2938 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2940 hclge_mbx_handler(hdev
);
2942 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2945 static void hclge_service_task(struct work_struct
*work
)
2947 struct hclge_dev
*hdev
=
2948 container_of(work
, struct hclge_dev
, service_task
);
2950 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2951 hclge_update_stats_for_all(hdev
);
2952 hdev
->hw_stats
.stats_timer
= 0;
2955 hclge_update_speed_duplex(hdev
);
2956 hclge_update_link_status(hdev
);
2957 hclge_service_complete(hdev
);
2960 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2962 /* VF handle has no client */
2963 if (!handle
->client
)
2964 return container_of(handle
, struct hclge_vport
, nic
);
2965 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2966 return container_of(handle
, struct hclge_vport
, roce
);
2968 return container_of(handle
, struct hclge_vport
, nic
);
2971 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2972 struct hnae3_vector_info
*vector_info
)
2974 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2975 struct hnae3_vector_info
*vector
= vector_info
;
2976 struct hclge_dev
*hdev
= vport
->back
;
2980 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2982 for (j
= 0; j
< vector_num
; j
++) {
2983 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2984 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2985 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2986 vector
->io_addr
= hdev
->hw
.io_base
+
2987 HCLGE_VECTOR_REG_BASE
+
2988 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2990 HCLGE_VECTOR_VF_OFFSET
;
2991 hdev
->vector_status
[i
] = vport
->vport_id
;
2992 hdev
->vector_irq
[i
] = vector
->vector
;
3001 hdev
->num_msi_left
-= alloc
;
3002 hdev
->num_msi_used
+= alloc
;
3007 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
3011 for (i
= 0; i
< hdev
->num_msi
; i
++)
3012 if (vector
== hdev
->vector_irq
[i
])
3018 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
3020 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3021 struct hclge_dev
*hdev
= vport
->back
;
3024 vector_id
= hclge_get_vector_index(hdev
, vector
);
3025 if (vector_id
< 0) {
3026 dev_err(&hdev
->pdev
->dev
,
3027 "Get vector index fail. vector_id =%d\n", vector_id
);
3031 hclge_free_vector(hdev
, vector_id
);
3036 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
3038 return HCLGE_RSS_KEY_SIZE
;
3041 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
3043 return HCLGE_RSS_IND_TBL_SIZE
;
3046 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3047 const u8 hfunc
, const u8
*key
)
3049 struct hclge_rss_config_cmd
*req
;
3050 struct hclge_desc desc
;
3055 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3057 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3058 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3061 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3062 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3064 if (key_offset
== 2)
3066 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3068 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3070 memcpy(req
->hash_key
,
3071 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3073 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3075 dev_err(&hdev
->pdev
->dev
,
3076 "Configure RSS config fail, status = %d\n",
3084 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3086 struct hclge_rss_indirection_table_cmd
*req
;
3087 struct hclge_desc desc
;
3091 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3093 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3094 hclge_cmd_setup_basic_desc
3095 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3097 req
->start_table_index
=
3098 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3099 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3101 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3102 req
->rss_result
[j
] =
3103 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3105 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3107 dev_err(&hdev
->pdev
->dev
,
3108 "Configure rss indir table fail,status = %d\n",
3116 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3117 u16
*tc_size
, u16
*tc_offset
)
3119 struct hclge_rss_tc_mode_cmd
*req
;
3120 struct hclge_desc desc
;
3124 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3125 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3127 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3130 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3131 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3132 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3133 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3134 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3136 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3139 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3141 dev_err(&hdev
->pdev
->dev
,
3142 "Configure rss tc mode fail, status = %d\n", ret
);
3149 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3151 struct hclge_rss_input_tuple_cmd
*req
;
3152 struct hclge_desc desc
;
3155 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3157 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3159 /* Get the tuple cfg from pf */
3160 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3161 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3162 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3163 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3164 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3165 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3166 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3167 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3168 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3170 dev_err(&hdev
->pdev
->dev
,
3171 "Configure rss input fail, status = %d\n", ret
);
3178 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3181 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3184 /* Get hash algorithm */
3186 *hfunc
= vport
->rss_algo
;
3188 /* Get the RSS Key required by the user */
3190 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3192 /* Get indirect table */
3194 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3195 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3200 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3201 const u8
*key
, const u8 hfunc
)
3203 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3204 struct hclge_dev
*hdev
= vport
->back
;
3208 /* Set the RSS Hash Key if specififed by the user */
3211 if (hfunc
== ETH_RSS_HASH_TOP
||
3212 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3213 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3216 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3220 /* Update the shadow RSS key with user specified qids */
3221 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3222 vport
->rss_algo
= hash_algo
;
3225 /* Update the shadow RSS table with user specified qids */
3226 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3227 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3229 /* Update the hardware */
3230 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3233 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3235 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3237 if (nfc
->data
& RXH_L4_B_2_3
)
3238 hash_sets
|= HCLGE_D_PORT_BIT
;
3240 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3242 if (nfc
->data
& RXH_IP_SRC
)
3243 hash_sets
|= HCLGE_S_IP_BIT
;
3245 hash_sets
&= ~HCLGE_S_IP_BIT
;
3247 if (nfc
->data
& RXH_IP_DST
)
3248 hash_sets
|= HCLGE_D_IP_BIT
;
3250 hash_sets
&= ~HCLGE_D_IP_BIT
;
3252 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3253 hash_sets
|= HCLGE_V_TAG_BIT
;
3258 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3259 struct ethtool_rxnfc
*nfc
)
3261 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3262 struct hclge_dev
*hdev
= vport
->back
;
3263 struct hclge_rss_input_tuple_cmd
*req
;
3264 struct hclge_desc desc
;
3268 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3269 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3272 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3273 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3275 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3276 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3277 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3278 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3279 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3280 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3281 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3282 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3284 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3285 switch (nfc
->flow_type
) {
3287 req
->ipv4_tcp_en
= tuple_sets
;
3290 req
->ipv6_tcp_en
= tuple_sets
;
3293 req
->ipv4_udp_en
= tuple_sets
;
3296 req
->ipv6_udp_en
= tuple_sets
;
3299 req
->ipv4_sctp_en
= tuple_sets
;
3302 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3303 (nfc
->data
& RXH_L4_B_2_3
))
3306 req
->ipv6_sctp_en
= tuple_sets
;
3309 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3312 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3318 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3320 dev_err(&hdev
->pdev
->dev
,
3321 "Set rss tuple fail, status = %d\n", ret
);
3325 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3326 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3327 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3328 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3329 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3330 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3331 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3332 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3336 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3337 struct ethtool_rxnfc
*nfc
)
3339 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3344 switch (nfc
->flow_type
) {
3346 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3349 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3352 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3355 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3358 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3361 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3365 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3374 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3375 nfc
->data
|= RXH_L4_B_2_3
;
3376 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3377 nfc
->data
|= RXH_L4_B_0_1
;
3378 if (tuple_sets
& HCLGE_D_IP_BIT
)
3379 nfc
->data
|= RXH_IP_DST
;
3380 if (tuple_sets
& HCLGE_S_IP_BIT
)
3381 nfc
->data
|= RXH_IP_SRC
;
3386 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3388 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3389 struct hclge_dev
*hdev
= vport
->back
;
3391 return hdev
->rss_size_max
;
3394 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3396 struct hclge_vport
*vport
= hdev
->vport
;
3397 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3398 u16 rss_size
= vport
[0].alloc_rss_size
;
3399 u8
*key
= vport
[0].rss_hash_key
;
3400 u8 hfunc
= vport
[0].rss_algo
;
3401 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3402 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3403 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3407 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3411 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3415 ret
= hclge_set_rss_input_tuple(hdev
);
3419 /* Each TC have the same queue size, and tc_size set to hardware is
3420 * the log2 of roundup power of two of rss_size, the acutal queue
3421 * size is limited by indirection table.
3423 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3424 dev_err(&hdev
->pdev
->dev
,
3425 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3430 roundup_size
= roundup_pow_of_two(rss_size
);
3431 roundup_size
= ilog2(roundup_size
);
3433 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3436 if (!(hdev
->hw_tc_map
& BIT(i
)))
3440 tc_size
[i
] = roundup_size
;
3441 tc_offset
[i
] = rss_size
* i
;
3444 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3447 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3449 struct hclge_vport
*vport
= hdev
->vport
;
3452 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3453 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3454 vport
[j
].rss_indirection_tbl
[i
] =
3455 i
% vport
[j
].alloc_rss_size
;
3459 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3461 struct hclge_vport
*vport
= hdev
->vport
;
3464 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3465 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3466 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3467 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3468 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3469 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3470 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3471 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3472 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3473 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3474 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3475 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3476 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3477 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3478 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3479 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3480 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3482 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3484 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3487 hclge_rss_indir_init_cfg(hdev
);
3490 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3491 int vector_id
, bool en
,
3492 struct hnae3_ring_chain_node
*ring_chain
)
3494 struct hclge_dev
*hdev
= vport
->back
;
3495 struct hnae3_ring_chain_node
*node
;
3496 struct hclge_desc desc
;
3497 struct hclge_ctrl_vector_chain_cmd
*req
3498 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3499 enum hclge_cmd_status status
;
3500 enum hclge_opcode_type op
;
3501 u16 tqp_type_and_id
;
3504 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3505 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3506 req
->int_vector_id
= vector_id
;
3509 for (node
= ring_chain
; node
; node
= node
->next
) {
3510 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3511 hnae_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3513 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3514 hnae_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3515 HCLGE_TQP_ID_S
, node
->tqp_index
);
3516 hnae_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3518 hnae_get_field(node
->int_gl_idx
,
3519 HNAE3_RING_GL_IDX_M
,
3520 HNAE3_RING_GL_IDX_S
));
3521 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3522 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3523 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3524 req
->vfid
= vport
->vport_id
;
3526 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3528 dev_err(&hdev
->pdev
->dev
,
3529 "Map TQP fail, status is %d.\n",
3535 hclge_cmd_setup_basic_desc(&desc
,
3538 req
->int_vector_id
= vector_id
;
3543 req
->int_cause_num
= i
;
3544 req
->vfid
= vport
->vport_id
;
3545 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3547 dev_err(&hdev
->pdev
->dev
,
3548 "Map TQP fail, status is %d.\n", status
);
3556 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3558 struct hnae3_ring_chain_node
*ring_chain
)
3560 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3561 struct hclge_dev
*hdev
= vport
->back
;
3564 vector_id
= hclge_get_vector_index(hdev
, vector
);
3565 if (vector_id
< 0) {
3566 dev_err(&hdev
->pdev
->dev
,
3567 "Get vector index fail. vector_id =%d\n", vector_id
);
3571 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3574 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3576 struct hnae3_ring_chain_node
*ring_chain
)
3578 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3579 struct hclge_dev
*hdev
= vport
->back
;
3582 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3585 vector_id
= hclge_get_vector_index(hdev
, vector
);
3586 if (vector_id
< 0) {
3587 dev_err(&handle
->pdev
->dev
,
3588 "Get vector index fail. ret =%d\n", vector_id
);
3592 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3594 dev_err(&handle
->pdev
->dev
,
3595 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3602 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3603 struct hclge_promisc_param
*param
)
3605 struct hclge_promisc_cfg_cmd
*req
;
3606 struct hclge_desc desc
;
3609 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3611 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3612 req
->vf_id
= param
->vf_id
;
3614 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3615 * pdev revision(0x20), new revision support them. The
3616 * value of this two fields will not return error when driver
3617 * send command to fireware in revision(0x20).
3619 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
) |
3620 HCLGE_PROMISC_TX_EN_B
| HCLGE_PROMISC_RX_EN_B
;
3622 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3624 dev_err(&hdev
->pdev
->dev
,
3625 "Set promisc mode fail, status is %d.\n", ret
);
3631 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3632 bool en_mc
, bool en_bc
, int vport_id
)
3637 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3639 param
->enable
= HCLGE_PROMISC_EN_UC
;
3641 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3643 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3644 param
->vf_id
= vport_id
;
3647 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, bool en_uc_pmc
,
3650 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3651 struct hclge_dev
*hdev
= vport
->back
;
3652 struct hclge_promisc_param param
;
3654 hclge_promisc_param_init(¶m
, en_uc_pmc
, en_mc_pmc
, true,
3656 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3659 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3661 struct hclge_desc desc
;
3662 struct hclge_config_mac_mode_cmd
*req
=
3663 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3667 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3668 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3669 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3670 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3671 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3672 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3673 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3674 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3675 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3676 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3677 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3678 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3679 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3680 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3681 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3682 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3684 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3686 dev_err(&hdev
->pdev
->dev
,
3687 "mac enable fail, ret =%d.\n", ret
);
3690 static int hclge_set_mac_loopback(struct hclge_dev
*hdev
, bool en
)
3692 struct hclge_config_mac_mode_cmd
*req
;
3693 struct hclge_desc desc
;
3697 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3698 /* 1 Read out the MAC mode config at first */
3699 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, true);
3700 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3702 dev_err(&hdev
->pdev
->dev
,
3703 "mac loopback get fail, ret =%d.\n", ret
);
3707 /* 2 Then setup the loopback flag */
3708 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3709 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, en
? 1 : 0);
3711 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3713 /* 3 Config mac work mode with loopback flag
3714 * and its original configure parameters
3716 hclge_cmd_reuse_desc(&desc
, false);
3717 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3719 dev_err(&hdev
->pdev
->dev
,
3720 "mac loopback set fail, ret =%d.\n", ret
);
3724 static int hclge_set_serdes_loopback(struct hclge_dev
*hdev
, bool en
)
3726 #define HCLGE_SERDES_RETRY_MS 10
3727 #define HCLGE_SERDES_RETRY_NUM 100
3728 struct hclge_serdes_lb_cmd
*req
;
3729 struct hclge_desc desc
;
3732 req
= (struct hclge_serdes_lb_cmd
*)&desc
.data
[0];
3733 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SERDES_LOOPBACK
, false);
3736 req
->enable
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3737 req
->mask
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3739 req
->mask
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3742 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3744 dev_err(&hdev
->pdev
->dev
,
3745 "serdes loopback set fail, ret = %d\n", ret
);
3750 msleep(HCLGE_SERDES_RETRY_MS
);
3751 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SERDES_LOOPBACK
,
3753 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3755 dev_err(&hdev
->pdev
->dev
,
3756 "serdes loopback get, ret = %d\n", ret
);
3759 } while (++i
< HCLGE_SERDES_RETRY_NUM
&&
3760 !(req
->result
& HCLGE_CMD_SERDES_DONE_B
));
3762 if (!(req
->result
& HCLGE_CMD_SERDES_DONE_B
)) {
3763 dev_err(&hdev
->pdev
->dev
, "serdes loopback set timeout\n");
3765 } else if (!(req
->result
& HCLGE_CMD_SERDES_SUCCESS_B
)) {
3766 dev_err(&hdev
->pdev
->dev
, "serdes loopback set failed in fw\n");
3773 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3774 enum hnae3_loop loop_mode
, bool en
)
3776 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3777 struct hclge_dev
*hdev
= vport
->back
;
3780 switch (loop_mode
) {
3781 case HNAE3_MAC_INTER_LOOP_MAC
:
3782 ret
= hclge_set_mac_loopback(hdev
, en
);
3784 case HNAE3_MAC_INTER_LOOP_SERDES
:
3785 ret
= hclge_set_serdes_loopback(hdev
, en
);
3789 dev_err(&hdev
->pdev
->dev
,
3790 "loop_mode %d is not supported\n", loop_mode
);
3797 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3798 int stream_id
, bool enable
)
3800 struct hclge_desc desc
;
3801 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3802 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3805 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3806 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3807 req
->stream_id
= cpu_to_le16(stream_id
);
3808 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3810 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3812 dev_err(&hdev
->pdev
->dev
,
3813 "Tqp enable fail, status =%d.\n", ret
);
3817 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3819 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3820 struct hnae3_queue
*queue
;
3821 struct hclge_tqp
*tqp
;
3824 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3825 queue
= handle
->kinfo
.tqp
[i
];
3826 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3827 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3831 static int hclge_ae_start(struct hnae3_handle
*handle
)
3833 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3834 struct hclge_dev
*hdev
= vport
->back
;
3837 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3838 hclge_tqp_enable(hdev
, i
, 0, true);
3841 hclge_cfg_mac_mode(hdev
, true);
3842 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3843 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3844 hdev
->hw
.mac
.link
= 0;
3846 /* reset tqp stats */
3847 hclge_reset_tqp_stats(handle
);
3849 ret
= hclge_mac_start_phy(hdev
);
3856 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3858 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3859 struct hclge_dev
*hdev
= vport
->back
;
3862 del_timer_sync(&hdev
->service_timer
);
3863 cancel_work_sync(&hdev
->service_task
);
3864 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
3866 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
3867 hclge_mac_stop_phy(hdev
);
3871 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3872 hclge_tqp_enable(hdev
, i
, 0, false);
3875 hclge_cfg_mac_mode(hdev
, false);
3877 hclge_mac_stop_phy(hdev
);
3879 /* reset tqp stats */
3880 hclge_reset_tqp_stats(handle
);
3881 del_timer_sync(&hdev
->service_timer
);
3882 cancel_work_sync(&hdev
->service_task
);
3883 hclge_update_link_status(hdev
);
3886 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3887 u16 cmdq_resp
, u8 resp_code
,
3888 enum hclge_mac_vlan_tbl_opcode op
)
3890 struct hclge_dev
*hdev
= vport
->back
;
3891 int return_status
= -EIO
;
3894 dev_err(&hdev
->pdev
->dev
,
3895 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3900 if (op
== HCLGE_MAC_VLAN_ADD
) {
3901 if ((!resp_code
) || (resp_code
== 1)) {
3903 } else if (resp_code
== 2) {
3904 return_status
= -ENOSPC
;
3905 dev_err(&hdev
->pdev
->dev
,
3906 "add mac addr failed for uc_overflow.\n");
3907 } else if (resp_code
== 3) {
3908 return_status
= -ENOSPC
;
3909 dev_err(&hdev
->pdev
->dev
,
3910 "add mac addr failed for mc_overflow.\n");
3912 dev_err(&hdev
->pdev
->dev
,
3913 "add mac addr failed for undefined, code=%d.\n",
3916 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3919 } else if (resp_code
== 1) {
3920 return_status
= -ENOENT
;
3921 dev_dbg(&hdev
->pdev
->dev
,
3922 "remove mac addr failed for miss.\n");
3924 dev_err(&hdev
->pdev
->dev
,
3925 "remove mac addr failed for undefined, code=%d.\n",
3928 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3931 } else if (resp_code
== 1) {
3932 return_status
= -ENOENT
;
3933 dev_dbg(&hdev
->pdev
->dev
,
3934 "lookup mac addr failed for miss.\n");
3936 dev_err(&hdev
->pdev
->dev
,
3937 "lookup mac addr failed for undefined, code=%d.\n",
3941 return_status
= -EINVAL
;
3942 dev_err(&hdev
->pdev
->dev
,
3943 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3947 return return_status
;
3950 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3955 if (vfid
> 255 || vfid
< 0)
3958 if (vfid
>= 0 && vfid
<= 191) {
3959 word_num
= vfid
/ 32;
3960 bit_num
= vfid
% 32;
3962 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3964 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3966 word_num
= (vfid
- 192) / 32;
3967 bit_num
= vfid
% 32;
3969 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3971 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3977 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3979 #define HCLGE_DESC_NUMBER 3
3980 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3983 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3984 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3985 if (desc
[i
].data
[j
])
3991 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3994 const unsigned char *mac_addr
= addr
;
3995 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3996 (mac_addr
[0]) | (mac_addr
[1] << 8);
3997 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3999 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
4000 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
4003 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
4006 u16 high_val
= addr
[1] | (addr
[0] << 8);
4007 struct hclge_dev
*hdev
= vport
->back
;
4008 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
4009 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
4014 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
4015 enum hclge_mta_dmac_sel_type mta_mac_sel
,
4018 struct hclge_mta_filter_mode_cmd
*req
;
4019 struct hclge_desc desc
;
4022 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
4023 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
4025 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
4027 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
4028 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
4030 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4032 dev_err(&hdev
->pdev
->dev
,
4033 "Config mat filter mode failed for cmd_send, ret =%d.\n",
4041 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
4045 struct hclge_cfg_func_mta_filter_cmd
*req
;
4046 struct hclge_desc desc
;
4049 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
4050 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
4052 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
4054 req
->function_id
= func_id
;
4056 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4058 dev_err(&hdev
->pdev
->dev
,
4059 "Config func_id enable failed for cmd_send, ret =%d.\n",
4067 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
4071 struct hclge_dev
*hdev
= vport
->back
;
4072 struct hclge_cfg_func_mta_item_cmd
*req
;
4073 struct hclge_desc desc
;
4077 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
4078 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
4079 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
4081 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
4082 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
4083 req
->item_idx
= cpu_to_le16(item_idx
);
4085 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4087 dev_err(&hdev
->pdev
->dev
,
4088 "Config mta table item failed for cmd_send, ret =%d.\n",
4094 set_bit(idx
, vport
->mta_shadow
);
4096 clear_bit(idx
, vport
->mta_shadow
);
4101 static int hclge_update_mta_status(struct hnae3_handle
*handle
)
4103 unsigned long mta_status
[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE
)];
4104 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4105 struct net_device
*netdev
= handle
->kinfo
.netdev
;
4106 struct netdev_hw_addr
*ha
;
4109 memset(mta_status
, 0, sizeof(mta_status
));
4111 /* update mta_status from mc addr list */
4112 netdev_for_each_mc_addr(ha
, netdev
) {
4113 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, ha
->addr
);
4114 set_bit(tbl_idx
, mta_status
);
4117 return hclge_update_mta_status_common(vport
, mta_status
,
4118 0, HCLGE_MTA_TBL_SIZE
, true);
4121 int hclge_update_mta_status_common(struct hclge_vport
*vport
,
4122 unsigned long *status
,
4127 struct hclge_dev
*hdev
= vport
->back
;
4128 u16 update_max
= idx
+ count
;
4134 /* setup mta check range */
4135 if (update_filter
) {
4137 check_max
= HCLGE_MTA_TBL_SIZE
;
4140 check_max
= update_max
;
4144 /* check and update all mta item */
4145 for (; i
< check_max
; i
++) {
4146 /* ignore unused item */
4147 if (!test_bit(i
, vport
->mta_shadow
))
4150 /* if i in update range then update it */
4151 if (i
>= idx
&& i
< update_max
)
4152 if (!test_bit(i
- idx
, status
))
4153 hclge_set_mta_table_item(vport
, i
, false);
4155 if (!used
&& test_bit(i
, vport
->mta_shadow
))
4159 /* no longer use mta, disable it */
4160 if (vport
->accept_mta_mc
&& update_filter
&& !used
) {
4161 ret
= hclge_cfg_func_mta_filter(hdev
,
4165 dev_err(&hdev
->pdev
->dev
,
4166 "disable func mta filter fail ret=%d\n",
4169 vport
->accept_mta_mc
= false;
4175 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4176 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4178 struct hclge_dev
*hdev
= vport
->back
;
4179 struct hclge_desc desc
;
4184 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4186 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4188 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4190 dev_err(&hdev
->pdev
->dev
,
4191 "del mac addr failed for cmd_send, ret =%d.\n",
4195 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4196 retval
= le16_to_cpu(desc
.retval
);
4198 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4199 HCLGE_MAC_VLAN_REMOVE
);
4202 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4203 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4204 struct hclge_desc
*desc
,
4207 struct hclge_dev
*hdev
= vport
->back
;
4212 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4214 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4215 memcpy(desc
[0].data
,
4217 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4218 hclge_cmd_setup_basic_desc(&desc
[1],
4219 HCLGE_OPC_MAC_VLAN_ADD
,
4221 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4222 hclge_cmd_setup_basic_desc(&desc
[2],
4223 HCLGE_OPC_MAC_VLAN_ADD
,
4225 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4227 memcpy(desc
[0].data
,
4229 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4230 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4233 dev_err(&hdev
->pdev
->dev
,
4234 "lookup mac addr failed for cmd_send, ret =%d.\n",
4238 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4239 retval
= le16_to_cpu(desc
[0].retval
);
4241 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4242 HCLGE_MAC_VLAN_LKUP
);
4245 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4246 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4247 struct hclge_desc
*mc_desc
)
4249 struct hclge_dev
*hdev
= vport
->back
;
4256 struct hclge_desc desc
;
4258 hclge_cmd_setup_basic_desc(&desc
,
4259 HCLGE_OPC_MAC_VLAN_ADD
,
4261 memcpy(desc
.data
, req
,
4262 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4263 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4264 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4265 retval
= le16_to_cpu(desc
.retval
);
4267 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4269 HCLGE_MAC_VLAN_ADD
);
4271 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4272 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4273 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4274 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4275 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4276 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4277 memcpy(mc_desc
[0].data
, req
,
4278 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4279 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4280 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4281 retval
= le16_to_cpu(mc_desc
[0].retval
);
4283 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4285 HCLGE_MAC_VLAN_ADD
);
4289 dev_err(&hdev
->pdev
->dev
,
4290 "add mac addr failed for cmd_send, ret =%d.\n",
4298 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4299 const unsigned char *addr
)
4301 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4303 return hclge_add_uc_addr_common(vport
, addr
);
4306 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4307 const unsigned char *addr
)
4309 struct hclge_dev
*hdev
= vport
->back
;
4310 struct hclge_mac_vlan_tbl_entry_cmd req
;
4311 struct hclge_desc desc
;
4312 u16 egress_port
= 0;
4315 /* mac addr check */
4316 if (is_zero_ether_addr(addr
) ||
4317 is_broadcast_ether_addr(addr
) ||
4318 is_multicast_ether_addr(addr
)) {
4319 dev_err(&hdev
->pdev
->dev
,
4320 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4322 is_zero_ether_addr(addr
),
4323 is_broadcast_ether_addr(addr
),
4324 is_multicast_ether_addr(addr
));
4328 memset(&req
, 0, sizeof(req
));
4329 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4331 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4332 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4334 req
.egress_port
= cpu_to_le16(egress_port
);
4336 hclge_prepare_mac_addr(&req
, addr
);
4338 /* Lookup the mac address in the mac_vlan table, and add
4339 * it if the entry is inexistent. Repeated unicast entry
4340 * is not allowed in the mac vlan table.
4342 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4344 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4346 /* check if we just hit the duplicate */
4350 dev_err(&hdev
->pdev
->dev
,
4351 "PF failed to add unicast entry(%pM) in the MAC table\n",
4357 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4358 const unsigned char *addr
)
4360 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4362 return hclge_rm_uc_addr_common(vport
, addr
);
4365 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4366 const unsigned char *addr
)
4368 struct hclge_dev
*hdev
= vport
->back
;
4369 struct hclge_mac_vlan_tbl_entry_cmd req
;
4372 /* mac addr check */
4373 if (is_zero_ether_addr(addr
) ||
4374 is_broadcast_ether_addr(addr
) ||
4375 is_multicast_ether_addr(addr
)) {
4376 dev_dbg(&hdev
->pdev
->dev
,
4377 "Remove mac err! invalid mac:%pM.\n",
4382 memset(&req
, 0, sizeof(req
));
4383 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4384 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4385 hclge_prepare_mac_addr(&req
, addr
);
4386 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4391 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4392 const unsigned char *addr
)
4394 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4396 return hclge_add_mc_addr_common(vport
, addr
);
4399 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4400 const unsigned char *addr
)
4402 struct hclge_dev
*hdev
= vport
->back
;
4403 struct hclge_mac_vlan_tbl_entry_cmd req
;
4404 struct hclge_desc desc
[3];
4408 /* mac addr check */
4409 if (!is_multicast_ether_addr(addr
)) {
4410 dev_err(&hdev
->pdev
->dev
,
4411 "Add mc mac err! invalid mac:%pM.\n",
4415 memset(&req
, 0, sizeof(req
));
4416 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4417 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4418 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4419 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4420 hclge_prepare_mac_addr(&req
, addr
);
4421 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4423 /* This mac addr exist, update VFID for it */
4424 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4425 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4427 /* This mac addr do not exist, add new entry for it */
4428 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4429 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4430 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4431 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4432 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4435 /* If mc mac vlan table is full, use MTA table */
4436 if (status
== -ENOSPC
) {
4437 if (!vport
->accept_mta_mc
) {
4438 status
= hclge_cfg_func_mta_filter(hdev
,
4442 dev_err(&hdev
->pdev
->dev
,
4443 "set mta filter mode fail ret=%d\n",
4447 vport
->accept_mta_mc
= true;
4450 /* Set MTA table for this MAC address */
4451 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4452 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4458 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4459 const unsigned char *addr
)
4461 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4463 return hclge_rm_mc_addr_common(vport
, addr
);
4466 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4467 const unsigned char *addr
)
4469 struct hclge_dev
*hdev
= vport
->back
;
4470 struct hclge_mac_vlan_tbl_entry_cmd req
;
4471 enum hclge_cmd_status status
;
4472 struct hclge_desc desc
[3];
4474 /* mac addr check */
4475 if (!is_multicast_ether_addr(addr
)) {
4476 dev_dbg(&hdev
->pdev
->dev
,
4477 "Remove mc mac err! invalid mac:%pM.\n",
4482 memset(&req
, 0, sizeof(req
));
4483 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4484 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4485 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4486 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4487 hclge_prepare_mac_addr(&req
, addr
);
4488 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4490 /* This mac addr exist, remove this handle's VFID for it */
4491 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4493 if (hclge_is_all_function_id_zero(desc
))
4494 /* All the vfid is zero, so need to delete this entry */
4495 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4497 /* Not all the vfid is zero, update the vfid */
4498 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4501 /* Maybe this mac address is in mta table, but it cannot be
4502 * deleted here because an entry of mta represents an address
4503 * range rather than a specific address. the delete action to
4504 * all entries will take effect in update_mta_status called by
4505 * hns3_nic_set_rx_mode.
4513 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4514 u16 cmdq_resp
, u8 resp_code
)
4516 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4517 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4518 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4519 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4524 dev_err(&hdev
->pdev
->dev
,
4525 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4530 switch (resp_code
) {
4531 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4532 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4535 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4536 dev_err(&hdev
->pdev
->dev
,
4537 "add mac ethertype failed for manager table overflow.\n");
4538 return_status
= -EIO
;
4540 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4541 dev_err(&hdev
->pdev
->dev
,
4542 "add mac ethertype failed for key conflict.\n");
4543 return_status
= -EIO
;
4546 dev_err(&hdev
->pdev
->dev
,
4547 "add mac ethertype failed for undefined, code=%d.\n",
4549 return_status
= -EIO
;
4552 return return_status
;
4555 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4556 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4558 struct hclge_desc desc
;
4563 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4564 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4566 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4568 dev_err(&hdev
->pdev
->dev
,
4569 "add mac ethertype failed for cmd_send, ret =%d.\n",
4574 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4575 retval
= le16_to_cpu(desc
.retval
);
4577 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4580 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4585 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4586 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4588 dev_err(&hdev
->pdev
->dev
,
4589 "add mac ethertype failed, ret =%d.\n",
4598 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4600 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4601 struct hclge_dev
*hdev
= vport
->back
;
4603 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4606 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4609 const unsigned char *new_addr
= (const unsigned char *)p
;
4610 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4611 struct hclge_dev
*hdev
= vport
->back
;
4614 /* mac addr check */
4615 if (is_zero_ether_addr(new_addr
) ||
4616 is_broadcast_ether_addr(new_addr
) ||
4617 is_multicast_ether_addr(new_addr
)) {
4618 dev_err(&hdev
->pdev
->dev
,
4619 "Change uc mac err! invalid mac:%p.\n",
4624 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4625 dev_warn(&hdev
->pdev
->dev
,
4626 "remove old uc mac address fail.\n");
4628 ret
= hclge_add_uc_addr(handle
, new_addr
);
4630 dev_err(&hdev
->pdev
->dev
,
4631 "add uc mac address fail, ret =%d.\n",
4635 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4636 dev_err(&hdev
->pdev
->dev
,
4637 "restore uc mac address fail.\n");
4642 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4644 dev_err(&hdev
->pdev
->dev
,
4645 "configure mac pause address fail, ret =%d.\n",
4650 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4655 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4658 struct hclge_vlan_filter_ctrl_cmd
*req
;
4659 struct hclge_desc desc
;
4662 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4664 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4665 req
->vlan_type
= vlan_type
;
4666 req
->vlan_fe
= filter_en
;
4668 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4670 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4678 #define HCLGE_FILTER_TYPE_VF 0
4679 #define HCLGE_FILTER_TYPE_PORT 1
4681 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4683 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4684 struct hclge_dev
*hdev
= vport
->back
;
4686 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4689 static int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4690 bool is_kill
, u16 vlan
, u8 qos
,
4693 #define HCLGE_MAX_VF_BYTES 16
4694 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4695 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4696 struct hclge_desc desc
[2];
4701 hclge_cmd_setup_basic_desc(&desc
[0],
4702 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4703 hclge_cmd_setup_basic_desc(&desc
[1],
4704 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4706 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4708 vf_byte_off
= vfid
/ 8;
4709 vf_byte_val
= 1 << (vfid
% 8);
4711 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4712 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4714 req0
->vlan_id
= cpu_to_le16(vlan
);
4715 req0
->vlan_cfg
= is_kill
;
4717 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4718 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4720 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4722 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4724 dev_err(&hdev
->pdev
->dev
,
4725 "Send vf vlan command fail, ret =%d.\n",
4731 #define HCLGE_VF_VLAN_NO_ENTRY 2
4732 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4735 if (req0
->resp_code
== HCLGE_VF_VLAN_NO_ENTRY
) {
4736 dev_warn(&hdev
->pdev
->dev
,
4737 "vf vlan table is full, vf vlan filter is disabled\n");
4741 dev_err(&hdev
->pdev
->dev
,
4742 "Add vf vlan filter fail, ret =%d.\n",
4745 if (!req0
->resp_code
)
4748 dev_err(&hdev
->pdev
->dev
,
4749 "Kill vf vlan filter fail, ret =%d.\n",
4756 static int hclge_set_port_vlan_filter(struct hclge_dev
*hdev
, __be16 proto
,
4757 u16 vlan_id
, bool is_kill
)
4759 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4760 struct hclge_desc desc
;
4761 u8 vlan_offset_byte_val
;
4762 u8 vlan_offset_byte
;
4766 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4768 vlan_offset_160
= vlan_id
/ 160;
4769 vlan_offset_byte
= (vlan_id
% 160) / 8;
4770 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4772 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4773 req
->vlan_offset
= vlan_offset_160
;
4774 req
->vlan_cfg
= is_kill
;
4775 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4777 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4779 dev_err(&hdev
->pdev
->dev
,
4780 "port vlan command, send fail, ret =%d.\n", ret
);
4784 static int hclge_set_vlan_filter_hw(struct hclge_dev
*hdev
, __be16 proto
,
4785 u16 vport_id
, u16 vlan_id
, u8 qos
,
4788 u16 vport_idx
, vport_num
= 0;
4791 ret
= hclge_set_vf_vlan_common(hdev
, vport_id
, is_kill
, vlan_id
,
4794 dev_err(&hdev
->pdev
->dev
,
4795 "Set %d vport vlan filter config fail, ret =%d.\n",
4800 /* vlan 0 may be added twice when 8021q module is enabled */
4801 if (!is_kill
&& !vlan_id
&&
4802 test_bit(vport_id
, hdev
->vlan_table
[vlan_id
]))
4805 if (!is_kill
&& test_and_set_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4806 dev_err(&hdev
->pdev
->dev
,
4807 "Add port vlan failed, vport %d is already in vlan %d\n",
4813 !test_and_clear_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4814 dev_err(&hdev
->pdev
->dev
,
4815 "Delete port vlan failed, vport %d is not in vlan %d\n",
4820 for_each_set_bit(vport_idx
, hdev
->vlan_table
[vlan_id
], VLAN_N_VID
)
4823 if ((is_kill
&& vport_num
== 0) || (!is_kill
&& vport_num
== 1))
4824 ret
= hclge_set_port_vlan_filter(hdev
, proto
, vlan_id
,
4830 int hclge_set_vlan_filter(struct hnae3_handle
*handle
, __be16 proto
,
4831 u16 vlan_id
, bool is_kill
)
4833 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4834 struct hclge_dev
*hdev
= vport
->back
;
4836 return hclge_set_vlan_filter_hw(hdev
, proto
, vport
->vport_id
, vlan_id
,
4840 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4841 u16 vlan
, u8 qos
, __be16 proto
)
4843 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4844 struct hclge_dev
*hdev
= vport
->back
;
4846 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4848 if (proto
!= htons(ETH_P_8021Q
))
4849 return -EPROTONOSUPPORT
;
4851 return hclge_set_vlan_filter_hw(hdev
, proto
, vfid
, vlan
, qos
, false);
4854 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4856 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4857 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4858 struct hclge_dev
*hdev
= vport
->back
;
4859 struct hclge_desc desc
;
4862 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4864 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4865 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4866 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4867 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG1_B
,
4868 vcfg
->accept_tag1
? 1 : 0);
4869 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG1_B
,
4870 vcfg
->accept_untag1
? 1 : 0);
4871 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG2_B
,
4872 vcfg
->accept_tag2
? 1 : 0);
4873 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG2_B
,
4874 vcfg
->accept_untag2
? 1 : 0);
4875 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4876 vcfg
->insert_tag1_en
? 1 : 0);
4877 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4878 vcfg
->insert_tag2_en
? 1 : 0);
4879 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4881 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4882 req
->vf_bitmap
[req
->vf_offset
] =
4883 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4885 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4887 dev_err(&hdev
->pdev
->dev
,
4888 "Send port txvlan cfg command fail, ret =%d\n",
4894 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4896 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4897 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4898 struct hclge_dev
*hdev
= vport
->back
;
4899 struct hclge_desc desc
;
4902 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4904 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4905 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4906 vcfg
->strip_tag1_en
? 1 : 0);
4907 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4908 vcfg
->strip_tag2_en
? 1 : 0);
4909 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4910 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4911 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4912 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4914 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4915 req
->vf_bitmap
[req
->vf_offset
] =
4916 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4918 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4920 dev_err(&hdev
->pdev
->dev
,
4921 "Send port rxvlan cfg command fail, ret =%d\n",
4927 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4929 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4930 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4931 struct hclge_desc desc
;
4934 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4935 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4936 rx_req
->ot_fst_vlan_type
=
4937 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4938 rx_req
->ot_sec_vlan_type
=
4939 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4940 rx_req
->in_fst_vlan_type
=
4941 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4942 rx_req
->in_sec_vlan_type
=
4943 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4945 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4947 dev_err(&hdev
->pdev
->dev
,
4948 "Send rxvlan protocol type command fail, ret =%d\n",
4953 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4955 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4956 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4957 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4959 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4961 dev_err(&hdev
->pdev
->dev
,
4962 "Send txvlan protocol type command fail, ret =%d\n",
4968 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4970 #define HCLGE_DEF_VLAN_TYPE 0x8100
4972 struct hnae3_handle
*handle
;
4973 struct hclge_vport
*vport
;
4977 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4981 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4985 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4986 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4987 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4988 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4989 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4990 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4992 ret
= hclge_set_vlan_protocol_type(hdev
);
4996 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4997 vport
= &hdev
->vport
[i
];
4998 vport
->txvlan_cfg
.accept_tag1
= true;
4999 vport
->txvlan_cfg
.accept_untag1
= true;
5001 /* accept_tag2 and accept_untag2 are not supported on
5002 * pdev revision(0x20), new revision support them. The
5003 * value of this two fields will not return error when driver
5004 * send command to fireware in revision(0x20).
5005 * This two fields can not configured by user.
5007 vport
->txvlan_cfg
.accept_tag2
= true;
5008 vport
->txvlan_cfg
.accept_untag2
= true;
5010 vport
->txvlan_cfg
.insert_tag1_en
= false;
5011 vport
->txvlan_cfg
.insert_tag2_en
= false;
5012 vport
->txvlan_cfg
.default_tag1
= 0;
5013 vport
->txvlan_cfg
.default_tag2
= 0;
5015 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
5019 vport
->rxvlan_cfg
.strip_tag1_en
= false;
5020 vport
->rxvlan_cfg
.strip_tag2_en
= true;
5021 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
5022 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
5024 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
5029 handle
= &hdev
->vport
[0].nic
;
5030 return hclge_set_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
5033 int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
5035 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5037 vport
->rxvlan_cfg
.strip_tag1_en
= false;
5038 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
5039 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
5040 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
5042 return hclge_set_vlan_rx_offload_cfg(vport
);
5045 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
5047 struct hclge_config_max_frm_size_cmd
*req
;
5048 struct hclge_desc desc
;
5052 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
5054 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
5055 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
5058 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
5060 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
5062 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
5063 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
5065 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5067 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
5071 hdev
->mps
= max_frm_size
;
5076 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
5078 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5079 struct hclge_dev
*hdev
= vport
->back
;
5082 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
5084 dev_err(&hdev
->pdev
->dev
,
5085 "Change mtu fail, ret =%d\n", ret
);
5089 ret
= hclge_buffer_alloc(hdev
);
5091 dev_err(&hdev
->pdev
->dev
,
5092 "Allocate buffer fail, ret =%d\n", ret
);
5097 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
5100 struct hclge_reset_tqp_queue_cmd
*req
;
5101 struct hclge_desc desc
;
5104 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
5106 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5107 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5108 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
5110 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5112 dev_err(&hdev
->pdev
->dev
,
5113 "Send tqp reset cmd error, status =%d\n", ret
);
5120 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
5122 struct hclge_reset_tqp_queue_cmd
*req
;
5123 struct hclge_desc desc
;
5126 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
5128 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5129 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5131 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5133 dev_err(&hdev
->pdev
->dev
,
5134 "Get reset status error, status =%d\n", ret
);
5138 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
5141 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
5144 struct hnae3_queue
*queue
;
5145 struct hclge_tqp
*tqp
;
5147 queue
= handle
->kinfo
.tqp
[queue_id
];
5148 tqp
= container_of(queue
, struct hclge_tqp
, q
);
5153 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
5155 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5156 struct hclge_dev
*hdev
= vport
->back
;
5157 int reset_try_times
= 0;
5162 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
5165 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
5167 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
5169 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
5173 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5175 dev_warn(&hdev
->pdev
->dev
,
5176 "Send reset tqp cmd fail, ret = %d\n", ret
);
5180 reset_try_times
= 0;
5181 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5182 /* Wait for tqp hw reset */
5184 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5189 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5190 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5194 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5196 dev_warn(&hdev
->pdev
->dev
,
5197 "Deassert the soft reset fail, ret = %d\n", ret
);
5202 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
5204 struct hclge_dev
*hdev
= vport
->back
;
5205 int reset_try_times
= 0;
5210 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5212 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5214 dev_warn(&hdev
->pdev
->dev
,
5215 "Send reset tqp cmd fail, ret = %d\n", ret
);
5219 reset_try_times
= 0;
5220 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5221 /* Wait for tqp hw reset */
5223 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5228 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5229 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5233 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5235 dev_warn(&hdev
->pdev
->dev
,
5236 "Deassert the soft reset fail, ret = %d\n", ret
);
5239 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5241 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5242 struct hclge_dev
*hdev
= vport
->back
;
5244 return hdev
->fw_version
;
5247 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5250 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5251 struct hclge_dev
*hdev
= vport
->back
;
5252 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5257 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5258 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5261 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5263 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5268 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5271 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5274 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5277 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5282 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5283 else if (rx_en
&& !tx_en
)
5284 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5285 else if (!rx_en
&& tx_en
)
5286 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5288 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5290 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5293 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5295 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5300 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5305 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5307 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5308 u16 remote_advertising
= 0;
5309 u16 local_advertising
= 0;
5310 u32 rx_pause
, tx_pause
;
5313 if (!phydev
->link
|| !phydev
->autoneg
)
5316 if (phydev
->advertising
& ADVERTISED_Pause
)
5317 local_advertising
= ADVERTISE_PAUSE_CAP
;
5319 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5320 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5323 remote_advertising
= LPA_PAUSE_CAP
;
5325 if (phydev
->asym_pause
)
5326 remote_advertising
|= LPA_PAUSE_ASYM
;
5328 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5329 remote_advertising
);
5330 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5331 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5333 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5338 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5341 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5342 u32
*rx_en
, u32
*tx_en
)
5344 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5345 struct hclge_dev
*hdev
= vport
->back
;
5347 *auto_neg
= hclge_get_autoneg(handle
);
5349 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5355 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5358 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5361 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5370 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5371 u32 rx_en
, u32 tx_en
)
5373 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5374 struct hclge_dev
*hdev
= vport
->back
;
5375 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5378 fc_autoneg
= hclge_get_autoneg(handle
);
5379 if (auto_neg
!= fc_autoneg
) {
5380 dev_info(&hdev
->pdev
->dev
,
5381 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5385 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5386 dev_info(&hdev
->pdev
->dev
,
5387 "Priority flow control enabled. Cannot set link flow control.\n");
5391 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5394 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5396 /* Only support flow control negotiation for netdev with
5397 * phy attached for now.
5402 return phy_start_aneg(phydev
);
5405 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5406 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5408 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5409 struct hclge_dev
*hdev
= vport
->back
;
5412 *speed
= hdev
->hw
.mac
.speed
;
5414 *duplex
= hdev
->hw
.mac
.duplex
;
5416 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5419 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5421 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5422 struct hclge_dev
*hdev
= vport
->back
;
5425 *media_type
= hdev
->hw
.mac
.media_type
;
5428 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5429 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5431 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5432 struct hclge_dev
*hdev
= vport
->back
;
5433 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5434 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5437 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5438 *tp_mdix
= ETH_TP_MDI_INVALID
;
5442 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5444 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5445 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5446 HCLGE_PHY_MDIX_CTRL_S
);
5448 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5449 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5450 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5452 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5454 switch (mdix_ctrl
) {
5456 *tp_mdix_ctrl
= ETH_TP_MDI
;
5459 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5462 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5465 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5470 *tp_mdix
= ETH_TP_MDI_INVALID
;
5472 *tp_mdix
= ETH_TP_MDI_X
;
5474 *tp_mdix
= ETH_TP_MDI
;
5477 static int hclge_init_client_instance(struct hnae3_client
*client
,
5478 struct hnae3_ae_dev
*ae_dev
)
5480 struct hclge_dev
*hdev
= ae_dev
->priv
;
5481 struct hclge_vport
*vport
;
5484 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5485 vport
= &hdev
->vport
[i
];
5487 switch (client
->type
) {
5488 case HNAE3_CLIENT_KNIC
:
5490 hdev
->nic_client
= client
;
5491 vport
->nic
.client
= client
;
5492 ret
= client
->ops
->init_instance(&vport
->nic
);
5496 if (hdev
->roce_client
&&
5497 hnae3_dev_roce_supported(hdev
)) {
5498 struct hnae3_client
*rc
= hdev
->roce_client
;
5500 ret
= hclge_init_roce_base_info(vport
);
5504 ret
= rc
->ops
->init_instance(&vport
->roce
);
5510 case HNAE3_CLIENT_UNIC
:
5511 hdev
->nic_client
= client
;
5512 vport
->nic
.client
= client
;
5514 ret
= client
->ops
->init_instance(&vport
->nic
);
5519 case HNAE3_CLIENT_ROCE
:
5520 if (hnae3_dev_roce_supported(hdev
)) {
5521 hdev
->roce_client
= client
;
5522 vport
->roce
.client
= client
;
5525 if (hdev
->roce_client
&& hdev
->nic_client
) {
5526 ret
= hclge_init_roce_base_info(vport
);
5530 ret
= client
->ops
->init_instance(&vport
->roce
);
5540 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5541 struct hnae3_ae_dev
*ae_dev
)
5543 struct hclge_dev
*hdev
= ae_dev
->priv
;
5544 struct hclge_vport
*vport
;
5547 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5548 vport
= &hdev
->vport
[i
];
5549 if (hdev
->roce_client
) {
5550 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5552 hdev
->roce_client
= NULL
;
5553 vport
->roce
.client
= NULL
;
5555 if (client
->type
== HNAE3_CLIENT_ROCE
)
5557 if (client
->ops
->uninit_instance
) {
5558 client
->ops
->uninit_instance(&vport
->nic
, 0);
5559 hdev
->nic_client
= NULL
;
5560 vport
->nic
.client
= NULL
;
5565 static int hclge_pci_init(struct hclge_dev
*hdev
)
5567 struct pci_dev
*pdev
= hdev
->pdev
;
5568 struct hclge_hw
*hw
;
5571 ret
= pci_enable_device(pdev
);
5573 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5577 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5579 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5582 "can't set consistent PCI DMA");
5583 goto err_disable_device
;
5585 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5588 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5590 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5591 goto err_disable_device
;
5594 pci_set_master(pdev
);
5596 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5598 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5600 goto err_clr_master
;
5603 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5607 pci_clear_master(pdev
);
5608 pci_release_regions(pdev
);
5610 pci_disable_device(pdev
);
5615 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5617 struct pci_dev
*pdev
= hdev
->pdev
;
5619 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5620 pci_free_irq_vectors(pdev
);
5621 pci_clear_master(pdev
);
5622 pci_release_mem_regions(pdev
);
5623 pci_disable_device(pdev
);
5626 static void hclge_state_init(struct hclge_dev
*hdev
)
5628 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5629 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5630 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5631 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5632 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5633 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5636 static void hclge_state_uninit(struct hclge_dev
*hdev
)
5638 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5640 if (hdev
->service_timer
.function
)
5641 del_timer_sync(&hdev
->service_timer
);
5642 if (hdev
->service_task
.func
)
5643 cancel_work_sync(&hdev
->service_task
);
5644 if (hdev
->rst_service_task
.func
)
5645 cancel_work_sync(&hdev
->rst_service_task
);
5646 if (hdev
->mbx_service_task
.func
)
5647 cancel_work_sync(&hdev
->mbx_service_task
);
5650 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5652 struct pci_dev
*pdev
= ae_dev
->pdev
;
5653 struct hclge_dev
*hdev
;
5656 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5663 hdev
->ae_dev
= ae_dev
;
5664 hdev
->reset_type
= HNAE3_NONE_RESET
;
5665 hdev
->reset_request
= 0;
5666 hdev
->reset_pending
= 0;
5667 ae_dev
->priv
= hdev
;
5669 ret
= hclge_pci_init(hdev
);
5671 dev_err(&pdev
->dev
, "PCI init failed\n");
5675 /* Firmware command queue initialize */
5676 ret
= hclge_cmd_queue_init(hdev
);
5678 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5679 goto err_pci_uninit
;
5682 /* Firmware command initialize */
5683 ret
= hclge_cmd_init(hdev
);
5685 goto err_cmd_uninit
;
5687 ret
= hclge_get_cap(hdev
);
5689 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5691 goto err_cmd_uninit
;
5694 ret
= hclge_configure(hdev
);
5696 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5697 goto err_cmd_uninit
;
5700 ret
= hclge_init_msi(hdev
);
5702 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5703 goto err_cmd_uninit
;
5706 ret
= hclge_misc_irq_init(hdev
);
5709 "Misc IRQ(vector0) init error, ret = %d.\n",
5711 goto err_msi_uninit
;
5714 ret
= hclge_alloc_tqps(hdev
);
5716 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5717 goto err_msi_irq_uninit
;
5720 ret
= hclge_alloc_vport(hdev
);
5722 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5723 goto err_msi_irq_uninit
;
5726 ret
= hclge_map_tqp(hdev
);
5728 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5729 goto err_msi_irq_uninit
;
5732 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5733 ret
= hclge_mac_mdio_config(hdev
);
5735 dev_err(&hdev
->pdev
->dev
,
5736 "mdio config fail ret=%d\n", ret
);
5737 goto err_msi_irq_uninit
;
5741 ret
= hclge_mac_init(hdev
);
5743 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5744 goto err_mdiobus_unreg
;
5747 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5749 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5750 goto err_mdiobus_unreg
;
5753 ret
= hclge_init_vlan_config(hdev
);
5755 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5756 goto err_mdiobus_unreg
;
5759 ret
= hclge_tm_schd_init(hdev
);
5761 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5762 goto err_mdiobus_unreg
;
5765 hclge_rss_init_cfg(hdev
);
5766 ret
= hclge_rss_init_hw(hdev
);
5768 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5769 goto err_mdiobus_unreg
;
5772 ret
= init_mgr_tbl(hdev
);
5774 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5775 goto err_mdiobus_unreg
;
5778 hclge_dcb_ops_set(hdev
);
5780 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5781 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5782 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5783 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5785 /* Enable MISC vector(vector0) */
5786 hclge_enable_vector(&hdev
->misc_vector
, true);
5788 hclge_state_init(hdev
);
5790 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5794 if (hdev
->hw
.mac
.phydev
)
5795 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5797 hclge_misc_irq_uninit(hdev
);
5799 pci_free_irq_vectors(pdev
);
5801 hclge_destroy_cmd_queue(&hdev
->hw
);
5803 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5804 pci_clear_master(pdev
);
5805 pci_release_regions(pdev
);
5806 pci_disable_device(pdev
);
5811 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5813 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5816 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5818 struct hclge_dev
*hdev
= ae_dev
->priv
;
5819 struct pci_dev
*pdev
= ae_dev
->pdev
;
5822 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5824 hclge_stats_clear(hdev
);
5825 memset(hdev
->vlan_table
, 0, sizeof(hdev
->vlan_table
));
5827 ret
= hclge_cmd_init(hdev
);
5829 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5833 ret
= hclge_get_cap(hdev
);
5835 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5840 ret
= hclge_configure(hdev
);
5842 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5846 ret
= hclge_map_tqp(hdev
);
5848 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5852 ret
= hclge_mac_init(hdev
);
5854 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5858 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5860 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5864 ret
= hclge_init_vlan_config(hdev
);
5866 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5870 ret
= hclge_tm_init_hw(hdev
);
5872 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5876 ret
= hclge_rss_init_hw(hdev
);
5878 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5882 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5888 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5890 struct hclge_dev
*hdev
= ae_dev
->priv
;
5891 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5893 hclge_state_uninit(hdev
);
5896 mdiobus_unregister(mac
->mdio_bus
);
5898 /* Disable MISC vector(vector0) */
5899 hclge_enable_vector(&hdev
->misc_vector
, false);
5900 hclge_destroy_cmd_queue(&hdev
->hw
);
5901 hclge_misc_irq_uninit(hdev
);
5902 hclge_pci_uninit(hdev
);
5903 ae_dev
->priv
= NULL
;
5906 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5908 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5909 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5910 struct hclge_dev
*hdev
= vport
->back
;
5912 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5915 static void hclge_get_channels(struct hnae3_handle
*handle
,
5916 struct ethtool_channels
*ch
)
5918 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5920 ch
->max_combined
= hclge_get_max_channels(handle
);
5921 ch
->other_count
= 1;
5923 ch
->combined_count
= vport
->alloc_tqps
;
5926 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5927 u16
*free_tqps
, u16
*max_rss_size
)
5929 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5930 struct hclge_dev
*hdev
= vport
->back
;
5934 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5935 if (!hdev
->htqp
[i
].alloced
)
5938 *free_tqps
= temp_tqps
;
5939 *max_rss_size
= hdev
->rss_size_max
;
5942 static void hclge_release_tqp(struct hclge_vport
*vport
)
5944 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5945 struct hclge_dev
*hdev
= vport
->back
;
5948 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5949 struct hclge_tqp
*tqp
=
5950 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5952 tqp
->q
.handle
= NULL
;
5953 tqp
->q
.tqp_index
= 0;
5954 tqp
->alloced
= false;
5957 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5961 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5963 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5964 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5965 struct hclge_dev
*hdev
= vport
->back
;
5966 int cur_rss_size
= kinfo
->rss_size
;
5967 int cur_tqps
= kinfo
->num_tqps
;
5968 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5969 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5970 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5975 hclge_release_tqp(vport
);
5977 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5979 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5983 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5985 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5989 ret
= hclge_tm_schd_init(hdev
);
5991 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5995 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5996 roundup_size
= ilog2(roundup_size
);
5997 /* Set the RSS TC mode according to the new RSS size */
5998 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
6001 if (!(hdev
->hw_tc_map
& BIT(i
)))
6005 tc_size
[i
] = roundup_size
;
6006 tc_offset
[i
] = kinfo
->rss_size
* i
;
6008 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
6012 /* Reinitializes the rss indirect table according to the new RSS size */
6013 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
6017 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
6018 rss_indir
[i
] = i
% kinfo
->rss_size
;
6020 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
6022 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
6028 dev_info(&hdev
->pdev
->dev
,
6029 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
6030 cur_rss_size
, kinfo
->rss_size
,
6031 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
6036 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
6037 u32
*regs_num_64_bit
)
6039 struct hclge_desc desc
;
6043 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
6044 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6046 dev_err(&hdev
->pdev
->dev
,
6047 "Query register number cmd failed, ret = %d.\n", ret
);
6051 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
6052 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
6054 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
6061 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6064 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6066 struct hclge_desc
*desc
;
6067 u32
*reg_val
= data
;
6076 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
6077 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6081 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
6082 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6084 dev_err(&hdev
->pdev
->dev
,
6085 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
6090 for (i
= 0; i
< cmd_num
; i
++) {
6092 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
6093 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
6095 desc_data
= (__le32
*)(&desc
[i
]);
6096 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
6098 for (k
= 0; k
< n
; k
++) {
6099 *reg_val
++ = le32_to_cpu(*desc_data
++);
6111 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6114 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6116 struct hclge_desc
*desc
;
6117 u64
*reg_val
= data
;
6126 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
6127 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6131 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
6132 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6134 dev_err(&hdev
->pdev
->dev
,
6135 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
6140 for (i
= 0; i
< cmd_num
; i
++) {
6142 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
6143 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
6145 desc_data
= (__le64
*)(&desc
[i
]);
6146 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
6148 for (k
= 0; k
< n
; k
++) {
6149 *reg_val
++ = le64_to_cpu(*desc_data
++);
6161 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
6163 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6164 struct hclge_dev
*hdev
= vport
->back
;
6165 u32 regs_num_32_bit
, regs_num_64_bit
;
6168 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6170 dev_err(&hdev
->pdev
->dev
,
6171 "Get register number failed, ret = %d.\n", ret
);
6175 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
6178 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
6181 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6182 struct hclge_dev
*hdev
= vport
->back
;
6183 u32 regs_num_32_bit
, regs_num_64_bit
;
6186 *version
= hdev
->fw_version
;
6188 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6190 dev_err(&hdev
->pdev
->dev
,
6191 "Get register number failed, ret = %d.\n", ret
);
6195 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
6197 dev_err(&hdev
->pdev
->dev
,
6198 "Get 32 bit register failed, ret = %d.\n", ret
);
6202 data
= (u32
*)data
+ regs_num_32_bit
;
6203 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
6206 dev_err(&hdev
->pdev
->dev
,
6207 "Get 64 bit register failed, ret = %d.\n", ret
);
6210 static int hclge_set_led_status(struct hclge_dev
*hdev
, u8 locate_led_status
)
6212 struct hclge_set_led_state_cmd
*req
;
6213 struct hclge_desc desc
;
6216 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6218 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6219 hnae_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6220 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6222 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6224 dev_err(&hdev
->pdev
->dev
,
6225 "Send set led state cmd error, ret =%d\n", ret
);
6230 enum hclge_led_status
{
6233 HCLGE_LED_NO_CHANGE
= 0xFF,
6236 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6237 enum ethtool_phys_id_state status
)
6239 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6240 struct hclge_dev
*hdev
= vport
->back
;
6243 case ETHTOOL_ID_ACTIVE
:
6244 return hclge_set_led_status(hdev
, HCLGE_LED_ON
);
6245 case ETHTOOL_ID_INACTIVE
:
6246 return hclge_set_led_status(hdev
, HCLGE_LED_OFF
);
6252 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6253 unsigned long *supported
,
6254 unsigned long *advertising
)
6256 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6257 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6258 struct hclge_dev
*hdev
= vport
->back
;
6259 unsigned int idx
= 0;
6261 for (; idx
< size
; idx
++) {
6262 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6263 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6267 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6270 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6271 struct hclge_dev
*hdev
= vport
->back
;
6272 u8 media_type
= hdev
->hw
.mac
.media_type
;
6274 switch (media_type
) {
6275 case HNAE3_MEDIA_TYPE_FIBER
:
6276 *port_type
= PORT_FIBRE
;
6278 case HNAE3_MEDIA_TYPE_COPPER
:
6279 *port_type
= PORT_TP
;
6281 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6283 *port_type
= PORT_OTHER
;
6288 static const struct hnae3_ae_ops hclge_ops
= {
6289 .init_ae_dev
= hclge_init_ae_dev
,
6290 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6291 .init_client_instance
= hclge_init_client_instance
,
6292 .uninit_client_instance
= hclge_uninit_client_instance
,
6293 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6294 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6295 .get_vector
= hclge_get_vector
,
6296 .put_vector
= hclge_put_vector
,
6297 .set_promisc_mode
= hclge_set_promisc_mode
,
6298 .set_loopback
= hclge_set_loopback
,
6299 .start
= hclge_ae_start
,
6300 .stop
= hclge_ae_stop
,
6301 .get_status
= hclge_get_status
,
6302 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6303 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6304 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6305 .get_media_type
= hclge_get_media_type
,
6306 .get_rss_key_size
= hclge_get_rss_key_size
,
6307 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6308 .get_rss
= hclge_get_rss
,
6309 .set_rss
= hclge_set_rss
,
6310 .set_rss_tuple
= hclge_set_rss_tuple
,
6311 .get_rss_tuple
= hclge_get_rss_tuple
,
6312 .get_tc_size
= hclge_get_tc_size
,
6313 .get_mac_addr
= hclge_get_mac_addr
,
6314 .set_mac_addr
= hclge_set_mac_addr
,
6315 .add_uc_addr
= hclge_add_uc_addr
,
6316 .rm_uc_addr
= hclge_rm_uc_addr
,
6317 .add_mc_addr
= hclge_add_mc_addr
,
6318 .rm_mc_addr
= hclge_rm_mc_addr
,
6319 .update_mta_status
= hclge_update_mta_status
,
6320 .set_autoneg
= hclge_set_autoneg
,
6321 .get_autoneg
= hclge_get_autoneg
,
6322 .get_pauseparam
= hclge_get_pauseparam
,
6323 .set_pauseparam
= hclge_set_pauseparam
,
6324 .set_mtu
= hclge_set_mtu
,
6325 .reset_queue
= hclge_reset_tqp
,
6326 .get_stats
= hclge_get_stats
,
6327 .update_stats
= hclge_update_stats
,
6328 .get_strings
= hclge_get_strings
,
6329 .get_sset_count
= hclge_get_sset_count
,
6330 .get_fw_version
= hclge_get_fw_version
,
6331 .get_mdix_mode
= hclge_get_mdix_mode
,
6332 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6333 .set_vlan_filter
= hclge_set_vlan_filter
,
6334 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6335 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6336 .reset_event
= hclge_reset_event
,
6337 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6338 .set_channels
= hclge_set_channels
,
6339 .get_channels
= hclge_get_channels
,
6340 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6341 .get_regs_len
= hclge_get_regs_len
,
6342 .get_regs
= hclge_get_regs
,
6343 .set_led_id
= hclge_set_led_id
,
6344 .get_link_mode
= hclge_get_link_mode
,
6345 .get_port_type
= hclge_get_port_type
,
6348 static struct hnae3_ae_algo ae_algo
= {
6351 .pdev_id_table
= ae_algo_pci_tbl
,
6354 static int hclge_init(void)
6356 pr_info("%s is initializing\n", HCLGE_NAME
);
6358 hnae3_register_ae_algo(&ae_algo
);
6363 static void hclge_exit(void)
6365 hnae3_unregister_ae_algo(&ae_algo
);
6367 module_init(hclge_init
);
6368 module_exit(hclge_exit
);
6370 MODULE_LICENSE("GPL");
6371 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6372 MODULE_DESCRIPTION("HCLGE Driver");
6373 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob