2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
42 static int hclge_update_led_status(struct hclge_dev
*hdev
);
44 static struct hnae3_ae_algo ae_algo
;
46 static const struct pci_device_id ae_algo_pci_tbl
[] = {
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
53 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
54 /* required last entry */
58 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
60 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
62 "Serdes Loopback test",
66 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
67 {"igu_rx_oversize_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
69 {"igu_rx_undersize_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
71 {"igu_rx_out_all_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
78 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
79 {"egu_tx_out_all_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
86 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
87 {"ssu_ppp_mac_key_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
89 {"ssu_ppp_host_key_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
91 {"ppp_ssu_mac_rlt_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
93 {"ppp_ssu_host_rlt_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
102 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
105 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
108 {"igu_rx_no_eof_pkt",
109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
110 {"igu_rx_no_sof_pkt",
111 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
113 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
114 {"ssu_full_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
116 {"ssu_part_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
121 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
123 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
125 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
130 {"qcn_fb_invaild_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
132 {"rx_packet_tc0_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
134 {"rx_packet_tc1_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
136 {"rx_packet_tc2_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
138 {"rx_packet_tc3_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
140 {"rx_packet_tc4_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
142 {"rx_packet_tc5_in_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
144 {"rx_packet_tc6_in_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
146 {"rx_packet_tc7_in_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
148 {"rx_packet_tc0_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
150 {"rx_packet_tc1_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
152 {"rx_packet_tc2_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
154 {"rx_packet_tc3_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
156 {"rx_packet_tc4_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
158 {"rx_packet_tc5_out_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
160 {"rx_packet_tc6_out_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
162 {"rx_packet_tc7_out_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
164 {"tx_packet_tc0_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
166 {"tx_packet_tc1_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
168 {"tx_packet_tc2_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
170 {"tx_packet_tc3_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
172 {"tx_packet_tc4_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
174 {"tx_packet_tc5_in_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
176 {"tx_packet_tc6_in_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
178 {"tx_packet_tc7_in_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
180 {"tx_packet_tc0_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
182 {"tx_packet_tc1_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
184 {"tx_packet_tc2_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
186 {"tx_packet_tc3_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
188 {"tx_packet_tc4_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
190 {"tx_packet_tc5_out_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
192 {"tx_packet_tc6_out_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
194 {"tx_packet_tc7_out_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
196 {"pkt_curr_buf_tc0_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
198 {"pkt_curr_buf_tc1_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
200 {"pkt_curr_buf_tc2_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
202 {"pkt_curr_buf_tc3_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
204 {"pkt_curr_buf_tc4_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
206 {"pkt_curr_buf_tc5_cnt",
207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
208 {"pkt_curr_buf_tc6_cnt",
209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
210 {"pkt_curr_buf_tc7_cnt",
211 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
213 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
214 {"lo_pri_unicast_rlt_drop_num",
215 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
216 {"hi_pri_multicast_rlt_drop_num",
217 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
218 {"lo_pri_multicast_rlt_drop_num",
219 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
220 {"rx_oq_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
222 {"tx_oq_drop_pkt_cnt",
223 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
224 {"nic_l2_err_drop_pkt_cnt",
225 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
226 {"roc_l2_err_drop_pkt_cnt",
227 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
230 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
231 {"mac_tx_mac_pause_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
233 {"mac_rx_mac_pause_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
235 {"mac_tx_pfc_pri0_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
237 {"mac_tx_pfc_pri1_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
239 {"mac_tx_pfc_pri2_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
241 {"mac_tx_pfc_pri3_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
243 {"mac_tx_pfc_pri4_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
245 {"mac_tx_pfc_pri5_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
247 {"mac_tx_pfc_pri6_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
249 {"mac_tx_pfc_pri7_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
251 {"mac_rx_pfc_pri0_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
253 {"mac_rx_pfc_pri1_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
255 {"mac_rx_pfc_pri2_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
257 {"mac_rx_pfc_pri3_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
259 {"mac_rx_pfc_pri4_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
261 {"mac_rx_pfc_pri5_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
263 {"mac_rx_pfc_pri6_pkt_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
265 {"mac_rx_pfc_pri7_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
267 {"mac_tx_total_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
269 {"mac_tx_total_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
271 {"mac_tx_good_pkt_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
273 {"mac_tx_bad_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
275 {"mac_tx_good_oct_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
277 {"mac_tx_bad_oct_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
279 {"mac_tx_uni_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
281 {"mac_tx_multi_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
283 {"mac_tx_broad_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
285 {"mac_tx_undersize_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
287 {"mac_tx_oversize_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
289 {"mac_tx_64_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
291 {"mac_tx_65_127_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
293 {"mac_tx_128_255_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
295 {"mac_tx_256_511_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
297 {"mac_tx_512_1023_oct_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
299 {"mac_tx_1024_1518_oct_pkt_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
301 {"mac_tx_1519_2047_oct_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
303 {"mac_tx_2048_4095_oct_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
305 {"mac_tx_4096_8191_oct_pkt_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
307 {"mac_tx_8192_9216_oct_pkt_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
309 {"mac_tx_9217_12287_oct_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
311 {"mac_tx_12288_16383_oct_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
313 {"mac_tx_1519_max_good_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
315 {"mac_tx_1519_max_bad_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
317 {"mac_rx_total_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
319 {"mac_rx_total_oct_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
321 {"mac_rx_good_pkt_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
323 {"mac_rx_bad_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
325 {"mac_rx_good_oct_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
327 {"mac_rx_bad_oct_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
329 {"mac_rx_uni_pkt_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
331 {"mac_rx_multi_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
333 {"mac_rx_broad_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
335 {"mac_rx_undersize_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
337 {"mac_rx_oversize_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
339 {"mac_rx_64_oct_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
341 {"mac_rx_65_127_oct_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
343 {"mac_rx_128_255_oct_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
345 {"mac_rx_256_511_oct_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
347 {"mac_rx_512_1023_oct_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
349 {"mac_rx_1024_1518_oct_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
351 {"mac_rx_1519_2047_oct_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
353 {"mac_rx_2048_4095_oct_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
355 {"mac_rx_4096_8191_oct_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
357 {"mac_rx_8192_9216_oct_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
359 {"mac_rx_9217_12287_oct_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
361 {"mac_rx_12288_16383_oct_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
363 {"mac_rx_1519_max_good_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
365 {"mac_rx_1519_max_bad_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
368 {"mac_tx_fragment_pkt_num",
369 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
370 {"mac_tx_undermin_pkt_num",
371 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
372 {"mac_tx_jabber_pkt_num",
373 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
374 {"mac_tx_err_all_pkt_num",
375 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
376 {"mac_tx_from_app_good_pkt_num",
377 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
378 {"mac_tx_from_app_bad_pkt_num",
379 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
380 {"mac_rx_fragment_pkt_num",
381 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
382 {"mac_rx_undermin_pkt_num",
383 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
384 {"mac_rx_jabber_pkt_num",
385 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
386 {"mac_rx_fcs_err_pkt_num",
387 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
388 {"mac_rx_send_app_good_pkt_num",
389 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
390 {"mac_rx_send_app_bad_pkt_num",
391 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
394 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
396 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
397 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
398 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
399 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
400 .i_port_bitmap
= 0x1,
404 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
406 #define HCLGE_64_BIT_CMD_NUM 5
407 #define HCLGE_64_BIT_RTN_DATANUM 4
408 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
409 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
414 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
415 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
417 dev_err(&hdev
->pdev
->dev
,
418 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
422 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
423 if (unlikely(i
== 0)) {
424 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
425 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
427 desc_data
= (__le64
*)(&desc
[i
]);
428 n
= HCLGE_64_BIT_RTN_DATANUM
;
430 for (k
= 0; k
< n
; k
++) {
431 *data
++ += le64_to_cpu(*desc_data
);
439 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
441 stats
->pkt_curr_buf_cnt
= 0;
442 stats
->pkt_curr_buf_tc0_cnt
= 0;
443 stats
->pkt_curr_buf_tc1_cnt
= 0;
444 stats
->pkt_curr_buf_tc2_cnt
= 0;
445 stats
->pkt_curr_buf_tc3_cnt
= 0;
446 stats
->pkt_curr_buf_tc4_cnt
= 0;
447 stats
->pkt_curr_buf_tc5_cnt
= 0;
448 stats
->pkt_curr_buf_tc6_cnt
= 0;
449 stats
->pkt_curr_buf_tc7_cnt
= 0;
452 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
454 #define HCLGE_32_BIT_CMD_NUM 8
455 #define HCLGE_32_BIT_RTN_DATANUM 8
457 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
458 struct hclge_32_bit_stats
*all_32_bit_stats
;
464 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
465 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
467 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
468 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
470 dev_err(&hdev
->pdev
->dev
,
471 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
476 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
477 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
478 if (unlikely(i
== 0)) {
479 __le16
*desc_data_16bit
;
481 all_32_bit_stats
->igu_rx_err_pkt
+=
482 le32_to_cpu(desc
[i
].data
[0]);
484 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
485 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
486 le16_to_cpu(*desc_data_16bit
);
489 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
490 le16_to_cpu(*desc_data_16bit
);
492 desc_data
= &desc
[i
].data
[2];
493 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
495 desc_data
= (__le32
*)&desc
[i
];
496 n
= HCLGE_32_BIT_RTN_DATANUM
;
498 for (k
= 0; k
< n
; k
++) {
499 *data
++ += le32_to_cpu(*desc_data
);
507 static int hclge_mac_get_traffic_stats(struct hclge_dev
*hdev
)
509 struct hclge_mac_stats
*mac_stats
= &hdev
->hw_stats
.mac_stats
;
510 struct hclge_desc desc
;
514 /* for fiber port, need to query the total rx/tx packets statstics,
515 * used for data transferring checking.
517 if (hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
520 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
523 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_STATS_MAC_TRAFFIC
, true);
524 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
526 dev_err(&hdev
->pdev
->dev
,
527 "Get MAC total pkt stats fail, ret = %d\n", ret
);
532 desc_data
= (__le64
*)(&desc
.data
[0]);
533 mac_stats
->mac_tx_total_pkt_num
+= le64_to_cpu(*desc_data
++);
534 mac_stats
->mac_rx_total_pkt_num
+= le64_to_cpu(*desc_data
);
539 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
541 #define HCLGE_MAC_CMD_NUM 21
542 #define HCLGE_RTN_DATA_NUM 4
544 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
545 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
550 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
551 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
553 dev_err(&hdev
->pdev
->dev
,
554 "Get MAC pkt stats fail, status = %d.\n", ret
);
559 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
560 if (unlikely(i
== 0)) {
561 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
562 n
= HCLGE_RTN_DATA_NUM
- 2;
564 desc_data
= (__le64
*)(&desc
[i
]);
565 n
= HCLGE_RTN_DATA_NUM
;
567 for (k
= 0; k
< n
; k
++) {
568 *data
++ += le64_to_cpu(*desc_data
);
576 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
578 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
579 struct hclge_vport
*vport
= hclge_get_vport(handle
);
580 struct hclge_dev
*hdev
= vport
->back
;
581 struct hnae3_queue
*queue
;
582 struct hclge_desc desc
[1];
583 struct hclge_tqp
*tqp
;
586 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
587 queue
= handle
->kinfo
.tqp
[i
];
588 tqp
= container_of(queue
, struct hclge_tqp
, q
);
589 /* command : HCLGE_OPC_QUERY_IGU_STAT */
590 hclge_cmd_setup_basic_desc(&desc
[0],
591 HCLGE_OPC_QUERY_RX_STATUS
,
594 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
595 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
597 dev_err(&hdev
->pdev
->dev
,
598 "Query tqp stat fail, status = %d,queue = %d\n",
602 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
603 le32_to_cpu(desc
[0].data
[1]);
606 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
607 queue
= handle
->kinfo
.tqp
[i
];
608 tqp
= container_of(queue
, struct hclge_tqp
, q
);
609 /* command : HCLGE_OPC_QUERY_IGU_STAT */
610 hclge_cmd_setup_basic_desc(&desc
[0],
611 HCLGE_OPC_QUERY_TX_STATUS
,
614 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
615 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
617 dev_err(&hdev
->pdev
->dev
,
618 "Query tqp stat fail, status = %d,queue = %d\n",
622 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
623 le32_to_cpu(desc
[0].data
[1]);
629 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
631 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
632 struct hclge_tqp
*tqp
;
636 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
637 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
638 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
641 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
642 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
643 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
649 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
651 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
653 return kinfo
->num_tqps
* (2);
656 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
658 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
662 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
663 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
664 struct hclge_tqp
, q
);
665 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
667 buff
= buff
+ ETH_GSTRING_LEN
;
670 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
671 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
672 struct hclge_tqp
, q
);
673 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
675 buff
= buff
+ ETH_GSTRING_LEN
;
681 static u64
*hclge_comm_get_stats(void *comm_stats
,
682 const struct hclge_comm_stats_str strs
[],
688 for (i
= 0; i
< size
; i
++)
689 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
694 static u8
*hclge_comm_get_strings(u32 stringset
,
695 const struct hclge_comm_stats_str strs
[],
698 char *buff
= (char *)data
;
701 if (stringset
!= ETH_SS_STATS
)
704 for (i
= 0; i
< size
; i
++) {
705 snprintf(buff
, ETH_GSTRING_LEN
,
707 buff
= buff
+ ETH_GSTRING_LEN
;
713 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
714 struct net_device_stats
*net_stats
)
716 net_stats
->tx_dropped
= 0;
717 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
718 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
719 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
721 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
722 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
723 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
724 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
725 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
727 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
728 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
730 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
731 net_stats
->rx_length_errors
=
732 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
733 net_stats
->rx_length_errors
+=
734 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
735 net_stats
->rx_over_errors
=
736 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
739 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
741 struct hnae3_handle
*handle
;
744 handle
= &hdev
->vport
[0].nic
;
745 if (handle
->client
) {
746 status
= hclge_tqps_update_stats(handle
);
748 dev_err(&hdev
->pdev
->dev
,
749 "Update TQPS stats fail, status = %d.\n",
754 status
= hclge_mac_update_stats(hdev
);
756 dev_err(&hdev
->pdev
->dev
,
757 "Update MAC stats fail, status = %d.\n", status
);
759 status
= hclge_32_bit_update_stats(hdev
);
761 dev_err(&hdev
->pdev
->dev
,
762 "Update 32 bit stats fail, status = %d.\n",
765 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
768 static void hclge_update_stats(struct hnae3_handle
*handle
,
769 struct net_device_stats
*net_stats
)
771 struct hclge_vport
*vport
= hclge_get_vport(handle
);
772 struct hclge_dev
*hdev
= vport
->back
;
773 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
776 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
779 status
= hclge_mac_update_stats(hdev
);
781 dev_err(&hdev
->pdev
->dev
,
782 "Update MAC stats fail, status = %d.\n",
785 status
= hclge_32_bit_update_stats(hdev
);
787 dev_err(&hdev
->pdev
->dev
,
788 "Update 32 bit stats fail, status = %d.\n",
791 status
= hclge_64_bit_update_stats(hdev
);
793 dev_err(&hdev
->pdev
->dev
,
794 "Update 64 bit stats fail, status = %d.\n",
797 status
= hclge_tqps_update_stats(handle
);
799 dev_err(&hdev
->pdev
->dev
,
800 "Update TQPS stats fail, status = %d.\n",
803 hclge_update_netstat(hw_stats
, net_stats
);
805 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
808 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
810 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
812 struct hclge_vport
*vport
= hclge_get_vport(handle
);
813 struct hclge_dev
*hdev
= vport
->back
;
816 /* Loopback test support rules:
817 * mac: only GE mode support
818 * serdes: all mac mode will support include GE/XGE/LGE/CGE
819 * phy: only support when phy device exist on board
821 if (stringset
== ETH_SS_TEST
) {
822 /* clear loopback bit flags at first */
823 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
824 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
825 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
826 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
828 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
832 } else if (stringset
== ETH_SS_STATS
) {
833 count
= ARRAY_SIZE(g_mac_stats_string
) +
834 ARRAY_SIZE(g_all_32bit_stats_string
) +
835 ARRAY_SIZE(g_all_64bit_stats_string
) +
836 hclge_tqps_get_sset_count(handle
, stringset
);
842 static void hclge_get_strings(struct hnae3_handle
*handle
,
846 u8
*p
= (char *)data
;
849 if (stringset
== ETH_SS_STATS
) {
850 size
= ARRAY_SIZE(g_mac_stats_string
);
851 p
= hclge_comm_get_strings(stringset
,
855 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
856 p
= hclge_comm_get_strings(stringset
,
857 g_all_32bit_stats_string
,
860 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
861 p
= hclge_comm_get_strings(stringset
,
862 g_all_64bit_stats_string
,
865 p
= hclge_tqps_get_strings(handle
, p
);
866 } else if (stringset
== ETH_SS_TEST
) {
867 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
869 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
871 p
+= ETH_GSTRING_LEN
;
873 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
875 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
877 p
+= ETH_GSTRING_LEN
;
879 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
881 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
883 p
+= ETH_GSTRING_LEN
;
888 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
890 struct hclge_vport
*vport
= hclge_get_vport(handle
);
891 struct hclge_dev
*hdev
= vport
->back
;
894 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
896 ARRAY_SIZE(g_mac_stats_string
),
898 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
899 g_all_32bit_stats_string
,
900 ARRAY_SIZE(g_all_32bit_stats_string
),
902 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
903 g_all_64bit_stats_string
,
904 ARRAY_SIZE(g_all_64bit_stats_string
),
906 p
= hclge_tqps_get_stats(handle
, p
);
909 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
910 struct hclge_func_status_cmd
*status
)
912 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
915 /* Set the pf to main pf */
916 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
917 hdev
->flag
|= HCLGE_FLAG_MAIN
;
919 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
924 static int hclge_query_function_status(struct hclge_dev
*hdev
)
926 struct hclge_func_status_cmd
*req
;
927 struct hclge_desc desc
;
931 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
932 req
= (struct hclge_func_status_cmd
*)desc
.data
;
935 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
937 dev_err(&hdev
->pdev
->dev
,
938 "query function status failed %d.\n",
944 /* Check pf reset is done */
947 usleep_range(1000, 2000);
948 } while (timeout
++ < 5);
950 ret
= hclge_parse_func_status(hdev
, req
);
955 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
957 struct hclge_pf_res_cmd
*req
;
958 struct hclge_desc desc
;
961 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
962 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
964 dev_err(&hdev
->pdev
->dev
,
965 "query pf resource failed %d.\n", ret
);
969 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
970 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
971 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
973 if (hnae3_dev_roce_supported(hdev
)) {
975 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
976 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
978 /* PF should have NIC vectors and Roce vectors,
979 * NIC vectors are queued before Roce vectors.
981 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
984 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
985 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
991 static int hclge_parse_speed(int speed_cmd
, int *speed
)
995 *speed
= HCLGE_MAC_SPEED_10M
;
998 *speed
= HCLGE_MAC_SPEED_100M
;
1001 *speed
= HCLGE_MAC_SPEED_1G
;
1004 *speed
= HCLGE_MAC_SPEED_10G
;
1007 *speed
= HCLGE_MAC_SPEED_25G
;
1010 *speed
= HCLGE_MAC_SPEED_40G
;
1013 *speed
= HCLGE_MAC_SPEED_50G
;
1016 *speed
= HCLGE_MAC_SPEED_100G
;
1025 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
1028 unsigned long *supported
= hdev
->hw
.mac
.supported
;
1030 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
1031 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1034 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1035 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1038 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1039 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1042 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1043 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1046 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1047 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1050 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1051 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1054 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1056 u8 media_type
= hdev
->hw
.mac
.media_type
;
1058 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1061 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1064 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1066 struct hclge_cfg_param_cmd
*req
;
1067 u64 mac_addr_tmp_high
;
1071 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1073 /* get the configuration */
1074 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1077 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1078 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1079 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1080 HCLGE_CFG_TQP_DESC_N_M
,
1081 HCLGE_CFG_TQP_DESC_N_S
);
1083 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1084 HCLGE_CFG_PHY_ADDR_M
,
1085 HCLGE_CFG_PHY_ADDR_S
);
1086 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1087 HCLGE_CFG_MEDIA_TP_M
,
1088 HCLGE_CFG_MEDIA_TP_S
);
1089 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1090 HCLGE_CFG_RX_BUF_LEN_M
,
1091 HCLGE_CFG_RX_BUF_LEN_S
);
1092 /* get mac_address */
1093 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1094 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1095 HCLGE_CFG_MAC_ADDR_H_M
,
1096 HCLGE_CFG_MAC_ADDR_H_S
);
1098 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1100 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1101 HCLGE_CFG_DEFAULT_SPEED_M
,
1102 HCLGE_CFG_DEFAULT_SPEED_S
);
1103 cfg
->rss_size_max
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1104 HCLGE_CFG_RSS_SIZE_M
,
1105 HCLGE_CFG_RSS_SIZE_S
);
1107 for (i
= 0; i
< ETH_ALEN
; i
++)
1108 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1110 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1111 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1113 cfg
->speed_ability
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1114 HCLGE_CFG_SPEED_ABILITY_M
,
1115 HCLGE_CFG_SPEED_ABILITY_S
);
1118 /* hclge_get_cfg: query the static parameter from flash
1119 * @hdev: pointer to struct hclge_dev
1120 * @hcfg: the config structure to be getted
1122 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1124 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1125 struct hclge_cfg_param_cmd
*req
;
1128 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1131 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1132 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1134 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1135 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1136 /* Len should be united by 4 bytes when send to hardware */
1137 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1138 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1139 req
->offset
= cpu_to_le32(offset
);
1142 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1144 dev_err(&hdev
->pdev
->dev
,
1145 "get config failed %d.\n", ret
);
1149 hclge_parse_cfg(hcfg
, desc
);
1153 static int hclge_get_cap(struct hclge_dev
*hdev
)
1157 ret
= hclge_query_function_status(hdev
);
1159 dev_err(&hdev
->pdev
->dev
,
1160 "query function status error %d.\n", ret
);
1164 /* get pf resource */
1165 ret
= hclge_query_pf_resource(hdev
);
1167 dev_err(&hdev
->pdev
->dev
,
1168 "query pf resource error %d.\n", ret
);
1175 static int hclge_configure(struct hclge_dev
*hdev
)
1177 struct hclge_cfg cfg
;
1180 ret
= hclge_get_cfg(hdev
, &cfg
);
1182 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1186 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1187 hdev
->base_tqp_pid
= 0;
1188 hdev
->rss_size_max
= cfg
.rss_size_max
;
1189 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1190 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1191 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1192 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1193 hdev
->num_desc
= cfg
.tqp_desc_num
;
1194 hdev
->tm_info
.num_pg
= 1;
1195 hdev
->tc_max
= cfg
.tc_num
;
1196 hdev
->tm_info
.hw_pfc_map
= 0;
1198 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1200 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1204 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1206 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1207 (hdev
->tc_max
< 1)) {
1208 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1213 /* Dev does not support DCB */
1214 if (!hnae3_dev_dcb_supported(hdev
)) {
1218 hdev
->pfc_max
= hdev
->tc_max
;
1221 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1223 /* Currently not support uncontiuous tc */
1224 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1225 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1227 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1232 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1235 struct hclge_cfg_tso_status_cmd
*req
;
1236 struct hclge_desc desc
;
1239 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1241 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1244 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1245 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1246 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1249 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1250 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1251 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1253 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1256 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1258 struct hclge_tqp
*tqp
;
1261 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1262 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1268 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1269 tqp
->dev
= &hdev
->pdev
->dev
;
1272 tqp
->q
.ae_algo
= &ae_algo
;
1273 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1274 tqp
->q
.desc_num
= hdev
->num_desc
;
1275 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1276 i
* HCLGE_TQP_REG_SIZE
;
1284 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1285 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1287 struct hclge_tqp_map_cmd
*req
;
1288 struct hclge_desc desc
;
1291 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1293 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1294 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1295 req
->tqp_vf
= func_id
;
1296 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1297 1 << HCLGE_TQP_MAP_EN_B
;
1298 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1300 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1302 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1310 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1311 struct hnae3_queue
**tqp
, u16 num_tqps
)
1313 struct hclge_dev
*hdev
= vport
->back
;
1316 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1317 alloced
< num_tqps
; i
++) {
1318 if (!hdev
->htqp
[i
].alloced
) {
1319 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1320 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1321 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1322 hdev
->htqp
[i
].alloced
= true;
1326 vport
->alloc_tqps
= num_tqps
;
1331 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1333 struct hnae3_handle
*nic
= &vport
->nic
;
1334 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1335 struct hclge_dev
*hdev
= vport
->back
;
1338 kinfo
->num_desc
= hdev
->num_desc
;
1339 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1340 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1342 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1343 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1345 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1346 if (hdev
->hw_tc_map
& BIT(i
)) {
1347 kinfo
->tc_info
[i
].enable
= true;
1348 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1349 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1350 kinfo
->tc_info
[i
].tc
= i
;
1352 /* Set to default queue if TC is disable */
1353 kinfo
->tc_info
[i
].enable
= false;
1354 kinfo
->tc_info
[i
].tqp_offset
= 0;
1355 kinfo
->tc_info
[i
].tqp_count
= 1;
1356 kinfo
->tc_info
[i
].tc
= 0;
1360 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1361 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1365 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1367 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1374 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1375 struct hclge_vport
*vport
)
1377 struct hnae3_handle
*nic
= &vport
->nic
;
1378 struct hnae3_knic_private_info
*kinfo
;
1381 kinfo
= &nic
->kinfo
;
1382 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1383 struct hclge_tqp
*q
=
1384 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1388 is_pf
= !(vport
->vport_id
);
1389 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1398 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1400 struct hclge_vport
*vport
= hdev
->vport
;
1403 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1404 for (i
= 0; i
< num_vport
; i
++) {
1407 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1417 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1419 /* this would be initialized later */
1422 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1424 struct hnae3_handle
*nic
= &vport
->nic
;
1425 struct hclge_dev
*hdev
= vport
->back
;
1428 nic
->pdev
= hdev
->pdev
;
1429 nic
->ae_algo
= &ae_algo
;
1430 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1432 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1433 ret
= hclge_knic_setup(vport
, num_tqps
);
1435 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1440 hclge_unic_setup(vport
, num_tqps
);
1446 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1448 struct pci_dev
*pdev
= hdev
->pdev
;
1449 struct hclge_vport
*vport
;
1455 /* We need to alloc a vport for main NIC of PF */
1456 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1458 if (hdev
->num_tqps
< num_vport
) {
1459 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1460 hdev
->num_tqps
, num_vport
);
1464 /* Alloc the same number of TQPs for every vport */
1465 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1466 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1468 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1473 hdev
->vport
= vport
;
1474 hdev
->num_alloc_vport
= num_vport
;
1476 #ifdef CONFIG_PCI_IOV
1478 if (hdev
->num_req_vfs
) {
1479 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1481 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1483 hdev
->num_alloc_vfs
= 0;
1484 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1489 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1492 for (i
= 0; i
< num_vport
; i
++) {
1494 vport
->vport_id
= i
;
1497 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1499 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1502 "vport setup failed for vport %d, %d\n",
1513 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1514 struct hclge_pkt_buf_alloc
*buf_alloc
)
1516 /* TX buffer size is unit by 128 byte */
1517 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1518 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1519 struct hclge_tx_buff_alloc_cmd
*req
;
1520 struct hclge_desc desc
;
1524 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1526 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1527 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1528 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1530 req
->tx_pkt_buff
[i
] =
1531 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1532 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1535 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1537 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1545 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1546 struct hclge_pkt_buf_alloc
*buf_alloc
)
1548 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1551 dev_err(&hdev
->pdev
->dev
,
1552 "tx buffer alloc failed %d\n", ret
);
1559 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1563 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1564 if (hdev
->hw_tc_map
& BIT(i
))
1569 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1573 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1574 if (hdev
->hw_tc_map
& BIT(i
) &&
1575 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1580 /* Get the number of pfc enabled TCs, which have private buffer */
1581 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1582 struct hclge_pkt_buf_alloc
*buf_alloc
)
1584 struct hclge_priv_buf
*priv
;
1587 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1588 priv
= &buf_alloc
->priv_buf
[i
];
1589 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1597 /* Get the number of pfc disabled TCs, which have private buffer */
1598 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1599 struct hclge_pkt_buf_alloc
*buf_alloc
)
1601 struct hclge_priv_buf
*priv
;
1604 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1605 priv
= &buf_alloc
->priv_buf
[i
];
1606 if (hdev
->hw_tc_map
& BIT(i
) &&
1607 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1615 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1617 struct hclge_priv_buf
*priv
;
1621 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1622 priv
= &buf_alloc
->priv_buf
[i
];
1624 rx_priv
+= priv
->buf_size
;
1629 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1631 u32 i
, total_tx_size
= 0;
1633 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1634 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1636 return total_tx_size
;
1639 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1640 struct hclge_pkt_buf_alloc
*buf_alloc
,
1643 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1644 int tc_num
, pfc_enable_num
;
1649 tc_num
= hclge_get_tc_num(hdev
);
1650 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1652 if (hnae3_dev_dcb_supported(hdev
))
1653 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1655 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1657 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1658 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1660 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1662 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1663 if (rx_all
<= rx_priv
+ shared_std
)
1666 shared_buf
= rx_all
- rx_priv
;
1667 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1668 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1669 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1671 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1672 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1673 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1674 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1675 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1677 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1678 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1685 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1686 struct hclge_pkt_buf_alloc
*buf_alloc
)
1690 total_size
= hdev
->pkt_buf_size
;
1692 /* alloc tx buffer for all enabled tc */
1693 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1694 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1696 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1699 if (hdev
->hw_tc_map
& BIT(i
))
1700 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1702 priv
->tx_buf_size
= 0;
1704 total_size
-= priv
->tx_buf_size
;
1710 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1711 * @hdev: pointer to struct hclge_dev
1712 * @buf_alloc: pointer to buffer calculation data
1713 * @return: 0: calculate sucessful, negative: fail
1715 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1716 struct hclge_pkt_buf_alloc
*buf_alloc
)
1718 u32 rx_all
= hdev
->pkt_buf_size
;
1719 int no_pfc_priv_num
, pfc_priv_num
;
1720 struct hclge_priv_buf
*priv
;
1723 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1725 /* When DCB is not supported, rx private
1726 * buffer is not allocated.
1728 if (!hnae3_dev_dcb_supported(hdev
)) {
1729 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1735 /* step 1, try to alloc private buffer for all enabled tc */
1736 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1737 priv
= &buf_alloc
->priv_buf
[i
];
1738 if (hdev
->hw_tc_map
& BIT(i
)) {
1740 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1741 priv
->wl
.low
= hdev
->mps
;
1742 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1743 priv
->buf_size
= priv
->wl
.high
+
1747 priv
->wl
.high
= 2 * hdev
->mps
;
1748 priv
->buf_size
= priv
->wl
.high
;
1758 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1761 /* step 2, try to decrease the buffer size of
1762 * no pfc TC's private buffer
1764 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1765 priv
= &buf_alloc
->priv_buf
[i
];
1772 if (!(hdev
->hw_tc_map
& BIT(i
)))
1777 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1779 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1780 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1783 priv
->wl
.high
= hdev
->mps
;
1784 priv
->buf_size
= priv
->wl
.high
;
1788 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1791 /* step 3, try to reduce the number of pfc disabled TCs,
1792 * which have private buffer
1794 /* get the total no pfc enable TC number, which have private buffer */
1795 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1797 /* let the last to be cleared first */
1798 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1799 priv
= &buf_alloc
->priv_buf
[i
];
1801 if (hdev
->hw_tc_map
& BIT(i
) &&
1802 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1803 /* Clear the no pfc TC private buffer */
1811 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1812 no_pfc_priv_num
== 0)
1816 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1819 /* step 4, try to reduce the number of pfc enabled TCs
1820 * which have private buffer.
1822 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1824 /* let the last to be cleared first */
1825 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1826 priv
= &buf_alloc
->priv_buf
[i
];
1828 if (hdev
->hw_tc_map
& BIT(i
) &&
1829 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1830 /* Reduce the number of pfc TC with private buffer */
1838 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1842 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1848 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1849 struct hclge_pkt_buf_alloc
*buf_alloc
)
1851 struct hclge_rx_priv_buff_cmd
*req
;
1852 struct hclge_desc desc
;
1856 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1857 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1859 /* Alloc private buffer TCs */
1860 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1861 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1864 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1866 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1870 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1871 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1873 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1875 dev_err(&hdev
->pdev
->dev
,
1876 "rx private buffer alloc cmd failed %d\n", ret
);
1883 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1885 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1886 struct hclge_pkt_buf_alloc
*buf_alloc
)
1888 struct hclge_rx_priv_wl_buf
*req
;
1889 struct hclge_priv_buf
*priv
;
1890 struct hclge_desc desc
[2];
1894 for (i
= 0; i
< 2; i
++) {
1895 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1897 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1899 /* The first descriptor set the NEXT bit to 1 */
1901 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1903 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1905 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1906 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1908 priv
= &buf_alloc
->priv_buf
[idx
];
1909 req
->tc_wl
[j
].high
=
1910 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1911 req
->tc_wl
[j
].high
|=
1912 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1913 HCLGE_RX_PRIV_EN_B
);
1915 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1916 req
->tc_wl
[j
].low
|=
1917 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1918 HCLGE_RX_PRIV_EN_B
);
1922 /* Send 2 descriptor at one time */
1923 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1925 dev_err(&hdev
->pdev
->dev
,
1926 "rx private waterline config cmd failed %d\n",
1933 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1934 struct hclge_pkt_buf_alloc
*buf_alloc
)
1936 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1937 struct hclge_rx_com_thrd
*req
;
1938 struct hclge_desc desc
[2];
1939 struct hclge_tc_thrd
*tc
;
1943 for (i
= 0; i
< 2; i
++) {
1944 hclge_cmd_setup_basic_desc(&desc
[i
],
1945 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1946 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1948 /* The first descriptor set the NEXT bit to 1 */
1950 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1952 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1954 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1955 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1957 req
->com_thrd
[j
].high
=
1958 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1959 req
->com_thrd
[j
].high
|=
1960 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1961 HCLGE_RX_PRIV_EN_B
);
1962 req
->com_thrd
[j
].low
=
1963 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1964 req
->com_thrd
[j
].low
|=
1965 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1966 HCLGE_RX_PRIV_EN_B
);
1970 /* Send 2 descriptors at one time */
1971 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1973 dev_err(&hdev
->pdev
->dev
,
1974 "common threshold config cmd failed %d\n", ret
);
1980 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1981 struct hclge_pkt_buf_alloc
*buf_alloc
)
1983 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1984 struct hclge_rx_com_wl
*req
;
1985 struct hclge_desc desc
;
1988 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1990 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1991 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1993 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1994 HCLGE_RX_PRIV_EN_B
);
1996 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1998 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1999 HCLGE_RX_PRIV_EN_B
);
2001 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2003 dev_err(&hdev
->pdev
->dev
,
2004 "common waterline config cmd failed %d\n", ret
);
2011 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
2013 struct hclge_pkt_buf_alloc
*pkt_buf
;
2016 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
2020 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
2022 dev_err(&hdev
->pdev
->dev
,
2023 "could not calc tx buffer size for all TCs %d\n", ret
);
2027 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
2029 dev_err(&hdev
->pdev
->dev
,
2030 "could not alloc tx buffers %d\n", ret
);
2034 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
2036 dev_err(&hdev
->pdev
->dev
,
2037 "could not calc rx priv buffer size for all TCs %d\n",
2042 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
2044 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
2049 if (hnae3_dev_dcb_supported(hdev
)) {
2050 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
2052 dev_err(&hdev
->pdev
->dev
,
2053 "could not configure rx private waterline %d\n",
2058 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
2060 dev_err(&hdev
->pdev
->dev
,
2061 "could not configure common threshold %d\n",
2067 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2069 dev_err(&hdev
->pdev
->dev
,
2070 "could not configure common waterline %d\n", ret
);
2077 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2079 struct hnae3_handle
*roce
= &vport
->roce
;
2080 struct hnae3_handle
*nic
= &vport
->nic
;
2082 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2084 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2085 vport
->back
->num_msi_left
== 0)
2088 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2090 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2091 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2093 roce
->pdev
= nic
->pdev
;
2094 roce
->ae_algo
= nic
->ae_algo
;
2095 roce
->numa_node_mask
= nic
->numa_node_mask
;
2100 static int hclge_init_msi(struct hclge_dev
*hdev
)
2102 struct pci_dev
*pdev
= hdev
->pdev
;
2106 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2107 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2110 "failed(%d) to allocate MSI/MSI-X vectors\n",
2114 if (vectors
< hdev
->num_msi
)
2115 dev_warn(&hdev
->pdev
->dev
,
2116 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2117 hdev
->num_msi
, vectors
);
2119 hdev
->num_msi
= vectors
;
2120 hdev
->num_msi_left
= vectors
;
2121 hdev
->base_msi_vector
= pdev
->irq
;
2122 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2123 HCLGE_ROCE_VECTOR_OFFSET
;
2125 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2126 sizeof(u16
), GFP_KERNEL
);
2127 if (!hdev
->vector_status
) {
2128 pci_free_irq_vectors(pdev
);
2132 for (i
= 0; i
< hdev
->num_msi
; i
++)
2133 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2135 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2136 sizeof(int), GFP_KERNEL
);
2137 if (!hdev
->vector_irq
) {
2138 pci_free_irq_vectors(pdev
);
2145 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2147 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2149 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2150 mac
->duplex
= (u8
)duplex
;
2152 mac
->duplex
= HCLGE_MAC_FULL
;
2157 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2159 struct hclge_config_mac_speed_dup_cmd
*req
;
2160 struct hclge_desc desc
;
2163 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2165 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2167 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2170 case HCLGE_MAC_SPEED_10M
:
2171 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2172 HCLGE_CFG_SPEED_S
, 6);
2174 case HCLGE_MAC_SPEED_100M
:
2175 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2176 HCLGE_CFG_SPEED_S
, 7);
2178 case HCLGE_MAC_SPEED_1G
:
2179 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2180 HCLGE_CFG_SPEED_S
, 0);
2182 case HCLGE_MAC_SPEED_10G
:
2183 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2184 HCLGE_CFG_SPEED_S
, 1);
2186 case HCLGE_MAC_SPEED_25G
:
2187 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2188 HCLGE_CFG_SPEED_S
, 2);
2190 case HCLGE_MAC_SPEED_40G
:
2191 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2192 HCLGE_CFG_SPEED_S
, 3);
2194 case HCLGE_MAC_SPEED_50G
:
2195 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2196 HCLGE_CFG_SPEED_S
, 4);
2198 case HCLGE_MAC_SPEED_100G
:
2199 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2200 HCLGE_CFG_SPEED_S
, 5);
2203 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2207 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2210 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2212 dev_err(&hdev
->pdev
->dev
,
2213 "mac speed/duplex config cmd failed %d.\n", ret
);
2217 hclge_check_speed_dup(hdev
, duplex
, speed
);
2222 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2225 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2226 struct hclge_dev
*hdev
= vport
->back
;
2228 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2231 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2234 struct hclge_query_an_speed_dup_cmd
*req
;
2235 struct hclge_desc desc
;
2239 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2241 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2242 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2244 dev_err(&hdev
->pdev
->dev
,
2245 "mac speed/autoneg/duplex query cmd failed %d\n",
2250 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2251 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2252 HCLGE_QUERY_SPEED_S
);
2254 ret
= hclge_parse_speed(speed_tmp
, speed
);
2256 dev_err(&hdev
->pdev
->dev
,
2257 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2264 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2266 struct hclge_config_auto_neg_cmd
*req
;
2267 struct hclge_desc desc
;
2271 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2273 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2274 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2275 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2277 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2279 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2287 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2289 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2290 struct hclge_dev
*hdev
= vport
->back
;
2292 return hclge_set_autoneg_en(hdev
, enable
);
2295 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2297 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2298 struct hclge_dev
*hdev
= vport
->back
;
2299 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2302 return phydev
->autoneg
;
2304 return hdev
->hw
.mac
.autoneg
;
2307 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2311 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2312 struct hclge_desc desc
;
2315 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2316 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2318 hnae_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2320 ether_addr_copy(req
->mac_mask
, mac_mask
);
2322 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2324 dev_err(&hdev
->pdev
->dev
,
2325 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2331 static int hclge_mac_init(struct hclge_dev
*hdev
)
2333 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2334 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2335 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2336 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2340 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2342 dev_err(&hdev
->pdev
->dev
,
2343 "Config mac speed dup fail ret=%d\n", ret
);
2349 /* Initialize the MTA table work mode */
2350 hdev
->accept_mta_mc
= true;
2351 hdev
->enable_mta
= true;
2352 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2354 ret
= hclge_set_mta_filter_mode(hdev
,
2355 hdev
->mta_mac_sel_type
,
2358 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2363 ret
= hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2365 dev_err(&hdev
->pdev
->dev
,
2366 "set mta filter mode fail ret=%d\n", ret
);
2370 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2372 dev_err(&hdev
->pdev
->dev
,
2373 "set default mac_vlan_mask fail ret=%d\n", ret
);
2382 ret
= hclge_set_mtu(handle
, mtu
);
2384 dev_err(&hdev
->pdev
->dev
,
2385 "set mtu failed ret=%d\n", ret
);
2392 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2394 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2395 schedule_work(&hdev
->mbx_service_task
);
2398 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2400 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2401 schedule_work(&hdev
->rst_service_task
);
2404 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2406 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2407 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2408 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2409 (void)schedule_work(&hdev
->service_task
);
2412 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2414 struct hclge_link_status_cmd
*req
;
2415 struct hclge_desc desc
;
2419 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2420 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2422 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2427 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2428 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2430 return !!link_status
;
2433 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2438 mac_state
= hclge_get_mac_link_status(hdev
);
2440 if (hdev
->hw
.mac
.phydev
) {
2441 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2442 link_stat
= mac_state
&
2443 hdev
->hw
.mac
.phydev
->link
;
2448 link_stat
= mac_state
;
2454 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2456 struct hnae3_client
*client
= hdev
->nic_client
;
2457 struct hnae3_handle
*handle
;
2463 state
= hclge_get_mac_phy_link(hdev
);
2464 if (state
!= hdev
->hw
.mac
.link
) {
2465 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2466 handle
= &hdev
->vport
[i
].nic
;
2467 client
->ops
->link_status_change(handle
, state
);
2469 hdev
->hw
.mac
.link
= state
;
2473 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2475 struct hclge_mac mac
= hdev
->hw
.mac
;
2480 /* get the speed and duplex as autoneg'result from mac cmd when phy
2483 if (mac
.phydev
|| !mac
.autoneg
)
2486 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2488 dev_err(&hdev
->pdev
->dev
,
2489 "mac autoneg/speed/duplex query failed %d\n", ret
);
2493 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2494 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2496 dev_err(&hdev
->pdev
->dev
,
2497 "mac speed/duplex config failed %d\n", ret
);
2505 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2507 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2508 struct hclge_dev
*hdev
= vport
->back
;
2510 return hclge_update_speed_duplex(hdev
);
2513 static int hclge_get_status(struct hnae3_handle
*handle
)
2515 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2516 struct hclge_dev
*hdev
= vport
->back
;
2518 hclge_update_link_status(hdev
);
2520 return hdev
->hw
.mac
.link
;
2523 static void hclge_service_timer(struct timer_list
*t
)
2525 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2527 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2528 hdev
->hw_stats
.stats_timer
++;
2529 hclge_task_schedule(hdev
);
2532 static void hclge_service_complete(struct hclge_dev
*hdev
)
2534 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2536 /* Flush memory before next watchdog */
2537 smp_mb__before_atomic();
2538 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2541 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2546 /* fetch the events from their corresponding regs */
2547 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2548 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2550 /* Assumption: If by any chance reset and mailbox events are reported
2551 * together then we will only process reset event in this go and will
2552 * defer the processing of the mailbox events. Since, we would have not
2553 * cleared RX CMDQ event this time we would receive again another
2554 * interrupt from H/W just for the mailbox.
2557 /* check for vector0 reset event sources */
2558 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2559 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2560 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2561 return HCLGE_VECTOR0_EVENT_RST
;
2564 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2565 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2566 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2567 return HCLGE_VECTOR0_EVENT_RST
;
2570 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2571 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2572 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2573 return HCLGE_VECTOR0_EVENT_RST
;
2576 /* check for vector0 mailbox(=CMDQ RX) event source */
2577 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2578 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2579 *clearval
= cmdq_src_reg
;
2580 return HCLGE_VECTOR0_EVENT_MBX
;
2583 return HCLGE_VECTOR0_EVENT_OTHER
;
2586 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2589 switch (event_type
) {
2590 case HCLGE_VECTOR0_EVENT_RST
:
2591 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2593 case HCLGE_VECTOR0_EVENT_MBX
:
2594 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2599 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2601 writel(enable
? 1 : 0, vector
->addr
);
2604 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2606 struct hclge_dev
*hdev
= data
;
2610 hclge_enable_vector(&hdev
->misc_vector
, false);
2611 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2613 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2614 switch (event_cause
) {
2615 case HCLGE_VECTOR0_EVENT_RST
:
2616 hclge_reset_task_schedule(hdev
);
2618 case HCLGE_VECTOR0_EVENT_MBX
:
2619 /* If we are here then,
2620 * 1. Either we are not handling any mbx task and we are not
2623 * 2. We could be handling a mbx task but nothing more is
2625 * In both cases, we should schedule mbx task as there are more
2626 * mbx messages reported by this interrupt.
2628 hclge_mbx_task_schedule(hdev
);
2631 dev_dbg(&hdev
->pdev
->dev
,
2632 "received unknown or unhandled event of vector0\n");
2636 /* we should clear the source of interrupt */
2637 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2638 hclge_enable_vector(&hdev
->misc_vector
, true);
2643 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2645 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2646 hdev
->num_msi_left
+= 1;
2647 hdev
->num_msi_used
-= 1;
2650 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2652 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2654 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2656 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2657 hdev
->vector_status
[0] = 0;
2659 hdev
->num_msi_left
-= 1;
2660 hdev
->num_msi_used
+= 1;
2663 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2667 hclge_get_misc_vector(hdev
);
2669 /* this would be explicitly freed in the end */
2670 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2671 0, "hclge_misc", hdev
);
2673 hclge_free_vector(hdev
, 0);
2674 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2675 hdev
->misc_vector
.vector_irq
);
2681 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2683 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2684 hclge_free_vector(hdev
, 0);
2687 static int hclge_notify_client(struct hclge_dev
*hdev
,
2688 enum hnae3_reset_notify_type type
)
2690 struct hnae3_client
*client
= hdev
->nic_client
;
2693 if (!client
->ops
->reset_notify
)
2696 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2697 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2700 ret
= client
->ops
->reset_notify(handle
, type
);
2708 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2710 #define HCLGE_RESET_WATI_MS 100
2711 #define HCLGE_RESET_WAIT_CNT 5
2712 u32 val
, reg
, reg_bit
;
2715 switch (hdev
->reset_type
) {
2716 case HNAE3_GLOBAL_RESET
:
2717 reg
= HCLGE_GLOBAL_RESET_REG
;
2718 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2720 case HNAE3_CORE_RESET
:
2721 reg
= HCLGE_GLOBAL_RESET_REG
;
2722 reg_bit
= HCLGE_CORE_RESET_BIT
;
2724 case HNAE3_FUNC_RESET
:
2725 reg
= HCLGE_FUN_RST_ING
;
2726 reg_bit
= HCLGE_FUN_RST_ING_B
;
2729 dev_err(&hdev
->pdev
->dev
,
2730 "Wait for unsupported reset type: %d\n",
2735 val
= hclge_read_dev(&hdev
->hw
, reg
);
2736 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2737 msleep(HCLGE_RESET_WATI_MS
);
2738 val
= hclge_read_dev(&hdev
->hw
, reg
);
2742 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2743 dev_warn(&hdev
->pdev
->dev
,
2744 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2751 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2753 struct hclge_desc desc
;
2754 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2757 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2758 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_MAC_B
, 0);
2759 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2760 req
->fun_reset_vfid
= func_id
;
2762 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2764 dev_err(&hdev
->pdev
->dev
,
2765 "send function reset cmd fail, status =%d\n", ret
);
2770 static void hclge_do_reset(struct hclge_dev
*hdev
)
2772 struct pci_dev
*pdev
= hdev
->pdev
;
2775 switch (hdev
->reset_type
) {
2776 case HNAE3_GLOBAL_RESET
:
2777 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2778 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2779 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2780 dev_info(&pdev
->dev
, "Global Reset requested\n");
2782 case HNAE3_CORE_RESET
:
2783 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2784 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2785 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2786 dev_info(&pdev
->dev
, "Core Reset requested\n");
2788 case HNAE3_FUNC_RESET
:
2789 dev_info(&pdev
->dev
, "PF Reset requested\n");
2790 hclge_func_reset_cmd(hdev
, 0);
2791 /* schedule again to check later */
2792 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2793 hclge_reset_task_schedule(hdev
);
2796 dev_warn(&pdev
->dev
,
2797 "Unsupported reset type: %d\n", hdev
->reset_type
);
2802 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2803 unsigned long *addr
)
2805 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2807 /* return the highest priority reset level amongst all */
2808 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2809 rst_level
= HNAE3_GLOBAL_RESET
;
2810 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2811 rst_level
= HNAE3_CORE_RESET
;
2812 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2813 rst_level
= HNAE3_IMP_RESET
;
2814 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2815 rst_level
= HNAE3_FUNC_RESET
;
2817 /* now, clear all other resets */
2818 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2819 clear_bit(HNAE3_CORE_RESET
, addr
);
2820 clear_bit(HNAE3_IMP_RESET
, addr
);
2821 clear_bit(HNAE3_FUNC_RESET
, addr
);
2826 static void hclge_reset(struct hclge_dev
*hdev
)
2828 /* perform reset of the stack & ae device for a client */
2830 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2832 if (!hclge_reset_wait(hdev
)) {
2834 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2835 hclge_reset_ae_dev(hdev
->ae_dev
);
2836 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2839 /* schedule again to check pending resets later */
2840 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2841 hclge_reset_task_schedule(hdev
);
2844 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2847 static void hclge_reset_event(struct hnae3_handle
*handle
)
2849 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2850 struct hclge_dev
*hdev
= vport
->back
;
2852 /* check if this is a new reset request and we are not here just because
2853 * last reset attempt did not succeed and watchdog hit us again. We will
2854 * know this if last reset request did not occur very recently (watchdog
2855 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2856 * In case of new request we reset the "reset level" to PF reset.
2858 if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2859 handle
->reset_level
= HNAE3_FUNC_RESET
;
2861 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2862 handle
->reset_level
);
2864 /* request reset & schedule reset task */
2865 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2866 hclge_reset_task_schedule(hdev
);
2868 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2869 handle
->reset_level
++;
2871 handle
->last_reset_time
= jiffies
;
2874 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2876 /* check if there is any ongoing reset in the hardware. This status can
2877 * be checked from reset_pending. If there is then, we need to wait for
2878 * hardware to complete reset.
2879 * a. If we are able to figure out in reasonable time that hardware
2880 * has fully resetted then, we can proceed with driver, client
2882 * b. else, we can come back later to check this status so re-sched
2885 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2886 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2889 /* check if we got any *new* reset requests to be honored */
2890 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2891 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2892 hclge_do_reset(hdev
);
2894 hdev
->reset_type
= HNAE3_NONE_RESET
;
2897 static void hclge_reset_service_task(struct work_struct
*work
)
2899 struct hclge_dev
*hdev
=
2900 container_of(work
, struct hclge_dev
, rst_service_task
);
2902 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2905 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2907 hclge_reset_subtask(hdev
);
2909 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2912 static void hclge_mailbox_service_task(struct work_struct
*work
)
2914 struct hclge_dev
*hdev
=
2915 container_of(work
, struct hclge_dev
, mbx_service_task
);
2917 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2920 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2922 hclge_mbx_handler(hdev
);
2924 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2927 static void hclge_service_task(struct work_struct
*work
)
2929 struct hclge_dev
*hdev
=
2930 container_of(work
, struct hclge_dev
, service_task
);
2932 /* The total rx/tx packets statstics are wanted to be updated
2933 * per second. Both hclge_update_stats_for_all() and
2934 * hclge_mac_get_traffic_stats() can do it.
2936 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2937 hclge_update_stats_for_all(hdev
);
2938 hdev
->hw_stats
.stats_timer
= 0;
2940 hclge_mac_get_traffic_stats(hdev
);
2943 hclge_update_speed_duplex(hdev
);
2944 hclge_update_link_status(hdev
);
2945 hclge_update_led_status(hdev
);
2946 hclge_service_complete(hdev
);
2949 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2951 /* If our VFs are assigned we cannot shut down SR-IOV
2952 * without causing issues, so just leave the hardware
2953 * available but disabled
2955 if (pci_vfs_assigned(hdev
->pdev
)) {
2956 dev_warn(&hdev
->pdev
->dev
,
2957 "disabling driver while VFs are assigned\n");
2961 pci_disable_sriov(hdev
->pdev
);
2964 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2966 /* VF handle has no client */
2967 if (!handle
->client
)
2968 return container_of(handle
, struct hclge_vport
, nic
);
2969 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2970 return container_of(handle
, struct hclge_vport
, roce
);
2972 return container_of(handle
, struct hclge_vport
, nic
);
2975 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2976 struct hnae3_vector_info
*vector_info
)
2978 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2979 struct hnae3_vector_info
*vector
= vector_info
;
2980 struct hclge_dev
*hdev
= vport
->back
;
2984 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2986 for (j
= 0; j
< vector_num
; j
++) {
2987 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2988 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2989 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2990 vector
->io_addr
= hdev
->hw
.io_base
+
2991 HCLGE_VECTOR_REG_BASE
+
2992 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2994 HCLGE_VECTOR_VF_OFFSET
;
2995 hdev
->vector_status
[i
] = vport
->vport_id
;
2996 hdev
->vector_irq
[i
] = vector
->vector
;
3005 hdev
->num_msi_left
-= alloc
;
3006 hdev
->num_msi_used
+= alloc
;
3011 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
3015 for (i
= 0; i
< hdev
->num_msi
; i
++)
3016 if (vector
== hdev
->vector_irq
[i
])
3022 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
3024 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3025 struct hclge_dev
*hdev
= vport
->back
;
3028 vector_id
= hclge_get_vector_index(hdev
, vector
);
3029 if (vector_id
< 0) {
3030 dev_err(&hdev
->pdev
->dev
,
3031 "Get vector index fail. vector_id =%d\n", vector_id
);
3035 hclge_free_vector(hdev
, vector_id
);
3040 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
3042 return HCLGE_RSS_KEY_SIZE
;
3045 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
3047 return HCLGE_RSS_IND_TBL_SIZE
;
3050 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3051 const u8 hfunc
, const u8
*key
)
3053 struct hclge_rss_config_cmd
*req
;
3054 struct hclge_desc desc
;
3059 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3061 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3062 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3065 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3066 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3068 if (key_offset
== 2)
3070 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3072 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3074 memcpy(req
->hash_key
,
3075 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3077 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3079 dev_err(&hdev
->pdev
->dev
,
3080 "Configure RSS config fail, status = %d\n",
3088 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3090 struct hclge_rss_indirection_table_cmd
*req
;
3091 struct hclge_desc desc
;
3095 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3097 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3098 hclge_cmd_setup_basic_desc
3099 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3101 req
->start_table_index
=
3102 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3103 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3105 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3106 req
->rss_result
[j
] =
3107 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3109 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3111 dev_err(&hdev
->pdev
->dev
,
3112 "Configure rss indir table fail,status = %d\n",
3120 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3121 u16
*tc_size
, u16
*tc_offset
)
3123 struct hclge_rss_tc_mode_cmd
*req
;
3124 struct hclge_desc desc
;
3128 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3129 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3131 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3134 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3135 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3136 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3137 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3138 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3140 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3143 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3145 dev_err(&hdev
->pdev
->dev
,
3146 "Configure rss tc mode fail, status = %d\n", ret
);
3153 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3155 struct hclge_rss_input_tuple_cmd
*req
;
3156 struct hclge_desc desc
;
3159 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3161 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3163 /* Get the tuple cfg from pf */
3164 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3165 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3166 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3167 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3168 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3169 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3170 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3171 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3172 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3174 dev_err(&hdev
->pdev
->dev
,
3175 "Configure rss input fail, status = %d\n", ret
);
3182 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3185 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3188 /* Get hash algorithm */
3190 *hfunc
= vport
->rss_algo
;
3192 /* Get the RSS Key required by the user */
3194 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3196 /* Get indirect table */
3198 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3199 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3204 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3205 const u8
*key
, const u8 hfunc
)
3207 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3208 struct hclge_dev
*hdev
= vport
->back
;
3212 /* Set the RSS Hash Key if specififed by the user */
3215 if (hfunc
== ETH_RSS_HASH_TOP
||
3216 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3217 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3220 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3224 /* Update the shadow RSS key with user specified qids */
3225 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3226 vport
->rss_algo
= hash_algo
;
3229 /* Update the shadow RSS table with user specified qids */
3230 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3231 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3233 /* Update the hardware */
3234 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3237 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3239 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3241 if (nfc
->data
& RXH_L4_B_2_3
)
3242 hash_sets
|= HCLGE_D_PORT_BIT
;
3244 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3246 if (nfc
->data
& RXH_IP_SRC
)
3247 hash_sets
|= HCLGE_S_IP_BIT
;
3249 hash_sets
&= ~HCLGE_S_IP_BIT
;
3251 if (nfc
->data
& RXH_IP_DST
)
3252 hash_sets
|= HCLGE_D_IP_BIT
;
3254 hash_sets
&= ~HCLGE_D_IP_BIT
;
3256 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3257 hash_sets
|= HCLGE_V_TAG_BIT
;
3262 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3263 struct ethtool_rxnfc
*nfc
)
3265 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3266 struct hclge_dev
*hdev
= vport
->back
;
3267 struct hclge_rss_input_tuple_cmd
*req
;
3268 struct hclge_desc desc
;
3272 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3273 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3276 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3277 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3279 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3280 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3281 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3282 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3283 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3284 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3285 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3286 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3288 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3289 switch (nfc
->flow_type
) {
3291 req
->ipv4_tcp_en
= tuple_sets
;
3294 req
->ipv6_tcp_en
= tuple_sets
;
3297 req
->ipv4_udp_en
= tuple_sets
;
3300 req
->ipv6_udp_en
= tuple_sets
;
3303 req
->ipv4_sctp_en
= tuple_sets
;
3306 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3307 (nfc
->data
& RXH_L4_B_2_3
))
3310 req
->ipv6_sctp_en
= tuple_sets
;
3313 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3316 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3322 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3324 dev_err(&hdev
->pdev
->dev
,
3325 "Set rss tuple fail, status = %d\n", ret
);
3329 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3330 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3331 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3332 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3333 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3334 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3335 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3336 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3340 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3341 struct ethtool_rxnfc
*nfc
)
3343 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3348 switch (nfc
->flow_type
) {
3350 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3353 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3356 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3359 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3362 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3365 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3369 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3378 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3379 nfc
->data
|= RXH_L4_B_2_3
;
3380 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3381 nfc
->data
|= RXH_L4_B_0_1
;
3382 if (tuple_sets
& HCLGE_D_IP_BIT
)
3383 nfc
->data
|= RXH_IP_DST
;
3384 if (tuple_sets
& HCLGE_S_IP_BIT
)
3385 nfc
->data
|= RXH_IP_SRC
;
3390 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3392 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3393 struct hclge_dev
*hdev
= vport
->back
;
3395 return hdev
->rss_size_max
;
3398 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3400 struct hclge_vport
*vport
= hdev
->vport
;
3401 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3402 u16 rss_size
= vport
[0].alloc_rss_size
;
3403 u8
*key
= vport
[0].rss_hash_key
;
3404 u8 hfunc
= vport
[0].rss_algo
;
3405 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3406 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3407 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3411 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3415 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3419 ret
= hclge_set_rss_input_tuple(hdev
);
3423 /* Each TC have the same queue size, and tc_size set to hardware is
3424 * the log2 of roundup power of two of rss_size, the acutal queue
3425 * size is limited by indirection table.
3427 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3428 dev_err(&hdev
->pdev
->dev
,
3429 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3434 roundup_size
= roundup_pow_of_two(rss_size
);
3435 roundup_size
= ilog2(roundup_size
);
3437 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3440 if (!(hdev
->hw_tc_map
& BIT(i
)))
3444 tc_size
[i
] = roundup_size
;
3445 tc_offset
[i
] = rss_size
* i
;
3448 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3451 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3453 struct hclge_vport
*vport
= hdev
->vport
;
3456 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3457 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3458 vport
[j
].rss_indirection_tbl
[i
] =
3459 i
% vport
[j
].alloc_rss_size
;
3463 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3465 struct hclge_vport
*vport
= hdev
->vport
;
3468 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3469 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3470 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3471 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3472 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3473 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3474 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3475 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3476 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3477 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3478 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3479 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3480 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3481 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3482 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3483 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3484 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3486 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3488 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3491 hclge_rss_indir_init_cfg(hdev
);
3494 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3495 int vector_id
, bool en
,
3496 struct hnae3_ring_chain_node
*ring_chain
)
3498 struct hclge_dev
*hdev
= vport
->back
;
3499 struct hnae3_ring_chain_node
*node
;
3500 struct hclge_desc desc
;
3501 struct hclge_ctrl_vector_chain_cmd
*req
3502 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3503 enum hclge_cmd_status status
;
3504 enum hclge_opcode_type op
;
3505 u16 tqp_type_and_id
;
3508 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3509 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3510 req
->int_vector_id
= vector_id
;
3513 for (node
= ring_chain
; node
; node
= node
->next
) {
3514 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3515 hnae_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3517 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3518 hnae_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3519 HCLGE_TQP_ID_S
, node
->tqp_index
);
3520 hnae_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3522 hnae_get_field(node
->int_gl_idx
,
3523 HNAE3_RING_GL_IDX_M
,
3524 HNAE3_RING_GL_IDX_S
));
3525 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3526 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3527 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3528 req
->vfid
= vport
->vport_id
;
3530 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3532 dev_err(&hdev
->pdev
->dev
,
3533 "Map TQP fail, status is %d.\n",
3539 hclge_cmd_setup_basic_desc(&desc
,
3542 req
->int_vector_id
= vector_id
;
3547 req
->int_cause_num
= i
;
3548 req
->vfid
= vport
->vport_id
;
3549 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3551 dev_err(&hdev
->pdev
->dev
,
3552 "Map TQP fail, status is %d.\n", status
);
3560 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3562 struct hnae3_ring_chain_node
*ring_chain
)
3564 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3565 struct hclge_dev
*hdev
= vport
->back
;
3568 vector_id
= hclge_get_vector_index(hdev
, vector
);
3569 if (vector_id
< 0) {
3570 dev_err(&hdev
->pdev
->dev
,
3571 "Get vector index fail. vector_id =%d\n", vector_id
);
3575 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3578 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3580 struct hnae3_ring_chain_node
*ring_chain
)
3582 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3583 struct hclge_dev
*hdev
= vport
->back
;
3586 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3589 vector_id
= hclge_get_vector_index(hdev
, vector
);
3590 if (vector_id
< 0) {
3591 dev_err(&handle
->pdev
->dev
,
3592 "Get vector index fail. ret =%d\n", vector_id
);
3596 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3598 dev_err(&handle
->pdev
->dev
,
3599 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3606 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3607 struct hclge_promisc_param
*param
)
3609 struct hclge_promisc_cfg_cmd
*req
;
3610 struct hclge_desc desc
;
3613 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3615 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3616 req
->vf_id
= param
->vf_id
;
3617 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
3619 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3621 dev_err(&hdev
->pdev
->dev
,
3622 "Set promisc mode fail, status is %d.\n", ret
);
3628 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3629 bool en_mc
, bool en_bc
, int vport_id
)
3634 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3636 param
->enable
= HCLGE_PROMISC_EN_UC
;
3638 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3640 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3641 param
->vf_id
= vport_id
;
3644 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
3646 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3647 struct hclge_dev
*hdev
= vport
->back
;
3648 struct hclge_promisc_param param
;
3650 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
3651 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3654 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3656 struct hclge_desc desc
;
3657 struct hclge_config_mac_mode_cmd
*req
=
3658 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3662 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3663 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3664 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3665 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3666 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3667 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3668 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3669 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3670 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3671 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3672 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3673 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3674 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3675 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3676 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3677 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3679 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3681 dev_err(&hdev
->pdev
->dev
,
3682 "mac enable fail, ret =%d.\n", ret
);
3685 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3686 enum hnae3_loop loop_mode
, bool en
)
3688 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3689 struct hclge_config_mac_mode_cmd
*req
;
3690 struct hclge_dev
*hdev
= vport
->back
;
3691 struct hclge_desc desc
;
3695 switch (loop_mode
) {
3696 case HNAE3_MAC_INTER_LOOP_MAC
:
3697 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3698 /* 1 Read out the MAC mode config at first */
3699 hclge_cmd_setup_basic_desc(&desc
,
3700 HCLGE_OPC_CONFIG_MAC_MODE
,
3702 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3704 dev_err(&hdev
->pdev
->dev
,
3705 "mac loopback get fail, ret =%d.\n",
3710 /* 2 Then setup the loopback flag */
3711 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3713 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 1);
3715 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3717 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3719 /* 3 Config mac work mode with loopback flag
3720 * and its original configure parameters
3722 hclge_cmd_reuse_desc(&desc
, false);
3723 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3725 dev_err(&hdev
->pdev
->dev
,
3726 "mac loopback set fail, ret =%d.\n", ret
);
3730 dev_err(&hdev
->pdev
->dev
,
3731 "loop_mode %d is not supported\n", loop_mode
);
3738 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3739 int stream_id
, bool enable
)
3741 struct hclge_desc desc
;
3742 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3743 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3746 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3747 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3748 req
->stream_id
= cpu_to_le16(stream_id
);
3749 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3751 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3753 dev_err(&hdev
->pdev
->dev
,
3754 "Tqp enable fail, status =%d.\n", ret
);
3758 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3760 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3761 struct hnae3_queue
*queue
;
3762 struct hclge_tqp
*tqp
;
3765 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3766 queue
= handle
->kinfo
.tqp
[i
];
3767 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3768 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3772 static int hclge_ae_start(struct hnae3_handle
*handle
)
3774 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3775 struct hclge_dev
*hdev
= vport
->back
;
3778 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3779 hclge_tqp_enable(hdev
, i
, 0, true);
3782 hclge_cfg_mac_mode(hdev
, true);
3783 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3784 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3786 /* reset tqp stats */
3787 hclge_reset_tqp_stats(handle
);
3789 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3792 ret
= hclge_mac_start_phy(hdev
);
3799 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3801 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3802 struct hclge_dev
*hdev
= vport
->back
;
3805 del_timer_sync(&hdev
->service_timer
);
3806 cancel_work_sync(&hdev
->service_task
);
3808 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3811 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3812 hclge_tqp_enable(hdev
, i
, 0, false);
3815 hclge_cfg_mac_mode(hdev
, false);
3817 hclge_mac_stop_phy(hdev
);
3819 /* reset tqp stats */
3820 hclge_reset_tqp_stats(handle
);
3821 hclge_update_link_status(hdev
);
3824 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3825 u16 cmdq_resp
, u8 resp_code
,
3826 enum hclge_mac_vlan_tbl_opcode op
)
3828 struct hclge_dev
*hdev
= vport
->back
;
3829 int return_status
= -EIO
;
3832 dev_err(&hdev
->pdev
->dev
,
3833 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3838 if (op
== HCLGE_MAC_VLAN_ADD
) {
3839 if ((!resp_code
) || (resp_code
== 1)) {
3841 } else if (resp_code
== 2) {
3842 return_status
= -ENOSPC
;
3843 dev_err(&hdev
->pdev
->dev
,
3844 "add mac addr failed for uc_overflow.\n");
3845 } else if (resp_code
== 3) {
3846 return_status
= -ENOSPC
;
3847 dev_err(&hdev
->pdev
->dev
,
3848 "add mac addr failed for mc_overflow.\n");
3850 dev_err(&hdev
->pdev
->dev
,
3851 "add mac addr failed for undefined, code=%d.\n",
3854 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3857 } else if (resp_code
== 1) {
3858 return_status
= -ENOENT
;
3859 dev_dbg(&hdev
->pdev
->dev
,
3860 "remove mac addr failed for miss.\n");
3862 dev_err(&hdev
->pdev
->dev
,
3863 "remove mac addr failed for undefined, code=%d.\n",
3866 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3869 } else if (resp_code
== 1) {
3870 return_status
= -ENOENT
;
3871 dev_dbg(&hdev
->pdev
->dev
,
3872 "lookup mac addr failed for miss.\n");
3874 dev_err(&hdev
->pdev
->dev
,
3875 "lookup mac addr failed for undefined, code=%d.\n",
3879 return_status
= -EINVAL
;
3880 dev_err(&hdev
->pdev
->dev
,
3881 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3885 return return_status
;
3888 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3893 if (vfid
> 255 || vfid
< 0)
3896 if (vfid
>= 0 && vfid
<= 191) {
3897 word_num
= vfid
/ 32;
3898 bit_num
= vfid
% 32;
3900 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3902 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3904 word_num
= (vfid
- 192) / 32;
3905 bit_num
= vfid
% 32;
3907 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3909 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3915 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3917 #define HCLGE_DESC_NUMBER 3
3918 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3921 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3922 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3923 if (desc
[i
].data
[j
])
3929 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3932 const unsigned char *mac_addr
= addr
;
3933 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3934 (mac_addr
[0]) | (mac_addr
[1] << 8);
3935 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3937 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3938 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3941 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3944 u16 high_val
= addr
[1] | (addr
[0] << 8);
3945 struct hclge_dev
*hdev
= vport
->back
;
3946 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3947 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3952 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3953 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3956 struct hclge_mta_filter_mode_cmd
*req
;
3957 struct hclge_desc desc
;
3960 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3961 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3963 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3965 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3966 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3968 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3970 dev_err(&hdev
->pdev
->dev
,
3971 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3979 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3983 struct hclge_cfg_func_mta_filter_cmd
*req
;
3984 struct hclge_desc desc
;
3987 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3988 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3990 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3992 req
->function_id
= func_id
;
3994 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3996 dev_err(&hdev
->pdev
->dev
,
3997 "Config func_id enable failed for cmd_send, ret =%d.\n",
4005 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
4009 struct hclge_dev
*hdev
= vport
->back
;
4010 struct hclge_cfg_func_mta_item_cmd
*req
;
4011 struct hclge_desc desc
;
4015 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
4016 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
4017 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
4019 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
4020 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
4021 req
->item_idx
= cpu_to_le16(item_idx
);
4023 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4025 dev_err(&hdev
->pdev
->dev
,
4026 "Config mta table item failed for cmd_send, ret =%d.\n",
4034 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4035 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4037 struct hclge_dev
*hdev
= vport
->back
;
4038 struct hclge_desc desc
;
4043 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4045 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4047 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4049 dev_err(&hdev
->pdev
->dev
,
4050 "del mac addr failed for cmd_send, ret =%d.\n",
4054 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4055 retval
= le16_to_cpu(desc
.retval
);
4057 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4058 HCLGE_MAC_VLAN_REMOVE
);
4061 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4062 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4063 struct hclge_desc
*desc
,
4066 struct hclge_dev
*hdev
= vport
->back
;
4071 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4073 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4074 memcpy(desc
[0].data
,
4076 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4077 hclge_cmd_setup_basic_desc(&desc
[1],
4078 HCLGE_OPC_MAC_VLAN_ADD
,
4080 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4081 hclge_cmd_setup_basic_desc(&desc
[2],
4082 HCLGE_OPC_MAC_VLAN_ADD
,
4084 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4086 memcpy(desc
[0].data
,
4088 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4089 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4092 dev_err(&hdev
->pdev
->dev
,
4093 "lookup mac addr failed for cmd_send, ret =%d.\n",
4097 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4098 retval
= le16_to_cpu(desc
[0].retval
);
4100 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4101 HCLGE_MAC_VLAN_LKUP
);
4104 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4105 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4106 struct hclge_desc
*mc_desc
)
4108 struct hclge_dev
*hdev
= vport
->back
;
4115 struct hclge_desc desc
;
4117 hclge_cmd_setup_basic_desc(&desc
,
4118 HCLGE_OPC_MAC_VLAN_ADD
,
4120 memcpy(desc
.data
, req
,
4121 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4122 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4123 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4124 retval
= le16_to_cpu(desc
.retval
);
4126 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4128 HCLGE_MAC_VLAN_ADD
);
4130 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4131 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4132 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4133 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4134 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4135 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4136 memcpy(mc_desc
[0].data
, req
,
4137 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4138 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4139 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4140 retval
= le16_to_cpu(mc_desc
[0].retval
);
4142 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4144 HCLGE_MAC_VLAN_ADD
);
4148 dev_err(&hdev
->pdev
->dev
,
4149 "add mac addr failed for cmd_send, ret =%d.\n",
4157 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4158 const unsigned char *addr
)
4160 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4162 return hclge_add_uc_addr_common(vport
, addr
);
4165 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4166 const unsigned char *addr
)
4168 struct hclge_dev
*hdev
= vport
->back
;
4169 struct hclge_mac_vlan_tbl_entry_cmd req
;
4170 struct hclge_desc desc
;
4171 u16 egress_port
= 0;
4174 /* mac addr check */
4175 if (is_zero_ether_addr(addr
) ||
4176 is_broadcast_ether_addr(addr
) ||
4177 is_multicast_ether_addr(addr
)) {
4178 dev_err(&hdev
->pdev
->dev
,
4179 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4181 is_zero_ether_addr(addr
),
4182 is_broadcast_ether_addr(addr
),
4183 is_multicast_ether_addr(addr
));
4187 memset(&req
, 0, sizeof(req
));
4188 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4189 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4190 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
4191 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4193 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_SW_EN_B
, 0);
4194 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_TYPE_B
, 0);
4195 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4196 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4197 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_PFID_M
,
4198 HCLGE_MAC_EPORT_PFID_S
, 0);
4200 req
.egress_port
= cpu_to_le16(egress_port
);
4202 hclge_prepare_mac_addr(&req
, addr
);
4204 /* Lookup the mac address in the mac_vlan table, and add
4205 * it if the entry is inexistent. Repeated unicast entry
4206 * is not allowed in the mac vlan table.
4208 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4210 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4212 /* check if we just hit the duplicate */
4216 dev_err(&hdev
->pdev
->dev
,
4217 "PF failed to add unicast entry(%pM) in the MAC table\n",
4223 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4224 const unsigned char *addr
)
4226 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4228 return hclge_rm_uc_addr_common(vport
, addr
);
4231 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4232 const unsigned char *addr
)
4234 struct hclge_dev
*hdev
= vport
->back
;
4235 struct hclge_mac_vlan_tbl_entry_cmd req
;
4238 /* mac addr check */
4239 if (is_zero_ether_addr(addr
) ||
4240 is_broadcast_ether_addr(addr
) ||
4241 is_multicast_ether_addr(addr
)) {
4242 dev_dbg(&hdev
->pdev
->dev
,
4243 "Remove mac err! invalid mac:%pM.\n",
4248 memset(&req
, 0, sizeof(req
));
4249 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4250 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4251 hclge_prepare_mac_addr(&req
, addr
);
4252 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4257 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4258 const unsigned char *addr
)
4260 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4262 return hclge_add_mc_addr_common(vport
, addr
);
4265 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4266 const unsigned char *addr
)
4268 struct hclge_dev
*hdev
= vport
->back
;
4269 struct hclge_mac_vlan_tbl_entry_cmd req
;
4270 struct hclge_desc desc
[3];
4274 /* mac addr check */
4275 if (!is_multicast_ether_addr(addr
)) {
4276 dev_err(&hdev
->pdev
->dev
,
4277 "Add mc mac err! invalid mac:%pM.\n",
4281 memset(&req
, 0, sizeof(req
));
4282 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4283 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4284 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4285 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4286 hclge_prepare_mac_addr(&req
, addr
);
4287 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4289 /* This mac addr exist, update VFID for it */
4290 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4291 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4293 /* This mac addr do not exist, add new entry for it */
4294 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4295 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4296 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4297 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4298 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4301 /* Set MTA table for this MAC address */
4302 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4303 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4308 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4309 const unsigned char *addr
)
4311 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4313 return hclge_rm_mc_addr_common(vport
, addr
);
4316 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4317 const unsigned char *addr
)
4319 struct hclge_dev
*hdev
= vport
->back
;
4320 struct hclge_mac_vlan_tbl_entry_cmd req
;
4321 enum hclge_cmd_status status
;
4322 struct hclge_desc desc
[3];
4325 /* mac addr check */
4326 if (!is_multicast_ether_addr(addr
)) {
4327 dev_dbg(&hdev
->pdev
->dev
,
4328 "Remove mc mac err! invalid mac:%pM.\n",
4333 memset(&req
, 0, sizeof(req
));
4334 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4335 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4336 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4337 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4338 hclge_prepare_mac_addr(&req
, addr
);
4339 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4341 /* This mac addr exist, remove this handle's VFID for it */
4342 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4344 if (hclge_is_all_function_id_zero(desc
))
4345 /* All the vfid is zero, so need to delete this entry */
4346 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4348 /* Not all the vfid is zero, update the vfid */
4349 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4352 /* This mac addr do not exist, can't delete it */
4353 dev_err(&hdev
->pdev
->dev
,
4354 "Rm multicast mac addr failed, ret = %d.\n",
4359 /* Set MTB table for this MAC address */
4360 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4361 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
4366 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4367 u16 cmdq_resp
, u8 resp_code
)
4369 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4370 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4371 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4372 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4377 dev_err(&hdev
->pdev
->dev
,
4378 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4383 switch (resp_code
) {
4384 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4385 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4388 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4389 dev_err(&hdev
->pdev
->dev
,
4390 "add mac ethertype failed for manager table overflow.\n");
4391 return_status
= -EIO
;
4393 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4394 dev_err(&hdev
->pdev
->dev
,
4395 "add mac ethertype failed for key conflict.\n");
4396 return_status
= -EIO
;
4399 dev_err(&hdev
->pdev
->dev
,
4400 "add mac ethertype failed for undefined, code=%d.\n",
4402 return_status
= -EIO
;
4405 return return_status
;
4408 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4409 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4411 struct hclge_desc desc
;
4416 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4417 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4419 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4421 dev_err(&hdev
->pdev
->dev
,
4422 "add mac ethertype failed for cmd_send, ret =%d.\n",
4427 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4428 retval
= le16_to_cpu(desc
.retval
);
4430 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4433 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4438 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4439 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4441 dev_err(&hdev
->pdev
->dev
,
4442 "add mac ethertype failed, ret =%d.\n",
4451 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4453 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4454 struct hclge_dev
*hdev
= vport
->back
;
4456 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4459 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4462 const unsigned char *new_addr
= (const unsigned char *)p
;
4463 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4464 struct hclge_dev
*hdev
= vport
->back
;
4467 /* mac addr check */
4468 if (is_zero_ether_addr(new_addr
) ||
4469 is_broadcast_ether_addr(new_addr
) ||
4470 is_multicast_ether_addr(new_addr
)) {
4471 dev_err(&hdev
->pdev
->dev
,
4472 "Change uc mac err! invalid mac:%p.\n",
4477 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4478 dev_warn(&hdev
->pdev
->dev
,
4479 "remove old uc mac address fail.\n");
4481 ret
= hclge_add_uc_addr(handle
, new_addr
);
4483 dev_err(&hdev
->pdev
->dev
,
4484 "add uc mac address fail, ret =%d.\n",
4488 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4489 dev_err(&hdev
->pdev
->dev
,
4490 "restore uc mac address fail.\n");
4495 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4497 dev_err(&hdev
->pdev
->dev
,
4498 "configure mac pause address fail, ret =%d.\n",
4503 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4508 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4511 struct hclge_vlan_filter_ctrl_cmd
*req
;
4512 struct hclge_desc desc
;
4515 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4517 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4518 req
->vlan_type
= vlan_type
;
4519 req
->vlan_fe
= filter_en
;
4521 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4523 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4531 #define HCLGE_FILTER_TYPE_VF 0
4532 #define HCLGE_FILTER_TYPE_PORT 1
4534 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4536 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4537 struct hclge_dev
*hdev
= vport
->back
;
4539 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4542 static int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4543 bool is_kill
, u16 vlan
, u8 qos
,
4546 #define HCLGE_MAX_VF_BYTES 16
4547 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4548 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4549 struct hclge_desc desc
[2];
4554 hclge_cmd_setup_basic_desc(&desc
[0],
4555 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4556 hclge_cmd_setup_basic_desc(&desc
[1],
4557 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4559 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4561 vf_byte_off
= vfid
/ 8;
4562 vf_byte_val
= 1 << (vfid
% 8);
4564 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4565 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4567 req0
->vlan_id
= cpu_to_le16(vlan
);
4568 req0
->vlan_cfg
= is_kill
;
4570 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4571 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4573 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4575 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4577 dev_err(&hdev
->pdev
->dev
,
4578 "Send vf vlan command fail, ret =%d.\n",
4584 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4587 dev_err(&hdev
->pdev
->dev
,
4588 "Add vf vlan filter fail, ret =%d.\n",
4591 if (!req0
->resp_code
)
4594 dev_err(&hdev
->pdev
->dev
,
4595 "Kill vf vlan filter fail, ret =%d.\n",
4602 static int hclge_set_port_vlan_filter(struct hclge_dev
*hdev
, __be16 proto
,
4603 u16 vlan_id
, bool is_kill
)
4605 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4606 struct hclge_desc desc
;
4607 u8 vlan_offset_byte_val
;
4608 u8 vlan_offset_byte
;
4612 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4614 vlan_offset_160
= vlan_id
/ 160;
4615 vlan_offset_byte
= (vlan_id
% 160) / 8;
4616 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4618 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4619 req
->vlan_offset
= vlan_offset_160
;
4620 req
->vlan_cfg
= is_kill
;
4621 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4623 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4625 dev_err(&hdev
->pdev
->dev
,
4626 "port vlan command, send fail, ret =%d.\n", ret
);
4630 static int hclge_set_vlan_filter_hw(struct hclge_dev
*hdev
, __be16 proto
,
4631 u16 vport_id
, u16 vlan_id
, u8 qos
,
4634 u16 vport_idx
, vport_num
= 0;
4637 ret
= hclge_set_vf_vlan_common(hdev
, vport_id
, is_kill
, vlan_id
,
4640 dev_err(&hdev
->pdev
->dev
,
4641 "Set %d vport vlan filter config fail, ret =%d.\n",
4646 /* vlan 0 may be added twice when 8021q module is enabled */
4647 if (!is_kill
&& !vlan_id
&&
4648 test_bit(vport_id
, hdev
->vlan_table
[vlan_id
]))
4651 if (!is_kill
&& test_and_set_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4652 dev_err(&hdev
->pdev
->dev
,
4653 "Add port vlan failed, vport %d is already in vlan %d\n",
4659 !test_and_clear_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4660 dev_err(&hdev
->pdev
->dev
,
4661 "Delete port vlan failed, vport %d is not in vlan %d\n",
4666 for_each_set_bit(vport_idx
, hdev
->vlan_table
[vlan_id
], VLAN_N_VID
)
4669 if ((is_kill
&& vport_num
== 0) || (!is_kill
&& vport_num
== 1))
4670 ret
= hclge_set_port_vlan_filter(hdev
, proto
, vlan_id
,
4676 int hclge_set_vlan_filter(struct hnae3_handle
*handle
, __be16 proto
,
4677 u16 vlan_id
, bool is_kill
)
4679 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4680 struct hclge_dev
*hdev
= vport
->back
;
4682 return hclge_set_vlan_filter_hw(hdev
, proto
, vport
->vport_id
, vlan_id
,
4686 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4687 u16 vlan
, u8 qos
, __be16 proto
)
4689 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4690 struct hclge_dev
*hdev
= vport
->back
;
4692 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4694 if (proto
!= htons(ETH_P_8021Q
))
4695 return -EPROTONOSUPPORT
;
4697 return hclge_set_vlan_filter_hw(hdev
, proto
, vfid
, vlan
, qos
, false);
4700 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4702 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4703 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4704 struct hclge_dev
*hdev
= vport
->back
;
4705 struct hclge_desc desc
;
4708 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4710 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4711 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4712 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4713 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG_B
,
4714 vcfg
->accept_tag
? 1 : 0);
4715 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG_B
,
4716 vcfg
->accept_untag
? 1 : 0);
4717 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4718 vcfg
->insert_tag1_en
? 1 : 0);
4719 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4720 vcfg
->insert_tag2_en
? 1 : 0);
4721 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4723 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4724 req
->vf_bitmap
[req
->vf_offset
] =
4725 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4727 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4729 dev_err(&hdev
->pdev
->dev
,
4730 "Send port txvlan cfg command fail, ret =%d\n",
4736 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4738 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4739 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4740 struct hclge_dev
*hdev
= vport
->back
;
4741 struct hclge_desc desc
;
4744 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4746 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4747 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4748 vcfg
->strip_tag1_en
? 1 : 0);
4749 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4750 vcfg
->strip_tag2_en
? 1 : 0);
4751 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4752 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4753 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4754 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4756 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4757 req
->vf_bitmap
[req
->vf_offset
] =
4758 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4760 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4762 dev_err(&hdev
->pdev
->dev
,
4763 "Send port rxvlan cfg command fail, ret =%d\n",
4769 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4771 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4772 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4773 struct hclge_desc desc
;
4776 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4777 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4778 rx_req
->ot_fst_vlan_type
=
4779 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4780 rx_req
->ot_sec_vlan_type
=
4781 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4782 rx_req
->in_fst_vlan_type
=
4783 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4784 rx_req
->in_sec_vlan_type
=
4785 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4787 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4789 dev_err(&hdev
->pdev
->dev
,
4790 "Send rxvlan protocol type command fail, ret =%d\n",
4795 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4797 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4798 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4799 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4801 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4803 dev_err(&hdev
->pdev
->dev
,
4804 "Send txvlan protocol type command fail, ret =%d\n",
4810 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4812 #define HCLGE_DEF_VLAN_TYPE 0x8100
4814 struct hnae3_handle
*handle
;
4815 struct hclge_vport
*vport
;
4819 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4823 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4827 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4828 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4829 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4830 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4831 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4832 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4834 ret
= hclge_set_vlan_protocol_type(hdev
);
4838 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4839 vport
= &hdev
->vport
[i
];
4840 vport
->txvlan_cfg
.accept_tag
= true;
4841 vport
->txvlan_cfg
.accept_untag
= true;
4842 vport
->txvlan_cfg
.insert_tag1_en
= false;
4843 vport
->txvlan_cfg
.insert_tag2_en
= false;
4844 vport
->txvlan_cfg
.default_tag1
= 0;
4845 vport
->txvlan_cfg
.default_tag2
= 0;
4847 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4851 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4852 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4853 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4854 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4856 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4861 handle
= &hdev
->vport
[0].nic
;
4862 return hclge_set_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4865 int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4867 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4869 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4870 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4871 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4872 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4874 return hclge_set_vlan_rx_offload_cfg(vport
);
4877 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
4879 struct hclge_config_max_frm_size_cmd
*req
;
4880 struct hclge_desc desc
;
4884 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
4886 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
4887 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
4890 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
4892 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4894 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4895 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
4897 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4899 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4903 hdev
->mps
= max_frm_size
;
4908 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4910 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4911 struct hclge_dev
*hdev
= vport
->back
;
4914 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
4916 dev_err(&hdev
->pdev
->dev
,
4917 "Change mtu fail, ret =%d\n", ret
);
4921 ret
= hclge_buffer_alloc(hdev
);
4923 dev_err(&hdev
->pdev
->dev
,
4924 "Allocate buffer fail, ret =%d\n", ret
);
4929 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
4932 struct hclge_reset_tqp_queue_cmd
*req
;
4933 struct hclge_desc desc
;
4936 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
4938 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4939 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4940 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
4942 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4944 dev_err(&hdev
->pdev
->dev
,
4945 "Send tqp reset cmd error, status =%d\n", ret
);
4952 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
4954 struct hclge_reset_tqp_queue_cmd
*req
;
4955 struct hclge_desc desc
;
4958 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
4960 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4961 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4963 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4965 dev_err(&hdev
->pdev
->dev
,
4966 "Get reset status error, status =%d\n", ret
);
4970 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
4973 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
4976 struct hnae3_queue
*queue
;
4977 struct hclge_tqp
*tqp
;
4979 queue
= handle
->kinfo
.tqp
[queue_id
];
4980 tqp
= container_of(queue
, struct hclge_tqp
, q
);
4985 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
4987 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4988 struct hclge_dev
*hdev
= vport
->back
;
4989 int reset_try_times
= 0;
4994 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
4997 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
4999 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
5001 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
5005 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5007 dev_warn(&hdev
->pdev
->dev
,
5008 "Send reset tqp cmd fail, ret = %d\n", ret
);
5012 reset_try_times
= 0;
5013 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5014 /* Wait for tqp hw reset */
5016 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5021 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5022 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5026 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5028 dev_warn(&hdev
->pdev
->dev
,
5029 "Deassert the soft reset fail, ret = %d\n", ret
);
5034 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
5036 struct hclge_dev
*hdev
= vport
->back
;
5037 int reset_try_times
= 0;
5042 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5044 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5046 dev_warn(&hdev
->pdev
->dev
,
5047 "Send reset tqp cmd fail, ret = %d\n", ret
);
5051 reset_try_times
= 0;
5052 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5053 /* Wait for tqp hw reset */
5055 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5060 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5061 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5065 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5067 dev_warn(&hdev
->pdev
->dev
,
5068 "Deassert the soft reset fail, ret = %d\n", ret
);
5071 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5073 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5074 struct hclge_dev
*hdev
= vport
->back
;
5076 return hdev
->fw_version
;
5079 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5082 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5083 struct hclge_dev
*hdev
= vport
->back
;
5084 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5089 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5090 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5093 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5095 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5100 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5103 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5106 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5109 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5114 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5115 else if (rx_en
&& !tx_en
)
5116 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5117 else if (!rx_en
&& tx_en
)
5118 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5120 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5122 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5125 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5127 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5132 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5137 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5139 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5140 u16 remote_advertising
= 0;
5141 u16 local_advertising
= 0;
5142 u32 rx_pause
, tx_pause
;
5145 if (!phydev
->link
|| !phydev
->autoneg
)
5148 if (phydev
->advertising
& ADVERTISED_Pause
)
5149 local_advertising
= ADVERTISE_PAUSE_CAP
;
5151 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5152 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5155 remote_advertising
= LPA_PAUSE_CAP
;
5157 if (phydev
->asym_pause
)
5158 remote_advertising
|= LPA_PAUSE_ASYM
;
5160 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5161 remote_advertising
);
5162 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5163 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5165 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5170 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5173 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5174 u32
*rx_en
, u32
*tx_en
)
5176 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5177 struct hclge_dev
*hdev
= vport
->back
;
5179 *auto_neg
= hclge_get_autoneg(handle
);
5181 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5187 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5190 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5193 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5202 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5203 u32 rx_en
, u32 tx_en
)
5205 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5206 struct hclge_dev
*hdev
= vport
->back
;
5207 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5210 fc_autoneg
= hclge_get_autoneg(handle
);
5211 if (auto_neg
!= fc_autoneg
) {
5212 dev_info(&hdev
->pdev
->dev
,
5213 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5217 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5218 dev_info(&hdev
->pdev
->dev
,
5219 "Priority flow control enabled. Cannot set link flow control.\n");
5223 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5226 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5228 /* Only support flow control negotiation for netdev with
5229 * phy attached for now.
5234 return phy_start_aneg(phydev
);
5237 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5238 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5240 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5241 struct hclge_dev
*hdev
= vport
->back
;
5244 *speed
= hdev
->hw
.mac
.speed
;
5246 *duplex
= hdev
->hw
.mac
.duplex
;
5248 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5251 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5253 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5254 struct hclge_dev
*hdev
= vport
->back
;
5257 *media_type
= hdev
->hw
.mac
.media_type
;
5260 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5261 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5263 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5264 struct hclge_dev
*hdev
= vport
->back
;
5265 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5266 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5269 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5270 *tp_mdix
= ETH_TP_MDI_INVALID
;
5274 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5276 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5277 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5278 HCLGE_PHY_MDIX_CTRL_S
);
5280 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5281 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5282 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5284 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5286 switch (mdix_ctrl
) {
5288 *tp_mdix_ctrl
= ETH_TP_MDI
;
5291 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5294 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5297 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5302 *tp_mdix
= ETH_TP_MDI_INVALID
;
5304 *tp_mdix
= ETH_TP_MDI_X
;
5306 *tp_mdix
= ETH_TP_MDI
;
5309 static int hclge_init_client_instance(struct hnae3_client
*client
,
5310 struct hnae3_ae_dev
*ae_dev
)
5312 struct hclge_dev
*hdev
= ae_dev
->priv
;
5313 struct hclge_vport
*vport
;
5316 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5317 vport
= &hdev
->vport
[i
];
5319 switch (client
->type
) {
5320 case HNAE3_CLIENT_KNIC
:
5322 hdev
->nic_client
= client
;
5323 vport
->nic
.client
= client
;
5324 ret
= client
->ops
->init_instance(&vport
->nic
);
5328 if (hdev
->roce_client
&&
5329 hnae3_dev_roce_supported(hdev
)) {
5330 struct hnae3_client
*rc
= hdev
->roce_client
;
5332 ret
= hclge_init_roce_base_info(vport
);
5336 ret
= rc
->ops
->init_instance(&vport
->roce
);
5342 case HNAE3_CLIENT_UNIC
:
5343 hdev
->nic_client
= client
;
5344 vport
->nic
.client
= client
;
5346 ret
= client
->ops
->init_instance(&vport
->nic
);
5351 case HNAE3_CLIENT_ROCE
:
5352 if (hnae3_dev_roce_supported(hdev
)) {
5353 hdev
->roce_client
= client
;
5354 vport
->roce
.client
= client
;
5357 if (hdev
->roce_client
&& hdev
->nic_client
) {
5358 ret
= hclge_init_roce_base_info(vport
);
5362 ret
= client
->ops
->init_instance(&vport
->roce
);
5374 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5375 struct hnae3_ae_dev
*ae_dev
)
5377 struct hclge_dev
*hdev
= ae_dev
->priv
;
5378 struct hclge_vport
*vport
;
5381 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5382 vport
= &hdev
->vport
[i
];
5383 if (hdev
->roce_client
) {
5384 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5386 hdev
->roce_client
= NULL
;
5387 vport
->roce
.client
= NULL
;
5389 if (client
->type
== HNAE3_CLIENT_ROCE
)
5391 if (client
->ops
->uninit_instance
) {
5392 client
->ops
->uninit_instance(&vport
->nic
, 0);
5393 hdev
->nic_client
= NULL
;
5394 vport
->nic
.client
= NULL
;
5399 static int hclge_pci_init(struct hclge_dev
*hdev
)
5401 struct pci_dev
*pdev
= hdev
->pdev
;
5402 struct hclge_hw
*hw
;
5405 ret
= pci_enable_device(pdev
);
5407 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5408 goto err_no_drvdata
;
5411 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5413 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5416 "can't set consistent PCI DMA");
5417 goto err_disable_device
;
5419 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5422 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5424 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5425 goto err_disable_device
;
5428 pci_set_master(pdev
);
5431 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5433 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5435 goto err_clr_master
;
5438 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5442 pci_clear_master(pdev
);
5443 pci_release_regions(pdev
);
5445 pci_disable_device(pdev
);
5447 pci_set_drvdata(pdev
, NULL
);
5452 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5454 struct pci_dev
*pdev
= hdev
->pdev
;
5456 pci_free_irq_vectors(pdev
);
5457 pci_clear_master(pdev
);
5458 pci_release_mem_regions(pdev
);
5459 pci_disable_device(pdev
);
5462 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5464 struct pci_dev
*pdev
= ae_dev
->pdev
;
5465 struct hclge_dev
*hdev
;
5468 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5475 hdev
->ae_dev
= ae_dev
;
5476 hdev
->reset_type
= HNAE3_NONE_RESET
;
5477 hdev
->reset_request
= 0;
5478 hdev
->reset_pending
= 0;
5479 ae_dev
->priv
= hdev
;
5481 ret
= hclge_pci_init(hdev
);
5483 dev_err(&pdev
->dev
, "PCI init failed\n");
5487 /* Firmware command queue initialize */
5488 ret
= hclge_cmd_queue_init(hdev
);
5490 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5491 goto err_pci_uninit
;
5494 /* Firmware command initialize */
5495 ret
= hclge_cmd_init(hdev
);
5497 goto err_cmd_uninit
;
5499 ret
= hclge_get_cap(hdev
);
5501 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5503 goto err_cmd_uninit
;
5506 ret
= hclge_configure(hdev
);
5508 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5509 goto err_cmd_uninit
;
5512 ret
= hclge_init_msi(hdev
);
5514 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5515 goto err_cmd_uninit
;
5518 ret
= hclge_misc_irq_init(hdev
);
5521 "Misc IRQ(vector0) init error, ret = %d.\n",
5523 goto err_msi_uninit
;
5526 ret
= hclge_alloc_tqps(hdev
);
5528 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5529 goto err_msi_irq_uninit
;
5532 ret
= hclge_alloc_vport(hdev
);
5534 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5535 goto err_msi_irq_uninit
;
5538 ret
= hclge_map_tqp(hdev
);
5540 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5541 goto err_sriov_disable
;
5544 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5545 ret
= hclge_mac_mdio_config(hdev
);
5547 dev_err(&hdev
->pdev
->dev
,
5548 "mdio config fail ret=%d\n", ret
);
5549 goto err_sriov_disable
;
5553 ret
= hclge_mac_init(hdev
);
5555 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5556 goto err_mdiobus_unreg
;
5559 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5561 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5562 goto err_mdiobus_unreg
;
5565 ret
= hclge_init_vlan_config(hdev
);
5567 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5568 goto err_mdiobus_unreg
;
5571 ret
= hclge_tm_schd_init(hdev
);
5573 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5574 goto err_mdiobus_unreg
;
5577 hclge_rss_init_cfg(hdev
);
5578 ret
= hclge_rss_init_hw(hdev
);
5580 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5581 goto err_mdiobus_unreg
;
5584 ret
= init_mgr_tbl(hdev
);
5586 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5587 goto err_mdiobus_unreg
;
5590 hclge_dcb_ops_set(hdev
);
5592 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5593 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5594 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5595 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5597 /* Enable MISC vector(vector0) */
5598 hclge_enable_vector(&hdev
->misc_vector
, true);
5600 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5601 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5602 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5603 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5604 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5605 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5607 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5611 if (hdev
->hw
.mac
.phydev
)
5612 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5614 if (IS_ENABLED(CONFIG_PCI_IOV
))
5615 hclge_disable_sriov(hdev
);
5617 hclge_misc_irq_uninit(hdev
);
5619 pci_free_irq_vectors(pdev
);
5621 hclge_destroy_cmd_queue(&hdev
->hw
);
5623 pci_clear_master(pdev
);
5624 pci_release_regions(pdev
);
5625 pci_disable_device(pdev
);
5626 pci_set_drvdata(pdev
, NULL
);
5631 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5633 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5636 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5638 struct hclge_dev
*hdev
= ae_dev
->priv
;
5639 struct pci_dev
*pdev
= ae_dev
->pdev
;
5642 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5644 hclge_stats_clear(hdev
);
5645 memset(hdev
->vlan_table
, 0, sizeof(hdev
->vlan_table
));
5647 ret
= hclge_cmd_init(hdev
);
5649 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5653 ret
= hclge_get_cap(hdev
);
5655 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5660 ret
= hclge_configure(hdev
);
5662 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5666 ret
= hclge_map_tqp(hdev
);
5668 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5672 ret
= hclge_mac_init(hdev
);
5674 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5678 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5680 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5684 ret
= hclge_init_vlan_config(hdev
);
5686 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5690 ret
= hclge_tm_init_hw(hdev
);
5692 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5696 ret
= hclge_rss_init_hw(hdev
);
5698 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5702 /* Enable MISC vector(vector0) */
5703 hclge_enable_vector(&hdev
->misc_vector
, true);
5705 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5711 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5713 struct hclge_dev
*hdev
= ae_dev
->priv
;
5714 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5716 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5718 if (IS_ENABLED(CONFIG_PCI_IOV
))
5719 hclge_disable_sriov(hdev
);
5721 if (hdev
->service_timer
.function
)
5722 del_timer_sync(&hdev
->service_timer
);
5723 if (hdev
->service_task
.func
)
5724 cancel_work_sync(&hdev
->service_task
);
5725 if (hdev
->rst_service_task
.func
)
5726 cancel_work_sync(&hdev
->rst_service_task
);
5727 if (hdev
->mbx_service_task
.func
)
5728 cancel_work_sync(&hdev
->mbx_service_task
);
5731 mdiobus_unregister(mac
->mdio_bus
);
5733 /* Disable MISC vector(vector0) */
5734 hclge_enable_vector(&hdev
->misc_vector
, false);
5735 hclge_destroy_cmd_queue(&hdev
->hw
);
5736 hclge_misc_irq_uninit(hdev
);
5737 hclge_pci_uninit(hdev
);
5738 ae_dev
->priv
= NULL
;
5741 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5743 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5744 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5745 struct hclge_dev
*hdev
= vport
->back
;
5747 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5750 static void hclge_get_channels(struct hnae3_handle
*handle
,
5751 struct ethtool_channels
*ch
)
5753 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5755 ch
->max_combined
= hclge_get_max_channels(handle
);
5756 ch
->other_count
= 1;
5758 ch
->combined_count
= vport
->alloc_tqps
;
5761 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5762 u16
*free_tqps
, u16
*max_rss_size
)
5764 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5765 struct hclge_dev
*hdev
= vport
->back
;
5769 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5770 if (!hdev
->htqp
[i
].alloced
)
5773 *free_tqps
= temp_tqps
;
5774 *max_rss_size
= hdev
->rss_size_max
;
5777 static void hclge_release_tqp(struct hclge_vport
*vport
)
5779 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5780 struct hclge_dev
*hdev
= vport
->back
;
5783 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5784 struct hclge_tqp
*tqp
=
5785 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5787 tqp
->q
.handle
= NULL
;
5788 tqp
->q
.tqp_index
= 0;
5789 tqp
->alloced
= false;
5792 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5796 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5798 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5799 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5800 struct hclge_dev
*hdev
= vport
->back
;
5801 int cur_rss_size
= kinfo
->rss_size
;
5802 int cur_tqps
= kinfo
->num_tqps
;
5803 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5804 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5805 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5810 hclge_release_tqp(vport
);
5812 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5814 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5818 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5820 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5824 ret
= hclge_tm_schd_init(hdev
);
5826 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5830 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5831 roundup_size
= ilog2(roundup_size
);
5832 /* Set the RSS TC mode according to the new RSS size */
5833 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5836 if (!(hdev
->hw_tc_map
& BIT(i
)))
5840 tc_size
[i
] = roundup_size
;
5841 tc_offset
[i
] = kinfo
->rss_size
* i
;
5843 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5847 /* Reinitializes the rss indirect table according to the new RSS size */
5848 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5852 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5853 rss_indir
[i
] = i
% kinfo
->rss_size
;
5855 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5857 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5863 dev_info(&hdev
->pdev
->dev
,
5864 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5865 cur_rss_size
, kinfo
->rss_size
,
5866 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5871 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5872 u32
*regs_num_64_bit
)
5874 struct hclge_desc desc
;
5878 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
5879 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5881 dev_err(&hdev
->pdev
->dev
,
5882 "Query register number cmd failed, ret = %d.\n", ret
);
5886 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
5887 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
5889 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
5896 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5899 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
5901 struct hclge_desc
*desc
;
5902 u32
*reg_val
= data
;
5911 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
5912 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5916 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
5917 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5919 dev_err(&hdev
->pdev
->dev
,
5920 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
5925 for (i
= 0; i
< cmd_num
; i
++) {
5927 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
5928 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
5930 desc_data
= (__le32
*)(&desc
[i
]);
5931 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
5933 for (k
= 0; k
< n
; k
++) {
5934 *reg_val
++ = le32_to_cpu(*desc_data
++);
5946 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5949 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
5951 struct hclge_desc
*desc
;
5952 u64
*reg_val
= data
;
5961 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
5962 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5966 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
5967 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5969 dev_err(&hdev
->pdev
->dev
,
5970 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
5975 for (i
= 0; i
< cmd_num
; i
++) {
5977 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
5978 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
5980 desc_data
= (__le64
*)(&desc
[i
]);
5981 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
5983 for (k
= 0; k
< n
; k
++) {
5984 *reg_val
++ = le64_to_cpu(*desc_data
++);
5996 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
5998 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5999 struct hclge_dev
*hdev
= vport
->back
;
6000 u32 regs_num_32_bit
, regs_num_64_bit
;
6003 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6005 dev_err(&hdev
->pdev
->dev
,
6006 "Get register number failed, ret = %d.\n", ret
);
6010 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
6013 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
6016 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6017 struct hclge_dev
*hdev
= vport
->back
;
6018 u32 regs_num_32_bit
, regs_num_64_bit
;
6021 *version
= hdev
->fw_version
;
6023 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6025 dev_err(&hdev
->pdev
->dev
,
6026 "Get register number failed, ret = %d.\n", ret
);
6030 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
6032 dev_err(&hdev
->pdev
->dev
,
6033 "Get 32 bit register failed, ret = %d.\n", ret
);
6037 data
= (u32
*)data
+ regs_num_32_bit
;
6038 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
6041 dev_err(&hdev
->pdev
->dev
,
6042 "Get 64 bit register failed, ret = %d.\n", ret
);
6045 static int hclge_set_led_status_sfp(struct hclge_dev
*hdev
, u8 speed_led_status
,
6046 u8 act_led_status
, u8 link_led_status
,
6047 u8 locate_led_status
)
6049 struct hclge_set_led_state_cmd
*req
;
6050 struct hclge_desc desc
;
6053 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6055 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6056 hnae_set_field(req
->port_speed_led_config
, HCLGE_LED_PORT_SPEED_STATE_M
,
6057 HCLGE_LED_PORT_SPEED_STATE_S
, speed_led_status
);
6058 hnae_set_field(req
->link_led_config
, HCLGE_LED_ACTIVITY_STATE_M
,
6059 HCLGE_LED_ACTIVITY_STATE_S
, act_led_status
);
6060 hnae_set_field(req
->activity_led_config
, HCLGE_LED_LINK_STATE_M
,
6061 HCLGE_LED_LINK_STATE_S
, link_led_status
);
6062 hnae_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6063 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6065 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6067 dev_err(&hdev
->pdev
->dev
,
6068 "Send set led state cmd error, ret =%d\n", ret
);
6073 enum hclge_led_status
{
6076 HCLGE_LED_NO_CHANGE
= 0xFF,
6079 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6080 enum ethtool_phys_id_state status
)
6082 #define BLINK_FREQUENCY 2
6083 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6084 struct hclge_dev
*hdev
= vport
->back
;
6085 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
6088 if (phydev
|| hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
6092 case ETHTOOL_ID_ACTIVE
:
6093 ret
= hclge_set_led_status_sfp(hdev
,
6094 HCLGE_LED_NO_CHANGE
,
6095 HCLGE_LED_NO_CHANGE
,
6096 HCLGE_LED_NO_CHANGE
,
6099 case ETHTOOL_ID_INACTIVE
:
6100 ret
= hclge_set_led_status_sfp(hdev
,
6101 HCLGE_LED_NO_CHANGE
,
6102 HCLGE_LED_NO_CHANGE
,
6103 HCLGE_LED_NO_CHANGE
,
6114 enum hclge_led_port_speed
{
6115 HCLGE_SPEED_LED_FOR_1G
,
6116 HCLGE_SPEED_LED_FOR_10G
,
6117 HCLGE_SPEED_LED_FOR_25G
,
6118 HCLGE_SPEED_LED_FOR_40G
,
6119 HCLGE_SPEED_LED_FOR_50G
,
6120 HCLGE_SPEED_LED_FOR_100G
,
6123 static u8
hclge_led_get_speed_status(u32 speed
)
6128 case HCLGE_MAC_SPEED_1G
:
6129 speed_led
= HCLGE_SPEED_LED_FOR_1G
;
6131 case HCLGE_MAC_SPEED_10G
:
6132 speed_led
= HCLGE_SPEED_LED_FOR_10G
;
6134 case HCLGE_MAC_SPEED_25G
:
6135 speed_led
= HCLGE_SPEED_LED_FOR_25G
;
6137 case HCLGE_MAC_SPEED_40G
:
6138 speed_led
= HCLGE_SPEED_LED_FOR_40G
;
6140 case HCLGE_MAC_SPEED_50G
:
6141 speed_led
= HCLGE_SPEED_LED_FOR_50G
;
6143 case HCLGE_MAC_SPEED_100G
:
6144 speed_led
= HCLGE_SPEED_LED_FOR_100G
;
6147 speed_led
= HCLGE_LED_NO_CHANGE
;
6153 static int hclge_update_led_status(struct hclge_dev
*hdev
)
6155 u8 port_speed_status
, link_status
, activity_status
;
6156 u64 rx_pkts
, tx_pkts
;
6158 if (hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
6161 port_speed_status
= hclge_led_get_speed_status(hdev
->hw
.mac
.speed
);
6163 rx_pkts
= hdev
->hw_stats
.mac_stats
.mac_rx_total_pkt_num
;
6164 tx_pkts
= hdev
->hw_stats
.mac_stats
.mac_tx_total_pkt_num
;
6165 if (rx_pkts
!= hdev
->rx_pkts_for_led
||
6166 tx_pkts
!= hdev
->tx_pkts_for_led
)
6167 activity_status
= HCLGE_LED_ON
;
6169 activity_status
= HCLGE_LED_OFF
;
6170 hdev
->rx_pkts_for_led
= rx_pkts
;
6171 hdev
->tx_pkts_for_led
= tx_pkts
;
6173 if (hdev
->hw
.mac
.link
)
6174 link_status
= HCLGE_LED_ON
;
6176 link_status
= HCLGE_LED_OFF
;
6178 return hclge_set_led_status_sfp(hdev
, port_speed_status
,
6179 activity_status
, link_status
,
6180 HCLGE_LED_NO_CHANGE
);
6183 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6184 unsigned long *supported
,
6185 unsigned long *advertising
)
6187 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6188 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6189 struct hclge_dev
*hdev
= vport
->back
;
6190 unsigned int idx
= 0;
6192 for (; idx
< size
; idx
++) {
6193 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6194 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6198 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6201 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6202 struct hclge_dev
*hdev
= vport
->back
;
6203 u8 media_type
= hdev
->hw
.mac
.media_type
;
6205 switch (media_type
) {
6206 case HNAE3_MEDIA_TYPE_FIBER
:
6207 *port_type
= PORT_FIBRE
;
6209 case HNAE3_MEDIA_TYPE_COPPER
:
6210 *port_type
= PORT_TP
;
6212 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6214 *port_type
= PORT_OTHER
;
6219 static const struct hnae3_ae_ops hclge_ops
= {
6220 .init_ae_dev
= hclge_init_ae_dev
,
6221 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6222 .init_client_instance
= hclge_init_client_instance
,
6223 .uninit_client_instance
= hclge_uninit_client_instance
,
6224 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6225 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6226 .get_vector
= hclge_get_vector
,
6227 .put_vector
= hclge_put_vector
,
6228 .set_promisc_mode
= hclge_set_promisc_mode
,
6229 .set_loopback
= hclge_set_loopback
,
6230 .start
= hclge_ae_start
,
6231 .stop
= hclge_ae_stop
,
6232 .get_status
= hclge_get_status
,
6233 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6234 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6235 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6236 .get_media_type
= hclge_get_media_type
,
6237 .get_rss_key_size
= hclge_get_rss_key_size
,
6238 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6239 .get_rss
= hclge_get_rss
,
6240 .set_rss
= hclge_set_rss
,
6241 .set_rss_tuple
= hclge_set_rss_tuple
,
6242 .get_rss_tuple
= hclge_get_rss_tuple
,
6243 .get_tc_size
= hclge_get_tc_size
,
6244 .get_mac_addr
= hclge_get_mac_addr
,
6245 .set_mac_addr
= hclge_set_mac_addr
,
6246 .add_uc_addr
= hclge_add_uc_addr
,
6247 .rm_uc_addr
= hclge_rm_uc_addr
,
6248 .add_mc_addr
= hclge_add_mc_addr
,
6249 .rm_mc_addr
= hclge_rm_mc_addr
,
6250 .set_autoneg
= hclge_set_autoneg
,
6251 .get_autoneg
= hclge_get_autoneg
,
6252 .get_pauseparam
= hclge_get_pauseparam
,
6253 .set_pauseparam
= hclge_set_pauseparam
,
6254 .set_mtu
= hclge_set_mtu
,
6255 .reset_queue
= hclge_reset_tqp
,
6256 .get_stats
= hclge_get_stats
,
6257 .update_stats
= hclge_update_stats
,
6258 .get_strings
= hclge_get_strings
,
6259 .get_sset_count
= hclge_get_sset_count
,
6260 .get_fw_version
= hclge_get_fw_version
,
6261 .get_mdix_mode
= hclge_get_mdix_mode
,
6262 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6263 .set_vlan_filter
= hclge_set_vlan_filter
,
6264 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6265 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6266 .reset_event
= hclge_reset_event
,
6267 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6268 .set_channels
= hclge_set_channels
,
6269 .get_channels
= hclge_get_channels
,
6270 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6271 .get_regs_len
= hclge_get_regs_len
,
6272 .get_regs
= hclge_get_regs
,
6273 .set_led_id
= hclge_set_led_id
,
6274 .get_link_mode
= hclge_get_link_mode
,
6275 .get_port_type
= hclge_get_port_type
,
6278 static struct hnae3_ae_algo ae_algo
= {
6281 .pdev_id_table
= ae_algo_pci_tbl
,
6284 static int hclge_init(void)
6286 pr_info("%s is initializing\n", HCLGE_NAME
);
6288 return hnae3_register_ae_algo(&ae_algo
);
6291 static void hclge_exit(void)
6293 hnae3_unregister_ae_algo(&ae_algo
);
6295 module_init(hclge_init
);
6296 module_exit(hclge_exit
);
6298 MODULE_LICENSE("GPL");
6299 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6300 MODULE_DESCRIPTION("HCLGE Driver");
6301 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob