2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
21 #include "hclge_cmd.h"
22 #include "hclge_main.h"
23 #include "hclge_mdio.h"
27 #define HCLGE_NAME "hclge"
28 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
29 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
30 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
31 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
33 static int hclge_rss_init_hw(struct hclge_dev
*hdev
);
34 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
35 enum hclge_mta_dmac_sel_type mta_mac_sel
,
37 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
39 static struct hnae3_ae_algo ae_algo
;
41 static const struct pci_device_id ae_algo_pci_tbl
[] = {
42 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
43 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
44 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
45 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
49 /* required last entry */
53 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
55 "Serdes Loopback test",
59 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
98 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
223 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
280 {"mac_tx_overrsize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num
)},
282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
294 {"mac_tx_1519_max_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num
)},
296 {"mac_rx_total_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
298 {"mac_rx_total_oct_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
300 {"mac_rx_good_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
302 {"mac_rx_bad_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
304 {"mac_rx_good_oct_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
306 {"mac_rx_bad_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
308 {"mac_rx_uni_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
310 {"mac_rx_multi_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
312 {"mac_rx_broad_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
314 {"mac_rx_undersize_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
316 {"mac_rx_overrsize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num
)},
318 {"mac_rx_64_oct_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
320 {"mac_rx_65_127_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
322 {"mac_rx_128_255_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
324 {"mac_rx_256_511_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
326 {"mac_rx_512_1023_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
328 {"mac_rx_1024_1518_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
330 {"mac_rx_1519_max_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num
)},
333 {"mac_trans_fragment_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num
)},
335 {"mac_trans_undermin_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num
)},
337 {"mac_trans_jabber_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num
)},
339 {"mac_trans_err_all_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num
)},
341 {"mac_trans_from_app_good_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num
)},
343 {"mac_trans_from_app_bad_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num
)},
345 {"mac_rcv_fragment_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num
)},
347 {"mac_rcv_undermin_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num
)},
349 {"mac_rcv_jabber_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num
)},
351 {"mac_rcv_fcs_err_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num
)},
353 {"mac_rcv_send_app_good_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num
)},
355 {"mac_rcv_send_app_bad_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num
)}
359 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
361 #define HCLGE_64_BIT_CMD_NUM 5
362 #define HCLGE_64_BIT_RTN_DATANUM 4
363 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
364 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
369 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
370 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
372 dev_err(&hdev
->pdev
->dev
,
373 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
377 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
378 if (unlikely(i
== 0)) {
379 desc_data
= (u64
*)(&desc
[i
].data
[0]);
380 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
382 desc_data
= (u64
*)(&desc
[i
]);
383 n
= HCLGE_64_BIT_RTN_DATANUM
;
385 for (k
= 0; k
< n
; k
++) {
386 *data
++ += cpu_to_le64(*desc_data
);
394 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
396 stats
->pkt_curr_buf_cnt
= 0;
397 stats
->pkt_curr_buf_tc0_cnt
= 0;
398 stats
->pkt_curr_buf_tc1_cnt
= 0;
399 stats
->pkt_curr_buf_tc2_cnt
= 0;
400 stats
->pkt_curr_buf_tc3_cnt
= 0;
401 stats
->pkt_curr_buf_tc4_cnt
= 0;
402 stats
->pkt_curr_buf_tc5_cnt
= 0;
403 stats
->pkt_curr_buf_tc6_cnt
= 0;
404 stats
->pkt_curr_buf_tc7_cnt
= 0;
407 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
409 #define HCLGE_32_BIT_CMD_NUM 8
410 #define HCLGE_32_BIT_RTN_DATANUM 8
412 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
413 struct hclge_32_bit_stats
*all_32_bit_stats
;
419 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
420 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
422 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
423 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
425 dev_err(&hdev
->pdev
->dev
,
426 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
431 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
432 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
433 if (unlikely(i
== 0)) {
434 all_32_bit_stats
->igu_rx_err_pkt
+=
435 cpu_to_le32(desc
[i
].data
[0]);
436 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
437 cpu_to_le32(desc
[i
].data
[1] & 0xffff);
438 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
439 cpu_to_le32((desc
[i
].data
[1] >> 16) & 0xffff);
441 desc_data
= (u32
*)(&desc
[i
].data
[2]);
442 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
444 desc_data
= (u32
*)(&desc
[i
]);
445 n
= HCLGE_32_BIT_RTN_DATANUM
;
447 for (k
= 0; k
< n
; k
++) {
448 *data
++ += cpu_to_le32(*desc_data
);
456 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
458 #define HCLGE_MAC_CMD_NUM 17
459 #define HCLGE_RTN_DATA_NUM 4
461 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
462 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
467 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
468 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
470 dev_err(&hdev
->pdev
->dev
,
471 "Get MAC pkt stats fail, status = %d.\n", ret
);
476 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
477 if (unlikely(i
== 0)) {
478 desc_data
= (u64
*)(&desc
[i
].data
[0]);
479 n
= HCLGE_RTN_DATA_NUM
- 2;
481 desc_data
= (u64
*)(&desc
[i
]);
482 n
= HCLGE_RTN_DATA_NUM
;
484 for (k
= 0; k
< n
; k
++) {
485 *data
++ += cpu_to_le64(*desc_data
);
493 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
495 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
496 struct hclge_vport
*vport
= hclge_get_vport(handle
);
497 struct hclge_dev
*hdev
= vport
->back
;
498 struct hnae3_queue
*queue
;
499 struct hclge_desc desc
[1];
500 struct hclge_tqp
*tqp
;
503 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
504 queue
= handle
->kinfo
.tqp
[i
];
505 tqp
= container_of(queue
, struct hclge_tqp
, q
);
506 /* command : HCLGE_OPC_QUERY_IGU_STAT */
507 hclge_cmd_setup_basic_desc(&desc
[0],
508 HCLGE_OPC_QUERY_RX_STATUS
,
511 desc
[0].data
[0] = (tqp
->index
& 0x1ff);
512 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
514 dev_err(&hdev
->pdev
->dev
,
515 "Query tqp stat fail, status = %d,queue = %d\n",
519 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
520 cpu_to_le32(desc
[0].data
[4]);
523 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
524 queue
= handle
->kinfo
.tqp
[i
];
525 tqp
= container_of(queue
, struct hclge_tqp
, q
);
526 /* command : HCLGE_OPC_QUERY_IGU_STAT */
527 hclge_cmd_setup_basic_desc(&desc
[0],
528 HCLGE_OPC_QUERY_TX_STATUS
,
531 desc
[0].data
[0] = (tqp
->index
& 0x1ff);
532 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
534 dev_err(&hdev
->pdev
->dev
,
535 "Query tqp stat fail, status = %d,queue = %d\n",
539 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
540 cpu_to_le32(desc
[0].data
[4]);
546 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
548 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
549 struct hclge_tqp
*tqp
;
553 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
554 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
555 *buff
++ = cpu_to_le64(tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
);
558 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
559 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
560 *buff
++ = cpu_to_le64(tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
);
566 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
568 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
570 return kinfo
->num_tqps
* (2);
573 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
575 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
579 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
580 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
581 struct hclge_tqp
, q
);
582 snprintf(buff
, ETH_GSTRING_LEN
, "rcb_q%d_tx_pktnum_rcd",
584 buff
= buff
+ ETH_GSTRING_LEN
;
587 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
588 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
589 struct hclge_tqp
, q
);
590 snprintf(buff
, ETH_GSTRING_LEN
, "rcb_q%d_rx_pktnum_rcd",
592 buff
= buff
+ ETH_GSTRING_LEN
;
598 static u64
*hclge_comm_get_stats(void *comm_stats
,
599 const struct hclge_comm_stats_str strs
[],
605 for (i
= 0; i
< size
; i
++)
606 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
611 static u8
*hclge_comm_get_strings(u32 stringset
,
612 const struct hclge_comm_stats_str strs
[],
615 char *buff
= (char *)data
;
618 if (stringset
!= ETH_SS_STATS
)
621 for (i
= 0; i
< size
; i
++) {
622 snprintf(buff
, ETH_GSTRING_LEN
,
624 buff
= buff
+ ETH_GSTRING_LEN
;
630 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
631 struct net_device_stats
*net_stats
)
633 net_stats
->tx_dropped
= 0;
634 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
635 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
636 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
638 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
639 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
640 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_err_pkt
;
641 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
642 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
643 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rcv_fcs_err_pkt_num
;
645 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
646 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
648 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rcv_fcs_err_pkt_num
;
649 net_stats
->rx_length_errors
=
650 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
651 net_stats
->rx_length_errors
+=
652 hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
653 net_stats
->rx_over_errors
=
654 hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
657 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
659 struct hnae3_handle
*handle
;
662 handle
= &hdev
->vport
[0].nic
;
663 if (handle
->client
) {
664 status
= hclge_tqps_update_stats(handle
);
666 dev_err(&hdev
->pdev
->dev
,
667 "Update TQPS stats fail, status = %d.\n",
672 status
= hclge_mac_update_stats(hdev
);
674 dev_err(&hdev
->pdev
->dev
,
675 "Update MAC stats fail, status = %d.\n", status
);
677 status
= hclge_32_bit_update_stats(hdev
);
679 dev_err(&hdev
->pdev
->dev
,
680 "Update 32 bit stats fail, status = %d.\n",
683 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
686 static void hclge_update_stats(struct hnae3_handle
*handle
,
687 struct net_device_stats
*net_stats
)
689 struct hclge_vport
*vport
= hclge_get_vport(handle
);
690 struct hclge_dev
*hdev
= vport
->back
;
691 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
694 status
= hclge_mac_update_stats(hdev
);
696 dev_err(&hdev
->pdev
->dev
,
697 "Update MAC stats fail, status = %d.\n",
700 status
= hclge_32_bit_update_stats(hdev
);
702 dev_err(&hdev
->pdev
->dev
,
703 "Update 32 bit stats fail, status = %d.\n",
706 status
= hclge_64_bit_update_stats(hdev
);
708 dev_err(&hdev
->pdev
->dev
,
709 "Update 64 bit stats fail, status = %d.\n",
712 status
= hclge_tqps_update_stats(handle
);
714 dev_err(&hdev
->pdev
->dev
,
715 "Update TQPS stats fail, status = %d.\n",
718 hclge_update_netstat(hw_stats
, net_stats
);
721 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
723 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
725 struct hclge_vport
*vport
= hclge_get_vport(handle
);
726 struct hclge_dev
*hdev
= vport
->back
;
729 /* Loopback test support rules:
730 * mac: only GE mode support
731 * serdes: all mac mode will support include GE/XGE/LGE/CGE
732 * phy: only support when phy device exist on board
734 if (stringset
== ETH_SS_TEST
) {
735 /* clear loopback bit flags at first */
736 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
737 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
738 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
739 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
741 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
745 } else if (stringset
== ETH_SS_STATS
) {
746 count
= ARRAY_SIZE(g_mac_stats_string
) +
747 ARRAY_SIZE(g_all_32bit_stats_string
) +
748 ARRAY_SIZE(g_all_64bit_stats_string
) +
749 hclge_tqps_get_sset_count(handle
, stringset
);
755 static void hclge_get_strings(struct hnae3_handle
*handle
,
759 u8
*p
= (char *)data
;
762 if (stringset
== ETH_SS_STATS
) {
763 size
= ARRAY_SIZE(g_mac_stats_string
);
764 p
= hclge_comm_get_strings(stringset
,
768 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
769 p
= hclge_comm_get_strings(stringset
,
770 g_all_32bit_stats_string
,
773 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
774 p
= hclge_comm_get_strings(stringset
,
775 g_all_64bit_stats_string
,
778 p
= hclge_tqps_get_strings(handle
, p
);
779 } else if (stringset
== ETH_SS_TEST
) {
780 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
782 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
784 p
+= ETH_GSTRING_LEN
;
786 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
788 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
790 p
+= ETH_GSTRING_LEN
;
792 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
794 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
796 p
+= ETH_GSTRING_LEN
;
801 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
803 struct hclge_vport
*vport
= hclge_get_vport(handle
);
804 struct hclge_dev
*hdev
= vport
->back
;
807 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
809 ARRAY_SIZE(g_mac_stats_string
),
811 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
812 g_all_32bit_stats_string
,
813 ARRAY_SIZE(g_all_32bit_stats_string
),
815 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
816 g_all_64bit_stats_string
,
817 ARRAY_SIZE(g_all_64bit_stats_string
),
819 p
= hclge_tqps_get_stats(handle
, p
);
822 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
823 struct hclge_func_status
*status
)
825 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
828 /* Set the pf to main pf */
829 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
830 hdev
->flag
|= HCLGE_FLAG_MAIN
;
832 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
834 hdev
->num_req_vfs
= status
->vf_num
/ status
->pf_num
;
838 static int hclge_query_function_status(struct hclge_dev
*hdev
)
840 struct hclge_func_status
*req
;
841 struct hclge_desc desc
;
845 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
846 req
= (struct hclge_func_status
*)desc
.data
;
849 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
851 dev_err(&hdev
->pdev
->dev
,
852 "query function status failed %d.\n",
858 /* Check pf reset is done */
861 usleep_range(1000, 2000);
862 } while (timeout
++ < 5);
864 ret
= hclge_parse_func_status(hdev
, req
);
869 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
871 struct hclge_pf_res
*req
;
872 struct hclge_desc desc
;
875 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
876 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
878 dev_err(&hdev
->pdev
->dev
,
879 "query pf resource failed %d.\n", ret
);
883 req
= (struct hclge_pf_res
*)desc
.data
;
884 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
885 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
887 if (hnae3_dev_roce_supported(hdev
)) {
888 hdev
->num_roce_msix
=
889 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
890 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
892 /* PF should have NIC vectors and Roce vectors,
893 * NIC vectors are queued before Roce vectors.
895 hdev
->num_msi
= hdev
->num_roce_msix
+ HCLGE_ROCE_VECTOR_OFFSET
;
898 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
899 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
905 static int hclge_parse_speed(int speed_cmd
, int *speed
)
909 *speed
= HCLGE_MAC_SPEED_10M
;
912 *speed
= HCLGE_MAC_SPEED_100M
;
915 *speed
= HCLGE_MAC_SPEED_1G
;
918 *speed
= HCLGE_MAC_SPEED_10G
;
921 *speed
= HCLGE_MAC_SPEED_25G
;
924 *speed
= HCLGE_MAC_SPEED_40G
;
927 *speed
= HCLGE_MAC_SPEED_50G
;
930 *speed
= HCLGE_MAC_SPEED_100G
;
939 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
941 struct hclge_cfg_param
*req
;
942 u64 mac_addr_tmp_high
;
946 req
= (struct hclge_cfg_param
*)desc
[0].data
;
948 /* get the configuration */
949 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
952 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
953 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
954 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
955 HCLGE_CFG_TQP_DESC_N_M
,
956 HCLGE_CFG_TQP_DESC_N_S
);
958 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
959 HCLGE_CFG_PHY_ADDR_M
,
960 HCLGE_CFG_PHY_ADDR_S
);
961 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
962 HCLGE_CFG_MEDIA_TP_M
,
963 HCLGE_CFG_MEDIA_TP_S
);
964 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
965 HCLGE_CFG_RX_BUF_LEN_M
,
966 HCLGE_CFG_RX_BUF_LEN_S
);
967 /* get mac_address */
968 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
969 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
970 HCLGE_CFG_MAC_ADDR_H_M
,
971 HCLGE_CFG_MAC_ADDR_H_S
);
973 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
975 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
976 HCLGE_CFG_DEFAULT_SPEED_M
,
977 HCLGE_CFG_DEFAULT_SPEED_S
);
978 for (i
= 0; i
< ETH_ALEN
; i
++)
979 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
981 req
= (struct hclge_cfg_param
*)desc
[1].data
;
982 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
985 /* hclge_get_cfg: query the static parameter from flash
986 * @hdev: pointer to struct hclge_dev
987 * @hcfg: the config structure to be getted
989 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
991 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
992 struct hclge_cfg_param
*req
;
995 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
996 req
= (struct hclge_cfg_param
*)desc
[i
].data
;
997 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
999 hnae_set_field(req
->offset
, HCLGE_CFG_OFFSET_M
,
1000 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1001 /* Len should be united by 4 bytes when send to hardware */
1002 hnae_set_field(req
->offset
, HCLGE_CFG_RD_LEN_M
,
1004 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1005 req
->offset
= cpu_to_le32(req
->offset
);
1008 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1010 dev_err(&hdev
->pdev
->dev
,
1011 "get config failed %d.\n", ret
);
1015 hclge_parse_cfg(hcfg
, desc
);
1019 static int hclge_get_cap(struct hclge_dev
*hdev
)
1023 ret
= hclge_query_function_status(hdev
);
1025 dev_err(&hdev
->pdev
->dev
,
1026 "query function status error %d.\n", ret
);
1030 /* get pf resource */
1031 ret
= hclge_query_pf_resource(hdev
);
1033 dev_err(&hdev
->pdev
->dev
,
1034 "query pf resource error %d.\n", ret
);
1041 static int hclge_configure(struct hclge_dev
*hdev
)
1043 struct hclge_cfg cfg
;
1046 ret
= hclge_get_cfg(hdev
, &cfg
);
1048 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1052 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1053 hdev
->base_tqp_pid
= 0;
1054 hdev
->rss_size_max
= 1;
1055 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1056 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1057 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1058 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1059 hdev
->num_desc
= cfg
.tqp_desc_num
;
1060 hdev
->tm_info
.num_pg
= 1;
1061 hdev
->tm_info
.num_tc
= cfg
.tc_num
;
1062 hdev
->tm_info
.hw_pfc_map
= 0;
1064 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1066 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1070 if ((hdev
->tm_info
.num_tc
> HNAE3_MAX_TC
) ||
1071 (hdev
->tm_info
.num_tc
< 1)) {
1072 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1073 hdev
->tm_info
.num_tc
);
1074 hdev
->tm_info
.num_tc
= 1;
1077 /* Currently not support uncontiuous tc */
1078 for (i
= 0; i
< cfg
.tc_num
; i
++)
1079 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1081 if (!hdev
->num_vmdq_vport
&& !hdev
->num_req_vfs
)
1082 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1084 hdev
->tx_sch_mode
= HCLGE_FLAG_VNET_BASE_SCH_MODE
;
1089 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1092 struct hclge_cfg_tso_status
*req
;
1093 struct hclge_desc desc
;
1095 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1097 req
= (struct hclge_cfg_tso_status
*)desc
.data
;
1098 hnae_set_field(req
->tso_mss_min
, HCLGE_TSO_MSS_MIN_M
,
1099 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1100 hnae_set_field(req
->tso_mss_max
, HCLGE_TSO_MSS_MIN_M
,
1101 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1103 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1106 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1108 struct hclge_tqp
*tqp
;
1111 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1112 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1118 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1119 tqp
->dev
= &hdev
->pdev
->dev
;
1122 tqp
->q
.ae_algo
= &ae_algo
;
1123 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1124 tqp
->q
.desc_num
= hdev
->num_desc
;
1125 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1126 i
* HCLGE_TQP_REG_SIZE
;
1134 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1135 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1137 struct hclge_tqp_map
*req
;
1138 struct hclge_desc desc
;
1141 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1143 req
= (struct hclge_tqp_map
*)desc
.data
;
1144 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1145 req
->tqp_vf
= cpu_to_le16(func_id
);
1146 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1147 1 << HCLGE_TQP_MAP_EN_B
;
1148 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1150 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1152 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1160 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1161 struct hnae3_queue
**tqp
, u16 num_tqps
)
1163 struct hclge_dev
*hdev
= vport
->back
;
1164 int i
, alloced
, func_id
, ret
;
1167 func_id
= vport
->vport_id
;
1168 is_pf
= (vport
->vport_id
== 0) ? true : false;
1170 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1171 alloced
< num_tqps
; i
++) {
1172 if (!hdev
->htqp
[i
].alloced
) {
1173 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1174 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1175 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1176 hdev
->htqp
[i
].alloced
= true;
1177 ret
= hclge_map_tqps_to_func(hdev
, func_id
,
1178 hdev
->htqp
[i
].index
,
1186 vport
->alloc_tqps
= num_tqps
;
1191 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1193 struct hnae3_handle
*nic
= &vport
->nic
;
1194 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1195 struct hclge_dev
*hdev
= vport
->back
;
1198 kinfo
->num_desc
= hdev
->num_desc
;
1199 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1200 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1202 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1203 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1205 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1206 if (hdev
->hw_tc_map
& BIT(i
)) {
1207 kinfo
->tc_info
[i
].enable
= true;
1208 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1209 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1210 kinfo
->tc_info
[i
].tc
= i
;
1212 /* Set to default queue if TC is disable */
1213 kinfo
->tc_info
[i
].enable
= false;
1214 kinfo
->tc_info
[i
].tqp_offset
= 0;
1215 kinfo
->tc_info
[i
].tqp_count
= 1;
1216 kinfo
->tc_info
[i
].tc
= 0;
1220 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1221 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1225 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1227 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1234 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1236 /* this would be initialized later */
1239 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1241 struct hnae3_handle
*nic
= &vport
->nic
;
1242 struct hclge_dev
*hdev
= vport
->back
;
1245 nic
->pdev
= hdev
->pdev
;
1246 nic
->ae_algo
= &ae_algo
;
1247 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1249 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1250 ret
= hclge_knic_setup(vport
, num_tqps
);
1252 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1257 hclge_unic_setup(vport
, num_tqps
);
1263 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1265 struct pci_dev
*pdev
= hdev
->pdev
;
1266 struct hclge_vport
*vport
;
1272 /* We need to alloc a vport for main NIC of PF */
1273 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1275 if (hdev
->num_tqps
< num_vport
)
1276 num_vport
= hdev
->num_tqps
;
1278 /* Alloc the same number of TQPs for every vport */
1279 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1280 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1282 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1287 hdev
->vport
= vport
;
1288 hdev
->num_alloc_vport
= num_vport
;
1290 #ifdef CONFIG_PCI_IOV
1292 if (hdev
->num_req_vfs
) {
1293 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1295 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1297 hdev
->num_alloc_vfs
= 0;
1298 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1303 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1306 for (i
= 0; i
< num_vport
; i
++) {
1308 vport
->vport_id
= i
;
1311 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1313 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1316 "vport setup failed for vport %d, %d\n",
1327 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
, u16 buf_size
)
1329 /* TX buffer size is unit by 128 byte */
1330 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1331 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1332 struct hclge_tx_buff_alloc
*req
;
1333 struct hclge_desc desc
;
1337 req
= (struct hclge_tx_buff_alloc
*)desc
.data
;
1339 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1340 for (i
= 0; i
< HCLGE_TC_NUM
; i
++)
1341 req
->tx_pkt_buff
[i
] =
1342 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1343 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1345 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1347 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1355 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
, u32 buf_size
)
1357 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_size
);
1360 dev_err(&hdev
->pdev
->dev
,
1361 "tx buffer alloc failed %d\n", ret
);
1368 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1372 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1373 if (hdev
->hw_tc_map
& BIT(i
))
1378 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1382 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1383 if (hdev
->hw_tc_map
& BIT(i
) &&
1384 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1389 /* Get the number of pfc enabled TCs, which have private buffer */
1390 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
)
1392 struct hclge_priv_buf
*priv
;
1395 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1396 priv
= &hdev
->priv_buf
[i
];
1397 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1405 /* Get the number of pfc disabled TCs, which have private buffer */
1406 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
)
1408 struct hclge_priv_buf
*priv
;
1411 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1412 priv
= &hdev
->priv_buf
[i
];
1413 if (hdev
->hw_tc_map
& BIT(i
) &&
1414 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1422 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_dev
*hdev
)
1424 struct hclge_priv_buf
*priv
;
1428 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1429 priv
= &hdev
->priv_buf
[i
];
1431 rx_priv
+= priv
->buf_size
;
1436 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
, u32 rx_all
)
1438 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1439 int tc_num
, pfc_enable_num
;
1444 tc_num
= hclge_get_tc_num(hdev
);
1445 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1447 if (hnae3_dev_dcb_supported(hdev
))
1448 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1450 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1452 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1453 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1455 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1457 rx_priv
= hclge_get_rx_priv_buff_alloced(hdev
);
1458 if (rx_all
<= rx_priv
+ shared_std
)
1461 shared_buf
= rx_all
- rx_priv
;
1462 hdev
->s_buf
.buf_size
= shared_buf
;
1463 hdev
->s_buf
.self
.high
= shared_buf
;
1464 hdev
->s_buf
.self
.low
= 2 * hdev
->mps
;
1466 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1467 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1468 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1469 hdev
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1470 hdev
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1472 hdev
->s_buf
.tc_thrd
[i
].low
= 0;
1473 hdev
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1480 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1481 * @hdev: pointer to struct hclge_dev
1482 * @tx_size: the allocated tx buffer for all TCs
1483 * @return: 0: calculate sucessful, negative: fail
1485 int hclge_rx_buffer_calc(struct hclge_dev
*hdev
, u32 tx_size
)
1487 u32 rx_all
= hdev
->pkt_buf_size
- tx_size
;
1488 int no_pfc_priv_num
, pfc_priv_num
;
1489 struct hclge_priv_buf
*priv
;
1492 /* When DCB is not supported, rx private
1493 * buffer is not allocated.
1495 if (!hnae3_dev_dcb_supported(hdev
)) {
1496 if (!hclge_is_rx_buf_ok(hdev
, rx_all
))
1502 /* step 1, try to alloc private buffer for all enabled tc */
1503 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1504 priv
= &hdev
->priv_buf
[i
];
1505 if (hdev
->hw_tc_map
& BIT(i
)) {
1507 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1508 priv
->wl
.low
= hdev
->mps
;
1509 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1510 priv
->buf_size
= priv
->wl
.high
+
1514 priv
->wl
.high
= 2 * hdev
->mps
;
1515 priv
->buf_size
= priv
->wl
.high
;
1525 if (hclge_is_rx_buf_ok(hdev
, rx_all
))
1528 /* step 2, try to decrease the buffer size of
1529 * no pfc TC's private buffer
1531 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1532 priv
= &hdev
->priv_buf
[i
];
1539 if (!(hdev
->hw_tc_map
& BIT(i
)))
1544 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1546 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1547 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1550 priv
->wl
.high
= hdev
->mps
;
1551 priv
->buf_size
= priv
->wl
.high
;
1555 if (hclge_is_rx_buf_ok(hdev
, rx_all
))
1558 /* step 3, try to reduce the number of pfc disabled TCs,
1559 * which have private buffer
1561 /* get the total no pfc enable TC number, which have private buffer */
1562 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
);
1564 /* let the last to be cleared first */
1565 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1566 priv
= &hdev
->priv_buf
[i
];
1568 if (hdev
->hw_tc_map
& BIT(i
) &&
1569 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1570 /* Clear the no pfc TC private buffer */
1578 if (hclge_is_rx_buf_ok(hdev
, rx_all
) ||
1579 no_pfc_priv_num
== 0)
1583 if (hclge_is_rx_buf_ok(hdev
, rx_all
))
1586 /* step 4, try to reduce the number of pfc enabled TCs
1587 * which have private buffer.
1589 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
);
1591 /* let the last to be cleared first */
1592 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1593 priv
= &hdev
->priv_buf
[i
];
1595 if (hdev
->hw_tc_map
& BIT(i
) &&
1596 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1597 /* Reduce the number of pfc TC with private buffer */
1605 if (hclge_is_rx_buf_ok(hdev
, rx_all
) ||
1609 if (hclge_is_rx_buf_ok(hdev
, rx_all
))
1615 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
)
1617 struct hclge_rx_priv_buff
*req
;
1618 struct hclge_desc desc
;
1622 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1623 req
= (struct hclge_rx_priv_buff
*)desc
.data
;
1625 /* Alloc private buffer TCs */
1626 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1627 struct hclge_priv_buf
*priv
= &hdev
->priv_buf
[i
];
1630 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1632 cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B
);
1636 cpu_to_le16((hdev
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1637 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1639 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1641 dev_err(&hdev
->pdev
->dev
,
1642 "rx private buffer alloc cmd failed %d\n", ret
);
1649 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1651 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
)
1653 struct hclge_rx_priv_wl_buf
*req
;
1654 struct hclge_priv_buf
*priv
;
1655 struct hclge_desc desc
[2];
1659 for (i
= 0; i
< 2; i
++) {
1660 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1662 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1664 /* The first descriptor set the NEXT bit to 1 */
1666 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1668 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1670 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1671 priv
= &hdev
->priv_buf
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1672 req
->tc_wl
[j
].high
=
1673 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1674 req
->tc_wl
[j
].high
|=
1675 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1676 HCLGE_RX_PRIV_EN_B
);
1678 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1679 req
->tc_wl
[j
].low
|=
1680 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1681 HCLGE_RX_PRIV_EN_B
);
1685 /* Send 2 descriptor at one time */
1686 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1688 dev_err(&hdev
->pdev
->dev
,
1689 "rx private waterline config cmd failed %d\n",
1696 static int hclge_common_thrd_config(struct hclge_dev
*hdev
)
1698 struct hclge_shared_buf
*s_buf
= &hdev
->s_buf
;
1699 struct hclge_rx_com_thrd
*req
;
1700 struct hclge_desc desc
[2];
1701 struct hclge_tc_thrd
*tc
;
1705 for (i
= 0; i
< 2; i
++) {
1706 hclge_cmd_setup_basic_desc(&desc
[i
],
1707 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1708 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1710 /* The first descriptor set the NEXT bit to 1 */
1712 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1714 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1716 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1717 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1719 req
->com_thrd
[j
].high
=
1720 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1721 req
->com_thrd
[j
].high
|=
1722 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1723 HCLGE_RX_PRIV_EN_B
);
1724 req
->com_thrd
[j
].low
=
1725 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1726 req
->com_thrd
[j
].low
|=
1727 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1728 HCLGE_RX_PRIV_EN_B
);
1732 /* Send 2 descriptors at one time */
1733 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1735 dev_err(&hdev
->pdev
->dev
,
1736 "common threshold config cmd failed %d\n", ret
);
1742 static int hclge_common_wl_config(struct hclge_dev
*hdev
)
1744 struct hclge_shared_buf
*buf
= &hdev
->s_buf
;
1745 struct hclge_rx_com_wl
*req
;
1746 struct hclge_desc desc
;
1749 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1751 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1752 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1754 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1755 HCLGE_RX_PRIV_EN_B
);
1757 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1759 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1760 HCLGE_RX_PRIV_EN_B
);
1762 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1764 dev_err(&hdev
->pdev
->dev
,
1765 "common waterline config cmd failed %d\n", ret
);
1772 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1774 u32 tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1777 hdev
->priv_buf
= devm_kmalloc_array(&hdev
->pdev
->dev
, HCLGE_MAX_TC_NUM
,
1778 sizeof(struct hclge_priv_buf
),
1779 GFP_KERNEL
| __GFP_ZERO
);
1780 if (!hdev
->priv_buf
)
1783 ret
= hclge_tx_buffer_alloc(hdev
, tx_buf_size
);
1785 dev_err(&hdev
->pdev
->dev
,
1786 "could not alloc tx buffers %d\n", ret
);
1790 ret
= hclge_rx_buffer_calc(hdev
, tx_buf_size
);
1792 dev_err(&hdev
->pdev
->dev
,
1793 "could not calc rx priv buffer size for all TCs %d\n",
1798 ret
= hclge_rx_priv_buf_alloc(hdev
);
1800 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1805 if (hnae3_dev_dcb_supported(hdev
)) {
1806 ret
= hclge_rx_priv_wl_config(hdev
);
1808 dev_err(&hdev
->pdev
->dev
,
1809 "could not configure rx private waterline %d\n",
1814 ret
= hclge_common_thrd_config(hdev
);
1816 dev_err(&hdev
->pdev
->dev
,
1817 "could not configure common threshold %d\n",
1823 ret
= hclge_common_wl_config(hdev
);
1825 dev_err(&hdev
->pdev
->dev
,
1826 "could not configure common waterline %d\n", ret
);
1833 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
1835 struct hnae3_handle
*roce
= &vport
->roce
;
1836 struct hnae3_handle
*nic
= &vport
->nic
;
1838 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msix
;
1840 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
1841 vport
->back
->num_msi_left
== 0)
1844 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
1846 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
1847 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
1849 roce
->pdev
= nic
->pdev
;
1850 roce
->ae_algo
= nic
->ae_algo
;
1851 roce
->numa_node_mask
= nic
->numa_node_mask
;
1856 static int hclge_init_msix(struct hclge_dev
*hdev
)
1858 struct pci_dev
*pdev
= hdev
->pdev
;
1861 hdev
->msix_entries
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1862 sizeof(struct msix_entry
),
1864 if (!hdev
->msix_entries
)
1867 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1868 sizeof(u16
), GFP_KERNEL
);
1869 if (!hdev
->vector_status
)
1872 for (i
= 0; i
< hdev
->num_msi
; i
++) {
1873 hdev
->msix_entries
[i
].entry
= i
;
1874 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
1877 hdev
->num_msi_left
= hdev
->num_msi
;
1878 hdev
->base_msi_vector
= hdev
->pdev
->irq
;
1879 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
1880 HCLGE_ROCE_VECTOR_OFFSET
;
1882 ret
= pci_enable_msix_range(hdev
->pdev
, hdev
->msix_entries
,
1883 hdev
->num_msi
, hdev
->num_msi
);
1885 dev_info(&hdev
->pdev
->dev
,
1886 "MSI-X vector alloc failed: %d\n", ret
);
1893 static int hclge_init_msi(struct hclge_dev
*hdev
)
1895 struct pci_dev
*pdev
= hdev
->pdev
;
1899 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1900 sizeof(u16
), GFP_KERNEL
);
1901 if (!hdev
->vector_status
)
1904 for (i
= 0; i
< hdev
->num_msi
; i
++)
1905 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
1907 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
, PCI_IRQ_MSI
);
1909 dev_err(&pdev
->dev
, "MSI vectors enable failed %d\n", vectors
);
1912 hdev
->num_msi
= vectors
;
1913 hdev
->num_msi_left
= vectors
;
1914 hdev
->base_msi_vector
= pdev
->irq
;
1915 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
1916 HCLGE_ROCE_VECTOR_OFFSET
;
1921 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
1923 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
1925 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
1926 mac
->duplex
= (u8
)duplex
;
1928 mac
->duplex
= HCLGE_MAC_FULL
;
1933 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
1935 struct hclge_config_mac_speed_dup
*req
;
1936 struct hclge_desc desc
;
1939 req
= (struct hclge_config_mac_speed_dup
*)desc
.data
;
1941 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
1943 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
1946 case HCLGE_MAC_SPEED_10M
:
1947 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
1948 HCLGE_CFG_SPEED_S
, 6);
1950 case HCLGE_MAC_SPEED_100M
:
1951 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
1952 HCLGE_CFG_SPEED_S
, 7);
1954 case HCLGE_MAC_SPEED_1G
:
1955 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
1956 HCLGE_CFG_SPEED_S
, 0);
1958 case HCLGE_MAC_SPEED_10G
:
1959 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
1960 HCLGE_CFG_SPEED_S
, 1);
1962 case HCLGE_MAC_SPEED_25G
:
1963 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
1964 HCLGE_CFG_SPEED_S
, 2);
1966 case HCLGE_MAC_SPEED_40G
:
1967 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
1968 HCLGE_CFG_SPEED_S
, 3);
1970 case HCLGE_MAC_SPEED_50G
:
1971 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
1972 HCLGE_CFG_SPEED_S
, 4);
1974 case HCLGE_MAC_SPEED_100G
:
1975 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
1976 HCLGE_CFG_SPEED_S
, 5);
1979 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
1983 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
1986 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1988 dev_err(&hdev
->pdev
->dev
,
1989 "mac speed/duplex config cmd failed %d.\n", ret
);
1993 hclge_check_speed_dup(hdev
, duplex
, speed
);
1998 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2001 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2002 struct hclge_dev
*hdev
= vport
->back
;
2004 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2007 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2010 struct hclge_query_an_speed_dup
*req
;
2011 struct hclge_desc desc
;
2015 req
= (struct hclge_query_an_speed_dup
*)desc
.data
;
2017 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2018 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2020 dev_err(&hdev
->pdev
->dev
,
2021 "mac speed/autoneg/duplex query cmd failed %d\n",
2026 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2027 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2028 HCLGE_QUERY_SPEED_S
);
2030 ret
= hclge_parse_speed(speed_tmp
, speed
);
2032 dev_err(&hdev
->pdev
->dev
,
2033 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2040 static int hclge_query_autoneg_result(struct hclge_dev
*hdev
)
2042 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2043 struct hclge_query_an_speed_dup
*req
;
2044 struct hclge_desc desc
;
2047 req
= (struct hclge_query_an_speed_dup
*)desc
.data
;
2049 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2050 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2052 dev_err(&hdev
->pdev
->dev
,
2053 "autoneg result query cmd failed %d.\n", ret
);
2057 mac
->autoneg
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_AN_B
);
2062 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2064 struct hclge_config_auto_neg
*req
;
2065 struct hclge_desc desc
;
2068 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2070 req
= (struct hclge_config_auto_neg
*)desc
.data
;
2071 hnae_set_bit(req
->cfg_an_cmd_flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2073 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2075 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2083 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2085 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2086 struct hclge_dev
*hdev
= vport
->back
;
2088 return hclge_set_autoneg_en(hdev
, enable
);
2091 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2093 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2094 struct hclge_dev
*hdev
= vport
->back
;
2096 hclge_query_autoneg_result(hdev
);
2098 return hdev
->hw
.mac
.autoneg
;
2101 static int hclge_mac_init(struct hclge_dev
*hdev
)
2103 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2106 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2108 dev_err(&hdev
->pdev
->dev
,
2109 "Config mac speed dup fail ret=%d\n", ret
);
2115 ret
= hclge_mac_mdio_config(hdev
);
2117 dev_warn(&hdev
->pdev
->dev
,
2118 "mdio config fail ret=%d\n", ret
);
2122 /* Initialize the MTA table work mode */
2123 hdev
->accept_mta_mc
= true;
2124 hdev
->enable_mta
= true;
2125 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2127 ret
= hclge_set_mta_filter_mode(hdev
,
2128 hdev
->mta_mac_sel_type
,
2131 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2136 return hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2139 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2141 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2142 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2143 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2144 (void)schedule_work(&hdev
->service_task
);
2147 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2149 struct hclge_link_status
*req
;
2150 struct hclge_desc desc
;
2154 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2155 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2157 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2162 req
= (struct hclge_link_status
*)desc
.data
;
2163 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2165 return !!link_status
;
2168 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2173 mac_state
= hclge_get_mac_link_status(hdev
);
2175 if (hdev
->hw
.mac
.phydev
) {
2176 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2177 link_stat
= mac_state
&
2178 hdev
->hw
.mac
.phydev
->link
;
2183 link_stat
= mac_state
;
2189 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2191 struct hnae3_client
*client
= hdev
->nic_client
;
2192 struct hnae3_handle
*handle
;
2198 state
= hclge_get_mac_phy_link(hdev
);
2199 if (state
!= hdev
->hw
.mac
.link
) {
2200 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2201 handle
= &hdev
->vport
[i
].nic
;
2202 client
->ops
->link_status_change(handle
, state
);
2204 hdev
->hw
.mac
.link
= state
;
2208 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2210 struct hclge_mac mac
= hdev
->hw
.mac
;
2215 /* get the speed and duplex as autoneg'result from mac cmd when phy
2221 /* update mac->antoneg. */
2222 ret
= hclge_query_autoneg_result(hdev
);
2224 dev_err(&hdev
->pdev
->dev
,
2225 "autoneg result query failed %d\n", ret
);
2232 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2234 dev_err(&hdev
->pdev
->dev
,
2235 "mac autoneg/speed/duplex query failed %d\n", ret
);
2239 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2240 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2242 dev_err(&hdev
->pdev
->dev
,
2243 "mac speed/duplex config failed %d\n", ret
);
2251 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2253 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2254 struct hclge_dev
*hdev
= vport
->back
;
2256 return hclge_update_speed_duplex(hdev
);
2259 static int hclge_get_status(struct hnae3_handle
*handle
)
2261 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2262 struct hclge_dev
*hdev
= vport
->back
;
2264 hclge_update_link_status(hdev
);
2266 return hdev
->hw
.mac
.link
;
2269 static void hclge_service_timer(unsigned long data
)
2271 struct hclge_dev
*hdev
= (struct hclge_dev
*)data
;
2272 (void)mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2274 hclge_task_schedule(hdev
);
2277 static void hclge_service_complete(struct hclge_dev
*hdev
)
2279 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2281 /* Flush memory before next watchdog */
2282 smp_mb__before_atomic();
2283 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2286 static void hclge_service_task(struct work_struct
*work
)
2288 struct hclge_dev
*hdev
=
2289 container_of(work
, struct hclge_dev
, service_task
);
2291 hclge_update_speed_duplex(hdev
);
2292 hclge_update_link_status(hdev
);
2293 hclge_update_stats_for_all(hdev
);
2294 hclge_service_complete(hdev
);
2297 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2299 /* If our VFs are assigned we cannot shut down SR-IOV
2300 * without causing issues, so just leave the hardware
2301 * available but disabled
2303 if (pci_vfs_assigned(hdev
->pdev
)) {
2304 dev_warn(&hdev
->pdev
->dev
,
2305 "disabling driver while VFs are assigned\n");
2309 pci_disable_sriov(hdev
->pdev
);
2312 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2314 /* VF handle has no client */
2315 if (!handle
->client
)
2316 return container_of(handle
, struct hclge_vport
, nic
);
2317 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2318 return container_of(handle
, struct hclge_vport
, roce
);
2320 return container_of(handle
, struct hclge_vport
, nic
);
2323 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2324 struct hnae3_vector_info
*vector_info
)
2326 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2327 struct hnae3_vector_info
*vector
= vector_info
;
2328 struct hclge_dev
*hdev
= vport
->back
;
2332 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2334 for (j
= 0; j
< vector_num
; j
++) {
2335 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2336 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2337 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2338 vector
->io_addr
= hdev
->hw
.io_base
+
2339 HCLGE_VECTOR_REG_BASE
+
2340 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2342 HCLGE_VECTOR_VF_OFFSET
;
2343 hdev
->vector_status
[i
] = vport
->vport_id
;
2352 hdev
->num_msi_left
-= alloc
;
2353 hdev
->num_msi_used
+= alloc
;
2358 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2362 for (i
= 0; i
< hdev
->num_msi
; i
++) {
2363 if (hdev
->msix_entries
) {
2364 if (vector
== hdev
->msix_entries
[i
].vector
)
2367 if (vector
== (hdev
->base_msi_vector
+ i
))
2374 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
2376 return HCLGE_RSS_KEY_SIZE
;
2379 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
2381 return HCLGE_RSS_IND_TBL_SIZE
;
2384 static int hclge_get_rss_algo(struct hclge_dev
*hdev
)
2386 struct hclge_rss_config
*req
;
2387 struct hclge_desc desc
;
2391 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
, true);
2393 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2395 dev_err(&hdev
->pdev
->dev
,
2396 "Get link status error, status =%d\n", ret
);
2400 req
= (struct hclge_rss_config
*)desc
.data
;
2401 rss_hash_algo
= (req
->hash_config
& HCLGE_RSS_HASH_ALGO_MASK
);
2403 if (rss_hash_algo
== HCLGE_RSS_HASH_ALGO_TOEPLITZ
)
2404 return ETH_RSS_HASH_TOP
;
2409 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
2410 const u8 hfunc
, const u8
*key
)
2412 struct hclge_rss_config
*req
;
2413 struct hclge_desc desc
;
2418 req
= (struct hclge_rss_config
*)desc
.data
;
2420 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
2421 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
2424 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
2425 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
2427 if (key_offset
== 2)
2429 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
2431 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
2433 memcpy(req
->hash_key
,
2434 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
2436 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2438 dev_err(&hdev
->pdev
->dev
,
2439 "Configure RSS config fail, status = %d\n",
2447 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u32
*indir
)
2449 struct hclge_rss_indirection_table
*req
;
2450 struct hclge_desc desc
;
2454 req
= (struct hclge_rss_indirection_table
*)desc
.data
;
2456 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
2457 hclge_cmd_setup_basic_desc
2458 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
2460 req
->start_table_index
= i
* HCLGE_RSS_CFG_TBL_SIZE
;
2461 req
->rss_set_bitmap
= HCLGE_RSS_SET_BITMAP_MSK
;
2463 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
2464 req
->rss_result
[j
] =
2465 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
2467 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2469 dev_err(&hdev
->pdev
->dev
,
2470 "Configure rss indir table fail,status = %d\n",
2478 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
2479 u16
*tc_size
, u16
*tc_offset
)
2481 struct hclge_rss_tc_mode
*req
;
2482 struct hclge_desc desc
;
2486 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
2487 req
= (struct hclge_rss_tc_mode
*)desc
.data
;
2489 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
2490 hnae_set_bit(req
->rss_tc_mode
[i
], HCLGE_RSS_TC_VALID_B
,
2491 (tc_valid
[i
] & 0x1));
2492 hnae_set_field(req
->rss_tc_mode
[i
], HCLGE_RSS_TC_SIZE_M
,
2493 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
2494 hnae_set_field(req
->rss_tc_mode
[i
], HCLGE_RSS_TC_OFFSET_M
,
2495 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
2498 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2500 dev_err(&hdev
->pdev
->dev
,
2501 "Configure rss tc mode fail, status = %d\n", ret
);
2508 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
2510 #define HCLGE_RSS_INPUT_TUPLE_OTHER 0xf
2511 #define HCLGE_RSS_INPUT_TUPLE_SCTP 0x1f
2512 struct hclge_rss_input_tuple
*req
;
2513 struct hclge_desc desc
;
2516 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
2518 req
= (struct hclge_rss_input_tuple
*)desc
.data
;
2519 req
->ipv4_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2520 req
->ipv4_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2521 req
->ipv4_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
2522 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2523 req
->ipv6_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2524 req
->ipv6_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2525 req
->ipv6_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
2526 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2527 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2529 dev_err(&hdev
->pdev
->dev
,
2530 "Configure rss input fail, status = %d\n", ret
);
2537 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
2540 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2541 struct hclge_dev
*hdev
= vport
->back
;
2544 /* Get hash algorithm */
2546 *hfunc
= hclge_get_rss_algo(hdev
);
2548 /* Get the RSS Key required by the user */
2550 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
2552 /* Get indirect table */
2554 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
2555 indir
[i
] = vport
->rss_indirection_tbl
[i
];
2560 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
2561 const u8
*key
, const u8 hfunc
)
2563 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2564 struct hclge_dev
*hdev
= vport
->back
;
2568 /* Set the RSS Hash Key if specififed by the user */
2570 /* Update the shadow RSS key with user specified qids */
2571 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
2573 if (hfunc
== ETH_RSS_HASH_TOP
||
2574 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
2575 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
2578 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
2583 /* Update the shadow RSS table with user specified qids */
2584 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
2585 vport
->rss_indirection_tbl
[i
] = indir
[i
];
2587 /* Update the hardware */
2588 ret
= hclge_set_rss_indir_table(hdev
, indir
);
2592 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
2594 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2595 struct hclge_dev
*hdev
= vport
->back
;
2597 return hdev
->rss_size_max
;
2600 static int hclge_rss_init_hw(struct hclge_dev
*hdev
)
2602 const u8 hfunc
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
2603 struct hclge_vport
*vport
= hdev
->vport
;
2604 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
2605 u8 rss_key
[HCLGE_RSS_KEY_SIZE
];
2606 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
2607 u16 tc_size
[HCLGE_MAX_TC_NUM
];
2608 u32
*rss_indir
= NULL
;
2609 u16 rss_size
= 0, roundup_size
;
2613 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
2617 /* Get default RSS key */
2618 netdev_rss_key_fill(rss_key
, HCLGE_RSS_KEY_SIZE
);
2620 /* Initialize RSS indirect table for each vport */
2621 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
2622 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++) {
2623 vport
[j
].rss_indirection_tbl
[i
] =
2624 i
% vport
[j
].alloc_rss_size
;
2626 /* vport 0 is for PF */
2630 rss_size
= vport
[j
].alloc_rss_size
;
2631 rss_indir
[i
] = vport
[j
].rss_indirection_tbl
[i
];
2634 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
2639 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
2643 ret
= hclge_set_rss_input_tuple(hdev
);
2647 /* Each TC have the same queue size, and tc_size set to hardware is
2648 * the log2 of roundup power of two of rss_size, the acutal queue
2649 * size is limited by indirection table.
2651 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
2652 dev_err(&hdev
->pdev
->dev
,
2653 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
2658 roundup_size
= roundup_pow_of_two(rss_size
);
2659 roundup_size
= ilog2(roundup_size
);
2661 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
2664 if (!(hdev
->hw_tc_map
& BIT(i
)))
2668 tc_size
[i
] = roundup_size
;
2669 tc_offset
[i
] = rss_size
* i
;
2672 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
2680 int hclge_map_vport_ring_to_vector(struct hclge_vport
*vport
, int vector_id
,
2681 struct hnae3_ring_chain_node
*ring_chain
)
2683 struct hclge_dev
*hdev
= vport
->back
;
2684 struct hclge_ctrl_vector_chain
*req
;
2685 struct hnae3_ring_chain_node
*node
;
2686 struct hclge_desc desc
;
2690 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_ADD_RING_TO_VECTOR
, false);
2692 req
= (struct hclge_ctrl_vector_chain
*)desc
.data
;
2693 req
->int_vector_id
= vector_id
;
2696 for (node
= ring_chain
; node
; node
= node
->next
) {
2697 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_INT_TYPE_M
,
2699 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
2700 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_TQP_ID_M
,
2701 HCLGE_TQP_ID_S
, node
->tqp_index
);
2702 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_INT_GL_IDX_M
,
2704 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
2705 req
->tqp_type_and_id
[i
] = cpu_to_le16(req
->tqp_type_and_id
[i
]);
2706 req
->vfid
= vport
->vport_id
;
2708 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
2709 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
2711 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2713 dev_err(&hdev
->pdev
->dev
,
2714 "Map TQP fail, status is %d.\n",
2720 hclge_cmd_setup_basic_desc(&desc
,
2721 HCLGE_OPC_ADD_RING_TO_VECTOR
,
2723 req
->int_vector_id
= vector_id
;
2728 req
->int_cause_num
= i
;
2730 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2732 dev_err(&hdev
->pdev
->dev
,
2733 "Map TQP fail, status is %d.\n", ret
);
2741 int hclge_map_handle_ring_to_vector(struct hnae3_handle
*handle
,
2743 struct hnae3_ring_chain_node
*ring_chain
)
2745 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2746 struct hclge_dev
*hdev
= vport
->back
;
2749 vector_id
= hclge_get_vector_index(hdev
, vector
);
2750 if (vector_id
< 0) {
2751 dev_err(&hdev
->pdev
->dev
,
2752 "Get vector index fail. ret =%d\n", vector_id
);
2756 return hclge_map_vport_ring_to_vector(vport
, vector_id
, ring_chain
);
2759 static int hclge_unmap_ring_from_vector(
2760 struct hnae3_handle
*handle
, int vector
,
2761 struct hnae3_ring_chain_node
*ring_chain
)
2763 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2764 struct hclge_dev
*hdev
= vport
->back
;
2765 struct hclge_ctrl_vector_chain
*req
;
2766 struct hnae3_ring_chain_node
*node
;
2767 struct hclge_desc desc
;
2771 vector_id
= hclge_get_vector_index(hdev
, vector
);
2772 if (vector_id
< 0) {
2773 dev_err(&handle
->pdev
->dev
,
2774 "Get vector index fail. ret =%d\n", vector_id
);
2778 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_DEL_RING_TO_VECTOR
, false);
2780 req
= (struct hclge_ctrl_vector_chain
*)desc
.data
;
2781 req
->int_vector_id
= vector_id
;
2784 for (node
= ring_chain
; node
; node
= node
->next
) {
2785 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_INT_TYPE_M
,
2787 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
2788 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_TQP_ID_M
,
2789 HCLGE_TQP_ID_S
, node
->tqp_index
);
2790 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_INT_GL_IDX_M
,
2792 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
2794 req
->tqp_type_and_id
[i
] = cpu_to_le16(req
->tqp_type_and_id
[i
]);
2795 req
->vfid
= vport
->vport_id
;
2797 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
2798 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
2800 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2802 dev_err(&hdev
->pdev
->dev
,
2803 "Unmap TQP fail, status is %d.\n",
2808 hclge_cmd_setup_basic_desc(&desc
,
2809 HCLGE_OPC_DEL_RING_TO_VECTOR
,
2811 req
->int_vector_id
= vector_id
;
2816 req
->int_cause_num
= i
;
2818 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2820 dev_err(&hdev
->pdev
->dev
,
2821 "Unmap TQP fail, status is %d.\n", ret
);
2829 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
2830 struct hclge_promisc_param
*param
)
2832 struct hclge_promisc_cfg
*req
;
2833 struct hclge_desc desc
;
2836 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
2838 req
= (struct hclge_promisc_cfg
*)desc
.data
;
2839 req
->vf_id
= param
->vf_id
;
2840 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
2842 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2844 dev_err(&hdev
->pdev
->dev
,
2845 "Set promisc mode fail, status is %d.\n", ret
);
2851 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
2852 bool en_mc
, bool en_bc
, int vport_id
)
2857 memset(param
, 0, sizeof(struct hclge_promisc_param
));
2859 param
->enable
= HCLGE_PROMISC_EN_UC
;
2861 param
->enable
|= HCLGE_PROMISC_EN_MC
;
2863 param
->enable
|= HCLGE_PROMISC_EN_BC
;
2864 param
->vf_id
= vport_id
;
2867 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
2869 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2870 struct hclge_dev
*hdev
= vport
->back
;
2871 struct hclge_promisc_param param
;
2873 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
2874 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
2877 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
2879 struct hclge_desc desc
;
2880 struct hclge_config_mac_mode
*req
=
2881 (struct hclge_config_mac_mode
*)desc
.data
;
2884 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
2885 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
2886 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
2887 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
2888 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
2889 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_1588_TX_B
, 0);
2890 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_1588_RX_B
, 0);
2891 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_APP_LP_B
, 0);
2892 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
2893 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
2894 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
2895 hnae_set_bit(req
->txrx_pad_fcs_loop_en
,
2896 HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
2897 hnae_set_bit(req
->txrx_pad_fcs_loop_en
,
2898 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
2899 hnae_set_bit(req
->txrx_pad_fcs_loop_en
,
2900 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
2901 hnae_set_bit(req
->txrx_pad_fcs_loop_en
,
2902 HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
2904 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2906 dev_err(&hdev
->pdev
->dev
,
2907 "mac enable fail, ret =%d.\n", ret
);
2910 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
2911 int stream_id
, bool enable
)
2913 struct hclge_desc desc
;
2914 struct hclge_cfg_com_tqp_queue
*req
=
2915 (struct hclge_cfg_com_tqp_queue
*)desc
.data
;
2918 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
2919 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
2920 req
->stream_id
= cpu_to_le16(stream_id
);
2921 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
2923 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2925 dev_err(&hdev
->pdev
->dev
,
2926 "Tqp enable fail, status =%d.\n", ret
);
2930 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
2932 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2933 struct hnae3_queue
*queue
;
2934 struct hclge_tqp
*tqp
;
2937 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
2938 queue
= handle
->kinfo
.tqp
[i
];
2939 tqp
= container_of(queue
, struct hclge_tqp
, q
);
2940 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
2944 static int hclge_ae_start(struct hnae3_handle
*handle
)
2946 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2947 struct hclge_dev
*hdev
= vport
->back
;
2948 int i
, queue_id
, ret
;
2950 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
2951 /* todo clear interrupt */
2953 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
2955 dev_warn(&hdev
->pdev
->dev
,
2956 "Get invalid queue id, ignore it\n");
2960 hclge_tqp_enable(hdev
, queue_id
, 0, true);
2963 hclge_cfg_mac_mode(hdev
, true);
2964 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
2965 (void)mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2967 ret
= hclge_mac_start_phy(hdev
);
2971 /* reset tqp stats */
2972 hclge_reset_tqp_stats(handle
);
2977 static void hclge_ae_stop(struct hnae3_handle
*handle
)
2979 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2980 struct hclge_dev
*hdev
= vport
->back
;
2983 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
2985 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
2987 dev_warn(&hdev
->pdev
->dev
,
2988 "Get invalid queue id, ignore it\n");
2992 hclge_tqp_enable(hdev
, queue_id
, 0, false);
2995 hclge_cfg_mac_mode(hdev
, false);
2997 hclge_mac_stop_phy(hdev
);
2999 /* reset tqp stats */
3000 hclge_reset_tqp_stats(handle
);
3003 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3004 u16 cmdq_resp
, u8 resp_code
,
3005 enum hclge_mac_vlan_tbl_opcode op
)
3007 struct hclge_dev
*hdev
= vport
->back
;
3008 int return_status
= -EIO
;
3011 dev_err(&hdev
->pdev
->dev
,
3012 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3017 if (op
== HCLGE_MAC_VLAN_ADD
) {
3018 if ((!resp_code
) || (resp_code
== 1)) {
3020 } else if (resp_code
== 2) {
3021 return_status
= -EIO
;
3022 dev_err(&hdev
->pdev
->dev
,
3023 "add mac addr failed for uc_overflow.\n");
3024 } else if (resp_code
== 3) {
3025 return_status
= -EIO
;
3026 dev_err(&hdev
->pdev
->dev
,
3027 "add mac addr failed for mc_overflow.\n");
3029 dev_err(&hdev
->pdev
->dev
,
3030 "add mac addr failed for undefined, code=%d.\n",
3033 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3036 } else if (resp_code
== 1) {
3037 return_status
= -EIO
;
3038 dev_dbg(&hdev
->pdev
->dev
,
3039 "remove mac addr failed for miss.\n");
3041 dev_err(&hdev
->pdev
->dev
,
3042 "remove mac addr failed for undefined, code=%d.\n",
3045 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3048 } else if (resp_code
== 1) {
3049 return_status
= -EIO
;
3050 dev_dbg(&hdev
->pdev
->dev
,
3051 "lookup mac addr failed for miss.\n");
3053 dev_err(&hdev
->pdev
->dev
,
3054 "lookup mac addr failed for undefined, code=%d.\n",
3058 return_status
= -EIO
;
3059 dev_err(&hdev
->pdev
->dev
,
3060 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3064 return return_status
;
3067 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3072 if (vfid
> 255 || vfid
< 0)
3075 if (vfid
>= 0 && vfid
<= 191) {
3076 word_num
= vfid
/ 32;
3077 bit_num
= vfid
% 32;
3079 desc
[1].data
[word_num
] &= ~(1 << bit_num
);
3081 desc
[1].data
[word_num
] |= (1 << bit_num
);
3083 word_num
= (vfid
- 192) / 32;
3084 bit_num
= vfid
% 32;
3086 desc
[2].data
[word_num
] &= ~(1 << bit_num
);
3088 desc
[2].data
[word_num
] |= (1 << bit_num
);
3094 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3096 #define HCLGE_DESC_NUMBER 3
3097 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3100 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3101 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3102 if (desc
[i
].data
[j
])
3108 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry
*new_req
,
3111 const unsigned char *mac_addr
= addr
;
3112 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3113 (mac_addr
[0]) | (mac_addr
[1] << 8);
3114 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3116 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3117 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3120 u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3123 u16 high_val
= addr
[1] | (addr
[0] << 8);
3124 struct hclge_dev
*hdev
= vport
->back
;
3125 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3126 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3131 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3132 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3135 struct hclge_mta_filter_mode
*req
;
3136 struct hclge_desc desc
;
3139 req
= (struct hclge_mta_filter_mode
*)desc
.data
;
3140 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3142 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3144 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3145 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3147 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3149 dev_err(&hdev
->pdev
->dev
,
3150 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3158 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3162 struct hclge_cfg_func_mta_filter
*req
;
3163 struct hclge_desc desc
;
3166 req
= (struct hclge_cfg_func_mta_filter
*)desc
.data
;
3167 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3169 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3171 req
->function_id
= func_id
;
3173 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3175 dev_err(&hdev
->pdev
->dev
,
3176 "Config func_id enable failed for cmd_send, ret =%d.\n",
3184 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
3188 struct hclge_dev
*hdev
= vport
->back
;
3189 struct hclge_cfg_func_mta_item
*req
;
3190 struct hclge_desc desc
;
3193 req
= (struct hclge_cfg_func_mta_item
*)desc
.data
;
3194 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
3195 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
3197 hnae_set_field(req
->item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
3198 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
3199 req
->item_idx
= cpu_to_le16(req
->item_idx
);
3201 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3203 dev_err(&hdev
->pdev
->dev
,
3204 "Config mta table item failed for cmd_send, ret =%d.\n",
3212 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
3213 struct hclge_mac_vlan_tbl_entry
*req
)
3215 struct hclge_dev
*hdev
= vport
->back
;
3216 struct hclge_desc desc
;
3220 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
3222 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry
));
3224 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3226 dev_err(&hdev
->pdev
->dev
,
3227 "del mac addr failed for cmd_send, ret =%d.\n",
3231 resp_code
= (desc
.data
[0] >> 8) & 0xff;
3233 return hclge_get_mac_vlan_cmd_status(vport
, desc
.retval
, resp_code
,
3234 HCLGE_MAC_VLAN_REMOVE
);
3237 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
3238 struct hclge_mac_vlan_tbl_entry
*req
,
3239 struct hclge_desc
*desc
,
3242 struct hclge_dev
*hdev
= vport
->back
;
3246 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
3248 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3249 memcpy(desc
[0].data
,
3251 sizeof(struct hclge_mac_vlan_tbl_entry
));
3252 hclge_cmd_setup_basic_desc(&desc
[1],
3253 HCLGE_OPC_MAC_VLAN_ADD
,
3255 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3256 hclge_cmd_setup_basic_desc(&desc
[2],
3257 HCLGE_OPC_MAC_VLAN_ADD
,
3259 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
3261 memcpy(desc
[0].data
,
3263 sizeof(struct hclge_mac_vlan_tbl_entry
));
3264 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
3267 dev_err(&hdev
->pdev
->dev
,
3268 "lookup mac addr failed for cmd_send, ret =%d.\n",
3272 resp_code
= (desc
[0].data
[0] >> 8) & 0xff;
3274 return hclge_get_mac_vlan_cmd_status(vport
, desc
[0].retval
, resp_code
,
3275 HCLGE_MAC_VLAN_LKUP
);
3278 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
3279 struct hclge_mac_vlan_tbl_entry
*req
,
3280 struct hclge_desc
*mc_desc
)
3282 struct hclge_dev
*hdev
= vport
->back
;
3288 struct hclge_desc desc
;
3290 hclge_cmd_setup_basic_desc(&desc
,
3291 HCLGE_OPC_MAC_VLAN_ADD
,
3293 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry
));
3294 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3295 resp_code
= (desc
.data
[0] >> 8) & 0xff;
3296 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, desc
.retval
,
3298 HCLGE_MAC_VLAN_ADD
);
3300 mc_desc
[0].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_WR
);
3301 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3302 mc_desc
[1].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_WR
);
3303 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3304 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_WR
);
3305 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
3306 memcpy(mc_desc
[0].data
, req
,
3307 sizeof(struct hclge_mac_vlan_tbl_entry
));
3308 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
3309 resp_code
= (mc_desc
[0].data
[0] >> 8) & 0xff;
3310 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
,
3313 HCLGE_MAC_VLAN_ADD
);
3317 dev_err(&hdev
->pdev
->dev
,
3318 "add mac addr failed for cmd_send, ret =%d.\n",
3326 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
3327 const unsigned char *addr
)
3329 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3331 return hclge_add_uc_addr_common(vport
, addr
);
3334 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
3335 const unsigned char *addr
)
3337 struct hclge_dev
*hdev
= vport
->back
;
3338 struct hclge_mac_vlan_tbl_entry req
;
3339 enum hclge_cmd_status status
;
3341 /* mac addr check */
3342 if (is_zero_ether_addr(addr
) ||
3343 is_broadcast_ether_addr(addr
) ||
3344 is_multicast_ether_addr(addr
)) {
3345 dev_err(&hdev
->pdev
->dev
,
3346 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3348 is_zero_ether_addr(addr
),
3349 is_broadcast_ether_addr(addr
),
3350 is_multicast_ether_addr(addr
));
3354 memset(&req
, 0, sizeof(req
));
3355 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3356 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3357 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
3358 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3359 hnae_set_bit(req
.egress_port
,
3360 HCLGE_MAC_EPORT_SW_EN_B
, 0);
3361 hnae_set_bit(req
.egress_port
,
3362 HCLGE_MAC_EPORT_TYPE_B
, 0);
3363 hnae_set_field(req
.egress_port
, HCLGE_MAC_EPORT_VFID_M
,
3364 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
3365 hnae_set_field(req
.egress_port
, HCLGE_MAC_EPORT_PFID_M
,
3366 HCLGE_MAC_EPORT_PFID_S
, 0);
3367 req
.egress_port
= cpu_to_le16(req
.egress_port
);
3369 hclge_prepare_mac_addr(&req
, addr
);
3371 status
= hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
3376 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
3377 const unsigned char *addr
)
3379 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3381 return hclge_rm_uc_addr_common(vport
, addr
);
3384 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
3385 const unsigned char *addr
)
3387 struct hclge_dev
*hdev
= vport
->back
;
3388 struct hclge_mac_vlan_tbl_entry req
;
3389 enum hclge_cmd_status status
;
3391 /* mac addr check */
3392 if (is_zero_ether_addr(addr
) ||
3393 is_broadcast_ether_addr(addr
) ||
3394 is_multicast_ether_addr(addr
)) {
3395 dev_dbg(&hdev
->pdev
->dev
,
3396 "Remove mac err! invalid mac:%pM.\n",
3401 memset(&req
, 0, sizeof(req
));
3402 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3403 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3404 hclge_prepare_mac_addr(&req
, addr
);
3405 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
3410 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
3411 const unsigned char *addr
)
3413 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3415 return hclge_add_mc_addr_common(vport
, addr
);
3418 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
3419 const unsigned char *addr
)
3421 struct hclge_dev
*hdev
= vport
->back
;
3422 struct hclge_mac_vlan_tbl_entry req
;
3423 struct hclge_desc desc
[3];
3427 /* mac addr check */
3428 if (!is_multicast_ether_addr(addr
)) {
3429 dev_err(&hdev
->pdev
->dev
,
3430 "Add mc mac err! invalid mac:%pM.\n",
3434 memset(&req
, 0, sizeof(req
));
3435 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3436 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3437 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
3438 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3439 hclge_prepare_mac_addr(&req
, addr
);
3440 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
3442 /* This mac addr exist, update VFID for it */
3443 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
3444 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
3446 /* This mac addr do not exist, add new entry for it */
3447 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
3448 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
3449 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
3450 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
3451 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
3454 /* Set MTA table for this MAC address */
3455 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
3456 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
3461 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
3462 const unsigned char *addr
)
3464 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3466 return hclge_rm_mc_addr_common(vport
, addr
);
3469 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
3470 const unsigned char *addr
)
3472 struct hclge_dev
*hdev
= vport
->back
;
3473 struct hclge_mac_vlan_tbl_entry req
;
3474 enum hclge_cmd_status status
;
3475 struct hclge_desc desc
[3];
3478 /* mac addr check */
3479 if (!is_multicast_ether_addr(addr
)) {
3480 dev_dbg(&hdev
->pdev
->dev
,
3481 "Remove mc mac err! invalid mac:%pM.\n",
3486 memset(&req
, 0, sizeof(req
));
3487 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3488 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3489 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
3490 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3491 hclge_prepare_mac_addr(&req
, addr
);
3492 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
3494 /* This mac addr exist, remove this handle's VFID for it */
3495 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
3497 if (hclge_is_all_function_id_zero(desc
))
3498 /* All the vfid is zero, so need to delete this entry */
3499 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
3501 /* Not all the vfid is zero, update the vfid */
3502 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
3505 /* This mac addr do not exist, can't delete it */
3506 dev_err(&hdev
->pdev
->dev
,
3507 "Rm multicast mac addr failed, ret = %d.\n",
3512 /* Set MTB table for this MAC address */
3513 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
3514 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
3519 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
3521 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3522 struct hclge_dev
*hdev
= vport
->back
;
3524 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
3527 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
)
3529 const unsigned char *new_addr
= (const unsigned char *)p
;
3530 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3531 struct hclge_dev
*hdev
= vport
->back
;
3533 /* mac addr check */
3534 if (is_zero_ether_addr(new_addr
) ||
3535 is_broadcast_ether_addr(new_addr
) ||
3536 is_multicast_ether_addr(new_addr
)) {
3537 dev_err(&hdev
->pdev
->dev
,
3538 "Change uc mac err! invalid mac:%p.\n",
3543 hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
);
3545 if (!hclge_add_uc_addr(handle
, new_addr
)) {
3546 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
3553 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
3556 struct hclge_vlan_filter_ctrl
*req
;
3557 struct hclge_desc desc
;
3560 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
3562 req
= (struct hclge_vlan_filter_ctrl
*)desc
.data
;
3563 req
->vlan_type
= vlan_type
;
3564 req
->vlan_fe
= filter_en
;
3566 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3568 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
3576 int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
3577 bool is_kill
, u16 vlan
, u8 qos
, __be16 proto
)
3579 #define HCLGE_MAX_VF_BYTES 16
3580 struct hclge_vlan_filter_vf_cfg
*req0
;
3581 struct hclge_vlan_filter_vf_cfg
*req1
;
3582 struct hclge_desc desc
[2];
3587 hclge_cmd_setup_basic_desc(&desc
[0],
3588 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
3589 hclge_cmd_setup_basic_desc(&desc
[1],
3590 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
3592 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3594 vf_byte_off
= vfid
/ 8;
3595 vf_byte_val
= 1 << (vfid
% 8);
3597 req0
= (struct hclge_vlan_filter_vf_cfg
*)desc
[0].data
;
3598 req1
= (struct hclge_vlan_filter_vf_cfg
*)desc
[1].data
;
3600 req0
->vlan_id
= vlan
;
3601 req0
->vlan_cfg
= is_kill
;
3603 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
3604 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
3606 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
3608 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
3610 dev_err(&hdev
->pdev
->dev
,
3611 "Send vf vlan command fail, ret =%d.\n",
3617 if (!req0
->resp_code
|| req0
->resp_code
== 1)
3620 dev_err(&hdev
->pdev
->dev
,
3621 "Add vf vlan filter fail, ret =%d.\n",
3624 if (!req0
->resp_code
)
3627 dev_err(&hdev
->pdev
->dev
,
3628 "Kill vf vlan filter fail, ret =%d.\n",
3635 static int hclge_set_port_vlan_filter(struct hnae3_handle
*handle
,
3636 __be16 proto
, u16 vlan_id
,
3639 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3640 struct hclge_dev
*hdev
= vport
->back
;
3641 struct hclge_vlan_filter_pf_cfg
*req
;
3642 struct hclge_desc desc
;
3643 u8 vlan_offset_byte_val
;
3644 u8 vlan_offset_byte
;
3648 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
3650 vlan_offset_160
= vlan_id
/ 160;
3651 vlan_offset_byte
= (vlan_id
% 160) / 8;
3652 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
3654 req
= (struct hclge_vlan_filter_pf_cfg
*)desc
.data
;
3655 req
->vlan_offset
= vlan_offset_160
;
3656 req
->vlan_cfg
= is_kill
;
3657 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
3659 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3661 dev_err(&hdev
->pdev
->dev
,
3662 "port vlan command, send fail, ret =%d.\n",
3667 ret
= hclge_set_vf_vlan_common(hdev
, 0, is_kill
, vlan_id
, 0, proto
);
3669 dev_err(&hdev
->pdev
->dev
,
3670 "Set pf vlan filter config fail, ret =%d.\n",
3678 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
3679 u16 vlan
, u8 qos
, __be16 proto
)
3681 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3682 struct hclge_dev
*hdev
= vport
->back
;
3684 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
3686 if (proto
!= htons(ETH_P_8021Q
))
3687 return -EPROTONOSUPPORT
;
3689 return hclge_set_vf_vlan_common(hdev
, vfid
, false, vlan
, qos
, proto
);
3692 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
3694 #define HCLGE_VLAN_TYPE_VF_TABLE 0
3695 #define HCLGE_VLAN_TYPE_PORT_TABLE 1
3696 struct hnae3_handle
*handle
;
3699 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_VLAN_TYPE_VF_TABLE
,
3704 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_VLAN_TYPE_PORT_TABLE
,
3709 handle
= &hdev
->vport
[0].nic
;
3710 return hclge_set_port_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
3713 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
3715 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3716 struct hclge_config_max_frm_size
*req
;
3717 struct hclge_dev
*hdev
= vport
->back
;
3718 struct hclge_desc desc
;
3721 if ((new_mtu
< HCLGE_MAC_MIN_MTU
) || (new_mtu
> HCLGE_MAC_MAX_MTU
))
3724 hdev
->mps
= new_mtu
;
3725 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
3727 req
= (struct hclge_config_max_frm_size
*)desc
.data
;
3728 req
->max_frm_size
= cpu_to_le16(new_mtu
);
3730 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3732 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
3739 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
3742 struct hclge_reset_tqp_queue
*req
;
3743 struct hclge_desc desc
;
3746 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
3748 req
= (struct hclge_reset_tqp_queue
*)desc
.data
;
3749 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
3750 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
3752 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3754 dev_err(&hdev
->pdev
->dev
,
3755 "Send tqp reset cmd error, status =%d\n", ret
);
3762 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
3764 struct hclge_reset_tqp_queue
*req
;
3765 struct hclge_desc desc
;
3768 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
3770 req
= (struct hclge_reset_tqp_queue
*)desc
.data
;
3771 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
3773 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3775 dev_err(&hdev
->pdev
->dev
,
3776 "Get reset status error, status =%d\n", ret
);
3780 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
3783 static void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
3785 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3786 struct hclge_dev
*hdev
= vport
->back
;
3787 int reset_try_times
= 0;
3791 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
3793 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
3797 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, true);
3799 dev_warn(&hdev
->pdev
->dev
,
3800 "Send reset tqp cmd fail, ret = %d\n", ret
);
3804 reset_try_times
= 0;
3805 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
3806 /* Wait for tqp hw reset */
3808 reset_status
= hclge_get_reset_status(hdev
, queue_id
);
3813 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
3814 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
3818 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, false);
3820 dev_warn(&hdev
->pdev
->dev
,
3821 "Deassert the soft reset fail, ret = %d\n", ret
);
3826 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
3828 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3829 struct hclge_dev
*hdev
= vport
->back
;
3831 return hdev
->fw_version
;
3834 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
3835 u32
*rx_en
, u32
*tx_en
)
3837 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3838 struct hclge_dev
*hdev
= vport
->back
;
3840 *auto_neg
= hclge_get_autoneg(handle
);
3842 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
3848 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
3851 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
3854 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
3863 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
3864 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
3866 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3867 struct hclge_dev
*hdev
= vport
->back
;
3870 *speed
= hdev
->hw
.mac
.speed
;
3872 *duplex
= hdev
->hw
.mac
.duplex
;
3874 *auto_neg
= hdev
->hw
.mac
.autoneg
;
3877 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
3879 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3880 struct hclge_dev
*hdev
= vport
->back
;
3883 *media_type
= hdev
->hw
.mac
.media_type
;
3886 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
3887 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
3889 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3890 struct hclge_dev
*hdev
= vport
->back
;
3891 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
3892 int mdix_ctrl
, mdix
, retval
, is_resolved
;
3895 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
3896 *tp_mdix
= ETH_TP_MDI_INVALID
;
3900 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
3902 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
3903 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
3904 HCLGE_PHY_MDIX_CTRL_S
);
3906 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
3907 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
3908 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
3910 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
3912 switch (mdix_ctrl
) {
3914 *tp_mdix_ctrl
= ETH_TP_MDI
;
3917 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
3920 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
3923 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
3928 *tp_mdix
= ETH_TP_MDI_INVALID
;
3930 *tp_mdix
= ETH_TP_MDI_X
;
3932 *tp_mdix
= ETH_TP_MDI
;
3935 static int hclge_init_client_instance(struct hnae3_client
*client
,
3936 struct hnae3_ae_dev
*ae_dev
)
3938 struct hclge_dev
*hdev
= ae_dev
->priv
;
3939 struct hclge_vport
*vport
;
3942 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3943 vport
= &hdev
->vport
[i
];
3945 switch (client
->type
) {
3946 case HNAE3_CLIENT_KNIC
:
3948 hdev
->nic_client
= client
;
3949 vport
->nic
.client
= client
;
3950 ret
= client
->ops
->init_instance(&vport
->nic
);
3954 if (hdev
->roce_client
&&
3955 hnae3_dev_roce_supported(hdev
)) {
3956 struct hnae3_client
*rc
= hdev
->roce_client
;
3958 ret
= hclge_init_roce_base_info(vport
);
3962 ret
= rc
->ops
->init_instance(&vport
->roce
);
3968 case HNAE3_CLIENT_UNIC
:
3969 hdev
->nic_client
= client
;
3970 vport
->nic
.client
= client
;
3972 ret
= client
->ops
->init_instance(&vport
->nic
);
3977 case HNAE3_CLIENT_ROCE
:
3978 if (hnae3_dev_roce_supported(hdev
)) {
3979 hdev
->roce_client
= client
;
3980 vport
->roce
.client
= client
;
3983 if (hdev
->roce_client
) {
3984 ret
= hclge_init_roce_base_info(vport
);
3988 ret
= client
->ops
->init_instance(&vport
->roce
);
4000 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
4001 struct hnae3_ae_dev
*ae_dev
)
4003 struct hclge_dev
*hdev
= ae_dev
->priv
;
4004 struct hclge_vport
*vport
;
4007 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4008 vport
= &hdev
->vport
[i
];
4009 if (hdev
->roce_client
)
4010 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
4012 if (client
->type
== HNAE3_CLIENT_ROCE
)
4014 if (client
->ops
->uninit_instance
)
4015 client
->ops
->uninit_instance(&vport
->nic
, 0);
4019 static int hclge_pci_init(struct hclge_dev
*hdev
)
4021 struct pci_dev
*pdev
= hdev
->pdev
;
4022 struct hclge_hw
*hw
;
4025 ret
= pci_enable_device(pdev
);
4027 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
4028 goto err_no_drvdata
;
4031 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
4033 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
4036 "can't set consistent PCI DMA");
4037 goto err_disable_device
;
4039 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
4042 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
4044 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
4045 goto err_disable_device
;
4048 pci_set_master(pdev
);
4051 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
4053 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
4055 goto err_clr_master
;
4060 pci_clear_master(pdev
);
4061 pci_release_regions(pdev
);
4063 pci_disable_device(pdev
);
4065 pci_set_drvdata(pdev
, NULL
);
4070 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
4072 struct pci_dev
*pdev
= hdev
->pdev
;
4074 if (hdev
->flag
& HCLGE_FLAG_USE_MSIX
) {
4075 pci_disable_msix(pdev
);
4076 devm_kfree(&pdev
->dev
, hdev
->msix_entries
);
4077 hdev
->msix_entries
= NULL
;
4079 pci_disable_msi(pdev
);
4082 pci_clear_master(pdev
);
4083 pci_release_mem_regions(pdev
);
4084 pci_disable_device(pdev
);
4087 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
4089 struct pci_dev
*pdev
= ae_dev
->pdev
;
4090 struct hclge_dev
*hdev
;
4093 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
4099 hdev
->flag
|= HCLGE_FLAG_USE_MSIX
;
4101 hdev
->ae_dev
= ae_dev
;
4102 ae_dev
->priv
= hdev
;
4104 ret
= hclge_pci_init(hdev
);
4106 dev_err(&pdev
->dev
, "PCI init failed\n");
4110 /* Command queue initialize */
4111 ret
= hclge_cmd_init(hdev
);
4115 ret
= hclge_get_cap(hdev
);
4117 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
4122 ret
= hclge_configure(hdev
);
4124 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
4128 if (hdev
->flag
& HCLGE_FLAG_USE_MSIX
)
4129 ret
= hclge_init_msix(hdev
);
4131 ret
= hclge_init_msi(hdev
);
4133 dev_err(&pdev
->dev
, "Init msix/msi error, ret = %d.\n", ret
);
4137 ret
= hclge_alloc_tqps(hdev
);
4139 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
4143 ret
= hclge_alloc_vport(hdev
);
4145 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
4149 ret
= hclge_mac_init(hdev
);
4151 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
4154 ret
= hclge_buffer_alloc(hdev
);
4156 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
4160 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
4162 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
4166 ret
= hclge_init_vlan_config(hdev
);
4168 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
4172 ret
= hclge_tm_schd_init(hdev
);
4174 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
4178 ret
= hclge_rss_init_hw(hdev
);
4180 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
4184 setup_timer(&hdev
->service_timer
, hclge_service_timer
,
4185 (unsigned long)hdev
);
4186 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
4188 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
4189 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
4191 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
4195 pci_release_regions(pdev
);
4197 pci_set_drvdata(pdev
, NULL
);
4202 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
4204 struct hclge_dev
*hdev
= ae_dev
->priv
;
4205 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
4207 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
4209 if (IS_ENABLED(CONFIG_PCI_IOV
))
4210 hclge_disable_sriov(hdev
);
4212 if (hdev
->service_timer
.data
)
4213 del_timer_sync(&hdev
->service_timer
);
4214 if (hdev
->service_task
.func
)
4215 cancel_work_sync(&hdev
->service_task
);
4218 mdiobus_unregister(mac
->mdio_bus
);
4220 hclge_destroy_cmd_queue(&hdev
->hw
);
4221 hclge_pci_uninit(hdev
);
4222 ae_dev
->priv
= NULL
;
4225 static const struct hnae3_ae_ops hclge_ops
= {
4226 .init_ae_dev
= hclge_init_ae_dev
,
4227 .uninit_ae_dev
= hclge_uninit_ae_dev
,
4228 .init_client_instance
= hclge_init_client_instance
,
4229 .uninit_client_instance
= hclge_uninit_client_instance
,
4230 .map_ring_to_vector
= hclge_map_handle_ring_to_vector
,
4231 .unmap_ring_from_vector
= hclge_unmap_ring_from_vector
,
4232 .get_vector
= hclge_get_vector
,
4233 .set_promisc_mode
= hclge_set_promisc_mode
,
4234 .start
= hclge_ae_start
,
4235 .stop
= hclge_ae_stop
,
4236 .get_status
= hclge_get_status
,
4237 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
4238 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
4239 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
4240 .get_media_type
= hclge_get_media_type
,
4241 .get_rss_key_size
= hclge_get_rss_key_size
,
4242 .get_rss_indir_size
= hclge_get_rss_indir_size
,
4243 .get_rss
= hclge_get_rss
,
4244 .set_rss
= hclge_set_rss
,
4245 .get_tc_size
= hclge_get_tc_size
,
4246 .get_mac_addr
= hclge_get_mac_addr
,
4247 .set_mac_addr
= hclge_set_mac_addr
,
4248 .add_uc_addr
= hclge_add_uc_addr
,
4249 .rm_uc_addr
= hclge_rm_uc_addr
,
4250 .add_mc_addr
= hclge_add_mc_addr
,
4251 .rm_mc_addr
= hclge_rm_mc_addr
,
4252 .set_autoneg
= hclge_set_autoneg
,
4253 .get_autoneg
= hclge_get_autoneg
,
4254 .get_pauseparam
= hclge_get_pauseparam
,
4255 .set_mtu
= hclge_set_mtu
,
4256 .reset_queue
= hclge_reset_tqp
,
4257 .get_stats
= hclge_get_stats
,
4258 .update_stats
= hclge_update_stats
,
4259 .get_strings
= hclge_get_strings
,
4260 .get_sset_count
= hclge_get_sset_count
,
4261 .get_fw_version
= hclge_get_fw_version
,
4262 .get_mdix_mode
= hclge_get_mdix_mode
,
4263 .set_vlan_filter
= hclge_set_port_vlan_filter
,
4264 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
4267 static struct hnae3_ae_algo ae_algo
= {
4270 .pdev_id_table
= ae_algo_pci_tbl
,
4273 static int hclge_init(void)
4275 pr_info("%s is initializing\n", HCLGE_NAME
);
4277 return hnae3_register_ae_algo(&ae_algo
);
4280 static void hclge_exit(void)
4282 hnae3_unregister_ae_algo(&ae_algo
);
4284 module_init(hclge_init
);
4285 module_exit(hclge_exit
);
4287 MODULE_LICENSE("GPL");
4288 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4289 MODULE_DESCRIPTION("HCLGE Driver");
4290 MODULE_VERSION(HCLGE_MOD_VERSION
);