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net: hns3: add ethtool related offload command
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <net/rtnetlink.h>
21 #include "hclge_cmd.h"
22 #include "hclge_dcb.h"
23 #include "hclge_main.h"
24 #include "hclge_mbx.h"
25 #include "hclge_mdio.h"
26 #include "hclge_tm.h"
27 #include "hnae3.h"
28
29 #define HCLGE_NAME "hclge"
30 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
31 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
32 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
33 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
34
35 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
36 enum hclge_mta_dmac_sel_type mta_mac_sel,
37 bool enable);
38 static int hclge_init_vlan_config(struct hclge_dev *hdev);
39 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
40
41 static struct hnae3_ae_algo ae_algo;
42
43 static const struct pci_device_id ae_algo_pci_tbl[] = {
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
51 /* required last entry */
52 {0, }
53 };
54
55 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
56 "Mac Loopback test",
57 "Serdes Loopback test",
58 "Phy Loopback test"
59 };
60
61 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
62 {"igu_rx_oversize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
64 {"igu_rx_undersize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
66 {"igu_rx_out_all_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
68 {"igu_rx_uni_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
70 {"igu_rx_multi_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
72 {"igu_rx_broad_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
74 {"egu_tx_out_all_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
76 {"egu_tx_uni_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
78 {"egu_tx_multi_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
80 {"egu_tx_broad_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
82 {"ssu_ppp_mac_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
84 {"ssu_ppp_host_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
86 {"ppp_ssu_mac_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
88 {"ppp_ssu_host_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
90 {"ssu_tx_in_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
92 {"ssu_tx_out_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
94 {"ssu_rx_in_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
96 {"ssu_rx_out_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
98 };
99
100 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
101 {"igu_rx_err_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
103 {"igu_rx_no_eof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
105 {"igu_rx_no_sof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
107 {"egu_tx_1588_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
109 {"ssu_full_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
111 {"ssu_part_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
113 {"ppp_key_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
115 {"ppp_rlt_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
117 {"ssu_key_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
119 {"pkt_curr_buf_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
121 {"qcn_fb_rcv_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
123 {"qcn_fb_drop_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
125 {"qcn_fb_invaild_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
127 {"rx_packet_tc0_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
129 {"rx_packet_tc1_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
131 {"rx_packet_tc2_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
133 {"rx_packet_tc3_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
135 {"rx_packet_tc4_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
137 {"rx_packet_tc5_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
139 {"rx_packet_tc6_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
141 {"rx_packet_tc7_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
143 {"rx_packet_tc0_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
145 {"rx_packet_tc1_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
147 {"rx_packet_tc2_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
149 {"rx_packet_tc3_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
151 {"rx_packet_tc4_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
153 {"rx_packet_tc5_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
155 {"rx_packet_tc6_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
157 {"rx_packet_tc7_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
159 {"tx_packet_tc0_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
161 {"tx_packet_tc1_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
163 {"tx_packet_tc2_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
165 {"tx_packet_tc3_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
167 {"tx_packet_tc4_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
169 {"tx_packet_tc5_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
171 {"tx_packet_tc6_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
173 {"tx_packet_tc7_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
175 {"tx_packet_tc0_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
177 {"tx_packet_tc1_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
179 {"tx_packet_tc2_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
181 {"tx_packet_tc3_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
183 {"tx_packet_tc4_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
185 {"tx_packet_tc5_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
187 {"tx_packet_tc6_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
189 {"tx_packet_tc7_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
191 {"pkt_curr_buf_tc0_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
193 {"pkt_curr_buf_tc1_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
195 {"pkt_curr_buf_tc2_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
197 {"pkt_curr_buf_tc3_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
199 {"pkt_curr_buf_tc4_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
201 {"pkt_curr_buf_tc5_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
203 {"pkt_curr_buf_tc6_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
205 {"pkt_curr_buf_tc7_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
207 {"mb_uncopy_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
209 {"lo_pri_unicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
211 {"hi_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
213 {"lo_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
215 {"rx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
217 {"tx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
219 {"nic_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
221 {"roc_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
223 };
224
225 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
226 {"mac_tx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
228 {"mac_rx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
230 {"mac_tx_pfc_pri0_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
232 {"mac_tx_pfc_pri1_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
234 {"mac_tx_pfc_pri2_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
236 {"mac_tx_pfc_pri3_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
238 {"mac_tx_pfc_pri4_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
240 {"mac_tx_pfc_pri5_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
242 {"mac_tx_pfc_pri6_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
244 {"mac_tx_pfc_pri7_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
246 {"mac_rx_pfc_pri0_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
248 {"mac_rx_pfc_pri1_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
250 {"mac_rx_pfc_pri2_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
252 {"mac_rx_pfc_pri3_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
254 {"mac_rx_pfc_pri4_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
256 {"mac_rx_pfc_pri5_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
258 {"mac_rx_pfc_pri6_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
260 {"mac_rx_pfc_pri7_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
262 {"mac_tx_total_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
264 {"mac_tx_total_oct_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
266 {"mac_tx_good_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
268 {"mac_tx_bad_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
270 {"mac_tx_good_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
272 {"mac_tx_bad_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
274 {"mac_tx_uni_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
276 {"mac_tx_multi_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
278 {"mac_tx_broad_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
280 {"mac_tx_undersize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
282 {"mac_tx_overrsize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
284 {"mac_tx_64_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
286 {"mac_tx_65_127_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
288 {"mac_tx_128_255_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
290 {"mac_tx_256_511_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
292 {"mac_tx_512_1023_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
294 {"mac_tx_1024_1518_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
296 {"mac_tx_1519_max_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
298 {"mac_rx_total_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
300 {"mac_rx_total_oct_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
302 {"mac_rx_good_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
304 {"mac_rx_bad_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
306 {"mac_rx_good_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
308 {"mac_rx_bad_oct_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
310 {"mac_rx_uni_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
312 {"mac_rx_multi_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
314 {"mac_rx_broad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
316 {"mac_rx_undersize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
318 {"mac_rx_overrsize_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
320 {"mac_rx_64_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
322 {"mac_rx_65_127_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
324 {"mac_rx_128_255_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
326 {"mac_rx_256_511_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
328 {"mac_rx_512_1023_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
330 {"mac_rx_1024_1518_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
332 {"mac_rx_1519_max_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
334
335 {"mac_trans_fragment_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
337 {"mac_trans_undermin_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
339 {"mac_trans_jabber_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
341 {"mac_trans_err_all_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
343 {"mac_trans_from_app_good_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
345 {"mac_trans_from_app_bad_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
347 {"mac_rcv_fragment_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
349 {"mac_rcv_undermin_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
351 {"mac_rcv_jabber_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
353 {"mac_rcv_fcs_err_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
355 {"mac_rcv_send_app_good_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
357 {"mac_rcv_send_app_bad_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
359 };
360
361 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
362 {
363 #define HCLGE_64_BIT_CMD_NUM 5
364 #define HCLGE_64_BIT_RTN_DATANUM 4
365 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
366 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
367 __le64 *desc_data;
368 int i, k, n;
369 int ret;
370
371 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
372 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
373 if (ret) {
374 dev_err(&hdev->pdev->dev,
375 "Get 64 bit pkt stats fail, status = %d.\n", ret);
376 return ret;
377 }
378
379 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
380 if (unlikely(i == 0)) {
381 desc_data = (__le64 *)(&desc[i].data[0]);
382 n = HCLGE_64_BIT_RTN_DATANUM - 1;
383 } else {
384 desc_data = (__le64 *)(&desc[i]);
385 n = HCLGE_64_BIT_RTN_DATANUM;
386 }
387 for (k = 0; k < n; k++) {
388 *data++ += le64_to_cpu(*desc_data);
389 desc_data++;
390 }
391 }
392
393 return 0;
394 }
395
396 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
397 {
398 stats->pkt_curr_buf_cnt = 0;
399 stats->pkt_curr_buf_tc0_cnt = 0;
400 stats->pkt_curr_buf_tc1_cnt = 0;
401 stats->pkt_curr_buf_tc2_cnt = 0;
402 stats->pkt_curr_buf_tc3_cnt = 0;
403 stats->pkt_curr_buf_tc4_cnt = 0;
404 stats->pkt_curr_buf_tc5_cnt = 0;
405 stats->pkt_curr_buf_tc6_cnt = 0;
406 stats->pkt_curr_buf_tc7_cnt = 0;
407 }
408
409 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
410 {
411 #define HCLGE_32_BIT_CMD_NUM 8
412 #define HCLGE_32_BIT_RTN_DATANUM 8
413
414 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
415 struct hclge_32_bit_stats *all_32_bit_stats;
416 __le32 *desc_data;
417 int i, k, n;
418 u64 *data;
419 int ret;
420
421 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
422 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
423
424 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
425 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
426 if (ret) {
427 dev_err(&hdev->pdev->dev,
428 "Get 32 bit pkt stats fail, status = %d.\n", ret);
429
430 return ret;
431 }
432
433 hclge_reset_partial_32bit_counter(all_32_bit_stats);
434 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
435 if (unlikely(i == 0)) {
436 __le16 *desc_data_16bit;
437
438 all_32_bit_stats->igu_rx_err_pkt +=
439 le32_to_cpu(desc[i].data[0]);
440
441 desc_data_16bit = (__le16 *)&desc[i].data[1];
442 all_32_bit_stats->igu_rx_no_eof_pkt +=
443 le16_to_cpu(*desc_data_16bit);
444
445 desc_data_16bit++;
446 all_32_bit_stats->igu_rx_no_sof_pkt +=
447 le16_to_cpu(*desc_data_16bit);
448
449 desc_data = &desc[i].data[2];
450 n = HCLGE_32_BIT_RTN_DATANUM - 4;
451 } else {
452 desc_data = (__le32 *)&desc[i];
453 n = HCLGE_32_BIT_RTN_DATANUM;
454 }
455 for (k = 0; k < n; k++) {
456 *data++ += le32_to_cpu(*desc_data);
457 desc_data++;
458 }
459 }
460
461 return 0;
462 }
463
464 static int hclge_mac_update_stats(struct hclge_dev *hdev)
465 {
466 #define HCLGE_MAC_CMD_NUM 17
467 #define HCLGE_RTN_DATA_NUM 4
468
469 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
470 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
471 __le64 *desc_data;
472 int i, k, n;
473 int ret;
474
475 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
476 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
477 if (ret) {
478 dev_err(&hdev->pdev->dev,
479 "Get MAC pkt stats fail, status = %d.\n", ret);
480
481 return ret;
482 }
483
484 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
485 if (unlikely(i == 0)) {
486 desc_data = (__le64 *)(&desc[i].data[0]);
487 n = HCLGE_RTN_DATA_NUM - 2;
488 } else {
489 desc_data = (__le64 *)(&desc[i]);
490 n = HCLGE_RTN_DATA_NUM;
491 }
492 for (k = 0; k < n; k++) {
493 *data++ += le64_to_cpu(*desc_data);
494 desc_data++;
495 }
496 }
497
498 return 0;
499 }
500
501 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
502 {
503 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
504 struct hclge_vport *vport = hclge_get_vport(handle);
505 struct hclge_dev *hdev = vport->back;
506 struct hnae3_queue *queue;
507 struct hclge_desc desc[1];
508 struct hclge_tqp *tqp;
509 int ret, i;
510
511 for (i = 0; i < kinfo->num_tqps; i++) {
512 queue = handle->kinfo.tqp[i];
513 tqp = container_of(queue, struct hclge_tqp, q);
514 /* command : HCLGE_OPC_QUERY_IGU_STAT */
515 hclge_cmd_setup_basic_desc(&desc[0],
516 HCLGE_OPC_QUERY_RX_STATUS,
517 true);
518
519 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
520 ret = hclge_cmd_send(&hdev->hw, desc, 1);
521 if (ret) {
522 dev_err(&hdev->pdev->dev,
523 "Query tqp stat fail, status = %d,queue = %d\n",
524 ret, i);
525 return ret;
526 }
527 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
528 le32_to_cpu(desc[0].data[4]);
529 }
530
531 for (i = 0; i < kinfo->num_tqps; i++) {
532 queue = handle->kinfo.tqp[i];
533 tqp = container_of(queue, struct hclge_tqp, q);
534 /* command : HCLGE_OPC_QUERY_IGU_STAT */
535 hclge_cmd_setup_basic_desc(&desc[0],
536 HCLGE_OPC_QUERY_TX_STATUS,
537 true);
538
539 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
540 ret = hclge_cmd_send(&hdev->hw, desc, 1);
541 if (ret) {
542 dev_err(&hdev->pdev->dev,
543 "Query tqp stat fail, status = %d,queue = %d\n",
544 ret, i);
545 return ret;
546 }
547 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
548 le32_to_cpu(desc[0].data[4]);
549 }
550
551 return 0;
552 }
553
554 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
555 {
556 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
557 struct hclge_tqp *tqp;
558 u64 *buff = data;
559 int i;
560
561 for (i = 0; i < kinfo->num_tqps; i++) {
562 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
563 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
564 }
565
566 for (i = 0; i < kinfo->num_tqps; i++) {
567 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
568 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
569 }
570
571 return buff;
572 }
573
574 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
575 {
576 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
577
578 return kinfo->num_tqps * (2);
579 }
580
581 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
582 {
583 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
584 u8 *buff = data;
585 int i = 0;
586
587 for (i = 0; i < kinfo->num_tqps; i++) {
588 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
589 struct hclge_tqp, q);
590 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
591 tqp->index);
592 buff = buff + ETH_GSTRING_LEN;
593 }
594
595 for (i = 0; i < kinfo->num_tqps; i++) {
596 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
597 struct hclge_tqp, q);
598 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
599 tqp->index);
600 buff = buff + ETH_GSTRING_LEN;
601 }
602
603 return buff;
604 }
605
606 static u64 *hclge_comm_get_stats(void *comm_stats,
607 const struct hclge_comm_stats_str strs[],
608 int size, u64 *data)
609 {
610 u64 *buf = data;
611 u32 i;
612
613 for (i = 0; i < size; i++)
614 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
615
616 return buf + size;
617 }
618
619 static u8 *hclge_comm_get_strings(u32 stringset,
620 const struct hclge_comm_stats_str strs[],
621 int size, u8 *data)
622 {
623 char *buff = (char *)data;
624 u32 i;
625
626 if (stringset != ETH_SS_STATS)
627 return buff;
628
629 for (i = 0; i < size; i++) {
630 snprintf(buff, ETH_GSTRING_LEN,
631 strs[i].desc);
632 buff = buff + ETH_GSTRING_LEN;
633 }
634
635 return (u8 *)buff;
636 }
637
638 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
639 struct net_device_stats *net_stats)
640 {
641 net_stats->tx_dropped = 0;
642 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
643 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
644 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
645
646 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
647 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
648 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
649 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
650 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
651 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
652
653 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
654 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
655
656 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
657 net_stats->rx_length_errors =
658 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
659 net_stats->rx_length_errors +=
660 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
661 net_stats->rx_over_errors =
662 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
663 }
664
665 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
666 {
667 struct hnae3_handle *handle;
668 int status;
669
670 handle = &hdev->vport[0].nic;
671 if (handle->client) {
672 status = hclge_tqps_update_stats(handle);
673 if (status) {
674 dev_err(&hdev->pdev->dev,
675 "Update TQPS stats fail, status = %d.\n",
676 status);
677 }
678 }
679
680 status = hclge_mac_update_stats(hdev);
681 if (status)
682 dev_err(&hdev->pdev->dev,
683 "Update MAC stats fail, status = %d.\n", status);
684
685 status = hclge_32_bit_update_stats(hdev);
686 if (status)
687 dev_err(&hdev->pdev->dev,
688 "Update 32 bit stats fail, status = %d.\n",
689 status);
690
691 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
692 }
693
694 static void hclge_update_stats(struct hnae3_handle *handle,
695 struct net_device_stats *net_stats)
696 {
697 struct hclge_vport *vport = hclge_get_vport(handle);
698 struct hclge_dev *hdev = vport->back;
699 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
700 int status;
701
702 status = hclge_mac_update_stats(hdev);
703 if (status)
704 dev_err(&hdev->pdev->dev,
705 "Update MAC stats fail, status = %d.\n",
706 status);
707
708 status = hclge_32_bit_update_stats(hdev);
709 if (status)
710 dev_err(&hdev->pdev->dev,
711 "Update 32 bit stats fail, status = %d.\n",
712 status);
713
714 status = hclge_64_bit_update_stats(hdev);
715 if (status)
716 dev_err(&hdev->pdev->dev,
717 "Update 64 bit stats fail, status = %d.\n",
718 status);
719
720 status = hclge_tqps_update_stats(handle);
721 if (status)
722 dev_err(&hdev->pdev->dev,
723 "Update TQPS stats fail, status = %d.\n",
724 status);
725
726 hclge_update_netstat(hw_stats, net_stats);
727 }
728
729 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
730 {
731 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
732
733 struct hclge_vport *vport = hclge_get_vport(handle);
734 struct hclge_dev *hdev = vport->back;
735 int count = 0;
736
737 /* Loopback test support rules:
738 * mac: only GE mode support
739 * serdes: all mac mode will support include GE/XGE/LGE/CGE
740 * phy: only support when phy device exist on board
741 */
742 if (stringset == ETH_SS_TEST) {
743 /* clear loopback bit flags at first */
744 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
745 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
746 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
747 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
748 count += 1;
749 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
750 } else {
751 count = -EOPNOTSUPP;
752 }
753 } else if (stringset == ETH_SS_STATS) {
754 count = ARRAY_SIZE(g_mac_stats_string) +
755 ARRAY_SIZE(g_all_32bit_stats_string) +
756 ARRAY_SIZE(g_all_64bit_stats_string) +
757 hclge_tqps_get_sset_count(handle, stringset);
758 }
759
760 return count;
761 }
762
763 static void hclge_get_strings(struct hnae3_handle *handle,
764 u32 stringset,
765 u8 *data)
766 {
767 u8 *p = (char *)data;
768 int size;
769
770 if (stringset == ETH_SS_STATS) {
771 size = ARRAY_SIZE(g_mac_stats_string);
772 p = hclge_comm_get_strings(stringset,
773 g_mac_stats_string,
774 size,
775 p);
776 size = ARRAY_SIZE(g_all_32bit_stats_string);
777 p = hclge_comm_get_strings(stringset,
778 g_all_32bit_stats_string,
779 size,
780 p);
781 size = ARRAY_SIZE(g_all_64bit_stats_string);
782 p = hclge_comm_get_strings(stringset,
783 g_all_64bit_stats_string,
784 size,
785 p);
786 p = hclge_tqps_get_strings(handle, p);
787 } else if (stringset == ETH_SS_TEST) {
788 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
789 memcpy(p,
790 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
791 ETH_GSTRING_LEN);
792 p += ETH_GSTRING_LEN;
793 }
794 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
795 memcpy(p,
796 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
797 ETH_GSTRING_LEN);
798 p += ETH_GSTRING_LEN;
799 }
800 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
801 memcpy(p,
802 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
803 ETH_GSTRING_LEN);
804 p += ETH_GSTRING_LEN;
805 }
806 }
807 }
808
809 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
810 {
811 struct hclge_vport *vport = hclge_get_vport(handle);
812 struct hclge_dev *hdev = vport->back;
813 u64 *p;
814
815 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
816 g_mac_stats_string,
817 ARRAY_SIZE(g_mac_stats_string),
818 data);
819 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
820 g_all_32bit_stats_string,
821 ARRAY_SIZE(g_all_32bit_stats_string),
822 p);
823 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
824 g_all_64bit_stats_string,
825 ARRAY_SIZE(g_all_64bit_stats_string),
826 p);
827 p = hclge_tqps_get_stats(handle, p);
828 }
829
830 static int hclge_parse_func_status(struct hclge_dev *hdev,
831 struct hclge_func_status_cmd *status)
832 {
833 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
834 return -EINVAL;
835
836 /* Set the pf to main pf */
837 if (status->pf_state & HCLGE_PF_STATE_MAIN)
838 hdev->flag |= HCLGE_FLAG_MAIN;
839 else
840 hdev->flag &= ~HCLGE_FLAG_MAIN;
841
842 return 0;
843 }
844
845 static int hclge_query_function_status(struct hclge_dev *hdev)
846 {
847 struct hclge_func_status_cmd *req;
848 struct hclge_desc desc;
849 int timeout = 0;
850 int ret;
851
852 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
853 req = (struct hclge_func_status_cmd *)desc.data;
854
855 do {
856 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
857 if (ret) {
858 dev_err(&hdev->pdev->dev,
859 "query function status failed %d.\n",
860 ret);
861
862 return ret;
863 }
864
865 /* Check pf reset is done */
866 if (req->pf_state)
867 break;
868 usleep_range(1000, 2000);
869 } while (timeout++ < 5);
870
871 ret = hclge_parse_func_status(hdev, req);
872
873 return ret;
874 }
875
876 static int hclge_query_pf_resource(struct hclge_dev *hdev)
877 {
878 struct hclge_pf_res_cmd *req;
879 struct hclge_desc desc;
880 int ret;
881
882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
883 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
884 if (ret) {
885 dev_err(&hdev->pdev->dev,
886 "query pf resource failed %d.\n", ret);
887 return ret;
888 }
889
890 req = (struct hclge_pf_res_cmd *)desc.data;
891 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
892 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
893
894 if (hnae3_dev_roce_supported(hdev)) {
895 hdev->num_roce_msi =
896 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
897 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
898
899 /* PF should have NIC vectors and Roce vectors,
900 * NIC vectors are queued before Roce vectors.
901 */
902 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
903 } else {
904 hdev->num_msi =
905 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
906 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
907 }
908
909 return 0;
910 }
911
912 static int hclge_parse_speed(int speed_cmd, int *speed)
913 {
914 switch (speed_cmd) {
915 case 6:
916 *speed = HCLGE_MAC_SPEED_10M;
917 break;
918 case 7:
919 *speed = HCLGE_MAC_SPEED_100M;
920 break;
921 case 0:
922 *speed = HCLGE_MAC_SPEED_1G;
923 break;
924 case 1:
925 *speed = HCLGE_MAC_SPEED_10G;
926 break;
927 case 2:
928 *speed = HCLGE_MAC_SPEED_25G;
929 break;
930 case 3:
931 *speed = HCLGE_MAC_SPEED_40G;
932 break;
933 case 4:
934 *speed = HCLGE_MAC_SPEED_50G;
935 break;
936 case 5:
937 *speed = HCLGE_MAC_SPEED_100G;
938 break;
939 default:
940 return -EINVAL;
941 }
942
943 return 0;
944 }
945
946 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
947 {
948 struct hclge_cfg_param_cmd *req;
949 u64 mac_addr_tmp_high;
950 u64 mac_addr_tmp;
951 int i;
952
953 req = (struct hclge_cfg_param_cmd *)desc[0].data;
954
955 /* get the configuration */
956 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
957 HCLGE_CFG_VMDQ_M,
958 HCLGE_CFG_VMDQ_S);
959 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
960 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
961 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
962 HCLGE_CFG_TQP_DESC_N_M,
963 HCLGE_CFG_TQP_DESC_N_S);
964
965 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
966 HCLGE_CFG_PHY_ADDR_M,
967 HCLGE_CFG_PHY_ADDR_S);
968 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
969 HCLGE_CFG_MEDIA_TP_M,
970 HCLGE_CFG_MEDIA_TP_S);
971 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
972 HCLGE_CFG_RX_BUF_LEN_M,
973 HCLGE_CFG_RX_BUF_LEN_S);
974 /* get mac_address */
975 mac_addr_tmp = __le32_to_cpu(req->param[2]);
976 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
977 HCLGE_CFG_MAC_ADDR_H_M,
978 HCLGE_CFG_MAC_ADDR_H_S);
979
980 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
981
982 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
983 HCLGE_CFG_DEFAULT_SPEED_M,
984 HCLGE_CFG_DEFAULT_SPEED_S);
985 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
986 HCLGE_CFG_RSS_SIZE_M,
987 HCLGE_CFG_RSS_SIZE_S);
988
989 for (i = 0; i < ETH_ALEN; i++)
990 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
991
992 req = (struct hclge_cfg_param_cmd *)desc[1].data;
993 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
994 }
995
996 /* hclge_get_cfg: query the static parameter from flash
997 * @hdev: pointer to struct hclge_dev
998 * @hcfg: the config structure to be getted
999 */
1000 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1001 {
1002 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1003 struct hclge_cfg_param_cmd *req;
1004 int i, ret;
1005
1006 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1007 u32 offset = 0;
1008
1009 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1010 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1011 true);
1012 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
1013 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1014 /* Len should be united by 4 bytes when send to hardware */
1015 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1016 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1017 req->offset = cpu_to_le32(offset);
1018 }
1019
1020 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1021 if (ret) {
1022 dev_err(&hdev->pdev->dev,
1023 "get config failed %d.\n", ret);
1024 return ret;
1025 }
1026
1027 hclge_parse_cfg(hcfg, desc);
1028 return 0;
1029 }
1030
1031 static int hclge_get_cap(struct hclge_dev *hdev)
1032 {
1033 int ret;
1034
1035 ret = hclge_query_function_status(hdev);
1036 if (ret) {
1037 dev_err(&hdev->pdev->dev,
1038 "query function status error %d.\n", ret);
1039 return ret;
1040 }
1041
1042 /* get pf resource */
1043 ret = hclge_query_pf_resource(hdev);
1044 if (ret) {
1045 dev_err(&hdev->pdev->dev,
1046 "query pf resource error %d.\n", ret);
1047 return ret;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static int hclge_configure(struct hclge_dev *hdev)
1054 {
1055 struct hclge_cfg cfg;
1056 int ret, i;
1057
1058 ret = hclge_get_cfg(hdev, &cfg);
1059 if (ret) {
1060 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1061 return ret;
1062 }
1063
1064 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1065 hdev->base_tqp_pid = 0;
1066 hdev->rss_size_max = cfg.rss_size_max;
1067 hdev->rx_buf_len = cfg.rx_buf_len;
1068 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1069 hdev->hw.mac.media_type = cfg.media_type;
1070 hdev->hw.mac.phy_addr = cfg.phy_addr;
1071 hdev->num_desc = cfg.tqp_desc_num;
1072 hdev->tm_info.num_pg = 1;
1073 hdev->tc_max = cfg.tc_num;
1074 hdev->tm_info.hw_pfc_map = 0;
1075
1076 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1077 if (ret) {
1078 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1079 return ret;
1080 }
1081
1082 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1083 (hdev->tc_max < 1)) {
1084 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1085 hdev->tc_max);
1086 hdev->tc_max = 1;
1087 }
1088
1089 /* Dev does not support DCB */
1090 if (!hnae3_dev_dcb_supported(hdev)) {
1091 hdev->tc_max = 1;
1092 hdev->pfc_max = 0;
1093 } else {
1094 hdev->pfc_max = hdev->tc_max;
1095 }
1096
1097 hdev->tm_info.num_tc = hdev->tc_max;
1098
1099 /* Currently not support uncontiuous tc */
1100 for (i = 0; i < hdev->tm_info.num_tc; i++)
1101 hnae_set_bit(hdev->hw_tc_map, i, 1);
1102
1103 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1104 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1105 else
1106 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1107
1108 return ret;
1109 }
1110
1111 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1112 int tso_mss_max)
1113 {
1114 struct hclge_cfg_tso_status_cmd *req;
1115 struct hclge_desc desc;
1116 u16 tso_mss;
1117
1118 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1119
1120 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1121
1122 tso_mss = 0;
1123 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1124 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1125 req->tso_mss_min = cpu_to_le16(tso_mss);
1126
1127 tso_mss = 0;
1128 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1129 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1130 req->tso_mss_max = cpu_to_le16(tso_mss);
1131
1132 return hclge_cmd_send(&hdev->hw, &desc, 1);
1133 }
1134
1135 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1136 {
1137 struct hclge_tqp *tqp;
1138 int i;
1139
1140 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1141 sizeof(struct hclge_tqp), GFP_KERNEL);
1142 if (!hdev->htqp)
1143 return -ENOMEM;
1144
1145 tqp = hdev->htqp;
1146
1147 for (i = 0; i < hdev->num_tqps; i++) {
1148 tqp->dev = &hdev->pdev->dev;
1149 tqp->index = i;
1150
1151 tqp->q.ae_algo = &ae_algo;
1152 tqp->q.buf_size = hdev->rx_buf_len;
1153 tqp->q.desc_num = hdev->num_desc;
1154 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1155 i * HCLGE_TQP_REG_SIZE;
1156
1157 tqp++;
1158 }
1159
1160 return 0;
1161 }
1162
1163 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1164 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1165 {
1166 struct hclge_tqp_map_cmd *req;
1167 struct hclge_desc desc;
1168 int ret;
1169
1170 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1171
1172 req = (struct hclge_tqp_map_cmd *)desc.data;
1173 req->tqp_id = cpu_to_le16(tqp_pid);
1174 req->tqp_vf = func_id;
1175 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1176 1 << HCLGE_TQP_MAP_EN_B;
1177 req->tqp_vid = cpu_to_le16(tqp_vid);
1178
1179 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1180 if (ret) {
1181 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1182 ret);
1183 return ret;
1184 }
1185
1186 return 0;
1187 }
1188
1189 static int hclge_assign_tqp(struct hclge_vport *vport,
1190 struct hnae3_queue **tqp, u16 num_tqps)
1191 {
1192 struct hclge_dev *hdev = vport->back;
1193 int i, alloced;
1194
1195 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1196 alloced < num_tqps; i++) {
1197 if (!hdev->htqp[i].alloced) {
1198 hdev->htqp[i].q.handle = &vport->nic;
1199 hdev->htqp[i].q.tqp_index = alloced;
1200 tqp[alloced] = &hdev->htqp[i].q;
1201 hdev->htqp[i].alloced = true;
1202 alloced++;
1203 }
1204 }
1205 vport->alloc_tqps = num_tqps;
1206
1207 return 0;
1208 }
1209
1210 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1211 {
1212 struct hnae3_handle *nic = &vport->nic;
1213 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1214 struct hclge_dev *hdev = vport->back;
1215 int i, ret;
1216
1217 kinfo->num_desc = hdev->num_desc;
1218 kinfo->rx_buf_len = hdev->rx_buf_len;
1219 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1220 kinfo->rss_size
1221 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1222 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1223
1224 for (i = 0; i < HNAE3_MAX_TC; i++) {
1225 if (hdev->hw_tc_map & BIT(i)) {
1226 kinfo->tc_info[i].enable = true;
1227 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1228 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1229 kinfo->tc_info[i].tc = i;
1230 } else {
1231 /* Set to default queue if TC is disable */
1232 kinfo->tc_info[i].enable = false;
1233 kinfo->tc_info[i].tqp_offset = 0;
1234 kinfo->tc_info[i].tqp_count = 1;
1235 kinfo->tc_info[i].tc = 0;
1236 }
1237 }
1238
1239 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1240 sizeof(struct hnae3_queue *), GFP_KERNEL);
1241 if (!kinfo->tqp)
1242 return -ENOMEM;
1243
1244 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1245 if (ret) {
1246 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1247 return -EINVAL;
1248 }
1249
1250 return 0;
1251 }
1252
1253 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1254 struct hclge_vport *vport)
1255 {
1256 struct hnae3_handle *nic = &vport->nic;
1257 struct hnae3_knic_private_info *kinfo;
1258 u16 i;
1259
1260 kinfo = &nic->kinfo;
1261 for (i = 0; i < kinfo->num_tqps; i++) {
1262 struct hclge_tqp *q =
1263 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1264 bool is_pf;
1265 int ret;
1266
1267 is_pf = !(vport->vport_id);
1268 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1269 i, is_pf);
1270 if (ret)
1271 return ret;
1272 }
1273
1274 return 0;
1275 }
1276
1277 static int hclge_map_tqp(struct hclge_dev *hdev)
1278 {
1279 struct hclge_vport *vport = hdev->vport;
1280 u16 i, num_vport;
1281
1282 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1283 for (i = 0; i < num_vport; i++) {
1284 int ret;
1285
1286 ret = hclge_map_tqp_to_vport(hdev, vport);
1287 if (ret)
1288 return ret;
1289
1290 vport++;
1291 }
1292
1293 return 0;
1294 }
1295
1296 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1297 {
1298 /* this would be initialized later */
1299 }
1300
1301 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1302 {
1303 struct hnae3_handle *nic = &vport->nic;
1304 struct hclge_dev *hdev = vport->back;
1305 int ret;
1306
1307 nic->pdev = hdev->pdev;
1308 nic->ae_algo = &ae_algo;
1309 nic->numa_node_mask = hdev->numa_node_mask;
1310
1311 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1312 ret = hclge_knic_setup(vport, num_tqps);
1313 if (ret) {
1314 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1315 ret);
1316 return ret;
1317 }
1318 } else {
1319 hclge_unic_setup(vport, num_tqps);
1320 }
1321
1322 return 0;
1323 }
1324
1325 static int hclge_alloc_vport(struct hclge_dev *hdev)
1326 {
1327 struct pci_dev *pdev = hdev->pdev;
1328 struct hclge_vport *vport;
1329 u32 tqp_main_vport;
1330 u32 tqp_per_vport;
1331 int num_vport, i;
1332 int ret;
1333
1334 /* We need to alloc a vport for main NIC of PF */
1335 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1336
1337 if (hdev->num_tqps < num_vport)
1338 num_vport = hdev->num_tqps;
1339
1340 /* Alloc the same number of TQPs for every vport */
1341 tqp_per_vport = hdev->num_tqps / num_vport;
1342 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1343
1344 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1345 GFP_KERNEL);
1346 if (!vport)
1347 return -ENOMEM;
1348
1349 hdev->vport = vport;
1350 hdev->num_alloc_vport = num_vport;
1351
1352 #ifdef CONFIG_PCI_IOV
1353 /* Enable SRIOV */
1354 if (hdev->num_req_vfs) {
1355 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1356 hdev->num_req_vfs);
1357 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1358 if (ret) {
1359 hdev->num_alloc_vfs = 0;
1360 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1361 ret);
1362 return ret;
1363 }
1364 }
1365 hdev->num_alloc_vfs = hdev->num_req_vfs;
1366 #endif
1367
1368 for (i = 0; i < num_vport; i++) {
1369 vport->back = hdev;
1370 vport->vport_id = i;
1371
1372 if (i == 0)
1373 ret = hclge_vport_setup(vport, tqp_main_vport);
1374 else
1375 ret = hclge_vport_setup(vport, tqp_per_vport);
1376 if (ret) {
1377 dev_err(&pdev->dev,
1378 "vport setup failed for vport %d, %d\n",
1379 i, ret);
1380 return ret;
1381 }
1382
1383 vport++;
1384 }
1385
1386 return 0;
1387 }
1388
1389 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1390 struct hclge_pkt_buf_alloc *buf_alloc)
1391 {
1392 /* TX buffer size is unit by 128 byte */
1393 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1394 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1395 struct hclge_tx_buff_alloc_cmd *req;
1396 struct hclge_desc desc;
1397 int ret;
1398 u8 i;
1399
1400 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1401
1402 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1403 for (i = 0; i < HCLGE_TC_NUM; i++) {
1404 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1405
1406 req->tx_pkt_buff[i] =
1407 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1408 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1409 }
1410
1411 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1412 if (ret) {
1413 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1414 ret);
1415 return ret;
1416 }
1417
1418 return 0;
1419 }
1420
1421 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1422 struct hclge_pkt_buf_alloc *buf_alloc)
1423 {
1424 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1425
1426 if (ret) {
1427 dev_err(&hdev->pdev->dev,
1428 "tx buffer alloc failed %d\n", ret);
1429 return ret;
1430 }
1431
1432 return 0;
1433 }
1434
1435 static int hclge_get_tc_num(struct hclge_dev *hdev)
1436 {
1437 int i, cnt = 0;
1438
1439 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1440 if (hdev->hw_tc_map & BIT(i))
1441 cnt++;
1442 return cnt;
1443 }
1444
1445 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1446 {
1447 int i, cnt = 0;
1448
1449 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1450 if (hdev->hw_tc_map & BIT(i) &&
1451 hdev->tm_info.hw_pfc_map & BIT(i))
1452 cnt++;
1453 return cnt;
1454 }
1455
1456 /* Get the number of pfc enabled TCs, which have private buffer */
1457 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1458 struct hclge_pkt_buf_alloc *buf_alloc)
1459 {
1460 struct hclge_priv_buf *priv;
1461 int i, cnt = 0;
1462
1463 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1464 priv = &buf_alloc->priv_buf[i];
1465 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1466 priv->enable)
1467 cnt++;
1468 }
1469
1470 return cnt;
1471 }
1472
1473 /* Get the number of pfc disabled TCs, which have private buffer */
1474 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1475 struct hclge_pkt_buf_alloc *buf_alloc)
1476 {
1477 struct hclge_priv_buf *priv;
1478 int i, cnt = 0;
1479
1480 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1481 priv = &buf_alloc->priv_buf[i];
1482 if (hdev->hw_tc_map & BIT(i) &&
1483 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1484 priv->enable)
1485 cnt++;
1486 }
1487
1488 return cnt;
1489 }
1490
1491 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1492 {
1493 struct hclge_priv_buf *priv;
1494 u32 rx_priv = 0;
1495 int i;
1496
1497 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1498 priv = &buf_alloc->priv_buf[i];
1499 if (priv->enable)
1500 rx_priv += priv->buf_size;
1501 }
1502 return rx_priv;
1503 }
1504
1505 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1506 {
1507 u32 i, total_tx_size = 0;
1508
1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1510 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1511
1512 return total_tx_size;
1513 }
1514
1515 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1516 struct hclge_pkt_buf_alloc *buf_alloc,
1517 u32 rx_all)
1518 {
1519 u32 shared_buf_min, shared_buf_tc, shared_std;
1520 int tc_num, pfc_enable_num;
1521 u32 shared_buf;
1522 u32 rx_priv;
1523 int i;
1524
1525 tc_num = hclge_get_tc_num(hdev);
1526 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1527
1528 if (hnae3_dev_dcb_supported(hdev))
1529 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1530 else
1531 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1532
1533 shared_buf_tc = pfc_enable_num * hdev->mps +
1534 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1535 hdev->mps;
1536 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1537
1538 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1539 if (rx_all <= rx_priv + shared_std)
1540 return false;
1541
1542 shared_buf = rx_all - rx_priv;
1543 buf_alloc->s_buf.buf_size = shared_buf;
1544 buf_alloc->s_buf.self.high = shared_buf;
1545 buf_alloc->s_buf.self.low = 2 * hdev->mps;
1546
1547 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1548 if ((hdev->hw_tc_map & BIT(i)) &&
1549 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1550 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1551 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1552 } else {
1553 buf_alloc->s_buf.tc_thrd[i].low = 0;
1554 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1555 }
1556 }
1557
1558 return true;
1559 }
1560
1561 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1562 struct hclge_pkt_buf_alloc *buf_alloc)
1563 {
1564 u32 i, total_size;
1565
1566 total_size = hdev->pkt_buf_size;
1567
1568 /* alloc tx buffer for all enabled tc */
1569 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1570 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1571
1572 if (total_size < HCLGE_DEFAULT_TX_BUF)
1573 return -ENOMEM;
1574
1575 if (hdev->hw_tc_map & BIT(i))
1576 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1577 else
1578 priv->tx_buf_size = 0;
1579
1580 total_size -= priv->tx_buf_size;
1581 }
1582
1583 return 0;
1584 }
1585
1586 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1587 * @hdev: pointer to struct hclge_dev
1588 * @buf_alloc: pointer to buffer calculation data
1589 * @return: 0: calculate sucessful, negative: fail
1590 */
1591 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1592 struct hclge_pkt_buf_alloc *buf_alloc)
1593 {
1594 u32 rx_all = hdev->pkt_buf_size;
1595 int no_pfc_priv_num, pfc_priv_num;
1596 struct hclge_priv_buf *priv;
1597 int i;
1598
1599 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1600
1601 /* When DCB is not supported, rx private
1602 * buffer is not allocated.
1603 */
1604 if (!hnae3_dev_dcb_supported(hdev)) {
1605 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1606 return -ENOMEM;
1607
1608 return 0;
1609 }
1610
1611 /* step 1, try to alloc private buffer for all enabled tc */
1612 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1613 priv = &buf_alloc->priv_buf[i];
1614 if (hdev->hw_tc_map & BIT(i)) {
1615 priv->enable = 1;
1616 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1617 priv->wl.low = hdev->mps;
1618 priv->wl.high = priv->wl.low + hdev->mps;
1619 priv->buf_size = priv->wl.high +
1620 HCLGE_DEFAULT_DV;
1621 } else {
1622 priv->wl.low = 0;
1623 priv->wl.high = 2 * hdev->mps;
1624 priv->buf_size = priv->wl.high;
1625 }
1626 } else {
1627 priv->enable = 0;
1628 priv->wl.low = 0;
1629 priv->wl.high = 0;
1630 priv->buf_size = 0;
1631 }
1632 }
1633
1634 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1635 return 0;
1636
1637 /* step 2, try to decrease the buffer size of
1638 * no pfc TC's private buffer
1639 */
1640 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1641 priv = &buf_alloc->priv_buf[i];
1642
1643 priv->enable = 0;
1644 priv->wl.low = 0;
1645 priv->wl.high = 0;
1646 priv->buf_size = 0;
1647
1648 if (!(hdev->hw_tc_map & BIT(i)))
1649 continue;
1650
1651 priv->enable = 1;
1652
1653 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1654 priv->wl.low = 128;
1655 priv->wl.high = priv->wl.low + hdev->mps;
1656 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1657 } else {
1658 priv->wl.low = 0;
1659 priv->wl.high = hdev->mps;
1660 priv->buf_size = priv->wl.high;
1661 }
1662 }
1663
1664 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1665 return 0;
1666
1667 /* step 3, try to reduce the number of pfc disabled TCs,
1668 * which have private buffer
1669 */
1670 /* get the total no pfc enable TC number, which have private buffer */
1671 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1672
1673 /* let the last to be cleared first */
1674 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1675 priv = &buf_alloc->priv_buf[i];
1676
1677 if (hdev->hw_tc_map & BIT(i) &&
1678 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1679 /* Clear the no pfc TC private buffer */
1680 priv->wl.low = 0;
1681 priv->wl.high = 0;
1682 priv->buf_size = 0;
1683 priv->enable = 0;
1684 no_pfc_priv_num--;
1685 }
1686
1687 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1688 no_pfc_priv_num == 0)
1689 break;
1690 }
1691
1692 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1693 return 0;
1694
1695 /* step 4, try to reduce the number of pfc enabled TCs
1696 * which have private buffer.
1697 */
1698 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1699
1700 /* let the last to be cleared first */
1701 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1702 priv = &buf_alloc->priv_buf[i];
1703
1704 if (hdev->hw_tc_map & BIT(i) &&
1705 hdev->tm_info.hw_pfc_map & BIT(i)) {
1706 /* Reduce the number of pfc TC with private buffer */
1707 priv->wl.low = 0;
1708 priv->enable = 0;
1709 priv->wl.high = 0;
1710 priv->buf_size = 0;
1711 pfc_priv_num--;
1712 }
1713
1714 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1715 pfc_priv_num == 0)
1716 break;
1717 }
1718 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1719 return 0;
1720
1721 return -ENOMEM;
1722 }
1723
1724 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1725 struct hclge_pkt_buf_alloc *buf_alloc)
1726 {
1727 struct hclge_rx_priv_buff_cmd *req;
1728 struct hclge_desc desc;
1729 int ret;
1730 int i;
1731
1732 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1733 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1734
1735 /* Alloc private buffer TCs */
1736 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1737 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1738
1739 req->buf_num[i] =
1740 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1741 req->buf_num[i] |=
1742 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1743 }
1744
1745 req->shared_buf =
1746 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1747 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1748
1749 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1750 if (ret) {
1751 dev_err(&hdev->pdev->dev,
1752 "rx private buffer alloc cmd failed %d\n", ret);
1753 return ret;
1754 }
1755
1756 return 0;
1757 }
1758
1759 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1760
1761 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1762 struct hclge_pkt_buf_alloc *buf_alloc)
1763 {
1764 struct hclge_rx_priv_wl_buf *req;
1765 struct hclge_priv_buf *priv;
1766 struct hclge_desc desc[2];
1767 int i, j;
1768 int ret;
1769
1770 for (i = 0; i < 2; i++) {
1771 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1772 false);
1773 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1774
1775 /* The first descriptor set the NEXT bit to 1 */
1776 if (i == 0)
1777 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1778 else
1779 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1780
1781 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1782 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1783
1784 priv = &buf_alloc->priv_buf[idx];
1785 req->tc_wl[j].high =
1786 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1787 req->tc_wl[j].high |=
1788 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1789 HCLGE_RX_PRIV_EN_B);
1790 req->tc_wl[j].low =
1791 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1792 req->tc_wl[j].low |=
1793 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1794 HCLGE_RX_PRIV_EN_B);
1795 }
1796 }
1797
1798 /* Send 2 descriptor at one time */
1799 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1800 if (ret) {
1801 dev_err(&hdev->pdev->dev,
1802 "rx private waterline config cmd failed %d\n",
1803 ret);
1804 return ret;
1805 }
1806 return 0;
1807 }
1808
1809 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1810 struct hclge_pkt_buf_alloc *buf_alloc)
1811 {
1812 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1813 struct hclge_rx_com_thrd *req;
1814 struct hclge_desc desc[2];
1815 struct hclge_tc_thrd *tc;
1816 int i, j;
1817 int ret;
1818
1819 for (i = 0; i < 2; i++) {
1820 hclge_cmd_setup_basic_desc(&desc[i],
1821 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1822 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1823
1824 /* The first descriptor set the NEXT bit to 1 */
1825 if (i == 0)
1826 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1827 else
1828 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1829
1830 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1831 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1832
1833 req->com_thrd[j].high =
1834 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1835 req->com_thrd[j].high |=
1836 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1837 HCLGE_RX_PRIV_EN_B);
1838 req->com_thrd[j].low =
1839 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1840 req->com_thrd[j].low |=
1841 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1842 HCLGE_RX_PRIV_EN_B);
1843 }
1844 }
1845
1846 /* Send 2 descriptors at one time */
1847 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1848 if (ret) {
1849 dev_err(&hdev->pdev->dev,
1850 "common threshold config cmd failed %d\n", ret);
1851 return ret;
1852 }
1853 return 0;
1854 }
1855
1856 static int hclge_common_wl_config(struct hclge_dev *hdev,
1857 struct hclge_pkt_buf_alloc *buf_alloc)
1858 {
1859 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1860 struct hclge_rx_com_wl *req;
1861 struct hclge_desc desc;
1862 int ret;
1863
1864 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1865
1866 req = (struct hclge_rx_com_wl *)desc.data;
1867 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1868 req->com_wl.high |=
1869 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1870 HCLGE_RX_PRIV_EN_B);
1871
1872 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1873 req->com_wl.low |=
1874 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1875 HCLGE_RX_PRIV_EN_B);
1876
1877 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1878 if (ret) {
1879 dev_err(&hdev->pdev->dev,
1880 "common waterline config cmd failed %d\n", ret);
1881 return ret;
1882 }
1883
1884 return 0;
1885 }
1886
1887 int hclge_buffer_alloc(struct hclge_dev *hdev)
1888 {
1889 struct hclge_pkt_buf_alloc *pkt_buf;
1890 int ret;
1891
1892 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1893 if (!pkt_buf)
1894 return -ENOMEM;
1895
1896 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1897 if (ret) {
1898 dev_err(&hdev->pdev->dev,
1899 "could not calc tx buffer size for all TCs %d\n", ret);
1900 goto out;
1901 }
1902
1903 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1904 if (ret) {
1905 dev_err(&hdev->pdev->dev,
1906 "could not alloc tx buffers %d\n", ret);
1907 goto out;
1908 }
1909
1910 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1911 if (ret) {
1912 dev_err(&hdev->pdev->dev,
1913 "could not calc rx priv buffer size for all TCs %d\n",
1914 ret);
1915 goto out;
1916 }
1917
1918 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1919 if (ret) {
1920 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1921 ret);
1922 goto out;
1923 }
1924
1925 if (hnae3_dev_dcb_supported(hdev)) {
1926 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1927 if (ret) {
1928 dev_err(&hdev->pdev->dev,
1929 "could not configure rx private waterline %d\n",
1930 ret);
1931 goto out;
1932 }
1933
1934 ret = hclge_common_thrd_config(hdev, pkt_buf);
1935 if (ret) {
1936 dev_err(&hdev->pdev->dev,
1937 "could not configure common threshold %d\n",
1938 ret);
1939 goto out;
1940 }
1941 }
1942
1943 ret = hclge_common_wl_config(hdev, pkt_buf);
1944 if (ret)
1945 dev_err(&hdev->pdev->dev,
1946 "could not configure common waterline %d\n", ret);
1947
1948 out:
1949 kfree(pkt_buf);
1950 return ret;
1951 }
1952
1953 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1954 {
1955 struct hnae3_handle *roce = &vport->roce;
1956 struct hnae3_handle *nic = &vport->nic;
1957
1958 roce->rinfo.num_vectors = vport->back->num_roce_msi;
1959
1960 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1961 vport->back->num_msi_left == 0)
1962 return -EINVAL;
1963
1964 roce->rinfo.base_vector = vport->back->roce_base_vector;
1965
1966 roce->rinfo.netdev = nic->kinfo.netdev;
1967 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1968
1969 roce->pdev = nic->pdev;
1970 roce->ae_algo = nic->ae_algo;
1971 roce->numa_node_mask = nic->numa_node_mask;
1972
1973 return 0;
1974 }
1975
1976 static int hclge_init_msi(struct hclge_dev *hdev)
1977 {
1978 struct pci_dev *pdev = hdev->pdev;
1979 int vectors;
1980 int i;
1981
1982 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1983 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1984 if (vectors < 0) {
1985 dev_err(&pdev->dev,
1986 "failed(%d) to allocate MSI/MSI-X vectors\n",
1987 vectors);
1988 return vectors;
1989 }
1990 if (vectors < hdev->num_msi)
1991 dev_warn(&hdev->pdev->dev,
1992 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1993 hdev->num_msi, vectors);
1994
1995 hdev->num_msi = vectors;
1996 hdev->num_msi_left = vectors;
1997 hdev->base_msi_vector = pdev->irq;
1998 hdev->roce_base_vector = hdev->base_msi_vector +
1999 HCLGE_ROCE_VECTOR_OFFSET;
2000
2001 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2002 sizeof(u16), GFP_KERNEL);
2003 if (!hdev->vector_status) {
2004 pci_free_irq_vectors(pdev);
2005 return -ENOMEM;
2006 }
2007
2008 for (i = 0; i < hdev->num_msi; i++)
2009 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2010
2011 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2012 sizeof(int), GFP_KERNEL);
2013 if (!hdev->vector_irq) {
2014 pci_free_irq_vectors(pdev);
2015 return -ENOMEM;
2016 }
2017
2018 return 0;
2019 }
2020
2021 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2022 {
2023 struct hclge_mac *mac = &hdev->hw.mac;
2024
2025 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2026 mac->duplex = (u8)duplex;
2027 else
2028 mac->duplex = HCLGE_MAC_FULL;
2029
2030 mac->speed = speed;
2031 }
2032
2033 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2034 {
2035 struct hclge_config_mac_speed_dup_cmd *req;
2036 struct hclge_desc desc;
2037 int ret;
2038
2039 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2040
2041 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2042
2043 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2044
2045 switch (speed) {
2046 case HCLGE_MAC_SPEED_10M:
2047 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2048 HCLGE_CFG_SPEED_S, 6);
2049 break;
2050 case HCLGE_MAC_SPEED_100M:
2051 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2052 HCLGE_CFG_SPEED_S, 7);
2053 break;
2054 case HCLGE_MAC_SPEED_1G:
2055 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2056 HCLGE_CFG_SPEED_S, 0);
2057 break;
2058 case HCLGE_MAC_SPEED_10G:
2059 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2060 HCLGE_CFG_SPEED_S, 1);
2061 break;
2062 case HCLGE_MAC_SPEED_25G:
2063 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2064 HCLGE_CFG_SPEED_S, 2);
2065 break;
2066 case HCLGE_MAC_SPEED_40G:
2067 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2068 HCLGE_CFG_SPEED_S, 3);
2069 break;
2070 case HCLGE_MAC_SPEED_50G:
2071 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2072 HCLGE_CFG_SPEED_S, 4);
2073 break;
2074 case HCLGE_MAC_SPEED_100G:
2075 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2076 HCLGE_CFG_SPEED_S, 5);
2077 break;
2078 default:
2079 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2080 return -EINVAL;
2081 }
2082
2083 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2084 1);
2085
2086 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2087 if (ret) {
2088 dev_err(&hdev->pdev->dev,
2089 "mac speed/duplex config cmd failed %d.\n", ret);
2090 return ret;
2091 }
2092
2093 hclge_check_speed_dup(hdev, duplex, speed);
2094
2095 return 0;
2096 }
2097
2098 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2099 u8 duplex)
2100 {
2101 struct hclge_vport *vport = hclge_get_vport(handle);
2102 struct hclge_dev *hdev = vport->back;
2103
2104 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2105 }
2106
2107 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2108 u8 *duplex)
2109 {
2110 struct hclge_query_an_speed_dup_cmd *req;
2111 struct hclge_desc desc;
2112 int speed_tmp;
2113 int ret;
2114
2115 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2116
2117 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2118 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2119 if (ret) {
2120 dev_err(&hdev->pdev->dev,
2121 "mac speed/autoneg/duplex query cmd failed %d\n",
2122 ret);
2123 return ret;
2124 }
2125
2126 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2127 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2128 HCLGE_QUERY_SPEED_S);
2129
2130 ret = hclge_parse_speed(speed_tmp, speed);
2131 if (ret) {
2132 dev_err(&hdev->pdev->dev,
2133 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2134 return -EIO;
2135 }
2136
2137 return 0;
2138 }
2139
2140 static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2141 {
2142 struct hclge_mac *mac = &hdev->hw.mac;
2143 struct hclge_query_an_speed_dup_cmd *req;
2144 struct hclge_desc desc;
2145 int ret;
2146
2147 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2148
2149 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2150 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2151 if (ret) {
2152 dev_err(&hdev->pdev->dev,
2153 "autoneg result query cmd failed %d.\n", ret);
2154 return ret;
2155 }
2156
2157 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2158
2159 return 0;
2160 }
2161
2162 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2163 {
2164 struct hclge_config_auto_neg_cmd *req;
2165 struct hclge_desc desc;
2166 u32 flag = 0;
2167 int ret;
2168
2169 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2170
2171 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2172 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2173 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2174
2175 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2176 if (ret) {
2177 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2178 ret);
2179 return ret;
2180 }
2181
2182 return 0;
2183 }
2184
2185 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2186 {
2187 struct hclge_vport *vport = hclge_get_vport(handle);
2188 struct hclge_dev *hdev = vport->back;
2189
2190 return hclge_set_autoneg_en(hdev, enable);
2191 }
2192
2193 static int hclge_get_autoneg(struct hnae3_handle *handle)
2194 {
2195 struct hclge_vport *vport = hclge_get_vport(handle);
2196 struct hclge_dev *hdev = vport->back;
2197
2198 hclge_query_autoneg_result(hdev);
2199
2200 return hdev->hw.mac.autoneg;
2201 }
2202
2203 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2204 bool mask_vlan,
2205 u8 *mac_mask)
2206 {
2207 struct hclge_mac_vlan_mask_entry_cmd *req;
2208 struct hclge_desc desc;
2209 int status;
2210
2211 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2212 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2213
2214 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2215 mask_vlan ? 1 : 0);
2216 ether_addr_copy(req->mac_mask, mac_mask);
2217
2218 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2219 if (status)
2220 dev_err(&hdev->pdev->dev,
2221 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2222 status);
2223
2224 return status;
2225 }
2226
2227 static int hclge_mac_init(struct hclge_dev *hdev)
2228 {
2229 struct hclge_mac *mac = &hdev->hw.mac;
2230 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2231 int ret;
2232
2233 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2234 if (ret) {
2235 dev_err(&hdev->pdev->dev,
2236 "Config mac speed dup fail ret=%d\n", ret);
2237 return ret;
2238 }
2239
2240 mac->link = 0;
2241
2242 /* Initialize the MTA table work mode */
2243 hdev->accept_mta_mc = true;
2244 hdev->enable_mta = true;
2245 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2246
2247 ret = hclge_set_mta_filter_mode(hdev,
2248 hdev->mta_mac_sel_type,
2249 hdev->enable_mta);
2250 if (ret) {
2251 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2252 ret);
2253 return ret;
2254 }
2255
2256 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2257 if (ret) {
2258 dev_err(&hdev->pdev->dev,
2259 "set mta filter mode fail ret=%d\n", ret);
2260 return ret;
2261 }
2262
2263 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2264 if (ret)
2265 dev_err(&hdev->pdev->dev,
2266 "set default mac_vlan_mask fail ret=%d\n", ret);
2267
2268 return ret;
2269 }
2270
2271 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2272 {
2273 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2274 schedule_work(&hdev->mbx_service_task);
2275 }
2276
2277 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2278 {
2279 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2280 schedule_work(&hdev->rst_service_task);
2281 }
2282
2283 static void hclge_task_schedule(struct hclge_dev *hdev)
2284 {
2285 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2286 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2287 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2288 (void)schedule_work(&hdev->service_task);
2289 }
2290
2291 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2292 {
2293 struct hclge_link_status_cmd *req;
2294 struct hclge_desc desc;
2295 int link_status;
2296 int ret;
2297
2298 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2299 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2300 if (ret) {
2301 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2302 ret);
2303 return ret;
2304 }
2305
2306 req = (struct hclge_link_status_cmd *)desc.data;
2307 link_status = req->status & HCLGE_LINK_STATUS;
2308
2309 return !!link_status;
2310 }
2311
2312 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2313 {
2314 int mac_state;
2315 int link_stat;
2316
2317 mac_state = hclge_get_mac_link_status(hdev);
2318
2319 if (hdev->hw.mac.phydev) {
2320 if (!genphy_read_status(hdev->hw.mac.phydev))
2321 link_stat = mac_state &
2322 hdev->hw.mac.phydev->link;
2323 else
2324 link_stat = 0;
2325
2326 } else {
2327 link_stat = mac_state;
2328 }
2329
2330 return !!link_stat;
2331 }
2332
2333 static void hclge_update_link_status(struct hclge_dev *hdev)
2334 {
2335 struct hnae3_client *client = hdev->nic_client;
2336 struct hnae3_handle *handle;
2337 int state;
2338 int i;
2339
2340 if (!client)
2341 return;
2342 state = hclge_get_mac_phy_link(hdev);
2343 if (state != hdev->hw.mac.link) {
2344 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2345 handle = &hdev->vport[i].nic;
2346 client->ops->link_status_change(handle, state);
2347 }
2348 hdev->hw.mac.link = state;
2349 }
2350 }
2351
2352 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2353 {
2354 struct hclge_mac mac = hdev->hw.mac;
2355 u8 duplex;
2356 int speed;
2357 int ret;
2358
2359 /* get the speed and duplex as autoneg'result from mac cmd when phy
2360 * doesn't exit.
2361 */
2362 if (mac.phydev || !mac.autoneg)
2363 return 0;
2364
2365 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2366 if (ret) {
2367 dev_err(&hdev->pdev->dev,
2368 "mac autoneg/speed/duplex query failed %d\n", ret);
2369 return ret;
2370 }
2371
2372 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2373 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2374 if (ret) {
2375 dev_err(&hdev->pdev->dev,
2376 "mac speed/duplex config failed %d\n", ret);
2377 return ret;
2378 }
2379 }
2380
2381 return 0;
2382 }
2383
2384 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2385 {
2386 struct hclge_vport *vport = hclge_get_vport(handle);
2387 struct hclge_dev *hdev = vport->back;
2388
2389 return hclge_update_speed_duplex(hdev);
2390 }
2391
2392 static int hclge_get_status(struct hnae3_handle *handle)
2393 {
2394 struct hclge_vport *vport = hclge_get_vport(handle);
2395 struct hclge_dev *hdev = vport->back;
2396
2397 hclge_update_link_status(hdev);
2398
2399 return hdev->hw.mac.link;
2400 }
2401
2402 static void hclge_service_timer(struct timer_list *t)
2403 {
2404 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2405
2406 mod_timer(&hdev->service_timer, jiffies + HZ);
2407 hclge_task_schedule(hdev);
2408 }
2409
2410 static void hclge_service_complete(struct hclge_dev *hdev)
2411 {
2412 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2413
2414 /* Flush memory before next watchdog */
2415 smp_mb__before_atomic();
2416 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2417 }
2418
2419 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2420 {
2421 u32 rst_src_reg;
2422 u32 cmdq_src_reg;
2423
2424 /* fetch the events from their corresponding regs */
2425 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2426 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2427
2428 /* Assumption: If by any chance reset and mailbox events are reported
2429 * together then we will only process reset event in this go and will
2430 * defer the processing of the mailbox events. Since, we would have not
2431 * cleared RX CMDQ event this time we would receive again another
2432 * interrupt from H/W just for the mailbox.
2433 */
2434
2435 /* check for vector0 reset event sources */
2436 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2437 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2438 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2439 return HCLGE_VECTOR0_EVENT_RST;
2440 }
2441
2442 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2443 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2444 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2445 return HCLGE_VECTOR0_EVENT_RST;
2446 }
2447
2448 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2449 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2450 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2451 return HCLGE_VECTOR0_EVENT_RST;
2452 }
2453
2454 /* check for vector0 mailbox(=CMDQ RX) event source */
2455 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2456 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2457 *clearval = cmdq_src_reg;
2458 return HCLGE_VECTOR0_EVENT_MBX;
2459 }
2460
2461 return HCLGE_VECTOR0_EVENT_OTHER;
2462 }
2463
2464 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2465 u32 regclr)
2466 {
2467 switch (event_type) {
2468 case HCLGE_VECTOR0_EVENT_RST:
2469 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2470 break;
2471 case HCLGE_VECTOR0_EVENT_MBX:
2472 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2473 break;
2474 }
2475 }
2476
2477 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2478 {
2479 writel(enable ? 1 : 0, vector->addr);
2480 }
2481
2482 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2483 {
2484 struct hclge_dev *hdev = data;
2485 u32 event_cause;
2486 u32 clearval;
2487
2488 hclge_enable_vector(&hdev->misc_vector, false);
2489 event_cause = hclge_check_event_cause(hdev, &clearval);
2490
2491 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2492 switch (event_cause) {
2493 case HCLGE_VECTOR0_EVENT_RST:
2494 hclge_reset_task_schedule(hdev);
2495 break;
2496 case HCLGE_VECTOR0_EVENT_MBX:
2497 /* If we are here then,
2498 * 1. Either we are not handling any mbx task and we are not
2499 * scheduled as well
2500 * OR
2501 * 2. We could be handling a mbx task but nothing more is
2502 * scheduled.
2503 * In both cases, we should schedule mbx task as there are more
2504 * mbx messages reported by this interrupt.
2505 */
2506 hclge_mbx_task_schedule(hdev);
2507
2508 default:
2509 dev_dbg(&hdev->pdev->dev,
2510 "received unknown or unhandled event of vector0\n");
2511 break;
2512 }
2513
2514 /* we should clear the source of interrupt */
2515 hclge_clear_event_cause(hdev, event_cause, clearval);
2516 hclge_enable_vector(&hdev->misc_vector, true);
2517
2518 return IRQ_HANDLED;
2519 }
2520
2521 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2522 {
2523 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2524 hdev->num_msi_left += 1;
2525 hdev->num_msi_used -= 1;
2526 }
2527
2528 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2529 {
2530 struct hclge_misc_vector *vector = &hdev->misc_vector;
2531
2532 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2533
2534 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2535 hdev->vector_status[0] = 0;
2536
2537 hdev->num_msi_left -= 1;
2538 hdev->num_msi_used += 1;
2539 }
2540
2541 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2542 {
2543 int ret;
2544
2545 hclge_get_misc_vector(hdev);
2546
2547 /* this would be explicitly freed in the end */
2548 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2549 0, "hclge_misc", hdev);
2550 if (ret) {
2551 hclge_free_vector(hdev, 0);
2552 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2553 hdev->misc_vector.vector_irq);
2554 }
2555
2556 return ret;
2557 }
2558
2559 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2560 {
2561 free_irq(hdev->misc_vector.vector_irq, hdev);
2562 hclge_free_vector(hdev, 0);
2563 }
2564
2565 static int hclge_notify_client(struct hclge_dev *hdev,
2566 enum hnae3_reset_notify_type type)
2567 {
2568 struct hnae3_client *client = hdev->nic_client;
2569 u16 i;
2570
2571 if (!client->ops->reset_notify)
2572 return -EOPNOTSUPP;
2573
2574 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2575 struct hnae3_handle *handle = &hdev->vport[i].nic;
2576 int ret;
2577
2578 ret = client->ops->reset_notify(handle, type);
2579 if (ret)
2580 return ret;
2581 }
2582
2583 return 0;
2584 }
2585
2586 static int hclge_reset_wait(struct hclge_dev *hdev)
2587 {
2588 #define HCLGE_RESET_WATI_MS 100
2589 #define HCLGE_RESET_WAIT_CNT 5
2590 u32 val, reg, reg_bit;
2591 u32 cnt = 0;
2592
2593 switch (hdev->reset_type) {
2594 case HNAE3_GLOBAL_RESET:
2595 reg = HCLGE_GLOBAL_RESET_REG;
2596 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2597 break;
2598 case HNAE3_CORE_RESET:
2599 reg = HCLGE_GLOBAL_RESET_REG;
2600 reg_bit = HCLGE_CORE_RESET_BIT;
2601 break;
2602 case HNAE3_FUNC_RESET:
2603 reg = HCLGE_FUN_RST_ING;
2604 reg_bit = HCLGE_FUN_RST_ING_B;
2605 break;
2606 default:
2607 dev_err(&hdev->pdev->dev,
2608 "Wait for unsupported reset type: %d\n",
2609 hdev->reset_type);
2610 return -EINVAL;
2611 }
2612
2613 val = hclge_read_dev(&hdev->hw, reg);
2614 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2615 msleep(HCLGE_RESET_WATI_MS);
2616 val = hclge_read_dev(&hdev->hw, reg);
2617 cnt++;
2618 }
2619
2620 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2621 dev_warn(&hdev->pdev->dev,
2622 "Wait for reset timeout: %d\n", hdev->reset_type);
2623 return -EBUSY;
2624 }
2625
2626 return 0;
2627 }
2628
2629 static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2630 {
2631 struct hclge_desc desc;
2632 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2633 int ret;
2634
2635 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2636 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2637 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2638 req->fun_reset_vfid = func_id;
2639
2640 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2641 if (ret)
2642 dev_err(&hdev->pdev->dev,
2643 "send function reset cmd fail, status =%d\n", ret);
2644
2645 return ret;
2646 }
2647
2648 static void hclge_do_reset(struct hclge_dev *hdev)
2649 {
2650 struct pci_dev *pdev = hdev->pdev;
2651 u32 val;
2652
2653 switch (hdev->reset_type) {
2654 case HNAE3_GLOBAL_RESET:
2655 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2656 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2657 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2658 dev_info(&pdev->dev, "Global Reset requested\n");
2659 break;
2660 case HNAE3_CORE_RESET:
2661 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2662 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2663 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2664 dev_info(&pdev->dev, "Core Reset requested\n");
2665 break;
2666 case HNAE3_FUNC_RESET:
2667 dev_info(&pdev->dev, "PF Reset requested\n");
2668 hclge_func_reset_cmd(hdev, 0);
2669 /* schedule again to check later */
2670 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2671 hclge_reset_task_schedule(hdev);
2672 break;
2673 default:
2674 dev_warn(&pdev->dev,
2675 "Unsupported reset type: %d\n", hdev->reset_type);
2676 break;
2677 }
2678 }
2679
2680 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2681 unsigned long *addr)
2682 {
2683 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2684
2685 /* return the highest priority reset level amongst all */
2686 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2687 rst_level = HNAE3_GLOBAL_RESET;
2688 else if (test_bit(HNAE3_CORE_RESET, addr))
2689 rst_level = HNAE3_CORE_RESET;
2690 else if (test_bit(HNAE3_IMP_RESET, addr))
2691 rst_level = HNAE3_IMP_RESET;
2692 else if (test_bit(HNAE3_FUNC_RESET, addr))
2693 rst_level = HNAE3_FUNC_RESET;
2694
2695 /* now, clear all other resets */
2696 clear_bit(HNAE3_GLOBAL_RESET, addr);
2697 clear_bit(HNAE3_CORE_RESET, addr);
2698 clear_bit(HNAE3_IMP_RESET, addr);
2699 clear_bit(HNAE3_FUNC_RESET, addr);
2700
2701 return rst_level;
2702 }
2703
2704 static void hclge_reset(struct hclge_dev *hdev)
2705 {
2706 /* perform reset of the stack & ae device for a client */
2707
2708 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2709
2710 if (!hclge_reset_wait(hdev)) {
2711 rtnl_lock();
2712 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2713 hclge_reset_ae_dev(hdev->ae_dev);
2714 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2715 rtnl_unlock();
2716 } else {
2717 /* schedule again to check pending resets later */
2718 set_bit(hdev->reset_type, &hdev->reset_pending);
2719 hclge_reset_task_schedule(hdev);
2720 }
2721
2722 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2723 }
2724
2725 static void hclge_reset_event(struct hnae3_handle *handle,
2726 enum hnae3_reset_type reset)
2727 {
2728 struct hclge_vport *vport = hclge_get_vport(handle);
2729 struct hclge_dev *hdev = vport->back;
2730
2731 dev_info(&hdev->pdev->dev,
2732 "Receive reset event , reset_type is %d", reset);
2733
2734 switch (reset) {
2735 case HNAE3_FUNC_RESET:
2736 case HNAE3_CORE_RESET:
2737 case HNAE3_GLOBAL_RESET:
2738 /* request reset & schedule reset task */
2739 set_bit(reset, &hdev->reset_request);
2740 hclge_reset_task_schedule(hdev);
2741 break;
2742 default:
2743 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2744 break;
2745 }
2746 }
2747
2748 static void hclge_reset_subtask(struct hclge_dev *hdev)
2749 {
2750 /* check if there is any ongoing reset in the hardware. This status can
2751 * be checked from reset_pending. If there is then, we need to wait for
2752 * hardware to complete reset.
2753 * a. If we are able to figure out in reasonable time that hardware
2754 * has fully resetted then, we can proceed with driver, client
2755 * reset.
2756 * b. else, we can come back later to check this status so re-sched
2757 * now.
2758 */
2759 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2760 if (hdev->reset_type != HNAE3_NONE_RESET)
2761 hclge_reset(hdev);
2762
2763 /* check if we got any *new* reset requests to be honored */
2764 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2765 if (hdev->reset_type != HNAE3_NONE_RESET)
2766 hclge_do_reset(hdev);
2767
2768 hdev->reset_type = HNAE3_NONE_RESET;
2769 }
2770
2771 static void hclge_reset_service_task(struct work_struct *work)
2772 {
2773 struct hclge_dev *hdev =
2774 container_of(work, struct hclge_dev, rst_service_task);
2775
2776 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2777 return;
2778
2779 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2780
2781 hclge_reset_subtask(hdev);
2782
2783 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2784 }
2785
2786 static void hclge_mailbox_service_task(struct work_struct *work)
2787 {
2788 struct hclge_dev *hdev =
2789 container_of(work, struct hclge_dev, mbx_service_task);
2790
2791 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2792 return;
2793
2794 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2795
2796 hclge_mbx_handler(hdev);
2797
2798 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2799 }
2800
2801 static void hclge_service_task(struct work_struct *work)
2802 {
2803 struct hclge_dev *hdev =
2804 container_of(work, struct hclge_dev, service_task);
2805
2806 hclge_update_speed_duplex(hdev);
2807 hclge_update_link_status(hdev);
2808 hclge_update_stats_for_all(hdev);
2809 hclge_service_complete(hdev);
2810 }
2811
2812 static void hclge_disable_sriov(struct hclge_dev *hdev)
2813 {
2814 /* If our VFs are assigned we cannot shut down SR-IOV
2815 * without causing issues, so just leave the hardware
2816 * available but disabled
2817 */
2818 if (pci_vfs_assigned(hdev->pdev)) {
2819 dev_warn(&hdev->pdev->dev,
2820 "disabling driver while VFs are assigned\n");
2821 return;
2822 }
2823
2824 pci_disable_sriov(hdev->pdev);
2825 }
2826
2827 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2828 {
2829 /* VF handle has no client */
2830 if (!handle->client)
2831 return container_of(handle, struct hclge_vport, nic);
2832 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2833 return container_of(handle, struct hclge_vport, roce);
2834 else
2835 return container_of(handle, struct hclge_vport, nic);
2836 }
2837
2838 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2839 struct hnae3_vector_info *vector_info)
2840 {
2841 struct hclge_vport *vport = hclge_get_vport(handle);
2842 struct hnae3_vector_info *vector = vector_info;
2843 struct hclge_dev *hdev = vport->back;
2844 int alloc = 0;
2845 int i, j;
2846
2847 vector_num = min(hdev->num_msi_left, vector_num);
2848
2849 for (j = 0; j < vector_num; j++) {
2850 for (i = 1; i < hdev->num_msi; i++) {
2851 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2852 vector->vector = pci_irq_vector(hdev->pdev, i);
2853 vector->io_addr = hdev->hw.io_base +
2854 HCLGE_VECTOR_REG_BASE +
2855 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2856 vport->vport_id *
2857 HCLGE_VECTOR_VF_OFFSET;
2858 hdev->vector_status[i] = vport->vport_id;
2859 hdev->vector_irq[i] = vector->vector;
2860
2861 vector++;
2862 alloc++;
2863
2864 break;
2865 }
2866 }
2867 }
2868 hdev->num_msi_left -= alloc;
2869 hdev->num_msi_used += alloc;
2870
2871 return alloc;
2872 }
2873
2874 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2875 {
2876 int i;
2877
2878 for (i = 0; i < hdev->num_msi; i++)
2879 if (vector == hdev->vector_irq[i])
2880 return i;
2881
2882 return -EINVAL;
2883 }
2884
2885 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2886 {
2887 return HCLGE_RSS_KEY_SIZE;
2888 }
2889
2890 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2891 {
2892 return HCLGE_RSS_IND_TBL_SIZE;
2893 }
2894
2895 static int hclge_get_rss_algo(struct hclge_dev *hdev)
2896 {
2897 struct hclge_rss_config_cmd *req;
2898 struct hclge_desc desc;
2899 int rss_hash_algo;
2900 int ret;
2901
2902 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2903
2904 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2905 if (ret) {
2906 dev_err(&hdev->pdev->dev,
2907 "Get link status error, status =%d\n", ret);
2908 return ret;
2909 }
2910
2911 req = (struct hclge_rss_config_cmd *)desc.data;
2912 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2913
2914 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2915 return ETH_RSS_HASH_TOP;
2916
2917 return -EINVAL;
2918 }
2919
2920 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2921 const u8 hfunc, const u8 *key)
2922 {
2923 struct hclge_rss_config_cmd *req;
2924 struct hclge_desc desc;
2925 int key_offset;
2926 int key_size;
2927 int ret;
2928
2929 req = (struct hclge_rss_config_cmd *)desc.data;
2930
2931 for (key_offset = 0; key_offset < 3; key_offset++) {
2932 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2933 false);
2934
2935 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2936 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2937
2938 if (key_offset == 2)
2939 key_size =
2940 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2941 else
2942 key_size = HCLGE_RSS_HASH_KEY_NUM;
2943
2944 memcpy(req->hash_key,
2945 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2946
2947 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2948 if (ret) {
2949 dev_err(&hdev->pdev->dev,
2950 "Configure RSS config fail, status = %d\n",
2951 ret);
2952 return ret;
2953 }
2954 }
2955 return 0;
2956 }
2957
2958 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2959 {
2960 struct hclge_rss_indirection_table_cmd *req;
2961 struct hclge_desc desc;
2962 int i, j;
2963 int ret;
2964
2965 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
2966
2967 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2968 hclge_cmd_setup_basic_desc
2969 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2970
2971 req->start_table_index =
2972 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2973 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
2974
2975 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2976 req->rss_result[j] =
2977 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2978
2979 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2980 if (ret) {
2981 dev_err(&hdev->pdev->dev,
2982 "Configure rss indir table fail,status = %d\n",
2983 ret);
2984 return ret;
2985 }
2986 }
2987 return 0;
2988 }
2989
2990 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2991 u16 *tc_size, u16 *tc_offset)
2992 {
2993 struct hclge_rss_tc_mode_cmd *req;
2994 struct hclge_desc desc;
2995 int ret;
2996 int i;
2997
2998 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2999 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3000
3001 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3002 u16 mode = 0;
3003
3004 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3005 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3006 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3007 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3008 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3009
3010 req->rss_tc_mode[i] = cpu_to_le16(mode);
3011 }
3012
3013 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3014 if (ret) {
3015 dev_err(&hdev->pdev->dev,
3016 "Configure rss tc mode fail, status = %d\n", ret);
3017 return ret;
3018 }
3019
3020 return 0;
3021 }
3022
3023 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3024 {
3025 struct hclge_rss_input_tuple_cmd *req;
3026 struct hclge_desc desc;
3027 int ret;
3028
3029 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3030
3031 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3032 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3033 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3034 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3035 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3036 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3037 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3038 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3039 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3040 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3041 if (ret) {
3042 dev_err(&hdev->pdev->dev,
3043 "Configure rss input fail, status = %d\n", ret);
3044 return ret;
3045 }
3046
3047 return 0;
3048 }
3049
3050 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3051 u8 *key, u8 *hfunc)
3052 {
3053 struct hclge_vport *vport = hclge_get_vport(handle);
3054 struct hclge_dev *hdev = vport->back;
3055 int i;
3056
3057 /* Get hash algorithm */
3058 if (hfunc)
3059 *hfunc = hclge_get_rss_algo(hdev);
3060
3061 /* Get the RSS Key required by the user */
3062 if (key)
3063 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3064
3065 /* Get indirect table */
3066 if (indir)
3067 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3068 indir[i] = vport->rss_indirection_tbl[i];
3069
3070 return 0;
3071 }
3072
3073 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3074 const u8 *key, const u8 hfunc)
3075 {
3076 struct hclge_vport *vport = hclge_get_vport(handle);
3077 struct hclge_dev *hdev = vport->back;
3078 u8 hash_algo;
3079 int ret, i;
3080
3081 /* Set the RSS Hash Key if specififed by the user */
3082 if (key) {
3083 /* Update the shadow RSS key with user specified qids */
3084 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3085
3086 if (hfunc == ETH_RSS_HASH_TOP ||
3087 hfunc == ETH_RSS_HASH_NO_CHANGE)
3088 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3089 else
3090 return -EINVAL;
3091 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3092 if (ret)
3093 return ret;
3094 }
3095
3096 /* Update the shadow RSS table with user specified qids */
3097 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3098 vport->rss_indirection_tbl[i] = indir[i];
3099
3100 /* Update the hardware */
3101 ret = hclge_set_rss_indir_table(hdev, indir);
3102 return ret;
3103 }
3104
3105 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3106 {
3107 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3108
3109 if (nfc->data & RXH_L4_B_2_3)
3110 hash_sets |= HCLGE_D_PORT_BIT;
3111 else
3112 hash_sets &= ~HCLGE_D_PORT_BIT;
3113
3114 if (nfc->data & RXH_IP_SRC)
3115 hash_sets |= HCLGE_S_IP_BIT;
3116 else
3117 hash_sets &= ~HCLGE_S_IP_BIT;
3118
3119 if (nfc->data & RXH_IP_DST)
3120 hash_sets |= HCLGE_D_IP_BIT;
3121 else
3122 hash_sets &= ~HCLGE_D_IP_BIT;
3123
3124 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3125 hash_sets |= HCLGE_V_TAG_BIT;
3126
3127 return hash_sets;
3128 }
3129
3130 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3131 struct ethtool_rxnfc *nfc)
3132 {
3133 struct hclge_vport *vport = hclge_get_vport(handle);
3134 struct hclge_dev *hdev = vport->back;
3135 struct hclge_rss_input_tuple_cmd *req;
3136 struct hclge_desc desc;
3137 u8 tuple_sets;
3138 int ret;
3139
3140 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3141 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3142 return -EINVAL;
3143
3144 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3145 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3146 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3147 if (ret) {
3148 dev_err(&hdev->pdev->dev,
3149 "Read rss tuple fail, status = %d\n", ret);
3150 return ret;
3151 }
3152
3153 hclge_cmd_reuse_desc(&desc, false);
3154
3155 tuple_sets = hclge_get_rss_hash_bits(nfc);
3156 switch (nfc->flow_type) {
3157 case TCP_V4_FLOW:
3158 req->ipv4_tcp_en = tuple_sets;
3159 break;
3160 case TCP_V6_FLOW:
3161 req->ipv6_tcp_en = tuple_sets;
3162 break;
3163 case UDP_V4_FLOW:
3164 req->ipv4_udp_en = tuple_sets;
3165 break;
3166 case UDP_V6_FLOW:
3167 req->ipv6_udp_en = tuple_sets;
3168 break;
3169 case SCTP_V4_FLOW:
3170 req->ipv4_sctp_en = tuple_sets;
3171 break;
3172 case SCTP_V6_FLOW:
3173 if ((nfc->data & RXH_L4_B_0_1) ||
3174 (nfc->data & RXH_L4_B_2_3))
3175 return -EINVAL;
3176
3177 req->ipv6_sctp_en = tuple_sets;
3178 break;
3179 case IPV4_FLOW:
3180 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3181 break;
3182 case IPV6_FLOW:
3183 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3184 break;
3185 default:
3186 return -EINVAL;
3187 }
3188
3189 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3190 if (ret)
3191 dev_err(&hdev->pdev->dev,
3192 "Set rss tuple fail, status = %d\n", ret);
3193
3194 return ret;
3195 }
3196
3197 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3198 struct ethtool_rxnfc *nfc)
3199 {
3200 struct hclge_vport *vport = hclge_get_vport(handle);
3201 struct hclge_dev *hdev = vport->back;
3202 struct hclge_rss_input_tuple_cmd *req;
3203 struct hclge_desc desc;
3204 u8 tuple_sets;
3205 int ret;
3206
3207 nfc->data = 0;
3208
3209 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3210 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3211 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3212 if (ret) {
3213 dev_err(&hdev->pdev->dev,
3214 "Read rss tuple fail, status = %d\n", ret);
3215 return ret;
3216 }
3217
3218 switch (nfc->flow_type) {
3219 case TCP_V4_FLOW:
3220 tuple_sets = req->ipv4_tcp_en;
3221 break;
3222 case UDP_V4_FLOW:
3223 tuple_sets = req->ipv4_udp_en;
3224 break;
3225 case TCP_V6_FLOW:
3226 tuple_sets = req->ipv6_tcp_en;
3227 break;
3228 case UDP_V6_FLOW:
3229 tuple_sets = req->ipv6_udp_en;
3230 break;
3231 case SCTP_V4_FLOW:
3232 tuple_sets = req->ipv4_sctp_en;
3233 break;
3234 case SCTP_V6_FLOW:
3235 tuple_sets = req->ipv6_sctp_en;
3236 break;
3237 case IPV4_FLOW:
3238 case IPV6_FLOW:
3239 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3240 break;
3241 default:
3242 return -EINVAL;
3243 }
3244
3245 if (!tuple_sets)
3246 return 0;
3247
3248 if (tuple_sets & HCLGE_D_PORT_BIT)
3249 nfc->data |= RXH_L4_B_2_3;
3250 if (tuple_sets & HCLGE_S_PORT_BIT)
3251 nfc->data |= RXH_L4_B_0_1;
3252 if (tuple_sets & HCLGE_D_IP_BIT)
3253 nfc->data |= RXH_IP_DST;
3254 if (tuple_sets & HCLGE_S_IP_BIT)
3255 nfc->data |= RXH_IP_SRC;
3256
3257 return 0;
3258 }
3259
3260 static int hclge_get_tc_size(struct hnae3_handle *handle)
3261 {
3262 struct hclge_vport *vport = hclge_get_vport(handle);
3263 struct hclge_dev *hdev = vport->back;
3264
3265 return hdev->rss_size_max;
3266 }
3267
3268 int hclge_rss_init_hw(struct hclge_dev *hdev)
3269 {
3270 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3271 struct hclge_vport *vport = hdev->vport;
3272 u16 tc_offset[HCLGE_MAX_TC_NUM];
3273 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3274 u16 tc_valid[HCLGE_MAX_TC_NUM];
3275 u16 tc_size[HCLGE_MAX_TC_NUM];
3276 u32 *rss_indir = NULL;
3277 u16 rss_size = 0, roundup_size;
3278 const u8 *key;
3279 int i, ret, j;
3280
3281 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3282 if (!rss_indir)
3283 return -ENOMEM;
3284
3285 /* Get default RSS key */
3286 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3287
3288 /* Initialize RSS indirect table for each vport */
3289 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3290 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3291 vport[j].rss_indirection_tbl[i] =
3292 i % vport[j].alloc_rss_size;
3293
3294 /* vport 0 is for PF */
3295 if (j != 0)
3296 continue;
3297
3298 rss_size = vport[j].alloc_rss_size;
3299 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3300 }
3301 }
3302 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3303 if (ret)
3304 goto err;
3305
3306 key = rss_key;
3307 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3308 if (ret)
3309 goto err;
3310
3311 ret = hclge_set_rss_input_tuple(hdev);
3312 if (ret)
3313 goto err;
3314
3315 /* Each TC have the same queue size, and tc_size set to hardware is
3316 * the log2 of roundup power of two of rss_size, the acutal queue
3317 * size is limited by indirection table.
3318 */
3319 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3320 dev_err(&hdev->pdev->dev,
3321 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3322 rss_size);
3323 ret = -EINVAL;
3324 goto err;
3325 }
3326
3327 roundup_size = roundup_pow_of_two(rss_size);
3328 roundup_size = ilog2(roundup_size);
3329
3330 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3331 tc_valid[i] = 0;
3332
3333 if (!(hdev->hw_tc_map & BIT(i)))
3334 continue;
3335
3336 tc_valid[i] = 1;
3337 tc_size[i] = roundup_size;
3338 tc_offset[i] = rss_size * i;
3339 }
3340
3341 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3342
3343 err:
3344 kfree(rss_indir);
3345
3346 return ret;
3347 }
3348
3349 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3350 int vector_id, bool en,
3351 struct hnae3_ring_chain_node *ring_chain)
3352 {
3353 struct hclge_dev *hdev = vport->back;
3354 struct hnae3_ring_chain_node *node;
3355 struct hclge_desc desc;
3356 struct hclge_ctrl_vector_chain_cmd *req
3357 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3358 enum hclge_cmd_status status;
3359 enum hclge_opcode_type op;
3360 u16 tqp_type_and_id;
3361 int i;
3362
3363 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3364 hclge_cmd_setup_basic_desc(&desc, op, false);
3365 req->int_vector_id = vector_id;
3366
3367 i = 0;
3368 for (node = ring_chain; node; node = node->next) {
3369 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3370 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3371 HCLGE_INT_TYPE_S,
3372 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3373 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3374 HCLGE_TQP_ID_S, node->tqp_index);
3375 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3376 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3377 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3378 req->vfid = vport->vport_id;
3379
3380 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3381 if (status) {
3382 dev_err(&hdev->pdev->dev,
3383 "Map TQP fail, status is %d.\n",
3384 status);
3385 return -EIO;
3386 }
3387 i = 0;
3388
3389 hclge_cmd_setup_basic_desc(&desc,
3390 op,
3391 false);
3392 req->int_vector_id = vector_id;
3393 }
3394 }
3395
3396 if (i > 0) {
3397 req->int_cause_num = i;
3398 req->vfid = vport->vport_id;
3399 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3400 if (status) {
3401 dev_err(&hdev->pdev->dev,
3402 "Map TQP fail, status is %d.\n", status);
3403 return -EIO;
3404 }
3405 }
3406
3407 return 0;
3408 }
3409
3410 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3411 int vector,
3412 struct hnae3_ring_chain_node *ring_chain)
3413 {
3414 struct hclge_vport *vport = hclge_get_vport(handle);
3415 struct hclge_dev *hdev = vport->back;
3416 int vector_id;
3417
3418 vector_id = hclge_get_vector_index(hdev, vector);
3419 if (vector_id < 0) {
3420 dev_err(&hdev->pdev->dev,
3421 "Get vector index fail. vector_id =%d\n", vector_id);
3422 return vector_id;
3423 }
3424
3425 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3426 }
3427
3428 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3429 int vector,
3430 struct hnae3_ring_chain_node *ring_chain)
3431 {
3432 struct hclge_vport *vport = hclge_get_vport(handle);
3433 struct hclge_dev *hdev = vport->back;
3434 int vector_id, ret;
3435
3436 vector_id = hclge_get_vector_index(hdev, vector);
3437 if (vector_id < 0) {
3438 dev_err(&handle->pdev->dev,
3439 "Get vector index fail. ret =%d\n", vector_id);
3440 return vector_id;
3441 }
3442
3443 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3444 if (ret) {
3445 dev_err(&handle->pdev->dev,
3446 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3447 vector_id,
3448 ret);
3449 return ret;
3450 }
3451
3452 /* Free this MSIX or MSI vector */
3453 hclge_free_vector(hdev, vector_id);
3454
3455 return 0;
3456 }
3457
3458 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3459 struct hclge_promisc_param *param)
3460 {
3461 struct hclge_promisc_cfg_cmd *req;
3462 struct hclge_desc desc;
3463 int ret;
3464
3465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3466
3467 req = (struct hclge_promisc_cfg_cmd *)desc.data;
3468 req->vf_id = param->vf_id;
3469 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3470
3471 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3472 if (ret) {
3473 dev_err(&hdev->pdev->dev,
3474 "Set promisc mode fail, status is %d.\n", ret);
3475 return ret;
3476 }
3477 return 0;
3478 }
3479
3480 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3481 bool en_mc, bool en_bc, int vport_id)
3482 {
3483 if (!param)
3484 return;
3485
3486 memset(param, 0, sizeof(struct hclge_promisc_param));
3487 if (en_uc)
3488 param->enable = HCLGE_PROMISC_EN_UC;
3489 if (en_mc)
3490 param->enable |= HCLGE_PROMISC_EN_MC;
3491 if (en_bc)
3492 param->enable |= HCLGE_PROMISC_EN_BC;
3493 param->vf_id = vport_id;
3494 }
3495
3496 static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3497 {
3498 struct hclge_vport *vport = hclge_get_vport(handle);
3499 struct hclge_dev *hdev = vport->back;
3500 struct hclge_promisc_param param;
3501
3502 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3503 hclge_cmd_set_promisc_mode(hdev, &param);
3504 }
3505
3506 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3507 {
3508 struct hclge_desc desc;
3509 struct hclge_config_mac_mode_cmd *req =
3510 (struct hclge_config_mac_mode_cmd *)desc.data;
3511 u32 loop_en = 0;
3512 int ret;
3513
3514 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3515 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3516 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3517 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3518 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3519 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3520 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3521 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3522 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3523 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3524 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3525 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3526 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3527 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3528 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3529 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3530
3531 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3532 if (ret)
3533 dev_err(&hdev->pdev->dev,
3534 "mac enable fail, ret =%d.\n", ret);
3535 }
3536
3537 static int hclge_set_loopback(struct hnae3_handle *handle,
3538 enum hnae3_loop loop_mode, bool en)
3539 {
3540 struct hclge_vport *vport = hclge_get_vport(handle);
3541 struct hclge_config_mac_mode_cmd *req;
3542 struct hclge_dev *hdev = vport->back;
3543 struct hclge_desc desc;
3544 u32 loop_en;
3545 int ret;
3546
3547 switch (loop_mode) {
3548 case HNAE3_MAC_INTER_LOOP_MAC:
3549 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3550 /* 1 Read out the MAC mode config at first */
3551 hclge_cmd_setup_basic_desc(&desc,
3552 HCLGE_OPC_CONFIG_MAC_MODE,
3553 true);
3554 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3555 if (ret) {
3556 dev_err(&hdev->pdev->dev,
3557 "mac loopback get fail, ret =%d.\n",
3558 ret);
3559 return ret;
3560 }
3561
3562 /* 2 Then setup the loopback flag */
3563 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3564 if (en)
3565 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3566 else
3567 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3568
3569 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3570
3571 /* 3 Config mac work mode with loopback flag
3572 * and its original configure parameters
3573 */
3574 hclge_cmd_reuse_desc(&desc, false);
3575 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3576 if (ret)
3577 dev_err(&hdev->pdev->dev,
3578 "mac loopback set fail, ret =%d.\n", ret);
3579 break;
3580 default:
3581 ret = -ENOTSUPP;
3582 dev_err(&hdev->pdev->dev,
3583 "loop_mode %d is not supported\n", loop_mode);
3584 break;
3585 }
3586
3587 return ret;
3588 }
3589
3590 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3591 int stream_id, bool enable)
3592 {
3593 struct hclge_desc desc;
3594 struct hclge_cfg_com_tqp_queue_cmd *req =
3595 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3596 int ret;
3597
3598 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3599 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3600 req->stream_id = cpu_to_le16(stream_id);
3601 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3602
3603 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3604 if (ret)
3605 dev_err(&hdev->pdev->dev,
3606 "Tqp enable fail, status =%d.\n", ret);
3607 return ret;
3608 }
3609
3610 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3611 {
3612 struct hclge_vport *vport = hclge_get_vport(handle);
3613 struct hnae3_queue *queue;
3614 struct hclge_tqp *tqp;
3615 int i;
3616
3617 for (i = 0; i < vport->alloc_tqps; i++) {
3618 queue = handle->kinfo.tqp[i];
3619 tqp = container_of(queue, struct hclge_tqp, q);
3620 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3621 }
3622 }
3623
3624 static int hclge_ae_start(struct hnae3_handle *handle)
3625 {
3626 struct hclge_vport *vport = hclge_get_vport(handle);
3627 struct hclge_dev *hdev = vport->back;
3628 int i, queue_id, ret;
3629
3630 for (i = 0; i < vport->alloc_tqps; i++) {
3631 /* todo clear interrupt */
3632 /* ring enable */
3633 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3634 if (queue_id < 0) {
3635 dev_warn(&hdev->pdev->dev,
3636 "Get invalid queue id, ignore it\n");
3637 continue;
3638 }
3639
3640 hclge_tqp_enable(hdev, queue_id, 0, true);
3641 }
3642 /* mac enable */
3643 hclge_cfg_mac_mode(hdev, true);
3644 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3645 mod_timer(&hdev->service_timer, jiffies + HZ);
3646
3647 ret = hclge_mac_start_phy(hdev);
3648 if (ret)
3649 return ret;
3650
3651 /* reset tqp stats */
3652 hclge_reset_tqp_stats(handle);
3653
3654 return 0;
3655 }
3656
3657 static void hclge_ae_stop(struct hnae3_handle *handle)
3658 {
3659 struct hclge_vport *vport = hclge_get_vport(handle);
3660 struct hclge_dev *hdev = vport->back;
3661 int i, queue_id;
3662
3663 for (i = 0; i < vport->alloc_tqps; i++) {
3664 /* Ring disable */
3665 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3666 if (queue_id < 0) {
3667 dev_warn(&hdev->pdev->dev,
3668 "Get invalid queue id, ignore it\n");
3669 continue;
3670 }
3671
3672 hclge_tqp_enable(hdev, queue_id, 0, false);
3673 }
3674 /* Mac disable */
3675 hclge_cfg_mac_mode(hdev, false);
3676
3677 hclge_mac_stop_phy(hdev);
3678
3679 /* reset tqp stats */
3680 hclge_reset_tqp_stats(handle);
3681 }
3682
3683 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3684 u16 cmdq_resp, u8 resp_code,
3685 enum hclge_mac_vlan_tbl_opcode op)
3686 {
3687 struct hclge_dev *hdev = vport->back;
3688 int return_status = -EIO;
3689
3690 if (cmdq_resp) {
3691 dev_err(&hdev->pdev->dev,
3692 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3693 cmdq_resp);
3694 return -EIO;
3695 }
3696
3697 if (op == HCLGE_MAC_VLAN_ADD) {
3698 if ((!resp_code) || (resp_code == 1)) {
3699 return_status = 0;
3700 } else if (resp_code == 2) {
3701 return_status = -EIO;
3702 dev_err(&hdev->pdev->dev,
3703 "add mac addr failed for uc_overflow.\n");
3704 } else if (resp_code == 3) {
3705 return_status = -EIO;
3706 dev_err(&hdev->pdev->dev,
3707 "add mac addr failed for mc_overflow.\n");
3708 } else {
3709 dev_err(&hdev->pdev->dev,
3710 "add mac addr failed for undefined, code=%d.\n",
3711 resp_code);
3712 }
3713 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3714 if (!resp_code) {
3715 return_status = 0;
3716 } else if (resp_code == 1) {
3717 return_status = -EIO;
3718 dev_dbg(&hdev->pdev->dev,
3719 "remove mac addr failed for miss.\n");
3720 } else {
3721 dev_err(&hdev->pdev->dev,
3722 "remove mac addr failed for undefined, code=%d.\n",
3723 resp_code);
3724 }
3725 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3726 if (!resp_code) {
3727 return_status = 0;
3728 } else if (resp_code == 1) {
3729 return_status = -EIO;
3730 dev_dbg(&hdev->pdev->dev,
3731 "lookup mac addr failed for miss.\n");
3732 } else {
3733 dev_err(&hdev->pdev->dev,
3734 "lookup mac addr failed for undefined, code=%d.\n",
3735 resp_code);
3736 }
3737 } else {
3738 return_status = -EIO;
3739 dev_err(&hdev->pdev->dev,
3740 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3741 op);
3742 }
3743
3744 return return_status;
3745 }
3746
3747 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3748 {
3749 int word_num;
3750 int bit_num;
3751
3752 if (vfid > 255 || vfid < 0)
3753 return -EIO;
3754
3755 if (vfid >= 0 && vfid <= 191) {
3756 word_num = vfid / 32;
3757 bit_num = vfid % 32;
3758 if (clr)
3759 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3760 else
3761 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3762 } else {
3763 word_num = (vfid - 192) / 32;
3764 bit_num = vfid % 32;
3765 if (clr)
3766 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3767 else
3768 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3769 }
3770
3771 return 0;
3772 }
3773
3774 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3775 {
3776 #define HCLGE_DESC_NUMBER 3
3777 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3778 int i, j;
3779
3780 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3781 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3782 if (desc[i].data[j])
3783 return false;
3784
3785 return true;
3786 }
3787
3788 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3789 const u8 *addr)
3790 {
3791 const unsigned char *mac_addr = addr;
3792 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3793 (mac_addr[0]) | (mac_addr[1] << 8);
3794 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3795
3796 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3797 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3798 }
3799
3800 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3801 const u8 *addr)
3802 {
3803 u16 high_val = addr[1] | (addr[0] << 8);
3804 struct hclge_dev *hdev = vport->back;
3805 u32 rsh = 4 - hdev->mta_mac_sel_type;
3806 u16 ret_val = (high_val >> rsh) & 0xfff;
3807
3808 return ret_val;
3809 }
3810
3811 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3812 enum hclge_mta_dmac_sel_type mta_mac_sel,
3813 bool enable)
3814 {
3815 struct hclge_mta_filter_mode_cmd *req;
3816 struct hclge_desc desc;
3817 int ret;
3818
3819 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3820 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3821
3822 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3823 enable);
3824 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3825 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3826
3827 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3828 if (ret) {
3829 dev_err(&hdev->pdev->dev,
3830 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3831 ret);
3832 return ret;
3833 }
3834
3835 return 0;
3836 }
3837
3838 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3839 u8 func_id,
3840 bool enable)
3841 {
3842 struct hclge_cfg_func_mta_filter_cmd *req;
3843 struct hclge_desc desc;
3844 int ret;
3845
3846 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3847 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3848
3849 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3850 enable);
3851 req->function_id = func_id;
3852
3853 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3854 if (ret) {
3855 dev_err(&hdev->pdev->dev,
3856 "Config func_id enable failed for cmd_send, ret =%d.\n",
3857 ret);
3858 return ret;
3859 }
3860
3861 return 0;
3862 }
3863
3864 static int hclge_set_mta_table_item(struct hclge_vport *vport,
3865 u16 idx,
3866 bool enable)
3867 {
3868 struct hclge_dev *hdev = vport->back;
3869 struct hclge_cfg_func_mta_item_cmd *req;
3870 struct hclge_desc desc;
3871 u16 item_idx = 0;
3872 int ret;
3873
3874 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
3875 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3876 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3877
3878 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3879 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3880 req->item_idx = cpu_to_le16(item_idx);
3881
3882 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3883 if (ret) {
3884 dev_err(&hdev->pdev->dev,
3885 "Config mta table item failed for cmd_send, ret =%d.\n",
3886 ret);
3887 return ret;
3888 }
3889
3890 return 0;
3891 }
3892
3893 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3894 struct hclge_mac_vlan_tbl_entry_cmd *req)
3895 {
3896 struct hclge_dev *hdev = vport->back;
3897 struct hclge_desc desc;
3898 u8 resp_code;
3899 u16 retval;
3900 int ret;
3901
3902 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3903
3904 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3905
3906 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3907 if (ret) {
3908 dev_err(&hdev->pdev->dev,
3909 "del mac addr failed for cmd_send, ret =%d.\n",
3910 ret);
3911 return ret;
3912 }
3913 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3914 retval = le16_to_cpu(desc.retval);
3915
3916 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3917 HCLGE_MAC_VLAN_REMOVE);
3918 }
3919
3920 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3921 struct hclge_mac_vlan_tbl_entry_cmd *req,
3922 struct hclge_desc *desc,
3923 bool is_mc)
3924 {
3925 struct hclge_dev *hdev = vport->back;
3926 u8 resp_code;
3927 u16 retval;
3928 int ret;
3929
3930 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3931 if (is_mc) {
3932 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3933 memcpy(desc[0].data,
3934 req,
3935 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3936 hclge_cmd_setup_basic_desc(&desc[1],
3937 HCLGE_OPC_MAC_VLAN_ADD,
3938 true);
3939 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3940 hclge_cmd_setup_basic_desc(&desc[2],
3941 HCLGE_OPC_MAC_VLAN_ADD,
3942 true);
3943 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3944 } else {
3945 memcpy(desc[0].data,
3946 req,
3947 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3948 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3949 }
3950 if (ret) {
3951 dev_err(&hdev->pdev->dev,
3952 "lookup mac addr failed for cmd_send, ret =%d.\n",
3953 ret);
3954 return ret;
3955 }
3956 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3957 retval = le16_to_cpu(desc[0].retval);
3958
3959 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3960 HCLGE_MAC_VLAN_LKUP);
3961 }
3962
3963 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3964 struct hclge_mac_vlan_tbl_entry_cmd *req,
3965 struct hclge_desc *mc_desc)
3966 {
3967 struct hclge_dev *hdev = vport->back;
3968 int cfg_status;
3969 u8 resp_code;
3970 u16 retval;
3971 int ret;
3972
3973 if (!mc_desc) {
3974 struct hclge_desc desc;
3975
3976 hclge_cmd_setup_basic_desc(&desc,
3977 HCLGE_OPC_MAC_VLAN_ADD,
3978 false);
3979 memcpy(desc.data, req,
3980 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3981 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3982 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3983 retval = le16_to_cpu(desc.retval);
3984
3985 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
3986 resp_code,
3987 HCLGE_MAC_VLAN_ADD);
3988 } else {
3989 hclge_cmd_reuse_desc(&mc_desc[0], false);
3990 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3991 hclge_cmd_reuse_desc(&mc_desc[1], false);
3992 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3993 hclge_cmd_reuse_desc(&mc_desc[2], false);
3994 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3995 memcpy(mc_desc[0].data, req,
3996 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3997 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
3998 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3999 retval = le16_to_cpu(mc_desc[0].retval);
4000
4001 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4002 resp_code,
4003 HCLGE_MAC_VLAN_ADD);
4004 }
4005
4006 if (ret) {
4007 dev_err(&hdev->pdev->dev,
4008 "add mac addr failed for cmd_send, ret =%d.\n",
4009 ret);
4010 return ret;
4011 }
4012
4013 return cfg_status;
4014 }
4015
4016 static int hclge_add_uc_addr(struct hnae3_handle *handle,
4017 const unsigned char *addr)
4018 {
4019 struct hclge_vport *vport = hclge_get_vport(handle);
4020
4021 return hclge_add_uc_addr_common(vport, addr);
4022 }
4023
4024 int hclge_add_uc_addr_common(struct hclge_vport *vport,
4025 const unsigned char *addr)
4026 {
4027 struct hclge_dev *hdev = vport->back;
4028 struct hclge_mac_vlan_tbl_entry_cmd req;
4029 enum hclge_cmd_status status;
4030 u16 egress_port = 0;
4031
4032 /* mac addr check */
4033 if (is_zero_ether_addr(addr) ||
4034 is_broadcast_ether_addr(addr) ||
4035 is_multicast_ether_addr(addr)) {
4036 dev_err(&hdev->pdev->dev,
4037 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4038 addr,
4039 is_zero_ether_addr(addr),
4040 is_broadcast_ether_addr(addr),
4041 is_multicast_ether_addr(addr));
4042 return -EINVAL;
4043 }
4044
4045 memset(&req, 0, sizeof(req));
4046 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4047 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4048 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4049 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4050
4051 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4052 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4053 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4054 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4055 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
4056 HCLGE_MAC_EPORT_PFID_S, 0);
4057
4058 req.egress_port = cpu_to_le16(egress_port);
4059
4060 hclge_prepare_mac_addr(&req, addr);
4061
4062 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4063
4064 return status;
4065 }
4066
4067 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4068 const unsigned char *addr)
4069 {
4070 struct hclge_vport *vport = hclge_get_vport(handle);
4071
4072 return hclge_rm_uc_addr_common(vport, addr);
4073 }
4074
4075 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4076 const unsigned char *addr)
4077 {
4078 struct hclge_dev *hdev = vport->back;
4079 struct hclge_mac_vlan_tbl_entry_cmd req;
4080 enum hclge_cmd_status status;
4081
4082 /* mac addr check */
4083 if (is_zero_ether_addr(addr) ||
4084 is_broadcast_ether_addr(addr) ||
4085 is_multicast_ether_addr(addr)) {
4086 dev_dbg(&hdev->pdev->dev,
4087 "Remove mac err! invalid mac:%pM.\n",
4088 addr);
4089 return -EINVAL;
4090 }
4091
4092 memset(&req, 0, sizeof(req));
4093 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4094 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4095 hclge_prepare_mac_addr(&req, addr);
4096 status = hclge_remove_mac_vlan_tbl(vport, &req);
4097
4098 return status;
4099 }
4100
4101 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4102 const unsigned char *addr)
4103 {
4104 struct hclge_vport *vport = hclge_get_vport(handle);
4105
4106 return hclge_add_mc_addr_common(vport, addr);
4107 }
4108
4109 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4110 const unsigned char *addr)
4111 {
4112 struct hclge_dev *hdev = vport->back;
4113 struct hclge_mac_vlan_tbl_entry_cmd req;
4114 struct hclge_desc desc[3];
4115 u16 tbl_idx;
4116 int status;
4117
4118 /* mac addr check */
4119 if (!is_multicast_ether_addr(addr)) {
4120 dev_err(&hdev->pdev->dev,
4121 "Add mc mac err! invalid mac:%pM.\n",
4122 addr);
4123 return -EINVAL;
4124 }
4125 memset(&req, 0, sizeof(req));
4126 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4127 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4128 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4129 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4130 hclge_prepare_mac_addr(&req, addr);
4131 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4132 if (!status) {
4133 /* This mac addr exist, update VFID for it */
4134 hclge_update_desc_vfid(desc, vport->vport_id, false);
4135 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4136 } else {
4137 /* This mac addr do not exist, add new entry for it */
4138 memset(desc[0].data, 0, sizeof(desc[0].data));
4139 memset(desc[1].data, 0, sizeof(desc[0].data));
4140 memset(desc[2].data, 0, sizeof(desc[0].data));
4141 hclge_update_desc_vfid(desc, vport->vport_id, false);
4142 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4143 }
4144
4145 /* Set MTA table for this MAC address */
4146 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4147 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4148
4149 return status;
4150 }
4151
4152 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4153 const unsigned char *addr)
4154 {
4155 struct hclge_vport *vport = hclge_get_vport(handle);
4156
4157 return hclge_rm_mc_addr_common(vport, addr);
4158 }
4159
4160 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4161 const unsigned char *addr)
4162 {
4163 struct hclge_dev *hdev = vport->back;
4164 struct hclge_mac_vlan_tbl_entry_cmd req;
4165 enum hclge_cmd_status status;
4166 struct hclge_desc desc[3];
4167 u16 tbl_idx;
4168
4169 /* mac addr check */
4170 if (!is_multicast_ether_addr(addr)) {
4171 dev_dbg(&hdev->pdev->dev,
4172 "Remove mc mac err! invalid mac:%pM.\n",
4173 addr);
4174 return -EINVAL;
4175 }
4176
4177 memset(&req, 0, sizeof(req));
4178 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4179 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4180 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4181 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4182 hclge_prepare_mac_addr(&req, addr);
4183 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4184 if (!status) {
4185 /* This mac addr exist, remove this handle's VFID for it */
4186 hclge_update_desc_vfid(desc, vport->vport_id, true);
4187
4188 if (hclge_is_all_function_id_zero(desc))
4189 /* All the vfid is zero, so need to delete this entry */
4190 status = hclge_remove_mac_vlan_tbl(vport, &req);
4191 else
4192 /* Not all the vfid is zero, update the vfid */
4193 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4194
4195 } else {
4196 /* This mac addr do not exist, can't delete it */
4197 dev_err(&hdev->pdev->dev,
4198 "Rm multicast mac addr failed, ret = %d.\n",
4199 status);
4200 return -EIO;
4201 }
4202
4203 /* Set MTB table for this MAC address */
4204 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4205 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4206
4207 return status;
4208 }
4209
4210 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4211 {
4212 struct hclge_vport *vport = hclge_get_vport(handle);
4213 struct hclge_dev *hdev = vport->back;
4214
4215 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4216 }
4217
4218 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4219 {
4220 const unsigned char *new_addr = (const unsigned char *)p;
4221 struct hclge_vport *vport = hclge_get_vport(handle);
4222 struct hclge_dev *hdev = vport->back;
4223
4224 /* mac addr check */
4225 if (is_zero_ether_addr(new_addr) ||
4226 is_broadcast_ether_addr(new_addr) ||
4227 is_multicast_ether_addr(new_addr)) {
4228 dev_err(&hdev->pdev->dev,
4229 "Change uc mac err! invalid mac:%p.\n",
4230 new_addr);
4231 return -EINVAL;
4232 }
4233
4234 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4235
4236 if (!hclge_add_uc_addr(handle, new_addr)) {
4237 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4238 return 0;
4239 }
4240
4241 return -EIO;
4242 }
4243
4244 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4245 bool filter_en)
4246 {
4247 struct hclge_vlan_filter_ctrl_cmd *req;
4248 struct hclge_desc desc;
4249 int ret;
4250
4251 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4252
4253 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4254 req->vlan_type = vlan_type;
4255 req->vlan_fe = filter_en;
4256
4257 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4258 if (ret) {
4259 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4260 ret);
4261 return ret;
4262 }
4263
4264 return 0;
4265 }
4266
4267 int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4268 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4269 {
4270 #define HCLGE_MAX_VF_BYTES 16
4271 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4272 struct hclge_vlan_filter_vf_cfg_cmd *req1;
4273 struct hclge_desc desc[2];
4274 u8 vf_byte_val;
4275 u8 vf_byte_off;
4276 int ret;
4277
4278 hclge_cmd_setup_basic_desc(&desc[0],
4279 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4280 hclge_cmd_setup_basic_desc(&desc[1],
4281 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4282
4283 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4284
4285 vf_byte_off = vfid / 8;
4286 vf_byte_val = 1 << (vfid % 8);
4287
4288 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4289 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4290
4291 req0->vlan_id = cpu_to_le16(vlan);
4292 req0->vlan_cfg = is_kill;
4293
4294 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4295 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4296 else
4297 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4298
4299 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4300 if (ret) {
4301 dev_err(&hdev->pdev->dev,
4302 "Send vf vlan command fail, ret =%d.\n",
4303 ret);
4304 return ret;
4305 }
4306
4307 if (!is_kill) {
4308 if (!req0->resp_code || req0->resp_code == 1)
4309 return 0;
4310
4311 dev_err(&hdev->pdev->dev,
4312 "Add vf vlan filter fail, ret =%d.\n",
4313 req0->resp_code);
4314 } else {
4315 if (!req0->resp_code)
4316 return 0;
4317
4318 dev_err(&hdev->pdev->dev,
4319 "Kill vf vlan filter fail, ret =%d.\n",
4320 req0->resp_code);
4321 }
4322
4323 return -EIO;
4324 }
4325
4326 static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4327 __be16 proto, u16 vlan_id,
4328 bool is_kill)
4329 {
4330 struct hclge_vport *vport = hclge_get_vport(handle);
4331 struct hclge_dev *hdev = vport->back;
4332 struct hclge_vlan_filter_pf_cfg_cmd *req;
4333 struct hclge_desc desc;
4334 u8 vlan_offset_byte_val;
4335 u8 vlan_offset_byte;
4336 u8 vlan_offset_160;
4337 int ret;
4338
4339 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4340
4341 vlan_offset_160 = vlan_id / 160;
4342 vlan_offset_byte = (vlan_id % 160) / 8;
4343 vlan_offset_byte_val = 1 << (vlan_id % 8);
4344
4345 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4346 req->vlan_offset = vlan_offset_160;
4347 req->vlan_cfg = is_kill;
4348 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4349
4350 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4351 if (ret) {
4352 dev_err(&hdev->pdev->dev,
4353 "port vlan command, send fail, ret =%d.\n",
4354 ret);
4355 return ret;
4356 }
4357
4358 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4359 if (ret) {
4360 dev_err(&hdev->pdev->dev,
4361 "Set pf vlan filter config fail, ret =%d.\n",
4362 ret);
4363 return -EIO;
4364 }
4365
4366 return 0;
4367 }
4368
4369 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4370 u16 vlan, u8 qos, __be16 proto)
4371 {
4372 struct hclge_vport *vport = hclge_get_vport(handle);
4373 struct hclge_dev *hdev = vport->back;
4374
4375 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4376 return -EINVAL;
4377 if (proto != htons(ETH_P_8021Q))
4378 return -EPROTONOSUPPORT;
4379
4380 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4381 }
4382
4383 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4384 {
4385 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4386 struct hclge_vport_vtag_tx_cfg_cmd *req;
4387 struct hclge_dev *hdev = vport->back;
4388 struct hclge_desc desc;
4389 int status;
4390
4391 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4392
4393 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4394 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4395 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4396 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B,
4397 vcfg->accept_tag ? 1 : 0);
4398 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B,
4399 vcfg->accept_untag ? 1 : 0);
4400 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4401 vcfg->insert_tag1_en ? 1 : 0);
4402 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4403 vcfg->insert_tag2_en ? 1 : 0);
4404 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4405
4406 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4407 req->vf_bitmap[req->vf_offset] =
4408 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4409
4410 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4411 if (status)
4412 dev_err(&hdev->pdev->dev,
4413 "Send port txvlan cfg command fail, ret =%d\n",
4414 status);
4415
4416 return status;
4417 }
4418
4419 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4420 {
4421 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4422 struct hclge_vport_vtag_rx_cfg_cmd *req;
4423 struct hclge_dev *hdev = vport->back;
4424 struct hclge_desc desc;
4425 int status;
4426
4427 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4428
4429 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4430 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4431 vcfg->strip_tag1_en ? 1 : 0);
4432 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4433 vcfg->strip_tag2_en ? 1 : 0);
4434 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4435 vcfg->vlan1_vlan_prionly ? 1 : 0);
4436 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4437 vcfg->vlan2_vlan_prionly ? 1 : 0);
4438
4439 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4440 req->vf_bitmap[req->vf_offset] =
4441 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4442
4443 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4444 if (status)
4445 dev_err(&hdev->pdev->dev,
4446 "Send port rxvlan cfg command fail, ret =%d\n",
4447 status);
4448
4449 return status;
4450 }
4451
4452 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4453 {
4454 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4455 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4456 struct hclge_desc desc;
4457 int status;
4458
4459 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4460 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4461 rx_req->ot_fst_vlan_type =
4462 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4463 rx_req->ot_sec_vlan_type =
4464 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4465 rx_req->in_fst_vlan_type =
4466 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4467 rx_req->in_sec_vlan_type =
4468 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4469
4470 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4471 if (status) {
4472 dev_err(&hdev->pdev->dev,
4473 "Send rxvlan protocol type command fail, ret =%d\n",
4474 status);
4475 return status;
4476 }
4477
4478 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4479
4480 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4481 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4482 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4483
4484 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4485 if (status)
4486 dev_err(&hdev->pdev->dev,
4487 "Send txvlan protocol type command fail, ret =%d\n",
4488 status);
4489
4490 return status;
4491 }
4492
4493 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4494 {
4495 #define HCLGE_FILTER_TYPE_VF 0
4496 #define HCLGE_FILTER_TYPE_PORT 1
4497 #define HCLGE_DEF_VLAN_TYPE 0x8100
4498
4499 struct hnae3_handle *handle;
4500 struct hclge_vport *vport;
4501 int ret;
4502 int i;
4503
4504 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4505 if (ret)
4506 return ret;
4507
4508 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
4509 if (ret)
4510 return ret;
4511
4512 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4513 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4514 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4515 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4516 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4517 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4518
4519 ret = hclge_set_vlan_protocol_type(hdev);
4520 if (ret)
4521 return ret;
4522
4523 for (i = 0; i < hdev->num_alloc_vport; i++) {
4524 vport = &hdev->vport[i];
4525 vport->txvlan_cfg.accept_tag = true;
4526 vport->txvlan_cfg.accept_untag = true;
4527 vport->txvlan_cfg.insert_tag1_en = false;
4528 vport->txvlan_cfg.insert_tag2_en = false;
4529 vport->txvlan_cfg.default_tag1 = 0;
4530 vport->txvlan_cfg.default_tag2 = 0;
4531
4532 ret = hclge_set_vlan_tx_offload_cfg(vport);
4533 if (ret)
4534 return ret;
4535
4536 vport->rxvlan_cfg.strip_tag1_en = false;
4537 vport->rxvlan_cfg.strip_tag2_en = true;
4538 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4539 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4540
4541 ret = hclge_set_vlan_rx_offload_cfg(vport);
4542 if (ret)
4543 return ret;
4544 }
4545
4546 handle = &hdev->vport[0].nic;
4547 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4548 }
4549
4550 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4551 {
4552 struct hclge_vport *vport = hclge_get_vport(handle);
4553
4554 vport->rxvlan_cfg.strip_tag1_en = false;
4555 vport->rxvlan_cfg.strip_tag2_en = enable;
4556 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4557 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4558
4559 return hclge_set_vlan_rx_offload_cfg(vport);
4560 }
4561
4562 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4563 {
4564 struct hclge_vport *vport = hclge_get_vport(handle);
4565 struct hclge_config_max_frm_size_cmd *req;
4566 struct hclge_dev *hdev = vport->back;
4567 struct hclge_desc desc;
4568 int ret;
4569
4570 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
4571 return -EINVAL;
4572
4573 hdev->mps = new_mtu;
4574 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4575
4576 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
4577 req->max_frm_size = cpu_to_le16(new_mtu);
4578
4579 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4580 if (ret) {
4581 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4582 return ret;
4583 }
4584
4585 return 0;
4586 }
4587
4588 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4589 bool enable)
4590 {
4591 struct hclge_reset_tqp_queue_cmd *req;
4592 struct hclge_desc desc;
4593 int ret;
4594
4595 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4596
4597 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4598 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4599 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4600
4601 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4602 if (ret) {
4603 dev_err(&hdev->pdev->dev,
4604 "Send tqp reset cmd error, status =%d\n", ret);
4605 return ret;
4606 }
4607
4608 return 0;
4609 }
4610
4611 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4612 {
4613 struct hclge_reset_tqp_queue_cmd *req;
4614 struct hclge_desc desc;
4615 int ret;
4616
4617 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4618
4619 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4620 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4621
4622 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4623 if (ret) {
4624 dev_err(&hdev->pdev->dev,
4625 "Get reset status error, status =%d\n", ret);
4626 return ret;
4627 }
4628
4629 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4630 }
4631
4632 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4633 {
4634 struct hclge_vport *vport = hclge_get_vport(handle);
4635 struct hclge_dev *hdev = vport->back;
4636 int reset_try_times = 0;
4637 int reset_status;
4638 int ret;
4639
4640 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4641 if (ret) {
4642 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4643 return;
4644 }
4645
4646 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4647 if (ret) {
4648 dev_warn(&hdev->pdev->dev,
4649 "Send reset tqp cmd fail, ret = %d\n", ret);
4650 return;
4651 }
4652
4653 reset_try_times = 0;
4654 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4655 /* Wait for tqp hw reset */
4656 msleep(20);
4657 reset_status = hclge_get_reset_status(hdev, queue_id);
4658 if (reset_status)
4659 break;
4660 }
4661
4662 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4663 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4664 return;
4665 }
4666
4667 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4668 if (ret) {
4669 dev_warn(&hdev->pdev->dev,
4670 "Deassert the soft reset fail, ret = %d\n", ret);
4671 return;
4672 }
4673 }
4674
4675 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4676 {
4677 struct hclge_vport *vport = hclge_get_vport(handle);
4678 struct hclge_dev *hdev = vport->back;
4679
4680 return hdev->fw_version;
4681 }
4682
4683 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4684 u32 *rx_en, u32 *tx_en)
4685 {
4686 struct hclge_vport *vport = hclge_get_vport(handle);
4687 struct hclge_dev *hdev = vport->back;
4688
4689 *auto_neg = hclge_get_autoneg(handle);
4690
4691 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4692 *rx_en = 0;
4693 *tx_en = 0;
4694 return;
4695 }
4696
4697 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4698 *rx_en = 1;
4699 *tx_en = 0;
4700 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4701 *tx_en = 1;
4702 *rx_en = 0;
4703 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4704 *rx_en = 1;
4705 *tx_en = 1;
4706 } else {
4707 *rx_en = 0;
4708 *tx_en = 0;
4709 }
4710 }
4711
4712 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4713 u8 *auto_neg, u32 *speed, u8 *duplex)
4714 {
4715 struct hclge_vport *vport = hclge_get_vport(handle);
4716 struct hclge_dev *hdev = vport->back;
4717
4718 if (speed)
4719 *speed = hdev->hw.mac.speed;
4720 if (duplex)
4721 *duplex = hdev->hw.mac.duplex;
4722 if (auto_neg)
4723 *auto_neg = hdev->hw.mac.autoneg;
4724 }
4725
4726 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4727 {
4728 struct hclge_vport *vport = hclge_get_vport(handle);
4729 struct hclge_dev *hdev = vport->back;
4730
4731 if (media_type)
4732 *media_type = hdev->hw.mac.media_type;
4733 }
4734
4735 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4736 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4737 {
4738 struct hclge_vport *vport = hclge_get_vport(handle);
4739 struct hclge_dev *hdev = vport->back;
4740 struct phy_device *phydev = hdev->hw.mac.phydev;
4741 int mdix_ctrl, mdix, retval, is_resolved;
4742
4743 if (!phydev) {
4744 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4745 *tp_mdix = ETH_TP_MDI_INVALID;
4746 return;
4747 }
4748
4749 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4750
4751 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4752 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4753 HCLGE_PHY_MDIX_CTRL_S);
4754
4755 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4756 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4757 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4758
4759 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4760
4761 switch (mdix_ctrl) {
4762 case 0x0:
4763 *tp_mdix_ctrl = ETH_TP_MDI;
4764 break;
4765 case 0x1:
4766 *tp_mdix_ctrl = ETH_TP_MDI_X;
4767 break;
4768 case 0x3:
4769 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4770 break;
4771 default:
4772 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4773 break;
4774 }
4775
4776 if (!is_resolved)
4777 *tp_mdix = ETH_TP_MDI_INVALID;
4778 else if (mdix)
4779 *tp_mdix = ETH_TP_MDI_X;
4780 else
4781 *tp_mdix = ETH_TP_MDI;
4782 }
4783
4784 static int hclge_init_client_instance(struct hnae3_client *client,
4785 struct hnae3_ae_dev *ae_dev)
4786 {
4787 struct hclge_dev *hdev = ae_dev->priv;
4788 struct hclge_vport *vport;
4789 int i, ret;
4790
4791 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4792 vport = &hdev->vport[i];
4793
4794 switch (client->type) {
4795 case HNAE3_CLIENT_KNIC:
4796
4797 hdev->nic_client = client;
4798 vport->nic.client = client;
4799 ret = client->ops->init_instance(&vport->nic);
4800 if (ret)
4801 goto err;
4802
4803 if (hdev->roce_client &&
4804 hnae3_dev_roce_supported(hdev)) {
4805 struct hnae3_client *rc = hdev->roce_client;
4806
4807 ret = hclge_init_roce_base_info(vport);
4808 if (ret)
4809 goto err;
4810
4811 ret = rc->ops->init_instance(&vport->roce);
4812 if (ret)
4813 goto err;
4814 }
4815
4816 break;
4817 case HNAE3_CLIENT_UNIC:
4818 hdev->nic_client = client;
4819 vport->nic.client = client;
4820
4821 ret = client->ops->init_instance(&vport->nic);
4822 if (ret)
4823 goto err;
4824
4825 break;
4826 case HNAE3_CLIENT_ROCE:
4827 if (hnae3_dev_roce_supported(hdev)) {
4828 hdev->roce_client = client;
4829 vport->roce.client = client;
4830 }
4831
4832 if (hdev->roce_client && hdev->nic_client) {
4833 ret = hclge_init_roce_base_info(vport);
4834 if (ret)
4835 goto err;
4836
4837 ret = client->ops->init_instance(&vport->roce);
4838 if (ret)
4839 goto err;
4840 }
4841 }
4842 }
4843
4844 return 0;
4845 err:
4846 return ret;
4847 }
4848
4849 static void hclge_uninit_client_instance(struct hnae3_client *client,
4850 struct hnae3_ae_dev *ae_dev)
4851 {
4852 struct hclge_dev *hdev = ae_dev->priv;
4853 struct hclge_vport *vport;
4854 int i;
4855
4856 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4857 vport = &hdev->vport[i];
4858 if (hdev->roce_client) {
4859 hdev->roce_client->ops->uninit_instance(&vport->roce,
4860 0);
4861 hdev->roce_client = NULL;
4862 vport->roce.client = NULL;
4863 }
4864 if (client->type == HNAE3_CLIENT_ROCE)
4865 return;
4866 if (client->ops->uninit_instance) {
4867 client->ops->uninit_instance(&vport->nic, 0);
4868 hdev->nic_client = NULL;
4869 vport->nic.client = NULL;
4870 }
4871 }
4872 }
4873
4874 static int hclge_pci_init(struct hclge_dev *hdev)
4875 {
4876 struct pci_dev *pdev = hdev->pdev;
4877 struct hclge_hw *hw;
4878 int ret;
4879
4880 ret = pci_enable_device(pdev);
4881 if (ret) {
4882 dev_err(&pdev->dev, "failed to enable PCI device\n");
4883 goto err_no_drvdata;
4884 }
4885
4886 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4887 if (ret) {
4888 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4889 if (ret) {
4890 dev_err(&pdev->dev,
4891 "can't set consistent PCI DMA");
4892 goto err_disable_device;
4893 }
4894 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4895 }
4896
4897 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4898 if (ret) {
4899 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4900 goto err_disable_device;
4901 }
4902
4903 pci_set_master(pdev);
4904 hw = &hdev->hw;
4905 hw->back = hdev;
4906 hw->io_base = pcim_iomap(pdev, 2, 0);
4907 if (!hw->io_base) {
4908 dev_err(&pdev->dev, "Can't map configuration register space\n");
4909 ret = -ENOMEM;
4910 goto err_clr_master;
4911 }
4912
4913 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
4914
4915 return 0;
4916 err_clr_master:
4917 pci_clear_master(pdev);
4918 pci_release_regions(pdev);
4919 err_disable_device:
4920 pci_disable_device(pdev);
4921 err_no_drvdata:
4922 pci_set_drvdata(pdev, NULL);
4923
4924 return ret;
4925 }
4926
4927 static void hclge_pci_uninit(struct hclge_dev *hdev)
4928 {
4929 struct pci_dev *pdev = hdev->pdev;
4930
4931 pci_free_irq_vectors(pdev);
4932 pci_clear_master(pdev);
4933 pci_release_mem_regions(pdev);
4934 pci_disable_device(pdev);
4935 }
4936
4937 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4938 {
4939 struct pci_dev *pdev = ae_dev->pdev;
4940 struct hclge_dev *hdev;
4941 int ret;
4942
4943 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4944 if (!hdev) {
4945 ret = -ENOMEM;
4946 goto err_hclge_dev;
4947 }
4948
4949 hdev->pdev = pdev;
4950 hdev->ae_dev = ae_dev;
4951 hdev->reset_type = HNAE3_NONE_RESET;
4952 hdev->reset_request = 0;
4953 hdev->reset_pending = 0;
4954 ae_dev->priv = hdev;
4955
4956 ret = hclge_pci_init(hdev);
4957 if (ret) {
4958 dev_err(&pdev->dev, "PCI init failed\n");
4959 goto err_pci_init;
4960 }
4961
4962 /* Firmware command queue initialize */
4963 ret = hclge_cmd_queue_init(hdev);
4964 if (ret) {
4965 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
4966 return ret;
4967 }
4968
4969 /* Firmware command initialize */
4970 ret = hclge_cmd_init(hdev);
4971 if (ret)
4972 goto err_cmd_init;
4973
4974 ret = hclge_get_cap(hdev);
4975 if (ret) {
4976 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4977 ret);
4978 return ret;
4979 }
4980
4981 ret = hclge_configure(hdev);
4982 if (ret) {
4983 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4984 return ret;
4985 }
4986
4987 ret = hclge_init_msi(hdev);
4988 if (ret) {
4989 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
4990 return ret;
4991 }
4992
4993 ret = hclge_misc_irq_init(hdev);
4994 if (ret) {
4995 dev_err(&pdev->dev,
4996 "Misc IRQ(vector0) init error, ret = %d.\n",
4997 ret);
4998 return ret;
4999 }
5000
5001 ret = hclge_alloc_tqps(hdev);
5002 if (ret) {
5003 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5004 return ret;
5005 }
5006
5007 ret = hclge_alloc_vport(hdev);
5008 if (ret) {
5009 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5010 return ret;
5011 }
5012
5013 ret = hclge_map_tqp(hdev);
5014 if (ret) {
5015 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5016 return ret;
5017 }
5018
5019 ret = hclge_mac_mdio_config(hdev);
5020 if (ret) {
5021 dev_warn(&hdev->pdev->dev,
5022 "mdio config fail ret=%d\n", ret);
5023 return ret;
5024 }
5025
5026 ret = hclge_mac_init(hdev);
5027 if (ret) {
5028 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5029 return ret;
5030 }
5031 ret = hclge_buffer_alloc(hdev);
5032 if (ret) {
5033 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5034 return ret;
5035 }
5036
5037 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5038 if (ret) {
5039 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5040 return ret;
5041 }
5042
5043 ret = hclge_init_vlan_config(hdev);
5044 if (ret) {
5045 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5046 return ret;
5047 }
5048
5049 ret = hclge_tm_schd_init(hdev);
5050 if (ret) {
5051 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5052 return ret;
5053 }
5054
5055 ret = hclge_rss_init_hw(hdev);
5056 if (ret) {
5057 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5058 return ret;
5059 }
5060
5061 hclge_dcb_ops_set(hdev);
5062
5063 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
5064 INIT_WORK(&hdev->service_task, hclge_service_task);
5065 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5066 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5067
5068 /* Enable MISC vector(vector0) */
5069 hclge_enable_vector(&hdev->misc_vector, true);
5070
5071 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5072 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5073 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5074 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5075 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5076 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5077
5078 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5079 return 0;
5080
5081 err_cmd_init:
5082 pci_release_regions(pdev);
5083 err_pci_init:
5084 pci_set_drvdata(pdev, NULL);
5085 err_hclge_dev:
5086 return ret;
5087 }
5088
5089 static void hclge_stats_clear(struct hclge_dev *hdev)
5090 {
5091 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5092 }
5093
5094 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5095 {
5096 struct hclge_dev *hdev = ae_dev->priv;
5097 struct pci_dev *pdev = ae_dev->pdev;
5098 int ret;
5099
5100 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5101
5102 hclge_stats_clear(hdev);
5103
5104 ret = hclge_cmd_init(hdev);
5105 if (ret) {
5106 dev_err(&pdev->dev, "Cmd queue init failed\n");
5107 return ret;
5108 }
5109
5110 ret = hclge_get_cap(hdev);
5111 if (ret) {
5112 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5113 ret);
5114 return ret;
5115 }
5116
5117 ret = hclge_configure(hdev);
5118 if (ret) {
5119 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5120 return ret;
5121 }
5122
5123 ret = hclge_map_tqp(hdev);
5124 if (ret) {
5125 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5126 return ret;
5127 }
5128
5129 ret = hclge_mac_init(hdev);
5130 if (ret) {
5131 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5132 return ret;
5133 }
5134
5135 ret = hclge_buffer_alloc(hdev);
5136 if (ret) {
5137 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5138 return ret;
5139 }
5140
5141 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5142 if (ret) {
5143 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5144 return ret;
5145 }
5146
5147 ret = hclge_init_vlan_config(hdev);
5148 if (ret) {
5149 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5150 return ret;
5151 }
5152
5153 ret = hclge_tm_schd_init(hdev);
5154 if (ret) {
5155 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5156 return ret;
5157 }
5158
5159 ret = hclge_rss_init_hw(hdev);
5160 if (ret) {
5161 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5162 return ret;
5163 }
5164
5165 /* Enable MISC vector(vector0) */
5166 hclge_enable_vector(&hdev->misc_vector, true);
5167
5168 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5169 HCLGE_DRIVER_NAME);
5170
5171 return 0;
5172 }
5173
5174 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5175 {
5176 struct hclge_dev *hdev = ae_dev->priv;
5177 struct hclge_mac *mac = &hdev->hw.mac;
5178
5179 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5180
5181 if (IS_ENABLED(CONFIG_PCI_IOV))
5182 hclge_disable_sriov(hdev);
5183
5184 if (hdev->service_timer.function)
5185 del_timer_sync(&hdev->service_timer);
5186 if (hdev->service_task.func)
5187 cancel_work_sync(&hdev->service_task);
5188 if (hdev->rst_service_task.func)
5189 cancel_work_sync(&hdev->rst_service_task);
5190 if (hdev->mbx_service_task.func)
5191 cancel_work_sync(&hdev->mbx_service_task);
5192
5193 if (mac->phydev)
5194 mdiobus_unregister(mac->mdio_bus);
5195
5196 /* Disable MISC vector(vector0) */
5197 hclge_enable_vector(&hdev->misc_vector, false);
5198 hclge_destroy_cmd_queue(&hdev->hw);
5199 hclge_misc_irq_uninit(hdev);
5200 hclge_pci_uninit(hdev);
5201 ae_dev->priv = NULL;
5202 }
5203
5204 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5205 {
5206 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5207 struct hclge_vport *vport = hclge_get_vport(handle);
5208 struct hclge_dev *hdev = vport->back;
5209
5210 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5211 }
5212
5213 static void hclge_get_channels(struct hnae3_handle *handle,
5214 struct ethtool_channels *ch)
5215 {
5216 struct hclge_vport *vport = hclge_get_vport(handle);
5217
5218 ch->max_combined = hclge_get_max_channels(handle);
5219 ch->other_count = 1;
5220 ch->max_other = 1;
5221 ch->combined_count = vport->alloc_tqps;
5222 }
5223
5224 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5225 u16 *free_tqps, u16 *max_rss_size)
5226 {
5227 struct hclge_vport *vport = hclge_get_vport(handle);
5228 struct hclge_dev *hdev = vport->back;
5229 u16 temp_tqps = 0;
5230 int i;
5231
5232 for (i = 0; i < hdev->num_tqps; i++) {
5233 if (!hdev->htqp[i].alloced)
5234 temp_tqps++;
5235 }
5236 *free_tqps = temp_tqps;
5237 *max_rss_size = hdev->rss_size_max;
5238 }
5239
5240 static void hclge_release_tqp(struct hclge_vport *vport)
5241 {
5242 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5243 struct hclge_dev *hdev = vport->back;
5244 int i;
5245
5246 for (i = 0; i < kinfo->num_tqps; i++) {
5247 struct hclge_tqp *tqp =
5248 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5249
5250 tqp->q.handle = NULL;
5251 tqp->q.tqp_index = 0;
5252 tqp->alloced = false;
5253 }
5254
5255 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5256 kinfo->tqp = NULL;
5257 }
5258
5259 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5260 {
5261 struct hclge_vport *vport = hclge_get_vport(handle);
5262 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5263 struct hclge_dev *hdev = vport->back;
5264 int cur_rss_size = kinfo->rss_size;
5265 int cur_tqps = kinfo->num_tqps;
5266 u16 tc_offset[HCLGE_MAX_TC_NUM];
5267 u16 tc_valid[HCLGE_MAX_TC_NUM];
5268 u16 tc_size[HCLGE_MAX_TC_NUM];
5269 u16 roundup_size;
5270 u32 *rss_indir;
5271 int ret, i;
5272
5273 hclge_release_tqp(vport);
5274
5275 ret = hclge_knic_setup(vport, new_tqps_num);
5276 if (ret) {
5277 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5278 return ret;
5279 }
5280
5281 ret = hclge_map_tqp_to_vport(hdev, vport);
5282 if (ret) {
5283 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5284 return ret;
5285 }
5286
5287 ret = hclge_tm_schd_init(hdev);
5288 if (ret) {
5289 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5290 return ret;
5291 }
5292
5293 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5294 roundup_size = ilog2(roundup_size);
5295 /* Set the RSS TC mode according to the new RSS size */
5296 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5297 tc_valid[i] = 0;
5298
5299 if (!(hdev->hw_tc_map & BIT(i)))
5300 continue;
5301
5302 tc_valid[i] = 1;
5303 tc_size[i] = roundup_size;
5304 tc_offset[i] = kinfo->rss_size * i;
5305 }
5306 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5307 if (ret)
5308 return ret;
5309
5310 /* Reinitializes the rss indirect table according to the new RSS size */
5311 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5312 if (!rss_indir)
5313 return -ENOMEM;
5314
5315 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5316 rss_indir[i] = i % kinfo->rss_size;
5317
5318 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5319 if (ret)
5320 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5321 ret);
5322
5323 kfree(rss_indir);
5324
5325 if (!ret)
5326 dev_info(&hdev->pdev->dev,
5327 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5328 cur_rss_size, kinfo->rss_size,
5329 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5330
5331 return ret;
5332 }
5333
5334 static const struct hnae3_ae_ops hclge_ops = {
5335 .init_ae_dev = hclge_init_ae_dev,
5336 .uninit_ae_dev = hclge_uninit_ae_dev,
5337 .init_client_instance = hclge_init_client_instance,
5338 .uninit_client_instance = hclge_uninit_client_instance,
5339 .map_ring_to_vector = hclge_map_ring_to_vector,
5340 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
5341 .get_vector = hclge_get_vector,
5342 .set_promisc_mode = hclge_set_promisc_mode,
5343 .set_loopback = hclge_set_loopback,
5344 .start = hclge_ae_start,
5345 .stop = hclge_ae_stop,
5346 .get_status = hclge_get_status,
5347 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5348 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5349 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5350 .get_media_type = hclge_get_media_type,
5351 .get_rss_key_size = hclge_get_rss_key_size,
5352 .get_rss_indir_size = hclge_get_rss_indir_size,
5353 .get_rss = hclge_get_rss,
5354 .set_rss = hclge_set_rss,
5355 .set_rss_tuple = hclge_set_rss_tuple,
5356 .get_rss_tuple = hclge_get_rss_tuple,
5357 .get_tc_size = hclge_get_tc_size,
5358 .get_mac_addr = hclge_get_mac_addr,
5359 .set_mac_addr = hclge_set_mac_addr,
5360 .add_uc_addr = hclge_add_uc_addr,
5361 .rm_uc_addr = hclge_rm_uc_addr,
5362 .add_mc_addr = hclge_add_mc_addr,
5363 .rm_mc_addr = hclge_rm_mc_addr,
5364 .set_autoneg = hclge_set_autoneg,
5365 .get_autoneg = hclge_get_autoneg,
5366 .get_pauseparam = hclge_get_pauseparam,
5367 .set_mtu = hclge_set_mtu,
5368 .reset_queue = hclge_reset_tqp,
5369 .get_stats = hclge_get_stats,
5370 .update_stats = hclge_update_stats,
5371 .get_strings = hclge_get_strings,
5372 .get_sset_count = hclge_get_sset_count,
5373 .get_fw_version = hclge_get_fw_version,
5374 .get_mdix_mode = hclge_get_mdix_mode,
5375 .set_vlan_filter = hclge_set_port_vlan_filter,
5376 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5377 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
5378 .reset_event = hclge_reset_event,
5379 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
5380 .set_channels = hclge_set_channels,
5381 .get_channels = hclge_get_channels,
5382 };
5383
5384 static struct hnae3_ae_algo ae_algo = {
5385 .ops = &hclge_ops,
5386 .name = HCLGE_NAME,
5387 .pdev_id_table = ae_algo_pci_tbl,
5388 };
5389
5390 static int hclge_init(void)
5391 {
5392 pr_info("%s is initializing\n", HCLGE_NAME);
5393
5394 return hnae3_register_ae_algo(&ae_algo);
5395 }
5396
5397 static void hclge_exit(void)
5398 {
5399 hnae3_unregister_ae_algo(&ae_algo);
5400 }
5401 module_init(hclge_init);
5402 module_exit(hclge_exit);
5403
5404 MODULE_LICENSE("GPL");
5405 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5406 MODULE_DESCRIPTION("HCLGE Driver");
5407 MODULE_VERSION(HCLGE_MOD_VERSION);
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