2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
43 static struct hnae3_ae_algo ae_algo
;
45 static const struct pci_device_id ae_algo_pci_tbl
[] = {
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
53 /* required last entry */
57 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
59 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
61 "Serdes Loopback test",
65 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
104 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
229 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
393 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
395 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
396 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
397 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap
= 0x1,
403 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
405 #define HCLGE_64_BIT_CMD_NUM 5
406 #define HCLGE_64_BIT_RTN_DATANUM 4
407 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
408 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
413 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
414 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
416 dev_err(&hdev
->pdev
->dev
,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
421 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
422 if (unlikely(i
== 0)) {
423 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
424 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
426 desc_data
= (__le64
*)(&desc
[i
]);
427 n
= HCLGE_64_BIT_RTN_DATANUM
;
429 for (k
= 0; k
< n
; k
++) {
430 *data
++ += le64_to_cpu(*desc_data
);
438 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
440 stats
->pkt_curr_buf_cnt
= 0;
441 stats
->pkt_curr_buf_tc0_cnt
= 0;
442 stats
->pkt_curr_buf_tc1_cnt
= 0;
443 stats
->pkt_curr_buf_tc2_cnt
= 0;
444 stats
->pkt_curr_buf_tc3_cnt
= 0;
445 stats
->pkt_curr_buf_tc4_cnt
= 0;
446 stats
->pkt_curr_buf_tc5_cnt
= 0;
447 stats
->pkt_curr_buf_tc6_cnt
= 0;
448 stats
->pkt_curr_buf_tc7_cnt
= 0;
451 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
453 #define HCLGE_32_BIT_CMD_NUM 8
454 #define HCLGE_32_BIT_RTN_DATANUM 8
456 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
457 struct hclge_32_bit_stats
*all_32_bit_stats
;
463 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
464 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
466 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
467 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
469 dev_err(&hdev
->pdev
->dev
,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
475 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
476 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
477 if (unlikely(i
== 0)) {
478 __le16
*desc_data_16bit
;
480 all_32_bit_stats
->igu_rx_err_pkt
+=
481 le32_to_cpu(desc
[i
].data
[0]);
483 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
484 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
485 le16_to_cpu(*desc_data_16bit
);
488 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
489 le16_to_cpu(*desc_data_16bit
);
491 desc_data
= &desc
[i
].data
[2];
492 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
494 desc_data
= (__le32
*)&desc
[i
];
495 n
= HCLGE_32_BIT_RTN_DATANUM
;
497 for (k
= 0; k
< n
; k
++) {
498 *data
++ += le32_to_cpu(*desc_data
);
506 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
508 #define HCLGE_MAC_CMD_NUM 21
509 #define HCLGE_RTN_DATA_NUM 4
511 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
512 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
517 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
518 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
520 dev_err(&hdev
->pdev
->dev
,
521 "Get MAC pkt stats fail, status = %d.\n", ret
);
526 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
527 if (unlikely(i
== 0)) {
528 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
529 n
= HCLGE_RTN_DATA_NUM
- 2;
531 desc_data
= (__le64
*)(&desc
[i
]);
532 n
= HCLGE_RTN_DATA_NUM
;
534 for (k
= 0; k
< n
; k
++) {
535 *data
++ += le64_to_cpu(*desc_data
);
543 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
545 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
546 struct hclge_vport
*vport
= hclge_get_vport(handle
);
547 struct hclge_dev
*hdev
= vport
->back
;
548 struct hnae3_queue
*queue
;
549 struct hclge_desc desc
[1];
550 struct hclge_tqp
*tqp
;
553 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
554 queue
= handle
->kinfo
.tqp
[i
];
555 tqp
= container_of(queue
, struct hclge_tqp
, q
);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc
[0],
558 HCLGE_OPC_QUERY_RX_STATUS
,
561 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
562 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
564 dev_err(&hdev
->pdev
->dev
,
565 "Query tqp stat fail, status = %d,queue = %d\n",
569 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
570 le32_to_cpu(desc
[0].data
[1]);
573 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
574 queue
= handle
->kinfo
.tqp
[i
];
575 tqp
= container_of(queue
, struct hclge_tqp
, q
);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc
[0],
578 HCLGE_OPC_QUERY_TX_STATUS
,
581 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
582 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
584 dev_err(&hdev
->pdev
->dev
,
585 "Query tqp stat fail, status = %d,queue = %d\n",
589 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
590 le32_to_cpu(desc
[0].data
[1]);
596 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
598 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
599 struct hclge_tqp
*tqp
;
603 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
604 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
605 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
608 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
609 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
610 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
616 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
618 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
620 return kinfo
->num_tqps
* (2);
623 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
625 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
629 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
630 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
631 struct hclge_tqp
, q
);
632 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
634 buff
= buff
+ ETH_GSTRING_LEN
;
637 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
638 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
639 struct hclge_tqp
, q
);
640 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
642 buff
= buff
+ ETH_GSTRING_LEN
;
648 static u64
*hclge_comm_get_stats(void *comm_stats
,
649 const struct hclge_comm_stats_str strs
[],
655 for (i
= 0; i
< size
; i
++)
656 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
661 static u8
*hclge_comm_get_strings(u32 stringset
,
662 const struct hclge_comm_stats_str strs
[],
665 char *buff
= (char *)data
;
668 if (stringset
!= ETH_SS_STATS
)
671 for (i
= 0; i
< size
; i
++) {
672 snprintf(buff
, ETH_GSTRING_LEN
,
674 buff
= buff
+ ETH_GSTRING_LEN
;
680 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
681 struct net_device_stats
*net_stats
)
683 net_stats
->tx_dropped
= 0;
684 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
685 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
686 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
688 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
689 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
690 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
691 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
692 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
694 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
695 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
697 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
698 net_stats
->rx_length_errors
=
699 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
700 net_stats
->rx_length_errors
+=
701 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
702 net_stats
->rx_over_errors
=
703 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
706 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
708 struct hnae3_handle
*handle
;
711 handle
= &hdev
->vport
[0].nic
;
712 if (handle
->client
) {
713 status
= hclge_tqps_update_stats(handle
);
715 dev_err(&hdev
->pdev
->dev
,
716 "Update TQPS stats fail, status = %d.\n",
721 status
= hclge_mac_update_stats(hdev
);
723 dev_err(&hdev
->pdev
->dev
,
724 "Update MAC stats fail, status = %d.\n", status
);
726 status
= hclge_32_bit_update_stats(hdev
);
728 dev_err(&hdev
->pdev
->dev
,
729 "Update 32 bit stats fail, status = %d.\n",
732 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
735 static void hclge_update_stats(struct hnae3_handle
*handle
,
736 struct net_device_stats
*net_stats
)
738 struct hclge_vport
*vport
= hclge_get_vport(handle
);
739 struct hclge_dev
*hdev
= vport
->back
;
740 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
746 status
= hclge_mac_update_stats(hdev
);
748 dev_err(&hdev
->pdev
->dev
,
749 "Update MAC stats fail, status = %d.\n",
752 status
= hclge_32_bit_update_stats(hdev
);
754 dev_err(&hdev
->pdev
->dev
,
755 "Update 32 bit stats fail, status = %d.\n",
758 status
= hclge_64_bit_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update 64 bit stats fail, status = %d.\n",
764 status
= hclge_tqps_update_stats(handle
);
766 dev_err(&hdev
->pdev
->dev
,
767 "Update TQPS stats fail, status = %d.\n",
770 hclge_update_netstat(hw_stats
, net_stats
);
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
775 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
777 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
779 struct hclge_vport
*vport
= hclge_get_vport(handle
);
780 struct hclge_dev
*hdev
= vport
->back
;
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
788 if (stringset
== ETH_SS_TEST
) {
789 /* clear loopback bit flags at first */
790 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
791 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
792 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
793 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
795 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
799 } else if (stringset
== ETH_SS_STATS
) {
800 count
= ARRAY_SIZE(g_mac_stats_string
) +
801 ARRAY_SIZE(g_all_32bit_stats_string
) +
802 ARRAY_SIZE(g_all_64bit_stats_string
) +
803 hclge_tqps_get_sset_count(handle
, stringset
);
809 static void hclge_get_strings(struct hnae3_handle
*handle
,
813 u8
*p
= (char *)data
;
816 if (stringset
== ETH_SS_STATS
) {
817 size
= ARRAY_SIZE(g_mac_stats_string
);
818 p
= hclge_comm_get_strings(stringset
,
822 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
823 p
= hclge_comm_get_strings(stringset
,
824 g_all_32bit_stats_string
,
827 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
828 p
= hclge_comm_get_strings(stringset
,
829 g_all_64bit_stats_string
,
832 p
= hclge_tqps_get_strings(handle
, p
);
833 } else if (stringset
== ETH_SS_TEST
) {
834 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
836 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
838 p
+= ETH_GSTRING_LEN
;
840 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
842 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
844 p
+= ETH_GSTRING_LEN
;
846 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
848 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
850 p
+= ETH_GSTRING_LEN
;
855 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
857 struct hclge_vport
*vport
= hclge_get_vport(handle
);
858 struct hclge_dev
*hdev
= vport
->back
;
861 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
863 ARRAY_SIZE(g_mac_stats_string
),
865 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
866 g_all_32bit_stats_string
,
867 ARRAY_SIZE(g_all_32bit_stats_string
),
869 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
870 g_all_64bit_stats_string
,
871 ARRAY_SIZE(g_all_64bit_stats_string
),
873 p
= hclge_tqps_get_stats(handle
, p
);
876 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
877 struct hclge_func_status_cmd
*status
)
879 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
882 /* Set the pf to main pf */
883 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
884 hdev
->flag
|= HCLGE_FLAG_MAIN
;
886 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
891 static int hclge_query_function_status(struct hclge_dev
*hdev
)
893 struct hclge_func_status_cmd
*req
;
894 struct hclge_desc desc
;
898 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
899 req
= (struct hclge_func_status_cmd
*)desc
.data
;
902 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
904 dev_err(&hdev
->pdev
->dev
,
905 "query function status failed %d.\n",
911 /* Check pf reset is done */
914 usleep_range(1000, 2000);
915 } while (timeout
++ < 5);
917 ret
= hclge_parse_func_status(hdev
, req
);
922 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
924 struct hclge_pf_res_cmd
*req
;
925 struct hclge_desc desc
;
928 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
929 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
931 dev_err(&hdev
->pdev
->dev
,
932 "query pf resource failed %d.\n", ret
);
936 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
937 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
938 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
940 if (hnae3_dev_roce_supported(hdev
)) {
942 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
943 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
945 /* PF should have NIC vectors and Roce vectors,
946 * NIC vectors are queued before Roce vectors.
948 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
951 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
952 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
958 static int hclge_parse_speed(int speed_cmd
, int *speed
)
962 *speed
= HCLGE_MAC_SPEED_10M
;
965 *speed
= HCLGE_MAC_SPEED_100M
;
968 *speed
= HCLGE_MAC_SPEED_1G
;
971 *speed
= HCLGE_MAC_SPEED_10G
;
974 *speed
= HCLGE_MAC_SPEED_25G
;
977 *speed
= HCLGE_MAC_SPEED_40G
;
980 *speed
= HCLGE_MAC_SPEED_50G
;
983 *speed
= HCLGE_MAC_SPEED_100G
;
992 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
995 unsigned long *supported
= hdev
->hw
.mac
.supported
;
997 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
998 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1001 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1002 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1005 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1006 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1009 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1010 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1013 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1014 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1017 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1018 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1021 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1023 u8 media_type
= hdev
->hw
.mac
.media_type
;
1025 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1028 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1031 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1033 struct hclge_cfg_param_cmd
*req
;
1034 u64 mac_addr_tmp_high
;
1038 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1040 /* get the configuration */
1041 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1044 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1045 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1046 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1047 HCLGE_CFG_TQP_DESC_N_M
,
1048 HCLGE_CFG_TQP_DESC_N_S
);
1050 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1051 HCLGE_CFG_PHY_ADDR_M
,
1052 HCLGE_CFG_PHY_ADDR_S
);
1053 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1054 HCLGE_CFG_MEDIA_TP_M
,
1055 HCLGE_CFG_MEDIA_TP_S
);
1056 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1057 HCLGE_CFG_RX_BUF_LEN_M
,
1058 HCLGE_CFG_RX_BUF_LEN_S
);
1059 /* get mac_address */
1060 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1061 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1062 HCLGE_CFG_MAC_ADDR_H_M
,
1063 HCLGE_CFG_MAC_ADDR_H_S
);
1065 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1067 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1068 HCLGE_CFG_DEFAULT_SPEED_M
,
1069 HCLGE_CFG_DEFAULT_SPEED_S
);
1070 cfg
->rss_size_max
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1071 HCLGE_CFG_RSS_SIZE_M
,
1072 HCLGE_CFG_RSS_SIZE_S
);
1074 for (i
= 0; i
< ETH_ALEN
; i
++)
1075 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1077 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1078 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1080 cfg
->speed_ability
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1081 HCLGE_CFG_SPEED_ABILITY_M
,
1082 HCLGE_CFG_SPEED_ABILITY_S
);
1085 /* hclge_get_cfg: query the static parameter from flash
1086 * @hdev: pointer to struct hclge_dev
1087 * @hcfg: the config structure to be getted
1089 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1091 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1092 struct hclge_cfg_param_cmd
*req
;
1095 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1098 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1099 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1101 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1102 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1103 /* Len should be united by 4 bytes when send to hardware */
1104 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1105 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1106 req
->offset
= cpu_to_le32(offset
);
1109 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1111 dev_err(&hdev
->pdev
->dev
,
1112 "get config failed %d.\n", ret
);
1116 hclge_parse_cfg(hcfg
, desc
);
1120 static int hclge_get_cap(struct hclge_dev
*hdev
)
1124 ret
= hclge_query_function_status(hdev
);
1126 dev_err(&hdev
->pdev
->dev
,
1127 "query function status error %d.\n", ret
);
1131 /* get pf resource */
1132 ret
= hclge_query_pf_resource(hdev
);
1134 dev_err(&hdev
->pdev
->dev
,
1135 "query pf resource error %d.\n", ret
);
1142 static int hclge_configure(struct hclge_dev
*hdev
)
1144 struct hclge_cfg cfg
;
1147 ret
= hclge_get_cfg(hdev
, &cfg
);
1149 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1153 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1154 hdev
->base_tqp_pid
= 0;
1155 hdev
->rss_size_max
= cfg
.rss_size_max
;
1156 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1157 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1158 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1159 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1160 hdev
->num_desc
= cfg
.tqp_desc_num
;
1161 hdev
->tm_info
.num_pg
= 1;
1162 hdev
->tc_max
= cfg
.tc_num
;
1163 hdev
->tm_info
.hw_pfc_map
= 0;
1165 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1167 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1171 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1173 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1174 (hdev
->tc_max
< 1)) {
1175 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1180 /* Dev does not support DCB */
1181 if (!hnae3_dev_dcb_supported(hdev
)) {
1185 hdev
->pfc_max
= hdev
->tc_max
;
1188 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1190 /* Currently not support uncontiuous tc */
1191 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1192 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1194 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1199 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1202 struct hclge_cfg_tso_status_cmd
*req
;
1203 struct hclge_desc desc
;
1206 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1208 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1211 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1212 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1213 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1216 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1217 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1218 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1220 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1223 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1225 struct hclge_tqp
*tqp
;
1228 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1229 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1235 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1236 tqp
->dev
= &hdev
->pdev
->dev
;
1239 tqp
->q
.ae_algo
= &ae_algo
;
1240 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1241 tqp
->q
.desc_num
= hdev
->num_desc
;
1242 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1243 i
* HCLGE_TQP_REG_SIZE
;
1251 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1252 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1254 struct hclge_tqp_map_cmd
*req
;
1255 struct hclge_desc desc
;
1258 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1260 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1261 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1262 req
->tqp_vf
= func_id
;
1263 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1264 1 << HCLGE_TQP_MAP_EN_B
;
1265 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1267 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1269 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1277 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1278 struct hnae3_queue
**tqp
, u16 num_tqps
)
1280 struct hclge_dev
*hdev
= vport
->back
;
1283 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1284 alloced
< num_tqps
; i
++) {
1285 if (!hdev
->htqp
[i
].alloced
) {
1286 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1287 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1288 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1289 hdev
->htqp
[i
].alloced
= true;
1293 vport
->alloc_tqps
= num_tqps
;
1298 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1300 struct hnae3_handle
*nic
= &vport
->nic
;
1301 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1302 struct hclge_dev
*hdev
= vport
->back
;
1305 kinfo
->num_desc
= hdev
->num_desc
;
1306 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1307 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1309 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1310 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1312 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1313 if (hdev
->hw_tc_map
& BIT(i
)) {
1314 kinfo
->tc_info
[i
].enable
= true;
1315 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1316 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1317 kinfo
->tc_info
[i
].tc
= i
;
1319 /* Set to default queue if TC is disable */
1320 kinfo
->tc_info
[i
].enable
= false;
1321 kinfo
->tc_info
[i
].tqp_offset
= 0;
1322 kinfo
->tc_info
[i
].tqp_count
= 1;
1323 kinfo
->tc_info
[i
].tc
= 0;
1327 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1328 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1332 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1334 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1341 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1342 struct hclge_vport
*vport
)
1344 struct hnae3_handle
*nic
= &vport
->nic
;
1345 struct hnae3_knic_private_info
*kinfo
;
1348 kinfo
= &nic
->kinfo
;
1349 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1350 struct hclge_tqp
*q
=
1351 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1355 is_pf
= !(vport
->vport_id
);
1356 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1365 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1367 struct hclge_vport
*vport
= hdev
->vport
;
1370 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1371 for (i
= 0; i
< num_vport
; i
++) {
1374 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1384 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1386 /* this would be initialized later */
1389 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1391 struct hnae3_handle
*nic
= &vport
->nic
;
1392 struct hclge_dev
*hdev
= vport
->back
;
1395 nic
->pdev
= hdev
->pdev
;
1396 nic
->ae_algo
= &ae_algo
;
1397 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1399 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1400 ret
= hclge_knic_setup(vport
, num_tqps
);
1402 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1407 hclge_unic_setup(vport
, num_tqps
);
1413 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1415 struct pci_dev
*pdev
= hdev
->pdev
;
1416 struct hclge_vport
*vport
;
1422 /* We need to alloc a vport for main NIC of PF */
1423 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1425 if (hdev
->num_tqps
< num_vport
) {
1426 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1427 hdev
->num_tqps
, num_vport
);
1431 /* Alloc the same number of TQPs for every vport */
1432 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1433 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1435 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1440 hdev
->vport
= vport
;
1441 hdev
->num_alloc_vport
= num_vport
;
1443 if (IS_ENABLED(CONFIG_PCI_IOV
))
1444 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1446 for (i
= 0; i
< num_vport
; i
++) {
1448 vport
->vport_id
= i
;
1451 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1453 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1456 "vport setup failed for vport %d, %d\n",
1467 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1468 struct hclge_pkt_buf_alloc
*buf_alloc
)
1470 /* TX buffer size is unit by 128 byte */
1471 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1472 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1473 struct hclge_tx_buff_alloc_cmd
*req
;
1474 struct hclge_desc desc
;
1478 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1480 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1481 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1482 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1484 req
->tx_pkt_buff
[i
] =
1485 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1486 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1489 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1491 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1499 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1500 struct hclge_pkt_buf_alloc
*buf_alloc
)
1502 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1505 dev_err(&hdev
->pdev
->dev
,
1506 "tx buffer alloc failed %d\n", ret
);
1513 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1517 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1518 if (hdev
->hw_tc_map
& BIT(i
))
1523 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1527 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1528 if (hdev
->hw_tc_map
& BIT(i
) &&
1529 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1534 /* Get the number of pfc enabled TCs, which have private buffer */
1535 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1536 struct hclge_pkt_buf_alloc
*buf_alloc
)
1538 struct hclge_priv_buf
*priv
;
1541 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1542 priv
= &buf_alloc
->priv_buf
[i
];
1543 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1551 /* Get the number of pfc disabled TCs, which have private buffer */
1552 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1553 struct hclge_pkt_buf_alloc
*buf_alloc
)
1555 struct hclge_priv_buf
*priv
;
1558 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1559 priv
= &buf_alloc
->priv_buf
[i
];
1560 if (hdev
->hw_tc_map
& BIT(i
) &&
1561 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1569 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1571 struct hclge_priv_buf
*priv
;
1575 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1576 priv
= &buf_alloc
->priv_buf
[i
];
1578 rx_priv
+= priv
->buf_size
;
1583 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1585 u32 i
, total_tx_size
= 0;
1587 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1588 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1590 return total_tx_size
;
1593 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1594 struct hclge_pkt_buf_alloc
*buf_alloc
,
1597 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1598 int tc_num
, pfc_enable_num
;
1603 tc_num
= hclge_get_tc_num(hdev
);
1604 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1606 if (hnae3_dev_dcb_supported(hdev
))
1607 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1609 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1611 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1612 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1614 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1616 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1617 if (rx_all
<= rx_priv
+ shared_std
)
1620 shared_buf
= rx_all
- rx_priv
;
1621 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1622 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1623 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1625 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1626 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1627 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1628 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1629 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1631 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1632 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1639 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1640 struct hclge_pkt_buf_alloc
*buf_alloc
)
1644 total_size
= hdev
->pkt_buf_size
;
1646 /* alloc tx buffer for all enabled tc */
1647 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1648 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1650 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1653 if (hdev
->hw_tc_map
& BIT(i
))
1654 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1656 priv
->tx_buf_size
= 0;
1658 total_size
-= priv
->tx_buf_size
;
1664 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1665 * @hdev: pointer to struct hclge_dev
1666 * @buf_alloc: pointer to buffer calculation data
1667 * @return: 0: calculate sucessful, negative: fail
1669 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1670 struct hclge_pkt_buf_alloc
*buf_alloc
)
1672 u32 rx_all
= hdev
->pkt_buf_size
;
1673 int no_pfc_priv_num
, pfc_priv_num
;
1674 struct hclge_priv_buf
*priv
;
1677 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1679 /* When DCB is not supported, rx private
1680 * buffer is not allocated.
1682 if (!hnae3_dev_dcb_supported(hdev
)) {
1683 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1689 /* step 1, try to alloc private buffer for all enabled tc */
1690 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1691 priv
= &buf_alloc
->priv_buf
[i
];
1692 if (hdev
->hw_tc_map
& BIT(i
)) {
1694 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1695 priv
->wl
.low
= hdev
->mps
;
1696 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1697 priv
->buf_size
= priv
->wl
.high
+
1701 priv
->wl
.high
= 2 * hdev
->mps
;
1702 priv
->buf_size
= priv
->wl
.high
;
1712 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1715 /* step 2, try to decrease the buffer size of
1716 * no pfc TC's private buffer
1718 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1719 priv
= &buf_alloc
->priv_buf
[i
];
1726 if (!(hdev
->hw_tc_map
& BIT(i
)))
1731 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1733 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1734 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1737 priv
->wl
.high
= hdev
->mps
;
1738 priv
->buf_size
= priv
->wl
.high
;
1742 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1745 /* step 3, try to reduce the number of pfc disabled TCs,
1746 * which have private buffer
1748 /* get the total no pfc enable TC number, which have private buffer */
1749 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1751 /* let the last to be cleared first */
1752 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1753 priv
= &buf_alloc
->priv_buf
[i
];
1755 if (hdev
->hw_tc_map
& BIT(i
) &&
1756 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1757 /* Clear the no pfc TC private buffer */
1765 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1766 no_pfc_priv_num
== 0)
1770 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1773 /* step 4, try to reduce the number of pfc enabled TCs
1774 * which have private buffer.
1776 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1778 /* let the last to be cleared first */
1779 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1780 priv
= &buf_alloc
->priv_buf
[i
];
1782 if (hdev
->hw_tc_map
& BIT(i
) &&
1783 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1784 /* Reduce the number of pfc TC with private buffer */
1792 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1796 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1802 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1803 struct hclge_pkt_buf_alloc
*buf_alloc
)
1805 struct hclge_rx_priv_buff_cmd
*req
;
1806 struct hclge_desc desc
;
1810 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1811 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1813 /* Alloc private buffer TCs */
1814 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1815 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1818 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1820 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1824 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1825 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1827 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1829 dev_err(&hdev
->pdev
->dev
,
1830 "rx private buffer alloc cmd failed %d\n", ret
);
1837 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1839 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1840 struct hclge_pkt_buf_alloc
*buf_alloc
)
1842 struct hclge_rx_priv_wl_buf
*req
;
1843 struct hclge_priv_buf
*priv
;
1844 struct hclge_desc desc
[2];
1848 for (i
= 0; i
< 2; i
++) {
1849 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1851 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1853 /* The first descriptor set the NEXT bit to 1 */
1855 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1857 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1859 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1860 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1862 priv
= &buf_alloc
->priv_buf
[idx
];
1863 req
->tc_wl
[j
].high
=
1864 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1865 req
->tc_wl
[j
].high
|=
1866 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1867 HCLGE_RX_PRIV_EN_B
);
1869 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1870 req
->tc_wl
[j
].low
|=
1871 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1872 HCLGE_RX_PRIV_EN_B
);
1876 /* Send 2 descriptor at one time */
1877 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1879 dev_err(&hdev
->pdev
->dev
,
1880 "rx private waterline config cmd failed %d\n",
1887 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1888 struct hclge_pkt_buf_alloc
*buf_alloc
)
1890 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1891 struct hclge_rx_com_thrd
*req
;
1892 struct hclge_desc desc
[2];
1893 struct hclge_tc_thrd
*tc
;
1897 for (i
= 0; i
< 2; i
++) {
1898 hclge_cmd_setup_basic_desc(&desc
[i
],
1899 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1900 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1902 /* The first descriptor set the NEXT bit to 1 */
1904 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1906 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1908 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1909 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1911 req
->com_thrd
[j
].high
=
1912 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1913 req
->com_thrd
[j
].high
|=
1914 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1915 HCLGE_RX_PRIV_EN_B
);
1916 req
->com_thrd
[j
].low
=
1917 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1918 req
->com_thrd
[j
].low
|=
1919 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1920 HCLGE_RX_PRIV_EN_B
);
1924 /* Send 2 descriptors at one time */
1925 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1927 dev_err(&hdev
->pdev
->dev
,
1928 "common threshold config cmd failed %d\n", ret
);
1934 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1935 struct hclge_pkt_buf_alloc
*buf_alloc
)
1937 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1938 struct hclge_rx_com_wl
*req
;
1939 struct hclge_desc desc
;
1942 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1944 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1945 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1947 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1948 HCLGE_RX_PRIV_EN_B
);
1950 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1952 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1953 HCLGE_RX_PRIV_EN_B
);
1955 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1957 dev_err(&hdev
->pdev
->dev
,
1958 "common waterline config cmd failed %d\n", ret
);
1965 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1967 struct hclge_pkt_buf_alloc
*pkt_buf
;
1970 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1974 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1976 dev_err(&hdev
->pdev
->dev
,
1977 "could not calc tx buffer size for all TCs %d\n", ret
);
1981 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1983 dev_err(&hdev
->pdev
->dev
,
1984 "could not alloc tx buffers %d\n", ret
);
1988 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1990 dev_err(&hdev
->pdev
->dev
,
1991 "could not calc rx priv buffer size for all TCs %d\n",
1996 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1998 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
2003 if (hnae3_dev_dcb_supported(hdev
)) {
2004 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
2006 dev_err(&hdev
->pdev
->dev
,
2007 "could not configure rx private waterline %d\n",
2012 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
2014 dev_err(&hdev
->pdev
->dev
,
2015 "could not configure common threshold %d\n",
2021 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2023 dev_err(&hdev
->pdev
->dev
,
2024 "could not configure common waterline %d\n", ret
);
2031 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2033 struct hnae3_handle
*roce
= &vport
->roce
;
2034 struct hnae3_handle
*nic
= &vport
->nic
;
2036 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2038 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2039 vport
->back
->num_msi_left
== 0)
2042 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2044 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2045 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2047 roce
->pdev
= nic
->pdev
;
2048 roce
->ae_algo
= nic
->ae_algo
;
2049 roce
->numa_node_mask
= nic
->numa_node_mask
;
2054 static int hclge_init_msi(struct hclge_dev
*hdev
)
2056 struct pci_dev
*pdev
= hdev
->pdev
;
2060 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2061 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2064 "failed(%d) to allocate MSI/MSI-X vectors\n",
2068 if (vectors
< hdev
->num_msi
)
2069 dev_warn(&hdev
->pdev
->dev
,
2070 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2071 hdev
->num_msi
, vectors
);
2073 hdev
->num_msi
= vectors
;
2074 hdev
->num_msi_left
= vectors
;
2075 hdev
->base_msi_vector
= pdev
->irq
;
2076 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2077 HCLGE_ROCE_VECTOR_OFFSET
;
2079 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2080 sizeof(u16
), GFP_KERNEL
);
2081 if (!hdev
->vector_status
) {
2082 pci_free_irq_vectors(pdev
);
2086 for (i
= 0; i
< hdev
->num_msi
; i
++)
2087 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2089 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2090 sizeof(int), GFP_KERNEL
);
2091 if (!hdev
->vector_irq
) {
2092 pci_free_irq_vectors(pdev
);
2099 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2101 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2103 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2104 mac
->duplex
= (u8
)duplex
;
2106 mac
->duplex
= HCLGE_MAC_FULL
;
2111 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2113 struct hclge_config_mac_speed_dup_cmd
*req
;
2114 struct hclge_desc desc
;
2117 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2119 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2121 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2124 case HCLGE_MAC_SPEED_10M
:
2125 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2126 HCLGE_CFG_SPEED_S
, 6);
2128 case HCLGE_MAC_SPEED_100M
:
2129 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2130 HCLGE_CFG_SPEED_S
, 7);
2132 case HCLGE_MAC_SPEED_1G
:
2133 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2134 HCLGE_CFG_SPEED_S
, 0);
2136 case HCLGE_MAC_SPEED_10G
:
2137 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2138 HCLGE_CFG_SPEED_S
, 1);
2140 case HCLGE_MAC_SPEED_25G
:
2141 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2142 HCLGE_CFG_SPEED_S
, 2);
2144 case HCLGE_MAC_SPEED_40G
:
2145 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2146 HCLGE_CFG_SPEED_S
, 3);
2148 case HCLGE_MAC_SPEED_50G
:
2149 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2150 HCLGE_CFG_SPEED_S
, 4);
2152 case HCLGE_MAC_SPEED_100G
:
2153 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2154 HCLGE_CFG_SPEED_S
, 5);
2157 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2161 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2164 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2166 dev_err(&hdev
->pdev
->dev
,
2167 "mac speed/duplex config cmd failed %d.\n", ret
);
2171 hclge_check_speed_dup(hdev
, duplex
, speed
);
2176 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2179 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2180 struct hclge_dev
*hdev
= vport
->back
;
2182 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2185 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2188 struct hclge_query_an_speed_dup_cmd
*req
;
2189 struct hclge_desc desc
;
2193 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2195 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2196 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2198 dev_err(&hdev
->pdev
->dev
,
2199 "mac speed/autoneg/duplex query cmd failed %d\n",
2204 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2205 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2206 HCLGE_QUERY_SPEED_S
);
2208 ret
= hclge_parse_speed(speed_tmp
, speed
);
2210 dev_err(&hdev
->pdev
->dev
,
2211 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2218 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2220 struct hclge_config_auto_neg_cmd
*req
;
2221 struct hclge_desc desc
;
2225 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2227 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2228 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2229 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2231 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2233 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2241 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2243 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2244 struct hclge_dev
*hdev
= vport
->back
;
2246 return hclge_set_autoneg_en(hdev
, enable
);
2249 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2251 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2252 struct hclge_dev
*hdev
= vport
->back
;
2253 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2256 return phydev
->autoneg
;
2258 return hdev
->hw
.mac
.autoneg
;
2261 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2265 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2266 struct hclge_desc desc
;
2269 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2270 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2272 hnae_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2274 ether_addr_copy(req
->mac_mask
, mac_mask
);
2276 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2278 dev_err(&hdev
->pdev
->dev
,
2279 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2285 static int hclge_mac_init(struct hclge_dev
*hdev
)
2287 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2288 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2289 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2290 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2294 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2296 dev_err(&hdev
->pdev
->dev
,
2297 "Config mac speed dup fail ret=%d\n", ret
);
2303 /* Initialize the MTA table work mode */
2304 hdev
->accept_mta_mc
= true;
2305 hdev
->enable_mta
= true;
2306 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2308 ret
= hclge_set_mta_filter_mode(hdev
,
2309 hdev
->mta_mac_sel_type
,
2312 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2317 ret
= hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2319 dev_err(&hdev
->pdev
->dev
,
2320 "set mta filter mode fail ret=%d\n", ret
);
2324 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2326 dev_err(&hdev
->pdev
->dev
,
2327 "set default mac_vlan_mask fail ret=%d\n", ret
);
2336 ret
= hclge_set_mtu(handle
, mtu
);
2338 dev_err(&hdev
->pdev
->dev
,
2339 "set mtu failed ret=%d\n", ret
);
2346 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2348 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2349 schedule_work(&hdev
->mbx_service_task
);
2352 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2354 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2355 schedule_work(&hdev
->rst_service_task
);
2358 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2360 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2361 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2362 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2363 (void)schedule_work(&hdev
->service_task
);
2366 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2368 struct hclge_link_status_cmd
*req
;
2369 struct hclge_desc desc
;
2373 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2374 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2376 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2381 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2382 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2384 return !!link_status
;
2387 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2392 mac_state
= hclge_get_mac_link_status(hdev
);
2394 if (hdev
->hw
.mac
.phydev
) {
2395 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2396 link_stat
= mac_state
&
2397 hdev
->hw
.mac
.phydev
->link
;
2402 link_stat
= mac_state
;
2408 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2410 struct hnae3_client
*client
= hdev
->nic_client
;
2411 struct hnae3_handle
*handle
;
2417 state
= hclge_get_mac_phy_link(hdev
);
2418 if (state
!= hdev
->hw
.mac
.link
) {
2419 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2420 handle
= &hdev
->vport
[i
].nic
;
2421 client
->ops
->link_status_change(handle
, state
);
2423 hdev
->hw
.mac
.link
= state
;
2427 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2429 struct hclge_mac mac
= hdev
->hw
.mac
;
2434 /* get the speed and duplex as autoneg'result from mac cmd when phy
2437 if (mac
.phydev
|| !mac
.autoneg
)
2440 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2442 dev_err(&hdev
->pdev
->dev
,
2443 "mac autoneg/speed/duplex query failed %d\n", ret
);
2447 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2448 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2450 dev_err(&hdev
->pdev
->dev
,
2451 "mac speed/duplex config failed %d\n", ret
);
2459 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2461 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2462 struct hclge_dev
*hdev
= vport
->back
;
2464 return hclge_update_speed_duplex(hdev
);
2467 static int hclge_get_status(struct hnae3_handle
*handle
)
2469 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2470 struct hclge_dev
*hdev
= vport
->back
;
2472 hclge_update_link_status(hdev
);
2474 return hdev
->hw
.mac
.link
;
2477 static void hclge_service_timer(struct timer_list
*t
)
2479 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2481 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2482 hdev
->hw_stats
.stats_timer
++;
2483 hclge_task_schedule(hdev
);
2486 static void hclge_service_complete(struct hclge_dev
*hdev
)
2488 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2490 /* Flush memory before next watchdog */
2491 smp_mb__before_atomic();
2492 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2495 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2500 /* fetch the events from their corresponding regs */
2501 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2502 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2504 /* Assumption: If by any chance reset and mailbox events are reported
2505 * together then we will only process reset event in this go and will
2506 * defer the processing of the mailbox events. Since, we would have not
2507 * cleared RX CMDQ event this time we would receive again another
2508 * interrupt from H/W just for the mailbox.
2511 /* check for vector0 reset event sources */
2512 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2513 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2514 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2515 return HCLGE_VECTOR0_EVENT_RST
;
2518 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2519 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2520 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2521 return HCLGE_VECTOR0_EVENT_RST
;
2524 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2525 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2526 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2527 return HCLGE_VECTOR0_EVENT_RST
;
2530 /* check for vector0 mailbox(=CMDQ RX) event source */
2531 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2532 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2533 *clearval
= cmdq_src_reg
;
2534 return HCLGE_VECTOR0_EVENT_MBX
;
2537 return HCLGE_VECTOR0_EVENT_OTHER
;
2540 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2543 switch (event_type
) {
2544 case HCLGE_VECTOR0_EVENT_RST
:
2545 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2547 case HCLGE_VECTOR0_EVENT_MBX
:
2548 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2553 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2555 writel(enable
? 1 : 0, vector
->addr
);
2558 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2560 struct hclge_dev
*hdev
= data
;
2564 hclge_enable_vector(&hdev
->misc_vector
, false);
2565 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2567 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2568 switch (event_cause
) {
2569 case HCLGE_VECTOR0_EVENT_RST
:
2570 hclge_reset_task_schedule(hdev
);
2572 case HCLGE_VECTOR0_EVENT_MBX
:
2573 /* If we are here then,
2574 * 1. Either we are not handling any mbx task and we are not
2577 * 2. We could be handling a mbx task but nothing more is
2579 * In both cases, we should schedule mbx task as there are more
2580 * mbx messages reported by this interrupt.
2582 hclge_mbx_task_schedule(hdev
);
2585 dev_dbg(&hdev
->pdev
->dev
,
2586 "received unknown or unhandled event of vector0\n");
2590 /* we should clear the source of interrupt */
2591 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2592 hclge_enable_vector(&hdev
->misc_vector
, true);
2597 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2599 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2600 hdev
->num_msi_left
+= 1;
2601 hdev
->num_msi_used
-= 1;
2604 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2606 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2608 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2610 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2611 hdev
->vector_status
[0] = 0;
2613 hdev
->num_msi_left
-= 1;
2614 hdev
->num_msi_used
+= 1;
2617 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2621 hclge_get_misc_vector(hdev
);
2623 /* this would be explicitly freed in the end */
2624 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2625 0, "hclge_misc", hdev
);
2627 hclge_free_vector(hdev
, 0);
2628 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2629 hdev
->misc_vector
.vector_irq
);
2635 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2637 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2638 hclge_free_vector(hdev
, 0);
2641 static int hclge_notify_client(struct hclge_dev
*hdev
,
2642 enum hnae3_reset_notify_type type
)
2644 struct hnae3_client
*client
= hdev
->nic_client
;
2647 if (!client
->ops
->reset_notify
)
2650 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2651 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2654 ret
= client
->ops
->reset_notify(handle
, type
);
2662 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2664 #define HCLGE_RESET_WATI_MS 100
2665 #define HCLGE_RESET_WAIT_CNT 5
2666 u32 val
, reg
, reg_bit
;
2669 switch (hdev
->reset_type
) {
2670 case HNAE3_GLOBAL_RESET
:
2671 reg
= HCLGE_GLOBAL_RESET_REG
;
2672 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2674 case HNAE3_CORE_RESET
:
2675 reg
= HCLGE_GLOBAL_RESET_REG
;
2676 reg_bit
= HCLGE_CORE_RESET_BIT
;
2678 case HNAE3_FUNC_RESET
:
2679 reg
= HCLGE_FUN_RST_ING
;
2680 reg_bit
= HCLGE_FUN_RST_ING_B
;
2683 dev_err(&hdev
->pdev
->dev
,
2684 "Wait for unsupported reset type: %d\n",
2689 val
= hclge_read_dev(&hdev
->hw
, reg
);
2690 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2691 msleep(HCLGE_RESET_WATI_MS
);
2692 val
= hclge_read_dev(&hdev
->hw
, reg
);
2696 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2697 dev_warn(&hdev
->pdev
->dev
,
2698 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2705 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2707 struct hclge_desc desc
;
2708 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2711 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2712 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_MAC_B
, 0);
2713 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2714 req
->fun_reset_vfid
= func_id
;
2716 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2718 dev_err(&hdev
->pdev
->dev
,
2719 "send function reset cmd fail, status =%d\n", ret
);
2724 static void hclge_do_reset(struct hclge_dev
*hdev
)
2726 struct pci_dev
*pdev
= hdev
->pdev
;
2729 switch (hdev
->reset_type
) {
2730 case HNAE3_GLOBAL_RESET
:
2731 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2732 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2733 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2734 dev_info(&pdev
->dev
, "Global Reset requested\n");
2736 case HNAE3_CORE_RESET
:
2737 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2738 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2739 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2740 dev_info(&pdev
->dev
, "Core Reset requested\n");
2742 case HNAE3_FUNC_RESET
:
2743 dev_info(&pdev
->dev
, "PF Reset requested\n");
2744 hclge_func_reset_cmd(hdev
, 0);
2745 /* schedule again to check later */
2746 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2747 hclge_reset_task_schedule(hdev
);
2750 dev_warn(&pdev
->dev
,
2751 "Unsupported reset type: %d\n", hdev
->reset_type
);
2756 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2757 unsigned long *addr
)
2759 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2761 /* return the highest priority reset level amongst all */
2762 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2763 rst_level
= HNAE3_GLOBAL_RESET
;
2764 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2765 rst_level
= HNAE3_CORE_RESET
;
2766 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2767 rst_level
= HNAE3_IMP_RESET
;
2768 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2769 rst_level
= HNAE3_FUNC_RESET
;
2771 /* now, clear all other resets */
2772 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2773 clear_bit(HNAE3_CORE_RESET
, addr
);
2774 clear_bit(HNAE3_IMP_RESET
, addr
);
2775 clear_bit(HNAE3_FUNC_RESET
, addr
);
2780 static void hclge_reset(struct hclge_dev
*hdev
)
2782 /* perform reset of the stack & ae device for a client */
2784 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2786 if (!hclge_reset_wait(hdev
)) {
2788 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2789 hclge_reset_ae_dev(hdev
->ae_dev
);
2790 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2793 /* schedule again to check pending resets later */
2794 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2795 hclge_reset_task_schedule(hdev
);
2798 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2801 static void hclge_reset_event(struct hnae3_handle
*handle
)
2803 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2804 struct hclge_dev
*hdev
= vport
->back
;
2806 /* check if this is a new reset request and we are not here just because
2807 * last reset attempt did not succeed and watchdog hit us again. We will
2808 * know this if last reset request did not occur very recently (watchdog
2809 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2810 * In case of new request we reset the "reset level" to PF reset.
2812 if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2813 handle
->reset_level
= HNAE3_FUNC_RESET
;
2815 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2816 handle
->reset_level
);
2818 /* request reset & schedule reset task */
2819 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2820 hclge_reset_task_schedule(hdev
);
2822 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2823 handle
->reset_level
++;
2825 handle
->last_reset_time
= jiffies
;
2828 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2830 /* check if there is any ongoing reset in the hardware. This status can
2831 * be checked from reset_pending. If there is then, we need to wait for
2832 * hardware to complete reset.
2833 * a. If we are able to figure out in reasonable time that hardware
2834 * has fully resetted then, we can proceed with driver, client
2836 * b. else, we can come back later to check this status so re-sched
2839 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2840 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2843 /* check if we got any *new* reset requests to be honored */
2844 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2845 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2846 hclge_do_reset(hdev
);
2848 hdev
->reset_type
= HNAE3_NONE_RESET
;
2851 static void hclge_reset_service_task(struct work_struct
*work
)
2853 struct hclge_dev
*hdev
=
2854 container_of(work
, struct hclge_dev
, rst_service_task
);
2856 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2859 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2861 hclge_reset_subtask(hdev
);
2863 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2866 static void hclge_mailbox_service_task(struct work_struct
*work
)
2868 struct hclge_dev
*hdev
=
2869 container_of(work
, struct hclge_dev
, mbx_service_task
);
2871 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2874 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2876 hclge_mbx_handler(hdev
);
2878 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2881 static void hclge_service_task(struct work_struct
*work
)
2883 struct hclge_dev
*hdev
=
2884 container_of(work
, struct hclge_dev
, service_task
);
2886 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2887 hclge_update_stats_for_all(hdev
);
2888 hdev
->hw_stats
.stats_timer
= 0;
2891 hclge_update_speed_duplex(hdev
);
2892 hclge_update_link_status(hdev
);
2893 hclge_service_complete(hdev
);
2896 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2898 /* VF handle has no client */
2899 if (!handle
->client
)
2900 return container_of(handle
, struct hclge_vport
, nic
);
2901 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2902 return container_of(handle
, struct hclge_vport
, roce
);
2904 return container_of(handle
, struct hclge_vport
, nic
);
2907 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2908 struct hnae3_vector_info
*vector_info
)
2910 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2911 struct hnae3_vector_info
*vector
= vector_info
;
2912 struct hclge_dev
*hdev
= vport
->back
;
2916 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2918 for (j
= 0; j
< vector_num
; j
++) {
2919 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2920 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2921 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2922 vector
->io_addr
= hdev
->hw
.io_base
+
2923 HCLGE_VECTOR_REG_BASE
+
2924 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2926 HCLGE_VECTOR_VF_OFFSET
;
2927 hdev
->vector_status
[i
] = vport
->vport_id
;
2928 hdev
->vector_irq
[i
] = vector
->vector
;
2937 hdev
->num_msi_left
-= alloc
;
2938 hdev
->num_msi_used
+= alloc
;
2943 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2947 for (i
= 0; i
< hdev
->num_msi
; i
++)
2948 if (vector
== hdev
->vector_irq
[i
])
2954 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
2956 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2957 struct hclge_dev
*hdev
= vport
->back
;
2960 vector_id
= hclge_get_vector_index(hdev
, vector
);
2961 if (vector_id
< 0) {
2962 dev_err(&hdev
->pdev
->dev
,
2963 "Get vector index fail. vector_id =%d\n", vector_id
);
2967 hclge_free_vector(hdev
, vector_id
);
2972 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
2974 return HCLGE_RSS_KEY_SIZE
;
2977 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
2979 return HCLGE_RSS_IND_TBL_SIZE
;
2982 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
2983 const u8 hfunc
, const u8
*key
)
2985 struct hclge_rss_config_cmd
*req
;
2986 struct hclge_desc desc
;
2991 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
2993 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
2994 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
2997 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
2998 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3000 if (key_offset
== 2)
3002 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3004 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3006 memcpy(req
->hash_key
,
3007 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3009 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3011 dev_err(&hdev
->pdev
->dev
,
3012 "Configure RSS config fail, status = %d\n",
3020 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3022 struct hclge_rss_indirection_table_cmd
*req
;
3023 struct hclge_desc desc
;
3027 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3029 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3030 hclge_cmd_setup_basic_desc
3031 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3033 req
->start_table_index
=
3034 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3035 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3037 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3038 req
->rss_result
[j
] =
3039 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3041 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3043 dev_err(&hdev
->pdev
->dev
,
3044 "Configure rss indir table fail,status = %d\n",
3052 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3053 u16
*tc_size
, u16
*tc_offset
)
3055 struct hclge_rss_tc_mode_cmd
*req
;
3056 struct hclge_desc desc
;
3060 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3061 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3063 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3066 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3067 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3068 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3069 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3070 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3072 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3075 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3077 dev_err(&hdev
->pdev
->dev
,
3078 "Configure rss tc mode fail, status = %d\n", ret
);
3085 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3087 struct hclge_rss_input_tuple_cmd
*req
;
3088 struct hclge_desc desc
;
3091 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3093 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3095 /* Get the tuple cfg from pf */
3096 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3097 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3098 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3099 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3100 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3101 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3102 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3103 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3104 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3106 dev_err(&hdev
->pdev
->dev
,
3107 "Configure rss input fail, status = %d\n", ret
);
3114 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3117 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3120 /* Get hash algorithm */
3122 *hfunc
= vport
->rss_algo
;
3124 /* Get the RSS Key required by the user */
3126 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3128 /* Get indirect table */
3130 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3131 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3136 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3137 const u8
*key
, const u8 hfunc
)
3139 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3140 struct hclge_dev
*hdev
= vport
->back
;
3144 /* Set the RSS Hash Key if specififed by the user */
3147 if (hfunc
== ETH_RSS_HASH_TOP
||
3148 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3149 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3152 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3156 /* Update the shadow RSS key with user specified qids */
3157 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3158 vport
->rss_algo
= hash_algo
;
3161 /* Update the shadow RSS table with user specified qids */
3162 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3163 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3165 /* Update the hardware */
3166 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3169 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3171 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3173 if (nfc
->data
& RXH_L4_B_2_3
)
3174 hash_sets
|= HCLGE_D_PORT_BIT
;
3176 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3178 if (nfc
->data
& RXH_IP_SRC
)
3179 hash_sets
|= HCLGE_S_IP_BIT
;
3181 hash_sets
&= ~HCLGE_S_IP_BIT
;
3183 if (nfc
->data
& RXH_IP_DST
)
3184 hash_sets
|= HCLGE_D_IP_BIT
;
3186 hash_sets
&= ~HCLGE_D_IP_BIT
;
3188 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3189 hash_sets
|= HCLGE_V_TAG_BIT
;
3194 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3195 struct ethtool_rxnfc
*nfc
)
3197 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3198 struct hclge_dev
*hdev
= vport
->back
;
3199 struct hclge_rss_input_tuple_cmd
*req
;
3200 struct hclge_desc desc
;
3204 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3205 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3208 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3209 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3211 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3212 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3213 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3214 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3215 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3216 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3217 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3218 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3220 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3221 switch (nfc
->flow_type
) {
3223 req
->ipv4_tcp_en
= tuple_sets
;
3226 req
->ipv6_tcp_en
= tuple_sets
;
3229 req
->ipv4_udp_en
= tuple_sets
;
3232 req
->ipv6_udp_en
= tuple_sets
;
3235 req
->ipv4_sctp_en
= tuple_sets
;
3238 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3239 (nfc
->data
& RXH_L4_B_2_3
))
3242 req
->ipv6_sctp_en
= tuple_sets
;
3245 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3248 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3254 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3256 dev_err(&hdev
->pdev
->dev
,
3257 "Set rss tuple fail, status = %d\n", ret
);
3261 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3262 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3263 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3264 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3265 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3266 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3267 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3268 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3272 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3273 struct ethtool_rxnfc
*nfc
)
3275 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3280 switch (nfc
->flow_type
) {
3282 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3285 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3288 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3291 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3294 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3297 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3301 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3310 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3311 nfc
->data
|= RXH_L4_B_2_3
;
3312 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3313 nfc
->data
|= RXH_L4_B_0_1
;
3314 if (tuple_sets
& HCLGE_D_IP_BIT
)
3315 nfc
->data
|= RXH_IP_DST
;
3316 if (tuple_sets
& HCLGE_S_IP_BIT
)
3317 nfc
->data
|= RXH_IP_SRC
;
3322 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3324 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3325 struct hclge_dev
*hdev
= vport
->back
;
3327 return hdev
->rss_size_max
;
3330 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3332 struct hclge_vport
*vport
= hdev
->vport
;
3333 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3334 u16 rss_size
= vport
[0].alloc_rss_size
;
3335 u8
*key
= vport
[0].rss_hash_key
;
3336 u8 hfunc
= vport
[0].rss_algo
;
3337 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3338 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3339 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3343 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3347 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3351 ret
= hclge_set_rss_input_tuple(hdev
);
3355 /* Each TC have the same queue size, and tc_size set to hardware is
3356 * the log2 of roundup power of two of rss_size, the acutal queue
3357 * size is limited by indirection table.
3359 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3360 dev_err(&hdev
->pdev
->dev
,
3361 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3366 roundup_size
= roundup_pow_of_two(rss_size
);
3367 roundup_size
= ilog2(roundup_size
);
3369 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3372 if (!(hdev
->hw_tc_map
& BIT(i
)))
3376 tc_size
[i
] = roundup_size
;
3377 tc_offset
[i
] = rss_size
* i
;
3380 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3383 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3385 struct hclge_vport
*vport
= hdev
->vport
;
3388 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3389 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3390 vport
[j
].rss_indirection_tbl
[i
] =
3391 i
% vport
[j
].alloc_rss_size
;
3395 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3397 struct hclge_vport
*vport
= hdev
->vport
;
3400 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3401 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3402 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3403 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3404 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3405 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3406 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3407 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3408 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3409 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3410 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3411 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3412 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3413 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3414 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3415 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3416 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3418 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3420 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3423 hclge_rss_indir_init_cfg(hdev
);
3426 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3427 int vector_id
, bool en
,
3428 struct hnae3_ring_chain_node
*ring_chain
)
3430 struct hclge_dev
*hdev
= vport
->back
;
3431 struct hnae3_ring_chain_node
*node
;
3432 struct hclge_desc desc
;
3433 struct hclge_ctrl_vector_chain_cmd
*req
3434 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3435 enum hclge_cmd_status status
;
3436 enum hclge_opcode_type op
;
3437 u16 tqp_type_and_id
;
3440 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3441 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3442 req
->int_vector_id
= vector_id
;
3445 for (node
= ring_chain
; node
; node
= node
->next
) {
3446 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3447 hnae_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3449 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3450 hnae_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3451 HCLGE_TQP_ID_S
, node
->tqp_index
);
3452 hnae_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3454 hnae_get_field(node
->int_gl_idx
,
3455 HNAE3_RING_GL_IDX_M
,
3456 HNAE3_RING_GL_IDX_S
));
3457 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3458 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3459 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3460 req
->vfid
= vport
->vport_id
;
3462 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3464 dev_err(&hdev
->pdev
->dev
,
3465 "Map TQP fail, status is %d.\n",
3471 hclge_cmd_setup_basic_desc(&desc
,
3474 req
->int_vector_id
= vector_id
;
3479 req
->int_cause_num
= i
;
3480 req
->vfid
= vport
->vport_id
;
3481 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3483 dev_err(&hdev
->pdev
->dev
,
3484 "Map TQP fail, status is %d.\n", status
);
3492 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3494 struct hnae3_ring_chain_node
*ring_chain
)
3496 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3497 struct hclge_dev
*hdev
= vport
->back
;
3500 vector_id
= hclge_get_vector_index(hdev
, vector
);
3501 if (vector_id
< 0) {
3502 dev_err(&hdev
->pdev
->dev
,
3503 "Get vector index fail. vector_id =%d\n", vector_id
);
3507 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3510 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3512 struct hnae3_ring_chain_node
*ring_chain
)
3514 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3515 struct hclge_dev
*hdev
= vport
->back
;
3518 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3521 vector_id
= hclge_get_vector_index(hdev
, vector
);
3522 if (vector_id
< 0) {
3523 dev_err(&handle
->pdev
->dev
,
3524 "Get vector index fail. ret =%d\n", vector_id
);
3528 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3530 dev_err(&handle
->pdev
->dev
,
3531 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3538 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3539 struct hclge_promisc_param
*param
)
3541 struct hclge_promisc_cfg_cmd
*req
;
3542 struct hclge_desc desc
;
3545 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3547 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3548 req
->vf_id
= param
->vf_id
;
3550 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3551 * pdev revision(0x20), new revision support them. The
3552 * value of this two fields will not return error when driver
3553 * send command to fireware in revision(0x20).
3555 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
) |
3556 HCLGE_PROMISC_TX_EN_B
| HCLGE_PROMISC_RX_EN_B
;
3558 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3560 dev_err(&hdev
->pdev
->dev
,
3561 "Set promisc mode fail, status is %d.\n", ret
);
3567 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3568 bool en_mc
, bool en_bc
, int vport_id
)
3573 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3575 param
->enable
= HCLGE_PROMISC_EN_UC
;
3577 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3579 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3580 param
->vf_id
= vport_id
;
3583 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
3585 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3586 struct hclge_dev
*hdev
= vport
->back
;
3587 struct hclge_promisc_param param
;
3589 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
3590 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3593 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3595 struct hclge_desc desc
;
3596 struct hclge_config_mac_mode_cmd
*req
=
3597 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3601 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3602 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3603 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3604 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3605 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3606 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3607 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3608 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3609 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3610 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3611 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3612 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3613 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3614 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3615 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3616 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3618 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3620 dev_err(&hdev
->pdev
->dev
,
3621 "mac enable fail, ret =%d.\n", ret
);
3624 static int hclge_set_mac_loopback(struct hclge_dev
*hdev
, bool en
)
3626 struct hclge_config_mac_mode_cmd
*req
;
3627 struct hclge_desc desc
;
3631 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3632 /* 1 Read out the MAC mode config at first */
3633 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, true);
3634 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3636 dev_err(&hdev
->pdev
->dev
,
3637 "mac loopback get fail, ret =%d.\n", ret
);
3641 /* 2 Then setup the loopback flag */
3642 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3643 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, en
? 1 : 0);
3645 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3647 /* 3 Config mac work mode with loopback flag
3648 * and its original configure parameters
3650 hclge_cmd_reuse_desc(&desc
, false);
3651 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3653 dev_err(&hdev
->pdev
->dev
,
3654 "mac loopback set fail, ret =%d.\n", ret
);
3658 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3659 enum hnae3_loop loop_mode
, bool en
)
3661 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3662 struct hclge_dev
*hdev
= vport
->back
;
3665 switch (loop_mode
) {
3666 case HNAE3_MAC_INTER_LOOP_MAC
:
3667 ret
= hclge_set_mac_loopback(hdev
, en
);
3671 dev_err(&hdev
->pdev
->dev
,
3672 "loop_mode %d is not supported\n", loop_mode
);
3679 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3680 int stream_id
, bool enable
)
3682 struct hclge_desc desc
;
3683 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3684 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3687 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3688 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3689 req
->stream_id
= cpu_to_le16(stream_id
);
3690 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3692 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3694 dev_err(&hdev
->pdev
->dev
,
3695 "Tqp enable fail, status =%d.\n", ret
);
3699 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3701 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3702 struct hnae3_queue
*queue
;
3703 struct hclge_tqp
*tqp
;
3706 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3707 queue
= handle
->kinfo
.tqp
[i
];
3708 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3709 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3713 static int hclge_ae_start(struct hnae3_handle
*handle
)
3715 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3716 struct hclge_dev
*hdev
= vport
->back
;
3719 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3720 hclge_tqp_enable(hdev
, i
, 0, true);
3723 hclge_cfg_mac_mode(hdev
, true);
3724 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3725 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3726 hdev
->hw
.mac
.link
= 0;
3728 /* reset tqp stats */
3729 hclge_reset_tqp_stats(handle
);
3731 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3734 ret
= hclge_mac_start_phy(hdev
);
3741 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3743 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3744 struct hclge_dev
*hdev
= vport
->back
;
3747 del_timer_sync(&hdev
->service_timer
);
3748 cancel_work_sync(&hdev
->service_task
);
3750 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3753 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3754 hclge_tqp_enable(hdev
, i
, 0, false);
3757 hclge_cfg_mac_mode(hdev
, false);
3759 hclge_mac_stop_phy(hdev
);
3761 /* reset tqp stats */
3762 hclge_reset_tqp_stats(handle
);
3763 del_timer_sync(&hdev
->service_timer
);
3764 cancel_work_sync(&hdev
->service_task
);
3765 hclge_update_link_status(hdev
);
3768 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3769 u16 cmdq_resp
, u8 resp_code
,
3770 enum hclge_mac_vlan_tbl_opcode op
)
3772 struct hclge_dev
*hdev
= vport
->back
;
3773 int return_status
= -EIO
;
3776 dev_err(&hdev
->pdev
->dev
,
3777 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3782 if (op
== HCLGE_MAC_VLAN_ADD
) {
3783 if ((!resp_code
) || (resp_code
== 1)) {
3785 } else if (resp_code
== 2) {
3786 return_status
= -ENOSPC
;
3787 dev_err(&hdev
->pdev
->dev
,
3788 "add mac addr failed for uc_overflow.\n");
3789 } else if (resp_code
== 3) {
3790 return_status
= -ENOSPC
;
3791 dev_err(&hdev
->pdev
->dev
,
3792 "add mac addr failed for mc_overflow.\n");
3794 dev_err(&hdev
->pdev
->dev
,
3795 "add mac addr failed for undefined, code=%d.\n",
3798 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3801 } else if (resp_code
== 1) {
3802 return_status
= -ENOENT
;
3803 dev_dbg(&hdev
->pdev
->dev
,
3804 "remove mac addr failed for miss.\n");
3806 dev_err(&hdev
->pdev
->dev
,
3807 "remove mac addr failed for undefined, code=%d.\n",
3810 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3813 } else if (resp_code
== 1) {
3814 return_status
= -ENOENT
;
3815 dev_dbg(&hdev
->pdev
->dev
,
3816 "lookup mac addr failed for miss.\n");
3818 dev_err(&hdev
->pdev
->dev
,
3819 "lookup mac addr failed for undefined, code=%d.\n",
3823 return_status
= -EINVAL
;
3824 dev_err(&hdev
->pdev
->dev
,
3825 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3829 return return_status
;
3832 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3837 if (vfid
> 255 || vfid
< 0)
3840 if (vfid
>= 0 && vfid
<= 191) {
3841 word_num
= vfid
/ 32;
3842 bit_num
= vfid
% 32;
3844 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3846 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3848 word_num
= (vfid
- 192) / 32;
3849 bit_num
= vfid
% 32;
3851 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3853 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3859 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3861 #define HCLGE_DESC_NUMBER 3
3862 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3865 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3866 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3867 if (desc
[i
].data
[j
])
3873 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3876 const unsigned char *mac_addr
= addr
;
3877 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3878 (mac_addr
[0]) | (mac_addr
[1] << 8);
3879 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3881 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3882 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3885 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3888 u16 high_val
= addr
[1] | (addr
[0] << 8);
3889 struct hclge_dev
*hdev
= vport
->back
;
3890 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3891 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3896 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3897 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3900 struct hclge_mta_filter_mode_cmd
*req
;
3901 struct hclge_desc desc
;
3904 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3905 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3907 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3909 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3910 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3912 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3914 dev_err(&hdev
->pdev
->dev
,
3915 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3923 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3927 struct hclge_cfg_func_mta_filter_cmd
*req
;
3928 struct hclge_desc desc
;
3931 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3932 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3934 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3936 req
->function_id
= func_id
;
3938 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3940 dev_err(&hdev
->pdev
->dev
,
3941 "Config func_id enable failed for cmd_send, ret =%d.\n",
3949 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
3953 struct hclge_dev
*hdev
= vport
->back
;
3954 struct hclge_cfg_func_mta_item_cmd
*req
;
3955 struct hclge_desc desc
;
3959 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
3960 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
3961 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
3963 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
3964 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
3965 req
->item_idx
= cpu_to_le16(item_idx
);
3967 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3969 dev_err(&hdev
->pdev
->dev
,
3970 "Config mta table item failed for cmd_send, ret =%d.\n",
3978 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
3979 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
3981 struct hclge_dev
*hdev
= vport
->back
;
3982 struct hclge_desc desc
;
3987 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
3989 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3991 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3993 dev_err(&hdev
->pdev
->dev
,
3994 "del mac addr failed for cmd_send, ret =%d.\n",
3998 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
3999 retval
= le16_to_cpu(desc
.retval
);
4001 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4002 HCLGE_MAC_VLAN_REMOVE
);
4005 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4006 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4007 struct hclge_desc
*desc
,
4010 struct hclge_dev
*hdev
= vport
->back
;
4015 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4017 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4018 memcpy(desc
[0].data
,
4020 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4021 hclge_cmd_setup_basic_desc(&desc
[1],
4022 HCLGE_OPC_MAC_VLAN_ADD
,
4024 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4025 hclge_cmd_setup_basic_desc(&desc
[2],
4026 HCLGE_OPC_MAC_VLAN_ADD
,
4028 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4030 memcpy(desc
[0].data
,
4032 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4033 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4036 dev_err(&hdev
->pdev
->dev
,
4037 "lookup mac addr failed for cmd_send, ret =%d.\n",
4041 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4042 retval
= le16_to_cpu(desc
[0].retval
);
4044 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4045 HCLGE_MAC_VLAN_LKUP
);
4048 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4049 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4050 struct hclge_desc
*mc_desc
)
4052 struct hclge_dev
*hdev
= vport
->back
;
4059 struct hclge_desc desc
;
4061 hclge_cmd_setup_basic_desc(&desc
,
4062 HCLGE_OPC_MAC_VLAN_ADD
,
4064 memcpy(desc
.data
, req
,
4065 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4066 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4067 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4068 retval
= le16_to_cpu(desc
.retval
);
4070 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4072 HCLGE_MAC_VLAN_ADD
);
4074 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4075 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4076 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4077 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4078 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4079 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4080 memcpy(mc_desc
[0].data
, req
,
4081 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4082 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4083 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4084 retval
= le16_to_cpu(mc_desc
[0].retval
);
4086 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4088 HCLGE_MAC_VLAN_ADD
);
4092 dev_err(&hdev
->pdev
->dev
,
4093 "add mac addr failed for cmd_send, ret =%d.\n",
4101 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4102 const unsigned char *addr
)
4104 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4106 return hclge_add_uc_addr_common(vport
, addr
);
4109 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4110 const unsigned char *addr
)
4112 struct hclge_dev
*hdev
= vport
->back
;
4113 struct hclge_mac_vlan_tbl_entry_cmd req
;
4114 struct hclge_desc desc
;
4115 u16 egress_port
= 0;
4118 /* mac addr check */
4119 if (is_zero_ether_addr(addr
) ||
4120 is_broadcast_ether_addr(addr
) ||
4121 is_multicast_ether_addr(addr
)) {
4122 dev_err(&hdev
->pdev
->dev
,
4123 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4125 is_zero_ether_addr(addr
),
4126 is_broadcast_ether_addr(addr
),
4127 is_multicast_ether_addr(addr
));
4131 memset(&req
, 0, sizeof(req
));
4132 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4133 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4134 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
4135 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4137 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_SW_EN_B
, 0);
4138 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_TYPE_B
, 0);
4139 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4140 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4141 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_PFID_M
,
4142 HCLGE_MAC_EPORT_PFID_S
, 0);
4144 req
.egress_port
= cpu_to_le16(egress_port
);
4146 hclge_prepare_mac_addr(&req
, addr
);
4148 /* Lookup the mac address in the mac_vlan table, and add
4149 * it if the entry is inexistent. Repeated unicast entry
4150 * is not allowed in the mac vlan table.
4152 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4154 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4156 /* check if we just hit the duplicate */
4160 dev_err(&hdev
->pdev
->dev
,
4161 "PF failed to add unicast entry(%pM) in the MAC table\n",
4167 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4168 const unsigned char *addr
)
4170 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4172 return hclge_rm_uc_addr_common(vport
, addr
);
4175 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4176 const unsigned char *addr
)
4178 struct hclge_dev
*hdev
= vport
->back
;
4179 struct hclge_mac_vlan_tbl_entry_cmd req
;
4182 /* mac addr check */
4183 if (is_zero_ether_addr(addr
) ||
4184 is_broadcast_ether_addr(addr
) ||
4185 is_multicast_ether_addr(addr
)) {
4186 dev_dbg(&hdev
->pdev
->dev
,
4187 "Remove mac err! invalid mac:%pM.\n",
4192 memset(&req
, 0, sizeof(req
));
4193 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4194 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4195 hclge_prepare_mac_addr(&req
, addr
);
4196 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4201 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4202 const unsigned char *addr
)
4204 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4206 return hclge_add_mc_addr_common(vport
, addr
);
4209 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4210 const unsigned char *addr
)
4212 struct hclge_dev
*hdev
= vport
->back
;
4213 struct hclge_mac_vlan_tbl_entry_cmd req
;
4214 struct hclge_desc desc
[3];
4218 /* mac addr check */
4219 if (!is_multicast_ether_addr(addr
)) {
4220 dev_err(&hdev
->pdev
->dev
,
4221 "Add mc mac err! invalid mac:%pM.\n",
4225 memset(&req
, 0, sizeof(req
));
4226 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4227 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4228 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4229 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4230 hclge_prepare_mac_addr(&req
, addr
);
4231 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4233 /* This mac addr exist, update VFID for it */
4234 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4235 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4237 /* This mac addr do not exist, add new entry for it */
4238 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4239 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4240 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4241 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4242 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4245 /* Set MTA table for this MAC address */
4246 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4247 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4252 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4253 const unsigned char *addr
)
4255 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4257 return hclge_rm_mc_addr_common(vport
, addr
);
4260 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4261 const unsigned char *addr
)
4263 struct hclge_dev
*hdev
= vport
->back
;
4264 struct hclge_mac_vlan_tbl_entry_cmd req
;
4265 enum hclge_cmd_status status
;
4266 struct hclge_desc desc
[3];
4269 /* mac addr check */
4270 if (!is_multicast_ether_addr(addr
)) {
4271 dev_dbg(&hdev
->pdev
->dev
,
4272 "Remove mc mac err! invalid mac:%pM.\n",
4277 memset(&req
, 0, sizeof(req
));
4278 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4279 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4280 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4281 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4282 hclge_prepare_mac_addr(&req
, addr
);
4283 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4285 /* This mac addr exist, remove this handle's VFID for it */
4286 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4288 if (hclge_is_all_function_id_zero(desc
))
4289 /* All the vfid is zero, so need to delete this entry */
4290 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4292 /* Not all the vfid is zero, update the vfid */
4293 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4296 /* This mac addr do not exist, can't delete it */
4297 dev_err(&hdev
->pdev
->dev
,
4298 "Rm multicast mac addr failed, ret = %d.\n",
4303 /* Set MTB table for this MAC address */
4304 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4305 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
4310 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4311 u16 cmdq_resp
, u8 resp_code
)
4313 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4314 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4315 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4316 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4321 dev_err(&hdev
->pdev
->dev
,
4322 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4327 switch (resp_code
) {
4328 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4329 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4332 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4333 dev_err(&hdev
->pdev
->dev
,
4334 "add mac ethertype failed for manager table overflow.\n");
4335 return_status
= -EIO
;
4337 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4338 dev_err(&hdev
->pdev
->dev
,
4339 "add mac ethertype failed for key conflict.\n");
4340 return_status
= -EIO
;
4343 dev_err(&hdev
->pdev
->dev
,
4344 "add mac ethertype failed for undefined, code=%d.\n",
4346 return_status
= -EIO
;
4349 return return_status
;
4352 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4353 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4355 struct hclge_desc desc
;
4360 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4361 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4363 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4365 dev_err(&hdev
->pdev
->dev
,
4366 "add mac ethertype failed for cmd_send, ret =%d.\n",
4371 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4372 retval
= le16_to_cpu(desc
.retval
);
4374 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4377 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4382 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4383 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4385 dev_err(&hdev
->pdev
->dev
,
4386 "add mac ethertype failed, ret =%d.\n",
4395 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4397 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4398 struct hclge_dev
*hdev
= vport
->back
;
4400 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4403 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4406 const unsigned char *new_addr
= (const unsigned char *)p
;
4407 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4408 struct hclge_dev
*hdev
= vport
->back
;
4411 /* mac addr check */
4412 if (is_zero_ether_addr(new_addr
) ||
4413 is_broadcast_ether_addr(new_addr
) ||
4414 is_multicast_ether_addr(new_addr
)) {
4415 dev_err(&hdev
->pdev
->dev
,
4416 "Change uc mac err! invalid mac:%p.\n",
4421 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4422 dev_warn(&hdev
->pdev
->dev
,
4423 "remove old uc mac address fail.\n");
4425 ret
= hclge_add_uc_addr(handle
, new_addr
);
4427 dev_err(&hdev
->pdev
->dev
,
4428 "add uc mac address fail, ret =%d.\n",
4432 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4433 dev_err(&hdev
->pdev
->dev
,
4434 "restore uc mac address fail.\n");
4439 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4441 dev_err(&hdev
->pdev
->dev
,
4442 "configure mac pause address fail, ret =%d.\n",
4447 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4452 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4455 struct hclge_vlan_filter_ctrl_cmd
*req
;
4456 struct hclge_desc desc
;
4459 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4461 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4462 req
->vlan_type
= vlan_type
;
4463 req
->vlan_fe
= filter_en
;
4465 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4467 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4475 #define HCLGE_FILTER_TYPE_VF 0
4476 #define HCLGE_FILTER_TYPE_PORT 1
4478 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4480 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4481 struct hclge_dev
*hdev
= vport
->back
;
4483 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4486 static int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4487 bool is_kill
, u16 vlan
, u8 qos
,
4490 #define HCLGE_MAX_VF_BYTES 16
4491 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4492 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4493 struct hclge_desc desc
[2];
4498 hclge_cmd_setup_basic_desc(&desc
[0],
4499 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4500 hclge_cmd_setup_basic_desc(&desc
[1],
4501 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4503 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4505 vf_byte_off
= vfid
/ 8;
4506 vf_byte_val
= 1 << (vfid
% 8);
4508 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4509 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4511 req0
->vlan_id
= cpu_to_le16(vlan
);
4512 req0
->vlan_cfg
= is_kill
;
4514 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4515 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4517 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4519 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4521 dev_err(&hdev
->pdev
->dev
,
4522 "Send vf vlan command fail, ret =%d.\n",
4528 #define HCLGE_VF_VLAN_NO_ENTRY 2
4529 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4532 if (req0
->resp_code
== HCLGE_VF_VLAN_NO_ENTRY
) {
4533 dev_warn(&hdev
->pdev
->dev
,
4534 "vf vlan table is full, vf vlan filter is disabled\n");
4538 dev_err(&hdev
->pdev
->dev
,
4539 "Add vf vlan filter fail, ret =%d.\n",
4542 if (!req0
->resp_code
)
4545 dev_err(&hdev
->pdev
->dev
,
4546 "Kill vf vlan filter fail, ret =%d.\n",
4553 static int hclge_set_port_vlan_filter(struct hclge_dev
*hdev
, __be16 proto
,
4554 u16 vlan_id
, bool is_kill
)
4556 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4557 struct hclge_desc desc
;
4558 u8 vlan_offset_byte_val
;
4559 u8 vlan_offset_byte
;
4563 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4565 vlan_offset_160
= vlan_id
/ 160;
4566 vlan_offset_byte
= (vlan_id
% 160) / 8;
4567 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4569 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4570 req
->vlan_offset
= vlan_offset_160
;
4571 req
->vlan_cfg
= is_kill
;
4572 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4574 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4576 dev_err(&hdev
->pdev
->dev
,
4577 "port vlan command, send fail, ret =%d.\n", ret
);
4581 static int hclge_set_vlan_filter_hw(struct hclge_dev
*hdev
, __be16 proto
,
4582 u16 vport_id
, u16 vlan_id
, u8 qos
,
4585 u16 vport_idx
, vport_num
= 0;
4588 ret
= hclge_set_vf_vlan_common(hdev
, vport_id
, is_kill
, vlan_id
,
4591 dev_err(&hdev
->pdev
->dev
,
4592 "Set %d vport vlan filter config fail, ret =%d.\n",
4597 /* vlan 0 may be added twice when 8021q module is enabled */
4598 if (!is_kill
&& !vlan_id
&&
4599 test_bit(vport_id
, hdev
->vlan_table
[vlan_id
]))
4602 if (!is_kill
&& test_and_set_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4603 dev_err(&hdev
->pdev
->dev
,
4604 "Add port vlan failed, vport %d is already in vlan %d\n",
4610 !test_and_clear_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4611 dev_err(&hdev
->pdev
->dev
,
4612 "Delete port vlan failed, vport %d is not in vlan %d\n",
4617 for_each_set_bit(vport_idx
, hdev
->vlan_table
[vlan_id
], VLAN_N_VID
)
4620 if ((is_kill
&& vport_num
== 0) || (!is_kill
&& vport_num
== 1))
4621 ret
= hclge_set_port_vlan_filter(hdev
, proto
, vlan_id
,
4627 int hclge_set_vlan_filter(struct hnae3_handle
*handle
, __be16 proto
,
4628 u16 vlan_id
, bool is_kill
)
4630 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4631 struct hclge_dev
*hdev
= vport
->back
;
4633 return hclge_set_vlan_filter_hw(hdev
, proto
, vport
->vport_id
, vlan_id
,
4637 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4638 u16 vlan
, u8 qos
, __be16 proto
)
4640 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4641 struct hclge_dev
*hdev
= vport
->back
;
4643 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4645 if (proto
!= htons(ETH_P_8021Q
))
4646 return -EPROTONOSUPPORT
;
4648 return hclge_set_vlan_filter_hw(hdev
, proto
, vfid
, vlan
, qos
, false);
4651 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4653 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4654 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4655 struct hclge_dev
*hdev
= vport
->back
;
4656 struct hclge_desc desc
;
4659 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4661 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4662 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4663 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4664 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG1_B
,
4665 vcfg
->accept_tag1
? 1 : 0);
4666 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG1_B
,
4667 vcfg
->accept_untag1
? 1 : 0);
4668 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG2_B
,
4669 vcfg
->accept_tag2
? 1 : 0);
4670 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG2_B
,
4671 vcfg
->accept_untag2
? 1 : 0);
4672 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4673 vcfg
->insert_tag1_en
? 1 : 0);
4674 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4675 vcfg
->insert_tag2_en
? 1 : 0);
4676 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4678 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4679 req
->vf_bitmap
[req
->vf_offset
] =
4680 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4682 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4684 dev_err(&hdev
->pdev
->dev
,
4685 "Send port txvlan cfg command fail, ret =%d\n",
4691 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4693 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4694 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4695 struct hclge_dev
*hdev
= vport
->back
;
4696 struct hclge_desc desc
;
4699 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4701 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4702 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4703 vcfg
->strip_tag1_en
? 1 : 0);
4704 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4705 vcfg
->strip_tag2_en
? 1 : 0);
4706 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4707 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4708 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4709 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4711 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4712 req
->vf_bitmap
[req
->vf_offset
] =
4713 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4715 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4717 dev_err(&hdev
->pdev
->dev
,
4718 "Send port rxvlan cfg command fail, ret =%d\n",
4724 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4726 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4727 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4728 struct hclge_desc desc
;
4731 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4732 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4733 rx_req
->ot_fst_vlan_type
=
4734 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4735 rx_req
->ot_sec_vlan_type
=
4736 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4737 rx_req
->in_fst_vlan_type
=
4738 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4739 rx_req
->in_sec_vlan_type
=
4740 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4742 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4744 dev_err(&hdev
->pdev
->dev
,
4745 "Send rxvlan protocol type command fail, ret =%d\n",
4750 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4752 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4753 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4754 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4756 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4758 dev_err(&hdev
->pdev
->dev
,
4759 "Send txvlan protocol type command fail, ret =%d\n",
4765 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4767 #define HCLGE_DEF_VLAN_TYPE 0x8100
4769 struct hnae3_handle
*handle
;
4770 struct hclge_vport
*vport
;
4774 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4778 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4782 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4783 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4784 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4785 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4786 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4787 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4789 ret
= hclge_set_vlan_protocol_type(hdev
);
4793 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4794 vport
= &hdev
->vport
[i
];
4795 vport
->txvlan_cfg
.accept_tag1
= true;
4796 vport
->txvlan_cfg
.accept_untag1
= true;
4798 /* accept_tag2 and accept_untag2 are not supported on
4799 * pdev revision(0x20), new revision support them. The
4800 * value of this two fields will not return error when driver
4801 * send command to fireware in revision(0x20).
4802 * This two fields can not configured by user.
4804 vport
->txvlan_cfg
.accept_tag2
= true;
4805 vport
->txvlan_cfg
.accept_untag2
= true;
4807 vport
->txvlan_cfg
.insert_tag1_en
= false;
4808 vport
->txvlan_cfg
.insert_tag2_en
= false;
4809 vport
->txvlan_cfg
.default_tag1
= 0;
4810 vport
->txvlan_cfg
.default_tag2
= 0;
4812 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4816 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4817 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4818 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4819 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4821 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4826 handle
= &hdev
->vport
[0].nic
;
4827 return hclge_set_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4830 int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4832 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4834 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4835 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4836 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4837 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4839 return hclge_set_vlan_rx_offload_cfg(vport
);
4842 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
4844 struct hclge_config_max_frm_size_cmd
*req
;
4845 struct hclge_desc desc
;
4849 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
4851 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
4852 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
4855 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
4857 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4859 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4860 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
4862 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4864 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4868 hdev
->mps
= max_frm_size
;
4873 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4875 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4876 struct hclge_dev
*hdev
= vport
->back
;
4879 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
4881 dev_err(&hdev
->pdev
->dev
,
4882 "Change mtu fail, ret =%d\n", ret
);
4886 ret
= hclge_buffer_alloc(hdev
);
4888 dev_err(&hdev
->pdev
->dev
,
4889 "Allocate buffer fail, ret =%d\n", ret
);
4894 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
4897 struct hclge_reset_tqp_queue_cmd
*req
;
4898 struct hclge_desc desc
;
4901 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
4903 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4904 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4905 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
4907 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4909 dev_err(&hdev
->pdev
->dev
,
4910 "Send tqp reset cmd error, status =%d\n", ret
);
4917 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
4919 struct hclge_reset_tqp_queue_cmd
*req
;
4920 struct hclge_desc desc
;
4923 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
4925 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4926 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4928 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4930 dev_err(&hdev
->pdev
->dev
,
4931 "Get reset status error, status =%d\n", ret
);
4935 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
4938 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
4941 struct hnae3_queue
*queue
;
4942 struct hclge_tqp
*tqp
;
4944 queue
= handle
->kinfo
.tqp
[queue_id
];
4945 tqp
= container_of(queue
, struct hclge_tqp
, q
);
4950 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
4952 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4953 struct hclge_dev
*hdev
= vport
->back
;
4954 int reset_try_times
= 0;
4959 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
4962 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
4964 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
4966 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
4970 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
4972 dev_warn(&hdev
->pdev
->dev
,
4973 "Send reset tqp cmd fail, ret = %d\n", ret
);
4977 reset_try_times
= 0;
4978 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
4979 /* Wait for tqp hw reset */
4981 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
4986 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
4987 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
4991 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
4993 dev_warn(&hdev
->pdev
->dev
,
4994 "Deassert the soft reset fail, ret = %d\n", ret
);
4999 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
5001 struct hclge_dev
*hdev
= vport
->back
;
5002 int reset_try_times
= 0;
5007 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5009 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5011 dev_warn(&hdev
->pdev
->dev
,
5012 "Send reset tqp cmd fail, ret = %d\n", ret
);
5016 reset_try_times
= 0;
5017 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5018 /* Wait for tqp hw reset */
5020 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5025 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5026 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5030 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5032 dev_warn(&hdev
->pdev
->dev
,
5033 "Deassert the soft reset fail, ret = %d\n", ret
);
5036 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5038 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5039 struct hclge_dev
*hdev
= vport
->back
;
5041 return hdev
->fw_version
;
5044 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5047 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5048 struct hclge_dev
*hdev
= vport
->back
;
5049 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5054 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5055 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5058 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5060 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5065 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5068 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5071 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5074 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5079 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5080 else if (rx_en
&& !tx_en
)
5081 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5082 else if (!rx_en
&& tx_en
)
5083 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5085 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5087 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5090 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5092 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5097 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5102 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5104 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5105 u16 remote_advertising
= 0;
5106 u16 local_advertising
= 0;
5107 u32 rx_pause
, tx_pause
;
5110 if (!phydev
->link
|| !phydev
->autoneg
)
5113 if (phydev
->advertising
& ADVERTISED_Pause
)
5114 local_advertising
= ADVERTISE_PAUSE_CAP
;
5116 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5117 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5120 remote_advertising
= LPA_PAUSE_CAP
;
5122 if (phydev
->asym_pause
)
5123 remote_advertising
|= LPA_PAUSE_ASYM
;
5125 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5126 remote_advertising
);
5127 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5128 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5130 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5135 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5138 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5139 u32
*rx_en
, u32
*tx_en
)
5141 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5142 struct hclge_dev
*hdev
= vport
->back
;
5144 *auto_neg
= hclge_get_autoneg(handle
);
5146 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5152 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5155 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5158 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5167 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5168 u32 rx_en
, u32 tx_en
)
5170 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5171 struct hclge_dev
*hdev
= vport
->back
;
5172 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5175 fc_autoneg
= hclge_get_autoneg(handle
);
5176 if (auto_neg
!= fc_autoneg
) {
5177 dev_info(&hdev
->pdev
->dev
,
5178 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5182 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5183 dev_info(&hdev
->pdev
->dev
,
5184 "Priority flow control enabled. Cannot set link flow control.\n");
5188 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5191 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5193 /* Only support flow control negotiation for netdev with
5194 * phy attached for now.
5199 return phy_start_aneg(phydev
);
5202 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5203 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5205 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5206 struct hclge_dev
*hdev
= vport
->back
;
5209 *speed
= hdev
->hw
.mac
.speed
;
5211 *duplex
= hdev
->hw
.mac
.duplex
;
5213 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5216 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5218 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5219 struct hclge_dev
*hdev
= vport
->back
;
5222 *media_type
= hdev
->hw
.mac
.media_type
;
5225 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5226 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5228 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5229 struct hclge_dev
*hdev
= vport
->back
;
5230 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5231 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5234 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5235 *tp_mdix
= ETH_TP_MDI_INVALID
;
5239 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5241 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5242 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5243 HCLGE_PHY_MDIX_CTRL_S
);
5245 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5246 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5247 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5249 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5251 switch (mdix_ctrl
) {
5253 *tp_mdix_ctrl
= ETH_TP_MDI
;
5256 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5259 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5262 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5267 *tp_mdix
= ETH_TP_MDI_INVALID
;
5269 *tp_mdix
= ETH_TP_MDI_X
;
5271 *tp_mdix
= ETH_TP_MDI
;
5274 static int hclge_init_client_instance(struct hnae3_client
*client
,
5275 struct hnae3_ae_dev
*ae_dev
)
5277 struct hclge_dev
*hdev
= ae_dev
->priv
;
5278 struct hclge_vport
*vport
;
5281 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5282 vport
= &hdev
->vport
[i
];
5284 switch (client
->type
) {
5285 case HNAE3_CLIENT_KNIC
:
5287 hdev
->nic_client
= client
;
5288 vport
->nic
.client
= client
;
5289 ret
= client
->ops
->init_instance(&vport
->nic
);
5293 if (hdev
->roce_client
&&
5294 hnae3_dev_roce_supported(hdev
)) {
5295 struct hnae3_client
*rc
= hdev
->roce_client
;
5297 ret
= hclge_init_roce_base_info(vport
);
5301 ret
= rc
->ops
->init_instance(&vport
->roce
);
5307 case HNAE3_CLIENT_UNIC
:
5308 hdev
->nic_client
= client
;
5309 vport
->nic
.client
= client
;
5311 ret
= client
->ops
->init_instance(&vport
->nic
);
5316 case HNAE3_CLIENT_ROCE
:
5317 if (hnae3_dev_roce_supported(hdev
)) {
5318 hdev
->roce_client
= client
;
5319 vport
->roce
.client
= client
;
5322 if (hdev
->roce_client
&& hdev
->nic_client
) {
5323 ret
= hclge_init_roce_base_info(vport
);
5327 ret
= client
->ops
->init_instance(&vport
->roce
);
5337 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5338 struct hnae3_ae_dev
*ae_dev
)
5340 struct hclge_dev
*hdev
= ae_dev
->priv
;
5341 struct hclge_vport
*vport
;
5344 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5345 vport
= &hdev
->vport
[i
];
5346 if (hdev
->roce_client
) {
5347 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5349 hdev
->roce_client
= NULL
;
5350 vport
->roce
.client
= NULL
;
5352 if (client
->type
== HNAE3_CLIENT_ROCE
)
5354 if (client
->ops
->uninit_instance
) {
5355 client
->ops
->uninit_instance(&vport
->nic
, 0);
5356 hdev
->nic_client
= NULL
;
5357 vport
->nic
.client
= NULL
;
5362 static int hclge_pci_init(struct hclge_dev
*hdev
)
5364 struct pci_dev
*pdev
= hdev
->pdev
;
5365 struct hclge_hw
*hw
;
5368 ret
= pci_enable_device(pdev
);
5370 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5374 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5376 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5379 "can't set consistent PCI DMA");
5380 goto err_disable_device
;
5382 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5385 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5387 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5388 goto err_disable_device
;
5391 pci_set_master(pdev
);
5394 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5396 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5398 goto err_clr_master
;
5401 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5405 pci_clear_master(pdev
);
5406 pci_release_regions(pdev
);
5408 pci_disable_device(pdev
);
5413 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5415 struct pci_dev
*pdev
= hdev
->pdev
;
5417 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5418 pci_free_irq_vectors(pdev
);
5419 pci_clear_master(pdev
);
5420 pci_release_mem_regions(pdev
);
5421 pci_disable_device(pdev
);
5424 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5426 struct pci_dev
*pdev
= ae_dev
->pdev
;
5427 struct hclge_dev
*hdev
;
5430 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5437 hdev
->ae_dev
= ae_dev
;
5438 hdev
->reset_type
= HNAE3_NONE_RESET
;
5439 hdev
->reset_request
= 0;
5440 hdev
->reset_pending
= 0;
5441 ae_dev
->priv
= hdev
;
5443 ret
= hclge_pci_init(hdev
);
5445 dev_err(&pdev
->dev
, "PCI init failed\n");
5449 /* Firmware command queue initialize */
5450 ret
= hclge_cmd_queue_init(hdev
);
5452 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5453 goto err_pci_uninit
;
5456 /* Firmware command initialize */
5457 ret
= hclge_cmd_init(hdev
);
5459 goto err_cmd_uninit
;
5461 ret
= hclge_get_cap(hdev
);
5463 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5465 goto err_cmd_uninit
;
5468 ret
= hclge_configure(hdev
);
5470 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5471 goto err_cmd_uninit
;
5474 ret
= hclge_init_msi(hdev
);
5476 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5477 goto err_cmd_uninit
;
5480 ret
= hclge_misc_irq_init(hdev
);
5483 "Misc IRQ(vector0) init error, ret = %d.\n",
5485 goto err_msi_uninit
;
5488 ret
= hclge_alloc_tqps(hdev
);
5490 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5491 goto err_msi_irq_uninit
;
5494 ret
= hclge_alloc_vport(hdev
);
5496 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5497 goto err_msi_irq_uninit
;
5500 ret
= hclge_map_tqp(hdev
);
5502 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5503 goto err_msi_irq_uninit
;
5506 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5507 ret
= hclge_mac_mdio_config(hdev
);
5509 dev_err(&hdev
->pdev
->dev
,
5510 "mdio config fail ret=%d\n", ret
);
5511 goto err_msi_irq_uninit
;
5515 ret
= hclge_mac_init(hdev
);
5517 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5518 goto err_mdiobus_unreg
;
5521 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5523 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5524 goto err_mdiobus_unreg
;
5527 ret
= hclge_init_vlan_config(hdev
);
5529 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5530 goto err_mdiobus_unreg
;
5533 ret
= hclge_tm_schd_init(hdev
);
5535 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5536 goto err_mdiobus_unreg
;
5539 hclge_rss_init_cfg(hdev
);
5540 ret
= hclge_rss_init_hw(hdev
);
5542 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5543 goto err_mdiobus_unreg
;
5546 ret
= init_mgr_tbl(hdev
);
5548 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5549 goto err_mdiobus_unreg
;
5552 hclge_dcb_ops_set(hdev
);
5554 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5555 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5556 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5557 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5559 /* Enable MISC vector(vector0) */
5560 hclge_enable_vector(&hdev
->misc_vector
, true);
5562 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5563 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5564 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5565 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5566 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5567 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5569 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5573 if (hdev
->hw
.mac
.phydev
)
5574 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5576 hclge_misc_irq_uninit(hdev
);
5578 pci_free_irq_vectors(pdev
);
5580 hclge_destroy_cmd_queue(&hdev
->hw
);
5582 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5583 pci_clear_master(pdev
);
5584 pci_release_regions(pdev
);
5585 pci_disable_device(pdev
);
5590 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5592 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5595 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5597 struct hclge_dev
*hdev
= ae_dev
->priv
;
5598 struct pci_dev
*pdev
= ae_dev
->pdev
;
5601 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5603 hclge_stats_clear(hdev
);
5604 memset(hdev
->vlan_table
, 0, sizeof(hdev
->vlan_table
));
5606 ret
= hclge_cmd_init(hdev
);
5608 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5612 ret
= hclge_get_cap(hdev
);
5614 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5619 ret
= hclge_configure(hdev
);
5621 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5625 ret
= hclge_map_tqp(hdev
);
5627 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5631 ret
= hclge_mac_init(hdev
);
5633 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5637 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5639 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5643 ret
= hclge_init_vlan_config(hdev
);
5645 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5649 ret
= hclge_tm_init_hw(hdev
);
5651 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5655 ret
= hclge_rss_init_hw(hdev
);
5657 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5661 /* Enable MISC vector(vector0) */
5662 hclge_enable_vector(&hdev
->misc_vector
, true);
5664 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5670 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5672 struct hclge_dev
*hdev
= ae_dev
->priv
;
5673 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5675 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5677 if (hdev
->service_timer
.function
)
5678 del_timer_sync(&hdev
->service_timer
);
5679 if (hdev
->service_task
.func
)
5680 cancel_work_sync(&hdev
->service_task
);
5681 if (hdev
->rst_service_task
.func
)
5682 cancel_work_sync(&hdev
->rst_service_task
);
5683 if (hdev
->mbx_service_task
.func
)
5684 cancel_work_sync(&hdev
->mbx_service_task
);
5687 mdiobus_unregister(mac
->mdio_bus
);
5689 /* Disable MISC vector(vector0) */
5690 hclge_enable_vector(&hdev
->misc_vector
, false);
5691 hclge_destroy_cmd_queue(&hdev
->hw
);
5692 hclge_misc_irq_uninit(hdev
);
5693 hclge_pci_uninit(hdev
);
5694 ae_dev
->priv
= NULL
;
5697 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5699 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5700 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5701 struct hclge_dev
*hdev
= vport
->back
;
5703 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5706 static void hclge_get_channels(struct hnae3_handle
*handle
,
5707 struct ethtool_channels
*ch
)
5709 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5711 ch
->max_combined
= hclge_get_max_channels(handle
);
5712 ch
->other_count
= 1;
5714 ch
->combined_count
= vport
->alloc_tqps
;
5717 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5718 u16
*free_tqps
, u16
*max_rss_size
)
5720 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5721 struct hclge_dev
*hdev
= vport
->back
;
5725 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5726 if (!hdev
->htqp
[i
].alloced
)
5729 *free_tqps
= temp_tqps
;
5730 *max_rss_size
= hdev
->rss_size_max
;
5733 static void hclge_release_tqp(struct hclge_vport
*vport
)
5735 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5736 struct hclge_dev
*hdev
= vport
->back
;
5739 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5740 struct hclge_tqp
*tqp
=
5741 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5743 tqp
->q
.handle
= NULL
;
5744 tqp
->q
.tqp_index
= 0;
5745 tqp
->alloced
= false;
5748 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5752 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5754 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5755 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5756 struct hclge_dev
*hdev
= vport
->back
;
5757 int cur_rss_size
= kinfo
->rss_size
;
5758 int cur_tqps
= kinfo
->num_tqps
;
5759 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5760 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5761 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5766 hclge_release_tqp(vport
);
5768 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5770 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5774 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5776 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5780 ret
= hclge_tm_schd_init(hdev
);
5782 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5786 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5787 roundup_size
= ilog2(roundup_size
);
5788 /* Set the RSS TC mode according to the new RSS size */
5789 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5792 if (!(hdev
->hw_tc_map
& BIT(i
)))
5796 tc_size
[i
] = roundup_size
;
5797 tc_offset
[i
] = kinfo
->rss_size
* i
;
5799 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5803 /* Reinitializes the rss indirect table according to the new RSS size */
5804 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5808 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5809 rss_indir
[i
] = i
% kinfo
->rss_size
;
5811 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5813 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5819 dev_info(&hdev
->pdev
->dev
,
5820 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5821 cur_rss_size
, kinfo
->rss_size
,
5822 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5827 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5828 u32
*regs_num_64_bit
)
5830 struct hclge_desc desc
;
5834 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
5835 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5837 dev_err(&hdev
->pdev
->dev
,
5838 "Query register number cmd failed, ret = %d.\n", ret
);
5842 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
5843 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
5845 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
5852 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5855 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
5857 struct hclge_desc
*desc
;
5858 u32
*reg_val
= data
;
5867 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
5868 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5872 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
5873 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5875 dev_err(&hdev
->pdev
->dev
,
5876 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
5881 for (i
= 0; i
< cmd_num
; i
++) {
5883 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
5884 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
5886 desc_data
= (__le32
*)(&desc
[i
]);
5887 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
5889 for (k
= 0; k
< n
; k
++) {
5890 *reg_val
++ = le32_to_cpu(*desc_data
++);
5902 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5905 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
5907 struct hclge_desc
*desc
;
5908 u64
*reg_val
= data
;
5917 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
5918 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5922 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
5923 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5925 dev_err(&hdev
->pdev
->dev
,
5926 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
5931 for (i
= 0; i
< cmd_num
; i
++) {
5933 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
5934 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
5936 desc_data
= (__le64
*)(&desc
[i
]);
5937 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
5939 for (k
= 0; k
< n
; k
++) {
5940 *reg_val
++ = le64_to_cpu(*desc_data
++);
5952 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
5954 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5955 struct hclge_dev
*hdev
= vport
->back
;
5956 u32 regs_num_32_bit
, regs_num_64_bit
;
5959 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
5961 dev_err(&hdev
->pdev
->dev
,
5962 "Get register number failed, ret = %d.\n", ret
);
5966 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
5969 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
5972 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5973 struct hclge_dev
*hdev
= vport
->back
;
5974 u32 regs_num_32_bit
, regs_num_64_bit
;
5977 *version
= hdev
->fw_version
;
5979 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
5981 dev_err(&hdev
->pdev
->dev
,
5982 "Get register number failed, ret = %d.\n", ret
);
5986 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
5988 dev_err(&hdev
->pdev
->dev
,
5989 "Get 32 bit register failed, ret = %d.\n", ret
);
5993 data
= (u32
*)data
+ regs_num_32_bit
;
5994 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
5997 dev_err(&hdev
->pdev
->dev
,
5998 "Get 64 bit register failed, ret = %d.\n", ret
);
6001 static int hclge_set_led_status(struct hclge_dev
*hdev
, u8 locate_led_status
)
6003 struct hclge_set_led_state_cmd
*req
;
6004 struct hclge_desc desc
;
6007 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6009 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6010 hnae_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6011 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6013 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6015 dev_err(&hdev
->pdev
->dev
,
6016 "Send set led state cmd error, ret =%d\n", ret
);
6021 enum hclge_led_status
{
6024 HCLGE_LED_NO_CHANGE
= 0xFF,
6027 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6028 enum ethtool_phys_id_state status
)
6030 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6031 struct hclge_dev
*hdev
= vport
->back
;
6034 case ETHTOOL_ID_ACTIVE
:
6035 return hclge_set_led_status(hdev
, HCLGE_LED_ON
);
6036 case ETHTOOL_ID_INACTIVE
:
6037 return hclge_set_led_status(hdev
, HCLGE_LED_OFF
);
6043 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6044 unsigned long *supported
,
6045 unsigned long *advertising
)
6047 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6048 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6049 struct hclge_dev
*hdev
= vport
->back
;
6050 unsigned int idx
= 0;
6052 for (; idx
< size
; idx
++) {
6053 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6054 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6058 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6061 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6062 struct hclge_dev
*hdev
= vport
->back
;
6063 u8 media_type
= hdev
->hw
.mac
.media_type
;
6065 switch (media_type
) {
6066 case HNAE3_MEDIA_TYPE_FIBER
:
6067 *port_type
= PORT_FIBRE
;
6069 case HNAE3_MEDIA_TYPE_COPPER
:
6070 *port_type
= PORT_TP
;
6072 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6074 *port_type
= PORT_OTHER
;
6079 static const struct hnae3_ae_ops hclge_ops
= {
6080 .init_ae_dev
= hclge_init_ae_dev
,
6081 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6082 .init_client_instance
= hclge_init_client_instance
,
6083 .uninit_client_instance
= hclge_uninit_client_instance
,
6084 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6085 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6086 .get_vector
= hclge_get_vector
,
6087 .put_vector
= hclge_put_vector
,
6088 .set_promisc_mode
= hclge_set_promisc_mode
,
6089 .set_loopback
= hclge_set_loopback
,
6090 .start
= hclge_ae_start
,
6091 .stop
= hclge_ae_stop
,
6092 .get_status
= hclge_get_status
,
6093 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6094 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6095 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6096 .get_media_type
= hclge_get_media_type
,
6097 .get_rss_key_size
= hclge_get_rss_key_size
,
6098 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6099 .get_rss
= hclge_get_rss
,
6100 .set_rss
= hclge_set_rss
,
6101 .set_rss_tuple
= hclge_set_rss_tuple
,
6102 .get_rss_tuple
= hclge_get_rss_tuple
,
6103 .get_tc_size
= hclge_get_tc_size
,
6104 .get_mac_addr
= hclge_get_mac_addr
,
6105 .set_mac_addr
= hclge_set_mac_addr
,
6106 .add_uc_addr
= hclge_add_uc_addr
,
6107 .rm_uc_addr
= hclge_rm_uc_addr
,
6108 .add_mc_addr
= hclge_add_mc_addr
,
6109 .rm_mc_addr
= hclge_rm_mc_addr
,
6110 .set_autoneg
= hclge_set_autoneg
,
6111 .get_autoneg
= hclge_get_autoneg
,
6112 .get_pauseparam
= hclge_get_pauseparam
,
6113 .set_pauseparam
= hclge_set_pauseparam
,
6114 .set_mtu
= hclge_set_mtu
,
6115 .reset_queue
= hclge_reset_tqp
,
6116 .get_stats
= hclge_get_stats
,
6117 .update_stats
= hclge_update_stats
,
6118 .get_strings
= hclge_get_strings
,
6119 .get_sset_count
= hclge_get_sset_count
,
6120 .get_fw_version
= hclge_get_fw_version
,
6121 .get_mdix_mode
= hclge_get_mdix_mode
,
6122 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6123 .set_vlan_filter
= hclge_set_vlan_filter
,
6124 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6125 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6126 .reset_event
= hclge_reset_event
,
6127 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6128 .set_channels
= hclge_set_channels
,
6129 .get_channels
= hclge_get_channels
,
6130 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6131 .get_regs_len
= hclge_get_regs_len
,
6132 .get_regs
= hclge_get_regs
,
6133 .set_led_id
= hclge_set_led_id
,
6134 .get_link_mode
= hclge_get_link_mode
,
6135 .get_port_type
= hclge_get_port_type
,
6138 static struct hnae3_ae_algo ae_algo
= {
6141 .pdev_id_table
= ae_algo_pci_tbl
,
6144 static int hclge_init(void)
6146 pr_info("%s is initializing\n", HCLGE_NAME
);
6148 hnae3_register_ae_algo(&ae_algo
);
6153 static void hclge_exit(void)
6155 hnae3_unregister_ae_algo(&ae_algo
);
6157 module_init(hclge_init
);
6158 module_exit(hclge_exit
);
6160 MODULE_LICENSE("GPL");
6161 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6162 MODULE_DESCRIPTION("HCLGE Driver");
6163 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob