2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
43 static struct hnae3_ae_algo ae_algo
;
45 static const struct pci_device_id ae_algo_pci_tbl
[] = {
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
53 /* required last entry */
57 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
59 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
61 "Serdes Loopback test",
65 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
104 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
229 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
393 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
395 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
396 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
397 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap
= 0x1,
403 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
405 #define HCLGE_64_BIT_CMD_NUM 5
406 #define HCLGE_64_BIT_RTN_DATANUM 4
407 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
408 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
413 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
414 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
416 dev_err(&hdev
->pdev
->dev
,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
421 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
422 if (unlikely(i
== 0)) {
423 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
424 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
426 desc_data
= (__le64
*)(&desc
[i
]);
427 n
= HCLGE_64_BIT_RTN_DATANUM
;
429 for (k
= 0; k
< n
; k
++) {
430 *data
++ += le64_to_cpu(*desc_data
);
438 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
440 stats
->pkt_curr_buf_cnt
= 0;
441 stats
->pkt_curr_buf_tc0_cnt
= 0;
442 stats
->pkt_curr_buf_tc1_cnt
= 0;
443 stats
->pkt_curr_buf_tc2_cnt
= 0;
444 stats
->pkt_curr_buf_tc3_cnt
= 0;
445 stats
->pkt_curr_buf_tc4_cnt
= 0;
446 stats
->pkt_curr_buf_tc5_cnt
= 0;
447 stats
->pkt_curr_buf_tc6_cnt
= 0;
448 stats
->pkt_curr_buf_tc7_cnt
= 0;
451 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
453 #define HCLGE_32_BIT_CMD_NUM 8
454 #define HCLGE_32_BIT_RTN_DATANUM 8
456 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
457 struct hclge_32_bit_stats
*all_32_bit_stats
;
463 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
464 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
466 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
467 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
469 dev_err(&hdev
->pdev
->dev
,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
475 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
476 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
477 if (unlikely(i
== 0)) {
478 __le16
*desc_data_16bit
;
480 all_32_bit_stats
->igu_rx_err_pkt
+=
481 le32_to_cpu(desc
[i
].data
[0]);
483 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
484 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
485 le16_to_cpu(*desc_data_16bit
);
488 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
489 le16_to_cpu(*desc_data_16bit
);
491 desc_data
= &desc
[i
].data
[2];
492 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
494 desc_data
= (__le32
*)&desc
[i
];
495 n
= HCLGE_32_BIT_RTN_DATANUM
;
497 for (k
= 0; k
< n
; k
++) {
498 *data
++ += le32_to_cpu(*desc_data
);
506 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
508 #define HCLGE_MAC_CMD_NUM 21
509 #define HCLGE_RTN_DATA_NUM 4
511 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
512 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
517 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
518 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
520 dev_err(&hdev
->pdev
->dev
,
521 "Get MAC pkt stats fail, status = %d.\n", ret
);
526 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
527 if (unlikely(i
== 0)) {
528 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
529 n
= HCLGE_RTN_DATA_NUM
- 2;
531 desc_data
= (__le64
*)(&desc
[i
]);
532 n
= HCLGE_RTN_DATA_NUM
;
534 for (k
= 0; k
< n
; k
++) {
535 *data
++ += le64_to_cpu(*desc_data
);
543 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
545 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
546 struct hclge_vport
*vport
= hclge_get_vport(handle
);
547 struct hclge_dev
*hdev
= vport
->back
;
548 struct hnae3_queue
*queue
;
549 struct hclge_desc desc
[1];
550 struct hclge_tqp
*tqp
;
553 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
554 queue
= handle
->kinfo
.tqp
[i
];
555 tqp
= container_of(queue
, struct hclge_tqp
, q
);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc
[0],
558 HCLGE_OPC_QUERY_RX_STATUS
,
561 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
562 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
564 dev_err(&hdev
->pdev
->dev
,
565 "Query tqp stat fail, status = %d,queue = %d\n",
569 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
570 le32_to_cpu(desc
[0].data
[1]);
573 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
574 queue
= handle
->kinfo
.tqp
[i
];
575 tqp
= container_of(queue
, struct hclge_tqp
, q
);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc
[0],
578 HCLGE_OPC_QUERY_TX_STATUS
,
581 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
582 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
584 dev_err(&hdev
->pdev
->dev
,
585 "Query tqp stat fail, status = %d,queue = %d\n",
589 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
590 le32_to_cpu(desc
[0].data
[1]);
596 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
598 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
599 struct hclge_tqp
*tqp
;
603 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
604 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
605 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
608 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
609 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
610 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
616 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
618 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
620 return kinfo
->num_tqps
* (2);
623 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
625 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
629 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
630 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
631 struct hclge_tqp
, q
);
632 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
634 buff
= buff
+ ETH_GSTRING_LEN
;
637 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
638 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
639 struct hclge_tqp
, q
);
640 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
642 buff
= buff
+ ETH_GSTRING_LEN
;
648 static u64
*hclge_comm_get_stats(void *comm_stats
,
649 const struct hclge_comm_stats_str strs
[],
655 for (i
= 0; i
< size
; i
++)
656 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
661 static u8
*hclge_comm_get_strings(u32 stringset
,
662 const struct hclge_comm_stats_str strs
[],
665 char *buff
= (char *)data
;
668 if (stringset
!= ETH_SS_STATS
)
671 for (i
= 0; i
< size
; i
++) {
672 snprintf(buff
, ETH_GSTRING_LEN
,
674 buff
= buff
+ ETH_GSTRING_LEN
;
680 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
681 struct net_device_stats
*net_stats
)
683 net_stats
->tx_dropped
= 0;
684 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
685 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
686 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
688 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
689 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
690 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
691 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
692 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
694 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
695 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
697 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
698 net_stats
->rx_length_errors
=
699 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
700 net_stats
->rx_length_errors
+=
701 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
702 net_stats
->rx_over_errors
=
703 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
706 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
708 struct hnae3_handle
*handle
;
711 handle
= &hdev
->vport
[0].nic
;
712 if (handle
->client
) {
713 status
= hclge_tqps_update_stats(handle
);
715 dev_err(&hdev
->pdev
->dev
,
716 "Update TQPS stats fail, status = %d.\n",
721 status
= hclge_mac_update_stats(hdev
);
723 dev_err(&hdev
->pdev
->dev
,
724 "Update MAC stats fail, status = %d.\n", status
);
726 status
= hclge_32_bit_update_stats(hdev
);
728 dev_err(&hdev
->pdev
->dev
,
729 "Update 32 bit stats fail, status = %d.\n",
732 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
735 static void hclge_update_stats(struct hnae3_handle
*handle
,
736 struct net_device_stats
*net_stats
)
738 struct hclge_vport
*vport
= hclge_get_vport(handle
);
739 struct hclge_dev
*hdev
= vport
->back
;
740 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
746 status
= hclge_mac_update_stats(hdev
);
748 dev_err(&hdev
->pdev
->dev
,
749 "Update MAC stats fail, status = %d.\n",
752 status
= hclge_32_bit_update_stats(hdev
);
754 dev_err(&hdev
->pdev
->dev
,
755 "Update 32 bit stats fail, status = %d.\n",
758 status
= hclge_64_bit_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update 64 bit stats fail, status = %d.\n",
764 status
= hclge_tqps_update_stats(handle
);
766 dev_err(&hdev
->pdev
->dev
,
767 "Update TQPS stats fail, status = %d.\n",
770 hclge_update_netstat(hw_stats
, net_stats
);
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
775 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
777 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
779 struct hclge_vport
*vport
= hclge_get_vport(handle
);
780 struct hclge_dev
*hdev
= vport
->back
;
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
788 if (stringset
== ETH_SS_TEST
) {
789 /* clear loopback bit flags at first */
790 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
791 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
792 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
793 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
795 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
799 handle
->flags
|= HNAE3_SUPPORT_SERDES_LOOPBACK
;
800 } else if (stringset
== ETH_SS_STATS
) {
801 count
= ARRAY_SIZE(g_mac_stats_string
) +
802 ARRAY_SIZE(g_all_32bit_stats_string
) +
803 ARRAY_SIZE(g_all_64bit_stats_string
) +
804 hclge_tqps_get_sset_count(handle
, stringset
);
810 static void hclge_get_strings(struct hnae3_handle
*handle
,
814 u8
*p
= (char *)data
;
817 if (stringset
== ETH_SS_STATS
) {
818 size
= ARRAY_SIZE(g_mac_stats_string
);
819 p
= hclge_comm_get_strings(stringset
,
823 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
824 p
= hclge_comm_get_strings(stringset
,
825 g_all_32bit_stats_string
,
828 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
829 p
= hclge_comm_get_strings(stringset
,
830 g_all_64bit_stats_string
,
833 p
= hclge_tqps_get_strings(handle
, p
);
834 } else if (stringset
== ETH_SS_TEST
) {
835 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
837 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
839 p
+= ETH_GSTRING_LEN
;
841 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
843 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
845 p
+= ETH_GSTRING_LEN
;
847 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
849 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
851 p
+= ETH_GSTRING_LEN
;
856 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
858 struct hclge_vport
*vport
= hclge_get_vport(handle
);
859 struct hclge_dev
*hdev
= vport
->back
;
862 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
864 ARRAY_SIZE(g_mac_stats_string
),
866 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
867 g_all_32bit_stats_string
,
868 ARRAY_SIZE(g_all_32bit_stats_string
),
870 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
871 g_all_64bit_stats_string
,
872 ARRAY_SIZE(g_all_64bit_stats_string
),
874 p
= hclge_tqps_get_stats(handle
, p
);
877 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
878 struct hclge_func_status_cmd
*status
)
880 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
883 /* Set the pf to main pf */
884 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
885 hdev
->flag
|= HCLGE_FLAG_MAIN
;
887 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
892 static int hclge_query_function_status(struct hclge_dev
*hdev
)
894 struct hclge_func_status_cmd
*req
;
895 struct hclge_desc desc
;
899 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
900 req
= (struct hclge_func_status_cmd
*)desc
.data
;
903 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
905 dev_err(&hdev
->pdev
->dev
,
906 "query function status failed %d.\n",
912 /* Check pf reset is done */
915 usleep_range(1000, 2000);
916 } while (timeout
++ < 5);
918 ret
= hclge_parse_func_status(hdev
, req
);
923 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
925 struct hclge_pf_res_cmd
*req
;
926 struct hclge_desc desc
;
929 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
930 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
932 dev_err(&hdev
->pdev
->dev
,
933 "query pf resource failed %d.\n", ret
);
937 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
938 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
939 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
941 if (hnae3_dev_roce_supported(hdev
)) {
943 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
944 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
946 /* PF should have NIC vectors and Roce vectors,
947 * NIC vectors are queued before Roce vectors.
949 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
952 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
953 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
959 static int hclge_parse_speed(int speed_cmd
, int *speed
)
963 *speed
= HCLGE_MAC_SPEED_10M
;
966 *speed
= HCLGE_MAC_SPEED_100M
;
969 *speed
= HCLGE_MAC_SPEED_1G
;
972 *speed
= HCLGE_MAC_SPEED_10G
;
975 *speed
= HCLGE_MAC_SPEED_25G
;
978 *speed
= HCLGE_MAC_SPEED_40G
;
981 *speed
= HCLGE_MAC_SPEED_50G
;
984 *speed
= HCLGE_MAC_SPEED_100G
;
993 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
996 unsigned long *supported
= hdev
->hw
.mac
.supported
;
998 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
999 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1002 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1003 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1006 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1007 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1010 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1011 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1014 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1015 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1018 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1019 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1022 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1024 u8 media_type
= hdev
->hw
.mac
.media_type
;
1026 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1029 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1032 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1034 struct hclge_cfg_param_cmd
*req
;
1035 u64 mac_addr_tmp_high
;
1039 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1041 /* get the configuration */
1042 cfg
->vmdq_vport_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1045 cfg
->tc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1046 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1047 cfg
->tqp_desc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1048 HCLGE_CFG_TQP_DESC_N_M
,
1049 HCLGE_CFG_TQP_DESC_N_S
);
1051 cfg
->phy_addr
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1052 HCLGE_CFG_PHY_ADDR_M
,
1053 HCLGE_CFG_PHY_ADDR_S
);
1054 cfg
->media_type
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1055 HCLGE_CFG_MEDIA_TP_M
,
1056 HCLGE_CFG_MEDIA_TP_S
);
1057 cfg
->rx_buf_len
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1058 HCLGE_CFG_RX_BUF_LEN_M
,
1059 HCLGE_CFG_RX_BUF_LEN_S
);
1060 /* get mac_address */
1061 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1062 mac_addr_tmp_high
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1063 HCLGE_CFG_MAC_ADDR_H_M
,
1064 HCLGE_CFG_MAC_ADDR_H_S
);
1066 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1068 cfg
->default_speed
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1069 HCLGE_CFG_DEFAULT_SPEED_M
,
1070 HCLGE_CFG_DEFAULT_SPEED_S
);
1071 cfg
->rss_size_max
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1072 HCLGE_CFG_RSS_SIZE_M
,
1073 HCLGE_CFG_RSS_SIZE_S
);
1075 for (i
= 0; i
< ETH_ALEN
; i
++)
1076 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1078 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1079 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1081 cfg
->speed_ability
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1082 HCLGE_CFG_SPEED_ABILITY_M
,
1083 HCLGE_CFG_SPEED_ABILITY_S
);
1086 /* hclge_get_cfg: query the static parameter from flash
1087 * @hdev: pointer to struct hclge_dev
1088 * @hcfg: the config structure to be getted
1090 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1092 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1093 struct hclge_cfg_param_cmd
*req
;
1096 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1099 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1100 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1102 hnae3_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1103 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1104 /* Len should be united by 4 bytes when send to hardware */
1105 hnae3_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1106 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1107 req
->offset
= cpu_to_le32(offset
);
1110 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1112 dev_err(&hdev
->pdev
->dev
, "get config failed %d.\n", ret
);
1116 hclge_parse_cfg(hcfg
, desc
);
1121 static int hclge_get_cap(struct hclge_dev
*hdev
)
1125 ret
= hclge_query_function_status(hdev
);
1127 dev_err(&hdev
->pdev
->dev
,
1128 "query function status error %d.\n", ret
);
1132 /* get pf resource */
1133 ret
= hclge_query_pf_resource(hdev
);
1135 dev_err(&hdev
->pdev
->dev
, "query pf resource error %d.\n", ret
);
1140 static int hclge_configure(struct hclge_dev
*hdev
)
1142 struct hclge_cfg cfg
;
1145 ret
= hclge_get_cfg(hdev
, &cfg
);
1147 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1151 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1152 hdev
->base_tqp_pid
= 0;
1153 hdev
->rss_size_max
= cfg
.rss_size_max
;
1154 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1155 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1156 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1157 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1158 hdev
->num_desc
= cfg
.tqp_desc_num
;
1159 hdev
->tm_info
.num_pg
= 1;
1160 hdev
->tc_max
= cfg
.tc_num
;
1161 hdev
->tm_info
.hw_pfc_map
= 0;
1163 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1165 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1169 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1171 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1172 (hdev
->tc_max
< 1)) {
1173 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1178 /* Dev does not support DCB */
1179 if (!hnae3_dev_dcb_supported(hdev
)) {
1183 hdev
->pfc_max
= hdev
->tc_max
;
1186 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1188 /* Currently not support uncontiuous tc */
1189 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1190 hnae3_set_bit(hdev
->hw_tc_map
, i
, 1);
1192 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1197 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1200 struct hclge_cfg_tso_status_cmd
*req
;
1201 struct hclge_desc desc
;
1204 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1206 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1209 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1210 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1211 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1214 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1215 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1216 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1218 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1221 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1223 struct hclge_tqp
*tqp
;
1226 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1227 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1233 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1234 tqp
->dev
= &hdev
->pdev
->dev
;
1237 tqp
->q
.ae_algo
= &ae_algo
;
1238 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1239 tqp
->q
.desc_num
= hdev
->num_desc
;
1240 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1241 i
* HCLGE_TQP_REG_SIZE
;
1249 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1250 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1252 struct hclge_tqp_map_cmd
*req
;
1253 struct hclge_desc desc
;
1256 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1258 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1259 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1260 req
->tqp_vf
= func_id
;
1261 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1262 1 << HCLGE_TQP_MAP_EN_B
;
1263 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1265 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1267 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n", ret
);
1272 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1273 struct hnae3_queue
**tqp
, u16 num_tqps
)
1275 struct hclge_dev
*hdev
= vport
->back
;
1278 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1279 alloced
< num_tqps
; i
++) {
1280 if (!hdev
->htqp
[i
].alloced
) {
1281 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1282 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1283 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1284 hdev
->htqp
[i
].alloced
= true;
1288 vport
->alloc_tqps
= num_tqps
;
1293 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1295 struct hnae3_handle
*nic
= &vport
->nic
;
1296 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1297 struct hclge_dev
*hdev
= vport
->back
;
1300 kinfo
->num_desc
= hdev
->num_desc
;
1301 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1302 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1304 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1305 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1307 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1308 if (hdev
->hw_tc_map
& BIT(i
)) {
1309 kinfo
->tc_info
[i
].enable
= true;
1310 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1311 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1312 kinfo
->tc_info
[i
].tc
= i
;
1314 /* Set to default queue if TC is disable */
1315 kinfo
->tc_info
[i
].enable
= false;
1316 kinfo
->tc_info
[i
].tqp_offset
= 0;
1317 kinfo
->tc_info
[i
].tqp_count
= 1;
1318 kinfo
->tc_info
[i
].tc
= 0;
1322 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1323 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1327 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1329 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1334 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1335 struct hclge_vport
*vport
)
1337 struct hnae3_handle
*nic
= &vport
->nic
;
1338 struct hnae3_knic_private_info
*kinfo
;
1341 kinfo
= &nic
->kinfo
;
1342 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1343 struct hclge_tqp
*q
=
1344 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1348 is_pf
= !(vport
->vport_id
);
1349 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1358 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1360 struct hclge_vport
*vport
= hdev
->vport
;
1363 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1364 for (i
= 0; i
< num_vport
; i
++) {
1367 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1377 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1379 /* this would be initialized later */
1382 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1384 struct hnae3_handle
*nic
= &vport
->nic
;
1385 struct hclge_dev
*hdev
= vport
->back
;
1388 nic
->pdev
= hdev
->pdev
;
1389 nic
->ae_algo
= &ae_algo
;
1390 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1392 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1393 ret
= hclge_knic_setup(vport
, num_tqps
);
1395 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1400 hclge_unic_setup(vport
, num_tqps
);
1406 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1408 struct pci_dev
*pdev
= hdev
->pdev
;
1409 struct hclge_vport
*vport
;
1415 /* We need to alloc a vport for main NIC of PF */
1416 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1418 if (hdev
->num_tqps
< num_vport
) {
1419 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1420 hdev
->num_tqps
, num_vport
);
1424 /* Alloc the same number of TQPs for every vport */
1425 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1426 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1428 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1433 hdev
->vport
= vport
;
1434 hdev
->num_alloc_vport
= num_vport
;
1436 if (IS_ENABLED(CONFIG_PCI_IOV
))
1437 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1439 for (i
= 0; i
< num_vport
; i
++) {
1441 vport
->vport_id
= i
;
1444 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1446 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1449 "vport setup failed for vport %d, %d\n",
1460 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1461 struct hclge_pkt_buf_alloc
*buf_alloc
)
1463 /* TX buffer size is unit by 128 byte */
1464 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1465 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1466 struct hclge_tx_buff_alloc_cmd
*req
;
1467 struct hclge_desc desc
;
1471 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1473 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1474 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1475 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1477 req
->tx_pkt_buff
[i
] =
1478 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1479 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1482 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1484 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1490 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1491 struct hclge_pkt_buf_alloc
*buf_alloc
)
1493 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1496 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc failed %d\n", ret
);
1501 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1505 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1506 if (hdev
->hw_tc_map
& BIT(i
))
1511 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1515 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1516 if (hdev
->hw_tc_map
& BIT(i
) &&
1517 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1522 /* Get the number of pfc enabled TCs, which have private buffer */
1523 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1524 struct hclge_pkt_buf_alloc
*buf_alloc
)
1526 struct hclge_priv_buf
*priv
;
1529 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1530 priv
= &buf_alloc
->priv_buf
[i
];
1531 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1539 /* Get the number of pfc disabled TCs, which have private buffer */
1540 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1541 struct hclge_pkt_buf_alloc
*buf_alloc
)
1543 struct hclge_priv_buf
*priv
;
1546 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1547 priv
= &buf_alloc
->priv_buf
[i
];
1548 if (hdev
->hw_tc_map
& BIT(i
) &&
1549 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1557 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1559 struct hclge_priv_buf
*priv
;
1563 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1564 priv
= &buf_alloc
->priv_buf
[i
];
1566 rx_priv
+= priv
->buf_size
;
1571 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1573 u32 i
, total_tx_size
= 0;
1575 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1576 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1578 return total_tx_size
;
1581 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1582 struct hclge_pkt_buf_alloc
*buf_alloc
,
1585 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1586 int tc_num
, pfc_enable_num
;
1591 tc_num
= hclge_get_tc_num(hdev
);
1592 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1594 if (hnae3_dev_dcb_supported(hdev
))
1595 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1597 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1599 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1600 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1602 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1604 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1605 if (rx_all
<= rx_priv
+ shared_std
)
1608 shared_buf
= rx_all
- rx_priv
;
1609 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1610 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1611 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1613 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1614 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1615 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1616 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1617 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1619 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1620 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1627 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1628 struct hclge_pkt_buf_alloc
*buf_alloc
)
1632 total_size
= hdev
->pkt_buf_size
;
1634 /* alloc tx buffer for all enabled tc */
1635 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1636 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1638 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1641 if (hdev
->hw_tc_map
& BIT(i
))
1642 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1644 priv
->tx_buf_size
= 0;
1646 total_size
-= priv
->tx_buf_size
;
1652 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1653 * @hdev: pointer to struct hclge_dev
1654 * @buf_alloc: pointer to buffer calculation data
1655 * @return: 0: calculate sucessful, negative: fail
1657 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1658 struct hclge_pkt_buf_alloc
*buf_alloc
)
1660 u32 rx_all
= hdev
->pkt_buf_size
;
1661 int no_pfc_priv_num
, pfc_priv_num
;
1662 struct hclge_priv_buf
*priv
;
1665 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1667 /* When DCB is not supported, rx private
1668 * buffer is not allocated.
1670 if (!hnae3_dev_dcb_supported(hdev
)) {
1671 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1677 /* step 1, try to alloc private buffer for all enabled tc */
1678 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1679 priv
= &buf_alloc
->priv_buf
[i
];
1680 if (hdev
->hw_tc_map
& BIT(i
)) {
1682 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1683 priv
->wl
.low
= hdev
->mps
;
1684 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1685 priv
->buf_size
= priv
->wl
.high
+
1689 priv
->wl
.high
= 2 * hdev
->mps
;
1690 priv
->buf_size
= priv
->wl
.high
;
1700 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1703 /* step 2, try to decrease the buffer size of
1704 * no pfc TC's private buffer
1706 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1707 priv
= &buf_alloc
->priv_buf
[i
];
1714 if (!(hdev
->hw_tc_map
& BIT(i
)))
1719 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1721 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1722 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1725 priv
->wl
.high
= hdev
->mps
;
1726 priv
->buf_size
= priv
->wl
.high
;
1730 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1733 /* step 3, try to reduce the number of pfc disabled TCs,
1734 * which have private buffer
1736 /* get the total no pfc enable TC number, which have private buffer */
1737 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1739 /* let the last to be cleared first */
1740 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1741 priv
= &buf_alloc
->priv_buf
[i
];
1743 if (hdev
->hw_tc_map
& BIT(i
) &&
1744 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1745 /* Clear the no pfc TC private buffer */
1753 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1754 no_pfc_priv_num
== 0)
1758 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1761 /* step 4, try to reduce the number of pfc enabled TCs
1762 * which have private buffer.
1764 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1766 /* let the last to be cleared first */
1767 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1768 priv
= &buf_alloc
->priv_buf
[i
];
1770 if (hdev
->hw_tc_map
& BIT(i
) &&
1771 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1772 /* Reduce the number of pfc TC with private buffer */
1780 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1784 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1790 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1791 struct hclge_pkt_buf_alloc
*buf_alloc
)
1793 struct hclge_rx_priv_buff_cmd
*req
;
1794 struct hclge_desc desc
;
1798 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1799 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1801 /* Alloc private buffer TCs */
1802 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1803 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1806 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1808 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1812 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1813 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1815 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1817 dev_err(&hdev
->pdev
->dev
,
1818 "rx private buffer alloc cmd failed %d\n", ret
);
1823 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1825 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1826 struct hclge_pkt_buf_alloc
*buf_alloc
)
1828 struct hclge_rx_priv_wl_buf
*req
;
1829 struct hclge_priv_buf
*priv
;
1830 struct hclge_desc desc
[2];
1834 for (i
= 0; i
< 2; i
++) {
1835 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1837 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1839 /* The first descriptor set the NEXT bit to 1 */
1841 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1843 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1845 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1846 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1848 priv
= &buf_alloc
->priv_buf
[idx
];
1849 req
->tc_wl
[j
].high
=
1850 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1851 req
->tc_wl
[j
].high
|=
1852 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1853 HCLGE_RX_PRIV_EN_B
);
1855 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1856 req
->tc_wl
[j
].low
|=
1857 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1858 HCLGE_RX_PRIV_EN_B
);
1862 /* Send 2 descriptor at one time */
1863 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1865 dev_err(&hdev
->pdev
->dev
,
1866 "rx private waterline config cmd failed %d\n",
1871 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1872 struct hclge_pkt_buf_alloc
*buf_alloc
)
1874 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1875 struct hclge_rx_com_thrd
*req
;
1876 struct hclge_desc desc
[2];
1877 struct hclge_tc_thrd
*tc
;
1881 for (i
= 0; i
< 2; i
++) {
1882 hclge_cmd_setup_basic_desc(&desc
[i
],
1883 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1884 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1886 /* The first descriptor set the NEXT bit to 1 */
1888 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1890 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1892 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1893 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1895 req
->com_thrd
[j
].high
=
1896 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1897 req
->com_thrd
[j
].high
|=
1898 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1899 HCLGE_RX_PRIV_EN_B
);
1900 req
->com_thrd
[j
].low
=
1901 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1902 req
->com_thrd
[j
].low
|=
1903 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1904 HCLGE_RX_PRIV_EN_B
);
1908 /* Send 2 descriptors at one time */
1909 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1911 dev_err(&hdev
->pdev
->dev
,
1912 "common threshold config cmd failed %d\n", ret
);
1916 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1917 struct hclge_pkt_buf_alloc
*buf_alloc
)
1919 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1920 struct hclge_rx_com_wl
*req
;
1921 struct hclge_desc desc
;
1924 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1926 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1927 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1929 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1930 HCLGE_RX_PRIV_EN_B
);
1932 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1934 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1935 HCLGE_RX_PRIV_EN_B
);
1937 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1939 dev_err(&hdev
->pdev
->dev
,
1940 "common waterline config cmd failed %d\n", ret
);
1944 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1946 struct hclge_pkt_buf_alloc
*pkt_buf
;
1949 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1953 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1955 dev_err(&hdev
->pdev
->dev
,
1956 "could not calc tx buffer size for all TCs %d\n", ret
);
1960 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1962 dev_err(&hdev
->pdev
->dev
,
1963 "could not alloc tx buffers %d\n", ret
);
1967 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1969 dev_err(&hdev
->pdev
->dev
,
1970 "could not calc rx priv buffer size for all TCs %d\n",
1975 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1977 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1982 if (hnae3_dev_dcb_supported(hdev
)) {
1983 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1985 dev_err(&hdev
->pdev
->dev
,
1986 "could not configure rx private waterline %d\n",
1991 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
1993 dev_err(&hdev
->pdev
->dev
,
1994 "could not configure common threshold %d\n",
2000 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2002 dev_err(&hdev
->pdev
->dev
,
2003 "could not configure common waterline %d\n", ret
);
2010 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2012 struct hnae3_handle
*roce
= &vport
->roce
;
2013 struct hnae3_handle
*nic
= &vport
->nic
;
2015 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2017 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2018 vport
->back
->num_msi_left
== 0)
2021 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2023 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2024 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2026 roce
->pdev
= nic
->pdev
;
2027 roce
->ae_algo
= nic
->ae_algo
;
2028 roce
->numa_node_mask
= nic
->numa_node_mask
;
2033 static int hclge_init_msi(struct hclge_dev
*hdev
)
2035 struct pci_dev
*pdev
= hdev
->pdev
;
2039 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2040 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2043 "failed(%d) to allocate MSI/MSI-X vectors\n",
2047 if (vectors
< hdev
->num_msi
)
2048 dev_warn(&hdev
->pdev
->dev
,
2049 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2050 hdev
->num_msi
, vectors
);
2052 hdev
->num_msi
= vectors
;
2053 hdev
->num_msi_left
= vectors
;
2054 hdev
->base_msi_vector
= pdev
->irq
;
2055 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2056 HCLGE_ROCE_VECTOR_OFFSET
;
2058 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2059 sizeof(u16
), GFP_KERNEL
);
2060 if (!hdev
->vector_status
) {
2061 pci_free_irq_vectors(pdev
);
2065 for (i
= 0; i
< hdev
->num_msi
; i
++)
2066 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2068 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2069 sizeof(int), GFP_KERNEL
);
2070 if (!hdev
->vector_irq
) {
2071 pci_free_irq_vectors(pdev
);
2078 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2080 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2082 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2083 mac
->duplex
= (u8
)duplex
;
2085 mac
->duplex
= HCLGE_MAC_FULL
;
2090 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2092 struct hclge_config_mac_speed_dup_cmd
*req
;
2093 struct hclge_desc desc
;
2096 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2098 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2100 hnae3_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2103 case HCLGE_MAC_SPEED_10M
:
2104 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2105 HCLGE_CFG_SPEED_S
, 6);
2107 case HCLGE_MAC_SPEED_100M
:
2108 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2109 HCLGE_CFG_SPEED_S
, 7);
2111 case HCLGE_MAC_SPEED_1G
:
2112 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2113 HCLGE_CFG_SPEED_S
, 0);
2115 case HCLGE_MAC_SPEED_10G
:
2116 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2117 HCLGE_CFG_SPEED_S
, 1);
2119 case HCLGE_MAC_SPEED_25G
:
2120 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2121 HCLGE_CFG_SPEED_S
, 2);
2123 case HCLGE_MAC_SPEED_40G
:
2124 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2125 HCLGE_CFG_SPEED_S
, 3);
2127 case HCLGE_MAC_SPEED_50G
:
2128 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2129 HCLGE_CFG_SPEED_S
, 4);
2131 case HCLGE_MAC_SPEED_100G
:
2132 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2133 HCLGE_CFG_SPEED_S
, 5);
2136 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2140 hnae3_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2143 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2145 dev_err(&hdev
->pdev
->dev
,
2146 "mac speed/duplex config cmd failed %d.\n", ret
);
2150 hclge_check_speed_dup(hdev
, duplex
, speed
);
2155 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2158 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2159 struct hclge_dev
*hdev
= vport
->back
;
2161 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2164 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2167 struct hclge_query_an_speed_dup_cmd
*req
;
2168 struct hclge_desc desc
;
2172 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2174 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2175 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2177 dev_err(&hdev
->pdev
->dev
,
2178 "mac speed/autoneg/duplex query cmd failed %d\n",
2183 *duplex
= hnae3_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2184 speed_tmp
= hnae3_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2185 HCLGE_QUERY_SPEED_S
);
2187 ret
= hclge_parse_speed(speed_tmp
, speed
);
2189 dev_err(&hdev
->pdev
->dev
,
2190 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2195 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2197 struct hclge_config_auto_neg_cmd
*req
;
2198 struct hclge_desc desc
;
2202 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2204 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2205 hnae3_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2206 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2208 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2210 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2216 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2218 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2219 struct hclge_dev
*hdev
= vport
->back
;
2221 return hclge_set_autoneg_en(hdev
, enable
);
2224 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2226 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2227 struct hclge_dev
*hdev
= vport
->back
;
2228 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2231 return phydev
->autoneg
;
2233 return hdev
->hw
.mac
.autoneg
;
2236 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2240 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2241 struct hclge_desc desc
;
2244 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2245 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2247 hnae3_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2249 ether_addr_copy(req
->mac_mask
, mac_mask
);
2251 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2253 dev_err(&hdev
->pdev
->dev
,
2254 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2260 static int hclge_mac_init(struct hclge_dev
*hdev
)
2262 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2263 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2264 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2265 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2266 struct hclge_vport
*vport
;
2271 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2273 dev_err(&hdev
->pdev
->dev
,
2274 "Config mac speed dup fail ret=%d\n", ret
);
2280 /* Initialize the MTA table work mode */
2281 hdev
->enable_mta
= true;
2282 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2284 ret
= hclge_set_mta_filter_mode(hdev
,
2285 hdev
->mta_mac_sel_type
,
2288 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2293 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
2294 vport
= &hdev
->vport
[i
];
2295 vport
->accept_mta_mc
= false;
2297 memset(vport
->mta_shadow
, 0, sizeof(vport
->mta_shadow
));
2298 ret
= hclge_cfg_func_mta_filter(hdev
, vport
->vport_id
, false);
2300 dev_err(&hdev
->pdev
->dev
,
2301 "set mta filter mode fail ret=%d\n", ret
);
2306 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2308 dev_err(&hdev
->pdev
->dev
,
2309 "set default mac_vlan_mask fail ret=%d\n", ret
);
2318 ret
= hclge_set_mtu(handle
, mtu
);
2320 dev_err(&hdev
->pdev
->dev
,
2321 "set mtu failed ret=%d\n", ret
);
2326 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2328 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2329 schedule_work(&hdev
->mbx_service_task
);
2332 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2334 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2335 schedule_work(&hdev
->rst_service_task
);
2338 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2340 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2341 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2342 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2343 (void)schedule_work(&hdev
->service_task
);
2346 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2348 struct hclge_link_status_cmd
*req
;
2349 struct hclge_desc desc
;
2353 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2354 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2356 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2361 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2362 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2364 return !!link_status
;
2367 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2372 mac_state
= hclge_get_mac_link_status(hdev
);
2374 if (hdev
->hw
.mac
.phydev
) {
2375 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2376 link_stat
= mac_state
&
2377 hdev
->hw
.mac
.phydev
->link
;
2382 link_stat
= mac_state
;
2388 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2390 struct hnae3_client
*rclient
= hdev
->roce_client
;
2391 struct hnae3_client
*client
= hdev
->nic_client
;
2392 struct hnae3_handle
*rhandle
;
2393 struct hnae3_handle
*handle
;
2399 state
= hclge_get_mac_phy_link(hdev
);
2400 if (state
!= hdev
->hw
.mac
.link
) {
2401 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2402 handle
= &hdev
->vport
[i
].nic
;
2403 client
->ops
->link_status_change(handle
, state
);
2404 rhandle
= &hdev
->vport
[i
].roce
;
2405 if (rclient
&& rclient
->ops
->link_status_change
)
2406 rclient
->ops
->link_status_change(rhandle
,
2409 hdev
->hw
.mac
.link
= state
;
2413 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2415 struct hclge_mac mac
= hdev
->hw
.mac
;
2420 /* get the speed and duplex as autoneg'result from mac cmd when phy
2423 if (mac
.phydev
|| !mac
.autoneg
)
2426 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2428 dev_err(&hdev
->pdev
->dev
,
2429 "mac autoneg/speed/duplex query failed %d\n", ret
);
2433 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2434 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2436 dev_err(&hdev
->pdev
->dev
,
2437 "mac speed/duplex config failed %d\n", ret
);
2445 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2447 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2448 struct hclge_dev
*hdev
= vport
->back
;
2450 return hclge_update_speed_duplex(hdev
);
2453 static int hclge_get_status(struct hnae3_handle
*handle
)
2455 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2456 struct hclge_dev
*hdev
= vport
->back
;
2458 hclge_update_link_status(hdev
);
2460 return hdev
->hw
.mac
.link
;
2463 static void hclge_service_timer(struct timer_list
*t
)
2465 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2467 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2468 hdev
->hw_stats
.stats_timer
++;
2469 hclge_task_schedule(hdev
);
2472 static void hclge_service_complete(struct hclge_dev
*hdev
)
2474 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2476 /* Flush memory before next watchdog */
2477 smp_mb__before_atomic();
2478 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2481 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2486 /* fetch the events from their corresponding regs */
2487 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2488 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2490 /* Assumption: If by any chance reset and mailbox events are reported
2491 * together then we will only process reset event in this go and will
2492 * defer the processing of the mailbox events. Since, we would have not
2493 * cleared RX CMDQ event this time we would receive again another
2494 * interrupt from H/W just for the mailbox.
2497 /* check for vector0 reset event sources */
2498 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2499 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2500 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2501 return HCLGE_VECTOR0_EVENT_RST
;
2504 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2505 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2506 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2507 return HCLGE_VECTOR0_EVENT_RST
;
2510 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2511 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2512 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2513 return HCLGE_VECTOR0_EVENT_RST
;
2516 /* check for vector0 mailbox(=CMDQ RX) event source */
2517 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2518 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2519 *clearval
= cmdq_src_reg
;
2520 return HCLGE_VECTOR0_EVENT_MBX
;
2523 return HCLGE_VECTOR0_EVENT_OTHER
;
2526 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2529 switch (event_type
) {
2530 case HCLGE_VECTOR0_EVENT_RST
:
2531 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2533 case HCLGE_VECTOR0_EVENT_MBX
:
2534 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2539 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2541 writel(enable
? 1 : 0, vector
->addr
);
2544 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2546 struct hclge_dev
*hdev
= data
;
2550 hclge_enable_vector(&hdev
->misc_vector
, false);
2551 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2553 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2554 switch (event_cause
) {
2555 case HCLGE_VECTOR0_EVENT_RST
:
2556 hclge_reset_task_schedule(hdev
);
2558 case HCLGE_VECTOR0_EVENT_MBX
:
2559 /* If we are here then,
2560 * 1. Either we are not handling any mbx task and we are not
2563 * 2. We could be handling a mbx task but nothing more is
2565 * In both cases, we should schedule mbx task as there are more
2566 * mbx messages reported by this interrupt.
2568 hclge_mbx_task_schedule(hdev
);
2571 dev_warn(&hdev
->pdev
->dev
,
2572 "received unknown or unhandled event of vector0\n");
2576 /* clear the source of interrupt if it is not cause by reset */
2577 if (event_cause
!= HCLGE_VECTOR0_EVENT_RST
) {
2578 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2579 hclge_enable_vector(&hdev
->misc_vector
, true);
2585 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2587 if (hdev
->vector_status
[vector_id
] == HCLGE_INVALID_VPORT
) {
2588 dev_warn(&hdev
->pdev
->dev
,
2589 "vector(vector_id %d) has been freed.\n", vector_id
);
2593 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2594 hdev
->num_msi_left
+= 1;
2595 hdev
->num_msi_used
-= 1;
2598 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2600 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2602 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2604 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2605 hdev
->vector_status
[0] = 0;
2607 hdev
->num_msi_left
-= 1;
2608 hdev
->num_msi_used
+= 1;
2611 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2615 hclge_get_misc_vector(hdev
);
2617 /* this would be explicitly freed in the end */
2618 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2619 0, "hclge_misc", hdev
);
2621 hclge_free_vector(hdev
, 0);
2622 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2623 hdev
->misc_vector
.vector_irq
);
2629 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2631 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2632 hclge_free_vector(hdev
, 0);
2635 static int hclge_notify_client(struct hclge_dev
*hdev
,
2636 enum hnae3_reset_notify_type type
)
2638 struct hnae3_client
*rclient
= hdev
->roce_client
;
2639 struct hnae3_client
*client
= hdev
->nic_client
;
2640 struct hnae3_handle
*handle
;
2644 if (!client
->ops
->reset_notify
)
2647 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2648 handle
= &hdev
->vport
[i
].nic
;
2649 ret
= client
->ops
->reset_notify(handle
, type
);
2651 dev_err(&hdev
->pdev
->dev
,
2652 "notify nic client failed %d", ret
);
2656 if (rclient
&& rclient
->ops
->reset_notify
) {
2657 handle
= &hdev
->vport
[i
].roce
;
2658 ret
= rclient
->ops
->reset_notify(handle
, type
);
2660 dev_err(&hdev
->pdev
->dev
,
2661 "notify roce client failed %d", ret
);
2670 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2672 #define HCLGE_RESET_WATI_MS 100
2673 #define HCLGE_RESET_WAIT_CNT 5
2674 u32 val
, reg
, reg_bit
;
2677 switch (hdev
->reset_type
) {
2678 case HNAE3_GLOBAL_RESET
:
2679 reg
= HCLGE_GLOBAL_RESET_REG
;
2680 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2682 case HNAE3_CORE_RESET
:
2683 reg
= HCLGE_GLOBAL_RESET_REG
;
2684 reg_bit
= HCLGE_CORE_RESET_BIT
;
2686 case HNAE3_FUNC_RESET
:
2687 reg
= HCLGE_FUN_RST_ING
;
2688 reg_bit
= HCLGE_FUN_RST_ING_B
;
2691 dev_err(&hdev
->pdev
->dev
,
2692 "Wait for unsupported reset type: %d\n",
2697 val
= hclge_read_dev(&hdev
->hw
, reg
);
2698 while (hnae3_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
&&
2699 test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
2700 msleep(HCLGE_RESET_WATI_MS
);
2701 val
= hclge_read_dev(&hdev
->hw
, reg
);
2705 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2706 dev_warn(&hdev
->pdev
->dev
,
2707 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2714 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2716 struct hclge_desc desc
;
2717 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2720 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2721 hnae3_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2722 req
->fun_reset_vfid
= func_id
;
2724 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2726 dev_err(&hdev
->pdev
->dev
,
2727 "send function reset cmd fail, status =%d\n", ret
);
2732 static void hclge_do_reset(struct hclge_dev
*hdev
)
2734 struct pci_dev
*pdev
= hdev
->pdev
;
2737 switch (hdev
->reset_type
) {
2738 case HNAE3_GLOBAL_RESET
:
2739 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2740 hnae3_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2741 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2742 dev_info(&pdev
->dev
, "Global Reset requested\n");
2744 case HNAE3_CORE_RESET
:
2745 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2746 hnae3_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2747 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2748 dev_info(&pdev
->dev
, "Core Reset requested\n");
2750 case HNAE3_FUNC_RESET
:
2751 dev_info(&pdev
->dev
, "PF Reset requested\n");
2752 hclge_func_reset_cmd(hdev
, 0);
2753 /* schedule again to check later */
2754 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2755 hclge_reset_task_schedule(hdev
);
2758 dev_warn(&pdev
->dev
,
2759 "Unsupported reset type: %d\n", hdev
->reset_type
);
2764 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2765 unsigned long *addr
)
2767 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2769 /* return the highest priority reset level amongst all */
2770 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2771 rst_level
= HNAE3_GLOBAL_RESET
;
2772 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2773 rst_level
= HNAE3_CORE_RESET
;
2774 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2775 rst_level
= HNAE3_IMP_RESET
;
2776 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2777 rst_level
= HNAE3_FUNC_RESET
;
2779 /* now, clear all other resets */
2780 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2781 clear_bit(HNAE3_CORE_RESET
, addr
);
2782 clear_bit(HNAE3_IMP_RESET
, addr
);
2783 clear_bit(HNAE3_FUNC_RESET
, addr
);
2788 static void hclge_clear_reset_cause(struct hclge_dev
*hdev
)
2792 switch (hdev
->reset_type
) {
2793 case HNAE3_IMP_RESET
:
2794 clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2796 case HNAE3_GLOBAL_RESET
:
2797 clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2799 case HNAE3_CORE_RESET
:
2800 clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2803 dev_warn(&hdev
->pdev
->dev
, "Unsupported reset event to clear:%d",
2811 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, clearval
);
2812 hclge_enable_vector(&hdev
->misc_vector
, true);
2815 static void hclge_reset(struct hclge_dev
*hdev
)
2817 /* perform reset of the stack & ae device for a client */
2819 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2821 if (!hclge_reset_wait(hdev
)) {
2823 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2824 hclge_reset_ae_dev(hdev
->ae_dev
);
2825 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2828 hclge_clear_reset_cause(hdev
);
2830 /* schedule again to check pending resets later */
2831 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2832 hclge_reset_task_schedule(hdev
);
2835 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2838 static void hclge_reset_event(struct hnae3_handle
*handle
)
2840 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2841 struct hclge_dev
*hdev
= vport
->back
;
2843 /* check if this is a new reset request and we are not here just because
2844 * last reset attempt did not succeed and watchdog hit us again. We will
2845 * know this if last reset request did not occur very recently (watchdog
2846 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2847 * In case of new request we reset the "reset level" to PF reset.
2849 if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2850 handle
->reset_level
= HNAE3_FUNC_RESET
;
2852 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2853 handle
->reset_level
);
2855 /* request reset & schedule reset task */
2856 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2857 hclge_reset_task_schedule(hdev
);
2859 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2860 handle
->reset_level
++;
2862 handle
->last_reset_time
= jiffies
;
2865 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2867 /* check if there is any ongoing reset in the hardware. This status can
2868 * be checked from reset_pending. If there is then, we need to wait for
2869 * hardware to complete reset.
2870 * a. If we are able to figure out in reasonable time that hardware
2871 * has fully resetted then, we can proceed with driver, client
2873 * b. else, we can come back later to check this status so re-sched
2876 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2877 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2880 /* check if we got any *new* reset requests to be honored */
2881 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2882 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2883 hclge_do_reset(hdev
);
2885 hdev
->reset_type
= HNAE3_NONE_RESET
;
2888 static void hclge_reset_service_task(struct work_struct
*work
)
2890 struct hclge_dev
*hdev
=
2891 container_of(work
, struct hclge_dev
, rst_service_task
);
2893 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2896 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2898 hclge_reset_subtask(hdev
);
2900 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2903 static void hclge_mailbox_service_task(struct work_struct
*work
)
2905 struct hclge_dev
*hdev
=
2906 container_of(work
, struct hclge_dev
, mbx_service_task
);
2908 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2911 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2913 hclge_mbx_handler(hdev
);
2915 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2918 static void hclge_service_task(struct work_struct
*work
)
2920 struct hclge_dev
*hdev
=
2921 container_of(work
, struct hclge_dev
, service_task
);
2923 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2924 hclge_update_stats_for_all(hdev
);
2925 hdev
->hw_stats
.stats_timer
= 0;
2928 hclge_update_speed_duplex(hdev
);
2929 hclge_update_link_status(hdev
);
2930 hclge_service_complete(hdev
);
2933 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2935 /* VF handle has no client */
2936 if (!handle
->client
)
2937 return container_of(handle
, struct hclge_vport
, nic
);
2938 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2939 return container_of(handle
, struct hclge_vport
, roce
);
2941 return container_of(handle
, struct hclge_vport
, nic
);
2944 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2945 struct hnae3_vector_info
*vector_info
)
2947 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2948 struct hnae3_vector_info
*vector
= vector_info
;
2949 struct hclge_dev
*hdev
= vport
->back
;
2953 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2955 for (j
= 0; j
< vector_num
; j
++) {
2956 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2957 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2958 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2959 vector
->io_addr
= hdev
->hw
.io_base
+
2960 HCLGE_VECTOR_REG_BASE
+
2961 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2963 HCLGE_VECTOR_VF_OFFSET
;
2964 hdev
->vector_status
[i
] = vport
->vport_id
;
2965 hdev
->vector_irq
[i
] = vector
->vector
;
2974 hdev
->num_msi_left
-= alloc
;
2975 hdev
->num_msi_used
+= alloc
;
2980 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2984 for (i
= 0; i
< hdev
->num_msi
; i
++)
2985 if (vector
== hdev
->vector_irq
[i
])
2991 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
2993 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2994 struct hclge_dev
*hdev
= vport
->back
;
2997 vector_id
= hclge_get_vector_index(hdev
, vector
);
2998 if (vector_id
< 0) {
2999 dev_err(&hdev
->pdev
->dev
,
3000 "Get vector index fail. vector_id =%d\n", vector_id
);
3004 hclge_free_vector(hdev
, vector_id
);
3009 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
3011 return HCLGE_RSS_KEY_SIZE
;
3014 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
3016 return HCLGE_RSS_IND_TBL_SIZE
;
3019 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3020 const u8 hfunc
, const u8
*key
)
3022 struct hclge_rss_config_cmd
*req
;
3023 struct hclge_desc desc
;
3028 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3030 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3031 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3034 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3035 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3037 if (key_offset
== 2)
3039 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3041 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3043 memcpy(req
->hash_key
,
3044 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3046 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3048 dev_err(&hdev
->pdev
->dev
,
3049 "Configure RSS config fail, status = %d\n",
3057 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3059 struct hclge_rss_indirection_table_cmd
*req
;
3060 struct hclge_desc desc
;
3064 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3066 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3067 hclge_cmd_setup_basic_desc
3068 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3070 req
->start_table_index
=
3071 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3072 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3074 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3075 req
->rss_result
[j
] =
3076 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3078 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3080 dev_err(&hdev
->pdev
->dev
,
3081 "Configure rss indir table fail,status = %d\n",
3089 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3090 u16
*tc_size
, u16
*tc_offset
)
3092 struct hclge_rss_tc_mode_cmd
*req
;
3093 struct hclge_desc desc
;
3097 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3098 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3100 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3103 hnae3_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3104 hnae3_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3105 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3106 hnae3_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3107 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3109 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3112 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3114 dev_err(&hdev
->pdev
->dev
,
3115 "Configure rss tc mode fail, status = %d\n", ret
);
3120 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3122 struct hclge_rss_input_tuple_cmd
*req
;
3123 struct hclge_desc desc
;
3126 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3128 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3130 /* Get the tuple cfg from pf */
3131 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3132 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3133 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3134 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3135 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3136 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3137 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3138 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3139 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3141 dev_err(&hdev
->pdev
->dev
,
3142 "Configure rss input fail, status = %d\n", ret
);
3146 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3149 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3152 /* Get hash algorithm */
3154 *hfunc
= vport
->rss_algo
;
3156 /* Get the RSS Key required by the user */
3158 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3160 /* Get indirect table */
3162 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3163 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3168 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3169 const u8
*key
, const u8 hfunc
)
3171 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3172 struct hclge_dev
*hdev
= vport
->back
;
3176 /* Set the RSS Hash Key if specififed by the user */
3179 if (hfunc
== ETH_RSS_HASH_TOP
||
3180 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3181 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3184 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3188 /* Update the shadow RSS key with user specified qids */
3189 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3190 vport
->rss_algo
= hash_algo
;
3193 /* Update the shadow RSS table with user specified qids */
3194 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3195 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3197 /* Update the hardware */
3198 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3201 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3203 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3205 if (nfc
->data
& RXH_L4_B_2_3
)
3206 hash_sets
|= HCLGE_D_PORT_BIT
;
3208 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3210 if (nfc
->data
& RXH_IP_SRC
)
3211 hash_sets
|= HCLGE_S_IP_BIT
;
3213 hash_sets
&= ~HCLGE_S_IP_BIT
;
3215 if (nfc
->data
& RXH_IP_DST
)
3216 hash_sets
|= HCLGE_D_IP_BIT
;
3218 hash_sets
&= ~HCLGE_D_IP_BIT
;
3220 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3221 hash_sets
|= HCLGE_V_TAG_BIT
;
3226 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3227 struct ethtool_rxnfc
*nfc
)
3229 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3230 struct hclge_dev
*hdev
= vport
->back
;
3231 struct hclge_rss_input_tuple_cmd
*req
;
3232 struct hclge_desc desc
;
3236 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3237 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3240 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3241 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3243 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3244 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3245 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3246 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3247 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3248 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3249 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3250 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3252 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3253 switch (nfc
->flow_type
) {
3255 req
->ipv4_tcp_en
= tuple_sets
;
3258 req
->ipv6_tcp_en
= tuple_sets
;
3261 req
->ipv4_udp_en
= tuple_sets
;
3264 req
->ipv6_udp_en
= tuple_sets
;
3267 req
->ipv4_sctp_en
= tuple_sets
;
3270 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3271 (nfc
->data
& RXH_L4_B_2_3
))
3274 req
->ipv6_sctp_en
= tuple_sets
;
3277 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3280 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3286 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3288 dev_err(&hdev
->pdev
->dev
,
3289 "Set rss tuple fail, status = %d\n", ret
);
3293 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3294 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3295 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3296 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3297 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3298 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3299 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3300 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3304 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3305 struct ethtool_rxnfc
*nfc
)
3307 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3312 switch (nfc
->flow_type
) {
3314 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3317 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3320 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3323 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3326 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3329 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3333 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3342 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3343 nfc
->data
|= RXH_L4_B_2_3
;
3344 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3345 nfc
->data
|= RXH_L4_B_0_1
;
3346 if (tuple_sets
& HCLGE_D_IP_BIT
)
3347 nfc
->data
|= RXH_IP_DST
;
3348 if (tuple_sets
& HCLGE_S_IP_BIT
)
3349 nfc
->data
|= RXH_IP_SRC
;
3354 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3356 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3357 struct hclge_dev
*hdev
= vport
->back
;
3359 return hdev
->rss_size_max
;
3362 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3364 struct hclge_vport
*vport
= hdev
->vport
;
3365 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3366 u16 rss_size
= vport
[0].alloc_rss_size
;
3367 u8
*key
= vport
[0].rss_hash_key
;
3368 u8 hfunc
= vport
[0].rss_algo
;
3369 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3370 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3371 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3375 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3379 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3383 ret
= hclge_set_rss_input_tuple(hdev
);
3387 /* Each TC have the same queue size, and tc_size set to hardware is
3388 * the log2 of roundup power of two of rss_size, the acutal queue
3389 * size is limited by indirection table.
3391 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3392 dev_err(&hdev
->pdev
->dev
,
3393 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3398 roundup_size
= roundup_pow_of_two(rss_size
);
3399 roundup_size
= ilog2(roundup_size
);
3401 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3404 if (!(hdev
->hw_tc_map
& BIT(i
)))
3408 tc_size
[i
] = roundup_size
;
3409 tc_offset
[i
] = rss_size
* i
;
3412 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3415 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3417 struct hclge_vport
*vport
= hdev
->vport
;
3420 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3421 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3422 vport
[j
].rss_indirection_tbl
[i
] =
3423 i
% vport
[j
].alloc_rss_size
;
3427 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3429 struct hclge_vport
*vport
= hdev
->vport
;
3432 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3433 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3434 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3435 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3436 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3437 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3438 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3439 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3440 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3441 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3442 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3443 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3444 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3445 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3446 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3447 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3448 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3450 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3452 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3455 hclge_rss_indir_init_cfg(hdev
);
3458 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3459 int vector_id
, bool en
,
3460 struct hnae3_ring_chain_node
*ring_chain
)
3462 struct hclge_dev
*hdev
= vport
->back
;
3463 struct hnae3_ring_chain_node
*node
;
3464 struct hclge_desc desc
;
3465 struct hclge_ctrl_vector_chain_cmd
*req
3466 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3467 enum hclge_cmd_status status
;
3468 enum hclge_opcode_type op
;
3469 u16 tqp_type_and_id
;
3472 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3473 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3474 req
->int_vector_id
= vector_id
;
3477 for (node
= ring_chain
; node
; node
= node
->next
) {
3478 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3479 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3481 hnae3_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3482 hnae3_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3483 HCLGE_TQP_ID_S
, node
->tqp_index
);
3484 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3486 hnae3_get_field(node
->int_gl_idx
,
3487 HNAE3_RING_GL_IDX_M
,
3488 HNAE3_RING_GL_IDX_S
));
3489 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3490 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3491 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3492 req
->vfid
= vport
->vport_id
;
3494 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3496 dev_err(&hdev
->pdev
->dev
,
3497 "Map TQP fail, status is %d.\n",
3503 hclge_cmd_setup_basic_desc(&desc
,
3506 req
->int_vector_id
= vector_id
;
3511 req
->int_cause_num
= i
;
3512 req
->vfid
= vport
->vport_id
;
3513 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3515 dev_err(&hdev
->pdev
->dev
,
3516 "Map TQP fail, status is %d.\n", status
);
3524 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3526 struct hnae3_ring_chain_node
*ring_chain
)
3528 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3529 struct hclge_dev
*hdev
= vport
->back
;
3532 vector_id
= hclge_get_vector_index(hdev
, vector
);
3533 if (vector_id
< 0) {
3534 dev_err(&hdev
->pdev
->dev
,
3535 "Get vector index fail. vector_id =%d\n", vector_id
);
3539 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3542 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3544 struct hnae3_ring_chain_node
*ring_chain
)
3546 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3547 struct hclge_dev
*hdev
= vport
->back
;
3550 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3553 vector_id
= hclge_get_vector_index(hdev
, vector
);
3554 if (vector_id
< 0) {
3555 dev_err(&handle
->pdev
->dev
,
3556 "Get vector index fail. ret =%d\n", vector_id
);
3560 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3562 dev_err(&handle
->pdev
->dev
,
3563 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3570 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3571 struct hclge_promisc_param
*param
)
3573 struct hclge_promisc_cfg_cmd
*req
;
3574 struct hclge_desc desc
;
3577 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3579 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3580 req
->vf_id
= param
->vf_id
;
3582 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3583 * pdev revision(0x20), new revision support them. The
3584 * value of this two fields will not return error when driver
3585 * send command to fireware in revision(0x20).
3587 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
) |
3588 HCLGE_PROMISC_TX_EN_B
| HCLGE_PROMISC_RX_EN_B
;
3590 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3592 dev_err(&hdev
->pdev
->dev
,
3593 "Set promisc mode fail, status is %d.\n", ret
);
3598 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3599 bool en_mc
, bool en_bc
, int vport_id
)
3604 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3606 param
->enable
= HCLGE_PROMISC_EN_UC
;
3608 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3610 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3611 param
->vf_id
= vport_id
;
3614 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, bool en_uc_pmc
,
3617 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3618 struct hclge_dev
*hdev
= vport
->back
;
3619 struct hclge_promisc_param param
;
3621 hclge_promisc_param_init(¶m
, en_uc_pmc
, en_mc_pmc
, true,
3623 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3626 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3628 struct hclge_desc desc
;
3629 struct hclge_config_mac_mode_cmd
*req
=
3630 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3634 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3635 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3636 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3637 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3638 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3639 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3640 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3641 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3642 hnae3_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3643 hnae3_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3644 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3645 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3646 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3647 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3648 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3649 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3651 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3653 dev_err(&hdev
->pdev
->dev
,
3654 "mac enable fail, ret =%d.\n", ret
);
3657 static int hclge_set_mac_loopback(struct hclge_dev
*hdev
, bool en
)
3659 struct hclge_config_mac_mode_cmd
*req
;
3660 struct hclge_desc desc
;
3664 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3665 /* 1 Read out the MAC mode config at first */
3666 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, true);
3667 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3669 dev_err(&hdev
->pdev
->dev
,
3670 "mac loopback get fail, ret =%d.\n", ret
);
3674 /* 2 Then setup the loopback flag */
3675 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3676 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, en
? 1 : 0);
3678 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3680 /* 3 Config mac work mode with loopback flag
3681 * and its original configure parameters
3683 hclge_cmd_reuse_desc(&desc
, false);
3684 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3686 dev_err(&hdev
->pdev
->dev
,
3687 "mac loopback set fail, ret =%d.\n", ret
);
3691 static int hclge_set_serdes_loopback(struct hclge_dev
*hdev
, bool en
)
3693 #define HCLGE_SERDES_RETRY_MS 10
3694 #define HCLGE_SERDES_RETRY_NUM 100
3695 struct hclge_serdes_lb_cmd
*req
;
3696 struct hclge_desc desc
;
3699 req
= (struct hclge_serdes_lb_cmd
*)&desc
.data
[0];
3700 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SERDES_LOOPBACK
, false);
3703 req
->enable
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3704 req
->mask
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3706 req
->mask
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3709 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3711 dev_err(&hdev
->pdev
->dev
,
3712 "serdes loopback set fail, ret = %d\n", ret
);
3717 msleep(HCLGE_SERDES_RETRY_MS
);
3718 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SERDES_LOOPBACK
,
3720 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3722 dev_err(&hdev
->pdev
->dev
,
3723 "serdes loopback get, ret = %d\n", ret
);
3726 } while (++i
< HCLGE_SERDES_RETRY_NUM
&&
3727 !(req
->result
& HCLGE_CMD_SERDES_DONE_B
));
3729 if (!(req
->result
& HCLGE_CMD_SERDES_DONE_B
)) {
3730 dev_err(&hdev
->pdev
->dev
, "serdes loopback set timeout\n");
3732 } else if (!(req
->result
& HCLGE_CMD_SERDES_SUCCESS_B
)) {
3733 dev_err(&hdev
->pdev
->dev
, "serdes loopback set failed in fw\n");
3740 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3741 enum hnae3_loop loop_mode
, bool en
)
3743 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3744 struct hclge_dev
*hdev
= vport
->back
;
3747 switch (loop_mode
) {
3748 case HNAE3_MAC_INTER_LOOP_MAC
:
3749 ret
= hclge_set_mac_loopback(hdev
, en
);
3751 case HNAE3_MAC_INTER_LOOP_SERDES
:
3752 ret
= hclge_set_serdes_loopback(hdev
, en
);
3756 dev_err(&hdev
->pdev
->dev
,
3757 "loop_mode %d is not supported\n", loop_mode
);
3764 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3765 int stream_id
, bool enable
)
3767 struct hclge_desc desc
;
3768 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3769 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3772 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3773 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3774 req
->stream_id
= cpu_to_le16(stream_id
);
3775 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3777 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3779 dev_err(&hdev
->pdev
->dev
,
3780 "Tqp enable fail, status =%d.\n", ret
);
3784 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3786 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3787 struct hnae3_queue
*queue
;
3788 struct hclge_tqp
*tqp
;
3791 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3792 queue
= handle
->kinfo
.tqp
[i
];
3793 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3794 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3798 static int hclge_ae_start(struct hnae3_handle
*handle
)
3800 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3801 struct hclge_dev
*hdev
= vport
->back
;
3804 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3805 hclge_tqp_enable(hdev
, i
, 0, true);
3808 hclge_cfg_mac_mode(hdev
, true);
3809 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3810 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3811 hdev
->hw
.mac
.link
= 0;
3813 /* reset tqp stats */
3814 hclge_reset_tqp_stats(handle
);
3816 ret
= hclge_mac_start_phy(hdev
);
3823 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3825 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3826 struct hclge_dev
*hdev
= vport
->back
;
3829 del_timer_sync(&hdev
->service_timer
);
3830 cancel_work_sync(&hdev
->service_task
);
3831 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
3833 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
3834 hclge_mac_stop_phy(hdev
);
3838 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3839 hclge_tqp_enable(hdev
, i
, 0, false);
3842 hclge_cfg_mac_mode(hdev
, false);
3844 hclge_mac_stop_phy(hdev
);
3846 /* reset tqp stats */
3847 hclge_reset_tqp_stats(handle
);
3848 del_timer_sync(&hdev
->service_timer
);
3849 cancel_work_sync(&hdev
->service_task
);
3850 hclge_update_link_status(hdev
);
3853 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3854 u16 cmdq_resp
, u8 resp_code
,
3855 enum hclge_mac_vlan_tbl_opcode op
)
3857 struct hclge_dev
*hdev
= vport
->back
;
3858 int return_status
= -EIO
;
3861 dev_err(&hdev
->pdev
->dev
,
3862 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3867 if (op
== HCLGE_MAC_VLAN_ADD
) {
3868 if ((!resp_code
) || (resp_code
== 1)) {
3870 } else if (resp_code
== 2) {
3871 return_status
= -ENOSPC
;
3872 dev_err(&hdev
->pdev
->dev
,
3873 "add mac addr failed for uc_overflow.\n");
3874 } else if (resp_code
== 3) {
3875 return_status
= -ENOSPC
;
3876 dev_err(&hdev
->pdev
->dev
,
3877 "add mac addr failed for mc_overflow.\n");
3879 dev_err(&hdev
->pdev
->dev
,
3880 "add mac addr failed for undefined, code=%d.\n",
3883 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3886 } else if (resp_code
== 1) {
3887 return_status
= -ENOENT
;
3888 dev_dbg(&hdev
->pdev
->dev
,
3889 "remove mac addr failed for miss.\n");
3891 dev_err(&hdev
->pdev
->dev
,
3892 "remove mac addr failed for undefined, code=%d.\n",
3895 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3898 } else if (resp_code
== 1) {
3899 return_status
= -ENOENT
;
3900 dev_dbg(&hdev
->pdev
->dev
,
3901 "lookup mac addr failed for miss.\n");
3903 dev_err(&hdev
->pdev
->dev
,
3904 "lookup mac addr failed for undefined, code=%d.\n",
3908 return_status
= -EINVAL
;
3909 dev_err(&hdev
->pdev
->dev
,
3910 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3914 return return_status
;
3917 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3922 if (vfid
> 255 || vfid
< 0)
3925 if (vfid
>= 0 && vfid
<= 191) {
3926 word_num
= vfid
/ 32;
3927 bit_num
= vfid
% 32;
3929 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3931 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3933 word_num
= (vfid
- 192) / 32;
3934 bit_num
= vfid
% 32;
3936 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3938 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3944 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3946 #define HCLGE_DESC_NUMBER 3
3947 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3950 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3951 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3952 if (desc
[i
].data
[j
])
3958 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3961 const unsigned char *mac_addr
= addr
;
3962 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3963 (mac_addr
[0]) | (mac_addr
[1] << 8);
3964 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3966 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3967 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3970 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3973 u16 high_val
= addr
[1] | (addr
[0] << 8);
3974 struct hclge_dev
*hdev
= vport
->back
;
3975 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3976 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3981 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3982 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3985 struct hclge_mta_filter_mode_cmd
*req
;
3986 struct hclge_desc desc
;
3989 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3990 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3992 hnae3_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3994 hnae3_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3995 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3997 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3999 dev_err(&hdev
->pdev
->dev
,
4000 "Config mat filter mode failed for cmd_send, ret =%d.\n",
4006 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
4010 struct hclge_cfg_func_mta_filter_cmd
*req
;
4011 struct hclge_desc desc
;
4014 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
4015 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
4017 hnae3_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
4019 req
->function_id
= func_id
;
4021 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4023 dev_err(&hdev
->pdev
->dev
,
4024 "Config func_id enable failed for cmd_send, ret =%d.\n",
4030 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
4034 struct hclge_dev
*hdev
= vport
->back
;
4035 struct hclge_cfg_func_mta_item_cmd
*req
;
4036 struct hclge_desc desc
;
4040 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
4041 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
4042 hnae3_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
4044 hnae3_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
4045 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
4046 req
->item_idx
= cpu_to_le16(item_idx
);
4048 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4050 dev_err(&hdev
->pdev
->dev
,
4051 "Config mta table item failed for cmd_send, ret =%d.\n",
4057 set_bit(idx
, vport
->mta_shadow
);
4059 clear_bit(idx
, vport
->mta_shadow
);
4064 static int hclge_update_mta_status(struct hnae3_handle
*handle
)
4066 unsigned long mta_status
[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE
)];
4067 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4068 struct net_device
*netdev
= handle
->kinfo
.netdev
;
4069 struct netdev_hw_addr
*ha
;
4072 memset(mta_status
, 0, sizeof(mta_status
));
4074 /* update mta_status from mc addr list */
4075 netdev_for_each_mc_addr(ha
, netdev
) {
4076 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, ha
->addr
);
4077 set_bit(tbl_idx
, mta_status
);
4080 return hclge_update_mta_status_common(vport
, mta_status
,
4081 0, HCLGE_MTA_TBL_SIZE
, true);
4084 int hclge_update_mta_status_common(struct hclge_vport
*vport
,
4085 unsigned long *status
,
4090 struct hclge_dev
*hdev
= vport
->back
;
4091 u16 update_max
= idx
+ count
;
4097 /* setup mta check range */
4098 if (update_filter
) {
4100 check_max
= HCLGE_MTA_TBL_SIZE
;
4103 check_max
= update_max
;
4107 /* check and update all mta item */
4108 for (; i
< check_max
; i
++) {
4109 /* ignore unused item */
4110 if (!test_bit(i
, vport
->mta_shadow
))
4113 /* if i in update range then update it */
4114 if (i
>= idx
&& i
< update_max
)
4115 if (!test_bit(i
- idx
, status
))
4116 hclge_set_mta_table_item(vport
, i
, false);
4118 if (!used
&& test_bit(i
, vport
->mta_shadow
))
4122 /* no longer use mta, disable it */
4123 if (vport
->accept_mta_mc
&& update_filter
&& !used
) {
4124 ret
= hclge_cfg_func_mta_filter(hdev
,
4128 dev_err(&hdev
->pdev
->dev
,
4129 "disable func mta filter fail ret=%d\n",
4132 vport
->accept_mta_mc
= false;
4138 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4139 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4141 struct hclge_dev
*hdev
= vport
->back
;
4142 struct hclge_desc desc
;
4147 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4149 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4151 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4153 dev_err(&hdev
->pdev
->dev
,
4154 "del mac addr failed for cmd_send, ret =%d.\n",
4158 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4159 retval
= le16_to_cpu(desc
.retval
);
4161 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4162 HCLGE_MAC_VLAN_REMOVE
);
4165 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4166 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4167 struct hclge_desc
*desc
,
4170 struct hclge_dev
*hdev
= vport
->back
;
4175 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4177 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4178 memcpy(desc
[0].data
,
4180 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4181 hclge_cmd_setup_basic_desc(&desc
[1],
4182 HCLGE_OPC_MAC_VLAN_ADD
,
4184 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4185 hclge_cmd_setup_basic_desc(&desc
[2],
4186 HCLGE_OPC_MAC_VLAN_ADD
,
4188 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4190 memcpy(desc
[0].data
,
4192 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4193 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4196 dev_err(&hdev
->pdev
->dev
,
4197 "lookup mac addr failed for cmd_send, ret =%d.\n",
4201 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4202 retval
= le16_to_cpu(desc
[0].retval
);
4204 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4205 HCLGE_MAC_VLAN_LKUP
);
4208 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4209 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4210 struct hclge_desc
*mc_desc
)
4212 struct hclge_dev
*hdev
= vport
->back
;
4219 struct hclge_desc desc
;
4221 hclge_cmd_setup_basic_desc(&desc
,
4222 HCLGE_OPC_MAC_VLAN_ADD
,
4224 memcpy(desc
.data
, req
,
4225 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4226 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4227 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4228 retval
= le16_to_cpu(desc
.retval
);
4230 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4232 HCLGE_MAC_VLAN_ADD
);
4234 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4235 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4236 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4237 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4238 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4239 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4240 memcpy(mc_desc
[0].data
, req
,
4241 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4242 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4243 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4244 retval
= le16_to_cpu(mc_desc
[0].retval
);
4246 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4248 HCLGE_MAC_VLAN_ADD
);
4252 dev_err(&hdev
->pdev
->dev
,
4253 "add mac addr failed for cmd_send, ret =%d.\n",
4261 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4262 const unsigned char *addr
)
4264 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4266 return hclge_add_uc_addr_common(vport
, addr
);
4269 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4270 const unsigned char *addr
)
4272 struct hclge_dev
*hdev
= vport
->back
;
4273 struct hclge_mac_vlan_tbl_entry_cmd req
;
4274 struct hclge_desc desc
;
4275 u16 egress_port
= 0;
4278 /* mac addr check */
4279 if (is_zero_ether_addr(addr
) ||
4280 is_broadcast_ether_addr(addr
) ||
4281 is_multicast_ether_addr(addr
)) {
4282 dev_err(&hdev
->pdev
->dev
,
4283 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4285 is_zero_ether_addr(addr
),
4286 is_broadcast_ether_addr(addr
),
4287 is_multicast_ether_addr(addr
));
4291 memset(&req
, 0, sizeof(req
));
4292 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4294 hnae3_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4295 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4297 req
.egress_port
= cpu_to_le16(egress_port
);
4299 hclge_prepare_mac_addr(&req
, addr
);
4301 /* Lookup the mac address in the mac_vlan table, and add
4302 * it if the entry is inexistent. Repeated unicast entry
4303 * is not allowed in the mac vlan table.
4305 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4307 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4309 /* check if we just hit the duplicate */
4313 dev_err(&hdev
->pdev
->dev
,
4314 "PF failed to add unicast entry(%pM) in the MAC table\n",
4320 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4321 const unsigned char *addr
)
4323 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4325 return hclge_rm_uc_addr_common(vport
, addr
);
4328 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4329 const unsigned char *addr
)
4331 struct hclge_dev
*hdev
= vport
->back
;
4332 struct hclge_mac_vlan_tbl_entry_cmd req
;
4335 /* mac addr check */
4336 if (is_zero_ether_addr(addr
) ||
4337 is_broadcast_ether_addr(addr
) ||
4338 is_multicast_ether_addr(addr
)) {
4339 dev_dbg(&hdev
->pdev
->dev
,
4340 "Remove mac err! invalid mac:%pM.\n",
4345 memset(&req
, 0, sizeof(req
));
4346 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4347 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4348 hclge_prepare_mac_addr(&req
, addr
);
4349 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4354 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4355 const unsigned char *addr
)
4357 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4359 return hclge_add_mc_addr_common(vport
, addr
);
4362 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4363 const unsigned char *addr
)
4365 struct hclge_dev
*hdev
= vport
->back
;
4366 struct hclge_mac_vlan_tbl_entry_cmd req
;
4367 struct hclge_desc desc
[3];
4371 /* mac addr check */
4372 if (!is_multicast_ether_addr(addr
)) {
4373 dev_err(&hdev
->pdev
->dev
,
4374 "Add mc mac err! invalid mac:%pM.\n",
4378 memset(&req
, 0, sizeof(req
));
4379 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4380 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4381 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4382 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4383 hclge_prepare_mac_addr(&req
, addr
);
4384 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4386 /* This mac addr exist, update VFID for it */
4387 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4388 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4390 /* This mac addr do not exist, add new entry for it */
4391 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4392 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4393 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4394 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4395 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4398 /* If mc mac vlan table is full, use MTA table */
4399 if (status
== -ENOSPC
) {
4400 if (!vport
->accept_mta_mc
) {
4401 status
= hclge_cfg_func_mta_filter(hdev
,
4405 dev_err(&hdev
->pdev
->dev
,
4406 "set mta filter mode fail ret=%d\n",
4410 vport
->accept_mta_mc
= true;
4413 /* Set MTA table for this MAC address */
4414 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4415 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4421 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4422 const unsigned char *addr
)
4424 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4426 return hclge_rm_mc_addr_common(vport
, addr
);
4429 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4430 const unsigned char *addr
)
4432 struct hclge_dev
*hdev
= vport
->back
;
4433 struct hclge_mac_vlan_tbl_entry_cmd req
;
4434 enum hclge_cmd_status status
;
4435 struct hclge_desc desc
[3];
4437 /* mac addr check */
4438 if (!is_multicast_ether_addr(addr
)) {
4439 dev_dbg(&hdev
->pdev
->dev
,
4440 "Remove mc mac err! invalid mac:%pM.\n",
4445 memset(&req
, 0, sizeof(req
));
4446 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4447 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4448 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4449 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4450 hclge_prepare_mac_addr(&req
, addr
);
4451 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4453 /* This mac addr exist, remove this handle's VFID for it */
4454 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4456 if (hclge_is_all_function_id_zero(desc
))
4457 /* All the vfid is zero, so need to delete this entry */
4458 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4460 /* Not all the vfid is zero, update the vfid */
4461 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4464 /* Maybe this mac address is in mta table, but it cannot be
4465 * deleted here because an entry of mta represents an address
4466 * range rather than a specific address. the delete action to
4467 * all entries will take effect in update_mta_status called by
4468 * hns3_nic_set_rx_mode.
4476 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4477 u16 cmdq_resp
, u8 resp_code
)
4479 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4480 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4481 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4482 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4487 dev_err(&hdev
->pdev
->dev
,
4488 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4493 switch (resp_code
) {
4494 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4495 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4498 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4499 dev_err(&hdev
->pdev
->dev
,
4500 "add mac ethertype failed for manager table overflow.\n");
4501 return_status
= -EIO
;
4503 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4504 dev_err(&hdev
->pdev
->dev
,
4505 "add mac ethertype failed for key conflict.\n");
4506 return_status
= -EIO
;
4509 dev_err(&hdev
->pdev
->dev
,
4510 "add mac ethertype failed for undefined, code=%d.\n",
4512 return_status
= -EIO
;
4515 return return_status
;
4518 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4519 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4521 struct hclge_desc desc
;
4526 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4527 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4529 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4531 dev_err(&hdev
->pdev
->dev
,
4532 "add mac ethertype failed for cmd_send, ret =%d.\n",
4537 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4538 retval
= le16_to_cpu(desc
.retval
);
4540 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4543 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4548 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4549 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4551 dev_err(&hdev
->pdev
->dev
,
4552 "add mac ethertype failed, ret =%d.\n",
4561 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4563 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4564 struct hclge_dev
*hdev
= vport
->back
;
4566 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4569 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4572 const unsigned char *new_addr
= (const unsigned char *)p
;
4573 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4574 struct hclge_dev
*hdev
= vport
->back
;
4577 /* mac addr check */
4578 if (is_zero_ether_addr(new_addr
) ||
4579 is_broadcast_ether_addr(new_addr
) ||
4580 is_multicast_ether_addr(new_addr
)) {
4581 dev_err(&hdev
->pdev
->dev
,
4582 "Change uc mac err! invalid mac:%p.\n",
4587 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4588 dev_warn(&hdev
->pdev
->dev
,
4589 "remove old uc mac address fail.\n");
4591 ret
= hclge_add_uc_addr(handle
, new_addr
);
4593 dev_err(&hdev
->pdev
->dev
,
4594 "add uc mac address fail, ret =%d.\n",
4598 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4599 dev_err(&hdev
->pdev
->dev
,
4600 "restore uc mac address fail.\n");
4605 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4607 dev_err(&hdev
->pdev
->dev
,
4608 "configure mac pause address fail, ret =%d.\n",
4613 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4618 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4621 struct hclge_vlan_filter_ctrl_cmd
*req
;
4622 struct hclge_desc desc
;
4625 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4627 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4628 req
->vlan_type
= vlan_type
;
4629 req
->vlan_fe
= filter_en
;
4631 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4633 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4639 #define HCLGE_FILTER_TYPE_VF 0
4640 #define HCLGE_FILTER_TYPE_PORT 1
4642 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4644 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4645 struct hclge_dev
*hdev
= vport
->back
;
4647 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4650 static int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4651 bool is_kill
, u16 vlan
, u8 qos
,
4654 #define HCLGE_MAX_VF_BYTES 16
4655 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4656 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4657 struct hclge_desc desc
[2];
4662 hclge_cmd_setup_basic_desc(&desc
[0],
4663 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4664 hclge_cmd_setup_basic_desc(&desc
[1],
4665 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4667 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4669 vf_byte_off
= vfid
/ 8;
4670 vf_byte_val
= 1 << (vfid
% 8);
4672 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4673 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4675 req0
->vlan_id
= cpu_to_le16(vlan
);
4676 req0
->vlan_cfg
= is_kill
;
4678 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4679 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4681 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4683 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4685 dev_err(&hdev
->pdev
->dev
,
4686 "Send vf vlan command fail, ret =%d.\n",
4692 #define HCLGE_VF_VLAN_NO_ENTRY 2
4693 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4696 if (req0
->resp_code
== HCLGE_VF_VLAN_NO_ENTRY
) {
4697 dev_warn(&hdev
->pdev
->dev
,
4698 "vf vlan table is full, vf vlan filter is disabled\n");
4702 dev_err(&hdev
->pdev
->dev
,
4703 "Add vf vlan filter fail, ret =%d.\n",
4706 if (!req0
->resp_code
)
4709 dev_err(&hdev
->pdev
->dev
,
4710 "Kill vf vlan filter fail, ret =%d.\n",
4717 static int hclge_set_port_vlan_filter(struct hclge_dev
*hdev
, __be16 proto
,
4718 u16 vlan_id
, bool is_kill
)
4720 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4721 struct hclge_desc desc
;
4722 u8 vlan_offset_byte_val
;
4723 u8 vlan_offset_byte
;
4727 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4729 vlan_offset_160
= vlan_id
/ 160;
4730 vlan_offset_byte
= (vlan_id
% 160) / 8;
4731 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4733 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4734 req
->vlan_offset
= vlan_offset_160
;
4735 req
->vlan_cfg
= is_kill
;
4736 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4738 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4740 dev_err(&hdev
->pdev
->dev
,
4741 "port vlan command, send fail, ret =%d.\n", ret
);
4745 static int hclge_set_vlan_filter_hw(struct hclge_dev
*hdev
, __be16 proto
,
4746 u16 vport_id
, u16 vlan_id
, u8 qos
,
4749 u16 vport_idx
, vport_num
= 0;
4752 ret
= hclge_set_vf_vlan_common(hdev
, vport_id
, is_kill
, vlan_id
,
4755 dev_err(&hdev
->pdev
->dev
,
4756 "Set %d vport vlan filter config fail, ret =%d.\n",
4761 /* vlan 0 may be added twice when 8021q module is enabled */
4762 if (!is_kill
&& !vlan_id
&&
4763 test_bit(vport_id
, hdev
->vlan_table
[vlan_id
]))
4766 if (!is_kill
&& test_and_set_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4767 dev_err(&hdev
->pdev
->dev
,
4768 "Add port vlan failed, vport %d is already in vlan %d\n",
4774 !test_and_clear_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4775 dev_err(&hdev
->pdev
->dev
,
4776 "Delete port vlan failed, vport %d is not in vlan %d\n",
4781 for_each_set_bit(vport_idx
, hdev
->vlan_table
[vlan_id
], VLAN_N_VID
)
4784 if ((is_kill
&& vport_num
== 0) || (!is_kill
&& vport_num
== 1))
4785 ret
= hclge_set_port_vlan_filter(hdev
, proto
, vlan_id
,
4791 int hclge_set_vlan_filter(struct hnae3_handle
*handle
, __be16 proto
,
4792 u16 vlan_id
, bool is_kill
)
4794 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4795 struct hclge_dev
*hdev
= vport
->back
;
4797 return hclge_set_vlan_filter_hw(hdev
, proto
, vport
->vport_id
, vlan_id
,
4801 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4802 u16 vlan
, u8 qos
, __be16 proto
)
4804 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4805 struct hclge_dev
*hdev
= vport
->back
;
4807 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4809 if (proto
!= htons(ETH_P_8021Q
))
4810 return -EPROTONOSUPPORT
;
4812 return hclge_set_vlan_filter_hw(hdev
, proto
, vfid
, vlan
, qos
, false);
4815 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4817 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4818 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4819 struct hclge_dev
*hdev
= vport
->back
;
4820 struct hclge_desc desc
;
4823 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4825 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4826 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4827 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4828 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG1_B
,
4829 vcfg
->accept_tag1
? 1 : 0);
4830 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG1_B
,
4831 vcfg
->accept_untag1
? 1 : 0);
4832 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG2_B
,
4833 vcfg
->accept_tag2
? 1 : 0);
4834 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG2_B
,
4835 vcfg
->accept_untag2
? 1 : 0);
4836 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4837 vcfg
->insert_tag1_en
? 1 : 0);
4838 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4839 vcfg
->insert_tag2_en
? 1 : 0);
4840 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4842 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4843 req
->vf_bitmap
[req
->vf_offset
] =
4844 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4846 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4848 dev_err(&hdev
->pdev
->dev
,
4849 "Send port txvlan cfg command fail, ret =%d\n",
4855 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4857 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4858 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4859 struct hclge_dev
*hdev
= vport
->back
;
4860 struct hclge_desc desc
;
4863 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4865 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4866 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4867 vcfg
->strip_tag1_en
? 1 : 0);
4868 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4869 vcfg
->strip_tag2_en
? 1 : 0);
4870 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4871 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4872 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4873 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4875 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4876 req
->vf_bitmap
[req
->vf_offset
] =
4877 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4879 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4881 dev_err(&hdev
->pdev
->dev
,
4882 "Send port rxvlan cfg command fail, ret =%d\n",
4888 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4890 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4891 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4892 struct hclge_desc desc
;
4895 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4896 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4897 rx_req
->ot_fst_vlan_type
=
4898 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4899 rx_req
->ot_sec_vlan_type
=
4900 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4901 rx_req
->in_fst_vlan_type
=
4902 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4903 rx_req
->in_sec_vlan_type
=
4904 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4906 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4908 dev_err(&hdev
->pdev
->dev
,
4909 "Send rxvlan protocol type command fail, ret =%d\n",
4914 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4916 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4917 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4918 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4920 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4922 dev_err(&hdev
->pdev
->dev
,
4923 "Send txvlan protocol type command fail, ret =%d\n",
4929 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4931 #define HCLGE_DEF_VLAN_TYPE 0x8100
4933 struct hnae3_handle
*handle
;
4934 struct hclge_vport
*vport
;
4938 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4942 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4946 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4947 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4948 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4949 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4950 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4951 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4953 ret
= hclge_set_vlan_protocol_type(hdev
);
4957 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4958 vport
= &hdev
->vport
[i
];
4959 vport
->txvlan_cfg
.accept_tag1
= true;
4960 vport
->txvlan_cfg
.accept_untag1
= true;
4962 /* accept_tag2 and accept_untag2 are not supported on
4963 * pdev revision(0x20), new revision support them. The
4964 * value of this two fields will not return error when driver
4965 * send command to fireware in revision(0x20).
4966 * This two fields can not configured by user.
4968 vport
->txvlan_cfg
.accept_tag2
= true;
4969 vport
->txvlan_cfg
.accept_untag2
= true;
4971 vport
->txvlan_cfg
.insert_tag1_en
= false;
4972 vport
->txvlan_cfg
.insert_tag2_en
= false;
4973 vport
->txvlan_cfg
.default_tag1
= 0;
4974 vport
->txvlan_cfg
.default_tag2
= 0;
4976 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4980 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4981 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4982 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4983 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4985 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4990 handle
= &hdev
->vport
[0].nic
;
4991 return hclge_set_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4994 int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4996 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4998 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4999 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
5000 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
5001 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
5003 return hclge_set_vlan_rx_offload_cfg(vport
);
5006 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
5008 struct hclge_config_max_frm_size_cmd
*req
;
5009 struct hclge_desc desc
;
5013 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
5015 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
5016 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
5019 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
5021 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
5023 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
5024 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
5026 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5028 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
5030 hdev
->mps
= max_frm_size
;
5035 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
5037 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5038 struct hclge_dev
*hdev
= vport
->back
;
5041 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
5043 dev_err(&hdev
->pdev
->dev
,
5044 "Change mtu fail, ret =%d\n", ret
);
5048 ret
= hclge_buffer_alloc(hdev
);
5050 dev_err(&hdev
->pdev
->dev
,
5051 "Allocate buffer fail, ret =%d\n", ret
);
5056 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
5059 struct hclge_reset_tqp_queue_cmd
*req
;
5060 struct hclge_desc desc
;
5063 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
5065 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5066 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5067 hnae3_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
5069 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5071 dev_err(&hdev
->pdev
->dev
,
5072 "Send tqp reset cmd error, status =%d\n", ret
);
5079 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
5081 struct hclge_reset_tqp_queue_cmd
*req
;
5082 struct hclge_desc desc
;
5085 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
5087 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5088 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5090 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5092 dev_err(&hdev
->pdev
->dev
,
5093 "Get reset status error, status =%d\n", ret
);
5097 return hnae3_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
5100 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
5103 struct hnae3_queue
*queue
;
5104 struct hclge_tqp
*tqp
;
5106 queue
= handle
->kinfo
.tqp
[queue_id
];
5107 tqp
= container_of(queue
, struct hclge_tqp
, q
);
5112 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
5114 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5115 struct hclge_dev
*hdev
= vport
->back
;
5116 int reset_try_times
= 0;
5121 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
5124 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
5126 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
5128 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
5132 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5134 dev_warn(&hdev
->pdev
->dev
,
5135 "Send reset tqp cmd fail, ret = %d\n", ret
);
5139 reset_try_times
= 0;
5140 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5141 /* Wait for tqp hw reset */
5143 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5148 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5149 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5153 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5155 dev_warn(&hdev
->pdev
->dev
,
5156 "Deassert the soft reset fail, ret = %d\n", ret
);
5161 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
5163 struct hclge_dev
*hdev
= vport
->back
;
5164 int reset_try_times
= 0;
5169 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5171 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5173 dev_warn(&hdev
->pdev
->dev
,
5174 "Send reset tqp cmd fail, ret = %d\n", ret
);
5178 reset_try_times
= 0;
5179 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5180 /* Wait for tqp hw reset */
5182 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5187 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5188 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5192 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5194 dev_warn(&hdev
->pdev
->dev
,
5195 "Deassert the soft reset fail, ret = %d\n", ret
);
5198 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5200 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5201 struct hclge_dev
*hdev
= vport
->back
;
5203 return hdev
->fw_version
;
5206 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5209 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5210 struct hclge_dev
*hdev
= vport
->back
;
5211 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5216 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5217 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5220 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5222 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5227 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5230 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5233 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5236 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5241 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5242 else if (rx_en
&& !tx_en
)
5243 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5244 else if (!rx_en
&& tx_en
)
5245 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5247 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5249 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5252 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5254 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5259 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5264 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5266 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5267 u16 remote_advertising
= 0;
5268 u16 local_advertising
= 0;
5269 u32 rx_pause
, tx_pause
;
5272 if (!phydev
->link
|| !phydev
->autoneg
)
5275 if (phydev
->advertising
& ADVERTISED_Pause
)
5276 local_advertising
= ADVERTISE_PAUSE_CAP
;
5278 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5279 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5282 remote_advertising
= LPA_PAUSE_CAP
;
5284 if (phydev
->asym_pause
)
5285 remote_advertising
|= LPA_PAUSE_ASYM
;
5287 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5288 remote_advertising
);
5289 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5290 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5292 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5297 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5300 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5301 u32
*rx_en
, u32
*tx_en
)
5303 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5304 struct hclge_dev
*hdev
= vport
->back
;
5306 *auto_neg
= hclge_get_autoneg(handle
);
5308 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5314 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5317 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5320 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5329 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5330 u32 rx_en
, u32 tx_en
)
5332 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5333 struct hclge_dev
*hdev
= vport
->back
;
5334 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5337 fc_autoneg
= hclge_get_autoneg(handle
);
5338 if (auto_neg
!= fc_autoneg
) {
5339 dev_info(&hdev
->pdev
->dev
,
5340 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5344 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5345 dev_info(&hdev
->pdev
->dev
,
5346 "Priority flow control enabled. Cannot set link flow control.\n");
5350 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5353 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5355 /* Only support flow control negotiation for netdev with
5356 * phy attached for now.
5361 return phy_start_aneg(phydev
);
5364 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5365 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5367 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5368 struct hclge_dev
*hdev
= vport
->back
;
5371 *speed
= hdev
->hw
.mac
.speed
;
5373 *duplex
= hdev
->hw
.mac
.duplex
;
5375 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5378 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5380 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5381 struct hclge_dev
*hdev
= vport
->back
;
5384 *media_type
= hdev
->hw
.mac
.media_type
;
5387 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5388 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5390 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5391 struct hclge_dev
*hdev
= vport
->back
;
5392 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5393 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5396 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5397 *tp_mdix
= ETH_TP_MDI_INVALID
;
5401 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5403 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5404 mdix_ctrl
= hnae3_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5405 HCLGE_PHY_MDIX_CTRL_S
);
5407 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5408 mdix
= hnae3_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5409 is_resolved
= hnae3_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5411 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5413 switch (mdix_ctrl
) {
5415 *tp_mdix_ctrl
= ETH_TP_MDI
;
5418 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5421 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5424 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5429 *tp_mdix
= ETH_TP_MDI_INVALID
;
5431 *tp_mdix
= ETH_TP_MDI_X
;
5433 *tp_mdix
= ETH_TP_MDI
;
5436 static int hclge_init_client_instance(struct hnae3_client
*client
,
5437 struct hnae3_ae_dev
*ae_dev
)
5439 struct hclge_dev
*hdev
= ae_dev
->priv
;
5440 struct hclge_vport
*vport
;
5443 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5444 vport
= &hdev
->vport
[i
];
5446 switch (client
->type
) {
5447 case HNAE3_CLIENT_KNIC
:
5449 hdev
->nic_client
= client
;
5450 vport
->nic
.client
= client
;
5451 ret
= client
->ops
->init_instance(&vport
->nic
);
5455 if (hdev
->roce_client
&&
5456 hnae3_dev_roce_supported(hdev
)) {
5457 struct hnae3_client
*rc
= hdev
->roce_client
;
5459 ret
= hclge_init_roce_base_info(vport
);
5463 ret
= rc
->ops
->init_instance(&vport
->roce
);
5469 case HNAE3_CLIENT_UNIC
:
5470 hdev
->nic_client
= client
;
5471 vport
->nic
.client
= client
;
5473 ret
= client
->ops
->init_instance(&vport
->nic
);
5478 case HNAE3_CLIENT_ROCE
:
5479 if (hnae3_dev_roce_supported(hdev
)) {
5480 hdev
->roce_client
= client
;
5481 vport
->roce
.client
= client
;
5484 if (hdev
->roce_client
&& hdev
->nic_client
) {
5485 ret
= hclge_init_roce_base_info(vport
);
5489 ret
= client
->ops
->init_instance(&vport
->roce
);
5499 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5500 struct hnae3_ae_dev
*ae_dev
)
5502 struct hclge_dev
*hdev
= ae_dev
->priv
;
5503 struct hclge_vport
*vport
;
5506 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5507 vport
= &hdev
->vport
[i
];
5508 if (hdev
->roce_client
) {
5509 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5511 hdev
->roce_client
= NULL
;
5512 vport
->roce
.client
= NULL
;
5514 if (client
->type
== HNAE3_CLIENT_ROCE
)
5516 if (client
->ops
->uninit_instance
) {
5517 client
->ops
->uninit_instance(&vport
->nic
, 0);
5518 hdev
->nic_client
= NULL
;
5519 vport
->nic
.client
= NULL
;
5524 static int hclge_pci_init(struct hclge_dev
*hdev
)
5526 struct pci_dev
*pdev
= hdev
->pdev
;
5527 struct hclge_hw
*hw
;
5530 ret
= pci_enable_device(pdev
);
5532 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5536 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5538 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5541 "can't set consistent PCI DMA");
5542 goto err_disable_device
;
5544 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5547 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5549 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5550 goto err_disable_device
;
5553 pci_set_master(pdev
);
5555 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5557 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5559 goto err_clr_master
;
5562 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5566 pci_clear_master(pdev
);
5567 pci_release_regions(pdev
);
5569 pci_disable_device(pdev
);
5574 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5576 struct pci_dev
*pdev
= hdev
->pdev
;
5578 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5579 pci_free_irq_vectors(pdev
);
5580 pci_clear_master(pdev
);
5581 pci_release_mem_regions(pdev
);
5582 pci_disable_device(pdev
);
5585 static void hclge_state_init(struct hclge_dev
*hdev
)
5587 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5588 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5589 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5590 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5591 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5592 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5595 static void hclge_state_uninit(struct hclge_dev
*hdev
)
5597 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5599 if (hdev
->service_timer
.function
)
5600 del_timer_sync(&hdev
->service_timer
);
5601 if (hdev
->service_task
.func
)
5602 cancel_work_sync(&hdev
->service_task
);
5603 if (hdev
->rst_service_task
.func
)
5604 cancel_work_sync(&hdev
->rst_service_task
);
5605 if (hdev
->mbx_service_task
.func
)
5606 cancel_work_sync(&hdev
->mbx_service_task
);
5609 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5611 struct pci_dev
*pdev
= ae_dev
->pdev
;
5612 struct hclge_dev
*hdev
;
5615 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5622 hdev
->ae_dev
= ae_dev
;
5623 hdev
->reset_type
= HNAE3_NONE_RESET
;
5624 ae_dev
->priv
= hdev
;
5626 ret
= hclge_pci_init(hdev
);
5628 dev_err(&pdev
->dev
, "PCI init failed\n");
5632 /* Firmware command queue initialize */
5633 ret
= hclge_cmd_queue_init(hdev
);
5635 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5636 goto err_pci_uninit
;
5639 /* Firmware command initialize */
5640 ret
= hclge_cmd_init(hdev
);
5642 goto err_cmd_uninit
;
5644 ret
= hclge_get_cap(hdev
);
5646 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5648 goto err_cmd_uninit
;
5651 ret
= hclge_configure(hdev
);
5653 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5654 goto err_cmd_uninit
;
5657 ret
= hclge_init_msi(hdev
);
5659 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5660 goto err_cmd_uninit
;
5663 ret
= hclge_misc_irq_init(hdev
);
5666 "Misc IRQ(vector0) init error, ret = %d.\n",
5668 goto err_msi_uninit
;
5671 ret
= hclge_alloc_tqps(hdev
);
5673 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5674 goto err_msi_irq_uninit
;
5677 ret
= hclge_alloc_vport(hdev
);
5679 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5680 goto err_msi_irq_uninit
;
5683 ret
= hclge_map_tqp(hdev
);
5685 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5686 goto err_msi_irq_uninit
;
5689 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5690 ret
= hclge_mac_mdio_config(hdev
);
5692 dev_err(&hdev
->pdev
->dev
,
5693 "mdio config fail ret=%d\n", ret
);
5694 goto err_msi_irq_uninit
;
5698 ret
= hclge_mac_init(hdev
);
5700 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5701 goto err_mdiobus_unreg
;
5704 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5706 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5707 goto err_mdiobus_unreg
;
5710 ret
= hclge_init_vlan_config(hdev
);
5712 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5713 goto err_mdiobus_unreg
;
5716 ret
= hclge_tm_schd_init(hdev
);
5718 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5719 goto err_mdiobus_unreg
;
5722 hclge_rss_init_cfg(hdev
);
5723 ret
= hclge_rss_init_hw(hdev
);
5725 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5726 goto err_mdiobus_unreg
;
5729 ret
= init_mgr_tbl(hdev
);
5731 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5732 goto err_mdiobus_unreg
;
5735 hclge_dcb_ops_set(hdev
);
5737 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5738 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5739 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5740 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5742 /* Enable MISC vector(vector0) */
5743 hclge_enable_vector(&hdev
->misc_vector
, true);
5745 hclge_state_init(hdev
);
5747 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5751 if (hdev
->hw
.mac
.phydev
)
5752 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5754 hclge_misc_irq_uninit(hdev
);
5756 pci_free_irq_vectors(pdev
);
5758 hclge_destroy_cmd_queue(&hdev
->hw
);
5760 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5761 pci_clear_master(pdev
);
5762 pci_release_regions(pdev
);
5763 pci_disable_device(pdev
);
5768 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5770 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5773 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5775 struct hclge_dev
*hdev
= ae_dev
->priv
;
5776 struct pci_dev
*pdev
= ae_dev
->pdev
;
5779 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5781 hclge_stats_clear(hdev
);
5782 memset(hdev
->vlan_table
, 0, sizeof(hdev
->vlan_table
));
5784 ret
= hclge_cmd_init(hdev
);
5786 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5790 ret
= hclge_get_cap(hdev
);
5792 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5797 ret
= hclge_configure(hdev
);
5799 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5803 ret
= hclge_map_tqp(hdev
);
5805 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5809 ret
= hclge_mac_init(hdev
);
5811 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5815 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5817 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5821 ret
= hclge_init_vlan_config(hdev
);
5823 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5827 ret
= hclge_tm_init_hw(hdev
);
5829 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5833 ret
= hclge_rss_init_hw(hdev
);
5835 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5839 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5845 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5847 struct hclge_dev
*hdev
= ae_dev
->priv
;
5848 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5850 hclge_state_uninit(hdev
);
5853 mdiobus_unregister(mac
->mdio_bus
);
5855 /* Disable MISC vector(vector0) */
5856 hclge_enable_vector(&hdev
->misc_vector
, false);
5857 hclge_destroy_cmd_queue(&hdev
->hw
);
5858 hclge_misc_irq_uninit(hdev
);
5859 hclge_pci_uninit(hdev
);
5860 ae_dev
->priv
= NULL
;
5863 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5865 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5866 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5867 struct hclge_dev
*hdev
= vport
->back
;
5869 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5872 static void hclge_get_channels(struct hnae3_handle
*handle
,
5873 struct ethtool_channels
*ch
)
5875 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5877 ch
->max_combined
= hclge_get_max_channels(handle
);
5878 ch
->other_count
= 1;
5880 ch
->combined_count
= vport
->alloc_tqps
;
5883 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5884 u16
*free_tqps
, u16
*max_rss_size
)
5886 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5887 struct hclge_dev
*hdev
= vport
->back
;
5891 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5892 if (!hdev
->htqp
[i
].alloced
)
5895 *free_tqps
= temp_tqps
;
5896 *max_rss_size
= hdev
->rss_size_max
;
5899 static void hclge_release_tqp(struct hclge_vport
*vport
)
5901 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5902 struct hclge_dev
*hdev
= vport
->back
;
5905 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5906 struct hclge_tqp
*tqp
=
5907 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5909 tqp
->q
.handle
= NULL
;
5910 tqp
->q
.tqp_index
= 0;
5911 tqp
->alloced
= false;
5914 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5918 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5920 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5921 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5922 struct hclge_dev
*hdev
= vport
->back
;
5923 int cur_rss_size
= kinfo
->rss_size
;
5924 int cur_tqps
= kinfo
->num_tqps
;
5925 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5926 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5927 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5932 /* Free old tqps, and reallocate with new tqp number when nic setup */
5933 hclge_release_tqp(vport
);
5935 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5937 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5941 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5943 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5947 ret
= hclge_tm_schd_init(hdev
);
5949 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5953 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5954 roundup_size
= ilog2(roundup_size
);
5955 /* Set the RSS TC mode according to the new RSS size */
5956 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5959 if (!(hdev
->hw_tc_map
& BIT(i
)))
5963 tc_size
[i
] = roundup_size
;
5964 tc_offset
[i
] = kinfo
->rss_size
* i
;
5966 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5970 /* Reinitializes the rss indirect table according to the new RSS size */
5971 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5975 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5976 rss_indir
[i
] = i
% kinfo
->rss_size
;
5978 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5980 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5986 dev_info(&hdev
->pdev
->dev
,
5987 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5988 cur_rss_size
, kinfo
->rss_size
,
5989 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5994 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5995 u32
*regs_num_64_bit
)
5997 struct hclge_desc desc
;
6001 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
6002 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6004 dev_err(&hdev
->pdev
->dev
,
6005 "Query register number cmd failed, ret = %d.\n", ret
);
6009 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
6010 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
6012 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
6019 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6022 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6024 struct hclge_desc
*desc
;
6025 u32
*reg_val
= data
;
6034 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
6035 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6039 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
6040 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6042 dev_err(&hdev
->pdev
->dev
,
6043 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
6048 for (i
= 0; i
< cmd_num
; i
++) {
6050 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
6051 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
6053 desc_data
= (__le32
*)(&desc
[i
]);
6054 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
6056 for (k
= 0; k
< n
; k
++) {
6057 *reg_val
++ = le32_to_cpu(*desc_data
++);
6069 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6072 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6074 struct hclge_desc
*desc
;
6075 u64
*reg_val
= data
;
6084 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
6085 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6089 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
6090 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6092 dev_err(&hdev
->pdev
->dev
,
6093 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
6098 for (i
= 0; i
< cmd_num
; i
++) {
6100 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
6101 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
6103 desc_data
= (__le64
*)(&desc
[i
]);
6104 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
6106 for (k
= 0; k
< n
; k
++) {
6107 *reg_val
++ = le64_to_cpu(*desc_data
++);
6119 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
6121 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6122 struct hclge_dev
*hdev
= vport
->back
;
6123 u32 regs_num_32_bit
, regs_num_64_bit
;
6126 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6128 dev_err(&hdev
->pdev
->dev
,
6129 "Get register number failed, ret = %d.\n", ret
);
6133 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
6136 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
6139 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6140 struct hclge_dev
*hdev
= vport
->back
;
6141 u32 regs_num_32_bit
, regs_num_64_bit
;
6144 *version
= hdev
->fw_version
;
6146 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6148 dev_err(&hdev
->pdev
->dev
,
6149 "Get register number failed, ret = %d.\n", ret
);
6153 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
6155 dev_err(&hdev
->pdev
->dev
,
6156 "Get 32 bit register failed, ret = %d.\n", ret
);
6160 data
= (u32
*)data
+ regs_num_32_bit
;
6161 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
6164 dev_err(&hdev
->pdev
->dev
,
6165 "Get 64 bit register failed, ret = %d.\n", ret
);
6168 static int hclge_set_led_status(struct hclge_dev
*hdev
, u8 locate_led_status
)
6170 struct hclge_set_led_state_cmd
*req
;
6171 struct hclge_desc desc
;
6174 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6176 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6177 hnae3_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6178 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6180 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6182 dev_err(&hdev
->pdev
->dev
,
6183 "Send set led state cmd error, ret =%d\n", ret
);
6188 enum hclge_led_status
{
6191 HCLGE_LED_NO_CHANGE
= 0xFF,
6194 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6195 enum ethtool_phys_id_state status
)
6197 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6198 struct hclge_dev
*hdev
= vport
->back
;
6201 case ETHTOOL_ID_ACTIVE
:
6202 return hclge_set_led_status(hdev
, HCLGE_LED_ON
);
6203 case ETHTOOL_ID_INACTIVE
:
6204 return hclge_set_led_status(hdev
, HCLGE_LED_OFF
);
6210 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6211 unsigned long *supported
,
6212 unsigned long *advertising
)
6214 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6215 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6216 struct hclge_dev
*hdev
= vport
->back
;
6217 unsigned int idx
= 0;
6219 for (; idx
< size
; idx
++) {
6220 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6221 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6225 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6228 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6229 struct hclge_dev
*hdev
= vport
->back
;
6230 u8 media_type
= hdev
->hw
.mac
.media_type
;
6232 switch (media_type
) {
6233 case HNAE3_MEDIA_TYPE_FIBER
:
6234 *port_type
= PORT_FIBRE
;
6236 case HNAE3_MEDIA_TYPE_COPPER
:
6237 *port_type
= PORT_TP
;
6239 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6241 *port_type
= PORT_OTHER
;
6246 static const struct hnae3_ae_ops hclge_ops
= {
6247 .init_ae_dev
= hclge_init_ae_dev
,
6248 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6249 .init_client_instance
= hclge_init_client_instance
,
6250 .uninit_client_instance
= hclge_uninit_client_instance
,
6251 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6252 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6253 .get_vector
= hclge_get_vector
,
6254 .put_vector
= hclge_put_vector
,
6255 .set_promisc_mode
= hclge_set_promisc_mode
,
6256 .set_loopback
= hclge_set_loopback
,
6257 .start
= hclge_ae_start
,
6258 .stop
= hclge_ae_stop
,
6259 .get_status
= hclge_get_status
,
6260 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6261 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6262 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6263 .get_media_type
= hclge_get_media_type
,
6264 .get_rss_key_size
= hclge_get_rss_key_size
,
6265 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6266 .get_rss
= hclge_get_rss
,
6267 .set_rss
= hclge_set_rss
,
6268 .set_rss_tuple
= hclge_set_rss_tuple
,
6269 .get_rss_tuple
= hclge_get_rss_tuple
,
6270 .get_tc_size
= hclge_get_tc_size
,
6271 .get_mac_addr
= hclge_get_mac_addr
,
6272 .set_mac_addr
= hclge_set_mac_addr
,
6273 .add_uc_addr
= hclge_add_uc_addr
,
6274 .rm_uc_addr
= hclge_rm_uc_addr
,
6275 .add_mc_addr
= hclge_add_mc_addr
,
6276 .rm_mc_addr
= hclge_rm_mc_addr
,
6277 .update_mta_status
= hclge_update_mta_status
,
6278 .set_autoneg
= hclge_set_autoneg
,
6279 .get_autoneg
= hclge_get_autoneg
,
6280 .get_pauseparam
= hclge_get_pauseparam
,
6281 .set_pauseparam
= hclge_set_pauseparam
,
6282 .set_mtu
= hclge_set_mtu
,
6283 .reset_queue
= hclge_reset_tqp
,
6284 .get_stats
= hclge_get_stats
,
6285 .update_stats
= hclge_update_stats
,
6286 .get_strings
= hclge_get_strings
,
6287 .get_sset_count
= hclge_get_sset_count
,
6288 .get_fw_version
= hclge_get_fw_version
,
6289 .get_mdix_mode
= hclge_get_mdix_mode
,
6290 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6291 .set_vlan_filter
= hclge_set_vlan_filter
,
6292 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6293 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6294 .reset_event
= hclge_reset_event
,
6295 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6296 .set_channels
= hclge_set_channels
,
6297 .get_channels
= hclge_get_channels
,
6298 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6299 .get_regs_len
= hclge_get_regs_len
,
6300 .get_regs
= hclge_get_regs
,
6301 .set_led_id
= hclge_set_led_id
,
6302 .get_link_mode
= hclge_get_link_mode
,
6303 .get_port_type
= hclge_get_port_type
,
6306 static struct hnae3_ae_algo ae_algo
= {
6308 .pdev_id_table
= ae_algo_pci_tbl
,
6311 static int hclge_init(void)
6313 pr_info("%s is initializing\n", HCLGE_NAME
);
6315 hnae3_register_ae_algo(&ae_algo
);
6320 static void hclge_exit(void)
6322 hnae3_unregister_ae_algo(&ae_algo
);
6324 module_init(hclge_init
);
6325 module_exit(hclge_exit
);
6327 MODULE_LICENSE("GPL");
6328 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6329 MODULE_DESCRIPTION("HCLGE Driver");
6330 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob