2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
21 #include "hclge_cmd.h"
22 #include "hclge_dcb.h"
23 #include "hclge_main.h"
24 #include "hclge_mdio.h"
28 #define HCLGE_NAME "hclge"
29 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
30 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
31 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
32 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
34 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
35 enum hclge_mta_dmac_sel_type mta_mac_sel
,
37 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
39 static struct hnae3_ae_algo ae_algo
;
41 static const struct pci_device_id ae_algo_pci_tbl
[] = {
42 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
43 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
44 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
45 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
49 /* required last entry */
53 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
55 "Serdes Loopback test",
59 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
98 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
223 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
280 {"mac_tx_overrsize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num
)},
282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
294 {"mac_tx_1519_max_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num
)},
296 {"mac_rx_total_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
298 {"mac_rx_total_oct_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
300 {"mac_rx_good_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
302 {"mac_rx_bad_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
304 {"mac_rx_good_oct_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
306 {"mac_rx_bad_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
308 {"mac_rx_uni_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
310 {"mac_rx_multi_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
312 {"mac_rx_broad_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
314 {"mac_rx_undersize_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
316 {"mac_rx_overrsize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num
)},
318 {"mac_rx_64_oct_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
320 {"mac_rx_65_127_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
322 {"mac_rx_128_255_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
324 {"mac_rx_256_511_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
326 {"mac_rx_512_1023_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
328 {"mac_rx_1024_1518_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
330 {"mac_rx_1519_max_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num
)},
333 {"mac_trans_fragment_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num
)},
335 {"mac_trans_undermin_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num
)},
337 {"mac_trans_jabber_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num
)},
339 {"mac_trans_err_all_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num
)},
341 {"mac_trans_from_app_good_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num
)},
343 {"mac_trans_from_app_bad_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num
)},
345 {"mac_rcv_fragment_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num
)},
347 {"mac_rcv_undermin_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num
)},
349 {"mac_rcv_jabber_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num
)},
351 {"mac_rcv_fcs_err_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num
)},
353 {"mac_rcv_send_app_good_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num
)},
355 {"mac_rcv_send_app_bad_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num
)}
359 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
361 #define HCLGE_64_BIT_CMD_NUM 5
362 #define HCLGE_64_BIT_RTN_DATANUM 4
363 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
364 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
369 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
370 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
372 dev_err(&hdev
->pdev
->dev
,
373 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
377 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
378 if (unlikely(i
== 0)) {
379 desc_data
= (u64
*)(&desc
[i
].data
[0]);
380 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
382 desc_data
= (u64
*)(&desc
[i
]);
383 n
= HCLGE_64_BIT_RTN_DATANUM
;
385 for (k
= 0; k
< n
; k
++) {
386 *data
++ += cpu_to_le64(*desc_data
);
394 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
396 stats
->pkt_curr_buf_cnt
= 0;
397 stats
->pkt_curr_buf_tc0_cnt
= 0;
398 stats
->pkt_curr_buf_tc1_cnt
= 0;
399 stats
->pkt_curr_buf_tc2_cnt
= 0;
400 stats
->pkt_curr_buf_tc3_cnt
= 0;
401 stats
->pkt_curr_buf_tc4_cnt
= 0;
402 stats
->pkt_curr_buf_tc5_cnt
= 0;
403 stats
->pkt_curr_buf_tc6_cnt
= 0;
404 stats
->pkt_curr_buf_tc7_cnt
= 0;
407 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
409 #define HCLGE_32_BIT_CMD_NUM 8
410 #define HCLGE_32_BIT_RTN_DATANUM 8
412 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
413 struct hclge_32_bit_stats
*all_32_bit_stats
;
419 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
420 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
422 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
423 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
425 dev_err(&hdev
->pdev
->dev
,
426 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
431 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
432 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
433 if (unlikely(i
== 0)) {
434 all_32_bit_stats
->igu_rx_err_pkt
+=
435 cpu_to_le32(desc
[i
].data
[0]);
436 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
437 cpu_to_le32(desc
[i
].data
[1] & 0xffff);
438 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
439 cpu_to_le32((desc
[i
].data
[1] >> 16) & 0xffff);
441 desc_data
= (u32
*)(&desc
[i
].data
[2]);
442 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
444 desc_data
= (u32
*)(&desc
[i
]);
445 n
= HCLGE_32_BIT_RTN_DATANUM
;
447 for (k
= 0; k
< n
; k
++) {
448 *data
++ += cpu_to_le32(*desc_data
);
456 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
458 #define HCLGE_MAC_CMD_NUM 17
459 #define HCLGE_RTN_DATA_NUM 4
461 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
462 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
467 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
468 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
470 dev_err(&hdev
->pdev
->dev
,
471 "Get MAC pkt stats fail, status = %d.\n", ret
);
476 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
477 if (unlikely(i
== 0)) {
478 desc_data
= (u64
*)(&desc
[i
].data
[0]);
479 n
= HCLGE_RTN_DATA_NUM
- 2;
481 desc_data
= (u64
*)(&desc
[i
]);
482 n
= HCLGE_RTN_DATA_NUM
;
484 for (k
= 0; k
< n
; k
++) {
485 *data
++ += cpu_to_le64(*desc_data
);
493 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
495 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
496 struct hclge_vport
*vport
= hclge_get_vport(handle
);
497 struct hclge_dev
*hdev
= vport
->back
;
498 struct hnae3_queue
*queue
;
499 struct hclge_desc desc
[1];
500 struct hclge_tqp
*tqp
;
503 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
504 queue
= handle
->kinfo
.tqp
[i
];
505 tqp
= container_of(queue
, struct hclge_tqp
, q
);
506 /* command : HCLGE_OPC_QUERY_IGU_STAT */
507 hclge_cmd_setup_basic_desc(&desc
[0],
508 HCLGE_OPC_QUERY_RX_STATUS
,
511 desc
[0].data
[0] = (tqp
->index
& 0x1ff);
512 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
514 dev_err(&hdev
->pdev
->dev
,
515 "Query tqp stat fail, status = %d,queue = %d\n",
519 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
520 cpu_to_le32(desc
[0].data
[4]);
523 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
524 queue
= handle
->kinfo
.tqp
[i
];
525 tqp
= container_of(queue
, struct hclge_tqp
, q
);
526 /* command : HCLGE_OPC_QUERY_IGU_STAT */
527 hclge_cmd_setup_basic_desc(&desc
[0],
528 HCLGE_OPC_QUERY_TX_STATUS
,
531 desc
[0].data
[0] = (tqp
->index
& 0x1ff);
532 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
534 dev_err(&hdev
->pdev
->dev
,
535 "Query tqp stat fail, status = %d,queue = %d\n",
539 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
540 cpu_to_le32(desc
[0].data
[4]);
546 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
548 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
549 struct hclge_tqp
*tqp
;
553 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
554 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
555 *buff
++ = cpu_to_le64(tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
);
558 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
559 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
560 *buff
++ = cpu_to_le64(tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
);
566 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
568 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
570 return kinfo
->num_tqps
* (2);
573 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
575 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
579 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
580 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
581 struct hclge_tqp
, q
);
582 snprintf(buff
, ETH_GSTRING_LEN
, "rcb_q%d_tx_pktnum_rcd",
584 buff
= buff
+ ETH_GSTRING_LEN
;
587 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
588 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
589 struct hclge_tqp
, q
);
590 snprintf(buff
, ETH_GSTRING_LEN
, "rcb_q%d_rx_pktnum_rcd",
592 buff
= buff
+ ETH_GSTRING_LEN
;
598 static u64
*hclge_comm_get_stats(void *comm_stats
,
599 const struct hclge_comm_stats_str strs
[],
605 for (i
= 0; i
< size
; i
++)
606 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
611 static u8
*hclge_comm_get_strings(u32 stringset
,
612 const struct hclge_comm_stats_str strs
[],
615 char *buff
= (char *)data
;
618 if (stringset
!= ETH_SS_STATS
)
621 for (i
= 0; i
< size
; i
++) {
622 snprintf(buff
, ETH_GSTRING_LEN
,
624 buff
= buff
+ ETH_GSTRING_LEN
;
630 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
631 struct net_device_stats
*net_stats
)
633 net_stats
->tx_dropped
= 0;
634 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
635 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
636 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
638 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
639 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
640 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_err_pkt
;
641 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
642 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
643 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rcv_fcs_err_pkt_num
;
645 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
646 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
648 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rcv_fcs_err_pkt_num
;
649 net_stats
->rx_length_errors
=
650 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
651 net_stats
->rx_length_errors
+=
652 hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
653 net_stats
->rx_over_errors
=
654 hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
657 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
659 struct hnae3_handle
*handle
;
662 handle
= &hdev
->vport
[0].nic
;
663 if (handle
->client
) {
664 status
= hclge_tqps_update_stats(handle
);
666 dev_err(&hdev
->pdev
->dev
,
667 "Update TQPS stats fail, status = %d.\n",
672 status
= hclge_mac_update_stats(hdev
);
674 dev_err(&hdev
->pdev
->dev
,
675 "Update MAC stats fail, status = %d.\n", status
);
677 status
= hclge_32_bit_update_stats(hdev
);
679 dev_err(&hdev
->pdev
->dev
,
680 "Update 32 bit stats fail, status = %d.\n",
683 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
686 static void hclge_update_stats(struct hnae3_handle
*handle
,
687 struct net_device_stats
*net_stats
)
689 struct hclge_vport
*vport
= hclge_get_vport(handle
);
690 struct hclge_dev
*hdev
= vport
->back
;
691 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
694 status
= hclge_mac_update_stats(hdev
);
696 dev_err(&hdev
->pdev
->dev
,
697 "Update MAC stats fail, status = %d.\n",
700 status
= hclge_32_bit_update_stats(hdev
);
702 dev_err(&hdev
->pdev
->dev
,
703 "Update 32 bit stats fail, status = %d.\n",
706 status
= hclge_64_bit_update_stats(hdev
);
708 dev_err(&hdev
->pdev
->dev
,
709 "Update 64 bit stats fail, status = %d.\n",
712 status
= hclge_tqps_update_stats(handle
);
714 dev_err(&hdev
->pdev
->dev
,
715 "Update TQPS stats fail, status = %d.\n",
718 hclge_update_netstat(hw_stats
, net_stats
);
721 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
723 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
725 struct hclge_vport
*vport
= hclge_get_vport(handle
);
726 struct hclge_dev
*hdev
= vport
->back
;
729 /* Loopback test support rules:
730 * mac: only GE mode support
731 * serdes: all mac mode will support include GE/XGE/LGE/CGE
732 * phy: only support when phy device exist on board
734 if (stringset
== ETH_SS_TEST
) {
735 /* clear loopback bit flags at first */
736 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
737 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
738 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
739 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
741 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
745 } else if (stringset
== ETH_SS_STATS
) {
746 count
= ARRAY_SIZE(g_mac_stats_string
) +
747 ARRAY_SIZE(g_all_32bit_stats_string
) +
748 ARRAY_SIZE(g_all_64bit_stats_string
) +
749 hclge_tqps_get_sset_count(handle
, stringset
);
755 static void hclge_get_strings(struct hnae3_handle
*handle
,
759 u8
*p
= (char *)data
;
762 if (stringset
== ETH_SS_STATS
) {
763 size
= ARRAY_SIZE(g_mac_stats_string
);
764 p
= hclge_comm_get_strings(stringset
,
768 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
769 p
= hclge_comm_get_strings(stringset
,
770 g_all_32bit_stats_string
,
773 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
774 p
= hclge_comm_get_strings(stringset
,
775 g_all_64bit_stats_string
,
778 p
= hclge_tqps_get_strings(handle
, p
);
779 } else if (stringset
== ETH_SS_TEST
) {
780 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
782 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
784 p
+= ETH_GSTRING_LEN
;
786 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
788 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
790 p
+= ETH_GSTRING_LEN
;
792 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
794 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
796 p
+= ETH_GSTRING_LEN
;
801 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
803 struct hclge_vport
*vport
= hclge_get_vport(handle
);
804 struct hclge_dev
*hdev
= vport
->back
;
807 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
809 ARRAY_SIZE(g_mac_stats_string
),
811 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
812 g_all_32bit_stats_string
,
813 ARRAY_SIZE(g_all_32bit_stats_string
),
815 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
816 g_all_64bit_stats_string
,
817 ARRAY_SIZE(g_all_64bit_stats_string
),
819 p
= hclge_tqps_get_stats(handle
, p
);
822 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
823 struct hclge_func_status
*status
)
825 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
828 /* Set the pf to main pf */
829 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
830 hdev
->flag
|= HCLGE_FLAG_MAIN
;
832 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
834 hdev
->num_req_vfs
= status
->vf_num
/ status
->pf_num
;
838 static int hclge_query_function_status(struct hclge_dev
*hdev
)
840 struct hclge_func_status
*req
;
841 struct hclge_desc desc
;
845 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
846 req
= (struct hclge_func_status
*)desc
.data
;
849 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
851 dev_err(&hdev
->pdev
->dev
,
852 "query function status failed %d.\n",
858 /* Check pf reset is done */
861 usleep_range(1000, 2000);
862 } while (timeout
++ < 5);
864 ret
= hclge_parse_func_status(hdev
, req
);
869 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
871 struct hclge_pf_res
*req
;
872 struct hclge_desc desc
;
875 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
876 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
878 dev_err(&hdev
->pdev
->dev
,
879 "query pf resource failed %d.\n", ret
);
883 req
= (struct hclge_pf_res
*)desc
.data
;
884 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
885 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
887 if (hnae3_dev_roce_supported(hdev
)) {
888 hdev
->num_roce_msix
=
889 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
890 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
892 /* PF should have NIC vectors and Roce vectors,
893 * NIC vectors are queued before Roce vectors.
895 hdev
->num_msi
= hdev
->num_roce_msix
+ HCLGE_ROCE_VECTOR_OFFSET
;
898 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
899 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
905 static int hclge_parse_speed(int speed_cmd
, int *speed
)
909 *speed
= HCLGE_MAC_SPEED_10M
;
912 *speed
= HCLGE_MAC_SPEED_100M
;
915 *speed
= HCLGE_MAC_SPEED_1G
;
918 *speed
= HCLGE_MAC_SPEED_10G
;
921 *speed
= HCLGE_MAC_SPEED_25G
;
924 *speed
= HCLGE_MAC_SPEED_40G
;
927 *speed
= HCLGE_MAC_SPEED_50G
;
930 *speed
= HCLGE_MAC_SPEED_100G
;
939 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
941 struct hclge_cfg_param
*req
;
942 u64 mac_addr_tmp_high
;
946 req
= (struct hclge_cfg_param
*)desc
[0].data
;
948 /* get the configuration */
949 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
952 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
953 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
954 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
955 HCLGE_CFG_TQP_DESC_N_M
,
956 HCLGE_CFG_TQP_DESC_N_S
);
958 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
959 HCLGE_CFG_PHY_ADDR_M
,
960 HCLGE_CFG_PHY_ADDR_S
);
961 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
962 HCLGE_CFG_MEDIA_TP_M
,
963 HCLGE_CFG_MEDIA_TP_S
);
964 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
965 HCLGE_CFG_RX_BUF_LEN_M
,
966 HCLGE_CFG_RX_BUF_LEN_S
);
967 /* get mac_address */
968 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
969 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
970 HCLGE_CFG_MAC_ADDR_H_M
,
971 HCLGE_CFG_MAC_ADDR_H_S
);
973 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
975 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
976 HCLGE_CFG_DEFAULT_SPEED_M
,
977 HCLGE_CFG_DEFAULT_SPEED_S
);
978 for (i
= 0; i
< ETH_ALEN
; i
++)
979 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
981 req
= (struct hclge_cfg_param
*)desc
[1].data
;
982 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
985 /* hclge_get_cfg: query the static parameter from flash
986 * @hdev: pointer to struct hclge_dev
987 * @hcfg: the config structure to be getted
989 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
991 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
992 struct hclge_cfg_param
*req
;
995 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
996 req
= (struct hclge_cfg_param
*)desc
[i
].data
;
997 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
999 hnae_set_field(req
->offset
, HCLGE_CFG_OFFSET_M
,
1000 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1001 /* Len should be united by 4 bytes when send to hardware */
1002 hnae_set_field(req
->offset
, HCLGE_CFG_RD_LEN_M
,
1004 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1005 req
->offset
= cpu_to_le32(req
->offset
);
1008 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1010 dev_err(&hdev
->pdev
->dev
,
1011 "get config failed %d.\n", ret
);
1015 hclge_parse_cfg(hcfg
, desc
);
1019 static int hclge_get_cap(struct hclge_dev
*hdev
)
1023 ret
= hclge_query_function_status(hdev
);
1025 dev_err(&hdev
->pdev
->dev
,
1026 "query function status error %d.\n", ret
);
1030 /* get pf resource */
1031 ret
= hclge_query_pf_resource(hdev
);
1033 dev_err(&hdev
->pdev
->dev
,
1034 "query pf resource error %d.\n", ret
);
1041 static int hclge_configure(struct hclge_dev
*hdev
)
1043 struct hclge_cfg cfg
;
1046 ret
= hclge_get_cfg(hdev
, &cfg
);
1048 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1052 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1053 hdev
->base_tqp_pid
= 0;
1054 hdev
->rss_size_max
= 1;
1055 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1056 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1057 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1058 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1059 hdev
->num_desc
= cfg
.tqp_desc_num
;
1060 hdev
->tm_info
.num_pg
= 1;
1061 hdev
->tc_max
= cfg
.tc_num
;
1062 hdev
->tm_info
.hw_pfc_map
= 0;
1064 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1066 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1070 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1071 (hdev
->tc_max
< 1)) {
1072 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1077 /* Dev does not support DCB */
1078 if (!hnae3_dev_dcb_supported(hdev
)) {
1082 hdev
->pfc_max
= hdev
->tc_max
;
1085 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1087 /* Currently not support uncontiuous tc */
1088 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1089 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1091 if (!hdev
->num_vmdq_vport
&& !hdev
->num_req_vfs
)
1092 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1094 hdev
->tx_sch_mode
= HCLGE_FLAG_VNET_BASE_SCH_MODE
;
1099 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1102 struct hclge_cfg_tso_status
*req
;
1103 struct hclge_desc desc
;
1105 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1107 req
= (struct hclge_cfg_tso_status
*)desc
.data
;
1108 hnae_set_field(req
->tso_mss_min
, HCLGE_TSO_MSS_MIN_M
,
1109 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1110 hnae_set_field(req
->tso_mss_max
, HCLGE_TSO_MSS_MIN_M
,
1111 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1113 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1116 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1118 struct hclge_tqp
*tqp
;
1121 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1122 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1128 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1129 tqp
->dev
= &hdev
->pdev
->dev
;
1132 tqp
->q
.ae_algo
= &ae_algo
;
1133 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1134 tqp
->q
.desc_num
= hdev
->num_desc
;
1135 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1136 i
* HCLGE_TQP_REG_SIZE
;
1144 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1145 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1147 struct hclge_tqp_map
*req
;
1148 struct hclge_desc desc
;
1151 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1153 req
= (struct hclge_tqp_map
*)desc
.data
;
1154 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1155 req
->tqp_vf
= cpu_to_le16(func_id
);
1156 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1157 1 << HCLGE_TQP_MAP_EN_B
;
1158 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1160 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1162 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1170 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1171 struct hnae3_queue
**tqp
, u16 num_tqps
)
1173 struct hclge_dev
*hdev
= vport
->back
;
1174 int i
, alloced
, func_id
, ret
;
1177 func_id
= vport
->vport_id
;
1178 is_pf
= (vport
->vport_id
== 0) ? true : false;
1180 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1181 alloced
< num_tqps
; i
++) {
1182 if (!hdev
->htqp
[i
].alloced
) {
1183 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1184 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1185 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1186 hdev
->htqp
[i
].alloced
= true;
1187 ret
= hclge_map_tqps_to_func(hdev
, func_id
,
1188 hdev
->htqp
[i
].index
,
1196 vport
->alloc_tqps
= num_tqps
;
1201 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1203 struct hnae3_handle
*nic
= &vport
->nic
;
1204 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1205 struct hclge_dev
*hdev
= vport
->back
;
1208 kinfo
->num_desc
= hdev
->num_desc
;
1209 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1210 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1212 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1213 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1215 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1216 if (hdev
->hw_tc_map
& BIT(i
)) {
1217 kinfo
->tc_info
[i
].enable
= true;
1218 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1219 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1220 kinfo
->tc_info
[i
].tc
= i
;
1222 /* Set to default queue if TC is disable */
1223 kinfo
->tc_info
[i
].enable
= false;
1224 kinfo
->tc_info
[i
].tqp_offset
= 0;
1225 kinfo
->tc_info
[i
].tqp_count
= 1;
1226 kinfo
->tc_info
[i
].tc
= 0;
1230 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1231 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1235 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1237 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1244 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1246 /* this would be initialized later */
1249 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1251 struct hnae3_handle
*nic
= &vport
->nic
;
1252 struct hclge_dev
*hdev
= vport
->back
;
1255 nic
->pdev
= hdev
->pdev
;
1256 nic
->ae_algo
= &ae_algo
;
1257 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1259 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1260 ret
= hclge_knic_setup(vport
, num_tqps
);
1262 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1267 hclge_unic_setup(vport
, num_tqps
);
1273 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1275 struct pci_dev
*pdev
= hdev
->pdev
;
1276 struct hclge_vport
*vport
;
1282 /* We need to alloc a vport for main NIC of PF */
1283 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1285 if (hdev
->num_tqps
< num_vport
)
1286 num_vport
= hdev
->num_tqps
;
1288 /* Alloc the same number of TQPs for every vport */
1289 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1290 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1292 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1297 hdev
->vport
= vport
;
1298 hdev
->num_alloc_vport
= num_vport
;
1300 #ifdef CONFIG_PCI_IOV
1302 if (hdev
->num_req_vfs
) {
1303 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1305 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1307 hdev
->num_alloc_vfs
= 0;
1308 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1313 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1316 for (i
= 0; i
< num_vport
; i
++) {
1318 vport
->vport_id
= i
;
1321 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1323 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1326 "vport setup failed for vport %d, %d\n",
1337 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1338 struct hclge_pkt_buf_alloc
*buf_alloc
)
1340 /* TX buffer size is unit by 128 byte */
1341 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1342 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1343 struct hclge_tx_buff_alloc
*req
;
1344 struct hclge_desc desc
;
1348 req
= (struct hclge_tx_buff_alloc
*)desc
.data
;
1350 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1351 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1352 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1354 req
->tx_pkt_buff
[i
] =
1355 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1356 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1359 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1361 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1369 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1370 struct hclge_pkt_buf_alloc
*buf_alloc
)
1372 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1375 dev_err(&hdev
->pdev
->dev
,
1376 "tx buffer alloc failed %d\n", ret
);
1383 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1387 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1388 if (hdev
->hw_tc_map
& BIT(i
))
1393 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1397 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1398 if (hdev
->hw_tc_map
& BIT(i
) &&
1399 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1404 /* Get the number of pfc enabled TCs, which have private buffer */
1405 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1406 struct hclge_pkt_buf_alloc
*buf_alloc
)
1408 struct hclge_priv_buf
*priv
;
1411 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1412 priv
= &buf_alloc
->priv_buf
[i
];
1413 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1421 /* Get the number of pfc disabled TCs, which have private buffer */
1422 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1423 struct hclge_pkt_buf_alloc
*buf_alloc
)
1425 struct hclge_priv_buf
*priv
;
1428 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1429 priv
= &buf_alloc
->priv_buf
[i
];
1430 if (hdev
->hw_tc_map
& BIT(i
) &&
1431 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1439 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1441 struct hclge_priv_buf
*priv
;
1445 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1446 priv
= &buf_alloc
->priv_buf
[i
];
1448 rx_priv
+= priv
->buf_size
;
1453 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1455 u32 i
, total_tx_size
= 0;
1457 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1458 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1460 return total_tx_size
;
1463 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1464 struct hclge_pkt_buf_alloc
*buf_alloc
,
1467 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1468 int tc_num
, pfc_enable_num
;
1473 tc_num
= hclge_get_tc_num(hdev
);
1474 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1476 if (hnae3_dev_dcb_supported(hdev
))
1477 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1479 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1481 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1482 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1484 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1486 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1487 if (rx_all
<= rx_priv
+ shared_std
)
1490 shared_buf
= rx_all
- rx_priv
;
1491 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1492 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1493 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1495 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1496 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1497 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1498 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1499 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1501 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1502 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1509 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1510 struct hclge_pkt_buf_alloc
*buf_alloc
)
1514 total_size
= hdev
->pkt_buf_size
;
1516 /* alloc tx buffer for all enabled tc */
1517 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1518 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1520 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1523 if (hdev
->hw_tc_map
& BIT(i
))
1524 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1526 priv
->tx_buf_size
= 0;
1528 total_size
-= priv
->tx_buf_size
;
1534 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1535 * @hdev: pointer to struct hclge_dev
1536 * @buf_alloc: pointer to buffer calculation data
1537 * @return: 0: calculate sucessful, negative: fail
1539 int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1540 struct hclge_pkt_buf_alloc
*buf_alloc
)
1542 u32 rx_all
= hdev
->pkt_buf_size
;
1543 int no_pfc_priv_num
, pfc_priv_num
;
1544 struct hclge_priv_buf
*priv
;
1547 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1549 /* When DCB is not supported, rx private
1550 * buffer is not allocated.
1552 if (!hnae3_dev_dcb_supported(hdev
)) {
1553 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1559 /* step 1, try to alloc private buffer for all enabled tc */
1560 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1561 priv
= &buf_alloc
->priv_buf
[i
];
1562 if (hdev
->hw_tc_map
& BIT(i
)) {
1564 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1565 priv
->wl
.low
= hdev
->mps
;
1566 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1567 priv
->buf_size
= priv
->wl
.high
+
1571 priv
->wl
.high
= 2 * hdev
->mps
;
1572 priv
->buf_size
= priv
->wl
.high
;
1582 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1585 /* step 2, try to decrease the buffer size of
1586 * no pfc TC's private buffer
1588 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1589 priv
= &buf_alloc
->priv_buf
[i
];
1596 if (!(hdev
->hw_tc_map
& BIT(i
)))
1601 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1603 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1604 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1607 priv
->wl
.high
= hdev
->mps
;
1608 priv
->buf_size
= priv
->wl
.high
;
1612 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1615 /* step 3, try to reduce the number of pfc disabled TCs,
1616 * which have private buffer
1618 /* get the total no pfc enable TC number, which have private buffer */
1619 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1621 /* let the last to be cleared first */
1622 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1623 priv
= &buf_alloc
->priv_buf
[i
];
1625 if (hdev
->hw_tc_map
& BIT(i
) &&
1626 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1627 /* Clear the no pfc TC private buffer */
1635 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1636 no_pfc_priv_num
== 0)
1640 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1643 /* step 4, try to reduce the number of pfc enabled TCs
1644 * which have private buffer.
1646 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1648 /* let the last to be cleared first */
1649 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1650 priv
= &buf_alloc
->priv_buf
[i
];
1652 if (hdev
->hw_tc_map
& BIT(i
) &&
1653 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1654 /* Reduce the number of pfc TC with private buffer */
1662 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1666 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1672 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1673 struct hclge_pkt_buf_alloc
*buf_alloc
)
1675 struct hclge_rx_priv_buff
*req
;
1676 struct hclge_desc desc
;
1680 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1681 req
= (struct hclge_rx_priv_buff
*)desc
.data
;
1683 /* Alloc private buffer TCs */
1684 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1685 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1688 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1690 cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B
);
1694 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1695 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1697 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1699 dev_err(&hdev
->pdev
->dev
,
1700 "rx private buffer alloc cmd failed %d\n", ret
);
1707 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1709 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1710 struct hclge_pkt_buf_alloc
*buf_alloc
)
1712 struct hclge_rx_priv_wl_buf
*req
;
1713 struct hclge_priv_buf
*priv
;
1714 struct hclge_desc desc
[2];
1718 for (i
= 0; i
< 2; i
++) {
1719 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1721 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1723 /* The first descriptor set the NEXT bit to 1 */
1725 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1727 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1729 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1730 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1732 priv
= &buf_alloc
->priv_buf
[idx
];
1733 req
->tc_wl
[j
].high
=
1734 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1735 req
->tc_wl
[j
].high
|=
1736 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1737 HCLGE_RX_PRIV_EN_B
);
1739 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1740 req
->tc_wl
[j
].low
|=
1741 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1742 HCLGE_RX_PRIV_EN_B
);
1746 /* Send 2 descriptor at one time */
1747 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1749 dev_err(&hdev
->pdev
->dev
,
1750 "rx private waterline config cmd failed %d\n",
1757 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1758 struct hclge_pkt_buf_alloc
*buf_alloc
)
1760 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1761 struct hclge_rx_com_thrd
*req
;
1762 struct hclge_desc desc
[2];
1763 struct hclge_tc_thrd
*tc
;
1767 for (i
= 0; i
< 2; i
++) {
1768 hclge_cmd_setup_basic_desc(&desc
[i
],
1769 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1770 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1772 /* The first descriptor set the NEXT bit to 1 */
1774 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1776 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1778 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1779 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1781 req
->com_thrd
[j
].high
=
1782 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1783 req
->com_thrd
[j
].high
|=
1784 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1785 HCLGE_RX_PRIV_EN_B
);
1786 req
->com_thrd
[j
].low
=
1787 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1788 req
->com_thrd
[j
].low
|=
1789 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1790 HCLGE_RX_PRIV_EN_B
);
1794 /* Send 2 descriptors at one time */
1795 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1797 dev_err(&hdev
->pdev
->dev
,
1798 "common threshold config cmd failed %d\n", ret
);
1804 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1805 struct hclge_pkt_buf_alloc
*buf_alloc
)
1807 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1808 struct hclge_rx_com_wl
*req
;
1809 struct hclge_desc desc
;
1812 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1814 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1815 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1817 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1818 HCLGE_RX_PRIV_EN_B
);
1820 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1822 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1823 HCLGE_RX_PRIV_EN_B
);
1825 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1827 dev_err(&hdev
->pdev
->dev
,
1828 "common waterline config cmd failed %d\n", ret
);
1835 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1837 struct hclge_pkt_buf_alloc
*pkt_buf
;
1840 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1844 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1846 dev_err(&hdev
->pdev
->dev
,
1847 "could not calc tx buffer size for all TCs %d\n", ret
);
1851 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1853 dev_err(&hdev
->pdev
->dev
,
1854 "could not alloc tx buffers %d\n", ret
);
1858 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1860 dev_err(&hdev
->pdev
->dev
,
1861 "could not calc rx priv buffer size for all TCs %d\n",
1866 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1868 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1873 if (hnae3_dev_dcb_supported(hdev
)) {
1874 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1876 dev_err(&hdev
->pdev
->dev
,
1877 "could not configure rx private waterline %d\n",
1882 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
1884 dev_err(&hdev
->pdev
->dev
,
1885 "could not configure common threshold %d\n",
1891 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
1893 dev_err(&hdev
->pdev
->dev
,
1894 "could not configure common waterline %d\n", ret
);
1901 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
1903 struct hnae3_handle
*roce
= &vport
->roce
;
1904 struct hnae3_handle
*nic
= &vport
->nic
;
1906 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msix
;
1908 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
1909 vport
->back
->num_msi_left
== 0)
1912 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
1914 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
1915 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
1917 roce
->pdev
= nic
->pdev
;
1918 roce
->ae_algo
= nic
->ae_algo
;
1919 roce
->numa_node_mask
= nic
->numa_node_mask
;
1924 static int hclge_init_msix(struct hclge_dev
*hdev
)
1926 struct pci_dev
*pdev
= hdev
->pdev
;
1929 hdev
->msix_entries
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1930 sizeof(struct msix_entry
),
1932 if (!hdev
->msix_entries
)
1935 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1936 sizeof(u16
), GFP_KERNEL
);
1937 if (!hdev
->vector_status
)
1940 for (i
= 0; i
< hdev
->num_msi
; i
++) {
1941 hdev
->msix_entries
[i
].entry
= i
;
1942 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
1945 hdev
->num_msi_left
= hdev
->num_msi
;
1946 hdev
->base_msi_vector
= hdev
->pdev
->irq
;
1947 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
1948 HCLGE_ROCE_VECTOR_OFFSET
;
1950 ret
= pci_enable_msix_range(hdev
->pdev
, hdev
->msix_entries
,
1951 hdev
->num_msi
, hdev
->num_msi
);
1953 dev_info(&hdev
->pdev
->dev
,
1954 "MSI-X vector alloc failed: %d\n", ret
);
1961 static int hclge_init_msi(struct hclge_dev
*hdev
)
1963 struct pci_dev
*pdev
= hdev
->pdev
;
1967 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1968 sizeof(u16
), GFP_KERNEL
);
1969 if (!hdev
->vector_status
)
1972 for (i
= 0; i
< hdev
->num_msi
; i
++)
1973 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
1975 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
, PCI_IRQ_MSI
);
1977 dev_err(&pdev
->dev
, "MSI vectors enable failed %d\n", vectors
);
1980 hdev
->num_msi
= vectors
;
1981 hdev
->num_msi_left
= vectors
;
1982 hdev
->base_msi_vector
= pdev
->irq
;
1983 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
1984 HCLGE_ROCE_VECTOR_OFFSET
;
1989 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
1991 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
1993 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
1994 mac
->duplex
= (u8
)duplex
;
1996 mac
->duplex
= HCLGE_MAC_FULL
;
2001 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2003 struct hclge_config_mac_speed_dup
*req
;
2004 struct hclge_desc desc
;
2007 req
= (struct hclge_config_mac_speed_dup
*)desc
.data
;
2009 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2011 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2014 case HCLGE_MAC_SPEED_10M
:
2015 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2016 HCLGE_CFG_SPEED_S
, 6);
2018 case HCLGE_MAC_SPEED_100M
:
2019 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2020 HCLGE_CFG_SPEED_S
, 7);
2022 case HCLGE_MAC_SPEED_1G
:
2023 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2024 HCLGE_CFG_SPEED_S
, 0);
2026 case HCLGE_MAC_SPEED_10G
:
2027 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2028 HCLGE_CFG_SPEED_S
, 1);
2030 case HCLGE_MAC_SPEED_25G
:
2031 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2032 HCLGE_CFG_SPEED_S
, 2);
2034 case HCLGE_MAC_SPEED_40G
:
2035 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2036 HCLGE_CFG_SPEED_S
, 3);
2038 case HCLGE_MAC_SPEED_50G
:
2039 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2040 HCLGE_CFG_SPEED_S
, 4);
2042 case HCLGE_MAC_SPEED_100G
:
2043 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2044 HCLGE_CFG_SPEED_S
, 5);
2047 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2051 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2054 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2056 dev_err(&hdev
->pdev
->dev
,
2057 "mac speed/duplex config cmd failed %d.\n", ret
);
2061 hclge_check_speed_dup(hdev
, duplex
, speed
);
2066 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2069 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2070 struct hclge_dev
*hdev
= vport
->back
;
2072 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2075 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2078 struct hclge_query_an_speed_dup
*req
;
2079 struct hclge_desc desc
;
2083 req
= (struct hclge_query_an_speed_dup
*)desc
.data
;
2085 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2086 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2088 dev_err(&hdev
->pdev
->dev
,
2089 "mac speed/autoneg/duplex query cmd failed %d\n",
2094 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2095 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2096 HCLGE_QUERY_SPEED_S
);
2098 ret
= hclge_parse_speed(speed_tmp
, speed
);
2100 dev_err(&hdev
->pdev
->dev
,
2101 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2108 static int hclge_query_autoneg_result(struct hclge_dev
*hdev
)
2110 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2111 struct hclge_query_an_speed_dup
*req
;
2112 struct hclge_desc desc
;
2115 req
= (struct hclge_query_an_speed_dup
*)desc
.data
;
2117 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2118 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2120 dev_err(&hdev
->pdev
->dev
,
2121 "autoneg result query cmd failed %d.\n", ret
);
2125 mac
->autoneg
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_AN_B
);
2130 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2132 struct hclge_config_auto_neg
*req
;
2133 struct hclge_desc desc
;
2136 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2138 req
= (struct hclge_config_auto_neg
*)desc
.data
;
2139 hnae_set_bit(req
->cfg_an_cmd_flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2141 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2143 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2151 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2153 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2154 struct hclge_dev
*hdev
= vport
->back
;
2156 return hclge_set_autoneg_en(hdev
, enable
);
2159 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2161 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2162 struct hclge_dev
*hdev
= vport
->back
;
2164 hclge_query_autoneg_result(hdev
);
2166 return hdev
->hw
.mac
.autoneg
;
2169 static int hclge_mac_init(struct hclge_dev
*hdev
)
2171 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2174 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2176 dev_err(&hdev
->pdev
->dev
,
2177 "Config mac speed dup fail ret=%d\n", ret
);
2183 ret
= hclge_mac_mdio_config(hdev
);
2185 dev_warn(&hdev
->pdev
->dev
,
2186 "mdio config fail ret=%d\n", ret
);
2190 /* Initialize the MTA table work mode */
2191 hdev
->accept_mta_mc
= true;
2192 hdev
->enable_mta
= true;
2193 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2195 ret
= hclge_set_mta_filter_mode(hdev
,
2196 hdev
->mta_mac_sel_type
,
2199 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2204 return hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2207 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2209 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2210 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2211 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2212 (void)schedule_work(&hdev
->service_task
);
2215 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2217 struct hclge_link_status
*req
;
2218 struct hclge_desc desc
;
2222 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2223 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2225 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2230 req
= (struct hclge_link_status
*)desc
.data
;
2231 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2233 return !!link_status
;
2236 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2241 mac_state
= hclge_get_mac_link_status(hdev
);
2243 if (hdev
->hw
.mac
.phydev
) {
2244 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2245 link_stat
= mac_state
&
2246 hdev
->hw
.mac
.phydev
->link
;
2251 link_stat
= mac_state
;
2257 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2259 struct hnae3_client
*client
= hdev
->nic_client
;
2260 struct hnae3_handle
*handle
;
2266 state
= hclge_get_mac_phy_link(hdev
);
2267 if (state
!= hdev
->hw
.mac
.link
) {
2268 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2269 handle
= &hdev
->vport
[i
].nic
;
2270 client
->ops
->link_status_change(handle
, state
);
2272 hdev
->hw
.mac
.link
= state
;
2276 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2278 struct hclge_mac mac
= hdev
->hw
.mac
;
2283 /* get the speed and duplex as autoneg'result from mac cmd when phy
2289 /* update mac->antoneg. */
2290 ret
= hclge_query_autoneg_result(hdev
);
2292 dev_err(&hdev
->pdev
->dev
,
2293 "autoneg result query failed %d\n", ret
);
2300 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2302 dev_err(&hdev
->pdev
->dev
,
2303 "mac autoneg/speed/duplex query failed %d\n", ret
);
2307 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2308 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2310 dev_err(&hdev
->pdev
->dev
,
2311 "mac speed/duplex config failed %d\n", ret
);
2319 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2321 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2322 struct hclge_dev
*hdev
= vport
->back
;
2324 return hclge_update_speed_duplex(hdev
);
2327 static int hclge_get_status(struct hnae3_handle
*handle
)
2329 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2330 struct hclge_dev
*hdev
= vport
->back
;
2332 hclge_update_link_status(hdev
);
2334 return hdev
->hw
.mac
.link
;
2337 static void hclge_service_timer(unsigned long data
)
2339 struct hclge_dev
*hdev
= (struct hclge_dev
*)data
;
2340 (void)mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2342 hclge_task_schedule(hdev
);
2345 static void hclge_service_complete(struct hclge_dev
*hdev
)
2347 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2349 /* Flush memory before next watchdog */
2350 smp_mb__before_atomic();
2351 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2354 static void hclge_service_task(struct work_struct
*work
)
2356 struct hclge_dev
*hdev
=
2357 container_of(work
, struct hclge_dev
, service_task
);
2359 hclge_update_speed_duplex(hdev
);
2360 hclge_update_link_status(hdev
);
2361 hclge_update_stats_for_all(hdev
);
2362 hclge_service_complete(hdev
);
2365 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2367 /* If our VFs are assigned we cannot shut down SR-IOV
2368 * without causing issues, so just leave the hardware
2369 * available but disabled
2371 if (pci_vfs_assigned(hdev
->pdev
)) {
2372 dev_warn(&hdev
->pdev
->dev
,
2373 "disabling driver while VFs are assigned\n");
2377 pci_disable_sriov(hdev
->pdev
);
2380 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2382 /* VF handle has no client */
2383 if (!handle
->client
)
2384 return container_of(handle
, struct hclge_vport
, nic
);
2385 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2386 return container_of(handle
, struct hclge_vport
, roce
);
2388 return container_of(handle
, struct hclge_vport
, nic
);
2391 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2392 struct hnae3_vector_info
*vector_info
)
2394 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2395 struct hnae3_vector_info
*vector
= vector_info
;
2396 struct hclge_dev
*hdev
= vport
->back
;
2400 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2402 for (j
= 0; j
< vector_num
; j
++) {
2403 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2404 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2405 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2406 vector
->io_addr
= hdev
->hw
.io_base
+
2407 HCLGE_VECTOR_REG_BASE
+
2408 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2410 HCLGE_VECTOR_VF_OFFSET
;
2411 hdev
->vector_status
[i
] = vport
->vport_id
;
2420 hdev
->num_msi_left
-= alloc
;
2421 hdev
->num_msi_used
+= alloc
;
2426 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2430 for (i
= 0; i
< hdev
->num_msi
; i
++) {
2431 if (hdev
->msix_entries
) {
2432 if (vector
== hdev
->msix_entries
[i
].vector
)
2435 if (vector
== (hdev
->base_msi_vector
+ i
))
2442 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
2444 return HCLGE_RSS_KEY_SIZE
;
2447 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
2449 return HCLGE_RSS_IND_TBL_SIZE
;
2452 static int hclge_get_rss_algo(struct hclge_dev
*hdev
)
2454 struct hclge_rss_config
*req
;
2455 struct hclge_desc desc
;
2459 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
, true);
2461 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2463 dev_err(&hdev
->pdev
->dev
,
2464 "Get link status error, status =%d\n", ret
);
2468 req
= (struct hclge_rss_config
*)desc
.data
;
2469 rss_hash_algo
= (req
->hash_config
& HCLGE_RSS_HASH_ALGO_MASK
);
2471 if (rss_hash_algo
== HCLGE_RSS_HASH_ALGO_TOEPLITZ
)
2472 return ETH_RSS_HASH_TOP
;
2477 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
2478 const u8 hfunc
, const u8
*key
)
2480 struct hclge_rss_config
*req
;
2481 struct hclge_desc desc
;
2486 req
= (struct hclge_rss_config
*)desc
.data
;
2488 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
2489 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
2492 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
2493 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
2495 if (key_offset
== 2)
2497 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
2499 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
2501 memcpy(req
->hash_key
,
2502 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
2504 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2506 dev_err(&hdev
->pdev
->dev
,
2507 "Configure RSS config fail, status = %d\n",
2515 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u32
*indir
)
2517 struct hclge_rss_indirection_table
*req
;
2518 struct hclge_desc desc
;
2522 req
= (struct hclge_rss_indirection_table
*)desc
.data
;
2524 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
2525 hclge_cmd_setup_basic_desc
2526 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
2528 req
->start_table_index
= i
* HCLGE_RSS_CFG_TBL_SIZE
;
2529 req
->rss_set_bitmap
= HCLGE_RSS_SET_BITMAP_MSK
;
2531 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
2532 req
->rss_result
[j
] =
2533 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
2535 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2537 dev_err(&hdev
->pdev
->dev
,
2538 "Configure rss indir table fail,status = %d\n",
2546 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
2547 u16
*tc_size
, u16
*tc_offset
)
2549 struct hclge_rss_tc_mode
*req
;
2550 struct hclge_desc desc
;
2554 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
2555 req
= (struct hclge_rss_tc_mode
*)desc
.data
;
2557 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
2558 hnae_set_bit(req
->rss_tc_mode
[i
], HCLGE_RSS_TC_VALID_B
,
2559 (tc_valid
[i
] & 0x1));
2560 hnae_set_field(req
->rss_tc_mode
[i
], HCLGE_RSS_TC_SIZE_M
,
2561 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
2562 hnae_set_field(req
->rss_tc_mode
[i
], HCLGE_RSS_TC_OFFSET_M
,
2563 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
2566 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2568 dev_err(&hdev
->pdev
->dev
,
2569 "Configure rss tc mode fail, status = %d\n", ret
);
2576 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
2578 #define HCLGE_RSS_INPUT_TUPLE_OTHER 0xf
2579 #define HCLGE_RSS_INPUT_TUPLE_SCTP 0x1f
2580 struct hclge_rss_input_tuple
*req
;
2581 struct hclge_desc desc
;
2584 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
2586 req
= (struct hclge_rss_input_tuple
*)desc
.data
;
2587 req
->ipv4_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2588 req
->ipv4_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2589 req
->ipv4_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
2590 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2591 req
->ipv6_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2592 req
->ipv6_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2593 req
->ipv6_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
2594 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2595 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2597 dev_err(&hdev
->pdev
->dev
,
2598 "Configure rss input fail, status = %d\n", ret
);
2605 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
2608 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2609 struct hclge_dev
*hdev
= vport
->back
;
2612 /* Get hash algorithm */
2614 *hfunc
= hclge_get_rss_algo(hdev
);
2616 /* Get the RSS Key required by the user */
2618 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
2620 /* Get indirect table */
2622 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
2623 indir
[i
] = vport
->rss_indirection_tbl
[i
];
2628 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
2629 const u8
*key
, const u8 hfunc
)
2631 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2632 struct hclge_dev
*hdev
= vport
->back
;
2636 /* Set the RSS Hash Key if specififed by the user */
2638 /* Update the shadow RSS key with user specified qids */
2639 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
2641 if (hfunc
== ETH_RSS_HASH_TOP
||
2642 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
2643 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
2646 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
2651 /* Update the shadow RSS table with user specified qids */
2652 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
2653 vport
->rss_indirection_tbl
[i
] = indir
[i
];
2655 /* Update the hardware */
2656 ret
= hclge_set_rss_indir_table(hdev
, indir
);
2660 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
2662 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2663 struct hclge_dev
*hdev
= vport
->back
;
2665 return hdev
->rss_size_max
;
2668 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
2670 const u8 hfunc
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
2671 struct hclge_vport
*vport
= hdev
->vport
;
2672 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
2673 u8 rss_key
[HCLGE_RSS_KEY_SIZE
];
2674 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
2675 u16 tc_size
[HCLGE_MAX_TC_NUM
];
2676 u32
*rss_indir
= NULL
;
2677 u16 rss_size
= 0, roundup_size
;
2681 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
2685 /* Get default RSS key */
2686 netdev_rss_key_fill(rss_key
, HCLGE_RSS_KEY_SIZE
);
2688 /* Initialize RSS indirect table for each vport */
2689 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
2690 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++) {
2691 vport
[j
].rss_indirection_tbl
[i
] =
2692 i
% vport
[j
].alloc_rss_size
;
2694 /* vport 0 is for PF */
2698 rss_size
= vport
[j
].alloc_rss_size
;
2699 rss_indir
[i
] = vport
[j
].rss_indirection_tbl
[i
];
2702 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
2707 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
2711 ret
= hclge_set_rss_input_tuple(hdev
);
2715 /* Each TC have the same queue size, and tc_size set to hardware is
2716 * the log2 of roundup power of two of rss_size, the acutal queue
2717 * size is limited by indirection table.
2719 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
2720 dev_err(&hdev
->pdev
->dev
,
2721 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
2727 roundup_size
= roundup_pow_of_two(rss_size
);
2728 roundup_size
= ilog2(roundup_size
);
2730 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
2733 if (!(hdev
->hw_tc_map
& BIT(i
)))
2737 tc_size
[i
] = roundup_size
;
2738 tc_offset
[i
] = rss_size
* i
;
2741 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
2749 int hclge_map_vport_ring_to_vector(struct hclge_vport
*vport
, int vector_id
,
2750 struct hnae3_ring_chain_node
*ring_chain
)
2752 struct hclge_dev
*hdev
= vport
->back
;
2753 struct hclge_ctrl_vector_chain
*req
;
2754 struct hnae3_ring_chain_node
*node
;
2755 struct hclge_desc desc
;
2759 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_ADD_RING_TO_VECTOR
, false);
2761 req
= (struct hclge_ctrl_vector_chain
*)desc
.data
;
2762 req
->int_vector_id
= vector_id
;
2765 for (node
= ring_chain
; node
; node
= node
->next
) {
2766 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_INT_TYPE_M
,
2768 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
2769 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_TQP_ID_M
,
2770 HCLGE_TQP_ID_S
, node
->tqp_index
);
2771 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_INT_GL_IDX_M
,
2773 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
2774 req
->tqp_type_and_id
[i
] = cpu_to_le16(req
->tqp_type_and_id
[i
]);
2775 req
->vfid
= vport
->vport_id
;
2777 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
2778 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
2780 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2782 dev_err(&hdev
->pdev
->dev
,
2783 "Map TQP fail, status is %d.\n",
2789 hclge_cmd_setup_basic_desc(&desc
,
2790 HCLGE_OPC_ADD_RING_TO_VECTOR
,
2792 req
->int_vector_id
= vector_id
;
2797 req
->int_cause_num
= i
;
2799 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2801 dev_err(&hdev
->pdev
->dev
,
2802 "Map TQP fail, status is %d.\n", ret
);
2810 int hclge_map_handle_ring_to_vector(struct hnae3_handle
*handle
,
2812 struct hnae3_ring_chain_node
*ring_chain
)
2814 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2815 struct hclge_dev
*hdev
= vport
->back
;
2818 vector_id
= hclge_get_vector_index(hdev
, vector
);
2819 if (vector_id
< 0) {
2820 dev_err(&hdev
->pdev
->dev
,
2821 "Get vector index fail. ret =%d\n", vector_id
);
2825 return hclge_map_vport_ring_to_vector(vport
, vector_id
, ring_chain
);
2828 static int hclge_unmap_ring_from_vector(
2829 struct hnae3_handle
*handle
, int vector
,
2830 struct hnae3_ring_chain_node
*ring_chain
)
2832 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2833 struct hclge_dev
*hdev
= vport
->back
;
2834 struct hclge_ctrl_vector_chain
*req
;
2835 struct hnae3_ring_chain_node
*node
;
2836 struct hclge_desc desc
;
2840 vector_id
= hclge_get_vector_index(hdev
, vector
);
2841 if (vector_id
< 0) {
2842 dev_err(&handle
->pdev
->dev
,
2843 "Get vector index fail. ret =%d\n", vector_id
);
2847 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_DEL_RING_TO_VECTOR
, false);
2849 req
= (struct hclge_ctrl_vector_chain
*)desc
.data
;
2850 req
->int_vector_id
= vector_id
;
2853 for (node
= ring_chain
; node
; node
= node
->next
) {
2854 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_INT_TYPE_M
,
2856 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
2857 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_TQP_ID_M
,
2858 HCLGE_TQP_ID_S
, node
->tqp_index
);
2859 hnae_set_field(req
->tqp_type_and_id
[i
], HCLGE_INT_GL_IDX_M
,
2861 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
2863 req
->tqp_type_and_id
[i
] = cpu_to_le16(req
->tqp_type_and_id
[i
]);
2864 req
->vfid
= vport
->vport_id
;
2866 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
2867 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
2869 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2871 dev_err(&hdev
->pdev
->dev
,
2872 "Unmap TQP fail, status is %d.\n",
2877 hclge_cmd_setup_basic_desc(&desc
,
2878 HCLGE_OPC_DEL_RING_TO_VECTOR
,
2880 req
->int_vector_id
= vector_id
;
2885 req
->int_cause_num
= i
;
2887 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2889 dev_err(&hdev
->pdev
->dev
,
2890 "Unmap TQP fail, status is %d.\n", ret
);
2898 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
2899 struct hclge_promisc_param
*param
)
2901 struct hclge_promisc_cfg
*req
;
2902 struct hclge_desc desc
;
2905 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
2907 req
= (struct hclge_promisc_cfg
*)desc
.data
;
2908 req
->vf_id
= param
->vf_id
;
2909 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
2911 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2913 dev_err(&hdev
->pdev
->dev
,
2914 "Set promisc mode fail, status is %d.\n", ret
);
2920 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
2921 bool en_mc
, bool en_bc
, int vport_id
)
2926 memset(param
, 0, sizeof(struct hclge_promisc_param
));
2928 param
->enable
= HCLGE_PROMISC_EN_UC
;
2930 param
->enable
|= HCLGE_PROMISC_EN_MC
;
2932 param
->enable
|= HCLGE_PROMISC_EN_BC
;
2933 param
->vf_id
= vport_id
;
2936 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
2938 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2939 struct hclge_dev
*hdev
= vport
->back
;
2940 struct hclge_promisc_param param
;
2942 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
2943 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
2946 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
2948 struct hclge_desc desc
;
2949 struct hclge_config_mac_mode
*req
=
2950 (struct hclge_config_mac_mode
*)desc
.data
;
2953 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
2954 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
2955 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
2956 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
2957 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
2958 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_1588_TX_B
, 0);
2959 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_1588_RX_B
, 0);
2960 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_APP_LP_B
, 0);
2961 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
2962 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
2963 hnae_set_bit(req
->txrx_pad_fcs_loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
2964 hnae_set_bit(req
->txrx_pad_fcs_loop_en
,
2965 HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
2966 hnae_set_bit(req
->txrx_pad_fcs_loop_en
,
2967 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
2968 hnae_set_bit(req
->txrx_pad_fcs_loop_en
,
2969 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
2970 hnae_set_bit(req
->txrx_pad_fcs_loop_en
,
2971 HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
2973 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2975 dev_err(&hdev
->pdev
->dev
,
2976 "mac enable fail, ret =%d.\n", ret
);
2979 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
2980 int stream_id
, bool enable
)
2982 struct hclge_desc desc
;
2983 struct hclge_cfg_com_tqp_queue
*req
=
2984 (struct hclge_cfg_com_tqp_queue
*)desc
.data
;
2987 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
2988 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
2989 req
->stream_id
= cpu_to_le16(stream_id
);
2990 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
2992 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2994 dev_err(&hdev
->pdev
->dev
,
2995 "Tqp enable fail, status =%d.\n", ret
);
2999 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3001 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3002 struct hnae3_queue
*queue
;
3003 struct hclge_tqp
*tqp
;
3006 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3007 queue
= handle
->kinfo
.tqp
[i
];
3008 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3009 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3013 static int hclge_ae_start(struct hnae3_handle
*handle
)
3015 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3016 struct hclge_dev
*hdev
= vport
->back
;
3017 int i
, queue_id
, ret
;
3019 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3020 /* todo clear interrupt */
3022 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
3024 dev_warn(&hdev
->pdev
->dev
,
3025 "Get invalid queue id, ignore it\n");
3029 hclge_tqp_enable(hdev
, queue_id
, 0, true);
3032 hclge_cfg_mac_mode(hdev
, true);
3033 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3034 (void)mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3036 ret
= hclge_mac_start_phy(hdev
);
3040 /* reset tqp stats */
3041 hclge_reset_tqp_stats(handle
);
3046 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3048 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3049 struct hclge_dev
*hdev
= vport
->back
;
3052 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3054 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
3056 dev_warn(&hdev
->pdev
->dev
,
3057 "Get invalid queue id, ignore it\n");
3061 hclge_tqp_enable(hdev
, queue_id
, 0, false);
3064 hclge_cfg_mac_mode(hdev
, false);
3066 hclge_mac_stop_phy(hdev
);
3068 /* reset tqp stats */
3069 hclge_reset_tqp_stats(handle
);
3072 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3073 u16 cmdq_resp
, u8 resp_code
,
3074 enum hclge_mac_vlan_tbl_opcode op
)
3076 struct hclge_dev
*hdev
= vport
->back
;
3077 int return_status
= -EIO
;
3080 dev_err(&hdev
->pdev
->dev
,
3081 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3086 if (op
== HCLGE_MAC_VLAN_ADD
) {
3087 if ((!resp_code
) || (resp_code
== 1)) {
3089 } else if (resp_code
== 2) {
3090 return_status
= -EIO
;
3091 dev_err(&hdev
->pdev
->dev
,
3092 "add mac addr failed for uc_overflow.\n");
3093 } else if (resp_code
== 3) {
3094 return_status
= -EIO
;
3095 dev_err(&hdev
->pdev
->dev
,
3096 "add mac addr failed for mc_overflow.\n");
3098 dev_err(&hdev
->pdev
->dev
,
3099 "add mac addr failed for undefined, code=%d.\n",
3102 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3105 } else if (resp_code
== 1) {
3106 return_status
= -EIO
;
3107 dev_dbg(&hdev
->pdev
->dev
,
3108 "remove mac addr failed for miss.\n");
3110 dev_err(&hdev
->pdev
->dev
,
3111 "remove mac addr failed for undefined, code=%d.\n",
3114 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3117 } else if (resp_code
== 1) {
3118 return_status
= -EIO
;
3119 dev_dbg(&hdev
->pdev
->dev
,
3120 "lookup mac addr failed for miss.\n");
3122 dev_err(&hdev
->pdev
->dev
,
3123 "lookup mac addr failed for undefined, code=%d.\n",
3127 return_status
= -EIO
;
3128 dev_err(&hdev
->pdev
->dev
,
3129 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3133 return return_status
;
3136 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3141 if (vfid
> 255 || vfid
< 0)
3144 if (vfid
>= 0 && vfid
<= 191) {
3145 word_num
= vfid
/ 32;
3146 bit_num
= vfid
% 32;
3148 desc
[1].data
[word_num
] &= ~(1 << bit_num
);
3150 desc
[1].data
[word_num
] |= (1 << bit_num
);
3152 word_num
= (vfid
- 192) / 32;
3153 bit_num
= vfid
% 32;
3155 desc
[2].data
[word_num
] &= ~(1 << bit_num
);
3157 desc
[2].data
[word_num
] |= (1 << bit_num
);
3163 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3165 #define HCLGE_DESC_NUMBER 3
3166 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3169 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3170 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3171 if (desc
[i
].data
[j
])
3177 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry
*new_req
,
3180 const unsigned char *mac_addr
= addr
;
3181 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3182 (mac_addr
[0]) | (mac_addr
[1] << 8);
3183 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3185 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3186 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3189 u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3192 u16 high_val
= addr
[1] | (addr
[0] << 8);
3193 struct hclge_dev
*hdev
= vport
->back
;
3194 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3195 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3200 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3201 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3204 struct hclge_mta_filter_mode
*req
;
3205 struct hclge_desc desc
;
3208 req
= (struct hclge_mta_filter_mode
*)desc
.data
;
3209 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3211 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3213 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3214 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3216 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3218 dev_err(&hdev
->pdev
->dev
,
3219 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3227 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3231 struct hclge_cfg_func_mta_filter
*req
;
3232 struct hclge_desc desc
;
3235 req
= (struct hclge_cfg_func_mta_filter
*)desc
.data
;
3236 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3238 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3240 req
->function_id
= func_id
;
3242 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3244 dev_err(&hdev
->pdev
->dev
,
3245 "Config func_id enable failed for cmd_send, ret =%d.\n",
3253 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
3257 struct hclge_dev
*hdev
= vport
->back
;
3258 struct hclge_cfg_func_mta_item
*req
;
3259 struct hclge_desc desc
;
3262 req
= (struct hclge_cfg_func_mta_item
*)desc
.data
;
3263 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
3264 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
3266 hnae_set_field(req
->item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
3267 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
3268 req
->item_idx
= cpu_to_le16(req
->item_idx
);
3270 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3272 dev_err(&hdev
->pdev
->dev
,
3273 "Config mta table item failed for cmd_send, ret =%d.\n",
3281 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
3282 struct hclge_mac_vlan_tbl_entry
*req
)
3284 struct hclge_dev
*hdev
= vport
->back
;
3285 struct hclge_desc desc
;
3289 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
3291 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry
));
3293 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3295 dev_err(&hdev
->pdev
->dev
,
3296 "del mac addr failed for cmd_send, ret =%d.\n",
3300 resp_code
= (desc
.data
[0] >> 8) & 0xff;
3302 return hclge_get_mac_vlan_cmd_status(vport
, desc
.retval
, resp_code
,
3303 HCLGE_MAC_VLAN_REMOVE
);
3306 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
3307 struct hclge_mac_vlan_tbl_entry
*req
,
3308 struct hclge_desc
*desc
,
3311 struct hclge_dev
*hdev
= vport
->back
;
3315 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
3317 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3318 memcpy(desc
[0].data
,
3320 sizeof(struct hclge_mac_vlan_tbl_entry
));
3321 hclge_cmd_setup_basic_desc(&desc
[1],
3322 HCLGE_OPC_MAC_VLAN_ADD
,
3324 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3325 hclge_cmd_setup_basic_desc(&desc
[2],
3326 HCLGE_OPC_MAC_VLAN_ADD
,
3328 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
3330 memcpy(desc
[0].data
,
3332 sizeof(struct hclge_mac_vlan_tbl_entry
));
3333 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
3336 dev_err(&hdev
->pdev
->dev
,
3337 "lookup mac addr failed for cmd_send, ret =%d.\n",
3341 resp_code
= (desc
[0].data
[0] >> 8) & 0xff;
3343 return hclge_get_mac_vlan_cmd_status(vport
, desc
[0].retval
, resp_code
,
3344 HCLGE_MAC_VLAN_LKUP
);
3347 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
3348 struct hclge_mac_vlan_tbl_entry
*req
,
3349 struct hclge_desc
*mc_desc
)
3351 struct hclge_dev
*hdev
= vport
->back
;
3357 struct hclge_desc desc
;
3359 hclge_cmd_setup_basic_desc(&desc
,
3360 HCLGE_OPC_MAC_VLAN_ADD
,
3362 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry
));
3363 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3364 resp_code
= (desc
.data
[0] >> 8) & 0xff;
3365 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, desc
.retval
,
3367 HCLGE_MAC_VLAN_ADD
);
3369 mc_desc
[0].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_WR
);
3370 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3371 mc_desc
[1].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_WR
);
3372 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3373 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_WR
);
3374 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
3375 memcpy(mc_desc
[0].data
, req
,
3376 sizeof(struct hclge_mac_vlan_tbl_entry
));
3377 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
3378 resp_code
= (mc_desc
[0].data
[0] >> 8) & 0xff;
3379 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
,
3382 HCLGE_MAC_VLAN_ADD
);
3386 dev_err(&hdev
->pdev
->dev
,
3387 "add mac addr failed for cmd_send, ret =%d.\n",
3395 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
3396 const unsigned char *addr
)
3398 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3400 return hclge_add_uc_addr_common(vport
, addr
);
3403 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
3404 const unsigned char *addr
)
3406 struct hclge_dev
*hdev
= vport
->back
;
3407 struct hclge_mac_vlan_tbl_entry req
;
3408 enum hclge_cmd_status status
;
3410 /* mac addr check */
3411 if (is_zero_ether_addr(addr
) ||
3412 is_broadcast_ether_addr(addr
) ||
3413 is_multicast_ether_addr(addr
)) {
3414 dev_err(&hdev
->pdev
->dev
,
3415 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3417 is_zero_ether_addr(addr
),
3418 is_broadcast_ether_addr(addr
),
3419 is_multicast_ether_addr(addr
));
3423 memset(&req
, 0, sizeof(req
));
3424 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3425 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3426 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
3427 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3428 hnae_set_bit(req
.egress_port
,
3429 HCLGE_MAC_EPORT_SW_EN_B
, 0);
3430 hnae_set_bit(req
.egress_port
,
3431 HCLGE_MAC_EPORT_TYPE_B
, 0);
3432 hnae_set_field(req
.egress_port
, HCLGE_MAC_EPORT_VFID_M
,
3433 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
3434 hnae_set_field(req
.egress_port
, HCLGE_MAC_EPORT_PFID_M
,
3435 HCLGE_MAC_EPORT_PFID_S
, 0);
3436 req
.egress_port
= cpu_to_le16(req
.egress_port
);
3438 hclge_prepare_mac_addr(&req
, addr
);
3440 status
= hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
3445 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
3446 const unsigned char *addr
)
3448 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3450 return hclge_rm_uc_addr_common(vport
, addr
);
3453 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
3454 const unsigned char *addr
)
3456 struct hclge_dev
*hdev
= vport
->back
;
3457 struct hclge_mac_vlan_tbl_entry req
;
3458 enum hclge_cmd_status status
;
3460 /* mac addr check */
3461 if (is_zero_ether_addr(addr
) ||
3462 is_broadcast_ether_addr(addr
) ||
3463 is_multicast_ether_addr(addr
)) {
3464 dev_dbg(&hdev
->pdev
->dev
,
3465 "Remove mac err! invalid mac:%pM.\n",
3470 memset(&req
, 0, sizeof(req
));
3471 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3472 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3473 hclge_prepare_mac_addr(&req
, addr
);
3474 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
3479 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
3480 const unsigned char *addr
)
3482 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3484 return hclge_add_mc_addr_common(vport
, addr
);
3487 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
3488 const unsigned char *addr
)
3490 struct hclge_dev
*hdev
= vport
->back
;
3491 struct hclge_mac_vlan_tbl_entry req
;
3492 struct hclge_desc desc
[3];
3496 /* mac addr check */
3497 if (!is_multicast_ether_addr(addr
)) {
3498 dev_err(&hdev
->pdev
->dev
,
3499 "Add mc mac err! invalid mac:%pM.\n",
3503 memset(&req
, 0, sizeof(req
));
3504 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3505 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3506 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
3507 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3508 hclge_prepare_mac_addr(&req
, addr
);
3509 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
3511 /* This mac addr exist, update VFID for it */
3512 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
3513 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
3515 /* This mac addr do not exist, add new entry for it */
3516 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
3517 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
3518 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
3519 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
3520 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
3523 /* Set MTA table for this MAC address */
3524 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
3525 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
3530 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
3531 const unsigned char *addr
)
3533 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3535 return hclge_rm_mc_addr_common(vport
, addr
);
3538 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
3539 const unsigned char *addr
)
3541 struct hclge_dev
*hdev
= vport
->back
;
3542 struct hclge_mac_vlan_tbl_entry req
;
3543 enum hclge_cmd_status status
;
3544 struct hclge_desc desc
[3];
3547 /* mac addr check */
3548 if (!is_multicast_ether_addr(addr
)) {
3549 dev_dbg(&hdev
->pdev
->dev
,
3550 "Remove mc mac err! invalid mac:%pM.\n",
3555 memset(&req
, 0, sizeof(req
));
3556 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3557 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3558 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
3559 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3560 hclge_prepare_mac_addr(&req
, addr
);
3561 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
3563 /* This mac addr exist, remove this handle's VFID for it */
3564 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
3566 if (hclge_is_all_function_id_zero(desc
))
3567 /* All the vfid is zero, so need to delete this entry */
3568 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
3570 /* Not all the vfid is zero, update the vfid */
3571 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
3574 /* This mac addr do not exist, can't delete it */
3575 dev_err(&hdev
->pdev
->dev
,
3576 "Rm multicast mac addr failed, ret = %d.\n",
3581 /* Set MTB table for this MAC address */
3582 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
3583 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
3588 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
3590 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3591 struct hclge_dev
*hdev
= vport
->back
;
3593 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
3596 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
)
3598 const unsigned char *new_addr
= (const unsigned char *)p
;
3599 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3600 struct hclge_dev
*hdev
= vport
->back
;
3602 /* mac addr check */
3603 if (is_zero_ether_addr(new_addr
) ||
3604 is_broadcast_ether_addr(new_addr
) ||
3605 is_multicast_ether_addr(new_addr
)) {
3606 dev_err(&hdev
->pdev
->dev
,
3607 "Change uc mac err! invalid mac:%p.\n",
3612 hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
);
3614 if (!hclge_add_uc_addr(handle
, new_addr
)) {
3615 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
3622 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
3625 struct hclge_vlan_filter_ctrl
*req
;
3626 struct hclge_desc desc
;
3629 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
3631 req
= (struct hclge_vlan_filter_ctrl
*)desc
.data
;
3632 req
->vlan_type
= vlan_type
;
3633 req
->vlan_fe
= filter_en
;
3635 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3637 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
3645 int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
3646 bool is_kill
, u16 vlan
, u8 qos
, __be16 proto
)
3648 #define HCLGE_MAX_VF_BYTES 16
3649 struct hclge_vlan_filter_vf_cfg
*req0
;
3650 struct hclge_vlan_filter_vf_cfg
*req1
;
3651 struct hclge_desc desc
[2];
3656 hclge_cmd_setup_basic_desc(&desc
[0],
3657 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
3658 hclge_cmd_setup_basic_desc(&desc
[1],
3659 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
3661 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3663 vf_byte_off
= vfid
/ 8;
3664 vf_byte_val
= 1 << (vfid
% 8);
3666 req0
= (struct hclge_vlan_filter_vf_cfg
*)desc
[0].data
;
3667 req1
= (struct hclge_vlan_filter_vf_cfg
*)desc
[1].data
;
3669 req0
->vlan_id
= vlan
;
3670 req0
->vlan_cfg
= is_kill
;
3672 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
3673 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
3675 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
3677 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
3679 dev_err(&hdev
->pdev
->dev
,
3680 "Send vf vlan command fail, ret =%d.\n",
3686 if (!req0
->resp_code
|| req0
->resp_code
== 1)
3689 dev_err(&hdev
->pdev
->dev
,
3690 "Add vf vlan filter fail, ret =%d.\n",
3693 if (!req0
->resp_code
)
3696 dev_err(&hdev
->pdev
->dev
,
3697 "Kill vf vlan filter fail, ret =%d.\n",
3704 static int hclge_set_port_vlan_filter(struct hnae3_handle
*handle
,
3705 __be16 proto
, u16 vlan_id
,
3708 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3709 struct hclge_dev
*hdev
= vport
->back
;
3710 struct hclge_vlan_filter_pf_cfg
*req
;
3711 struct hclge_desc desc
;
3712 u8 vlan_offset_byte_val
;
3713 u8 vlan_offset_byte
;
3717 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
3719 vlan_offset_160
= vlan_id
/ 160;
3720 vlan_offset_byte
= (vlan_id
% 160) / 8;
3721 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
3723 req
= (struct hclge_vlan_filter_pf_cfg
*)desc
.data
;
3724 req
->vlan_offset
= vlan_offset_160
;
3725 req
->vlan_cfg
= is_kill
;
3726 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
3728 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3730 dev_err(&hdev
->pdev
->dev
,
3731 "port vlan command, send fail, ret =%d.\n",
3736 ret
= hclge_set_vf_vlan_common(hdev
, 0, is_kill
, vlan_id
, 0, proto
);
3738 dev_err(&hdev
->pdev
->dev
,
3739 "Set pf vlan filter config fail, ret =%d.\n",
3747 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
3748 u16 vlan
, u8 qos
, __be16 proto
)
3750 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3751 struct hclge_dev
*hdev
= vport
->back
;
3753 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
3755 if (proto
!= htons(ETH_P_8021Q
))
3756 return -EPROTONOSUPPORT
;
3758 return hclge_set_vf_vlan_common(hdev
, vfid
, false, vlan
, qos
, proto
);
3761 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
3763 #define HCLGE_VLAN_TYPE_VF_TABLE 0
3764 #define HCLGE_VLAN_TYPE_PORT_TABLE 1
3765 struct hnae3_handle
*handle
;
3768 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_VLAN_TYPE_VF_TABLE
,
3773 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_VLAN_TYPE_PORT_TABLE
,
3778 handle
= &hdev
->vport
[0].nic
;
3779 return hclge_set_port_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
3782 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
3784 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3785 struct hclge_config_max_frm_size
*req
;
3786 struct hclge_dev
*hdev
= vport
->back
;
3787 struct hclge_desc desc
;
3790 if ((new_mtu
< HCLGE_MAC_MIN_MTU
) || (new_mtu
> HCLGE_MAC_MAX_MTU
))
3793 hdev
->mps
= new_mtu
;
3794 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
3796 req
= (struct hclge_config_max_frm_size
*)desc
.data
;
3797 req
->max_frm_size
= cpu_to_le16(new_mtu
);
3799 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3801 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
3808 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
3811 struct hclge_reset_tqp_queue
*req
;
3812 struct hclge_desc desc
;
3815 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
3817 req
= (struct hclge_reset_tqp_queue
*)desc
.data
;
3818 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
3819 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
3821 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3823 dev_err(&hdev
->pdev
->dev
,
3824 "Send tqp reset cmd error, status =%d\n", ret
);
3831 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
3833 struct hclge_reset_tqp_queue
*req
;
3834 struct hclge_desc desc
;
3837 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
3839 req
= (struct hclge_reset_tqp_queue
*)desc
.data
;
3840 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
3842 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3844 dev_err(&hdev
->pdev
->dev
,
3845 "Get reset status error, status =%d\n", ret
);
3849 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
3852 static void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
3854 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3855 struct hclge_dev
*hdev
= vport
->back
;
3856 int reset_try_times
= 0;
3860 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
3862 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
3866 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, true);
3868 dev_warn(&hdev
->pdev
->dev
,
3869 "Send reset tqp cmd fail, ret = %d\n", ret
);
3873 reset_try_times
= 0;
3874 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
3875 /* Wait for tqp hw reset */
3877 reset_status
= hclge_get_reset_status(hdev
, queue_id
);
3882 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
3883 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
3887 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, false);
3889 dev_warn(&hdev
->pdev
->dev
,
3890 "Deassert the soft reset fail, ret = %d\n", ret
);
3895 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
3897 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3898 struct hclge_dev
*hdev
= vport
->back
;
3900 return hdev
->fw_version
;
3903 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
3904 u32
*rx_en
, u32
*tx_en
)
3906 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3907 struct hclge_dev
*hdev
= vport
->back
;
3909 *auto_neg
= hclge_get_autoneg(handle
);
3911 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
3917 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
3920 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
3923 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
3932 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
3933 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
3935 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3936 struct hclge_dev
*hdev
= vport
->back
;
3939 *speed
= hdev
->hw
.mac
.speed
;
3941 *duplex
= hdev
->hw
.mac
.duplex
;
3943 *auto_neg
= hdev
->hw
.mac
.autoneg
;
3946 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
3948 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3949 struct hclge_dev
*hdev
= vport
->back
;
3952 *media_type
= hdev
->hw
.mac
.media_type
;
3955 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
3956 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
3958 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3959 struct hclge_dev
*hdev
= vport
->back
;
3960 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
3961 int mdix_ctrl
, mdix
, retval
, is_resolved
;
3964 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
3965 *tp_mdix
= ETH_TP_MDI_INVALID
;
3969 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
3971 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
3972 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
3973 HCLGE_PHY_MDIX_CTRL_S
);
3975 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
3976 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
3977 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
3979 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
3981 switch (mdix_ctrl
) {
3983 *tp_mdix_ctrl
= ETH_TP_MDI
;
3986 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
3989 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
3992 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
3997 *tp_mdix
= ETH_TP_MDI_INVALID
;
3999 *tp_mdix
= ETH_TP_MDI_X
;
4001 *tp_mdix
= ETH_TP_MDI
;
4004 static int hclge_init_client_instance(struct hnae3_client
*client
,
4005 struct hnae3_ae_dev
*ae_dev
)
4007 struct hclge_dev
*hdev
= ae_dev
->priv
;
4008 struct hclge_vport
*vport
;
4011 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4012 vport
= &hdev
->vport
[i
];
4014 switch (client
->type
) {
4015 case HNAE3_CLIENT_KNIC
:
4017 hdev
->nic_client
= client
;
4018 vport
->nic
.client
= client
;
4019 ret
= client
->ops
->init_instance(&vport
->nic
);
4023 if (hdev
->roce_client
&&
4024 hnae3_dev_roce_supported(hdev
)) {
4025 struct hnae3_client
*rc
= hdev
->roce_client
;
4027 ret
= hclge_init_roce_base_info(vport
);
4031 ret
= rc
->ops
->init_instance(&vport
->roce
);
4037 case HNAE3_CLIENT_UNIC
:
4038 hdev
->nic_client
= client
;
4039 vport
->nic
.client
= client
;
4041 ret
= client
->ops
->init_instance(&vport
->nic
);
4046 case HNAE3_CLIENT_ROCE
:
4047 if (hnae3_dev_roce_supported(hdev
)) {
4048 hdev
->roce_client
= client
;
4049 vport
->roce
.client
= client
;
4052 if (hdev
->roce_client
) {
4053 ret
= hclge_init_roce_base_info(vport
);
4057 ret
= client
->ops
->init_instance(&vport
->roce
);
4069 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
4070 struct hnae3_ae_dev
*ae_dev
)
4072 struct hclge_dev
*hdev
= ae_dev
->priv
;
4073 struct hclge_vport
*vport
;
4076 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4077 vport
= &hdev
->vport
[i
];
4078 if (hdev
->roce_client
)
4079 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
4081 if (client
->type
== HNAE3_CLIENT_ROCE
)
4083 if (client
->ops
->uninit_instance
)
4084 client
->ops
->uninit_instance(&vport
->nic
, 0);
4088 static int hclge_pci_init(struct hclge_dev
*hdev
)
4090 struct pci_dev
*pdev
= hdev
->pdev
;
4091 struct hclge_hw
*hw
;
4094 ret
= pci_enable_device(pdev
);
4096 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
4097 goto err_no_drvdata
;
4100 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
4102 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
4105 "can't set consistent PCI DMA");
4106 goto err_disable_device
;
4108 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
4111 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
4113 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
4114 goto err_disable_device
;
4117 pci_set_master(pdev
);
4120 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
4122 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
4124 goto err_clr_master
;
4129 pci_clear_master(pdev
);
4130 pci_release_regions(pdev
);
4132 pci_disable_device(pdev
);
4134 pci_set_drvdata(pdev
, NULL
);
4139 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
4141 struct pci_dev
*pdev
= hdev
->pdev
;
4143 if (hdev
->flag
& HCLGE_FLAG_USE_MSIX
) {
4144 pci_disable_msix(pdev
);
4145 devm_kfree(&pdev
->dev
, hdev
->msix_entries
);
4146 hdev
->msix_entries
= NULL
;
4148 pci_disable_msi(pdev
);
4151 pci_clear_master(pdev
);
4152 pci_release_mem_regions(pdev
);
4153 pci_disable_device(pdev
);
4156 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
4158 struct pci_dev
*pdev
= ae_dev
->pdev
;
4159 struct hclge_dev
*hdev
;
4162 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
4168 hdev
->flag
|= HCLGE_FLAG_USE_MSIX
;
4170 hdev
->ae_dev
= ae_dev
;
4171 ae_dev
->priv
= hdev
;
4173 ret
= hclge_pci_init(hdev
);
4175 dev_err(&pdev
->dev
, "PCI init failed\n");
4179 /* Command queue initialize */
4180 ret
= hclge_cmd_init(hdev
);
4184 ret
= hclge_get_cap(hdev
);
4186 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
4191 ret
= hclge_configure(hdev
);
4193 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
4197 if (hdev
->flag
& HCLGE_FLAG_USE_MSIX
)
4198 ret
= hclge_init_msix(hdev
);
4200 ret
= hclge_init_msi(hdev
);
4202 dev_err(&pdev
->dev
, "Init msix/msi error, ret = %d.\n", ret
);
4206 ret
= hclge_alloc_tqps(hdev
);
4208 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
4212 ret
= hclge_alloc_vport(hdev
);
4214 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
4218 ret
= hclge_mac_init(hdev
);
4220 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
4223 ret
= hclge_buffer_alloc(hdev
);
4225 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
4229 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
4231 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
4235 ret
= hclge_init_vlan_config(hdev
);
4237 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
4241 ret
= hclge_tm_schd_init(hdev
);
4243 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
4247 ret
= hclge_rss_init_hw(hdev
);
4249 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
4253 hclge_dcb_ops_set(hdev
);
4255 setup_timer(&hdev
->service_timer
, hclge_service_timer
,
4256 (unsigned long)hdev
);
4257 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
4259 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
4260 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
4262 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
4266 pci_release_regions(pdev
);
4268 pci_set_drvdata(pdev
, NULL
);
4273 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
4275 struct hclge_dev
*hdev
= ae_dev
->priv
;
4276 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
4278 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
4280 if (IS_ENABLED(CONFIG_PCI_IOV
))
4281 hclge_disable_sriov(hdev
);
4283 if (hdev
->service_timer
.data
)
4284 del_timer_sync(&hdev
->service_timer
);
4285 if (hdev
->service_task
.func
)
4286 cancel_work_sync(&hdev
->service_task
);
4289 mdiobus_unregister(mac
->mdio_bus
);
4291 hclge_destroy_cmd_queue(&hdev
->hw
);
4292 hclge_pci_uninit(hdev
);
4293 ae_dev
->priv
= NULL
;
4296 static const struct hnae3_ae_ops hclge_ops
= {
4297 .init_ae_dev
= hclge_init_ae_dev
,
4298 .uninit_ae_dev
= hclge_uninit_ae_dev
,
4299 .init_client_instance
= hclge_init_client_instance
,
4300 .uninit_client_instance
= hclge_uninit_client_instance
,
4301 .map_ring_to_vector
= hclge_map_handle_ring_to_vector
,
4302 .unmap_ring_from_vector
= hclge_unmap_ring_from_vector
,
4303 .get_vector
= hclge_get_vector
,
4304 .set_promisc_mode
= hclge_set_promisc_mode
,
4305 .start
= hclge_ae_start
,
4306 .stop
= hclge_ae_stop
,
4307 .get_status
= hclge_get_status
,
4308 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
4309 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
4310 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
4311 .get_media_type
= hclge_get_media_type
,
4312 .get_rss_key_size
= hclge_get_rss_key_size
,
4313 .get_rss_indir_size
= hclge_get_rss_indir_size
,
4314 .get_rss
= hclge_get_rss
,
4315 .set_rss
= hclge_set_rss
,
4316 .get_tc_size
= hclge_get_tc_size
,
4317 .get_mac_addr
= hclge_get_mac_addr
,
4318 .set_mac_addr
= hclge_set_mac_addr
,
4319 .add_uc_addr
= hclge_add_uc_addr
,
4320 .rm_uc_addr
= hclge_rm_uc_addr
,
4321 .add_mc_addr
= hclge_add_mc_addr
,
4322 .rm_mc_addr
= hclge_rm_mc_addr
,
4323 .set_autoneg
= hclge_set_autoneg
,
4324 .get_autoneg
= hclge_get_autoneg
,
4325 .get_pauseparam
= hclge_get_pauseparam
,
4326 .set_mtu
= hclge_set_mtu
,
4327 .reset_queue
= hclge_reset_tqp
,
4328 .get_stats
= hclge_get_stats
,
4329 .update_stats
= hclge_update_stats
,
4330 .get_strings
= hclge_get_strings
,
4331 .get_sset_count
= hclge_get_sset_count
,
4332 .get_fw_version
= hclge_get_fw_version
,
4333 .get_mdix_mode
= hclge_get_mdix_mode
,
4334 .set_vlan_filter
= hclge_set_port_vlan_filter
,
4335 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
4338 static struct hnae3_ae_algo ae_algo
= {
4341 .pdev_id_table
= ae_algo_pci_tbl
,
4344 static int hclge_init(void)
4346 pr_info("%s is initializing\n", HCLGE_NAME
);
4348 return hnae3_register_ae_algo(&ae_algo
);
4351 static void hclge_exit(void)
4353 hnae3_unregister_ae_algo(&ae_algo
);
4355 module_init(hclge_init
);
4356 module_exit(hclge_exit
);
4358 MODULE_LICENSE("GPL");
4359 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4360 MODULE_DESCRIPTION("HCLGE Driver");
4361 MODULE_VERSION(HCLGE_MOD_VERSION
);