2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
43 static struct hnae3_ae_algo ae_algo
;
45 static const struct pci_device_id ae_algo_pci_tbl
[] = {
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
53 /* required last entry */
57 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
59 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
61 "Serdes Loopback test",
65 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
104 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
229 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
393 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
395 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
396 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
397 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap
= 0x1,
403 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
405 #define HCLGE_64_BIT_CMD_NUM 5
406 #define HCLGE_64_BIT_RTN_DATANUM 4
407 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
408 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
413 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
414 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
416 dev_err(&hdev
->pdev
->dev
,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
421 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
422 if (unlikely(i
== 0)) {
423 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
424 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
426 desc_data
= (__le64
*)(&desc
[i
]);
427 n
= HCLGE_64_BIT_RTN_DATANUM
;
429 for (k
= 0; k
< n
; k
++) {
430 *data
++ += le64_to_cpu(*desc_data
);
438 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
440 stats
->pkt_curr_buf_cnt
= 0;
441 stats
->pkt_curr_buf_tc0_cnt
= 0;
442 stats
->pkt_curr_buf_tc1_cnt
= 0;
443 stats
->pkt_curr_buf_tc2_cnt
= 0;
444 stats
->pkt_curr_buf_tc3_cnt
= 0;
445 stats
->pkt_curr_buf_tc4_cnt
= 0;
446 stats
->pkt_curr_buf_tc5_cnt
= 0;
447 stats
->pkt_curr_buf_tc6_cnt
= 0;
448 stats
->pkt_curr_buf_tc7_cnt
= 0;
451 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
453 #define HCLGE_32_BIT_CMD_NUM 8
454 #define HCLGE_32_BIT_RTN_DATANUM 8
456 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
457 struct hclge_32_bit_stats
*all_32_bit_stats
;
463 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
464 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
466 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
467 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
469 dev_err(&hdev
->pdev
->dev
,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
475 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
476 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
477 if (unlikely(i
== 0)) {
478 __le16
*desc_data_16bit
;
480 all_32_bit_stats
->igu_rx_err_pkt
+=
481 le32_to_cpu(desc
[i
].data
[0]);
483 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
484 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
485 le16_to_cpu(*desc_data_16bit
);
488 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
489 le16_to_cpu(*desc_data_16bit
);
491 desc_data
= &desc
[i
].data
[2];
492 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
494 desc_data
= (__le32
*)&desc
[i
];
495 n
= HCLGE_32_BIT_RTN_DATANUM
;
497 for (k
= 0; k
< n
; k
++) {
498 *data
++ += le32_to_cpu(*desc_data
);
506 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
508 #define HCLGE_MAC_CMD_NUM 21
509 #define HCLGE_RTN_DATA_NUM 4
511 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
512 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
517 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
518 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
520 dev_err(&hdev
->pdev
->dev
,
521 "Get MAC pkt stats fail, status = %d.\n", ret
);
526 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
527 if (unlikely(i
== 0)) {
528 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
529 n
= HCLGE_RTN_DATA_NUM
- 2;
531 desc_data
= (__le64
*)(&desc
[i
]);
532 n
= HCLGE_RTN_DATA_NUM
;
534 for (k
= 0; k
< n
; k
++) {
535 *data
++ += le64_to_cpu(*desc_data
);
543 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
545 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
546 struct hclge_vport
*vport
= hclge_get_vport(handle
);
547 struct hclge_dev
*hdev
= vport
->back
;
548 struct hnae3_queue
*queue
;
549 struct hclge_desc desc
[1];
550 struct hclge_tqp
*tqp
;
553 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
554 queue
= handle
->kinfo
.tqp
[i
];
555 tqp
= container_of(queue
, struct hclge_tqp
, q
);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc
[0],
558 HCLGE_OPC_QUERY_RX_STATUS
,
561 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
562 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
564 dev_err(&hdev
->pdev
->dev
,
565 "Query tqp stat fail, status = %d,queue = %d\n",
569 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
570 le32_to_cpu(desc
[0].data
[1]);
573 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
574 queue
= handle
->kinfo
.tqp
[i
];
575 tqp
= container_of(queue
, struct hclge_tqp
, q
);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc
[0],
578 HCLGE_OPC_QUERY_TX_STATUS
,
581 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
582 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
584 dev_err(&hdev
->pdev
->dev
,
585 "Query tqp stat fail, status = %d,queue = %d\n",
589 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
590 le32_to_cpu(desc
[0].data
[1]);
596 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
598 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
599 struct hclge_tqp
*tqp
;
603 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
604 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
605 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
608 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
609 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
610 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
616 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
618 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
620 return kinfo
->num_tqps
* (2);
623 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
625 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
629 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
630 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
631 struct hclge_tqp
, q
);
632 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
634 buff
= buff
+ ETH_GSTRING_LEN
;
637 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
638 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
639 struct hclge_tqp
, q
);
640 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
642 buff
= buff
+ ETH_GSTRING_LEN
;
648 static u64
*hclge_comm_get_stats(void *comm_stats
,
649 const struct hclge_comm_stats_str strs
[],
655 for (i
= 0; i
< size
; i
++)
656 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
661 static u8
*hclge_comm_get_strings(u32 stringset
,
662 const struct hclge_comm_stats_str strs
[],
665 char *buff
= (char *)data
;
668 if (stringset
!= ETH_SS_STATS
)
671 for (i
= 0; i
< size
; i
++) {
672 snprintf(buff
, ETH_GSTRING_LEN
,
674 buff
= buff
+ ETH_GSTRING_LEN
;
680 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
681 struct net_device_stats
*net_stats
)
683 net_stats
->tx_dropped
= 0;
684 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
685 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
686 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
688 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
689 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
690 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
691 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
692 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
694 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
695 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
697 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
698 net_stats
->rx_length_errors
=
699 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
700 net_stats
->rx_length_errors
+=
701 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
702 net_stats
->rx_over_errors
=
703 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
706 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
708 struct hnae3_handle
*handle
;
711 handle
= &hdev
->vport
[0].nic
;
712 if (handle
->client
) {
713 status
= hclge_tqps_update_stats(handle
);
715 dev_err(&hdev
->pdev
->dev
,
716 "Update TQPS stats fail, status = %d.\n",
721 status
= hclge_mac_update_stats(hdev
);
723 dev_err(&hdev
->pdev
->dev
,
724 "Update MAC stats fail, status = %d.\n", status
);
726 status
= hclge_32_bit_update_stats(hdev
);
728 dev_err(&hdev
->pdev
->dev
,
729 "Update 32 bit stats fail, status = %d.\n",
732 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
735 static void hclge_update_stats(struct hnae3_handle
*handle
,
736 struct net_device_stats
*net_stats
)
738 struct hclge_vport
*vport
= hclge_get_vport(handle
);
739 struct hclge_dev
*hdev
= vport
->back
;
740 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
746 status
= hclge_mac_update_stats(hdev
);
748 dev_err(&hdev
->pdev
->dev
,
749 "Update MAC stats fail, status = %d.\n",
752 status
= hclge_32_bit_update_stats(hdev
);
754 dev_err(&hdev
->pdev
->dev
,
755 "Update 32 bit stats fail, status = %d.\n",
758 status
= hclge_64_bit_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update 64 bit stats fail, status = %d.\n",
764 status
= hclge_tqps_update_stats(handle
);
766 dev_err(&hdev
->pdev
->dev
,
767 "Update TQPS stats fail, status = %d.\n",
770 hclge_update_netstat(hw_stats
, net_stats
);
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
775 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
777 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
779 struct hclge_vport
*vport
= hclge_get_vport(handle
);
780 struct hclge_dev
*hdev
= vport
->back
;
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
788 if (stringset
== ETH_SS_TEST
) {
789 /* clear loopback bit flags at first */
790 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
791 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
792 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
793 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
795 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
799 } else if (stringset
== ETH_SS_STATS
) {
800 count
= ARRAY_SIZE(g_mac_stats_string
) +
801 ARRAY_SIZE(g_all_32bit_stats_string
) +
802 ARRAY_SIZE(g_all_64bit_stats_string
) +
803 hclge_tqps_get_sset_count(handle
, stringset
);
809 static void hclge_get_strings(struct hnae3_handle
*handle
,
813 u8
*p
= (char *)data
;
816 if (stringset
== ETH_SS_STATS
) {
817 size
= ARRAY_SIZE(g_mac_stats_string
);
818 p
= hclge_comm_get_strings(stringset
,
822 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
823 p
= hclge_comm_get_strings(stringset
,
824 g_all_32bit_stats_string
,
827 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
828 p
= hclge_comm_get_strings(stringset
,
829 g_all_64bit_stats_string
,
832 p
= hclge_tqps_get_strings(handle
, p
);
833 } else if (stringset
== ETH_SS_TEST
) {
834 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
836 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
838 p
+= ETH_GSTRING_LEN
;
840 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
842 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
844 p
+= ETH_GSTRING_LEN
;
846 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
848 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
850 p
+= ETH_GSTRING_LEN
;
855 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
857 struct hclge_vport
*vport
= hclge_get_vport(handle
);
858 struct hclge_dev
*hdev
= vport
->back
;
861 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
863 ARRAY_SIZE(g_mac_stats_string
),
865 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
866 g_all_32bit_stats_string
,
867 ARRAY_SIZE(g_all_32bit_stats_string
),
869 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
870 g_all_64bit_stats_string
,
871 ARRAY_SIZE(g_all_64bit_stats_string
),
873 p
= hclge_tqps_get_stats(handle
, p
);
876 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
877 struct hclge_func_status_cmd
*status
)
879 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
882 /* Set the pf to main pf */
883 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
884 hdev
->flag
|= HCLGE_FLAG_MAIN
;
886 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
891 static int hclge_query_function_status(struct hclge_dev
*hdev
)
893 struct hclge_func_status_cmd
*req
;
894 struct hclge_desc desc
;
898 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
899 req
= (struct hclge_func_status_cmd
*)desc
.data
;
902 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
904 dev_err(&hdev
->pdev
->dev
,
905 "query function status failed %d.\n",
911 /* Check pf reset is done */
914 usleep_range(1000, 2000);
915 } while (timeout
++ < 5);
917 ret
= hclge_parse_func_status(hdev
, req
);
922 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
924 struct hclge_pf_res_cmd
*req
;
925 struct hclge_desc desc
;
928 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
929 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
931 dev_err(&hdev
->pdev
->dev
,
932 "query pf resource failed %d.\n", ret
);
936 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
937 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
938 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
940 if (hnae3_dev_roce_supported(hdev
)) {
942 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
943 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
945 /* PF should have NIC vectors and Roce vectors,
946 * NIC vectors are queued before Roce vectors.
948 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
951 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
952 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
958 static int hclge_parse_speed(int speed_cmd
, int *speed
)
962 *speed
= HCLGE_MAC_SPEED_10M
;
965 *speed
= HCLGE_MAC_SPEED_100M
;
968 *speed
= HCLGE_MAC_SPEED_1G
;
971 *speed
= HCLGE_MAC_SPEED_10G
;
974 *speed
= HCLGE_MAC_SPEED_25G
;
977 *speed
= HCLGE_MAC_SPEED_40G
;
980 *speed
= HCLGE_MAC_SPEED_50G
;
983 *speed
= HCLGE_MAC_SPEED_100G
;
992 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
995 unsigned long *supported
= hdev
->hw
.mac
.supported
;
997 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
998 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1001 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1002 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1005 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1006 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1009 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1010 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1013 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1014 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1017 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1018 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1021 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1023 u8 media_type
= hdev
->hw
.mac
.media_type
;
1025 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1028 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1031 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1033 struct hclge_cfg_param_cmd
*req
;
1034 u64 mac_addr_tmp_high
;
1038 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1040 /* get the configuration */
1041 cfg
->vmdq_vport_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1044 cfg
->tc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1045 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1046 cfg
->tqp_desc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1047 HCLGE_CFG_TQP_DESC_N_M
,
1048 HCLGE_CFG_TQP_DESC_N_S
);
1050 cfg
->phy_addr
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1051 HCLGE_CFG_PHY_ADDR_M
,
1052 HCLGE_CFG_PHY_ADDR_S
);
1053 cfg
->media_type
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1054 HCLGE_CFG_MEDIA_TP_M
,
1055 HCLGE_CFG_MEDIA_TP_S
);
1056 cfg
->rx_buf_len
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1057 HCLGE_CFG_RX_BUF_LEN_M
,
1058 HCLGE_CFG_RX_BUF_LEN_S
);
1059 /* get mac_address */
1060 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1061 mac_addr_tmp_high
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1062 HCLGE_CFG_MAC_ADDR_H_M
,
1063 HCLGE_CFG_MAC_ADDR_H_S
);
1065 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1067 cfg
->default_speed
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1068 HCLGE_CFG_DEFAULT_SPEED_M
,
1069 HCLGE_CFG_DEFAULT_SPEED_S
);
1070 cfg
->rss_size_max
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1071 HCLGE_CFG_RSS_SIZE_M
,
1072 HCLGE_CFG_RSS_SIZE_S
);
1074 for (i
= 0; i
< ETH_ALEN
; i
++)
1075 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1077 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1078 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1080 cfg
->speed_ability
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1081 HCLGE_CFG_SPEED_ABILITY_M
,
1082 HCLGE_CFG_SPEED_ABILITY_S
);
1085 /* hclge_get_cfg: query the static parameter from flash
1086 * @hdev: pointer to struct hclge_dev
1087 * @hcfg: the config structure to be getted
1089 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1091 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1092 struct hclge_cfg_param_cmd
*req
;
1095 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1098 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1099 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1101 hnae3_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1102 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1103 /* Len should be united by 4 bytes when send to hardware */
1104 hnae3_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1105 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1106 req
->offset
= cpu_to_le32(offset
);
1109 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1111 dev_err(&hdev
->pdev
->dev
,
1112 "get config failed %d.\n", ret
);
1116 hclge_parse_cfg(hcfg
, desc
);
1120 static int hclge_get_cap(struct hclge_dev
*hdev
)
1124 ret
= hclge_query_function_status(hdev
);
1126 dev_err(&hdev
->pdev
->dev
,
1127 "query function status error %d.\n", ret
);
1131 /* get pf resource */
1132 ret
= hclge_query_pf_resource(hdev
);
1134 dev_err(&hdev
->pdev
->dev
,
1135 "query pf resource error %d.\n", ret
);
1142 static int hclge_configure(struct hclge_dev
*hdev
)
1144 struct hclge_cfg cfg
;
1147 ret
= hclge_get_cfg(hdev
, &cfg
);
1149 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1153 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1154 hdev
->base_tqp_pid
= 0;
1155 hdev
->rss_size_max
= cfg
.rss_size_max
;
1156 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1157 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1158 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1159 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1160 hdev
->num_desc
= cfg
.tqp_desc_num
;
1161 hdev
->tm_info
.num_pg
= 1;
1162 hdev
->tc_max
= cfg
.tc_num
;
1163 hdev
->tm_info
.hw_pfc_map
= 0;
1165 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1167 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1171 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1173 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1174 (hdev
->tc_max
< 1)) {
1175 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1180 /* Dev does not support DCB */
1181 if (!hnae3_dev_dcb_supported(hdev
)) {
1185 hdev
->pfc_max
= hdev
->tc_max
;
1188 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1190 /* Currently not support uncontiuous tc */
1191 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1192 hnae3_set_bit(hdev
->hw_tc_map
, i
, 1);
1194 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1199 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1202 struct hclge_cfg_tso_status_cmd
*req
;
1203 struct hclge_desc desc
;
1206 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1208 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1211 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1212 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1213 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1216 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1217 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1218 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1220 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1223 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1225 struct hclge_tqp
*tqp
;
1228 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1229 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1235 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1236 tqp
->dev
= &hdev
->pdev
->dev
;
1239 tqp
->q
.ae_algo
= &ae_algo
;
1240 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1241 tqp
->q
.desc_num
= hdev
->num_desc
;
1242 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1243 i
* HCLGE_TQP_REG_SIZE
;
1251 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1252 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1254 struct hclge_tqp_map_cmd
*req
;
1255 struct hclge_desc desc
;
1258 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1260 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1261 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1262 req
->tqp_vf
= func_id
;
1263 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1264 1 << HCLGE_TQP_MAP_EN_B
;
1265 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1267 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1269 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1277 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1278 struct hnae3_queue
**tqp
, u16 num_tqps
)
1280 struct hclge_dev
*hdev
= vport
->back
;
1283 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1284 alloced
< num_tqps
; i
++) {
1285 if (!hdev
->htqp
[i
].alloced
) {
1286 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1287 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1288 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1289 hdev
->htqp
[i
].alloced
= true;
1293 vport
->alloc_tqps
= num_tqps
;
1298 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1300 struct hnae3_handle
*nic
= &vport
->nic
;
1301 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1302 struct hclge_dev
*hdev
= vport
->back
;
1305 kinfo
->num_desc
= hdev
->num_desc
;
1306 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1307 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1309 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1310 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1312 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1313 if (hdev
->hw_tc_map
& BIT(i
)) {
1314 kinfo
->tc_info
[i
].enable
= true;
1315 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1316 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1317 kinfo
->tc_info
[i
].tc
= i
;
1319 /* Set to default queue if TC is disable */
1320 kinfo
->tc_info
[i
].enable
= false;
1321 kinfo
->tc_info
[i
].tqp_offset
= 0;
1322 kinfo
->tc_info
[i
].tqp_count
= 1;
1323 kinfo
->tc_info
[i
].tc
= 0;
1327 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1328 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1332 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1334 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1341 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1342 struct hclge_vport
*vport
)
1344 struct hnae3_handle
*nic
= &vport
->nic
;
1345 struct hnae3_knic_private_info
*kinfo
;
1348 kinfo
= &nic
->kinfo
;
1349 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1350 struct hclge_tqp
*q
=
1351 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1355 is_pf
= !(vport
->vport_id
);
1356 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1365 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1367 struct hclge_vport
*vport
= hdev
->vport
;
1370 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1371 for (i
= 0; i
< num_vport
; i
++) {
1374 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1384 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1386 /* this would be initialized later */
1389 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1391 struct hnae3_handle
*nic
= &vport
->nic
;
1392 struct hclge_dev
*hdev
= vport
->back
;
1395 nic
->pdev
= hdev
->pdev
;
1396 nic
->ae_algo
= &ae_algo
;
1397 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1399 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1400 ret
= hclge_knic_setup(vport
, num_tqps
);
1402 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1407 hclge_unic_setup(vport
, num_tqps
);
1413 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1415 struct pci_dev
*pdev
= hdev
->pdev
;
1416 struct hclge_vport
*vport
;
1422 /* We need to alloc a vport for main NIC of PF */
1423 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1425 if (hdev
->num_tqps
< num_vport
) {
1426 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1427 hdev
->num_tqps
, num_vport
);
1431 /* Alloc the same number of TQPs for every vport */
1432 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1433 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1435 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1440 hdev
->vport
= vport
;
1441 hdev
->num_alloc_vport
= num_vport
;
1443 if (IS_ENABLED(CONFIG_PCI_IOV
))
1444 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1446 for (i
= 0; i
< num_vport
; i
++) {
1448 vport
->vport_id
= i
;
1451 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1453 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1456 "vport setup failed for vport %d, %d\n",
1467 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1468 struct hclge_pkt_buf_alloc
*buf_alloc
)
1470 /* TX buffer size is unit by 128 byte */
1471 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1472 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1473 struct hclge_tx_buff_alloc_cmd
*req
;
1474 struct hclge_desc desc
;
1478 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1480 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1481 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1482 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1484 req
->tx_pkt_buff
[i
] =
1485 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1486 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1489 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1491 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1499 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1500 struct hclge_pkt_buf_alloc
*buf_alloc
)
1502 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1505 dev_err(&hdev
->pdev
->dev
,
1506 "tx buffer alloc failed %d\n", ret
);
1513 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1517 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1518 if (hdev
->hw_tc_map
& BIT(i
))
1523 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1527 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1528 if (hdev
->hw_tc_map
& BIT(i
) &&
1529 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1534 /* Get the number of pfc enabled TCs, which have private buffer */
1535 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1536 struct hclge_pkt_buf_alloc
*buf_alloc
)
1538 struct hclge_priv_buf
*priv
;
1541 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1542 priv
= &buf_alloc
->priv_buf
[i
];
1543 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1551 /* Get the number of pfc disabled TCs, which have private buffer */
1552 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1553 struct hclge_pkt_buf_alloc
*buf_alloc
)
1555 struct hclge_priv_buf
*priv
;
1558 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1559 priv
= &buf_alloc
->priv_buf
[i
];
1560 if (hdev
->hw_tc_map
& BIT(i
) &&
1561 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1569 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1571 struct hclge_priv_buf
*priv
;
1575 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1576 priv
= &buf_alloc
->priv_buf
[i
];
1578 rx_priv
+= priv
->buf_size
;
1583 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1585 u32 i
, total_tx_size
= 0;
1587 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1588 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1590 return total_tx_size
;
1593 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1594 struct hclge_pkt_buf_alloc
*buf_alloc
,
1597 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1598 int tc_num
, pfc_enable_num
;
1603 tc_num
= hclge_get_tc_num(hdev
);
1604 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1606 if (hnae3_dev_dcb_supported(hdev
))
1607 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1609 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1611 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1612 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1614 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1616 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1617 if (rx_all
<= rx_priv
+ shared_std
)
1620 shared_buf
= rx_all
- rx_priv
;
1621 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1622 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1623 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1625 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1626 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1627 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1628 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1629 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1631 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1632 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1639 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1640 struct hclge_pkt_buf_alloc
*buf_alloc
)
1644 total_size
= hdev
->pkt_buf_size
;
1646 /* alloc tx buffer for all enabled tc */
1647 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1648 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1650 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1653 if (hdev
->hw_tc_map
& BIT(i
))
1654 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1656 priv
->tx_buf_size
= 0;
1658 total_size
-= priv
->tx_buf_size
;
1664 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1665 * @hdev: pointer to struct hclge_dev
1666 * @buf_alloc: pointer to buffer calculation data
1667 * @return: 0: calculate sucessful, negative: fail
1669 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1670 struct hclge_pkt_buf_alloc
*buf_alloc
)
1672 u32 rx_all
= hdev
->pkt_buf_size
;
1673 int no_pfc_priv_num
, pfc_priv_num
;
1674 struct hclge_priv_buf
*priv
;
1677 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1679 /* When DCB is not supported, rx private
1680 * buffer is not allocated.
1682 if (!hnae3_dev_dcb_supported(hdev
)) {
1683 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1689 /* step 1, try to alloc private buffer for all enabled tc */
1690 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1691 priv
= &buf_alloc
->priv_buf
[i
];
1692 if (hdev
->hw_tc_map
& BIT(i
)) {
1694 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1695 priv
->wl
.low
= hdev
->mps
;
1696 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1697 priv
->buf_size
= priv
->wl
.high
+
1701 priv
->wl
.high
= 2 * hdev
->mps
;
1702 priv
->buf_size
= priv
->wl
.high
;
1712 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1715 /* step 2, try to decrease the buffer size of
1716 * no pfc TC's private buffer
1718 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1719 priv
= &buf_alloc
->priv_buf
[i
];
1726 if (!(hdev
->hw_tc_map
& BIT(i
)))
1731 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1733 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1734 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1737 priv
->wl
.high
= hdev
->mps
;
1738 priv
->buf_size
= priv
->wl
.high
;
1742 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1745 /* step 3, try to reduce the number of pfc disabled TCs,
1746 * which have private buffer
1748 /* get the total no pfc enable TC number, which have private buffer */
1749 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1751 /* let the last to be cleared first */
1752 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1753 priv
= &buf_alloc
->priv_buf
[i
];
1755 if (hdev
->hw_tc_map
& BIT(i
) &&
1756 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1757 /* Clear the no pfc TC private buffer */
1765 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1766 no_pfc_priv_num
== 0)
1770 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1773 /* step 4, try to reduce the number of pfc enabled TCs
1774 * which have private buffer.
1776 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1778 /* let the last to be cleared first */
1779 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1780 priv
= &buf_alloc
->priv_buf
[i
];
1782 if (hdev
->hw_tc_map
& BIT(i
) &&
1783 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1784 /* Reduce the number of pfc TC with private buffer */
1792 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1796 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1802 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1803 struct hclge_pkt_buf_alloc
*buf_alloc
)
1805 struct hclge_rx_priv_buff_cmd
*req
;
1806 struct hclge_desc desc
;
1810 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1811 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1813 /* Alloc private buffer TCs */
1814 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1815 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1818 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1820 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1824 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1825 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1827 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1829 dev_err(&hdev
->pdev
->dev
,
1830 "rx private buffer alloc cmd failed %d\n", ret
);
1837 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1838 struct hclge_pkt_buf_alloc
*buf_alloc
)
1840 struct hclge_rx_priv_wl_buf
*req
;
1841 struct hclge_priv_buf
*priv
;
1842 struct hclge_desc desc
[2];
1846 for (i
= 0; i
< 2; i
++) {
1847 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1849 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1851 /* The first descriptor set the NEXT bit to 1 */
1853 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1855 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1857 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1858 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1860 priv
= &buf_alloc
->priv_buf
[idx
];
1861 req
->tc_wl
[j
].high
=
1862 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1863 req
->tc_wl
[j
].high
|=
1864 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1866 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1867 req
->tc_wl
[j
].low
|=
1868 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1872 /* Send 2 descriptor at one time */
1873 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1875 dev_err(&hdev
->pdev
->dev
,
1876 "rx private waterline config cmd failed %d\n",
1883 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1884 struct hclge_pkt_buf_alloc
*buf_alloc
)
1886 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1887 struct hclge_rx_com_thrd
*req
;
1888 struct hclge_desc desc
[2];
1889 struct hclge_tc_thrd
*tc
;
1893 for (i
= 0; i
< 2; i
++) {
1894 hclge_cmd_setup_basic_desc(&desc
[i
],
1895 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1896 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1898 /* The first descriptor set the NEXT bit to 1 */
1900 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1902 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1904 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1905 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1907 req
->com_thrd
[j
].high
=
1908 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1909 req
->com_thrd
[j
].high
|=
1910 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1911 req
->com_thrd
[j
].low
=
1912 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1913 req
->com_thrd
[j
].low
|=
1914 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1918 /* Send 2 descriptors at one time */
1919 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1921 dev_err(&hdev
->pdev
->dev
,
1922 "common threshold config cmd failed %d\n", ret
);
1928 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1929 struct hclge_pkt_buf_alloc
*buf_alloc
)
1931 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1932 struct hclge_rx_com_wl
*req
;
1933 struct hclge_desc desc
;
1936 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1938 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1939 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1940 req
->com_wl
.high
|= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1942 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1943 req
->com_wl
.low
|= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1945 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1947 dev_err(&hdev
->pdev
->dev
,
1948 "common waterline config cmd failed %d\n", ret
);
1955 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1957 struct hclge_pkt_buf_alloc
*pkt_buf
;
1960 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1964 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1966 dev_err(&hdev
->pdev
->dev
,
1967 "could not calc tx buffer size for all TCs %d\n", ret
);
1971 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1973 dev_err(&hdev
->pdev
->dev
,
1974 "could not alloc tx buffers %d\n", ret
);
1978 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1980 dev_err(&hdev
->pdev
->dev
,
1981 "could not calc rx priv buffer size for all TCs %d\n",
1986 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1988 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1993 if (hnae3_dev_dcb_supported(hdev
)) {
1994 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1996 dev_err(&hdev
->pdev
->dev
,
1997 "could not configure rx private waterline %d\n",
2002 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
2004 dev_err(&hdev
->pdev
->dev
,
2005 "could not configure common threshold %d\n",
2011 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2013 dev_err(&hdev
->pdev
->dev
,
2014 "could not configure common waterline %d\n", ret
);
2021 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2023 struct hnae3_handle
*roce
= &vport
->roce
;
2024 struct hnae3_handle
*nic
= &vport
->nic
;
2026 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2028 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2029 vport
->back
->num_msi_left
== 0)
2032 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2034 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2035 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2037 roce
->pdev
= nic
->pdev
;
2038 roce
->ae_algo
= nic
->ae_algo
;
2039 roce
->numa_node_mask
= nic
->numa_node_mask
;
2044 static int hclge_init_msi(struct hclge_dev
*hdev
)
2046 struct pci_dev
*pdev
= hdev
->pdev
;
2050 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2051 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2054 "failed(%d) to allocate MSI/MSI-X vectors\n",
2058 if (vectors
< hdev
->num_msi
)
2059 dev_warn(&hdev
->pdev
->dev
,
2060 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2061 hdev
->num_msi
, vectors
);
2063 hdev
->num_msi
= vectors
;
2064 hdev
->num_msi_left
= vectors
;
2065 hdev
->base_msi_vector
= pdev
->irq
;
2066 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2067 HCLGE_ROCE_VECTOR_OFFSET
;
2069 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2070 sizeof(u16
), GFP_KERNEL
);
2071 if (!hdev
->vector_status
) {
2072 pci_free_irq_vectors(pdev
);
2076 for (i
= 0; i
< hdev
->num_msi
; i
++)
2077 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2079 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2080 sizeof(int), GFP_KERNEL
);
2081 if (!hdev
->vector_irq
) {
2082 pci_free_irq_vectors(pdev
);
2089 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2091 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2093 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2094 mac
->duplex
= (u8
)duplex
;
2096 mac
->duplex
= HCLGE_MAC_FULL
;
2101 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2103 struct hclge_config_mac_speed_dup_cmd
*req
;
2104 struct hclge_desc desc
;
2107 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2109 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2111 hnae3_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2114 case HCLGE_MAC_SPEED_10M
:
2115 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2116 HCLGE_CFG_SPEED_S
, 6);
2118 case HCLGE_MAC_SPEED_100M
:
2119 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2120 HCLGE_CFG_SPEED_S
, 7);
2122 case HCLGE_MAC_SPEED_1G
:
2123 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2124 HCLGE_CFG_SPEED_S
, 0);
2126 case HCLGE_MAC_SPEED_10G
:
2127 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2128 HCLGE_CFG_SPEED_S
, 1);
2130 case HCLGE_MAC_SPEED_25G
:
2131 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2132 HCLGE_CFG_SPEED_S
, 2);
2134 case HCLGE_MAC_SPEED_40G
:
2135 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2136 HCLGE_CFG_SPEED_S
, 3);
2138 case HCLGE_MAC_SPEED_50G
:
2139 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2140 HCLGE_CFG_SPEED_S
, 4);
2142 case HCLGE_MAC_SPEED_100G
:
2143 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2144 HCLGE_CFG_SPEED_S
, 5);
2147 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2151 hnae3_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2154 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2156 dev_err(&hdev
->pdev
->dev
,
2157 "mac speed/duplex config cmd failed %d.\n", ret
);
2161 hclge_check_speed_dup(hdev
, duplex
, speed
);
2166 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2169 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2170 struct hclge_dev
*hdev
= vport
->back
;
2172 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2175 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2178 struct hclge_query_an_speed_dup_cmd
*req
;
2179 struct hclge_desc desc
;
2183 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2185 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2186 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2188 dev_err(&hdev
->pdev
->dev
,
2189 "mac speed/autoneg/duplex query cmd failed %d\n",
2194 *duplex
= hnae3_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2195 speed_tmp
= hnae3_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2196 HCLGE_QUERY_SPEED_S
);
2198 ret
= hclge_parse_speed(speed_tmp
, speed
);
2200 dev_err(&hdev
->pdev
->dev
,
2201 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2208 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2210 struct hclge_config_auto_neg_cmd
*req
;
2211 struct hclge_desc desc
;
2215 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2217 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2218 hnae3_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2219 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2221 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2223 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2231 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2233 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2234 struct hclge_dev
*hdev
= vport
->back
;
2236 return hclge_set_autoneg_en(hdev
, enable
);
2239 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2241 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2242 struct hclge_dev
*hdev
= vport
->back
;
2243 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2246 return phydev
->autoneg
;
2248 return hdev
->hw
.mac
.autoneg
;
2251 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2255 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2256 struct hclge_desc desc
;
2259 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2260 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2262 hnae3_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2264 ether_addr_copy(req
->mac_mask
, mac_mask
);
2266 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2268 dev_err(&hdev
->pdev
->dev
,
2269 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2275 static int hclge_mac_init(struct hclge_dev
*hdev
)
2277 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2278 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2279 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2280 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2281 struct hclge_vport
*vport
;
2286 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2288 dev_err(&hdev
->pdev
->dev
,
2289 "Config mac speed dup fail ret=%d\n", ret
);
2295 /* Initialize the MTA table work mode */
2296 hdev
->enable_mta
= true;
2297 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2299 ret
= hclge_set_mta_filter_mode(hdev
,
2300 hdev
->mta_mac_sel_type
,
2303 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2308 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
2309 vport
= &hdev
->vport
[i
];
2310 vport
->accept_mta_mc
= false;
2312 memset(vport
->mta_shadow
, 0, sizeof(vport
->mta_shadow
));
2313 ret
= hclge_cfg_func_mta_filter(hdev
, vport
->vport_id
, false);
2315 dev_err(&hdev
->pdev
->dev
,
2316 "set mta filter mode fail ret=%d\n", ret
);
2321 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2323 dev_err(&hdev
->pdev
->dev
,
2324 "set default mac_vlan_mask fail ret=%d\n", ret
);
2333 ret
= hclge_set_mtu(handle
, mtu
);
2335 dev_err(&hdev
->pdev
->dev
,
2336 "set mtu failed ret=%d\n", ret
);
2343 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2345 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2346 schedule_work(&hdev
->mbx_service_task
);
2349 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2351 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2352 schedule_work(&hdev
->rst_service_task
);
2355 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2357 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2358 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2359 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2360 (void)schedule_work(&hdev
->service_task
);
2363 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2365 struct hclge_link_status_cmd
*req
;
2366 struct hclge_desc desc
;
2370 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2371 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2373 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2378 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2379 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2381 return !!link_status
;
2384 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2389 mac_state
= hclge_get_mac_link_status(hdev
);
2391 if (hdev
->hw
.mac
.phydev
) {
2392 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2393 link_stat
= mac_state
&
2394 hdev
->hw
.mac
.phydev
->link
;
2399 link_stat
= mac_state
;
2405 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2407 struct hnae3_client
*rclient
= hdev
->roce_client
;
2408 struct hnae3_client
*client
= hdev
->nic_client
;
2409 struct hnae3_handle
*rhandle
;
2410 struct hnae3_handle
*handle
;
2416 state
= hclge_get_mac_phy_link(hdev
);
2417 if (state
!= hdev
->hw
.mac
.link
) {
2418 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2419 handle
= &hdev
->vport
[i
].nic
;
2420 client
->ops
->link_status_change(handle
, state
);
2421 rhandle
= &hdev
->vport
[i
].roce
;
2422 if (rclient
&& rclient
->ops
->link_status_change
)
2423 rclient
->ops
->link_status_change(rhandle
,
2426 hdev
->hw
.mac
.link
= state
;
2430 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2432 struct hclge_mac mac
= hdev
->hw
.mac
;
2437 /* get the speed and duplex as autoneg'result from mac cmd when phy
2440 if (mac
.phydev
|| !mac
.autoneg
)
2443 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2445 dev_err(&hdev
->pdev
->dev
,
2446 "mac autoneg/speed/duplex query failed %d\n", ret
);
2450 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2451 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2453 dev_err(&hdev
->pdev
->dev
,
2454 "mac speed/duplex config failed %d\n", ret
);
2462 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2464 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2465 struct hclge_dev
*hdev
= vport
->back
;
2467 return hclge_update_speed_duplex(hdev
);
2470 static int hclge_get_status(struct hnae3_handle
*handle
)
2472 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2473 struct hclge_dev
*hdev
= vport
->back
;
2475 hclge_update_link_status(hdev
);
2477 return hdev
->hw
.mac
.link
;
2480 static void hclge_service_timer(struct timer_list
*t
)
2482 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2484 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2485 hdev
->hw_stats
.stats_timer
++;
2486 hclge_task_schedule(hdev
);
2489 static void hclge_service_complete(struct hclge_dev
*hdev
)
2491 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2493 /* Flush memory before next watchdog */
2494 smp_mb__before_atomic();
2495 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2498 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2503 /* fetch the events from their corresponding regs */
2504 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2505 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2507 /* Assumption: If by any chance reset and mailbox events are reported
2508 * together then we will only process reset event in this go and will
2509 * defer the processing of the mailbox events. Since, we would have not
2510 * cleared RX CMDQ event this time we would receive again another
2511 * interrupt from H/W just for the mailbox.
2514 /* check for vector0 reset event sources */
2515 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2516 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2517 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2518 return HCLGE_VECTOR0_EVENT_RST
;
2521 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2522 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2523 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2524 return HCLGE_VECTOR0_EVENT_RST
;
2527 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2528 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2529 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2530 return HCLGE_VECTOR0_EVENT_RST
;
2533 /* check for vector0 mailbox(=CMDQ RX) event source */
2534 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2535 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2536 *clearval
= cmdq_src_reg
;
2537 return HCLGE_VECTOR0_EVENT_MBX
;
2540 return HCLGE_VECTOR0_EVENT_OTHER
;
2543 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2546 switch (event_type
) {
2547 case HCLGE_VECTOR0_EVENT_RST
:
2548 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2550 case HCLGE_VECTOR0_EVENT_MBX
:
2551 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2556 static void hclge_clear_all_event_cause(struct hclge_dev
*hdev
)
2558 hclge_clear_event_cause(hdev
, HCLGE_VECTOR0_EVENT_RST
,
2559 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) |
2560 BIT(HCLGE_VECTOR0_CORERESET_INT_B
) |
2561 BIT(HCLGE_VECTOR0_IMPRESET_INT_B
));
2562 hclge_clear_event_cause(hdev
, HCLGE_VECTOR0_EVENT_MBX
, 0);
2565 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2567 writel(enable
? 1 : 0, vector
->addr
);
2570 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2572 struct hclge_dev
*hdev
= data
;
2576 hclge_enable_vector(&hdev
->misc_vector
, false);
2577 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2579 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2580 switch (event_cause
) {
2581 case HCLGE_VECTOR0_EVENT_RST
:
2582 hclge_reset_task_schedule(hdev
);
2584 case HCLGE_VECTOR0_EVENT_MBX
:
2585 /* If we are here then,
2586 * 1. Either we are not handling any mbx task and we are not
2589 * 2. We could be handling a mbx task but nothing more is
2591 * In both cases, we should schedule mbx task as there are more
2592 * mbx messages reported by this interrupt.
2594 hclge_mbx_task_schedule(hdev
);
2597 dev_warn(&hdev
->pdev
->dev
,
2598 "received unknown or unhandled event of vector0\n");
2602 /* clear the source of interrupt if it is not cause by reset */
2603 if (event_cause
!= HCLGE_VECTOR0_EVENT_RST
) {
2604 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2605 hclge_enable_vector(&hdev
->misc_vector
, true);
2611 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2613 if (hdev
->vector_status
[vector_id
] == HCLGE_INVALID_VPORT
) {
2614 dev_warn(&hdev
->pdev
->dev
,
2615 "vector(vector_id %d) has been freed.\n", vector_id
);
2619 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2620 hdev
->num_msi_left
+= 1;
2621 hdev
->num_msi_used
-= 1;
2624 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2626 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2628 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2630 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2631 hdev
->vector_status
[0] = 0;
2633 hdev
->num_msi_left
-= 1;
2634 hdev
->num_msi_used
+= 1;
2637 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2641 hclge_get_misc_vector(hdev
);
2643 /* this would be explicitly freed in the end */
2644 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2645 0, "hclge_misc", hdev
);
2647 hclge_free_vector(hdev
, 0);
2648 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2649 hdev
->misc_vector
.vector_irq
);
2655 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2657 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2658 hclge_free_vector(hdev
, 0);
2661 static int hclge_notify_client(struct hclge_dev
*hdev
,
2662 enum hnae3_reset_notify_type type
)
2664 struct hnae3_client
*rclient
= hdev
->roce_client
;
2665 struct hnae3_client
*client
= hdev
->nic_client
;
2666 struct hnae3_handle
*handle
;
2670 if (!client
->ops
->reset_notify
)
2673 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2674 handle
= &hdev
->vport
[i
].nic
;
2675 ret
= client
->ops
->reset_notify(handle
, type
);
2677 dev_err(&hdev
->pdev
->dev
,
2678 "notify nic client failed %d", ret
);
2682 if (rclient
&& rclient
->ops
->reset_notify
) {
2683 handle
= &hdev
->vport
[i
].roce
;
2684 ret
= rclient
->ops
->reset_notify(handle
, type
);
2686 dev_err(&hdev
->pdev
->dev
,
2687 "notify roce client failed %d", ret
);
2696 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2698 #define HCLGE_RESET_WATI_MS 100
2699 #define HCLGE_RESET_WAIT_CNT 5
2700 u32 val
, reg
, reg_bit
;
2703 switch (hdev
->reset_type
) {
2704 case HNAE3_GLOBAL_RESET
:
2705 reg
= HCLGE_GLOBAL_RESET_REG
;
2706 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2708 case HNAE3_CORE_RESET
:
2709 reg
= HCLGE_GLOBAL_RESET_REG
;
2710 reg_bit
= HCLGE_CORE_RESET_BIT
;
2712 case HNAE3_FUNC_RESET
:
2713 reg
= HCLGE_FUN_RST_ING
;
2714 reg_bit
= HCLGE_FUN_RST_ING_B
;
2717 dev_err(&hdev
->pdev
->dev
,
2718 "Wait for unsupported reset type: %d\n",
2723 val
= hclge_read_dev(&hdev
->hw
, reg
);
2724 while (hnae3_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2725 msleep(HCLGE_RESET_WATI_MS
);
2726 val
= hclge_read_dev(&hdev
->hw
, reg
);
2730 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2731 dev_warn(&hdev
->pdev
->dev
,
2732 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2739 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2741 struct hclge_desc desc
;
2742 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2745 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2746 hnae3_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2747 req
->fun_reset_vfid
= func_id
;
2749 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2751 dev_err(&hdev
->pdev
->dev
,
2752 "send function reset cmd fail, status =%d\n", ret
);
2757 static void hclge_do_reset(struct hclge_dev
*hdev
)
2759 struct pci_dev
*pdev
= hdev
->pdev
;
2762 switch (hdev
->reset_type
) {
2763 case HNAE3_GLOBAL_RESET
:
2764 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2765 hnae3_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2766 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2767 dev_info(&pdev
->dev
, "Global Reset requested\n");
2769 case HNAE3_CORE_RESET
:
2770 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2771 hnae3_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2772 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2773 dev_info(&pdev
->dev
, "Core Reset requested\n");
2775 case HNAE3_FUNC_RESET
:
2776 dev_info(&pdev
->dev
, "PF Reset requested\n");
2777 hclge_func_reset_cmd(hdev
, 0);
2778 /* schedule again to check later */
2779 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2780 hclge_reset_task_schedule(hdev
);
2783 dev_warn(&pdev
->dev
,
2784 "Unsupported reset type: %d\n", hdev
->reset_type
);
2789 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2790 unsigned long *addr
)
2792 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2794 /* return the highest priority reset level amongst all */
2795 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2796 rst_level
= HNAE3_GLOBAL_RESET
;
2797 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2798 rst_level
= HNAE3_CORE_RESET
;
2799 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2800 rst_level
= HNAE3_IMP_RESET
;
2801 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2802 rst_level
= HNAE3_FUNC_RESET
;
2804 /* now, clear all other resets */
2805 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2806 clear_bit(HNAE3_CORE_RESET
, addr
);
2807 clear_bit(HNAE3_IMP_RESET
, addr
);
2808 clear_bit(HNAE3_FUNC_RESET
, addr
);
2813 static void hclge_clear_reset_cause(struct hclge_dev
*hdev
)
2817 switch (hdev
->reset_type
) {
2818 case HNAE3_IMP_RESET
:
2819 clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2821 case HNAE3_GLOBAL_RESET
:
2822 clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2824 case HNAE3_CORE_RESET
:
2825 clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2828 dev_warn(&hdev
->pdev
->dev
, "Unsupported reset event to clear:%d",
2836 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, clearval
);
2837 hclge_enable_vector(&hdev
->misc_vector
, true);
2840 static void hclge_reset(struct hclge_dev
*hdev
)
2842 /* perform reset of the stack & ae device for a client */
2844 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2846 if (!hclge_reset_wait(hdev
)) {
2848 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2849 hclge_reset_ae_dev(hdev
->ae_dev
);
2850 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2853 hclge_clear_reset_cause(hdev
);
2855 /* schedule again to check pending resets later */
2856 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2857 hclge_reset_task_schedule(hdev
);
2860 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2863 static void hclge_reset_event(struct hnae3_handle
*handle
)
2865 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2866 struct hclge_dev
*hdev
= vport
->back
;
2868 /* check if this is a new reset request and we are not here just because
2869 * last reset attempt did not succeed and watchdog hit us again. We will
2870 * know this if last reset request did not occur very recently (watchdog
2871 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2872 * In case of new request we reset the "reset level" to PF reset.
2874 if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2875 handle
->reset_level
= HNAE3_FUNC_RESET
;
2877 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2878 handle
->reset_level
);
2880 /* request reset & schedule reset task */
2881 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2882 hclge_reset_task_schedule(hdev
);
2884 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2885 handle
->reset_level
++;
2887 handle
->last_reset_time
= jiffies
;
2890 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2892 /* check if there is any ongoing reset in the hardware. This status can
2893 * be checked from reset_pending. If there is then, we need to wait for
2894 * hardware to complete reset.
2895 * a. If we are able to figure out in reasonable time that hardware
2896 * has fully resetted then, we can proceed with driver, client
2898 * b. else, we can come back later to check this status so re-sched
2901 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2902 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2905 /* check if we got any *new* reset requests to be honored */
2906 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2907 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2908 hclge_do_reset(hdev
);
2910 hdev
->reset_type
= HNAE3_NONE_RESET
;
2913 static void hclge_reset_service_task(struct work_struct
*work
)
2915 struct hclge_dev
*hdev
=
2916 container_of(work
, struct hclge_dev
, rst_service_task
);
2918 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2921 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2923 hclge_reset_subtask(hdev
);
2925 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2928 static void hclge_mailbox_service_task(struct work_struct
*work
)
2930 struct hclge_dev
*hdev
=
2931 container_of(work
, struct hclge_dev
, mbx_service_task
);
2933 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2936 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2938 hclge_mbx_handler(hdev
);
2940 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2943 static void hclge_service_task(struct work_struct
*work
)
2945 struct hclge_dev
*hdev
=
2946 container_of(work
, struct hclge_dev
, service_task
);
2948 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2949 hclge_update_stats_for_all(hdev
);
2950 hdev
->hw_stats
.stats_timer
= 0;
2953 hclge_update_speed_duplex(hdev
);
2954 hclge_update_link_status(hdev
);
2955 hclge_service_complete(hdev
);
2958 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2960 /* VF handle has no client */
2961 if (!handle
->client
)
2962 return container_of(handle
, struct hclge_vport
, nic
);
2963 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2964 return container_of(handle
, struct hclge_vport
, roce
);
2966 return container_of(handle
, struct hclge_vport
, nic
);
2969 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2970 struct hnae3_vector_info
*vector_info
)
2972 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2973 struct hnae3_vector_info
*vector
= vector_info
;
2974 struct hclge_dev
*hdev
= vport
->back
;
2978 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2980 for (j
= 0; j
< vector_num
; j
++) {
2981 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2982 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2983 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2984 vector
->io_addr
= hdev
->hw
.io_base
+
2985 HCLGE_VECTOR_REG_BASE
+
2986 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2988 HCLGE_VECTOR_VF_OFFSET
;
2989 hdev
->vector_status
[i
] = vport
->vport_id
;
2990 hdev
->vector_irq
[i
] = vector
->vector
;
2999 hdev
->num_msi_left
-= alloc
;
3000 hdev
->num_msi_used
+= alloc
;
3005 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
3009 for (i
= 0; i
< hdev
->num_msi
; i
++)
3010 if (vector
== hdev
->vector_irq
[i
])
3016 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
3018 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3019 struct hclge_dev
*hdev
= vport
->back
;
3022 vector_id
= hclge_get_vector_index(hdev
, vector
);
3023 if (vector_id
< 0) {
3024 dev_err(&hdev
->pdev
->dev
,
3025 "Get vector index fail. vector_id =%d\n", vector_id
);
3029 hclge_free_vector(hdev
, vector_id
);
3034 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
3036 return HCLGE_RSS_KEY_SIZE
;
3039 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
3041 return HCLGE_RSS_IND_TBL_SIZE
;
3044 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3045 const u8 hfunc
, const u8
*key
)
3047 struct hclge_rss_config_cmd
*req
;
3048 struct hclge_desc desc
;
3053 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3055 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3056 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3059 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3060 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3062 if (key_offset
== 2)
3064 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3066 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3068 memcpy(req
->hash_key
,
3069 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3071 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3073 dev_err(&hdev
->pdev
->dev
,
3074 "Configure RSS config fail, status = %d\n",
3082 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3084 struct hclge_rss_indirection_table_cmd
*req
;
3085 struct hclge_desc desc
;
3089 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3091 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3092 hclge_cmd_setup_basic_desc
3093 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3095 req
->start_table_index
=
3096 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3097 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3099 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3100 req
->rss_result
[j
] =
3101 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3103 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3105 dev_err(&hdev
->pdev
->dev
,
3106 "Configure rss indir table fail,status = %d\n",
3114 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3115 u16
*tc_size
, u16
*tc_offset
)
3117 struct hclge_rss_tc_mode_cmd
*req
;
3118 struct hclge_desc desc
;
3122 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3123 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3125 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3128 hnae3_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3129 hnae3_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3130 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3131 hnae3_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3132 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3134 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3137 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3139 dev_err(&hdev
->pdev
->dev
,
3140 "Configure rss tc mode fail, status = %d\n", ret
);
3147 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3149 struct hclge_rss_input_tuple_cmd
*req
;
3150 struct hclge_desc desc
;
3153 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3155 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3157 /* Get the tuple cfg from pf */
3158 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3159 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3160 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3161 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3162 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3163 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3164 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3165 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3166 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3168 dev_err(&hdev
->pdev
->dev
,
3169 "Configure rss input fail, status = %d\n", ret
);
3176 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3179 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3182 /* Get hash algorithm */
3184 *hfunc
= vport
->rss_algo
;
3186 /* Get the RSS Key required by the user */
3188 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3190 /* Get indirect table */
3192 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3193 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3198 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3199 const u8
*key
, const u8 hfunc
)
3201 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3202 struct hclge_dev
*hdev
= vport
->back
;
3206 /* Set the RSS Hash Key if specififed by the user */
3209 if (hfunc
== ETH_RSS_HASH_TOP
||
3210 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3211 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3214 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3218 /* Update the shadow RSS key with user specified qids */
3219 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3220 vport
->rss_algo
= hash_algo
;
3223 /* Update the shadow RSS table with user specified qids */
3224 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3225 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3227 /* Update the hardware */
3228 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3231 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3233 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3235 if (nfc
->data
& RXH_L4_B_2_3
)
3236 hash_sets
|= HCLGE_D_PORT_BIT
;
3238 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3240 if (nfc
->data
& RXH_IP_SRC
)
3241 hash_sets
|= HCLGE_S_IP_BIT
;
3243 hash_sets
&= ~HCLGE_S_IP_BIT
;
3245 if (nfc
->data
& RXH_IP_DST
)
3246 hash_sets
|= HCLGE_D_IP_BIT
;
3248 hash_sets
&= ~HCLGE_D_IP_BIT
;
3250 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3251 hash_sets
|= HCLGE_V_TAG_BIT
;
3256 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3257 struct ethtool_rxnfc
*nfc
)
3259 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3260 struct hclge_dev
*hdev
= vport
->back
;
3261 struct hclge_rss_input_tuple_cmd
*req
;
3262 struct hclge_desc desc
;
3266 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3267 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3270 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3271 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3273 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3274 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3275 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3276 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3277 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3278 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3279 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3280 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3282 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3283 switch (nfc
->flow_type
) {
3285 req
->ipv4_tcp_en
= tuple_sets
;
3288 req
->ipv6_tcp_en
= tuple_sets
;
3291 req
->ipv4_udp_en
= tuple_sets
;
3294 req
->ipv6_udp_en
= tuple_sets
;
3297 req
->ipv4_sctp_en
= tuple_sets
;
3300 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3301 (nfc
->data
& RXH_L4_B_2_3
))
3304 req
->ipv6_sctp_en
= tuple_sets
;
3307 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3310 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3316 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3318 dev_err(&hdev
->pdev
->dev
,
3319 "Set rss tuple fail, status = %d\n", ret
);
3323 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3324 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3325 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3326 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3327 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3328 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3329 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3330 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3334 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3335 struct ethtool_rxnfc
*nfc
)
3337 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3342 switch (nfc
->flow_type
) {
3344 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3347 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3350 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3353 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3356 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3359 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3363 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3372 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3373 nfc
->data
|= RXH_L4_B_2_3
;
3374 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3375 nfc
->data
|= RXH_L4_B_0_1
;
3376 if (tuple_sets
& HCLGE_D_IP_BIT
)
3377 nfc
->data
|= RXH_IP_DST
;
3378 if (tuple_sets
& HCLGE_S_IP_BIT
)
3379 nfc
->data
|= RXH_IP_SRC
;
3384 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3386 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3387 struct hclge_dev
*hdev
= vport
->back
;
3389 return hdev
->rss_size_max
;
3392 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3394 struct hclge_vport
*vport
= hdev
->vport
;
3395 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3396 u16 rss_size
= vport
[0].alloc_rss_size
;
3397 u8
*key
= vport
[0].rss_hash_key
;
3398 u8 hfunc
= vport
[0].rss_algo
;
3399 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3400 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3401 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3405 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3409 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3413 ret
= hclge_set_rss_input_tuple(hdev
);
3417 /* Each TC have the same queue size, and tc_size set to hardware is
3418 * the log2 of roundup power of two of rss_size, the acutal queue
3419 * size is limited by indirection table.
3421 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3422 dev_err(&hdev
->pdev
->dev
,
3423 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3428 roundup_size
= roundup_pow_of_two(rss_size
);
3429 roundup_size
= ilog2(roundup_size
);
3431 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3434 if (!(hdev
->hw_tc_map
& BIT(i
)))
3438 tc_size
[i
] = roundup_size
;
3439 tc_offset
[i
] = rss_size
* i
;
3442 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3445 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3447 struct hclge_vport
*vport
= hdev
->vport
;
3450 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3451 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3452 vport
[j
].rss_indirection_tbl
[i
] =
3453 i
% vport
[j
].alloc_rss_size
;
3457 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3459 struct hclge_vport
*vport
= hdev
->vport
;
3462 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3463 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3464 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3465 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3466 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3467 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3468 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3469 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3470 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3471 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3472 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3473 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3474 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3475 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3476 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3477 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3478 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3480 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3482 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3485 hclge_rss_indir_init_cfg(hdev
);
3488 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3489 int vector_id
, bool en
,
3490 struct hnae3_ring_chain_node
*ring_chain
)
3492 struct hclge_dev
*hdev
= vport
->back
;
3493 struct hnae3_ring_chain_node
*node
;
3494 struct hclge_desc desc
;
3495 struct hclge_ctrl_vector_chain_cmd
*req
3496 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3497 enum hclge_cmd_status status
;
3498 enum hclge_opcode_type op
;
3499 u16 tqp_type_and_id
;
3502 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3503 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3504 req
->int_vector_id
= vector_id
;
3507 for (node
= ring_chain
; node
; node
= node
->next
) {
3508 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3509 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3511 hnae3_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3512 hnae3_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3513 HCLGE_TQP_ID_S
, node
->tqp_index
);
3514 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3516 hnae3_get_field(node
->int_gl_idx
,
3517 HNAE3_RING_GL_IDX_M
,
3518 HNAE3_RING_GL_IDX_S
));
3519 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3520 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3521 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3522 req
->vfid
= vport
->vport_id
;
3524 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3526 dev_err(&hdev
->pdev
->dev
,
3527 "Map TQP fail, status is %d.\n",
3533 hclge_cmd_setup_basic_desc(&desc
,
3536 req
->int_vector_id
= vector_id
;
3541 req
->int_cause_num
= i
;
3542 req
->vfid
= vport
->vport_id
;
3543 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3545 dev_err(&hdev
->pdev
->dev
,
3546 "Map TQP fail, status is %d.\n", status
);
3554 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3556 struct hnae3_ring_chain_node
*ring_chain
)
3558 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3559 struct hclge_dev
*hdev
= vport
->back
;
3562 vector_id
= hclge_get_vector_index(hdev
, vector
);
3563 if (vector_id
< 0) {
3564 dev_err(&hdev
->pdev
->dev
,
3565 "Get vector index fail. vector_id =%d\n", vector_id
);
3569 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3572 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3574 struct hnae3_ring_chain_node
*ring_chain
)
3576 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3577 struct hclge_dev
*hdev
= vport
->back
;
3580 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3583 vector_id
= hclge_get_vector_index(hdev
, vector
);
3584 if (vector_id
< 0) {
3585 dev_err(&handle
->pdev
->dev
,
3586 "Get vector index fail. ret =%d\n", vector_id
);
3590 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3592 dev_err(&handle
->pdev
->dev
,
3593 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3600 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3601 struct hclge_promisc_param
*param
)
3603 struct hclge_promisc_cfg_cmd
*req
;
3604 struct hclge_desc desc
;
3607 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3609 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3610 req
->vf_id
= param
->vf_id
;
3612 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3613 * pdev revision(0x20), new revision support them. The
3614 * value of this two fields will not return error when driver
3615 * send command to fireware in revision(0x20).
3617 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
) |
3618 HCLGE_PROMISC_TX_EN_B
| HCLGE_PROMISC_RX_EN_B
;
3620 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3622 dev_err(&hdev
->pdev
->dev
,
3623 "Set promisc mode fail, status is %d.\n", ret
);
3629 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3630 bool en_mc
, bool en_bc
, int vport_id
)
3635 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3637 param
->enable
= HCLGE_PROMISC_EN_UC
;
3639 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3641 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3642 param
->vf_id
= vport_id
;
3645 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, bool en_uc_pmc
,
3648 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3649 struct hclge_dev
*hdev
= vport
->back
;
3650 struct hclge_promisc_param param
;
3652 hclge_promisc_param_init(¶m
, en_uc_pmc
, en_mc_pmc
, true,
3654 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3657 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3659 struct hclge_desc desc
;
3660 struct hclge_config_mac_mode_cmd
*req
=
3661 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3665 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3666 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3667 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3668 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3669 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3670 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3671 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3672 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3673 hnae3_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3674 hnae3_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3675 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3676 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3677 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3678 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3679 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3680 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3682 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3684 dev_err(&hdev
->pdev
->dev
,
3685 "mac enable fail, ret =%d.\n", ret
);
3688 static int hclge_set_mac_loopback(struct hclge_dev
*hdev
, bool en
)
3690 struct hclge_config_mac_mode_cmd
*req
;
3691 struct hclge_desc desc
;
3695 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3696 /* 1 Read out the MAC mode config at first */
3697 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, true);
3698 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3700 dev_err(&hdev
->pdev
->dev
,
3701 "mac loopback get fail, ret =%d.\n", ret
);
3705 /* 2 Then setup the loopback flag */
3706 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3707 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, en
? 1 : 0);
3709 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3711 /* 3 Config mac work mode with loopback flag
3712 * and its original configure parameters
3714 hclge_cmd_reuse_desc(&desc
, false);
3715 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3717 dev_err(&hdev
->pdev
->dev
,
3718 "mac loopback set fail, ret =%d.\n", ret
);
3722 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3723 enum hnae3_loop loop_mode
, bool en
)
3725 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3726 struct hclge_dev
*hdev
= vport
->back
;
3729 switch (loop_mode
) {
3730 case HNAE3_MAC_INTER_LOOP_MAC
:
3731 ret
= hclge_set_mac_loopback(hdev
, en
);
3735 dev_err(&hdev
->pdev
->dev
,
3736 "loop_mode %d is not supported\n", loop_mode
);
3743 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3744 int stream_id
, bool enable
)
3746 struct hclge_desc desc
;
3747 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3748 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3751 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3752 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3753 req
->stream_id
= cpu_to_le16(stream_id
);
3754 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3756 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3758 dev_err(&hdev
->pdev
->dev
,
3759 "Tqp enable fail, status =%d.\n", ret
);
3763 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3765 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3766 struct hnae3_queue
*queue
;
3767 struct hclge_tqp
*tqp
;
3770 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3771 queue
= handle
->kinfo
.tqp
[i
];
3772 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3773 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3777 static int hclge_ae_start(struct hnae3_handle
*handle
)
3779 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3780 struct hclge_dev
*hdev
= vport
->back
;
3783 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3784 hclge_tqp_enable(hdev
, i
, 0, true);
3787 hclge_cfg_mac_mode(hdev
, true);
3788 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3789 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3790 hdev
->hw
.mac
.link
= 0;
3792 /* reset tqp stats */
3793 hclge_reset_tqp_stats(handle
);
3795 ret
= hclge_mac_start_phy(hdev
);
3802 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3804 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3805 struct hclge_dev
*hdev
= vport
->back
;
3808 del_timer_sync(&hdev
->service_timer
);
3809 cancel_work_sync(&hdev
->service_task
);
3810 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
3812 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
3813 hclge_mac_stop_phy(hdev
);
3817 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3818 hclge_tqp_enable(hdev
, i
, 0, false);
3821 hclge_cfg_mac_mode(hdev
, false);
3823 hclge_mac_stop_phy(hdev
);
3825 /* reset tqp stats */
3826 hclge_reset_tqp_stats(handle
);
3827 del_timer_sync(&hdev
->service_timer
);
3828 cancel_work_sync(&hdev
->service_task
);
3829 hclge_update_link_status(hdev
);
3832 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3833 u16 cmdq_resp
, u8 resp_code
,
3834 enum hclge_mac_vlan_tbl_opcode op
)
3836 struct hclge_dev
*hdev
= vport
->back
;
3837 int return_status
= -EIO
;
3840 dev_err(&hdev
->pdev
->dev
,
3841 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3846 if (op
== HCLGE_MAC_VLAN_ADD
) {
3847 if ((!resp_code
) || (resp_code
== 1)) {
3849 } else if (resp_code
== 2) {
3850 return_status
= -ENOSPC
;
3851 dev_err(&hdev
->pdev
->dev
,
3852 "add mac addr failed for uc_overflow.\n");
3853 } else if (resp_code
== 3) {
3854 return_status
= -ENOSPC
;
3855 dev_err(&hdev
->pdev
->dev
,
3856 "add mac addr failed for mc_overflow.\n");
3858 dev_err(&hdev
->pdev
->dev
,
3859 "add mac addr failed for undefined, code=%d.\n",
3862 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3865 } else if (resp_code
== 1) {
3866 return_status
= -ENOENT
;
3867 dev_dbg(&hdev
->pdev
->dev
,
3868 "remove mac addr failed for miss.\n");
3870 dev_err(&hdev
->pdev
->dev
,
3871 "remove mac addr failed for undefined, code=%d.\n",
3874 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3877 } else if (resp_code
== 1) {
3878 return_status
= -ENOENT
;
3879 dev_dbg(&hdev
->pdev
->dev
,
3880 "lookup mac addr failed for miss.\n");
3882 dev_err(&hdev
->pdev
->dev
,
3883 "lookup mac addr failed for undefined, code=%d.\n",
3887 return_status
= -EINVAL
;
3888 dev_err(&hdev
->pdev
->dev
,
3889 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3893 return return_status
;
3896 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3901 if (vfid
> 255 || vfid
< 0)
3904 if (vfid
>= 0 && vfid
<= 191) {
3905 word_num
= vfid
/ 32;
3906 bit_num
= vfid
% 32;
3908 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3910 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3912 word_num
= (vfid
- 192) / 32;
3913 bit_num
= vfid
% 32;
3915 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3917 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3923 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3925 #define HCLGE_DESC_NUMBER 3
3926 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3929 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3930 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3931 if (desc
[i
].data
[j
])
3937 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3940 const unsigned char *mac_addr
= addr
;
3941 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3942 (mac_addr
[0]) | (mac_addr
[1] << 8);
3943 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3945 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3946 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3949 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3952 u16 high_val
= addr
[1] | (addr
[0] << 8);
3953 struct hclge_dev
*hdev
= vport
->back
;
3954 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3955 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3960 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3961 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3964 struct hclge_mta_filter_mode_cmd
*req
;
3965 struct hclge_desc desc
;
3968 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3969 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3971 hnae3_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3973 hnae3_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3974 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3976 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3978 dev_err(&hdev
->pdev
->dev
,
3979 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3987 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3991 struct hclge_cfg_func_mta_filter_cmd
*req
;
3992 struct hclge_desc desc
;
3995 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3996 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3998 hnae3_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
4000 req
->function_id
= func_id
;
4002 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4004 dev_err(&hdev
->pdev
->dev
,
4005 "Config func_id enable failed for cmd_send, ret =%d.\n",
4013 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
4017 struct hclge_dev
*hdev
= vport
->back
;
4018 struct hclge_cfg_func_mta_item_cmd
*req
;
4019 struct hclge_desc desc
;
4023 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
4024 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
4025 hnae3_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
4027 hnae3_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
4028 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
4029 req
->item_idx
= cpu_to_le16(item_idx
);
4031 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4033 dev_err(&hdev
->pdev
->dev
,
4034 "Config mta table item failed for cmd_send, ret =%d.\n",
4040 set_bit(idx
, vport
->mta_shadow
);
4042 clear_bit(idx
, vport
->mta_shadow
);
4047 static int hclge_update_mta_status(struct hnae3_handle
*handle
)
4049 unsigned long mta_status
[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE
)];
4050 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4051 struct net_device
*netdev
= handle
->kinfo
.netdev
;
4052 struct netdev_hw_addr
*ha
;
4055 memset(mta_status
, 0, sizeof(mta_status
));
4057 /* update mta_status from mc addr list */
4058 netdev_for_each_mc_addr(ha
, netdev
) {
4059 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, ha
->addr
);
4060 set_bit(tbl_idx
, mta_status
);
4063 return hclge_update_mta_status_common(vport
, mta_status
,
4064 0, HCLGE_MTA_TBL_SIZE
, true);
4067 int hclge_update_mta_status_common(struct hclge_vport
*vport
,
4068 unsigned long *status
,
4073 struct hclge_dev
*hdev
= vport
->back
;
4074 u16 update_max
= idx
+ count
;
4080 /* setup mta check range */
4081 if (update_filter
) {
4083 check_max
= HCLGE_MTA_TBL_SIZE
;
4086 check_max
= update_max
;
4090 /* check and update all mta item */
4091 for (; i
< check_max
; i
++) {
4092 /* ignore unused item */
4093 if (!test_bit(i
, vport
->mta_shadow
))
4096 /* if i in update range then update it */
4097 if (i
>= idx
&& i
< update_max
)
4098 if (!test_bit(i
- idx
, status
))
4099 hclge_set_mta_table_item(vport
, i
, false);
4101 if (!used
&& test_bit(i
, vport
->mta_shadow
))
4105 /* no longer use mta, disable it */
4106 if (vport
->accept_mta_mc
&& update_filter
&& !used
) {
4107 ret
= hclge_cfg_func_mta_filter(hdev
,
4111 dev_err(&hdev
->pdev
->dev
,
4112 "disable func mta filter fail ret=%d\n",
4115 vport
->accept_mta_mc
= false;
4121 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4122 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4124 struct hclge_dev
*hdev
= vport
->back
;
4125 struct hclge_desc desc
;
4130 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4132 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4134 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4136 dev_err(&hdev
->pdev
->dev
,
4137 "del mac addr failed for cmd_send, ret =%d.\n",
4141 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4142 retval
= le16_to_cpu(desc
.retval
);
4144 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4145 HCLGE_MAC_VLAN_REMOVE
);
4148 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4149 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4150 struct hclge_desc
*desc
,
4153 struct hclge_dev
*hdev
= vport
->back
;
4158 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4160 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4161 memcpy(desc
[0].data
,
4163 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4164 hclge_cmd_setup_basic_desc(&desc
[1],
4165 HCLGE_OPC_MAC_VLAN_ADD
,
4167 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4168 hclge_cmd_setup_basic_desc(&desc
[2],
4169 HCLGE_OPC_MAC_VLAN_ADD
,
4171 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4173 memcpy(desc
[0].data
,
4175 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4176 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4179 dev_err(&hdev
->pdev
->dev
,
4180 "lookup mac addr failed for cmd_send, ret =%d.\n",
4184 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4185 retval
= le16_to_cpu(desc
[0].retval
);
4187 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4188 HCLGE_MAC_VLAN_LKUP
);
4191 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4192 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4193 struct hclge_desc
*mc_desc
)
4195 struct hclge_dev
*hdev
= vport
->back
;
4202 struct hclge_desc desc
;
4204 hclge_cmd_setup_basic_desc(&desc
,
4205 HCLGE_OPC_MAC_VLAN_ADD
,
4207 memcpy(desc
.data
, req
,
4208 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4209 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4210 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4211 retval
= le16_to_cpu(desc
.retval
);
4213 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4215 HCLGE_MAC_VLAN_ADD
);
4217 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4218 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4219 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4220 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4221 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4222 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4223 memcpy(mc_desc
[0].data
, req
,
4224 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4225 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4226 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4227 retval
= le16_to_cpu(mc_desc
[0].retval
);
4229 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4231 HCLGE_MAC_VLAN_ADD
);
4235 dev_err(&hdev
->pdev
->dev
,
4236 "add mac addr failed for cmd_send, ret =%d.\n",
4244 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4245 const unsigned char *addr
)
4247 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4249 return hclge_add_uc_addr_common(vport
, addr
);
4252 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4253 const unsigned char *addr
)
4255 struct hclge_dev
*hdev
= vport
->back
;
4256 struct hclge_mac_vlan_tbl_entry_cmd req
;
4257 struct hclge_desc desc
;
4258 u16 egress_port
= 0;
4261 /* mac addr check */
4262 if (is_zero_ether_addr(addr
) ||
4263 is_broadcast_ether_addr(addr
) ||
4264 is_multicast_ether_addr(addr
)) {
4265 dev_err(&hdev
->pdev
->dev
,
4266 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4268 is_zero_ether_addr(addr
),
4269 is_broadcast_ether_addr(addr
),
4270 is_multicast_ether_addr(addr
));
4274 memset(&req
, 0, sizeof(req
));
4275 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4277 hnae3_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4278 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4280 req
.egress_port
= cpu_to_le16(egress_port
);
4282 hclge_prepare_mac_addr(&req
, addr
);
4284 /* Lookup the mac address in the mac_vlan table, and add
4285 * it if the entry is inexistent. Repeated unicast entry
4286 * is not allowed in the mac vlan table.
4288 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4290 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4292 /* check if we just hit the duplicate */
4296 dev_err(&hdev
->pdev
->dev
,
4297 "PF failed to add unicast entry(%pM) in the MAC table\n",
4303 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4304 const unsigned char *addr
)
4306 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4308 return hclge_rm_uc_addr_common(vport
, addr
);
4311 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4312 const unsigned char *addr
)
4314 struct hclge_dev
*hdev
= vport
->back
;
4315 struct hclge_mac_vlan_tbl_entry_cmd req
;
4318 /* mac addr check */
4319 if (is_zero_ether_addr(addr
) ||
4320 is_broadcast_ether_addr(addr
) ||
4321 is_multicast_ether_addr(addr
)) {
4322 dev_dbg(&hdev
->pdev
->dev
,
4323 "Remove mac err! invalid mac:%pM.\n",
4328 memset(&req
, 0, sizeof(req
));
4329 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4330 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4331 hclge_prepare_mac_addr(&req
, addr
);
4332 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4337 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4338 const unsigned char *addr
)
4340 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4342 return hclge_add_mc_addr_common(vport
, addr
);
4345 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4346 const unsigned char *addr
)
4348 struct hclge_dev
*hdev
= vport
->back
;
4349 struct hclge_mac_vlan_tbl_entry_cmd req
;
4350 struct hclge_desc desc
[3];
4354 /* mac addr check */
4355 if (!is_multicast_ether_addr(addr
)) {
4356 dev_err(&hdev
->pdev
->dev
,
4357 "Add mc mac err! invalid mac:%pM.\n",
4361 memset(&req
, 0, sizeof(req
));
4362 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4363 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4364 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4365 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4366 hclge_prepare_mac_addr(&req
, addr
);
4367 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4369 /* This mac addr exist, update VFID for it */
4370 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4371 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4373 /* This mac addr do not exist, add new entry for it */
4374 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4375 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4376 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4377 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4378 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4381 /* If mc mac vlan table is full, use MTA table */
4382 if (status
== -ENOSPC
) {
4383 if (!vport
->accept_mta_mc
) {
4384 status
= hclge_cfg_func_mta_filter(hdev
,
4388 dev_err(&hdev
->pdev
->dev
,
4389 "set mta filter mode fail ret=%d\n",
4393 vport
->accept_mta_mc
= true;
4396 /* Set MTA table for this MAC address */
4397 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4398 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4404 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4405 const unsigned char *addr
)
4407 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4409 return hclge_rm_mc_addr_common(vport
, addr
);
4412 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4413 const unsigned char *addr
)
4415 struct hclge_dev
*hdev
= vport
->back
;
4416 struct hclge_mac_vlan_tbl_entry_cmd req
;
4417 enum hclge_cmd_status status
;
4418 struct hclge_desc desc
[3];
4420 /* mac addr check */
4421 if (!is_multicast_ether_addr(addr
)) {
4422 dev_dbg(&hdev
->pdev
->dev
,
4423 "Remove mc mac err! invalid mac:%pM.\n",
4428 memset(&req
, 0, sizeof(req
));
4429 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4430 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4431 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4432 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4433 hclge_prepare_mac_addr(&req
, addr
);
4434 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4436 /* This mac addr exist, remove this handle's VFID for it */
4437 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4439 if (hclge_is_all_function_id_zero(desc
))
4440 /* All the vfid is zero, so need to delete this entry */
4441 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4443 /* Not all the vfid is zero, update the vfid */
4444 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4447 /* Maybe this mac address is in mta table, but it cannot be
4448 * deleted here because an entry of mta represents an address
4449 * range rather than a specific address. the delete action to
4450 * all entries will take effect in update_mta_status called by
4451 * hns3_nic_set_rx_mode.
4459 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4460 u16 cmdq_resp
, u8 resp_code
)
4462 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4463 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4464 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4465 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4470 dev_err(&hdev
->pdev
->dev
,
4471 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4476 switch (resp_code
) {
4477 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4478 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4481 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4482 dev_err(&hdev
->pdev
->dev
,
4483 "add mac ethertype failed for manager table overflow.\n");
4484 return_status
= -EIO
;
4486 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4487 dev_err(&hdev
->pdev
->dev
,
4488 "add mac ethertype failed for key conflict.\n");
4489 return_status
= -EIO
;
4492 dev_err(&hdev
->pdev
->dev
,
4493 "add mac ethertype failed for undefined, code=%d.\n",
4495 return_status
= -EIO
;
4498 return return_status
;
4501 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4502 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4504 struct hclge_desc desc
;
4509 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4510 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4512 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4514 dev_err(&hdev
->pdev
->dev
,
4515 "add mac ethertype failed for cmd_send, ret =%d.\n",
4520 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4521 retval
= le16_to_cpu(desc
.retval
);
4523 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4526 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4531 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4532 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4534 dev_err(&hdev
->pdev
->dev
,
4535 "add mac ethertype failed, ret =%d.\n",
4544 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4546 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4547 struct hclge_dev
*hdev
= vport
->back
;
4549 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4552 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4555 const unsigned char *new_addr
= (const unsigned char *)p
;
4556 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4557 struct hclge_dev
*hdev
= vport
->back
;
4560 /* mac addr check */
4561 if (is_zero_ether_addr(new_addr
) ||
4562 is_broadcast_ether_addr(new_addr
) ||
4563 is_multicast_ether_addr(new_addr
)) {
4564 dev_err(&hdev
->pdev
->dev
,
4565 "Change uc mac err! invalid mac:%p.\n",
4570 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4571 dev_warn(&hdev
->pdev
->dev
,
4572 "remove old uc mac address fail.\n");
4574 ret
= hclge_add_uc_addr(handle
, new_addr
);
4576 dev_err(&hdev
->pdev
->dev
,
4577 "add uc mac address fail, ret =%d.\n",
4581 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4582 dev_err(&hdev
->pdev
->dev
,
4583 "restore uc mac address fail.\n");
4588 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4590 dev_err(&hdev
->pdev
->dev
,
4591 "configure mac pause address fail, ret =%d.\n",
4596 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4601 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4604 struct hclge_vlan_filter_ctrl_cmd
*req
;
4605 struct hclge_desc desc
;
4608 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4610 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4611 req
->vlan_type
= vlan_type
;
4612 req
->vlan_fe
= filter_en
;
4614 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4616 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4624 #define HCLGE_FILTER_TYPE_VF 0
4625 #define HCLGE_FILTER_TYPE_PORT 1
4627 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4629 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4630 struct hclge_dev
*hdev
= vport
->back
;
4632 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4635 static int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4636 bool is_kill
, u16 vlan
, u8 qos
,
4639 #define HCLGE_MAX_VF_BYTES 16
4640 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4641 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4642 struct hclge_desc desc
[2];
4647 hclge_cmd_setup_basic_desc(&desc
[0],
4648 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4649 hclge_cmd_setup_basic_desc(&desc
[1],
4650 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4652 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4654 vf_byte_off
= vfid
/ 8;
4655 vf_byte_val
= 1 << (vfid
% 8);
4657 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4658 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4660 req0
->vlan_id
= cpu_to_le16(vlan
);
4661 req0
->vlan_cfg
= is_kill
;
4663 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4664 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4666 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4668 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4670 dev_err(&hdev
->pdev
->dev
,
4671 "Send vf vlan command fail, ret =%d.\n",
4677 #define HCLGE_VF_VLAN_NO_ENTRY 2
4678 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4681 if (req0
->resp_code
== HCLGE_VF_VLAN_NO_ENTRY
) {
4682 dev_warn(&hdev
->pdev
->dev
,
4683 "vf vlan table is full, vf vlan filter is disabled\n");
4687 dev_err(&hdev
->pdev
->dev
,
4688 "Add vf vlan filter fail, ret =%d.\n",
4691 if (!req0
->resp_code
)
4694 dev_err(&hdev
->pdev
->dev
,
4695 "Kill vf vlan filter fail, ret =%d.\n",
4702 static int hclge_set_port_vlan_filter(struct hclge_dev
*hdev
, __be16 proto
,
4703 u16 vlan_id
, bool is_kill
)
4705 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4706 struct hclge_desc desc
;
4707 u8 vlan_offset_byte_val
;
4708 u8 vlan_offset_byte
;
4712 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4714 vlan_offset_160
= vlan_id
/ 160;
4715 vlan_offset_byte
= (vlan_id
% 160) / 8;
4716 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4718 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4719 req
->vlan_offset
= vlan_offset_160
;
4720 req
->vlan_cfg
= is_kill
;
4721 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4723 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4725 dev_err(&hdev
->pdev
->dev
,
4726 "port vlan command, send fail, ret =%d.\n", ret
);
4730 static int hclge_set_vlan_filter_hw(struct hclge_dev
*hdev
, __be16 proto
,
4731 u16 vport_id
, u16 vlan_id
, u8 qos
,
4734 u16 vport_idx
, vport_num
= 0;
4737 ret
= hclge_set_vf_vlan_common(hdev
, vport_id
, is_kill
, vlan_id
,
4740 dev_err(&hdev
->pdev
->dev
,
4741 "Set %d vport vlan filter config fail, ret =%d.\n",
4746 /* vlan 0 may be added twice when 8021q module is enabled */
4747 if (!is_kill
&& !vlan_id
&&
4748 test_bit(vport_id
, hdev
->vlan_table
[vlan_id
]))
4751 if (!is_kill
&& test_and_set_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4752 dev_err(&hdev
->pdev
->dev
,
4753 "Add port vlan failed, vport %d is already in vlan %d\n",
4759 !test_and_clear_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4760 dev_err(&hdev
->pdev
->dev
,
4761 "Delete port vlan failed, vport %d is not in vlan %d\n",
4766 for_each_set_bit(vport_idx
, hdev
->vlan_table
[vlan_id
], VLAN_N_VID
)
4769 if ((is_kill
&& vport_num
== 0) || (!is_kill
&& vport_num
== 1))
4770 ret
= hclge_set_port_vlan_filter(hdev
, proto
, vlan_id
,
4776 int hclge_set_vlan_filter(struct hnae3_handle
*handle
, __be16 proto
,
4777 u16 vlan_id
, bool is_kill
)
4779 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4780 struct hclge_dev
*hdev
= vport
->back
;
4782 return hclge_set_vlan_filter_hw(hdev
, proto
, vport
->vport_id
, vlan_id
,
4786 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4787 u16 vlan
, u8 qos
, __be16 proto
)
4789 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4790 struct hclge_dev
*hdev
= vport
->back
;
4792 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4794 if (proto
!= htons(ETH_P_8021Q
))
4795 return -EPROTONOSUPPORT
;
4797 return hclge_set_vlan_filter_hw(hdev
, proto
, vfid
, vlan
, qos
, false);
4800 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4802 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4803 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4804 struct hclge_dev
*hdev
= vport
->back
;
4805 struct hclge_desc desc
;
4808 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4810 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4811 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4812 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4813 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG1_B
,
4814 vcfg
->accept_tag1
? 1 : 0);
4815 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG1_B
,
4816 vcfg
->accept_untag1
? 1 : 0);
4817 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG2_B
,
4818 vcfg
->accept_tag2
? 1 : 0);
4819 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG2_B
,
4820 vcfg
->accept_untag2
? 1 : 0);
4821 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4822 vcfg
->insert_tag1_en
? 1 : 0);
4823 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4824 vcfg
->insert_tag2_en
? 1 : 0);
4825 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4827 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4828 req
->vf_bitmap
[req
->vf_offset
] =
4829 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4831 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4833 dev_err(&hdev
->pdev
->dev
,
4834 "Send port txvlan cfg command fail, ret =%d\n",
4840 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4842 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4843 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4844 struct hclge_dev
*hdev
= vport
->back
;
4845 struct hclge_desc desc
;
4848 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4850 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4851 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4852 vcfg
->strip_tag1_en
? 1 : 0);
4853 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4854 vcfg
->strip_tag2_en
? 1 : 0);
4855 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4856 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4857 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4858 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4860 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4861 req
->vf_bitmap
[req
->vf_offset
] =
4862 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4864 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4866 dev_err(&hdev
->pdev
->dev
,
4867 "Send port rxvlan cfg command fail, ret =%d\n",
4873 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4875 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4876 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4877 struct hclge_desc desc
;
4880 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4881 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4882 rx_req
->ot_fst_vlan_type
=
4883 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4884 rx_req
->ot_sec_vlan_type
=
4885 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4886 rx_req
->in_fst_vlan_type
=
4887 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4888 rx_req
->in_sec_vlan_type
=
4889 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4891 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4893 dev_err(&hdev
->pdev
->dev
,
4894 "Send rxvlan protocol type command fail, ret =%d\n",
4899 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4901 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4902 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4903 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4905 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4907 dev_err(&hdev
->pdev
->dev
,
4908 "Send txvlan protocol type command fail, ret =%d\n",
4914 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4916 #define HCLGE_DEF_VLAN_TYPE 0x8100
4918 struct hnae3_handle
*handle
;
4919 struct hclge_vport
*vport
;
4923 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4927 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4931 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4932 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4933 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4934 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4935 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4936 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4938 ret
= hclge_set_vlan_protocol_type(hdev
);
4942 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4943 vport
= &hdev
->vport
[i
];
4944 vport
->txvlan_cfg
.accept_tag1
= true;
4945 vport
->txvlan_cfg
.accept_untag1
= true;
4947 /* accept_tag2 and accept_untag2 are not supported on
4948 * pdev revision(0x20), new revision support them. The
4949 * value of this two fields will not return error when driver
4950 * send command to fireware in revision(0x20).
4951 * This two fields can not configured by user.
4953 vport
->txvlan_cfg
.accept_tag2
= true;
4954 vport
->txvlan_cfg
.accept_untag2
= true;
4956 vport
->txvlan_cfg
.insert_tag1_en
= false;
4957 vport
->txvlan_cfg
.insert_tag2_en
= false;
4958 vport
->txvlan_cfg
.default_tag1
= 0;
4959 vport
->txvlan_cfg
.default_tag2
= 0;
4961 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4965 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4966 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4967 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4968 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4970 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4975 handle
= &hdev
->vport
[0].nic
;
4976 return hclge_set_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4979 int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4981 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4983 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4984 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4985 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4986 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4988 return hclge_set_vlan_rx_offload_cfg(vport
);
4991 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
4993 struct hclge_config_max_frm_size_cmd
*req
;
4994 struct hclge_desc desc
;
4998 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
5000 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
5001 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
5004 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
5006 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
5008 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
5009 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
5010 req
->min_frm_size
= HCLGE_MAC_MIN_FRAME
;
5012 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5014 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
5018 hdev
->mps
= max_frm_size
;
5023 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
5025 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5026 struct hclge_dev
*hdev
= vport
->back
;
5029 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
5031 dev_err(&hdev
->pdev
->dev
,
5032 "Change mtu fail, ret =%d\n", ret
);
5036 ret
= hclge_buffer_alloc(hdev
);
5038 dev_err(&hdev
->pdev
->dev
,
5039 "Allocate buffer fail, ret =%d\n", ret
);
5044 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
5047 struct hclge_reset_tqp_queue_cmd
*req
;
5048 struct hclge_desc desc
;
5051 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
5053 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5054 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5055 hnae3_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
5057 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5059 dev_err(&hdev
->pdev
->dev
,
5060 "Send tqp reset cmd error, status =%d\n", ret
);
5067 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
5069 struct hclge_reset_tqp_queue_cmd
*req
;
5070 struct hclge_desc desc
;
5073 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
5075 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5076 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5078 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5080 dev_err(&hdev
->pdev
->dev
,
5081 "Get reset status error, status =%d\n", ret
);
5085 return hnae3_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
5088 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
5091 struct hnae3_queue
*queue
;
5092 struct hclge_tqp
*tqp
;
5094 queue
= handle
->kinfo
.tqp
[queue_id
];
5095 tqp
= container_of(queue
, struct hclge_tqp
, q
);
5100 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
5102 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5103 struct hclge_dev
*hdev
= vport
->back
;
5104 int reset_try_times
= 0;
5109 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
5112 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
5114 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
5116 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
5120 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5122 dev_warn(&hdev
->pdev
->dev
,
5123 "Send reset tqp cmd fail, ret = %d\n", ret
);
5127 reset_try_times
= 0;
5128 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5129 /* Wait for tqp hw reset */
5131 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5136 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5137 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5141 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5143 dev_warn(&hdev
->pdev
->dev
,
5144 "Deassert the soft reset fail, ret = %d\n", ret
);
5149 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
5151 struct hclge_dev
*hdev
= vport
->back
;
5152 int reset_try_times
= 0;
5157 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5159 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5161 dev_warn(&hdev
->pdev
->dev
,
5162 "Send reset tqp cmd fail, ret = %d\n", ret
);
5166 reset_try_times
= 0;
5167 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5168 /* Wait for tqp hw reset */
5170 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5175 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5176 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5180 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5182 dev_warn(&hdev
->pdev
->dev
,
5183 "Deassert the soft reset fail, ret = %d\n", ret
);
5186 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5188 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5189 struct hclge_dev
*hdev
= vport
->back
;
5191 return hdev
->fw_version
;
5194 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5197 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5198 struct hclge_dev
*hdev
= vport
->back
;
5199 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5204 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5205 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5208 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5210 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5215 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5218 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5221 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5224 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5229 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5230 else if (rx_en
&& !tx_en
)
5231 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5232 else if (!rx_en
&& tx_en
)
5233 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5235 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5237 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5240 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5242 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5247 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5252 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5254 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5255 u16 remote_advertising
= 0;
5256 u16 local_advertising
= 0;
5257 u32 rx_pause
, tx_pause
;
5260 if (!phydev
->link
|| !phydev
->autoneg
)
5263 if (phydev
->advertising
& ADVERTISED_Pause
)
5264 local_advertising
= ADVERTISE_PAUSE_CAP
;
5266 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5267 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5270 remote_advertising
= LPA_PAUSE_CAP
;
5272 if (phydev
->asym_pause
)
5273 remote_advertising
|= LPA_PAUSE_ASYM
;
5275 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5276 remote_advertising
);
5277 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5278 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5280 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5285 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5288 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5289 u32
*rx_en
, u32
*tx_en
)
5291 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5292 struct hclge_dev
*hdev
= vport
->back
;
5294 *auto_neg
= hclge_get_autoneg(handle
);
5296 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5302 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5305 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5308 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5317 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5318 u32 rx_en
, u32 tx_en
)
5320 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5321 struct hclge_dev
*hdev
= vport
->back
;
5322 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5325 fc_autoneg
= hclge_get_autoneg(handle
);
5326 if (auto_neg
!= fc_autoneg
) {
5327 dev_info(&hdev
->pdev
->dev
,
5328 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5332 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5333 dev_info(&hdev
->pdev
->dev
,
5334 "Priority flow control enabled. Cannot set link flow control.\n");
5338 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5341 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5343 /* Only support flow control negotiation for netdev with
5344 * phy attached for now.
5349 return phy_start_aneg(phydev
);
5352 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5353 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5355 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5356 struct hclge_dev
*hdev
= vport
->back
;
5359 *speed
= hdev
->hw
.mac
.speed
;
5361 *duplex
= hdev
->hw
.mac
.duplex
;
5363 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5366 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5368 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5369 struct hclge_dev
*hdev
= vport
->back
;
5372 *media_type
= hdev
->hw
.mac
.media_type
;
5375 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5376 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5378 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5379 struct hclge_dev
*hdev
= vport
->back
;
5380 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5381 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5384 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5385 *tp_mdix
= ETH_TP_MDI_INVALID
;
5389 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5391 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5392 mdix_ctrl
= hnae3_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5393 HCLGE_PHY_MDIX_CTRL_S
);
5395 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5396 mdix
= hnae3_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5397 is_resolved
= hnae3_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5399 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5401 switch (mdix_ctrl
) {
5403 *tp_mdix_ctrl
= ETH_TP_MDI
;
5406 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5409 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5412 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5417 *tp_mdix
= ETH_TP_MDI_INVALID
;
5419 *tp_mdix
= ETH_TP_MDI_X
;
5421 *tp_mdix
= ETH_TP_MDI
;
5424 static int hclge_init_client_instance(struct hnae3_client
*client
,
5425 struct hnae3_ae_dev
*ae_dev
)
5427 struct hclge_dev
*hdev
= ae_dev
->priv
;
5428 struct hclge_vport
*vport
;
5431 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5432 vport
= &hdev
->vport
[i
];
5434 switch (client
->type
) {
5435 case HNAE3_CLIENT_KNIC
:
5437 hdev
->nic_client
= client
;
5438 vport
->nic
.client
= client
;
5439 ret
= client
->ops
->init_instance(&vport
->nic
);
5443 if (hdev
->roce_client
&&
5444 hnae3_dev_roce_supported(hdev
)) {
5445 struct hnae3_client
*rc
= hdev
->roce_client
;
5447 ret
= hclge_init_roce_base_info(vport
);
5451 ret
= rc
->ops
->init_instance(&vport
->roce
);
5457 case HNAE3_CLIENT_UNIC
:
5458 hdev
->nic_client
= client
;
5459 vport
->nic
.client
= client
;
5461 ret
= client
->ops
->init_instance(&vport
->nic
);
5466 case HNAE3_CLIENT_ROCE
:
5467 if (hnae3_dev_roce_supported(hdev
)) {
5468 hdev
->roce_client
= client
;
5469 vport
->roce
.client
= client
;
5472 if (hdev
->roce_client
&& hdev
->nic_client
) {
5473 ret
= hclge_init_roce_base_info(vport
);
5477 ret
= client
->ops
->init_instance(&vport
->roce
);
5487 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5488 struct hnae3_ae_dev
*ae_dev
)
5490 struct hclge_dev
*hdev
= ae_dev
->priv
;
5491 struct hclge_vport
*vport
;
5494 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5495 vport
= &hdev
->vport
[i
];
5496 if (hdev
->roce_client
) {
5497 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5499 hdev
->roce_client
= NULL
;
5500 vport
->roce
.client
= NULL
;
5502 if (client
->type
== HNAE3_CLIENT_ROCE
)
5504 if (client
->ops
->uninit_instance
) {
5505 client
->ops
->uninit_instance(&vport
->nic
, 0);
5506 hdev
->nic_client
= NULL
;
5507 vport
->nic
.client
= NULL
;
5512 static int hclge_pci_init(struct hclge_dev
*hdev
)
5514 struct pci_dev
*pdev
= hdev
->pdev
;
5515 struct hclge_hw
*hw
;
5518 ret
= pci_enable_device(pdev
);
5520 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5524 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5526 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5529 "can't set consistent PCI DMA");
5530 goto err_disable_device
;
5532 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5535 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5537 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5538 goto err_disable_device
;
5541 pci_set_master(pdev
);
5543 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5545 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5547 goto err_clr_master
;
5550 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5554 pci_clear_master(pdev
);
5555 pci_release_regions(pdev
);
5557 pci_disable_device(pdev
);
5562 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5564 struct pci_dev
*pdev
= hdev
->pdev
;
5566 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5567 pci_free_irq_vectors(pdev
);
5568 pci_clear_master(pdev
);
5569 pci_release_mem_regions(pdev
);
5570 pci_disable_device(pdev
);
5573 static void hclge_state_init(struct hclge_dev
*hdev
)
5575 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5576 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5577 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5578 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5579 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5580 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5583 static void hclge_state_uninit(struct hclge_dev
*hdev
)
5585 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5587 if (hdev
->service_timer
.function
)
5588 del_timer_sync(&hdev
->service_timer
);
5589 if (hdev
->service_task
.func
)
5590 cancel_work_sync(&hdev
->service_task
);
5591 if (hdev
->rst_service_task
.func
)
5592 cancel_work_sync(&hdev
->rst_service_task
);
5593 if (hdev
->mbx_service_task
.func
)
5594 cancel_work_sync(&hdev
->mbx_service_task
);
5597 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5599 struct pci_dev
*pdev
= ae_dev
->pdev
;
5600 struct hclge_dev
*hdev
;
5603 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5610 hdev
->ae_dev
= ae_dev
;
5611 hdev
->reset_type
= HNAE3_NONE_RESET
;
5612 hdev
->reset_request
= 0;
5613 hdev
->reset_pending
= 0;
5614 ae_dev
->priv
= hdev
;
5616 ret
= hclge_pci_init(hdev
);
5618 dev_err(&pdev
->dev
, "PCI init failed\n");
5622 /* Firmware command queue initialize */
5623 ret
= hclge_cmd_queue_init(hdev
);
5625 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5626 goto err_pci_uninit
;
5629 /* Firmware command initialize */
5630 ret
= hclge_cmd_init(hdev
);
5632 goto err_cmd_uninit
;
5634 ret
= hclge_get_cap(hdev
);
5636 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5638 goto err_cmd_uninit
;
5641 ret
= hclge_configure(hdev
);
5643 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5644 goto err_cmd_uninit
;
5647 ret
= hclge_init_msi(hdev
);
5649 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5650 goto err_cmd_uninit
;
5653 ret
= hclge_misc_irq_init(hdev
);
5656 "Misc IRQ(vector0) init error, ret = %d.\n",
5658 goto err_msi_uninit
;
5661 ret
= hclge_alloc_tqps(hdev
);
5663 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5664 goto err_msi_irq_uninit
;
5667 ret
= hclge_alloc_vport(hdev
);
5669 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5670 goto err_msi_irq_uninit
;
5673 ret
= hclge_map_tqp(hdev
);
5675 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5676 goto err_msi_irq_uninit
;
5679 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5680 ret
= hclge_mac_mdio_config(hdev
);
5682 dev_err(&hdev
->pdev
->dev
,
5683 "mdio config fail ret=%d\n", ret
);
5684 goto err_msi_irq_uninit
;
5688 ret
= hclge_mac_init(hdev
);
5690 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5691 goto err_mdiobus_unreg
;
5694 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5696 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5697 goto err_mdiobus_unreg
;
5700 ret
= hclge_init_vlan_config(hdev
);
5702 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5703 goto err_mdiobus_unreg
;
5706 ret
= hclge_tm_schd_init(hdev
);
5708 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5709 goto err_mdiobus_unreg
;
5712 hclge_rss_init_cfg(hdev
);
5713 ret
= hclge_rss_init_hw(hdev
);
5715 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5716 goto err_mdiobus_unreg
;
5719 ret
= init_mgr_tbl(hdev
);
5721 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5722 goto err_mdiobus_unreg
;
5725 hclge_dcb_ops_set(hdev
);
5727 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5728 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5729 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5730 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5732 hclge_clear_all_event_cause(hdev
);
5734 /* Enable MISC vector(vector0) */
5735 hclge_enable_vector(&hdev
->misc_vector
, true);
5737 hclge_state_init(hdev
);
5739 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5743 if (hdev
->hw
.mac
.phydev
)
5744 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5746 hclge_misc_irq_uninit(hdev
);
5748 pci_free_irq_vectors(pdev
);
5750 hclge_destroy_cmd_queue(&hdev
->hw
);
5752 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5753 pci_clear_master(pdev
);
5754 pci_release_regions(pdev
);
5755 pci_disable_device(pdev
);
5760 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5762 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5765 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5767 struct hclge_dev
*hdev
= ae_dev
->priv
;
5768 struct pci_dev
*pdev
= ae_dev
->pdev
;
5771 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5773 hclge_stats_clear(hdev
);
5774 memset(hdev
->vlan_table
, 0, sizeof(hdev
->vlan_table
));
5776 ret
= hclge_cmd_init(hdev
);
5778 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5782 ret
= hclge_get_cap(hdev
);
5784 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5789 ret
= hclge_configure(hdev
);
5791 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5795 ret
= hclge_map_tqp(hdev
);
5797 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5801 ret
= hclge_mac_init(hdev
);
5803 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5807 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5809 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5813 ret
= hclge_init_vlan_config(hdev
);
5815 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5819 ret
= hclge_tm_init_hw(hdev
);
5821 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5825 ret
= hclge_rss_init_hw(hdev
);
5827 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5831 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5837 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5839 struct hclge_dev
*hdev
= ae_dev
->priv
;
5840 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5842 hclge_state_uninit(hdev
);
5845 mdiobus_unregister(mac
->mdio_bus
);
5847 /* Disable MISC vector(vector0) */
5848 hclge_enable_vector(&hdev
->misc_vector
, false);
5849 synchronize_irq(hdev
->misc_vector
.vector_irq
);
5851 hclge_destroy_cmd_queue(&hdev
->hw
);
5852 hclge_misc_irq_uninit(hdev
);
5853 hclge_pci_uninit(hdev
);
5854 ae_dev
->priv
= NULL
;
5857 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5859 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5860 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5861 struct hclge_dev
*hdev
= vport
->back
;
5863 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5866 static void hclge_get_channels(struct hnae3_handle
*handle
,
5867 struct ethtool_channels
*ch
)
5869 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5871 ch
->max_combined
= hclge_get_max_channels(handle
);
5872 ch
->other_count
= 1;
5874 ch
->combined_count
= vport
->alloc_tqps
;
5877 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5878 u16
*free_tqps
, u16
*max_rss_size
)
5880 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5881 struct hclge_dev
*hdev
= vport
->back
;
5885 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5886 if (!hdev
->htqp
[i
].alloced
)
5889 *free_tqps
= temp_tqps
;
5890 *max_rss_size
= hdev
->rss_size_max
;
5893 static void hclge_release_tqp(struct hclge_vport
*vport
)
5895 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5896 struct hclge_dev
*hdev
= vport
->back
;
5899 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5900 struct hclge_tqp
*tqp
=
5901 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5903 tqp
->q
.handle
= NULL
;
5904 tqp
->q
.tqp_index
= 0;
5905 tqp
->alloced
= false;
5908 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5912 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5914 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5915 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5916 struct hclge_dev
*hdev
= vport
->back
;
5917 int cur_rss_size
= kinfo
->rss_size
;
5918 int cur_tqps
= kinfo
->num_tqps
;
5919 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5920 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5921 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5926 hclge_release_tqp(vport
);
5928 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5930 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5934 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5936 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5940 ret
= hclge_tm_schd_init(hdev
);
5942 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5946 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5947 roundup_size
= ilog2(roundup_size
);
5948 /* Set the RSS TC mode according to the new RSS size */
5949 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5952 if (!(hdev
->hw_tc_map
& BIT(i
)))
5956 tc_size
[i
] = roundup_size
;
5957 tc_offset
[i
] = kinfo
->rss_size
* i
;
5959 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5963 /* Reinitializes the rss indirect table according to the new RSS size */
5964 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5968 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5969 rss_indir
[i
] = i
% kinfo
->rss_size
;
5971 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5973 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5979 dev_info(&hdev
->pdev
->dev
,
5980 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5981 cur_rss_size
, kinfo
->rss_size
,
5982 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5987 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5988 u32
*regs_num_64_bit
)
5990 struct hclge_desc desc
;
5994 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
5995 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5997 dev_err(&hdev
->pdev
->dev
,
5998 "Query register number cmd failed, ret = %d.\n", ret
);
6002 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
6003 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
6005 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
6012 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6015 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6017 struct hclge_desc
*desc
;
6018 u32
*reg_val
= data
;
6027 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
6028 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6032 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
6033 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6035 dev_err(&hdev
->pdev
->dev
,
6036 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
6041 for (i
= 0; i
< cmd_num
; i
++) {
6043 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
6044 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
6046 desc_data
= (__le32
*)(&desc
[i
]);
6047 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
6049 for (k
= 0; k
< n
; k
++) {
6050 *reg_val
++ = le32_to_cpu(*desc_data
++);
6062 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6065 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6067 struct hclge_desc
*desc
;
6068 u64
*reg_val
= data
;
6077 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
6078 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6082 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
6083 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6085 dev_err(&hdev
->pdev
->dev
,
6086 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
6091 for (i
= 0; i
< cmd_num
; i
++) {
6093 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
6094 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
6096 desc_data
= (__le64
*)(&desc
[i
]);
6097 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
6099 for (k
= 0; k
< n
; k
++) {
6100 *reg_val
++ = le64_to_cpu(*desc_data
++);
6112 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
6114 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6115 struct hclge_dev
*hdev
= vport
->back
;
6116 u32 regs_num_32_bit
, regs_num_64_bit
;
6119 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6121 dev_err(&hdev
->pdev
->dev
,
6122 "Get register number failed, ret = %d.\n", ret
);
6126 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
6129 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
6132 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6133 struct hclge_dev
*hdev
= vport
->back
;
6134 u32 regs_num_32_bit
, regs_num_64_bit
;
6137 *version
= hdev
->fw_version
;
6139 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6141 dev_err(&hdev
->pdev
->dev
,
6142 "Get register number failed, ret = %d.\n", ret
);
6146 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
6148 dev_err(&hdev
->pdev
->dev
,
6149 "Get 32 bit register failed, ret = %d.\n", ret
);
6153 data
= (u32
*)data
+ regs_num_32_bit
;
6154 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
6157 dev_err(&hdev
->pdev
->dev
,
6158 "Get 64 bit register failed, ret = %d.\n", ret
);
6161 static int hclge_set_led_status(struct hclge_dev
*hdev
, u8 locate_led_status
)
6163 struct hclge_set_led_state_cmd
*req
;
6164 struct hclge_desc desc
;
6167 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6169 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6170 hnae3_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6171 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6173 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6175 dev_err(&hdev
->pdev
->dev
,
6176 "Send set led state cmd error, ret =%d\n", ret
);
6181 enum hclge_led_status
{
6184 HCLGE_LED_NO_CHANGE
= 0xFF,
6187 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6188 enum ethtool_phys_id_state status
)
6190 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6191 struct hclge_dev
*hdev
= vport
->back
;
6194 case ETHTOOL_ID_ACTIVE
:
6195 return hclge_set_led_status(hdev
, HCLGE_LED_ON
);
6196 case ETHTOOL_ID_INACTIVE
:
6197 return hclge_set_led_status(hdev
, HCLGE_LED_OFF
);
6203 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6204 unsigned long *supported
,
6205 unsigned long *advertising
)
6207 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6208 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6209 struct hclge_dev
*hdev
= vport
->back
;
6210 unsigned int idx
= 0;
6212 for (; idx
< size
; idx
++) {
6213 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6214 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6218 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6221 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6222 struct hclge_dev
*hdev
= vport
->back
;
6223 u8 media_type
= hdev
->hw
.mac
.media_type
;
6225 switch (media_type
) {
6226 case HNAE3_MEDIA_TYPE_FIBER
:
6227 *port_type
= PORT_FIBRE
;
6229 case HNAE3_MEDIA_TYPE_COPPER
:
6230 *port_type
= PORT_TP
;
6232 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6234 *port_type
= PORT_OTHER
;
6239 static const struct hnae3_ae_ops hclge_ops
= {
6240 .init_ae_dev
= hclge_init_ae_dev
,
6241 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6242 .init_client_instance
= hclge_init_client_instance
,
6243 .uninit_client_instance
= hclge_uninit_client_instance
,
6244 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6245 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6246 .get_vector
= hclge_get_vector
,
6247 .put_vector
= hclge_put_vector
,
6248 .set_promisc_mode
= hclge_set_promisc_mode
,
6249 .set_loopback
= hclge_set_loopback
,
6250 .start
= hclge_ae_start
,
6251 .stop
= hclge_ae_stop
,
6252 .get_status
= hclge_get_status
,
6253 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6254 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6255 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6256 .get_media_type
= hclge_get_media_type
,
6257 .get_rss_key_size
= hclge_get_rss_key_size
,
6258 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6259 .get_rss
= hclge_get_rss
,
6260 .set_rss
= hclge_set_rss
,
6261 .set_rss_tuple
= hclge_set_rss_tuple
,
6262 .get_rss_tuple
= hclge_get_rss_tuple
,
6263 .get_tc_size
= hclge_get_tc_size
,
6264 .get_mac_addr
= hclge_get_mac_addr
,
6265 .set_mac_addr
= hclge_set_mac_addr
,
6266 .add_uc_addr
= hclge_add_uc_addr
,
6267 .rm_uc_addr
= hclge_rm_uc_addr
,
6268 .add_mc_addr
= hclge_add_mc_addr
,
6269 .rm_mc_addr
= hclge_rm_mc_addr
,
6270 .update_mta_status
= hclge_update_mta_status
,
6271 .set_autoneg
= hclge_set_autoneg
,
6272 .get_autoneg
= hclge_get_autoneg
,
6273 .get_pauseparam
= hclge_get_pauseparam
,
6274 .set_pauseparam
= hclge_set_pauseparam
,
6275 .set_mtu
= hclge_set_mtu
,
6276 .reset_queue
= hclge_reset_tqp
,
6277 .get_stats
= hclge_get_stats
,
6278 .update_stats
= hclge_update_stats
,
6279 .get_strings
= hclge_get_strings
,
6280 .get_sset_count
= hclge_get_sset_count
,
6281 .get_fw_version
= hclge_get_fw_version
,
6282 .get_mdix_mode
= hclge_get_mdix_mode
,
6283 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6284 .set_vlan_filter
= hclge_set_vlan_filter
,
6285 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6286 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6287 .reset_event
= hclge_reset_event
,
6288 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6289 .set_channels
= hclge_set_channels
,
6290 .get_channels
= hclge_get_channels
,
6291 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6292 .get_regs_len
= hclge_get_regs_len
,
6293 .get_regs
= hclge_get_regs
,
6294 .set_led_id
= hclge_set_led_id
,
6295 .get_link_mode
= hclge_get_link_mode
,
6296 .get_port_type
= hclge_get_port_type
,
6299 static struct hnae3_ae_algo ae_algo
= {
6301 .pdev_id_table
= ae_algo_pci_tbl
,
6304 static int hclge_init(void)
6306 pr_info("%s is initializing\n", HCLGE_NAME
);
6308 hnae3_register_ae_algo(&ae_algo
);
6313 static void hclge_exit(void)
6315 hnae3_unregister_ae_algo(&ae_algo
);
6317 module_init(hclge_init
);
6318 module_exit(hclge_exit
);
6320 MODULE_LICENSE("GPL");
6321 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6322 MODULE_DESCRIPTION("HCLGE Driver");
6323 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob