2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
43 static struct hnae3_ae_algo ae_algo
;
45 static const struct pci_device_id ae_algo_pci_tbl
[] = {
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
53 /* required last entry */
57 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
59 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
61 "Serdes Loopback test",
65 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
104 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
229 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
393 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
395 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
396 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
397 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap
= 0x1,
403 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
405 #define HCLGE_64_BIT_CMD_NUM 5
406 #define HCLGE_64_BIT_RTN_DATANUM 4
407 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
408 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
413 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
414 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
416 dev_err(&hdev
->pdev
->dev
,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
421 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
422 if (unlikely(i
== 0)) {
423 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
424 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
426 desc_data
= (__le64
*)(&desc
[i
]);
427 n
= HCLGE_64_BIT_RTN_DATANUM
;
429 for (k
= 0; k
< n
; k
++) {
430 *data
++ += le64_to_cpu(*desc_data
);
438 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
440 stats
->pkt_curr_buf_cnt
= 0;
441 stats
->pkt_curr_buf_tc0_cnt
= 0;
442 stats
->pkt_curr_buf_tc1_cnt
= 0;
443 stats
->pkt_curr_buf_tc2_cnt
= 0;
444 stats
->pkt_curr_buf_tc3_cnt
= 0;
445 stats
->pkt_curr_buf_tc4_cnt
= 0;
446 stats
->pkt_curr_buf_tc5_cnt
= 0;
447 stats
->pkt_curr_buf_tc6_cnt
= 0;
448 stats
->pkt_curr_buf_tc7_cnt
= 0;
451 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
453 #define HCLGE_32_BIT_CMD_NUM 8
454 #define HCLGE_32_BIT_RTN_DATANUM 8
456 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
457 struct hclge_32_bit_stats
*all_32_bit_stats
;
463 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
464 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
466 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
467 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
469 dev_err(&hdev
->pdev
->dev
,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
475 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
476 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
477 if (unlikely(i
== 0)) {
478 __le16
*desc_data_16bit
;
480 all_32_bit_stats
->igu_rx_err_pkt
+=
481 le32_to_cpu(desc
[i
].data
[0]);
483 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
484 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
485 le16_to_cpu(*desc_data_16bit
);
488 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
489 le16_to_cpu(*desc_data_16bit
);
491 desc_data
= &desc
[i
].data
[2];
492 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
494 desc_data
= (__le32
*)&desc
[i
];
495 n
= HCLGE_32_BIT_RTN_DATANUM
;
497 for (k
= 0; k
< n
; k
++) {
498 *data
++ += le32_to_cpu(*desc_data
);
506 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
508 #define HCLGE_MAC_CMD_NUM 21
509 #define HCLGE_RTN_DATA_NUM 4
511 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
512 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
517 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
518 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
520 dev_err(&hdev
->pdev
->dev
,
521 "Get MAC pkt stats fail, status = %d.\n", ret
);
526 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
527 if (unlikely(i
== 0)) {
528 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
529 n
= HCLGE_RTN_DATA_NUM
- 2;
531 desc_data
= (__le64
*)(&desc
[i
]);
532 n
= HCLGE_RTN_DATA_NUM
;
534 for (k
= 0; k
< n
; k
++) {
535 *data
++ += le64_to_cpu(*desc_data
);
543 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
545 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
546 struct hclge_vport
*vport
= hclge_get_vport(handle
);
547 struct hclge_dev
*hdev
= vport
->back
;
548 struct hnae3_queue
*queue
;
549 struct hclge_desc desc
[1];
550 struct hclge_tqp
*tqp
;
553 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
554 queue
= handle
->kinfo
.tqp
[i
];
555 tqp
= container_of(queue
, struct hclge_tqp
, q
);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc
[0],
558 HCLGE_OPC_QUERY_RX_STATUS
,
561 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
562 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
564 dev_err(&hdev
->pdev
->dev
,
565 "Query tqp stat fail, status = %d,queue = %d\n",
569 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
570 le32_to_cpu(desc
[0].data
[1]);
573 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
574 queue
= handle
->kinfo
.tqp
[i
];
575 tqp
= container_of(queue
, struct hclge_tqp
, q
);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc
[0],
578 HCLGE_OPC_QUERY_TX_STATUS
,
581 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
582 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
584 dev_err(&hdev
->pdev
->dev
,
585 "Query tqp stat fail, status = %d,queue = %d\n",
589 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
590 le32_to_cpu(desc
[0].data
[1]);
596 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
598 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
599 struct hclge_tqp
*tqp
;
603 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
604 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
605 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
608 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
609 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
610 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
616 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
618 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
620 return kinfo
->num_tqps
* (2);
623 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
625 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
629 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
630 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
631 struct hclge_tqp
, q
);
632 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
634 buff
= buff
+ ETH_GSTRING_LEN
;
637 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
638 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
639 struct hclge_tqp
, q
);
640 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
642 buff
= buff
+ ETH_GSTRING_LEN
;
648 static u64
*hclge_comm_get_stats(void *comm_stats
,
649 const struct hclge_comm_stats_str strs
[],
655 for (i
= 0; i
< size
; i
++)
656 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
661 static u8
*hclge_comm_get_strings(u32 stringset
,
662 const struct hclge_comm_stats_str strs
[],
665 char *buff
= (char *)data
;
668 if (stringset
!= ETH_SS_STATS
)
671 for (i
= 0; i
< size
; i
++) {
672 snprintf(buff
, ETH_GSTRING_LEN
,
674 buff
= buff
+ ETH_GSTRING_LEN
;
680 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
681 struct net_device_stats
*net_stats
)
683 net_stats
->tx_dropped
= 0;
684 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
685 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
686 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
688 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
689 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
690 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
691 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
692 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
694 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
695 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
697 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
698 net_stats
->rx_length_errors
=
699 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
700 net_stats
->rx_length_errors
+=
701 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
702 net_stats
->rx_over_errors
=
703 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
706 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
708 struct hnae3_handle
*handle
;
711 handle
= &hdev
->vport
[0].nic
;
712 if (handle
->client
) {
713 status
= hclge_tqps_update_stats(handle
);
715 dev_err(&hdev
->pdev
->dev
,
716 "Update TQPS stats fail, status = %d.\n",
721 status
= hclge_mac_update_stats(hdev
);
723 dev_err(&hdev
->pdev
->dev
,
724 "Update MAC stats fail, status = %d.\n", status
);
726 status
= hclge_32_bit_update_stats(hdev
);
728 dev_err(&hdev
->pdev
->dev
,
729 "Update 32 bit stats fail, status = %d.\n",
732 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
735 static void hclge_update_stats(struct hnae3_handle
*handle
,
736 struct net_device_stats
*net_stats
)
738 struct hclge_vport
*vport
= hclge_get_vport(handle
);
739 struct hclge_dev
*hdev
= vport
->back
;
740 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
746 status
= hclge_mac_update_stats(hdev
);
748 dev_err(&hdev
->pdev
->dev
,
749 "Update MAC stats fail, status = %d.\n",
752 status
= hclge_32_bit_update_stats(hdev
);
754 dev_err(&hdev
->pdev
->dev
,
755 "Update 32 bit stats fail, status = %d.\n",
758 status
= hclge_64_bit_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update 64 bit stats fail, status = %d.\n",
764 status
= hclge_tqps_update_stats(handle
);
766 dev_err(&hdev
->pdev
->dev
,
767 "Update TQPS stats fail, status = %d.\n",
770 hclge_update_netstat(hw_stats
, net_stats
);
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
775 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
777 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
779 struct hclge_vport
*vport
= hclge_get_vport(handle
);
780 struct hclge_dev
*hdev
= vport
->back
;
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
788 if (stringset
== ETH_SS_TEST
) {
789 /* clear loopback bit flags at first */
790 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
791 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
792 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
793 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
795 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
799 handle
->flags
|= HNAE3_SUPPORT_SERDES_LOOPBACK
;
800 } else if (stringset
== ETH_SS_STATS
) {
801 count
= ARRAY_SIZE(g_mac_stats_string
) +
802 ARRAY_SIZE(g_all_32bit_stats_string
) +
803 ARRAY_SIZE(g_all_64bit_stats_string
) +
804 hclge_tqps_get_sset_count(handle
, stringset
);
810 static void hclge_get_strings(struct hnae3_handle
*handle
,
814 u8
*p
= (char *)data
;
817 if (stringset
== ETH_SS_STATS
) {
818 size
= ARRAY_SIZE(g_mac_stats_string
);
819 p
= hclge_comm_get_strings(stringset
,
823 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
824 p
= hclge_comm_get_strings(stringset
,
825 g_all_32bit_stats_string
,
828 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
829 p
= hclge_comm_get_strings(stringset
,
830 g_all_64bit_stats_string
,
833 p
= hclge_tqps_get_strings(handle
, p
);
834 } else if (stringset
== ETH_SS_TEST
) {
835 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
837 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
839 p
+= ETH_GSTRING_LEN
;
841 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
843 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
845 p
+= ETH_GSTRING_LEN
;
847 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
849 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
851 p
+= ETH_GSTRING_LEN
;
856 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
858 struct hclge_vport
*vport
= hclge_get_vport(handle
);
859 struct hclge_dev
*hdev
= vport
->back
;
862 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
864 ARRAY_SIZE(g_mac_stats_string
),
866 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
867 g_all_32bit_stats_string
,
868 ARRAY_SIZE(g_all_32bit_stats_string
),
870 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
871 g_all_64bit_stats_string
,
872 ARRAY_SIZE(g_all_64bit_stats_string
),
874 p
= hclge_tqps_get_stats(handle
, p
);
877 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
878 struct hclge_func_status_cmd
*status
)
880 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
883 /* Set the pf to main pf */
884 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
885 hdev
->flag
|= HCLGE_FLAG_MAIN
;
887 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
892 static int hclge_query_function_status(struct hclge_dev
*hdev
)
894 struct hclge_func_status_cmd
*req
;
895 struct hclge_desc desc
;
899 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
900 req
= (struct hclge_func_status_cmd
*)desc
.data
;
903 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
905 dev_err(&hdev
->pdev
->dev
,
906 "query function status failed %d.\n",
912 /* Check pf reset is done */
915 usleep_range(1000, 2000);
916 } while (timeout
++ < 5);
918 ret
= hclge_parse_func_status(hdev
, req
);
923 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
925 struct hclge_pf_res_cmd
*req
;
926 struct hclge_desc desc
;
929 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
930 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
932 dev_err(&hdev
->pdev
->dev
,
933 "query pf resource failed %d.\n", ret
);
937 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
938 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
939 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
941 if (hnae3_dev_roce_supported(hdev
)) {
943 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
944 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
946 /* PF should have NIC vectors and Roce vectors,
947 * NIC vectors are queued before Roce vectors.
949 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
952 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
953 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
959 static int hclge_parse_speed(int speed_cmd
, int *speed
)
963 *speed
= HCLGE_MAC_SPEED_10M
;
966 *speed
= HCLGE_MAC_SPEED_100M
;
969 *speed
= HCLGE_MAC_SPEED_1G
;
972 *speed
= HCLGE_MAC_SPEED_10G
;
975 *speed
= HCLGE_MAC_SPEED_25G
;
978 *speed
= HCLGE_MAC_SPEED_40G
;
981 *speed
= HCLGE_MAC_SPEED_50G
;
984 *speed
= HCLGE_MAC_SPEED_100G
;
993 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
996 unsigned long *supported
= hdev
->hw
.mac
.supported
;
998 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
999 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1002 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1003 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1006 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1007 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1010 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1011 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1014 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1015 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1018 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1019 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1022 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1024 u8 media_type
= hdev
->hw
.mac
.media_type
;
1026 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1029 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1032 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1034 struct hclge_cfg_param_cmd
*req
;
1035 u64 mac_addr_tmp_high
;
1039 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1041 /* get the configuration */
1042 cfg
->vmdq_vport_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1045 cfg
->tc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1046 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1047 cfg
->tqp_desc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1048 HCLGE_CFG_TQP_DESC_N_M
,
1049 HCLGE_CFG_TQP_DESC_N_S
);
1051 cfg
->phy_addr
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1052 HCLGE_CFG_PHY_ADDR_M
,
1053 HCLGE_CFG_PHY_ADDR_S
);
1054 cfg
->media_type
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1055 HCLGE_CFG_MEDIA_TP_M
,
1056 HCLGE_CFG_MEDIA_TP_S
);
1057 cfg
->rx_buf_len
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1058 HCLGE_CFG_RX_BUF_LEN_M
,
1059 HCLGE_CFG_RX_BUF_LEN_S
);
1060 /* get mac_address */
1061 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1062 mac_addr_tmp_high
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1063 HCLGE_CFG_MAC_ADDR_H_M
,
1064 HCLGE_CFG_MAC_ADDR_H_S
);
1066 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1068 cfg
->default_speed
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1069 HCLGE_CFG_DEFAULT_SPEED_M
,
1070 HCLGE_CFG_DEFAULT_SPEED_S
);
1071 cfg
->rss_size_max
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1072 HCLGE_CFG_RSS_SIZE_M
,
1073 HCLGE_CFG_RSS_SIZE_S
);
1075 for (i
= 0; i
< ETH_ALEN
; i
++)
1076 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1078 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1079 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1081 cfg
->speed_ability
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1082 HCLGE_CFG_SPEED_ABILITY_M
,
1083 HCLGE_CFG_SPEED_ABILITY_S
);
1086 /* hclge_get_cfg: query the static parameter from flash
1087 * @hdev: pointer to struct hclge_dev
1088 * @hcfg: the config structure to be getted
1090 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1092 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1093 struct hclge_cfg_param_cmd
*req
;
1096 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1099 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1100 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1102 hnae3_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1103 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1104 /* Len should be united by 4 bytes when send to hardware */
1105 hnae3_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1106 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1107 req
->offset
= cpu_to_le32(offset
);
1110 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1112 dev_err(&hdev
->pdev
->dev
, "get config failed %d.\n", ret
);
1116 hclge_parse_cfg(hcfg
, desc
);
1121 static int hclge_get_cap(struct hclge_dev
*hdev
)
1125 ret
= hclge_query_function_status(hdev
);
1127 dev_err(&hdev
->pdev
->dev
,
1128 "query function status error %d.\n", ret
);
1132 /* get pf resource */
1133 ret
= hclge_query_pf_resource(hdev
);
1135 dev_err(&hdev
->pdev
->dev
, "query pf resource error %d.\n", ret
);
1140 static int hclge_configure(struct hclge_dev
*hdev
)
1142 struct hclge_cfg cfg
;
1145 ret
= hclge_get_cfg(hdev
, &cfg
);
1147 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1151 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1152 hdev
->base_tqp_pid
= 0;
1153 hdev
->rss_size_max
= cfg
.rss_size_max
;
1154 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1155 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1156 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1157 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1158 hdev
->num_desc
= cfg
.tqp_desc_num
;
1159 hdev
->tm_info
.num_pg
= 1;
1160 hdev
->tc_max
= cfg
.tc_num
;
1161 hdev
->tm_info
.hw_pfc_map
= 0;
1163 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1165 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1169 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1171 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1172 (hdev
->tc_max
< 1)) {
1173 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1178 /* Dev does not support DCB */
1179 if (!hnae3_dev_dcb_supported(hdev
)) {
1183 hdev
->pfc_max
= hdev
->tc_max
;
1186 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1188 /* Currently not support uncontiuous tc */
1189 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1190 hnae3_set_bit(hdev
->hw_tc_map
, i
, 1);
1192 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1197 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1200 struct hclge_cfg_tso_status_cmd
*req
;
1201 struct hclge_desc desc
;
1204 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1206 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1209 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1210 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1211 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1214 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1215 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1216 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1218 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1221 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1223 struct hclge_tqp
*tqp
;
1226 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1227 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1233 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1234 tqp
->dev
= &hdev
->pdev
->dev
;
1237 tqp
->q
.ae_algo
= &ae_algo
;
1238 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1239 tqp
->q
.desc_num
= hdev
->num_desc
;
1240 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1241 i
* HCLGE_TQP_REG_SIZE
;
1249 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1250 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1252 struct hclge_tqp_map_cmd
*req
;
1253 struct hclge_desc desc
;
1256 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1258 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1259 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1260 req
->tqp_vf
= func_id
;
1261 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1262 1 << HCLGE_TQP_MAP_EN_B
;
1263 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1265 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1267 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n", ret
);
1272 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1273 struct hnae3_queue
**tqp
, u16 num_tqps
)
1275 struct hclge_dev
*hdev
= vport
->back
;
1278 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1279 alloced
< num_tqps
; i
++) {
1280 if (!hdev
->htqp
[i
].alloced
) {
1281 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1282 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1283 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1284 hdev
->htqp
[i
].alloced
= true;
1288 vport
->alloc_tqps
= num_tqps
;
1293 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1295 struct hnae3_handle
*nic
= &vport
->nic
;
1296 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1297 struct hclge_dev
*hdev
= vport
->back
;
1300 kinfo
->num_desc
= hdev
->num_desc
;
1301 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1302 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1304 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1305 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1307 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1308 if (hdev
->hw_tc_map
& BIT(i
)) {
1309 kinfo
->tc_info
[i
].enable
= true;
1310 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1311 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1312 kinfo
->tc_info
[i
].tc
= i
;
1314 /* Set to default queue if TC is disable */
1315 kinfo
->tc_info
[i
].enable
= false;
1316 kinfo
->tc_info
[i
].tqp_offset
= 0;
1317 kinfo
->tc_info
[i
].tqp_count
= 1;
1318 kinfo
->tc_info
[i
].tc
= 0;
1322 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1323 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1327 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1329 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1334 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1335 struct hclge_vport
*vport
)
1337 struct hnae3_handle
*nic
= &vport
->nic
;
1338 struct hnae3_knic_private_info
*kinfo
;
1341 kinfo
= &nic
->kinfo
;
1342 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1343 struct hclge_tqp
*q
=
1344 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1348 is_pf
= !(vport
->vport_id
);
1349 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1358 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1360 struct hclge_vport
*vport
= hdev
->vport
;
1363 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1364 for (i
= 0; i
< num_vport
; i
++) {
1367 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1377 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1379 /* this would be initialized later */
1382 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1384 struct hnae3_handle
*nic
= &vport
->nic
;
1385 struct hclge_dev
*hdev
= vport
->back
;
1388 nic
->pdev
= hdev
->pdev
;
1389 nic
->ae_algo
= &ae_algo
;
1390 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1392 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1393 ret
= hclge_knic_setup(vport
, num_tqps
);
1395 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1400 hclge_unic_setup(vport
, num_tqps
);
1406 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1408 struct pci_dev
*pdev
= hdev
->pdev
;
1409 struct hclge_vport
*vport
;
1415 /* We need to alloc a vport for main NIC of PF */
1416 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1418 if (hdev
->num_tqps
< num_vport
) {
1419 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1420 hdev
->num_tqps
, num_vport
);
1424 /* Alloc the same number of TQPs for every vport */
1425 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1426 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1428 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1433 hdev
->vport
= vport
;
1434 hdev
->num_alloc_vport
= num_vport
;
1436 if (IS_ENABLED(CONFIG_PCI_IOV
))
1437 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1439 for (i
= 0; i
< num_vport
; i
++) {
1441 vport
->vport_id
= i
;
1444 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1446 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1449 "vport setup failed for vport %d, %d\n",
1460 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1461 struct hclge_pkt_buf_alloc
*buf_alloc
)
1463 /* TX buffer size is unit by 128 byte */
1464 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1465 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1466 struct hclge_tx_buff_alloc_cmd
*req
;
1467 struct hclge_desc desc
;
1471 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1473 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1474 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1475 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1477 req
->tx_pkt_buff
[i
] =
1478 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1479 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1482 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1484 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1490 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1491 struct hclge_pkt_buf_alloc
*buf_alloc
)
1493 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1496 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc failed %d\n", ret
);
1501 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1505 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1506 if (hdev
->hw_tc_map
& BIT(i
))
1511 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1515 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1516 if (hdev
->hw_tc_map
& BIT(i
) &&
1517 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1522 /* Get the number of pfc enabled TCs, which have private buffer */
1523 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1524 struct hclge_pkt_buf_alloc
*buf_alloc
)
1526 struct hclge_priv_buf
*priv
;
1529 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1530 priv
= &buf_alloc
->priv_buf
[i
];
1531 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1539 /* Get the number of pfc disabled TCs, which have private buffer */
1540 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1541 struct hclge_pkt_buf_alloc
*buf_alloc
)
1543 struct hclge_priv_buf
*priv
;
1546 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1547 priv
= &buf_alloc
->priv_buf
[i
];
1548 if (hdev
->hw_tc_map
& BIT(i
) &&
1549 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1557 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1559 struct hclge_priv_buf
*priv
;
1563 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1564 priv
= &buf_alloc
->priv_buf
[i
];
1566 rx_priv
+= priv
->buf_size
;
1571 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1573 u32 i
, total_tx_size
= 0;
1575 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1576 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1578 return total_tx_size
;
1581 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1582 struct hclge_pkt_buf_alloc
*buf_alloc
,
1585 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1586 int tc_num
, pfc_enable_num
;
1591 tc_num
= hclge_get_tc_num(hdev
);
1592 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1594 if (hnae3_dev_dcb_supported(hdev
))
1595 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1597 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1599 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1600 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1602 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1604 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1605 if (rx_all
<= rx_priv
+ shared_std
)
1608 shared_buf
= rx_all
- rx_priv
;
1609 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1610 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1611 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1613 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1614 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1615 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1616 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1617 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1619 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1620 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1627 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1628 struct hclge_pkt_buf_alloc
*buf_alloc
)
1632 total_size
= hdev
->pkt_buf_size
;
1634 /* alloc tx buffer for all enabled tc */
1635 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1636 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1638 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1641 if (hdev
->hw_tc_map
& BIT(i
))
1642 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1644 priv
->tx_buf_size
= 0;
1646 total_size
-= priv
->tx_buf_size
;
1652 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1653 * @hdev: pointer to struct hclge_dev
1654 * @buf_alloc: pointer to buffer calculation data
1655 * @return: 0: calculate sucessful, negative: fail
1657 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1658 struct hclge_pkt_buf_alloc
*buf_alloc
)
1660 u32 rx_all
= hdev
->pkt_buf_size
;
1661 int no_pfc_priv_num
, pfc_priv_num
;
1662 struct hclge_priv_buf
*priv
;
1665 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1667 /* When DCB is not supported, rx private
1668 * buffer is not allocated.
1670 if (!hnae3_dev_dcb_supported(hdev
)) {
1671 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1677 /* step 1, try to alloc private buffer for all enabled tc */
1678 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1679 priv
= &buf_alloc
->priv_buf
[i
];
1680 if (hdev
->hw_tc_map
& BIT(i
)) {
1682 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1683 priv
->wl
.low
= hdev
->mps
;
1684 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1685 priv
->buf_size
= priv
->wl
.high
+
1689 priv
->wl
.high
= 2 * hdev
->mps
;
1690 priv
->buf_size
= priv
->wl
.high
;
1700 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1703 /* step 2, try to decrease the buffer size of
1704 * no pfc TC's private buffer
1706 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1707 priv
= &buf_alloc
->priv_buf
[i
];
1714 if (!(hdev
->hw_tc_map
& BIT(i
)))
1719 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1721 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1722 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1725 priv
->wl
.high
= hdev
->mps
;
1726 priv
->buf_size
= priv
->wl
.high
;
1730 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1733 /* step 3, try to reduce the number of pfc disabled TCs,
1734 * which have private buffer
1736 /* get the total no pfc enable TC number, which have private buffer */
1737 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1739 /* let the last to be cleared first */
1740 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1741 priv
= &buf_alloc
->priv_buf
[i
];
1743 if (hdev
->hw_tc_map
& BIT(i
) &&
1744 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1745 /* Clear the no pfc TC private buffer */
1753 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1754 no_pfc_priv_num
== 0)
1758 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1761 /* step 4, try to reduce the number of pfc enabled TCs
1762 * which have private buffer.
1764 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1766 /* let the last to be cleared first */
1767 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1768 priv
= &buf_alloc
->priv_buf
[i
];
1770 if (hdev
->hw_tc_map
& BIT(i
) &&
1771 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1772 /* Reduce the number of pfc TC with private buffer */
1780 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1784 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1790 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1791 struct hclge_pkt_buf_alloc
*buf_alloc
)
1793 struct hclge_rx_priv_buff_cmd
*req
;
1794 struct hclge_desc desc
;
1798 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1799 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1801 /* Alloc private buffer TCs */
1802 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1803 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1806 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1808 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1812 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1813 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1815 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1817 dev_err(&hdev
->pdev
->dev
,
1818 "rx private buffer alloc cmd failed %d\n", ret
);
1823 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1825 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1826 struct hclge_pkt_buf_alloc
*buf_alloc
)
1828 struct hclge_rx_priv_wl_buf
*req
;
1829 struct hclge_priv_buf
*priv
;
1830 struct hclge_desc desc
[2];
1834 for (i
= 0; i
< 2; i
++) {
1835 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1837 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1839 /* The first descriptor set the NEXT bit to 1 */
1841 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1843 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1845 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1846 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1848 priv
= &buf_alloc
->priv_buf
[idx
];
1849 req
->tc_wl
[j
].high
=
1850 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1851 req
->tc_wl
[j
].high
|=
1852 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1853 HCLGE_RX_PRIV_EN_B
);
1855 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1856 req
->tc_wl
[j
].low
|=
1857 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1858 HCLGE_RX_PRIV_EN_B
);
1862 /* Send 2 descriptor at one time */
1863 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1865 dev_err(&hdev
->pdev
->dev
,
1866 "rx private waterline config cmd failed %d\n",
1871 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1872 struct hclge_pkt_buf_alloc
*buf_alloc
)
1874 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1875 struct hclge_rx_com_thrd
*req
;
1876 struct hclge_desc desc
[2];
1877 struct hclge_tc_thrd
*tc
;
1881 for (i
= 0; i
< 2; i
++) {
1882 hclge_cmd_setup_basic_desc(&desc
[i
],
1883 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1884 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1886 /* The first descriptor set the NEXT bit to 1 */
1888 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1890 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1892 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1893 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1895 req
->com_thrd
[j
].high
=
1896 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1897 req
->com_thrd
[j
].high
|=
1898 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1899 HCLGE_RX_PRIV_EN_B
);
1900 req
->com_thrd
[j
].low
=
1901 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1902 req
->com_thrd
[j
].low
|=
1903 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1904 HCLGE_RX_PRIV_EN_B
);
1908 /* Send 2 descriptors at one time */
1909 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1911 dev_err(&hdev
->pdev
->dev
,
1912 "common threshold config cmd failed %d\n", ret
);
1916 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1917 struct hclge_pkt_buf_alloc
*buf_alloc
)
1919 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1920 struct hclge_rx_com_wl
*req
;
1921 struct hclge_desc desc
;
1924 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1926 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1927 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1929 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1930 HCLGE_RX_PRIV_EN_B
);
1932 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1934 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1935 HCLGE_RX_PRIV_EN_B
);
1937 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1939 dev_err(&hdev
->pdev
->dev
,
1940 "common waterline config cmd failed %d\n", ret
);
1944 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1946 struct hclge_pkt_buf_alloc
*pkt_buf
;
1949 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1953 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1955 dev_err(&hdev
->pdev
->dev
,
1956 "could not calc tx buffer size for all TCs %d\n", ret
);
1960 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1962 dev_err(&hdev
->pdev
->dev
,
1963 "could not alloc tx buffers %d\n", ret
);
1967 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1969 dev_err(&hdev
->pdev
->dev
,
1970 "could not calc rx priv buffer size for all TCs %d\n",
1975 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1977 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1982 if (hnae3_dev_dcb_supported(hdev
)) {
1983 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1985 dev_err(&hdev
->pdev
->dev
,
1986 "could not configure rx private waterline %d\n",
1991 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
1993 dev_err(&hdev
->pdev
->dev
,
1994 "could not configure common threshold %d\n",
2000 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2002 dev_err(&hdev
->pdev
->dev
,
2003 "could not configure common waterline %d\n", ret
);
2010 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2012 struct hnae3_handle
*roce
= &vport
->roce
;
2013 struct hnae3_handle
*nic
= &vport
->nic
;
2015 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2017 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2018 vport
->back
->num_msi_left
== 0)
2021 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2023 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2024 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2026 roce
->pdev
= nic
->pdev
;
2027 roce
->ae_algo
= nic
->ae_algo
;
2028 roce
->numa_node_mask
= nic
->numa_node_mask
;
2033 static int hclge_init_msi(struct hclge_dev
*hdev
)
2035 struct pci_dev
*pdev
= hdev
->pdev
;
2039 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2040 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2043 "failed(%d) to allocate MSI/MSI-X vectors\n",
2047 if (vectors
< hdev
->num_msi
)
2048 dev_warn(&hdev
->pdev
->dev
,
2049 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2050 hdev
->num_msi
, vectors
);
2052 hdev
->num_msi
= vectors
;
2053 hdev
->num_msi_left
= vectors
;
2054 hdev
->base_msi_vector
= pdev
->irq
;
2055 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2056 HCLGE_ROCE_VECTOR_OFFSET
;
2058 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2059 sizeof(u16
), GFP_KERNEL
);
2060 if (!hdev
->vector_status
) {
2061 pci_free_irq_vectors(pdev
);
2065 for (i
= 0; i
< hdev
->num_msi
; i
++)
2066 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2068 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2069 sizeof(int), GFP_KERNEL
);
2070 if (!hdev
->vector_irq
) {
2071 pci_free_irq_vectors(pdev
);
2078 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2080 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2082 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2083 mac
->duplex
= (u8
)duplex
;
2085 mac
->duplex
= HCLGE_MAC_FULL
;
2090 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2092 struct hclge_config_mac_speed_dup_cmd
*req
;
2093 struct hclge_desc desc
;
2096 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2098 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2100 hnae3_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2103 case HCLGE_MAC_SPEED_10M
:
2104 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2105 HCLGE_CFG_SPEED_S
, 6);
2107 case HCLGE_MAC_SPEED_100M
:
2108 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2109 HCLGE_CFG_SPEED_S
, 7);
2111 case HCLGE_MAC_SPEED_1G
:
2112 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2113 HCLGE_CFG_SPEED_S
, 0);
2115 case HCLGE_MAC_SPEED_10G
:
2116 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2117 HCLGE_CFG_SPEED_S
, 1);
2119 case HCLGE_MAC_SPEED_25G
:
2120 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2121 HCLGE_CFG_SPEED_S
, 2);
2123 case HCLGE_MAC_SPEED_40G
:
2124 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2125 HCLGE_CFG_SPEED_S
, 3);
2127 case HCLGE_MAC_SPEED_50G
:
2128 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2129 HCLGE_CFG_SPEED_S
, 4);
2131 case HCLGE_MAC_SPEED_100G
:
2132 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2133 HCLGE_CFG_SPEED_S
, 5);
2136 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2140 hnae3_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2143 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2145 dev_err(&hdev
->pdev
->dev
,
2146 "mac speed/duplex config cmd failed %d.\n", ret
);
2150 hclge_check_speed_dup(hdev
, duplex
, speed
);
2155 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2158 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2159 struct hclge_dev
*hdev
= vport
->back
;
2161 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2164 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2167 struct hclge_query_an_speed_dup_cmd
*req
;
2168 struct hclge_desc desc
;
2172 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2174 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2175 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2177 dev_err(&hdev
->pdev
->dev
,
2178 "mac speed/autoneg/duplex query cmd failed %d\n",
2183 *duplex
= hnae3_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2184 speed_tmp
= hnae3_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2185 HCLGE_QUERY_SPEED_S
);
2187 ret
= hclge_parse_speed(speed_tmp
, speed
);
2189 dev_err(&hdev
->pdev
->dev
,
2190 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2195 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2197 struct hclge_config_auto_neg_cmd
*req
;
2198 struct hclge_desc desc
;
2202 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2204 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2205 hnae3_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2206 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2208 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2210 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2216 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2218 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2219 struct hclge_dev
*hdev
= vport
->back
;
2221 return hclge_set_autoneg_en(hdev
, enable
);
2224 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2226 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2227 struct hclge_dev
*hdev
= vport
->back
;
2228 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2231 return phydev
->autoneg
;
2233 return hdev
->hw
.mac
.autoneg
;
2236 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2240 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2241 struct hclge_desc desc
;
2244 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2245 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2247 hnae3_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2249 ether_addr_copy(req
->mac_mask
, mac_mask
);
2251 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2253 dev_err(&hdev
->pdev
->dev
,
2254 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2260 static int hclge_mac_init(struct hclge_dev
*hdev
)
2262 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2263 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2264 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2265 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2266 struct hclge_vport
*vport
;
2271 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2273 dev_err(&hdev
->pdev
->dev
,
2274 "Config mac speed dup fail ret=%d\n", ret
);
2280 /* Initialize the MTA table work mode */
2281 hdev
->enable_mta
= true;
2282 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2284 ret
= hclge_set_mta_filter_mode(hdev
,
2285 hdev
->mta_mac_sel_type
,
2288 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2293 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
2294 vport
= &hdev
->vport
[i
];
2295 vport
->accept_mta_mc
= false;
2297 memset(vport
->mta_shadow
, 0, sizeof(vport
->mta_shadow
));
2298 ret
= hclge_cfg_func_mta_filter(hdev
, vport
->vport_id
, false);
2300 dev_err(&hdev
->pdev
->dev
,
2301 "set mta filter mode fail ret=%d\n", ret
);
2306 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2308 dev_err(&hdev
->pdev
->dev
,
2309 "set default mac_vlan_mask fail ret=%d\n", ret
);
2318 ret
= hclge_set_mtu(handle
, mtu
);
2320 dev_err(&hdev
->pdev
->dev
,
2321 "set mtu failed ret=%d\n", ret
);
2326 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2328 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2329 schedule_work(&hdev
->mbx_service_task
);
2332 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2334 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2335 schedule_work(&hdev
->rst_service_task
);
2338 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2340 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2341 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2342 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2343 (void)schedule_work(&hdev
->service_task
);
2346 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2348 struct hclge_link_status_cmd
*req
;
2349 struct hclge_desc desc
;
2353 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2354 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2356 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2361 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2362 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2364 return !!link_status
;
2367 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2372 mac_state
= hclge_get_mac_link_status(hdev
);
2374 if (hdev
->hw
.mac
.phydev
) {
2375 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2376 link_stat
= mac_state
&
2377 hdev
->hw
.mac
.phydev
->link
;
2382 link_stat
= mac_state
;
2388 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2390 struct hnae3_client
*client
= hdev
->nic_client
;
2391 struct hnae3_handle
*handle
;
2397 state
= hclge_get_mac_phy_link(hdev
);
2398 if (state
!= hdev
->hw
.mac
.link
) {
2399 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2400 handle
= &hdev
->vport
[i
].nic
;
2401 client
->ops
->link_status_change(handle
, state
);
2403 hdev
->hw
.mac
.link
= state
;
2407 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2409 struct hclge_mac mac
= hdev
->hw
.mac
;
2414 /* get the speed and duplex as autoneg'result from mac cmd when phy
2417 if (mac
.phydev
|| !mac
.autoneg
)
2420 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2422 dev_err(&hdev
->pdev
->dev
,
2423 "mac autoneg/speed/duplex query failed %d\n", ret
);
2427 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2428 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2430 dev_err(&hdev
->pdev
->dev
,
2431 "mac speed/duplex config failed %d\n", ret
);
2439 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2441 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2442 struct hclge_dev
*hdev
= vport
->back
;
2444 return hclge_update_speed_duplex(hdev
);
2447 static int hclge_get_status(struct hnae3_handle
*handle
)
2449 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2450 struct hclge_dev
*hdev
= vport
->back
;
2452 hclge_update_link_status(hdev
);
2454 return hdev
->hw
.mac
.link
;
2457 static void hclge_service_timer(struct timer_list
*t
)
2459 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2461 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2462 hdev
->hw_stats
.stats_timer
++;
2463 hclge_task_schedule(hdev
);
2466 static void hclge_service_complete(struct hclge_dev
*hdev
)
2468 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2470 /* Flush memory before next watchdog */
2471 smp_mb__before_atomic();
2472 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2475 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2480 /* fetch the events from their corresponding regs */
2481 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2482 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2484 /* Assumption: If by any chance reset and mailbox events are reported
2485 * together then we will only process reset event in this go and will
2486 * defer the processing of the mailbox events. Since, we would have not
2487 * cleared RX CMDQ event this time we would receive again another
2488 * interrupt from H/W just for the mailbox.
2491 /* check for vector0 reset event sources */
2492 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2493 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2494 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2495 return HCLGE_VECTOR0_EVENT_RST
;
2498 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2499 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2500 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2501 return HCLGE_VECTOR0_EVENT_RST
;
2504 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2505 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2506 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2507 return HCLGE_VECTOR0_EVENT_RST
;
2510 /* check for vector0 mailbox(=CMDQ RX) event source */
2511 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2512 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2513 *clearval
= cmdq_src_reg
;
2514 return HCLGE_VECTOR0_EVENT_MBX
;
2517 return HCLGE_VECTOR0_EVENT_OTHER
;
2520 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2523 switch (event_type
) {
2524 case HCLGE_VECTOR0_EVENT_RST
:
2525 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2527 case HCLGE_VECTOR0_EVENT_MBX
:
2528 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2533 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2535 writel(enable
? 1 : 0, vector
->addr
);
2538 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2540 struct hclge_dev
*hdev
= data
;
2544 hclge_enable_vector(&hdev
->misc_vector
, false);
2545 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2547 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2548 switch (event_cause
) {
2549 case HCLGE_VECTOR0_EVENT_RST
:
2550 hclge_reset_task_schedule(hdev
);
2552 case HCLGE_VECTOR0_EVENT_MBX
:
2553 /* If we are here then,
2554 * 1. Either we are not handling any mbx task and we are not
2557 * 2. We could be handling a mbx task but nothing more is
2559 * In both cases, we should schedule mbx task as there are more
2560 * mbx messages reported by this interrupt.
2562 hclge_mbx_task_schedule(hdev
);
2565 dev_warn(&hdev
->pdev
->dev
,
2566 "received unknown or unhandled event of vector0\n");
2570 /* clear the source of interrupt if it is not cause by reset */
2571 if (event_cause
!= HCLGE_VECTOR0_EVENT_RST
) {
2572 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2573 hclge_enable_vector(&hdev
->misc_vector
, true);
2579 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2581 if (hdev
->vector_status
[vector_id
] == HCLGE_INVALID_VPORT
) {
2582 dev_warn(&hdev
->pdev
->dev
,
2583 "vector(vector_id %d) has been freed.\n", vector_id
);
2587 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2588 hdev
->num_msi_left
+= 1;
2589 hdev
->num_msi_used
-= 1;
2592 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2594 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2596 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2598 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2599 hdev
->vector_status
[0] = 0;
2601 hdev
->num_msi_left
-= 1;
2602 hdev
->num_msi_used
+= 1;
2605 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2609 hclge_get_misc_vector(hdev
);
2611 /* this would be explicitly freed in the end */
2612 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2613 0, "hclge_misc", hdev
);
2615 hclge_free_vector(hdev
, 0);
2616 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2617 hdev
->misc_vector
.vector_irq
);
2623 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2625 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2626 hclge_free_vector(hdev
, 0);
2629 static int hclge_notify_client(struct hclge_dev
*hdev
,
2630 enum hnae3_reset_notify_type type
)
2632 struct hnae3_client
*client
= hdev
->nic_client
;
2635 if (!client
->ops
->reset_notify
)
2638 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2639 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2642 ret
= client
->ops
->reset_notify(handle
, type
);
2650 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2652 #define HCLGE_RESET_WATI_MS 100
2653 #define HCLGE_RESET_WAIT_CNT 5
2654 u32 val
, reg
, reg_bit
;
2657 switch (hdev
->reset_type
) {
2658 case HNAE3_GLOBAL_RESET
:
2659 reg
= HCLGE_GLOBAL_RESET_REG
;
2660 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2662 case HNAE3_CORE_RESET
:
2663 reg
= HCLGE_GLOBAL_RESET_REG
;
2664 reg_bit
= HCLGE_CORE_RESET_BIT
;
2666 case HNAE3_FUNC_RESET
:
2667 reg
= HCLGE_FUN_RST_ING
;
2668 reg_bit
= HCLGE_FUN_RST_ING_B
;
2671 dev_err(&hdev
->pdev
->dev
,
2672 "Wait for unsupported reset type: %d\n",
2677 val
= hclge_read_dev(&hdev
->hw
, reg
);
2678 while (hnae3_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
&&
2679 test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
2680 msleep(HCLGE_RESET_WATI_MS
);
2681 val
= hclge_read_dev(&hdev
->hw
, reg
);
2685 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2686 dev_warn(&hdev
->pdev
->dev
,
2687 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2694 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2696 struct hclge_desc desc
;
2697 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2700 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2701 hnae3_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2702 req
->fun_reset_vfid
= func_id
;
2704 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2706 dev_err(&hdev
->pdev
->dev
,
2707 "send function reset cmd fail, status =%d\n", ret
);
2712 static void hclge_do_reset(struct hclge_dev
*hdev
)
2714 struct pci_dev
*pdev
= hdev
->pdev
;
2717 switch (hdev
->reset_type
) {
2718 case HNAE3_GLOBAL_RESET
:
2719 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2720 hnae3_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2721 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2722 dev_info(&pdev
->dev
, "Global Reset requested\n");
2724 case HNAE3_CORE_RESET
:
2725 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2726 hnae3_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2727 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2728 dev_info(&pdev
->dev
, "Core Reset requested\n");
2730 case HNAE3_FUNC_RESET
:
2731 dev_info(&pdev
->dev
, "PF Reset requested\n");
2732 hclge_func_reset_cmd(hdev
, 0);
2733 /* schedule again to check later */
2734 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2735 hclge_reset_task_schedule(hdev
);
2738 dev_warn(&pdev
->dev
,
2739 "Unsupported reset type: %d\n", hdev
->reset_type
);
2744 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2745 unsigned long *addr
)
2747 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2749 /* return the highest priority reset level amongst all */
2750 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2751 rst_level
= HNAE3_GLOBAL_RESET
;
2752 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2753 rst_level
= HNAE3_CORE_RESET
;
2754 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2755 rst_level
= HNAE3_IMP_RESET
;
2756 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2757 rst_level
= HNAE3_FUNC_RESET
;
2759 /* now, clear all other resets */
2760 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2761 clear_bit(HNAE3_CORE_RESET
, addr
);
2762 clear_bit(HNAE3_IMP_RESET
, addr
);
2763 clear_bit(HNAE3_FUNC_RESET
, addr
);
2768 static void hclge_clear_reset_cause(struct hclge_dev
*hdev
)
2772 switch (hdev
->reset_type
) {
2773 case HNAE3_IMP_RESET
:
2774 clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2776 case HNAE3_GLOBAL_RESET
:
2777 clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2779 case HNAE3_CORE_RESET
:
2780 clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2783 dev_warn(&hdev
->pdev
->dev
, "Unsupported reset event to clear:%d",
2791 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, clearval
);
2792 hclge_enable_vector(&hdev
->misc_vector
, true);
2795 static void hclge_reset(struct hclge_dev
*hdev
)
2797 /* perform reset of the stack & ae device for a client */
2799 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2801 if (!hclge_reset_wait(hdev
)) {
2803 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2804 hclge_reset_ae_dev(hdev
->ae_dev
);
2805 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2808 hclge_clear_reset_cause(hdev
);
2810 /* schedule again to check pending resets later */
2811 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2812 hclge_reset_task_schedule(hdev
);
2815 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2818 static void hclge_reset_event(struct hnae3_handle
*handle
)
2820 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2821 struct hclge_dev
*hdev
= vport
->back
;
2823 /* check if this is a new reset request and we are not here just because
2824 * last reset attempt did not succeed and watchdog hit us again. We will
2825 * know this if last reset request did not occur very recently (watchdog
2826 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2827 * In case of new request we reset the "reset level" to PF reset.
2829 if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2830 handle
->reset_level
= HNAE3_FUNC_RESET
;
2832 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2833 handle
->reset_level
);
2835 /* request reset & schedule reset task */
2836 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2837 hclge_reset_task_schedule(hdev
);
2839 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2840 handle
->reset_level
++;
2842 handle
->last_reset_time
= jiffies
;
2845 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2847 /* check if there is any ongoing reset in the hardware. This status can
2848 * be checked from reset_pending. If there is then, we need to wait for
2849 * hardware to complete reset.
2850 * a. If we are able to figure out in reasonable time that hardware
2851 * has fully resetted then, we can proceed with driver, client
2853 * b. else, we can come back later to check this status so re-sched
2856 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2857 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2860 /* check if we got any *new* reset requests to be honored */
2861 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2862 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2863 hclge_do_reset(hdev
);
2865 hdev
->reset_type
= HNAE3_NONE_RESET
;
2868 static void hclge_reset_service_task(struct work_struct
*work
)
2870 struct hclge_dev
*hdev
=
2871 container_of(work
, struct hclge_dev
, rst_service_task
);
2873 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2876 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2878 hclge_reset_subtask(hdev
);
2880 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2883 static void hclge_mailbox_service_task(struct work_struct
*work
)
2885 struct hclge_dev
*hdev
=
2886 container_of(work
, struct hclge_dev
, mbx_service_task
);
2888 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2891 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2893 hclge_mbx_handler(hdev
);
2895 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2898 static void hclge_service_task(struct work_struct
*work
)
2900 struct hclge_dev
*hdev
=
2901 container_of(work
, struct hclge_dev
, service_task
);
2903 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2904 hclge_update_stats_for_all(hdev
);
2905 hdev
->hw_stats
.stats_timer
= 0;
2908 hclge_update_speed_duplex(hdev
);
2909 hclge_update_link_status(hdev
);
2910 hclge_service_complete(hdev
);
2913 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2915 /* VF handle has no client */
2916 if (!handle
->client
)
2917 return container_of(handle
, struct hclge_vport
, nic
);
2918 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2919 return container_of(handle
, struct hclge_vport
, roce
);
2921 return container_of(handle
, struct hclge_vport
, nic
);
2924 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2925 struct hnae3_vector_info
*vector_info
)
2927 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2928 struct hnae3_vector_info
*vector
= vector_info
;
2929 struct hclge_dev
*hdev
= vport
->back
;
2933 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2935 for (j
= 0; j
< vector_num
; j
++) {
2936 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2937 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2938 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2939 vector
->io_addr
= hdev
->hw
.io_base
+
2940 HCLGE_VECTOR_REG_BASE
+
2941 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2943 HCLGE_VECTOR_VF_OFFSET
;
2944 hdev
->vector_status
[i
] = vport
->vport_id
;
2945 hdev
->vector_irq
[i
] = vector
->vector
;
2954 hdev
->num_msi_left
-= alloc
;
2955 hdev
->num_msi_used
+= alloc
;
2960 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2964 for (i
= 0; i
< hdev
->num_msi
; i
++)
2965 if (vector
== hdev
->vector_irq
[i
])
2971 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
2973 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2974 struct hclge_dev
*hdev
= vport
->back
;
2977 vector_id
= hclge_get_vector_index(hdev
, vector
);
2978 if (vector_id
< 0) {
2979 dev_err(&hdev
->pdev
->dev
,
2980 "Get vector index fail. vector_id =%d\n", vector_id
);
2984 hclge_free_vector(hdev
, vector_id
);
2989 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
2991 return HCLGE_RSS_KEY_SIZE
;
2994 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
2996 return HCLGE_RSS_IND_TBL_SIZE
;
2999 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3000 const u8 hfunc
, const u8
*key
)
3002 struct hclge_rss_config_cmd
*req
;
3003 struct hclge_desc desc
;
3008 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3010 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3011 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3014 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3015 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3017 if (key_offset
== 2)
3019 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3021 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3023 memcpy(req
->hash_key
,
3024 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3026 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3028 dev_err(&hdev
->pdev
->dev
,
3029 "Configure RSS config fail, status = %d\n",
3037 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3039 struct hclge_rss_indirection_table_cmd
*req
;
3040 struct hclge_desc desc
;
3044 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3046 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3047 hclge_cmd_setup_basic_desc
3048 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3050 req
->start_table_index
=
3051 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3052 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3054 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3055 req
->rss_result
[j
] =
3056 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3058 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3060 dev_err(&hdev
->pdev
->dev
,
3061 "Configure rss indir table fail,status = %d\n",
3069 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3070 u16
*tc_size
, u16
*tc_offset
)
3072 struct hclge_rss_tc_mode_cmd
*req
;
3073 struct hclge_desc desc
;
3077 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3078 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3080 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3083 hnae3_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3084 hnae3_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3085 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3086 hnae3_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3087 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3089 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3092 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3094 dev_err(&hdev
->pdev
->dev
,
3095 "Configure rss tc mode fail, status = %d\n", ret
);
3100 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3102 struct hclge_rss_input_tuple_cmd
*req
;
3103 struct hclge_desc desc
;
3106 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3108 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3110 /* Get the tuple cfg from pf */
3111 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3112 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3113 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3114 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3115 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3116 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3117 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3118 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3119 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3121 dev_err(&hdev
->pdev
->dev
,
3122 "Configure rss input fail, status = %d\n", ret
);
3126 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3129 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3132 /* Get hash algorithm */
3134 *hfunc
= vport
->rss_algo
;
3136 /* Get the RSS Key required by the user */
3138 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3140 /* Get indirect table */
3142 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3143 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3148 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3149 const u8
*key
, const u8 hfunc
)
3151 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3152 struct hclge_dev
*hdev
= vport
->back
;
3156 /* Set the RSS Hash Key if specififed by the user */
3159 if (hfunc
== ETH_RSS_HASH_TOP
||
3160 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3161 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3164 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3168 /* Update the shadow RSS key with user specified qids */
3169 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3170 vport
->rss_algo
= hash_algo
;
3173 /* Update the shadow RSS table with user specified qids */
3174 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3175 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3177 /* Update the hardware */
3178 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3181 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3183 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3185 if (nfc
->data
& RXH_L4_B_2_3
)
3186 hash_sets
|= HCLGE_D_PORT_BIT
;
3188 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3190 if (nfc
->data
& RXH_IP_SRC
)
3191 hash_sets
|= HCLGE_S_IP_BIT
;
3193 hash_sets
&= ~HCLGE_S_IP_BIT
;
3195 if (nfc
->data
& RXH_IP_DST
)
3196 hash_sets
|= HCLGE_D_IP_BIT
;
3198 hash_sets
&= ~HCLGE_D_IP_BIT
;
3200 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3201 hash_sets
|= HCLGE_V_TAG_BIT
;
3206 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3207 struct ethtool_rxnfc
*nfc
)
3209 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3210 struct hclge_dev
*hdev
= vport
->back
;
3211 struct hclge_rss_input_tuple_cmd
*req
;
3212 struct hclge_desc desc
;
3216 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3217 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3220 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3221 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3223 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3224 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3225 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3226 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3227 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3228 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3229 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3230 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3232 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3233 switch (nfc
->flow_type
) {
3235 req
->ipv4_tcp_en
= tuple_sets
;
3238 req
->ipv6_tcp_en
= tuple_sets
;
3241 req
->ipv4_udp_en
= tuple_sets
;
3244 req
->ipv6_udp_en
= tuple_sets
;
3247 req
->ipv4_sctp_en
= tuple_sets
;
3250 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3251 (nfc
->data
& RXH_L4_B_2_3
))
3254 req
->ipv6_sctp_en
= tuple_sets
;
3257 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3260 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3266 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3268 dev_err(&hdev
->pdev
->dev
,
3269 "Set rss tuple fail, status = %d\n", ret
);
3273 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3274 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3275 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3276 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3277 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3278 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3279 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3280 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3284 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3285 struct ethtool_rxnfc
*nfc
)
3287 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3292 switch (nfc
->flow_type
) {
3294 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3297 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3300 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3303 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3306 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3309 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3313 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3322 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3323 nfc
->data
|= RXH_L4_B_2_3
;
3324 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3325 nfc
->data
|= RXH_L4_B_0_1
;
3326 if (tuple_sets
& HCLGE_D_IP_BIT
)
3327 nfc
->data
|= RXH_IP_DST
;
3328 if (tuple_sets
& HCLGE_S_IP_BIT
)
3329 nfc
->data
|= RXH_IP_SRC
;
3334 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3336 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3337 struct hclge_dev
*hdev
= vport
->back
;
3339 return hdev
->rss_size_max
;
3342 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3344 struct hclge_vport
*vport
= hdev
->vport
;
3345 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3346 u16 rss_size
= vport
[0].alloc_rss_size
;
3347 u8
*key
= vport
[0].rss_hash_key
;
3348 u8 hfunc
= vport
[0].rss_algo
;
3349 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3350 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3351 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3355 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3359 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3363 ret
= hclge_set_rss_input_tuple(hdev
);
3367 /* Each TC have the same queue size, and tc_size set to hardware is
3368 * the log2 of roundup power of two of rss_size, the acutal queue
3369 * size is limited by indirection table.
3371 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3372 dev_err(&hdev
->pdev
->dev
,
3373 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3378 roundup_size
= roundup_pow_of_two(rss_size
);
3379 roundup_size
= ilog2(roundup_size
);
3381 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3384 if (!(hdev
->hw_tc_map
& BIT(i
)))
3388 tc_size
[i
] = roundup_size
;
3389 tc_offset
[i
] = rss_size
* i
;
3392 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3395 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3397 struct hclge_vport
*vport
= hdev
->vport
;
3400 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3401 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3402 vport
[j
].rss_indirection_tbl
[i
] =
3403 i
% vport
[j
].alloc_rss_size
;
3407 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3409 struct hclge_vport
*vport
= hdev
->vport
;
3412 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3413 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3414 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3415 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3416 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3417 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3418 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3419 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3420 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3421 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3422 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3423 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3424 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3425 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3426 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3427 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3428 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3430 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3432 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3435 hclge_rss_indir_init_cfg(hdev
);
3438 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3439 int vector_id
, bool en
,
3440 struct hnae3_ring_chain_node
*ring_chain
)
3442 struct hclge_dev
*hdev
= vport
->back
;
3443 struct hnae3_ring_chain_node
*node
;
3444 struct hclge_desc desc
;
3445 struct hclge_ctrl_vector_chain_cmd
*req
3446 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3447 enum hclge_cmd_status status
;
3448 enum hclge_opcode_type op
;
3449 u16 tqp_type_and_id
;
3452 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3453 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3454 req
->int_vector_id
= vector_id
;
3457 for (node
= ring_chain
; node
; node
= node
->next
) {
3458 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3459 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3461 hnae3_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3462 hnae3_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3463 HCLGE_TQP_ID_S
, node
->tqp_index
);
3464 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3466 hnae3_get_field(node
->int_gl_idx
,
3467 HNAE3_RING_GL_IDX_M
,
3468 HNAE3_RING_GL_IDX_S
));
3469 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3470 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3471 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3472 req
->vfid
= vport
->vport_id
;
3474 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3476 dev_err(&hdev
->pdev
->dev
,
3477 "Map TQP fail, status is %d.\n",
3483 hclge_cmd_setup_basic_desc(&desc
,
3486 req
->int_vector_id
= vector_id
;
3491 req
->int_cause_num
= i
;
3492 req
->vfid
= vport
->vport_id
;
3493 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3495 dev_err(&hdev
->pdev
->dev
,
3496 "Map TQP fail, status is %d.\n", status
);
3504 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3506 struct hnae3_ring_chain_node
*ring_chain
)
3508 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3509 struct hclge_dev
*hdev
= vport
->back
;
3512 vector_id
= hclge_get_vector_index(hdev
, vector
);
3513 if (vector_id
< 0) {
3514 dev_err(&hdev
->pdev
->dev
,
3515 "Get vector index fail. vector_id =%d\n", vector_id
);
3519 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3522 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3524 struct hnae3_ring_chain_node
*ring_chain
)
3526 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3527 struct hclge_dev
*hdev
= vport
->back
;
3530 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3533 vector_id
= hclge_get_vector_index(hdev
, vector
);
3534 if (vector_id
< 0) {
3535 dev_err(&handle
->pdev
->dev
,
3536 "Get vector index fail. ret =%d\n", vector_id
);
3540 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3542 dev_err(&handle
->pdev
->dev
,
3543 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3550 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3551 struct hclge_promisc_param
*param
)
3553 struct hclge_promisc_cfg_cmd
*req
;
3554 struct hclge_desc desc
;
3557 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3559 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3560 req
->vf_id
= param
->vf_id
;
3562 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3563 * pdev revision(0x20), new revision support them. The
3564 * value of this two fields will not return error when driver
3565 * send command to fireware in revision(0x20).
3567 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
) |
3568 HCLGE_PROMISC_TX_EN_B
| HCLGE_PROMISC_RX_EN_B
;
3570 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3572 dev_err(&hdev
->pdev
->dev
,
3573 "Set promisc mode fail, status is %d.\n", ret
);
3578 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3579 bool en_mc
, bool en_bc
, int vport_id
)
3584 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3586 param
->enable
= HCLGE_PROMISC_EN_UC
;
3588 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3590 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3591 param
->vf_id
= vport_id
;
3594 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, bool en_uc_pmc
,
3597 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3598 struct hclge_dev
*hdev
= vport
->back
;
3599 struct hclge_promisc_param param
;
3601 hclge_promisc_param_init(¶m
, en_uc_pmc
, en_mc_pmc
, true,
3603 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3606 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3608 struct hclge_desc desc
;
3609 struct hclge_config_mac_mode_cmd
*req
=
3610 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3614 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3615 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3616 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3617 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3618 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3619 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3620 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3621 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3622 hnae3_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3623 hnae3_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3624 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3625 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3626 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3627 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3628 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3629 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3631 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3633 dev_err(&hdev
->pdev
->dev
,
3634 "mac enable fail, ret =%d.\n", ret
);
3637 static int hclge_set_mac_loopback(struct hclge_dev
*hdev
, bool en
)
3639 struct hclge_config_mac_mode_cmd
*req
;
3640 struct hclge_desc desc
;
3644 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3645 /* 1 Read out the MAC mode config at first */
3646 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, true);
3647 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3649 dev_err(&hdev
->pdev
->dev
,
3650 "mac loopback get fail, ret =%d.\n", ret
);
3654 /* 2 Then setup the loopback flag */
3655 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3656 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, en
? 1 : 0);
3658 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3660 /* 3 Config mac work mode with loopback flag
3661 * and its original configure parameters
3663 hclge_cmd_reuse_desc(&desc
, false);
3664 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3666 dev_err(&hdev
->pdev
->dev
,
3667 "mac loopback set fail, ret =%d.\n", ret
);
3671 static int hclge_set_serdes_loopback(struct hclge_dev
*hdev
, bool en
)
3673 #define HCLGE_SERDES_RETRY_MS 10
3674 #define HCLGE_SERDES_RETRY_NUM 100
3675 struct hclge_serdes_lb_cmd
*req
;
3676 struct hclge_desc desc
;
3679 req
= (struct hclge_serdes_lb_cmd
*)&desc
.data
[0];
3680 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SERDES_LOOPBACK
, false);
3683 req
->enable
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3684 req
->mask
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3686 req
->mask
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3689 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3691 dev_err(&hdev
->pdev
->dev
,
3692 "serdes loopback set fail, ret = %d\n", ret
);
3697 msleep(HCLGE_SERDES_RETRY_MS
);
3698 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SERDES_LOOPBACK
,
3700 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3702 dev_err(&hdev
->pdev
->dev
,
3703 "serdes loopback get, ret = %d\n", ret
);
3706 } while (++i
< HCLGE_SERDES_RETRY_NUM
&&
3707 !(req
->result
& HCLGE_CMD_SERDES_DONE_B
));
3709 if (!(req
->result
& HCLGE_CMD_SERDES_DONE_B
)) {
3710 dev_err(&hdev
->pdev
->dev
, "serdes loopback set timeout\n");
3712 } else if (!(req
->result
& HCLGE_CMD_SERDES_SUCCESS_B
)) {
3713 dev_err(&hdev
->pdev
->dev
, "serdes loopback set failed in fw\n");
3720 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3721 enum hnae3_loop loop_mode
, bool en
)
3723 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3724 struct hclge_dev
*hdev
= vport
->back
;
3727 switch (loop_mode
) {
3728 case HNAE3_MAC_INTER_LOOP_MAC
:
3729 ret
= hclge_set_mac_loopback(hdev
, en
);
3731 case HNAE3_MAC_INTER_LOOP_SERDES
:
3732 ret
= hclge_set_serdes_loopback(hdev
, en
);
3736 dev_err(&hdev
->pdev
->dev
,
3737 "loop_mode %d is not supported\n", loop_mode
);
3744 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3745 int stream_id
, bool enable
)
3747 struct hclge_desc desc
;
3748 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3749 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3752 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3753 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3754 req
->stream_id
= cpu_to_le16(stream_id
);
3755 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3757 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3759 dev_err(&hdev
->pdev
->dev
,
3760 "Tqp enable fail, status =%d.\n", ret
);
3764 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3766 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3767 struct hnae3_queue
*queue
;
3768 struct hclge_tqp
*tqp
;
3771 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3772 queue
= handle
->kinfo
.tqp
[i
];
3773 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3774 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3778 static int hclge_ae_start(struct hnae3_handle
*handle
)
3780 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3781 struct hclge_dev
*hdev
= vport
->back
;
3784 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3785 hclge_tqp_enable(hdev
, i
, 0, true);
3788 hclge_cfg_mac_mode(hdev
, true);
3789 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3790 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3791 hdev
->hw
.mac
.link
= 0;
3793 /* reset tqp stats */
3794 hclge_reset_tqp_stats(handle
);
3796 ret
= hclge_mac_start_phy(hdev
);
3803 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3805 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3806 struct hclge_dev
*hdev
= vport
->back
;
3809 del_timer_sync(&hdev
->service_timer
);
3810 cancel_work_sync(&hdev
->service_task
);
3811 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
3813 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
3814 hclge_mac_stop_phy(hdev
);
3818 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3819 hclge_tqp_enable(hdev
, i
, 0, false);
3822 hclge_cfg_mac_mode(hdev
, false);
3824 hclge_mac_stop_phy(hdev
);
3826 /* reset tqp stats */
3827 hclge_reset_tqp_stats(handle
);
3828 del_timer_sync(&hdev
->service_timer
);
3829 cancel_work_sync(&hdev
->service_task
);
3830 hclge_update_link_status(hdev
);
3833 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3834 u16 cmdq_resp
, u8 resp_code
,
3835 enum hclge_mac_vlan_tbl_opcode op
)
3837 struct hclge_dev
*hdev
= vport
->back
;
3838 int return_status
= -EIO
;
3841 dev_err(&hdev
->pdev
->dev
,
3842 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3847 if (op
== HCLGE_MAC_VLAN_ADD
) {
3848 if ((!resp_code
) || (resp_code
== 1)) {
3850 } else if (resp_code
== 2) {
3851 return_status
= -ENOSPC
;
3852 dev_err(&hdev
->pdev
->dev
,
3853 "add mac addr failed for uc_overflow.\n");
3854 } else if (resp_code
== 3) {
3855 return_status
= -ENOSPC
;
3856 dev_err(&hdev
->pdev
->dev
,
3857 "add mac addr failed for mc_overflow.\n");
3859 dev_err(&hdev
->pdev
->dev
,
3860 "add mac addr failed for undefined, code=%d.\n",
3863 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3866 } else if (resp_code
== 1) {
3867 return_status
= -ENOENT
;
3868 dev_dbg(&hdev
->pdev
->dev
,
3869 "remove mac addr failed for miss.\n");
3871 dev_err(&hdev
->pdev
->dev
,
3872 "remove mac addr failed for undefined, code=%d.\n",
3875 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3878 } else if (resp_code
== 1) {
3879 return_status
= -ENOENT
;
3880 dev_dbg(&hdev
->pdev
->dev
,
3881 "lookup mac addr failed for miss.\n");
3883 dev_err(&hdev
->pdev
->dev
,
3884 "lookup mac addr failed for undefined, code=%d.\n",
3888 return_status
= -EINVAL
;
3889 dev_err(&hdev
->pdev
->dev
,
3890 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3894 return return_status
;
3897 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3902 if (vfid
> 255 || vfid
< 0)
3905 if (vfid
>= 0 && vfid
<= 191) {
3906 word_num
= vfid
/ 32;
3907 bit_num
= vfid
% 32;
3909 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3911 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3913 word_num
= (vfid
- 192) / 32;
3914 bit_num
= vfid
% 32;
3916 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3918 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3924 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3926 #define HCLGE_DESC_NUMBER 3
3927 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3930 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3931 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3932 if (desc
[i
].data
[j
])
3938 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3941 const unsigned char *mac_addr
= addr
;
3942 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3943 (mac_addr
[0]) | (mac_addr
[1] << 8);
3944 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3946 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3947 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3950 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3953 u16 high_val
= addr
[1] | (addr
[0] << 8);
3954 struct hclge_dev
*hdev
= vport
->back
;
3955 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3956 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3961 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3962 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3965 struct hclge_mta_filter_mode_cmd
*req
;
3966 struct hclge_desc desc
;
3969 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3970 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3972 hnae3_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3974 hnae3_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3975 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3977 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3979 dev_err(&hdev
->pdev
->dev
,
3980 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3986 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3990 struct hclge_cfg_func_mta_filter_cmd
*req
;
3991 struct hclge_desc desc
;
3994 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3995 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3997 hnae3_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3999 req
->function_id
= func_id
;
4001 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4003 dev_err(&hdev
->pdev
->dev
,
4004 "Config func_id enable failed for cmd_send, ret =%d.\n",
4010 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
4014 struct hclge_dev
*hdev
= vport
->back
;
4015 struct hclge_cfg_func_mta_item_cmd
*req
;
4016 struct hclge_desc desc
;
4020 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
4021 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
4022 hnae3_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
4024 hnae3_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
4025 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
4026 req
->item_idx
= cpu_to_le16(item_idx
);
4028 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4030 dev_err(&hdev
->pdev
->dev
,
4031 "Config mta table item failed for cmd_send, ret =%d.\n",
4037 set_bit(idx
, vport
->mta_shadow
);
4039 clear_bit(idx
, vport
->mta_shadow
);
4044 static int hclge_update_mta_status(struct hnae3_handle
*handle
)
4046 unsigned long mta_status
[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE
)];
4047 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4048 struct net_device
*netdev
= handle
->kinfo
.netdev
;
4049 struct netdev_hw_addr
*ha
;
4052 memset(mta_status
, 0, sizeof(mta_status
));
4054 /* update mta_status from mc addr list */
4055 netdev_for_each_mc_addr(ha
, netdev
) {
4056 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, ha
->addr
);
4057 set_bit(tbl_idx
, mta_status
);
4060 return hclge_update_mta_status_common(vport
, mta_status
,
4061 0, HCLGE_MTA_TBL_SIZE
, true);
4064 int hclge_update_mta_status_common(struct hclge_vport
*vport
,
4065 unsigned long *status
,
4070 struct hclge_dev
*hdev
= vport
->back
;
4071 u16 update_max
= idx
+ count
;
4077 /* setup mta check range */
4078 if (update_filter
) {
4080 check_max
= HCLGE_MTA_TBL_SIZE
;
4083 check_max
= update_max
;
4087 /* check and update all mta item */
4088 for (; i
< check_max
; i
++) {
4089 /* ignore unused item */
4090 if (!test_bit(i
, vport
->mta_shadow
))
4093 /* if i in update range then update it */
4094 if (i
>= idx
&& i
< update_max
)
4095 if (!test_bit(i
- idx
, status
))
4096 hclge_set_mta_table_item(vport
, i
, false);
4098 if (!used
&& test_bit(i
, vport
->mta_shadow
))
4102 /* no longer use mta, disable it */
4103 if (vport
->accept_mta_mc
&& update_filter
&& !used
) {
4104 ret
= hclge_cfg_func_mta_filter(hdev
,
4108 dev_err(&hdev
->pdev
->dev
,
4109 "disable func mta filter fail ret=%d\n",
4112 vport
->accept_mta_mc
= false;
4118 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4119 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4121 struct hclge_dev
*hdev
= vport
->back
;
4122 struct hclge_desc desc
;
4127 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4129 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4131 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4133 dev_err(&hdev
->pdev
->dev
,
4134 "del mac addr failed for cmd_send, ret =%d.\n",
4138 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4139 retval
= le16_to_cpu(desc
.retval
);
4141 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4142 HCLGE_MAC_VLAN_REMOVE
);
4145 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4146 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4147 struct hclge_desc
*desc
,
4150 struct hclge_dev
*hdev
= vport
->back
;
4155 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4157 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4158 memcpy(desc
[0].data
,
4160 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4161 hclge_cmd_setup_basic_desc(&desc
[1],
4162 HCLGE_OPC_MAC_VLAN_ADD
,
4164 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4165 hclge_cmd_setup_basic_desc(&desc
[2],
4166 HCLGE_OPC_MAC_VLAN_ADD
,
4168 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4170 memcpy(desc
[0].data
,
4172 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4173 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4176 dev_err(&hdev
->pdev
->dev
,
4177 "lookup mac addr failed for cmd_send, ret =%d.\n",
4181 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4182 retval
= le16_to_cpu(desc
[0].retval
);
4184 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4185 HCLGE_MAC_VLAN_LKUP
);
4188 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4189 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4190 struct hclge_desc
*mc_desc
)
4192 struct hclge_dev
*hdev
= vport
->back
;
4199 struct hclge_desc desc
;
4201 hclge_cmd_setup_basic_desc(&desc
,
4202 HCLGE_OPC_MAC_VLAN_ADD
,
4204 memcpy(desc
.data
, req
,
4205 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4206 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4207 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4208 retval
= le16_to_cpu(desc
.retval
);
4210 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4212 HCLGE_MAC_VLAN_ADD
);
4214 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4215 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4216 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4217 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4218 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4219 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4220 memcpy(mc_desc
[0].data
, req
,
4221 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4222 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4223 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4224 retval
= le16_to_cpu(mc_desc
[0].retval
);
4226 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4228 HCLGE_MAC_VLAN_ADD
);
4232 dev_err(&hdev
->pdev
->dev
,
4233 "add mac addr failed for cmd_send, ret =%d.\n",
4241 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4242 const unsigned char *addr
)
4244 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4246 return hclge_add_uc_addr_common(vport
, addr
);
4249 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4250 const unsigned char *addr
)
4252 struct hclge_dev
*hdev
= vport
->back
;
4253 struct hclge_mac_vlan_tbl_entry_cmd req
;
4254 struct hclge_desc desc
;
4255 u16 egress_port
= 0;
4258 /* mac addr check */
4259 if (is_zero_ether_addr(addr
) ||
4260 is_broadcast_ether_addr(addr
) ||
4261 is_multicast_ether_addr(addr
)) {
4262 dev_err(&hdev
->pdev
->dev
,
4263 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4265 is_zero_ether_addr(addr
),
4266 is_broadcast_ether_addr(addr
),
4267 is_multicast_ether_addr(addr
));
4271 memset(&req
, 0, sizeof(req
));
4272 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4274 hnae3_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4275 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4277 req
.egress_port
= cpu_to_le16(egress_port
);
4279 hclge_prepare_mac_addr(&req
, addr
);
4281 /* Lookup the mac address in the mac_vlan table, and add
4282 * it if the entry is inexistent. Repeated unicast entry
4283 * is not allowed in the mac vlan table.
4285 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4287 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4289 /* check if we just hit the duplicate */
4293 dev_err(&hdev
->pdev
->dev
,
4294 "PF failed to add unicast entry(%pM) in the MAC table\n",
4300 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4301 const unsigned char *addr
)
4303 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4305 return hclge_rm_uc_addr_common(vport
, addr
);
4308 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4309 const unsigned char *addr
)
4311 struct hclge_dev
*hdev
= vport
->back
;
4312 struct hclge_mac_vlan_tbl_entry_cmd req
;
4315 /* mac addr check */
4316 if (is_zero_ether_addr(addr
) ||
4317 is_broadcast_ether_addr(addr
) ||
4318 is_multicast_ether_addr(addr
)) {
4319 dev_dbg(&hdev
->pdev
->dev
,
4320 "Remove mac err! invalid mac:%pM.\n",
4325 memset(&req
, 0, sizeof(req
));
4326 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4327 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4328 hclge_prepare_mac_addr(&req
, addr
);
4329 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4334 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4335 const unsigned char *addr
)
4337 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4339 return hclge_add_mc_addr_common(vport
, addr
);
4342 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4343 const unsigned char *addr
)
4345 struct hclge_dev
*hdev
= vport
->back
;
4346 struct hclge_mac_vlan_tbl_entry_cmd req
;
4347 struct hclge_desc desc
[3];
4351 /* mac addr check */
4352 if (!is_multicast_ether_addr(addr
)) {
4353 dev_err(&hdev
->pdev
->dev
,
4354 "Add mc mac err! invalid mac:%pM.\n",
4358 memset(&req
, 0, sizeof(req
));
4359 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4360 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4361 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4362 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4363 hclge_prepare_mac_addr(&req
, addr
);
4364 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4366 /* This mac addr exist, update VFID for it */
4367 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4368 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4370 /* This mac addr do not exist, add new entry for it */
4371 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4372 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4373 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4374 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4375 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4378 /* If mc mac vlan table is full, use MTA table */
4379 if (status
== -ENOSPC
) {
4380 if (!vport
->accept_mta_mc
) {
4381 status
= hclge_cfg_func_mta_filter(hdev
,
4385 dev_err(&hdev
->pdev
->dev
,
4386 "set mta filter mode fail ret=%d\n",
4390 vport
->accept_mta_mc
= true;
4393 /* Set MTA table for this MAC address */
4394 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4395 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4401 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4402 const unsigned char *addr
)
4404 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4406 return hclge_rm_mc_addr_common(vport
, addr
);
4409 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4410 const unsigned char *addr
)
4412 struct hclge_dev
*hdev
= vport
->back
;
4413 struct hclge_mac_vlan_tbl_entry_cmd req
;
4414 enum hclge_cmd_status status
;
4415 struct hclge_desc desc
[3];
4417 /* mac addr check */
4418 if (!is_multicast_ether_addr(addr
)) {
4419 dev_dbg(&hdev
->pdev
->dev
,
4420 "Remove mc mac err! invalid mac:%pM.\n",
4425 memset(&req
, 0, sizeof(req
));
4426 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4427 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4428 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4429 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4430 hclge_prepare_mac_addr(&req
, addr
);
4431 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4433 /* This mac addr exist, remove this handle's VFID for it */
4434 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4436 if (hclge_is_all_function_id_zero(desc
))
4437 /* All the vfid is zero, so need to delete this entry */
4438 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4440 /* Not all the vfid is zero, update the vfid */
4441 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4444 /* Maybe this mac address is in mta table, but it cannot be
4445 * deleted here because an entry of mta represents an address
4446 * range rather than a specific address. the delete action to
4447 * all entries will take effect in update_mta_status called by
4448 * hns3_nic_set_rx_mode.
4456 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4457 u16 cmdq_resp
, u8 resp_code
)
4459 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4460 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4461 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4462 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4467 dev_err(&hdev
->pdev
->dev
,
4468 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4473 switch (resp_code
) {
4474 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4475 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4478 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4479 dev_err(&hdev
->pdev
->dev
,
4480 "add mac ethertype failed for manager table overflow.\n");
4481 return_status
= -EIO
;
4483 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4484 dev_err(&hdev
->pdev
->dev
,
4485 "add mac ethertype failed for key conflict.\n");
4486 return_status
= -EIO
;
4489 dev_err(&hdev
->pdev
->dev
,
4490 "add mac ethertype failed for undefined, code=%d.\n",
4492 return_status
= -EIO
;
4495 return return_status
;
4498 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4499 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4501 struct hclge_desc desc
;
4506 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4507 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4509 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4511 dev_err(&hdev
->pdev
->dev
,
4512 "add mac ethertype failed for cmd_send, ret =%d.\n",
4517 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4518 retval
= le16_to_cpu(desc
.retval
);
4520 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4523 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4528 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4529 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4531 dev_err(&hdev
->pdev
->dev
,
4532 "add mac ethertype failed, ret =%d.\n",
4541 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4543 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4544 struct hclge_dev
*hdev
= vport
->back
;
4546 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4549 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4552 const unsigned char *new_addr
= (const unsigned char *)p
;
4553 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4554 struct hclge_dev
*hdev
= vport
->back
;
4557 /* mac addr check */
4558 if (is_zero_ether_addr(new_addr
) ||
4559 is_broadcast_ether_addr(new_addr
) ||
4560 is_multicast_ether_addr(new_addr
)) {
4561 dev_err(&hdev
->pdev
->dev
,
4562 "Change uc mac err! invalid mac:%p.\n",
4567 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4568 dev_warn(&hdev
->pdev
->dev
,
4569 "remove old uc mac address fail.\n");
4571 ret
= hclge_add_uc_addr(handle
, new_addr
);
4573 dev_err(&hdev
->pdev
->dev
,
4574 "add uc mac address fail, ret =%d.\n",
4578 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4579 dev_err(&hdev
->pdev
->dev
,
4580 "restore uc mac address fail.\n");
4585 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4587 dev_err(&hdev
->pdev
->dev
,
4588 "configure mac pause address fail, ret =%d.\n",
4593 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4598 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4601 struct hclge_vlan_filter_ctrl_cmd
*req
;
4602 struct hclge_desc desc
;
4605 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4607 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4608 req
->vlan_type
= vlan_type
;
4609 req
->vlan_fe
= filter_en
;
4611 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4613 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4619 #define HCLGE_FILTER_TYPE_VF 0
4620 #define HCLGE_FILTER_TYPE_PORT 1
4622 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4624 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4625 struct hclge_dev
*hdev
= vport
->back
;
4627 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4630 static int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4631 bool is_kill
, u16 vlan
, u8 qos
,
4634 #define HCLGE_MAX_VF_BYTES 16
4635 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4636 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4637 struct hclge_desc desc
[2];
4642 hclge_cmd_setup_basic_desc(&desc
[0],
4643 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4644 hclge_cmd_setup_basic_desc(&desc
[1],
4645 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4647 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4649 vf_byte_off
= vfid
/ 8;
4650 vf_byte_val
= 1 << (vfid
% 8);
4652 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4653 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4655 req0
->vlan_id
= cpu_to_le16(vlan
);
4656 req0
->vlan_cfg
= is_kill
;
4658 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4659 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4661 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4663 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4665 dev_err(&hdev
->pdev
->dev
,
4666 "Send vf vlan command fail, ret =%d.\n",
4672 #define HCLGE_VF_VLAN_NO_ENTRY 2
4673 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4676 if (req0
->resp_code
== HCLGE_VF_VLAN_NO_ENTRY
) {
4677 dev_warn(&hdev
->pdev
->dev
,
4678 "vf vlan table is full, vf vlan filter is disabled\n");
4682 dev_err(&hdev
->pdev
->dev
,
4683 "Add vf vlan filter fail, ret =%d.\n",
4686 if (!req0
->resp_code
)
4689 dev_err(&hdev
->pdev
->dev
,
4690 "Kill vf vlan filter fail, ret =%d.\n",
4697 static int hclge_set_port_vlan_filter(struct hclge_dev
*hdev
, __be16 proto
,
4698 u16 vlan_id
, bool is_kill
)
4700 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4701 struct hclge_desc desc
;
4702 u8 vlan_offset_byte_val
;
4703 u8 vlan_offset_byte
;
4707 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4709 vlan_offset_160
= vlan_id
/ 160;
4710 vlan_offset_byte
= (vlan_id
% 160) / 8;
4711 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4713 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4714 req
->vlan_offset
= vlan_offset_160
;
4715 req
->vlan_cfg
= is_kill
;
4716 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4718 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4720 dev_err(&hdev
->pdev
->dev
,
4721 "port vlan command, send fail, ret =%d.\n", ret
);
4725 static int hclge_set_vlan_filter_hw(struct hclge_dev
*hdev
, __be16 proto
,
4726 u16 vport_id
, u16 vlan_id
, u8 qos
,
4729 u16 vport_idx
, vport_num
= 0;
4732 ret
= hclge_set_vf_vlan_common(hdev
, vport_id
, is_kill
, vlan_id
,
4735 dev_err(&hdev
->pdev
->dev
,
4736 "Set %d vport vlan filter config fail, ret =%d.\n",
4741 /* vlan 0 may be added twice when 8021q module is enabled */
4742 if (!is_kill
&& !vlan_id
&&
4743 test_bit(vport_id
, hdev
->vlan_table
[vlan_id
]))
4746 if (!is_kill
&& test_and_set_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4747 dev_err(&hdev
->pdev
->dev
,
4748 "Add port vlan failed, vport %d is already in vlan %d\n",
4754 !test_and_clear_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4755 dev_err(&hdev
->pdev
->dev
,
4756 "Delete port vlan failed, vport %d is not in vlan %d\n",
4761 for_each_set_bit(vport_idx
, hdev
->vlan_table
[vlan_id
], VLAN_N_VID
)
4764 if ((is_kill
&& vport_num
== 0) || (!is_kill
&& vport_num
== 1))
4765 ret
= hclge_set_port_vlan_filter(hdev
, proto
, vlan_id
,
4771 int hclge_set_vlan_filter(struct hnae3_handle
*handle
, __be16 proto
,
4772 u16 vlan_id
, bool is_kill
)
4774 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4775 struct hclge_dev
*hdev
= vport
->back
;
4777 return hclge_set_vlan_filter_hw(hdev
, proto
, vport
->vport_id
, vlan_id
,
4781 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4782 u16 vlan
, u8 qos
, __be16 proto
)
4784 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4785 struct hclge_dev
*hdev
= vport
->back
;
4787 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4789 if (proto
!= htons(ETH_P_8021Q
))
4790 return -EPROTONOSUPPORT
;
4792 return hclge_set_vlan_filter_hw(hdev
, proto
, vfid
, vlan
, qos
, false);
4795 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4797 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4798 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4799 struct hclge_dev
*hdev
= vport
->back
;
4800 struct hclge_desc desc
;
4803 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4805 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4806 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4807 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4808 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG1_B
,
4809 vcfg
->accept_tag1
? 1 : 0);
4810 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG1_B
,
4811 vcfg
->accept_untag1
? 1 : 0);
4812 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG2_B
,
4813 vcfg
->accept_tag2
? 1 : 0);
4814 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG2_B
,
4815 vcfg
->accept_untag2
? 1 : 0);
4816 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4817 vcfg
->insert_tag1_en
? 1 : 0);
4818 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4819 vcfg
->insert_tag2_en
? 1 : 0);
4820 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4822 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4823 req
->vf_bitmap
[req
->vf_offset
] =
4824 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4826 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4828 dev_err(&hdev
->pdev
->dev
,
4829 "Send port txvlan cfg command fail, ret =%d\n",
4835 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4837 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4838 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4839 struct hclge_dev
*hdev
= vport
->back
;
4840 struct hclge_desc desc
;
4843 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4845 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4846 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4847 vcfg
->strip_tag1_en
? 1 : 0);
4848 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4849 vcfg
->strip_tag2_en
? 1 : 0);
4850 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4851 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4852 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4853 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4855 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4856 req
->vf_bitmap
[req
->vf_offset
] =
4857 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4859 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4861 dev_err(&hdev
->pdev
->dev
,
4862 "Send port rxvlan cfg command fail, ret =%d\n",
4868 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4870 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4871 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4872 struct hclge_desc desc
;
4875 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4876 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4877 rx_req
->ot_fst_vlan_type
=
4878 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4879 rx_req
->ot_sec_vlan_type
=
4880 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4881 rx_req
->in_fst_vlan_type
=
4882 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4883 rx_req
->in_sec_vlan_type
=
4884 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4886 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4888 dev_err(&hdev
->pdev
->dev
,
4889 "Send rxvlan protocol type command fail, ret =%d\n",
4894 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4896 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4897 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4898 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4900 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4902 dev_err(&hdev
->pdev
->dev
,
4903 "Send txvlan protocol type command fail, ret =%d\n",
4909 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4911 #define HCLGE_DEF_VLAN_TYPE 0x8100
4913 struct hnae3_handle
*handle
;
4914 struct hclge_vport
*vport
;
4918 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4922 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4926 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4927 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4928 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4929 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4930 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4931 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4933 ret
= hclge_set_vlan_protocol_type(hdev
);
4937 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4938 vport
= &hdev
->vport
[i
];
4939 vport
->txvlan_cfg
.accept_tag1
= true;
4940 vport
->txvlan_cfg
.accept_untag1
= true;
4942 /* accept_tag2 and accept_untag2 are not supported on
4943 * pdev revision(0x20), new revision support them. The
4944 * value of this two fields will not return error when driver
4945 * send command to fireware in revision(0x20).
4946 * This two fields can not configured by user.
4948 vport
->txvlan_cfg
.accept_tag2
= true;
4949 vport
->txvlan_cfg
.accept_untag2
= true;
4951 vport
->txvlan_cfg
.insert_tag1_en
= false;
4952 vport
->txvlan_cfg
.insert_tag2_en
= false;
4953 vport
->txvlan_cfg
.default_tag1
= 0;
4954 vport
->txvlan_cfg
.default_tag2
= 0;
4956 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4960 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4961 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4962 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4963 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4965 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4970 handle
= &hdev
->vport
[0].nic
;
4971 return hclge_set_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4974 int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4976 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4978 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4979 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4980 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4981 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4983 return hclge_set_vlan_rx_offload_cfg(vport
);
4986 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
4988 struct hclge_config_max_frm_size_cmd
*req
;
4989 struct hclge_desc desc
;
4993 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
4995 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
4996 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
4999 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
5001 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
5003 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
5004 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
5006 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5008 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
5010 hdev
->mps
= max_frm_size
;
5015 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
5017 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5018 struct hclge_dev
*hdev
= vport
->back
;
5021 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
5023 dev_err(&hdev
->pdev
->dev
,
5024 "Change mtu fail, ret =%d\n", ret
);
5028 ret
= hclge_buffer_alloc(hdev
);
5030 dev_err(&hdev
->pdev
->dev
,
5031 "Allocate buffer fail, ret =%d\n", ret
);
5036 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
5039 struct hclge_reset_tqp_queue_cmd
*req
;
5040 struct hclge_desc desc
;
5043 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
5045 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5046 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5047 hnae3_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
5049 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5051 dev_err(&hdev
->pdev
->dev
,
5052 "Send tqp reset cmd error, status =%d\n", ret
);
5059 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
5061 struct hclge_reset_tqp_queue_cmd
*req
;
5062 struct hclge_desc desc
;
5065 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
5067 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5068 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5070 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5072 dev_err(&hdev
->pdev
->dev
,
5073 "Get reset status error, status =%d\n", ret
);
5077 return hnae3_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
5080 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
5083 struct hnae3_queue
*queue
;
5084 struct hclge_tqp
*tqp
;
5086 queue
= handle
->kinfo
.tqp
[queue_id
];
5087 tqp
= container_of(queue
, struct hclge_tqp
, q
);
5092 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
5094 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5095 struct hclge_dev
*hdev
= vport
->back
;
5096 int reset_try_times
= 0;
5101 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
5104 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
5106 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
5108 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
5112 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5114 dev_warn(&hdev
->pdev
->dev
,
5115 "Send reset tqp cmd fail, ret = %d\n", ret
);
5119 reset_try_times
= 0;
5120 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5121 /* Wait for tqp hw reset */
5123 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5128 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5129 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5133 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5135 dev_warn(&hdev
->pdev
->dev
,
5136 "Deassert the soft reset fail, ret = %d\n", ret
);
5141 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
5143 struct hclge_dev
*hdev
= vport
->back
;
5144 int reset_try_times
= 0;
5149 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5151 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5153 dev_warn(&hdev
->pdev
->dev
,
5154 "Send reset tqp cmd fail, ret = %d\n", ret
);
5158 reset_try_times
= 0;
5159 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5160 /* Wait for tqp hw reset */
5162 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5167 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5168 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5172 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5174 dev_warn(&hdev
->pdev
->dev
,
5175 "Deassert the soft reset fail, ret = %d\n", ret
);
5178 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5180 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5181 struct hclge_dev
*hdev
= vport
->back
;
5183 return hdev
->fw_version
;
5186 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5189 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5190 struct hclge_dev
*hdev
= vport
->back
;
5191 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5196 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5197 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5200 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5202 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5207 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5210 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5213 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5216 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5221 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5222 else if (rx_en
&& !tx_en
)
5223 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5224 else if (!rx_en
&& tx_en
)
5225 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5227 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5229 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5232 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5234 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5239 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5244 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5246 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5247 u16 remote_advertising
= 0;
5248 u16 local_advertising
= 0;
5249 u32 rx_pause
, tx_pause
;
5252 if (!phydev
->link
|| !phydev
->autoneg
)
5255 if (phydev
->advertising
& ADVERTISED_Pause
)
5256 local_advertising
= ADVERTISE_PAUSE_CAP
;
5258 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5259 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5262 remote_advertising
= LPA_PAUSE_CAP
;
5264 if (phydev
->asym_pause
)
5265 remote_advertising
|= LPA_PAUSE_ASYM
;
5267 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5268 remote_advertising
);
5269 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5270 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5272 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5277 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5280 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5281 u32
*rx_en
, u32
*tx_en
)
5283 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5284 struct hclge_dev
*hdev
= vport
->back
;
5286 *auto_neg
= hclge_get_autoneg(handle
);
5288 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5294 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5297 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5300 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5309 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5310 u32 rx_en
, u32 tx_en
)
5312 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5313 struct hclge_dev
*hdev
= vport
->back
;
5314 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5317 fc_autoneg
= hclge_get_autoneg(handle
);
5318 if (auto_neg
!= fc_autoneg
) {
5319 dev_info(&hdev
->pdev
->dev
,
5320 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5324 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5325 dev_info(&hdev
->pdev
->dev
,
5326 "Priority flow control enabled. Cannot set link flow control.\n");
5330 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5333 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5335 /* Only support flow control negotiation for netdev with
5336 * phy attached for now.
5341 return phy_start_aneg(phydev
);
5344 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5345 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5347 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5348 struct hclge_dev
*hdev
= vport
->back
;
5351 *speed
= hdev
->hw
.mac
.speed
;
5353 *duplex
= hdev
->hw
.mac
.duplex
;
5355 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5358 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5360 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5361 struct hclge_dev
*hdev
= vport
->back
;
5364 *media_type
= hdev
->hw
.mac
.media_type
;
5367 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5368 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5370 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5371 struct hclge_dev
*hdev
= vport
->back
;
5372 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5373 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5376 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5377 *tp_mdix
= ETH_TP_MDI_INVALID
;
5381 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5383 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5384 mdix_ctrl
= hnae3_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5385 HCLGE_PHY_MDIX_CTRL_S
);
5387 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5388 mdix
= hnae3_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5389 is_resolved
= hnae3_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5391 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5393 switch (mdix_ctrl
) {
5395 *tp_mdix_ctrl
= ETH_TP_MDI
;
5398 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5401 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5404 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5409 *tp_mdix
= ETH_TP_MDI_INVALID
;
5411 *tp_mdix
= ETH_TP_MDI_X
;
5413 *tp_mdix
= ETH_TP_MDI
;
5416 static int hclge_init_client_instance(struct hnae3_client
*client
,
5417 struct hnae3_ae_dev
*ae_dev
)
5419 struct hclge_dev
*hdev
= ae_dev
->priv
;
5420 struct hclge_vport
*vport
;
5423 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5424 vport
= &hdev
->vport
[i
];
5426 switch (client
->type
) {
5427 case HNAE3_CLIENT_KNIC
:
5429 hdev
->nic_client
= client
;
5430 vport
->nic
.client
= client
;
5431 ret
= client
->ops
->init_instance(&vport
->nic
);
5435 if (hdev
->roce_client
&&
5436 hnae3_dev_roce_supported(hdev
)) {
5437 struct hnae3_client
*rc
= hdev
->roce_client
;
5439 ret
= hclge_init_roce_base_info(vport
);
5443 ret
= rc
->ops
->init_instance(&vport
->roce
);
5449 case HNAE3_CLIENT_UNIC
:
5450 hdev
->nic_client
= client
;
5451 vport
->nic
.client
= client
;
5453 ret
= client
->ops
->init_instance(&vport
->nic
);
5458 case HNAE3_CLIENT_ROCE
:
5459 if (hnae3_dev_roce_supported(hdev
)) {
5460 hdev
->roce_client
= client
;
5461 vport
->roce
.client
= client
;
5464 if (hdev
->roce_client
&& hdev
->nic_client
) {
5465 ret
= hclge_init_roce_base_info(vport
);
5469 ret
= client
->ops
->init_instance(&vport
->roce
);
5479 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5480 struct hnae3_ae_dev
*ae_dev
)
5482 struct hclge_dev
*hdev
= ae_dev
->priv
;
5483 struct hclge_vport
*vport
;
5486 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5487 vport
= &hdev
->vport
[i
];
5488 if (hdev
->roce_client
) {
5489 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5491 hdev
->roce_client
= NULL
;
5492 vport
->roce
.client
= NULL
;
5494 if (client
->type
== HNAE3_CLIENT_ROCE
)
5496 if (client
->ops
->uninit_instance
) {
5497 client
->ops
->uninit_instance(&vport
->nic
, 0);
5498 hdev
->nic_client
= NULL
;
5499 vport
->nic
.client
= NULL
;
5504 static int hclge_pci_init(struct hclge_dev
*hdev
)
5506 struct pci_dev
*pdev
= hdev
->pdev
;
5507 struct hclge_hw
*hw
;
5510 ret
= pci_enable_device(pdev
);
5512 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5516 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5518 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5521 "can't set consistent PCI DMA");
5522 goto err_disable_device
;
5524 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5527 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5529 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5530 goto err_disable_device
;
5533 pci_set_master(pdev
);
5535 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5537 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5539 goto err_clr_master
;
5542 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5546 pci_clear_master(pdev
);
5547 pci_release_regions(pdev
);
5549 pci_disable_device(pdev
);
5554 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5556 struct pci_dev
*pdev
= hdev
->pdev
;
5558 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5559 pci_free_irq_vectors(pdev
);
5560 pci_clear_master(pdev
);
5561 pci_release_mem_regions(pdev
);
5562 pci_disable_device(pdev
);
5565 static void hclge_state_init(struct hclge_dev
*hdev
)
5567 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5568 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5569 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5570 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5571 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5572 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5575 static void hclge_state_uninit(struct hclge_dev
*hdev
)
5577 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5579 if (hdev
->service_timer
.function
)
5580 del_timer_sync(&hdev
->service_timer
);
5581 if (hdev
->service_task
.func
)
5582 cancel_work_sync(&hdev
->service_task
);
5583 if (hdev
->rst_service_task
.func
)
5584 cancel_work_sync(&hdev
->rst_service_task
);
5585 if (hdev
->mbx_service_task
.func
)
5586 cancel_work_sync(&hdev
->mbx_service_task
);
5589 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5591 struct pci_dev
*pdev
= ae_dev
->pdev
;
5592 struct hclge_dev
*hdev
;
5595 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5602 hdev
->ae_dev
= ae_dev
;
5603 hdev
->reset_type
= HNAE3_NONE_RESET
;
5604 ae_dev
->priv
= hdev
;
5606 ret
= hclge_pci_init(hdev
);
5608 dev_err(&pdev
->dev
, "PCI init failed\n");
5612 /* Firmware command queue initialize */
5613 ret
= hclge_cmd_queue_init(hdev
);
5615 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5616 goto err_pci_uninit
;
5619 /* Firmware command initialize */
5620 ret
= hclge_cmd_init(hdev
);
5622 goto err_cmd_uninit
;
5624 ret
= hclge_get_cap(hdev
);
5626 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5628 goto err_cmd_uninit
;
5631 ret
= hclge_configure(hdev
);
5633 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5634 goto err_cmd_uninit
;
5637 ret
= hclge_init_msi(hdev
);
5639 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5640 goto err_cmd_uninit
;
5643 ret
= hclge_misc_irq_init(hdev
);
5646 "Misc IRQ(vector0) init error, ret = %d.\n",
5648 goto err_msi_uninit
;
5651 ret
= hclge_alloc_tqps(hdev
);
5653 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5654 goto err_msi_irq_uninit
;
5657 ret
= hclge_alloc_vport(hdev
);
5659 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5660 goto err_msi_irq_uninit
;
5663 ret
= hclge_map_tqp(hdev
);
5665 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5666 goto err_msi_irq_uninit
;
5669 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5670 ret
= hclge_mac_mdio_config(hdev
);
5672 dev_err(&hdev
->pdev
->dev
,
5673 "mdio config fail ret=%d\n", ret
);
5674 goto err_msi_irq_uninit
;
5678 ret
= hclge_mac_init(hdev
);
5680 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5681 goto err_mdiobus_unreg
;
5684 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5686 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5687 goto err_mdiobus_unreg
;
5690 ret
= hclge_init_vlan_config(hdev
);
5692 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5693 goto err_mdiobus_unreg
;
5696 ret
= hclge_tm_schd_init(hdev
);
5698 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5699 goto err_mdiobus_unreg
;
5702 hclge_rss_init_cfg(hdev
);
5703 ret
= hclge_rss_init_hw(hdev
);
5705 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5706 goto err_mdiobus_unreg
;
5709 ret
= init_mgr_tbl(hdev
);
5711 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5712 goto err_mdiobus_unreg
;
5715 hclge_dcb_ops_set(hdev
);
5717 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5718 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5719 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5720 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5722 /* Enable MISC vector(vector0) */
5723 hclge_enable_vector(&hdev
->misc_vector
, true);
5725 hclge_state_init(hdev
);
5727 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5731 if (hdev
->hw
.mac
.phydev
)
5732 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5734 hclge_misc_irq_uninit(hdev
);
5736 pci_free_irq_vectors(pdev
);
5738 hclge_destroy_cmd_queue(&hdev
->hw
);
5740 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5741 pci_clear_master(pdev
);
5742 pci_release_regions(pdev
);
5743 pci_disable_device(pdev
);
5748 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5750 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5753 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5755 struct hclge_dev
*hdev
= ae_dev
->priv
;
5756 struct pci_dev
*pdev
= ae_dev
->pdev
;
5759 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5761 hclge_stats_clear(hdev
);
5762 memset(hdev
->vlan_table
, 0, sizeof(hdev
->vlan_table
));
5764 ret
= hclge_cmd_init(hdev
);
5766 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5770 ret
= hclge_get_cap(hdev
);
5772 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5777 ret
= hclge_configure(hdev
);
5779 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5783 ret
= hclge_map_tqp(hdev
);
5785 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5789 ret
= hclge_mac_init(hdev
);
5791 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5795 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5797 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5801 ret
= hclge_init_vlan_config(hdev
);
5803 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5807 ret
= hclge_tm_init_hw(hdev
);
5809 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5813 ret
= hclge_rss_init_hw(hdev
);
5815 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5819 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5825 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5827 struct hclge_dev
*hdev
= ae_dev
->priv
;
5828 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5830 hclge_state_uninit(hdev
);
5833 mdiobus_unregister(mac
->mdio_bus
);
5835 /* Disable MISC vector(vector0) */
5836 hclge_enable_vector(&hdev
->misc_vector
, false);
5837 hclge_destroy_cmd_queue(&hdev
->hw
);
5838 hclge_misc_irq_uninit(hdev
);
5839 hclge_pci_uninit(hdev
);
5840 ae_dev
->priv
= NULL
;
5843 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5845 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5846 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5847 struct hclge_dev
*hdev
= vport
->back
;
5849 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5852 static void hclge_get_channels(struct hnae3_handle
*handle
,
5853 struct ethtool_channels
*ch
)
5855 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5857 ch
->max_combined
= hclge_get_max_channels(handle
);
5858 ch
->other_count
= 1;
5860 ch
->combined_count
= vport
->alloc_tqps
;
5863 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5864 u16
*free_tqps
, u16
*max_rss_size
)
5866 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5867 struct hclge_dev
*hdev
= vport
->back
;
5871 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5872 if (!hdev
->htqp
[i
].alloced
)
5875 *free_tqps
= temp_tqps
;
5876 *max_rss_size
= hdev
->rss_size_max
;
5879 static void hclge_release_tqp(struct hclge_vport
*vport
)
5881 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5882 struct hclge_dev
*hdev
= vport
->back
;
5885 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5886 struct hclge_tqp
*tqp
=
5887 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5889 tqp
->q
.handle
= NULL
;
5890 tqp
->q
.tqp_index
= 0;
5891 tqp
->alloced
= false;
5894 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5898 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5900 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5901 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5902 struct hclge_dev
*hdev
= vport
->back
;
5903 int cur_rss_size
= kinfo
->rss_size
;
5904 int cur_tqps
= kinfo
->num_tqps
;
5905 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5906 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5907 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5912 hclge_release_tqp(vport
);
5914 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5916 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5920 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5922 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5926 ret
= hclge_tm_schd_init(hdev
);
5928 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5932 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5933 roundup_size
= ilog2(roundup_size
);
5934 /* Set the RSS TC mode according to the new RSS size */
5935 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5938 if (!(hdev
->hw_tc_map
& BIT(i
)))
5942 tc_size
[i
] = roundup_size
;
5943 tc_offset
[i
] = kinfo
->rss_size
* i
;
5945 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5949 /* Reinitializes the rss indirect table according to the new RSS size */
5950 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5954 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5955 rss_indir
[i
] = i
% kinfo
->rss_size
;
5957 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5959 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5965 dev_info(&hdev
->pdev
->dev
,
5966 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5967 cur_rss_size
, kinfo
->rss_size
,
5968 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5973 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5974 u32
*regs_num_64_bit
)
5976 struct hclge_desc desc
;
5980 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
5981 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5983 dev_err(&hdev
->pdev
->dev
,
5984 "Query register number cmd failed, ret = %d.\n", ret
);
5988 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
5989 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
5991 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
5998 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6001 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6003 struct hclge_desc
*desc
;
6004 u32
*reg_val
= data
;
6013 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
6014 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6018 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
6019 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6021 dev_err(&hdev
->pdev
->dev
,
6022 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
6027 for (i
= 0; i
< cmd_num
; i
++) {
6029 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
6030 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
6032 desc_data
= (__le32
*)(&desc
[i
]);
6033 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
6035 for (k
= 0; k
< n
; k
++) {
6036 *reg_val
++ = le32_to_cpu(*desc_data
++);
6048 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6051 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6053 struct hclge_desc
*desc
;
6054 u64
*reg_val
= data
;
6063 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
6064 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6068 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
6069 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6071 dev_err(&hdev
->pdev
->dev
,
6072 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
6077 for (i
= 0; i
< cmd_num
; i
++) {
6079 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
6080 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
6082 desc_data
= (__le64
*)(&desc
[i
]);
6083 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
6085 for (k
= 0; k
< n
; k
++) {
6086 *reg_val
++ = le64_to_cpu(*desc_data
++);
6098 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
6100 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6101 struct hclge_dev
*hdev
= vport
->back
;
6102 u32 regs_num_32_bit
, regs_num_64_bit
;
6105 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6107 dev_err(&hdev
->pdev
->dev
,
6108 "Get register number failed, ret = %d.\n", ret
);
6112 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
6115 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
6118 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6119 struct hclge_dev
*hdev
= vport
->back
;
6120 u32 regs_num_32_bit
, regs_num_64_bit
;
6123 *version
= hdev
->fw_version
;
6125 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6127 dev_err(&hdev
->pdev
->dev
,
6128 "Get register number failed, ret = %d.\n", ret
);
6132 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
6134 dev_err(&hdev
->pdev
->dev
,
6135 "Get 32 bit register failed, ret = %d.\n", ret
);
6139 data
= (u32
*)data
+ regs_num_32_bit
;
6140 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
6143 dev_err(&hdev
->pdev
->dev
,
6144 "Get 64 bit register failed, ret = %d.\n", ret
);
6147 static int hclge_set_led_status(struct hclge_dev
*hdev
, u8 locate_led_status
)
6149 struct hclge_set_led_state_cmd
*req
;
6150 struct hclge_desc desc
;
6153 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6155 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6156 hnae3_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6157 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6159 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6161 dev_err(&hdev
->pdev
->dev
,
6162 "Send set led state cmd error, ret =%d\n", ret
);
6167 enum hclge_led_status
{
6170 HCLGE_LED_NO_CHANGE
= 0xFF,
6173 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6174 enum ethtool_phys_id_state status
)
6176 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6177 struct hclge_dev
*hdev
= vport
->back
;
6180 case ETHTOOL_ID_ACTIVE
:
6181 return hclge_set_led_status(hdev
, HCLGE_LED_ON
);
6182 case ETHTOOL_ID_INACTIVE
:
6183 return hclge_set_led_status(hdev
, HCLGE_LED_OFF
);
6189 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6190 unsigned long *supported
,
6191 unsigned long *advertising
)
6193 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6194 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6195 struct hclge_dev
*hdev
= vport
->back
;
6196 unsigned int idx
= 0;
6198 for (; idx
< size
; idx
++) {
6199 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6200 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6204 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6207 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6208 struct hclge_dev
*hdev
= vport
->back
;
6209 u8 media_type
= hdev
->hw
.mac
.media_type
;
6211 switch (media_type
) {
6212 case HNAE3_MEDIA_TYPE_FIBER
:
6213 *port_type
= PORT_FIBRE
;
6215 case HNAE3_MEDIA_TYPE_COPPER
:
6216 *port_type
= PORT_TP
;
6218 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6220 *port_type
= PORT_OTHER
;
6225 static const struct hnae3_ae_ops hclge_ops
= {
6226 .init_ae_dev
= hclge_init_ae_dev
,
6227 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6228 .init_client_instance
= hclge_init_client_instance
,
6229 .uninit_client_instance
= hclge_uninit_client_instance
,
6230 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6231 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6232 .get_vector
= hclge_get_vector
,
6233 .put_vector
= hclge_put_vector
,
6234 .set_promisc_mode
= hclge_set_promisc_mode
,
6235 .set_loopback
= hclge_set_loopback
,
6236 .start
= hclge_ae_start
,
6237 .stop
= hclge_ae_stop
,
6238 .get_status
= hclge_get_status
,
6239 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6240 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6241 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6242 .get_media_type
= hclge_get_media_type
,
6243 .get_rss_key_size
= hclge_get_rss_key_size
,
6244 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6245 .get_rss
= hclge_get_rss
,
6246 .set_rss
= hclge_set_rss
,
6247 .set_rss_tuple
= hclge_set_rss_tuple
,
6248 .get_rss_tuple
= hclge_get_rss_tuple
,
6249 .get_tc_size
= hclge_get_tc_size
,
6250 .get_mac_addr
= hclge_get_mac_addr
,
6251 .set_mac_addr
= hclge_set_mac_addr
,
6252 .add_uc_addr
= hclge_add_uc_addr
,
6253 .rm_uc_addr
= hclge_rm_uc_addr
,
6254 .add_mc_addr
= hclge_add_mc_addr
,
6255 .rm_mc_addr
= hclge_rm_mc_addr
,
6256 .update_mta_status
= hclge_update_mta_status
,
6257 .set_autoneg
= hclge_set_autoneg
,
6258 .get_autoneg
= hclge_get_autoneg
,
6259 .get_pauseparam
= hclge_get_pauseparam
,
6260 .set_pauseparam
= hclge_set_pauseparam
,
6261 .set_mtu
= hclge_set_mtu
,
6262 .reset_queue
= hclge_reset_tqp
,
6263 .get_stats
= hclge_get_stats
,
6264 .update_stats
= hclge_update_stats
,
6265 .get_strings
= hclge_get_strings
,
6266 .get_sset_count
= hclge_get_sset_count
,
6267 .get_fw_version
= hclge_get_fw_version
,
6268 .get_mdix_mode
= hclge_get_mdix_mode
,
6269 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6270 .set_vlan_filter
= hclge_set_vlan_filter
,
6271 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6272 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6273 .reset_event
= hclge_reset_event
,
6274 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6275 .set_channels
= hclge_set_channels
,
6276 .get_channels
= hclge_get_channels
,
6277 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6278 .get_regs_len
= hclge_get_regs_len
,
6279 .get_regs
= hclge_get_regs
,
6280 .set_led_id
= hclge_set_led_id
,
6281 .get_link_mode
= hclge_get_link_mode
,
6282 .get_port_type
= hclge_get_port_type
,
6285 static struct hnae3_ae_algo ae_algo
= {
6287 .pdev_id_table
= ae_algo_pci_tbl
,
6290 static int hclge_init(void)
6292 pr_info("%s is initializing\n", HCLGE_NAME
);
6294 hnae3_register_ae_algo(&ae_algo
);
6299 static void hclge_exit(void)
6301 hnae3_unregister_ae_algo(&ae_algo
);
6303 module_init(hclge_init
);
6304 module_exit(hclge_exit
);
6306 MODULE_LICENSE("GPL");
6307 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6308 MODULE_DESCRIPTION("HCLGE Driver");
6309 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob