1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/acpi.h>
5 #include <linux/device.h>
6 #include <linux/etherdevice.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/netdevice.h>
12 #include <linux/pci.h>
13 #include <linux/platform_device.h>
14 #include <linux/if_vlan.h>
15 #include <net/rtnetlink.h>
16 #include "hclge_cmd.h"
17 #include "hclge_dcb.h"
18 #include "hclge_main.h"
19 #include "hclge_mbx.h"
20 #include "hclge_mdio.h"
24 #define HCLGE_NAME "hclge"
25 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
27 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
28 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
30 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
31 enum hclge_mta_dmac_sel_type mta_mac_sel
,
33 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
34 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
35 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
37 static struct hnae3_ae_algo ae_algo
;
39 static const struct pci_device_id ae_algo_pci_tbl
[] = {
40 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
41 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
42 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
43 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
44 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
45 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
47 /* required last entry */
51 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
53 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
55 "Serdes Loopback test",
59 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
98 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
223 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
280 {"mac_tx_oversize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
294 {"mac_tx_1519_2047_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
296 {"mac_tx_2048_4095_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
298 {"mac_tx_4096_8191_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
300 {"mac_tx_8192_9216_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
302 {"mac_tx_9217_12287_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
304 {"mac_tx_12288_16383_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
306 {"mac_tx_1519_max_good_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
308 {"mac_tx_1519_max_bad_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
310 {"mac_rx_total_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
312 {"mac_rx_total_oct_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
314 {"mac_rx_good_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
316 {"mac_rx_bad_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
318 {"mac_rx_good_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
320 {"mac_rx_bad_oct_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
322 {"mac_rx_uni_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
324 {"mac_rx_multi_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
326 {"mac_rx_broad_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
328 {"mac_rx_undersize_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
330 {"mac_rx_oversize_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
332 {"mac_rx_64_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
334 {"mac_rx_65_127_oct_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
336 {"mac_rx_128_255_oct_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
338 {"mac_rx_256_511_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
340 {"mac_rx_512_1023_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
342 {"mac_rx_1024_1518_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
344 {"mac_rx_1519_2047_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
346 {"mac_rx_2048_4095_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
348 {"mac_rx_4096_8191_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
350 {"mac_rx_8192_9216_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
352 {"mac_rx_9217_12287_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
354 {"mac_rx_12288_16383_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
356 {"mac_rx_1519_max_good_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
358 {"mac_rx_1519_max_bad_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
361 {"mac_tx_fragment_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
363 {"mac_tx_undermin_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
365 {"mac_tx_jabber_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
367 {"mac_tx_err_all_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
369 {"mac_tx_from_app_good_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
371 {"mac_tx_from_app_bad_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
373 {"mac_rx_fragment_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
375 {"mac_rx_undermin_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
377 {"mac_rx_jabber_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
379 {"mac_rx_fcs_err_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
381 {"mac_rx_send_app_good_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
383 {"mac_rx_send_app_bad_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
387 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
389 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
390 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
391 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
392 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
393 .i_port_bitmap
= 0x1,
397 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
399 #define HCLGE_64_BIT_CMD_NUM 5
400 #define HCLGE_64_BIT_RTN_DATANUM 4
401 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
402 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
407 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
408 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
410 dev_err(&hdev
->pdev
->dev
,
411 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
415 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
416 if (unlikely(i
== 0)) {
417 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
418 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
420 desc_data
= (__le64
*)(&desc
[i
]);
421 n
= HCLGE_64_BIT_RTN_DATANUM
;
423 for (k
= 0; k
< n
; k
++) {
424 *data
++ += le64_to_cpu(*desc_data
);
432 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
434 stats
->pkt_curr_buf_cnt
= 0;
435 stats
->pkt_curr_buf_tc0_cnt
= 0;
436 stats
->pkt_curr_buf_tc1_cnt
= 0;
437 stats
->pkt_curr_buf_tc2_cnt
= 0;
438 stats
->pkt_curr_buf_tc3_cnt
= 0;
439 stats
->pkt_curr_buf_tc4_cnt
= 0;
440 stats
->pkt_curr_buf_tc5_cnt
= 0;
441 stats
->pkt_curr_buf_tc6_cnt
= 0;
442 stats
->pkt_curr_buf_tc7_cnt
= 0;
445 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
447 #define HCLGE_32_BIT_CMD_NUM 8
448 #define HCLGE_32_BIT_RTN_DATANUM 8
450 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
451 struct hclge_32_bit_stats
*all_32_bit_stats
;
457 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
458 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
460 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
461 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
463 dev_err(&hdev
->pdev
->dev
,
464 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
469 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
470 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
471 if (unlikely(i
== 0)) {
472 __le16
*desc_data_16bit
;
474 all_32_bit_stats
->igu_rx_err_pkt
+=
475 le32_to_cpu(desc
[i
].data
[0]);
477 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
478 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
479 le16_to_cpu(*desc_data_16bit
);
482 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
483 le16_to_cpu(*desc_data_16bit
);
485 desc_data
= &desc
[i
].data
[2];
486 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
488 desc_data
= (__le32
*)&desc
[i
];
489 n
= HCLGE_32_BIT_RTN_DATANUM
;
491 for (k
= 0; k
< n
; k
++) {
492 *data
++ += le32_to_cpu(*desc_data
);
500 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
502 #define HCLGE_MAC_CMD_NUM 21
503 #define HCLGE_RTN_DATA_NUM 4
505 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
506 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
511 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
512 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
514 dev_err(&hdev
->pdev
->dev
,
515 "Get MAC pkt stats fail, status = %d.\n", ret
);
520 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
521 if (unlikely(i
== 0)) {
522 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
523 n
= HCLGE_RTN_DATA_NUM
- 2;
525 desc_data
= (__le64
*)(&desc
[i
]);
526 n
= HCLGE_RTN_DATA_NUM
;
528 for (k
= 0; k
< n
; k
++) {
529 *data
++ += le64_to_cpu(*desc_data
);
537 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
539 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
540 struct hclge_vport
*vport
= hclge_get_vport(handle
);
541 struct hclge_dev
*hdev
= vport
->back
;
542 struct hnae3_queue
*queue
;
543 struct hclge_desc desc
[1];
544 struct hclge_tqp
*tqp
;
547 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
548 queue
= handle
->kinfo
.tqp
[i
];
549 tqp
= container_of(queue
, struct hclge_tqp
, q
);
550 /* command : HCLGE_OPC_QUERY_IGU_STAT */
551 hclge_cmd_setup_basic_desc(&desc
[0],
552 HCLGE_OPC_QUERY_RX_STATUS
,
555 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
556 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
558 dev_err(&hdev
->pdev
->dev
,
559 "Query tqp stat fail, status = %d,queue = %d\n",
563 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
564 le32_to_cpu(desc
[0].data
[1]);
567 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
568 queue
= handle
->kinfo
.tqp
[i
];
569 tqp
= container_of(queue
, struct hclge_tqp
, q
);
570 /* command : HCLGE_OPC_QUERY_IGU_STAT */
571 hclge_cmd_setup_basic_desc(&desc
[0],
572 HCLGE_OPC_QUERY_TX_STATUS
,
575 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
576 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
578 dev_err(&hdev
->pdev
->dev
,
579 "Query tqp stat fail, status = %d,queue = %d\n",
583 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
584 le32_to_cpu(desc
[0].data
[1]);
590 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
592 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
593 struct hclge_tqp
*tqp
;
597 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
598 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
599 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
602 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
603 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
604 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
610 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
612 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
614 return kinfo
->num_tqps
* (2);
617 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
619 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
623 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
624 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
625 struct hclge_tqp
, q
);
626 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
628 buff
= buff
+ ETH_GSTRING_LEN
;
631 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
632 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
633 struct hclge_tqp
, q
);
634 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
636 buff
= buff
+ ETH_GSTRING_LEN
;
642 static u64
*hclge_comm_get_stats(void *comm_stats
,
643 const struct hclge_comm_stats_str strs
[],
649 for (i
= 0; i
< size
; i
++)
650 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
655 static u8
*hclge_comm_get_strings(u32 stringset
,
656 const struct hclge_comm_stats_str strs
[],
659 char *buff
= (char *)data
;
662 if (stringset
!= ETH_SS_STATS
)
665 for (i
= 0; i
< size
; i
++) {
666 snprintf(buff
, ETH_GSTRING_LEN
,
668 buff
= buff
+ ETH_GSTRING_LEN
;
674 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
675 struct net_device_stats
*net_stats
)
677 net_stats
->tx_dropped
= 0;
678 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
679 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
680 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
682 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
683 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
684 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
685 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
686 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
688 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
689 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
691 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
692 net_stats
->rx_length_errors
=
693 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
694 net_stats
->rx_length_errors
+=
695 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
696 net_stats
->rx_over_errors
=
697 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
700 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
702 struct hnae3_handle
*handle
;
705 handle
= &hdev
->vport
[0].nic
;
706 if (handle
->client
) {
707 status
= hclge_tqps_update_stats(handle
);
709 dev_err(&hdev
->pdev
->dev
,
710 "Update TQPS stats fail, status = %d.\n",
715 status
= hclge_mac_update_stats(hdev
);
717 dev_err(&hdev
->pdev
->dev
,
718 "Update MAC stats fail, status = %d.\n", status
);
720 status
= hclge_32_bit_update_stats(hdev
);
722 dev_err(&hdev
->pdev
->dev
,
723 "Update 32 bit stats fail, status = %d.\n",
726 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
729 static void hclge_update_stats(struct hnae3_handle
*handle
,
730 struct net_device_stats
*net_stats
)
732 struct hclge_vport
*vport
= hclge_get_vport(handle
);
733 struct hclge_dev
*hdev
= vport
->back
;
734 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
737 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
740 status
= hclge_mac_update_stats(hdev
);
742 dev_err(&hdev
->pdev
->dev
,
743 "Update MAC stats fail, status = %d.\n",
746 status
= hclge_32_bit_update_stats(hdev
);
748 dev_err(&hdev
->pdev
->dev
,
749 "Update 32 bit stats fail, status = %d.\n",
752 status
= hclge_64_bit_update_stats(hdev
);
754 dev_err(&hdev
->pdev
->dev
,
755 "Update 64 bit stats fail, status = %d.\n",
758 status
= hclge_tqps_update_stats(handle
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update TQPS stats fail, status = %d.\n",
764 hclge_update_netstat(hw_stats
, net_stats
);
766 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
769 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
771 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
773 struct hclge_vport
*vport
= hclge_get_vport(handle
);
774 struct hclge_dev
*hdev
= vport
->back
;
777 /* Loopback test support rules:
778 * mac: only GE mode support
779 * serdes: all mac mode will support include GE/XGE/LGE/CGE
780 * phy: only support when phy device exist on board
782 if (stringset
== ETH_SS_TEST
) {
783 /* clear loopback bit flags at first */
784 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
785 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
786 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
787 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
789 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
793 handle
->flags
|= HNAE3_SUPPORT_SERDES_LOOPBACK
;
794 } else if (stringset
== ETH_SS_STATS
) {
795 count
= ARRAY_SIZE(g_mac_stats_string
) +
796 ARRAY_SIZE(g_all_32bit_stats_string
) +
797 ARRAY_SIZE(g_all_64bit_stats_string
) +
798 hclge_tqps_get_sset_count(handle
, stringset
);
804 static void hclge_get_strings(struct hnae3_handle
*handle
,
808 u8
*p
= (char *)data
;
811 if (stringset
== ETH_SS_STATS
) {
812 size
= ARRAY_SIZE(g_mac_stats_string
);
813 p
= hclge_comm_get_strings(stringset
,
817 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
818 p
= hclge_comm_get_strings(stringset
,
819 g_all_32bit_stats_string
,
822 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
823 p
= hclge_comm_get_strings(stringset
,
824 g_all_64bit_stats_string
,
827 p
= hclge_tqps_get_strings(handle
, p
);
828 } else if (stringset
== ETH_SS_TEST
) {
829 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
831 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
833 p
+= ETH_GSTRING_LEN
;
835 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
837 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
839 p
+= ETH_GSTRING_LEN
;
841 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
843 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
845 p
+= ETH_GSTRING_LEN
;
850 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
852 struct hclge_vport
*vport
= hclge_get_vport(handle
);
853 struct hclge_dev
*hdev
= vport
->back
;
856 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
858 ARRAY_SIZE(g_mac_stats_string
),
860 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
861 g_all_32bit_stats_string
,
862 ARRAY_SIZE(g_all_32bit_stats_string
),
864 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
865 g_all_64bit_stats_string
,
866 ARRAY_SIZE(g_all_64bit_stats_string
),
868 p
= hclge_tqps_get_stats(handle
, p
);
871 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
872 struct hclge_func_status_cmd
*status
)
874 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
877 /* Set the pf to main pf */
878 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
879 hdev
->flag
|= HCLGE_FLAG_MAIN
;
881 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
886 static int hclge_query_function_status(struct hclge_dev
*hdev
)
888 struct hclge_func_status_cmd
*req
;
889 struct hclge_desc desc
;
893 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
894 req
= (struct hclge_func_status_cmd
*)desc
.data
;
897 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
899 dev_err(&hdev
->pdev
->dev
,
900 "query function status failed %d.\n",
906 /* Check pf reset is done */
909 usleep_range(1000, 2000);
910 } while (timeout
++ < 5);
912 ret
= hclge_parse_func_status(hdev
, req
);
917 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
919 struct hclge_pf_res_cmd
*req
;
920 struct hclge_desc desc
;
923 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
924 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
926 dev_err(&hdev
->pdev
->dev
,
927 "query pf resource failed %d.\n", ret
);
931 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
932 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
933 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
935 if (hnae3_dev_roce_supported(hdev
)) {
937 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
938 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
940 /* PF should have NIC vectors and Roce vectors,
941 * NIC vectors are queued before Roce vectors.
943 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
946 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
947 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
953 static int hclge_parse_speed(int speed_cmd
, int *speed
)
957 *speed
= HCLGE_MAC_SPEED_10M
;
960 *speed
= HCLGE_MAC_SPEED_100M
;
963 *speed
= HCLGE_MAC_SPEED_1G
;
966 *speed
= HCLGE_MAC_SPEED_10G
;
969 *speed
= HCLGE_MAC_SPEED_25G
;
972 *speed
= HCLGE_MAC_SPEED_40G
;
975 *speed
= HCLGE_MAC_SPEED_50G
;
978 *speed
= HCLGE_MAC_SPEED_100G
;
987 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
990 unsigned long *supported
= hdev
->hw
.mac
.supported
;
992 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
993 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
996 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
997 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1000 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1001 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1004 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1005 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1008 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1009 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1012 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1013 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1016 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1018 u8 media_type
= hdev
->hw
.mac
.media_type
;
1020 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1023 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1026 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1028 struct hclge_cfg_param_cmd
*req
;
1029 u64 mac_addr_tmp_high
;
1033 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1035 /* get the configuration */
1036 cfg
->vmdq_vport_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1039 cfg
->tc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1040 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1041 cfg
->tqp_desc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1042 HCLGE_CFG_TQP_DESC_N_M
,
1043 HCLGE_CFG_TQP_DESC_N_S
);
1045 cfg
->phy_addr
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1046 HCLGE_CFG_PHY_ADDR_M
,
1047 HCLGE_CFG_PHY_ADDR_S
);
1048 cfg
->media_type
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1049 HCLGE_CFG_MEDIA_TP_M
,
1050 HCLGE_CFG_MEDIA_TP_S
);
1051 cfg
->rx_buf_len
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1052 HCLGE_CFG_RX_BUF_LEN_M
,
1053 HCLGE_CFG_RX_BUF_LEN_S
);
1054 /* get mac_address */
1055 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1056 mac_addr_tmp_high
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1057 HCLGE_CFG_MAC_ADDR_H_M
,
1058 HCLGE_CFG_MAC_ADDR_H_S
);
1060 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1062 cfg
->default_speed
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1063 HCLGE_CFG_DEFAULT_SPEED_M
,
1064 HCLGE_CFG_DEFAULT_SPEED_S
);
1065 cfg
->rss_size_max
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1066 HCLGE_CFG_RSS_SIZE_M
,
1067 HCLGE_CFG_RSS_SIZE_S
);
1069 for (i
= 0; i
< ETH_ALEN
; i
++)
1070 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1072 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1073 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1075 cfg
->speed_ability
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1076 HCLGE_CFG_SPEED_ABILITY_M
,
1077 HCLGE_CFG_SPEED_ABILITY_S
);
1080 /* hclge_get_cfg: query the static parameter from flash
1081 * @hdev: pointer to struct hclge_dev
1082 * @hcfg: the config structure to be getted
1084 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1086 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1087 struct hclge_cfg_param_cmd
*req
;
1090 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1093 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1094 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1096 hnae3_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1097 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1098 /* Len should be united by 4 bytes when send to hardware */
1099 hnae3_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1100 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1101 req
->offset
= cpu_to_le32(offset
);
1104 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1106 dev_err(&hdev
->pdev
->dev
, "get config failed %d.\n", ret
);
1110 hclge_parse_cfg(hcfg
, desc
);
1115 static int hclge_get_cap(struct hclge_dev
*hdev
)
1119 ret
= hclge_query_function_status(hdev
);
1121 dev_err(&hdev
->pdev
->dev
,
1122 "query function status error %d.\n", ret
);
1126 /* get pf resource */
1127 ret
= hclge_query_pf_resource(hdev
);
1129 dev_err(&hdev
->pdev
->dev
, "query pf resource error %d.\n", ret
);
1134 static int hclge_configure(struct hclge_dev
*hdev
)
1136 struct hclge_cfg cfg
;
1139 ret
= hclge_get_cfg(hdev
, &cfg
);
1141 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1145 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1146 hdev
->base_tqp_pid
= 0;
1147 hdev
->rss_size_max
= cfg
.rss_size_max
;
1148 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1149 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1150 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1151 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1152 hdev
->num_desc
= cfg
.tqp_desc_num
;
1153 hdev
->tm_info
.num_pg
= 1;
1154 hdev
->tc_max
= cfg
.tc_num
;
1155 hdev
->tm_info
.hw_pfc_map
= 0;
1157 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1159 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1163 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1165 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1166 (hdev
->tc_max
< 1)) {
1167 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1172 /* Dev does not support DCB */
1173 if (!hnae3_dev_dcb_supported(hdev
)) {
1177 hdev
->pfc_max
= hdev
->tc_max
;
1180 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1182 /* Currently not support uncontiuous tc */
1183 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1184 hnae3_set_bit(hdev
->hw_tc_map
, i
, 1);
1186 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1191 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1194 struct hclge_cfg_tso_status_cmd
*req
;
1195 struct hclge_desc desc
;
1198 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1200 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1203 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1204 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1205 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1208 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1209 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1210 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1212 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1215 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1217 struct hclge_tqp
*tqp
;
1220 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1221 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1227 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1228 tqp
->dev
= &hdev
->pdev
->dev
;
1231 tqp
->q
.ae_algo
= &ae_algo
;
1232 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1233 tqp
->q
.desc_num
= hdev
->num_desc
;
1234 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1235 i
* HCLGE_TQP_REG_SIZE
;
1243 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1244 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1246 struct hclge_tqp_map_cmd
*req
;
1247 struct hclge_desc desc
;
1250 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1252 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1253 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1254 req
->tqp_vf
= func_id
;
1255 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1256 1 << HCLGE_TQP_MAP_EN_B
;
1257 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1259 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1261 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n", ret
);
1266 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1267 struct hnae3_queue
**tqp
, u16 num_tqps
)
1269 struct hclge_dev
*hdev
= vport
->back
;
1272 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1273 alloced
< num_tqps
; i
++) {
1274 if (!hdev
->htqp
[i
].alloced
) {
1275 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1276 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1277 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1278 hdev
->htqp
[i
].alloced
= true;
1282 vport
->alloc_tqps
= num_tqps
;
1287 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1289 struct hnae3_handle
*nic
= &vport
->nic
;
1290 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1291 struct hclge_dev
*hdev
= vport
->back
;
1294 kinfo
->num_desc
= hdev
->num_desc
;
1295 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1296 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1298 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1299 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1301 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1302 if (hdev
->hw_tc_map
& BIT(i
)) {
1303 kinfo
->tc_info
[i
].enable
= true;
1304 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1305 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1306 kinfo
->tc_info
[i
].tc
= i
;
1308 /* Set to default queue if TC is disable */
1309 kinfo
->tc_info
[i
].enable
= false;
1310 kinfo
->tc_info
[i
].tqp_offset
= 0;
1311 kinfo
->tc_info
[i
].tqp_count
= 1;
1312 kinfo
->tc_info
[i
].tc
= 0;
1316 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1317 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1321 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1323 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1328 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1329 struct hclge_vport
*vport
)
1331 struct hnae3_handle
*nic
= &vport
->nic
;
1332 struct hnae3_knic_private_info
*kinfo
;
1335 kinfo
= &nic
->kinfo
;
1336 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1337 struct hclge_tqp
*q
=
1338 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1342 is_pf
= !(vport
->vport_id
);
1343 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1352 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1354 struct hclge_vport
*vport
= hdev
->vport
;
1357 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1358 for (i
= 0; i
< num_vport
; i
++) {
1361 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1371 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1373 /* this would be initialized later */
1376 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1378 struct hnae3_handle
*nic
= &vport
->nic
;
1379 struct hclge_dev
*hdev
= vport
->back
;
1382 nic
->pdev
= hdev
->pdev
;
1383 nic
->ae_algo
= &ae_algo
;
1384 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1386 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1387 ret
= hclge_knic_setup(vport
, num_tqps
);
1389 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1394 hclge_unic_setup(vport
, num_tqps
);
1400 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1402 struct pci_dev
*pdev
= hdev
->pdev
;
1403 struct hclge_vport
*vport
;
1409 /* We need to alloc a vport for main NIC of PF */
1410 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1412 if (hdev
->num_tqps
< num_vport
) {
1413 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1414 hdev
->num_tqps
, num_vport
);
1418 /* Alloc the same number of TQPs for every vport */
1419 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1420 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1422 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1427 hdev
->vport
= vport
;
1428 hdev
->num_alloc_vport
= num_vport
;
1430 if (IS_ENABLED(CONFIG_PCI_IOV
))
1431 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1433 for (i
= 0; i
< num_vport
; i
++) {
1435 vport
->vport_id
= i
;
1438 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1440 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1443 "vport setup failed for vport %d, %d\n",
1454 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1455 struct hclge_pkt_buf_alloc
*buf_alloc
)
1457 /* TX buffer size is unit by 128 byte */
1458 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1459 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1460 struct hclge_tx_buff_alloc_cmd
*req
;
1461 struct hclge_desc desc
;
1465 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1467 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1468 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1469 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1471 req
->tx_pkt_buff
[i
] =
1472 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1473 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1476 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1478 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1484 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1485 struct hclge_pkt_buf_alloc
*buf_alloc
)
1487 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1490 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc failed %d\n", ret
);
1495 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1499 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1500 if (hdev
->hw_tc_map
& BIT(i
))
1505 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1509 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1510 if (hdev
->hw_tc_map
& BIT(i
) &&
1511 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1516 /* Get the number of pfc enabled TCs, which have private buffer */
1517 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1518 struct hclge_pkt_buf_alloc
*buf_alloc
)
1520 struct hclge_priv_buf
*priv
;
1523 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1524 priv
= &buf_alloc
->priv_buf
[i
];
1525 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1533 /* Get the number of pfc disabled TCs, which have private buffer */
1534 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1535 struct hclge_pkt_buf_alloc
*buf_alloc
)
1537 struct hclge_priv_buf
*priv
;
1540 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1541 priv
= &buf_alloc
->priv_buf
[i
];
1542 if (hdev
->hw_tc_map
& BIT(i
) &&
1543 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1551 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1553 struct hclge_priv_buf
*priv
;
1557 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1558 priv
= &buf_alloc
->priv_buf
[i
];
1560 rx_priv
+= priv
->buf_size
;
1565 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1567 u32 i
, total_tx_size
= 0;
1569 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1570 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1572 return total_tx_size
;
1575 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1576 struct hclge_pkt_buf_alloc
*buf_alloc
,
1579 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1580 int tc_num
, pfc_enable_num
;
1585 tc_num
= hclge_get_tc_num(hdev
);
1586 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1588 if (hnae3_dev_dcb_supported(hdev
))
1589 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1591 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1593 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1594 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1596 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1598 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1599 if (rx_all
<= rx_priv
+ shared_std
)
1602 shared_buf
= rx_all
- rx_priv
;
1603 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1604 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1605 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1607 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1608 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1609 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1610 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1611 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1613 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1614 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1621 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1622 struct hclge_pkt_buf_alloc
*buf_alloc
)
1626 total_size
= hdev
->pkt_buf_size
;
1628 /* alloc tx buffer for all enabled tc */
1629 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1630 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1632 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1635 if (hdev
->hw_tc_map
& BIT(i
))
1636 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1638 priv
->tx_buf_size
= 0;
1640 total_size
-= priv
->tx_buf_size
;
1646 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1647 * @hdev: pointer to struct hclge_dev
1648 * @buf_alloc: pointer to buffer calculation data
1649 * @return: 0: calculate sucessful, negative: fail
1651 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1652 struct hclge_pkt_buf_alloc
*buf_alloc
)
1654 u32 rx_all
= hdev
->pkt_buf_size
;
1655 int no_pfc_priv_num
, pfc_priv_num
;
1656 struct hclge_priv_buf
*priv
;
1659 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1661 /* When DCB is not supported, rx private
1662 * buffer is not allocated.
1664 if (!hnae3_dev_dcb_supported(hdev
)) {
1665 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1671 /* step 1, try to alloc private buffer for all enabled tc */
1672 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1673 priv
= &buf_alloc
->priv_buf
[i
];
1674 if (hdev
->hw_tc_map
& BIT(i
)) {
1676 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1677 priv
->wl
.low
= hdev
->mps
;
1678 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1679 priv
->buf_size
= priv
->wl
.high
+
1683 priv
->wl
.high
= 2 * hdev
->mps
;
1684 priv
->buf_size
= priv
->wl
.high
;
1694 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1697 /* step 2, try to decrease the buffer size of
1698 * no pfc TC's private buffer
1700 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1701 priv
= &buf_alloc
->priv_buf
[i
];
1708 if (!(hdev
->hw_tc_map
& BIT(i
)))
1713 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1715 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1716 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1719 priv
->wl
.high
= hdev
->mps
;
1720 priv
->buf_size
= priv
->wl
.high
;
1724 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1727 /* step 3, try to reduce the number of pfc disabled TCs,
1728 * which have private buffer
1730 /* get the total no pfc enable TC number, which have private buffer */
1731 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1733 /* let the last to be cleared first */
1734 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1735 priv
= &buf_alloc
->priv_buf
[i
];
1737 if (hdev
->hw_tc_map
& BIT(i
) &&
1738 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1739 /* Clear the no pfc TC private buffer */
1747 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1748 no_pfc_priv_num
== 0)
1752 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1755 /* step 4, try to reduce the number of pfc enabled TCs
1756 * which have private buffer.
1758 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1760 /* let the last to be cleared first */
1761 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1762 priv
= &buf_alloc
->priv_buf
[i
];
1764 if (hdev
->hw_tc_map
& BIT(i
) &&
1765 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1766 /* Reduce the number of pfc TC with private buffer */
1774 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1778 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1784 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1785 struct hclge_pkt_buf_alloc
*buf_alloc
)
1787 struct hclge_rx_priv_buff_cmd
*req
;
1788 struct hclge_desc desc
;
1792 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1793 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1795 /* Alloc private buffer TCs */
1796 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1797 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1800 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1802 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1806 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1807 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1809 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1811 dev_err(&hdev
->pdev
->dev
,
1812 "rx private buffer alloc cmd failed %d\n", ret
);
1817 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1818 struct hclge_pkt_buf_alloc
*buf_alloc
)
1820 struct hclge_rx_priv_wl_buf
*req
;
1821 struct hclge_priv_buf
*priv
;
1822 struct hclge_desc desc
[2];
1826 for (i
= 0; i
< 2; i
++) {
1827 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1829 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1831 /* The first descriptor set the NEXT bit to 1 */
1833 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1835 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1837 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1838 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1840 priv
= &buf_alloc
->priv_buf
[idx
];
1841 req
->tc_wl
[j
].high
=
1842 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1843 req
->tc_wl
[j
].high
|=
1844 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1846 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1847 req
->tc_wl
[j
].low
|=
1848 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1852 /* Send 2 descriptor at one time */
1853 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1855 dev_err(&hdev
->pdev
->dev
,
1856 "rx private waterline config cmd failed %d\n",
1861 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1862 struct hclge_pkt_buf_alloc
*buf_alloc
)
1864 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1865 struct hclge_rx_com_thrd
*req
;
1866 struct hclge_desc desc
[2];
1867 struct hclge_tc_thrd
*tc
;
1871 for (i
= 0; i
< 2; i
++) {
1872 hclge_cmd_setup_basic_desc(&desc
[i
],
1873 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1874 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1876 /* The first descriptor set the NEXT bit to 1 */
1878 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1880 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1882 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1883 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1885 req
->com_thrd
[j
].high
=
1886 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1887 req
->com_thrd
[j
].high
|=
1888 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1889 req
->com_thrd
[j
].low
=
1890 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1891 req
->com_thrd
[j
].low
|=
1892 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1896 /* Send 2 descriptors at one time */
1897 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1899 dev_err(&hdev
->pdev
->dev
,
1900 "common threshold config cmd failed %d\n", ret
);
1904 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1905 struct hclge_pkt_buf_alloc
*buf_alloc
)
1907 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1908 struct hclge_rx_com_wl
*req
;
1909 struct hclge_desc desc
;
1912 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1914 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1915 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1916 req
->com_wl
.high
|= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1918 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1919 req
->com_wl
.low
|= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1921 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1923 dev_err(&hdev
->pdev
->dev
,
1924 "common waterline config cmd failed %d\n", ret
);
1928 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1930 struct hclge_pkt_buf_alloc
*pkt_buf
;
1933 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1937 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1939 dev_err(&hdev
->pdev
->dev
,
1940 "could not calc tx buffer size for all TCs %d\n", ret
);
1944 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1946 dev_err(&hdev
->pdev
->dev
,
1947 "could not alloc tx buffers %d\n", ret
);
1951 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1953 dev_err(&hdev
->pdev
->dev
,
1954 "could not calc rx priv buffer size for all TCs %d\n",
1959 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1961 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1966 if (hnae3_dev_dcb_supported(hdev
)) {
1967 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1969 dev_err(&hdev
->pdev
->dev
,
1970 "could not configure rx private waterline %d\n",
1975 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
1977 dev_err(&hdev
->pdev
->dev
,
1978 "could not configure common threshold %d\n",
1984 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
1986 dev_err(&hdev
->pdev
->dev
,
1987 "could not configure common waterline %d\n", ret
);
1994 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
1996 struct hnae3_handle
*roce
= &vport
->roce
;
1997 struct hnae3_handle
*nic
= &vport
->nic
;
1999 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2001 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2002 vport
->back
->num_msi_left
== 0)
2005 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2007 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2008 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2010 roce
->pdev
= nic
->pdev
;
2011 roce
->ae_algo
= nic
->ae_algo
;
2012 roce
->numa_node_mask
= nic
->numa_node_mask
;
2017 static int hclge_init_msi(struct hclge_dev
*hdev
)
2019 struct pci_dev
*pdev
= hdev
->pdev
;
2023 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2024 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2027 "failed(%d) to allocate MSI/MSI-X vectors\n",
2031 if (vectors
< hdev
->num_msi
)
2032 dev_warn(&hdev
->pdev
->dev
,
2033 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2034 hdev
->num_msi
, vectors
);
2036 hdev
->num_msi
= vectors
;
2037 hdev
->num_msi_left
= vectors
;
2038 hdev
->base_msi_vector
= pdev
->irq
;
2039 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2040 HCLGE_ROCE_VECTOR_OFFSET
;
2042 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2043 sizeof(u16
), GFP_KERNEL
);
2044 if (!hdev
->vector_status
) {
2045 pci_free_irq_vectors(pdev
);
2049 for (i
= 0; i
< hdev
->num_msi
; i
++)
2050 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2052 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2053 sizeof(int), GFP_KERNEL
);
2054 if (!hdev
->vector_irq
) {
2055 pci_free_irq_vectors(pdev
);
2062 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2064 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2066 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2067 mac
->duplex
= (u8
)duplex
;
2069 mac
->duplex
= HCLGE_MAC_FULL
;
2074 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2076 struct hclge_config_mac_speed_dup_cmd
*req
;
2077 struct hclge_desc desc
;
2080 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2082 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2084 hnae3_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2087 case HCLGE_MAC_SPEED_10M
:
2088 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2089 HCLGE_CFG_SPEED_S
, 6);
2091 case HCLGE_MAC_SPEED_100M
:
2092 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2093 HCLGE_CFG_SPEED_S
, 7);
2095 case HCLGE_MAC_SPEED_1G
:
2096 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2097 HCLGE_CFG_SPEED_S
, 0);
2099 case HCLGE_MAC_SPEED_10G
:
2100 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2101 HCLGE_CFG_SPEED_S
, 1);
2103 case HCLGE_MAC_SPEED_25G
:
2104 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2105 HCLGE_CFG_SPEED_S
, 2);
2107 case HCLGE_MAC_SPEED_40G
:
2108 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2109 HCLGE_CFG_SPEED_S
, 3);
2111 case HCLGE_MAC_SPEED_50G
:
2112 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2113 HCLGE_CFG_SPEED_S
, 4);
2115 case HCLGE_MAC_SPEED_100G
:
2116 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2117 HCLGE_CFG_SPEED_S
, 5);
2120 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2124 hnae3_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2127 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2129 dev_err(&hdev
->pdev
->dev
,
2130 "mac speed/duplex config cmd failed %d.\n", ret
);
2134 hclge_check_speed_dup(hdev
, duplex
, speed
);
2139 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2142 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2143 struct hclge_dev
*hdev
= vport
->back
;
2145 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2148 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2151 struct hclge_query_an_speed_dup_cmd
*req
;
2152 struct hclge_desc desc
;
2156 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2158 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2159 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2161 dev_err(&hdev
->pdev
->dev
,
2162 "mac speed/autoneg/duplex query cmd failed %d\n",
2167 *duplex
= hnae3_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2168 speed_tmp
= hnae3_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2169 HCLGE_QUERY_SPEED_S
);
2171 ret
= hclge_parse_speed(speed_tmp
, speed
);
2173 dev_err(&hdev
->pdev
->dev
,
2174 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2179 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2181 struct hclge_config_auto_neg_cmd
*req
;
2182 struct hclge_desc desc
;
2186 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2188 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2189 hnae3_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2190 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2192 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2194 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2200 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2202 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2203 struct hclge_dev
*hdev
= vport
->back
;
2205 return hclge_set_autoneg_en(hdev
, enable
);
2208 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2210 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2211 struct hclge_dev
*hdev
= vport
->back
;
2212 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2215 return phydev
->autoneg
;
2217 return hdev
->hw
.mac
.autoneg
;
2220 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2224 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2225 struct hclge_desc desc
;
2228 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2229 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2231 hnae3_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2233 ether_addr_copy(req
->mac_mask
, mac_mask
);
2235 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2237 dev_err(&hdev
->pdev
->dev
,
2238 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2244 static int hclge_mac_init(struct hclge_dev
*hdev
)
2246 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2247 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2248 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2249 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2250 struct hclge_vport
*vport
;
2255 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2257 dev_err(&hdev
->pdev
->dev
,
2258 "Config mac speed dup fail ret=%d\n", ret
);
2264 /* Initialize the MTA table work mode */
2265 hdev
->enable_mta
= true;
2266 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2268 ret
= hclge_set_mta_filter_mode(hdev
,
2269 hdev
->mta_mac_sel_type
,
2272 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2277 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
2278 vport
= &hdev
->vport
[i
];
2279 vport
->accept_mta_mc
= false;
2281 memset(vport
->mta_shadow
, 0, sizeof(vport
->mta_shadow
));
2282 ret
= hclge_cfg_func_mta_filter(hdev
, vport
->vport_id
, false);
2284 dev_err(&hdev
->pdev
->dev
,
2285 "set mta filter mode fail ret=%d\n", ret
);
2290 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2292 dev_err(&hdev
->pdev
->dev
,
2293 "set default mac_vlan_mask fail ret=%d\n", ret
);
2302 ret
= hclge_set_mtu(handle
, mtu
);
2304 dev_err(&hdev
->pdev
->dev
,
2305 "set mtu failed ret=%d\n", ret
);
2310 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2312 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2313 schedule_work(&hdev
->mbx_service_task
);
2316 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2318 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2319 schedule_work(&hdev
->rst_service_task
);
2322 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2324 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2325 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2326 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2327 (void)schedule_work(&hdev
->service_task
);
2330 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2332 struct hclge_link_status_cmd
*req
;
2333 struct hclge_desc desc
;
2337 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2338 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2340 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2345 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2346 link_status
= req
->status
& HCLGE_LINK_STATUS_UP_M
;
2348 return !!link_status
;
2351 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2356 mac_state
= hclge_get_mac_link_status(hdev
);
2358 if (hdev
->hw
.mac
.phydev
) {
2359 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2360 link_stat
= mac_state
&
2361 hdev
->hw
.mac
.phydev
->link
;
2366 link_stat
= mac_state
;
2372 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2374 struct hnae3_client
*rclient
= hdev
->roce_client
;
2375 struct hnae3_client
*client
= hdev
->nic_client
;
2376 struct hnae3_handle
*rhandle
;
2377 struct hnae3_handle
*handle
;
2383 state
= hclge_get_mac_phy_link(hdev
);
2384 if (state
!= hdev
->hw
.mac
.link
) {
2385 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2386 handle
= &hdev
->vport
[i
].nic
;
2387 client
->ops
->link_status_change(handle
, state
);
2388 rhandle
= &hdev
->vport
[i
].roce
;
2389 if (rclient
&& rclient
->ops
->link_status_change
)
2390 rclient
->ops
->link_status_change(rhandle
,
2393 hdev
->hw
.mac
.link
= state
;
2397 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2399 struct hclge_mac mac
= hdev
->hw
.mac
;
2404 /* get the speed and duplex as autoneg'result from mac cmd when phy
2407 if (mac
.phydev
|| !mac
.autoneg
)
2410 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2412 dev_err(&hdev
->pdev
->dev
,
2413 "mac autoneg/speed/duplex query failed %d\n", ret
);
2417 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2418 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2420 dev_err(&hdev
->pdev
->dev
,
2421 "mac speed/duplex config failed %d\n", ret
);
2429 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2431 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2432 struct hclge_dev
*hdev
= vport
->back
;
2434 return hclge_update_speed_duplex(hdev
);
2437 static int hclge_get_status(struct hnae3_handle
*handle
)
2439 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2440 struct hclge_dev
*hdev
= vport
->back
;
2442 hclge_update_link_status(hdev
);
2444 return hdev
->hw
.mac
.link
;
2447 static void hclge_service_timer(struct timer_list
*t
)
2449 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2451 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2452 hdev
->hw_stats
.stats_timer
++;
2453 hclge_task_schedule(hdev
);
2456 static void hclge_service_complete(struct hclge_dev
*hdev
)
2458 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2460 /* Flush memory before next watchdog */
2461 smp_mb__before_atomic();
2462 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2465 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2470 /* fetch the events from their corresponding regs */
2471 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_VECTOR_INT_STS
);
2472 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2474 /* Assumption: If by any chance reset and mailbox events are reported
2475 * together then we will only process reset event in this go and will
2476 * defer the processing of the mailbox events. Since, we would have not
2477 * cleared RX CMDQ event this time we would receive again another
2478 * interrupt from H/W just for the mailbox.
2481 /* check for vector0 reset event sources */
2482 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2483 set_bit(HCLGE_STATE_CMD_DISABLE
, &hdev
->state
);
2484 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2485 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2486 return HCLGE_VECTOR0_EVENT_RST
;
2489 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2490 set_bit(HCLGE_STATE_CMD_DISABLE
, &hdev
->state
);
2491 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2492 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2493 return HCLGE_VECTOR0_EVENT_RST
;
2496 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2497 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2498 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2499 return HCLGE_VECTOR0_EVENT_RST
;
2502 /* check for vector0 mailbox(=CMDQ RX) event source */
2503 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2504 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2505 *clearval
= cmdq_src_reg
;
2506 return HCLGE_VECTOR0_EVENT_MBX
;
2509 return HCLGE_VECTOR0_EVENT_OTHER
;
2512 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2515 switch (event_type
) {
2516 case HCLGE_VECTOR0_EVENT_RST
:
2517 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2519 case HCLGE_VECTOR0_EVENT_MBX
:
2520 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2525 static void hclge_clear_all_event_cause(struct hclge_dev
*hdev
)
2527 hclge_clear_event_cause(hdev
, HCLGE_VECTOR0_EVENT_RST
,
2528 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) |
2529 BIT(HCLGE_VECTOR0_CORERESET_INT_B
) |
2530 BIT(HCLGE_VECTOR0_IMPRESET_INT_B
));
2531 hclge_clear_event_cause(hdev
, HCLGE_VECTOR0_EVENT_MBX
, 0);
2534 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2536 writel(enable
? 1 : 0, vector
->addr
);
2539 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2541 struct hclge_dev
*hdev
= data
;
2545 hclge_enable_vector(&hdev
->misc_vector
, false);
2546 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2548 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2549 switch (event_cause
) {
2550 case HCLGE_VECTOR0_EVENT_RST
:
2551 hclge_reset_task_schedule(hdev
);
2553 case HCLGE_VECTOR0_EVENT_MBX
:
2554 /* If we are here then,
2555 * 1. Either we are not handling any mbx task and we are not
2558 * 2. We could be handling a mbx task but nothing more is
2560 * In both cases, we should schedule mbx task as there are more
2561 * mbx messages reported by this interrupt.
2563 hclge_mbx_task_schedule(hdev
);
2566 dev_warn(&hdev
->pdev
->dev
,
2567 "received unknown or unhandled event of vector0\n");
2571 /* clear the source of interrupt if it is not cause by reset */
2572 if (event_cause
!= HCLGE_VECTOR0_EVENT_RST
) {
2573 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2574 hclge_enable_vector(&hdev
->misc_vector
, true);
2580 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2582 if (hdev
->vector_status
[vector_id
] == HCLGE_INVALID_VPORT
) {
2583 dev_warn(&hdev
->pdev
->dev
,
2584 "vector(vector_id %d) has been freed.\n", vector_id
);
2588 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2589 hdev
->num_msi_left
+= 1;
2590 hdev
->num_msi_used
-= 1;
2593 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2595 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2597 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2599 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2600 hdev
->vector_status
[0] = 0;
2602 hdev
->num_msi_left
-= 1;
2603 hdev
->num_msi_used
+= 1;
2606 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2610 hclge_get_misc_vector(hdev
);
2612 /* this would be explicitly freed in the end */
2613 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2614 0, "hclge_misc", hdev
);
2616 hclge_free_vector(hdev
, 0);
2617 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2618 hdev
->misc_vector
.vector_irq
);
2624 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2626 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2627 hclge_free_vector(hdev
, 0);
2630 static int hclge_notify_client(struct hclge_dev
*hdev
,
2631 enum hnae3_reset_notify_type type
)
2633 struct hnae3_client
*client
= hdev
->nic_client
;
2634 struct hnae3_handle
*handle
;
2638 if (!client
->ops
->reset_notify
)
2641 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2642 handle
= &hdev
->vport
[i
].nic
;
2643 ret
= client
->ops
->reset_notify(handle
, type
);
2645 dev_err(&hdev
->pdev
->dev
,
2646 "notify nic client failed %d", ret
);
2654 static int hclge_notify_roce_client(struct hclge_dev
*hdev
,
2655 enum hnae3_reset_notify_type type
)
2657 struct hnae3_client
*client
= hdev
->roce_client
;
2658 struct hnae3_handle
*handle
;
2665 if (!client
->ops
->reset_notify
)
2668 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2669 handle
= &hdev
->vport
[i
].roce
;
2670 ret
= client
->ops
->reset_notify(handle
, type
);
2672 dev_err(&hdev
->pdev
->dev
,
2673 "notify roce client failed %d", ret
);
2681 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2683 #define HCLGE_RESET_WATI_MS 100
2684 #define HCLGE_RESET_WAIT_CNT 5
2685 u32 val
, reg
, reg_bit
;
2688 switch (hdev
->reset_type
) {
2689 case HNAE3_GLOBAL_RESET
:
2690 reg
= HCLGE_GLOBAL_RESET_REG
;
2691 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2693 case HNAE3_CORE_RESET
:
2694 reg
= HCLGE_GLOBAL_RESET_REG
;
2695 reg_bit
= HCLGE_CORE_RESET_BIT
;
2697 case HNAE3_FUNC_RESET
:
2698 reg
= HCLGE_FUN_RST_ING
;
2699 reg_bit
= HCLGE_FUN_RST_ING_B
;
2702 dev_err(&hdev
->pdev
->dev
,
2703 "Wait for unsupported reset type: %d\n",
2708 val
= hclge_read_dev(&hdev
->hw
, reg
);
2709 while (hnae3_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
&&
2710 test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
2711 msleep(HCLGE_RESET_WATI_MS
);
2712 val
= hclge_read_dev(&hdev
->hw
, reg
);
2716 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2717 dev_warn(&hdev
->pdev
->dev
,
2718 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2725 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2727 struct hclge_desc desc
;
2728 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2731 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2732 hnae3_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2733 req
->fun_reset_vfid
= func_id
;
2735 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2737 dev_err(&hdev
->pdev
->dev
,
2738 "send function reset cmd fail, status =%d\n", ret
);
2743 static void hclge_do_reset(struct hclge_dev
*hdev
)
2745 struct pci_dev
*pdev
= hdev
->pdev
;
2748 switch (hdev
->reset_type
) {
2749 case HNAE3_GLOBAL_RESET
:
2750 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2751 hnae3_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2752 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2753 dev_info(&pdev
->dev
, "Global Reset requested\n");
2755 case HNAE3_CORE_RESET
:
2756 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2757 hnae3_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2758 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2759 dev_info(&pdev
->dev
, "Core Reset requested\n");
2761 case HNAE3_FUNC_RESET
:
2762 dev_info(&pdev
->dev
, "PF Reset requested\n");
2763 hclge_func_reset_cmd(hdev
, 0);
2764 /* schedule again to check later */
2765 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2766 hclge_reset_task_schedule(hdev
);
2769 dev_warn(&pdev
->dev
,
2770 "Unsupported reset type: %d\n", hdev
->reset_type
);
2775 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2776 unsigned long *addr
)
2778 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2780 /* return the highest priority reset level amongst all */
2781 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2782 rst_level
= HNAE3_GLOBAL_RESET
;
2783 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2784 rst_level
= HNAE3_CORE_RESET
;
2785 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2786 rst_level
= HNAE3_IMP_RESET
;
2787 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2788 rst_level
= HNAE3_FUNC_RESET
;
2790 /* now, clear all other resets */
2791 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2792 clear_bit(HNAE3_CORE_RESET
, addr
);
2793 clear_bit(HNAE3_IMP_RESET
, addr
);
2794 clear_bit(HNAE3_FUNC_RESET
, addr
);
2799 static void hclge_clear_reset_cause(struct hclge_dev
*hdev
)
2803 switch (hdev
->reset_type
) {
2804 case HNAE3_IMP_RESET
:
2805 clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2807 case HNAE3_GLOBAL_RESET
:
2808 clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2810 case HNAE3_CORE_RESET
:
2811 clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2820 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, clearval
);
2821 hclge_enable_vector(&hdev
->misc_vector
, true);
2824 static void hclge_reset(struct hclge_dev
*hdev
)
2826 struct hnae3_handle
*handle
;
2828 /* perform reset of the stack & ae device for a client */
2829 handle
= &hdev
->vport
[0].nic
;
2831 hclge_notify_roce_client(hdev
, HNAE3_DOWN_CLIENT
);
2832 hclge_notify_roce_client(hdev
, HNAE3_UNINIT_CLIENT
);
2835 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2837 if (!hclge_reset_wait(hdev
)) {
2838 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2839 hclge_reset_ae_dev(hdev
->ae_dev
);
2840 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2842 hclge_clear_reset_cause(hdev
);
2844 /* schedule again to check pending resets later */
2845 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2846 hclge_reset_task_schedule(hdev
);
2849 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2850 handle
->last_reset_time
= jiffies
;
2853 hclge_notify_roce_client(hdev
, HNAE3_INIT_CLIENT
);
2854 hclge_notify_roce_client(hdev
, HNAE3_UP_CLIENT
);
2857 static void hclge_reset_event(struct hnae3_handle
*handle
)
2859 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2860 struct hclge_dev
*hdev
= vport
->back
;
2862 /* check if this is a new reset request and we are not here just because
2863 * last reset attempt did not succeed and watchdog hit us again. We will
2864 * know this if last reset request did not occur very recently (watchdog
2865 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2866 * In case of new request we reset the "reset level" to PF reset.
2867 * And if it is a repeat reset request of the most recent one then we
2868 * want to make sure we throttle the reset request. Therefore, we will
2869 * not allow it again before 3*HZ times.
2871 if (time_before(jiffies
, (handle
->last_reset_time
+ 3 * HZ
)))
2873 else if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2874 handle
->reset_level
= HNAE3_FUNC_RESET
;
2876 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2877 handle
->reset_level
);
2879 /* request reset & schedule reset task */
2880 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2881 hclge_reset_task_schedule(hdev
);
2883 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2884 handle
->reset_level
++;
2887 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2889 /* check if there is any ongoing reset in the hardware. This status can
2890 * be checked from reset_pending. If there is then, we need to wait for
2891 * hardware to complete reset.
2892 * a. If we are able to figure out in reasonable time that hardware
2893 * has fully resetted then, we can proceed with driver, client
2895 * b. else, we can come back later to check this status so re-sched
2898 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2899 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2902 /* check if we got any *new* reset requests to be honored */
2903 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2904 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2905 hclge_do_reset(hdev
);
2907 hdev
->reset_type
= HNAE3_NONE_RESET
;
2910 static void hclge_reset_service_task(struct work_struct
*work
)
2912 struct hclge_dev
*hdev
=
2913 container_of(work
, struct hclge_dev
, rst_service_task
);
2915 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2918 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2920 hclge_reset_subtask(hdev
);
2922 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2925 static void hclge_mailbox_service_task(struct work_struct
*work
)
2927 struct hclge_dev
*hdev
=
2928 container_of(work
, struct hclge_dev
, mbx_service_task
);
2930 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2933 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2935 hclge_mbx_handler(hdev
);
2937 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2940 static void hclge_service_task(struct work_struct
*work
)
2942 struct hclge_dev
*hdev
=
2943 container_of(work
, struct hclge_dev
, service_task
);
2945 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2946 hclge_update_stats_for_all(hdev
);
2947 hdev
->hw_stats
.stats_timer
= 0;
2950 hclge_update_speed_duplex(hdev
);
2951 hclge_update_link_status(hdev
);
2952 hclge_service_complete(hdev
);
2955 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2957 /* VF handle has no client */
2958 if (!handle
->client
)
2959 return container_of(handle
, struct hclge_vport
, nic
);
2960 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2961 return container_of(handle
, struct hclge_vport
, roce
);
2963 return container_of(handle
, struct hclge_vport
, nic
);
2966 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2967 struct hnae3_vector_info
*vector_info
)
2969 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2970 struct hnae3_vector_info
*vector
= vector_info
;
2971 struct hclge_dev
*hdev
= vport
->back
;
2975 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2977 for (j
= 0; j
< vector_num
; j
++) {
2978 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2979 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2980 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2981 vector
->io_addr
= hdev
->hw
.io_base
+
2982 HCLGE_VECTOR_REG_BASE
+
2983 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2985 HCLGE_VECTOR_VF_OFFSET
;
2986 hdev
->vector_status
[i
] = vport
->vport_id
;
2987 hdev
->vector_irq
[i
] = vector
->vector
;
2996 hdev
->num_msi_left
-= alloc
;
2997 hdev
->num_msi_used
+= alloc
;
3002 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
3006 for (i
= 0; i
< hdev
->num_msi
; i
++)
3007 if (vector
== hdev
->vector_irq
[i
])
3013 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
3015 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3016 struct hclge_dev
*hdev
= vport
->back
;
3019 vector_id
= hclge_get_vector_index(hdev
, vector
);
3020 if (vector_id
< 0) {
3021 dev_err(&hdev
->pdev
->dev
,
3022 "Get vector index fail. vector_id =%d\n", vector_id
);
3026 hclge_free_vector(hdev
, vector_id
);
3031 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
3033 return HCLGE_RSS_KEY_SIZE
;
3036 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
3038 return HCLGE_RSS_IND_TBL_SIZE
;
3041 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3042 const u8 hfunc
, const u8
*key
)
3044 struct hclge_rss_config_cmd
*req
;
3045 struct hclge_desc desc
;
3050 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3052 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3053 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3056 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3057 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3059 if (key_offset
== 2)
3061 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3063 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3065 memcpy(req
->hash_key
,
3066 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3068 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3070 dev_err(&hdev
->pdev
->dev
,
3071 "Configure RSS config fail, status = %d\n",
3079 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3081 struct hclge_rss_indirection_table_cmd
*req
;
3082 struct hclge_desc desc
;
3086 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3088 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3089 hclge_cmd_setup_basic_desc
3090 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3092 req
->start_table_index
=
3093 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3094 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3096 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3097 req
->rss_result
[j
] =
3098 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3100 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3102 dev_err(&hdev
->pdev
->dev
,
3103 "Configure rss indir table fail,status = %d\n",
3111 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3112 u16
*tc_size
, u16
*tc_offset
)
3114 struct hclge_rss_tc_mode_cmd
*req
;
3115 struct hclge_desc desc
;
3119 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3120 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3122 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3125 hnae3_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3126 hnae3_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3127 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3128 hnae3_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3129 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3131 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3134 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3136 dev_err(&hdev
->pdev
->dev
,
3137 "Configure rss tc mode fail, status = %d\n", ret
);
3142 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3144 struct hclge_rss_input_tuple_cmd
*req
;
3145 struct hclge_desc desc
;
3148 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3150 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3152 /* Get the tuple cfg from pf */
3153 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3154 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3155 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3156 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3157 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3158 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3159 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3160 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3161 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3163 dev_err(&hdev
->pdev
->dev
,
3164 "Configure rss input fail, status = %d\n", ret
);
3168 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3171 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3174 /* Get hash algorithm */
3176 *hfunc
= vport
->rss_algo
;
3178 /* Get the RSS Key required by the user */
3180 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3182 /* Get indirect table */
3184 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3185 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3190 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3191 const u8
*key
, const u8 hfunc
)
3193 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3194 struct hclge_dev
*hdev
= vport
->back
;
3198 /* Set the RSS Hash Key if specififed by the user */
3201 if (hfunc
== ETH_RSS_HASH_TOP
||
3202 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3203 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3206 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3210 /* Update the shadow RSS key with user specified qids */
3211 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3212 vport
->rss_algo
= hash_algo
;
3215 /* Update the shadow RSS table with user specified qids */
3216 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3217 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3219 /* Update the hardware */
3220 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3223 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3225 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3227 if (nfc
->data
& RXH_L4_B_2_3
)
3228 hash_sets
|= HCLGE_D_PORT_BIT
;
3230 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3232 if (nfc
->data
& RXH_IP_SRC
)
3233 hash_sets
|= HCLGE_S_IP_BIT
;
3235 hash_sets
&= ~HCLGE_S_IP_BIT
;
3237 if (nfc
->data
& RXH_IP_DST
)
3238 hash_sets
|= HCLGE_D_IP_BIT
;
3240 hash_sets
&= ~HCLGE_D_IP_BIT
;
3242 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3243 hash_sets
|= HCLGE_V_TAG_BIT
;
3248 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3249 struct ethtool_rxnfc
*nfc
)
3251 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3252 struct hclge_dev
*hdev
= vport
->back
;
3253 struct hclge_rss_input_tuple_cmd
*req
;
3254 struct hclge_desc desc
;
3258 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3259 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3262 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3263 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3265 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3266 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3267 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3268 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3269 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3270 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3271 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3272 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3274 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3275 switch (nfc
->flow_type
) {
3277 req
->ipv4_tcp_en
= tuple_sets
;
3280 req
->ipv6_tcp_en
= tuple_sets
;
3283 req
->ipv4_udp_en
= tuple_sets
;
3286 req
->ipv6_udp_en
= tuple_sets
;
3289 req
->ipv4_sctp_en
= tuple_sets
;
3292 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3293 (nfc
->data
& RXH_L4_B_2_3
))
3296 req
->ipv6_sctp_en
= tuple_sets
;
3299 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3302 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3308 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3310 dev_err(&hdev
->pdev
->dev
,
3311 "Set rss tuple fail, status = %d\n", ret
);
3315 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3316 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3317 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3318 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3319 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3320 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3321 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3322 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3326 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3327 struct ethtool_rxnfc
*nfc
)
3329 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3334 switch (nfc
->flow_type
) {
3336 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3339 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3342 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3345 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3348 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3351 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3355 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3364 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3365 nfc
->data
|= RXH_L4_B_2_3
;
3366 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3367 nfc
->data
|= RXH_L4_B_0_1
;
3368 if (tuple_sets
& HCLGE_D_IP_BIT
)
3369 nfc
->data
|= RXH_IP_DST
;
3370 if (tuple_sets
& HCLGE_S_IP_BIT
)
3371 nfc
->data
|= RXH_IP_SRC
;
3376 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3378 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3379 struct hclge_dev
*hdev
= vport
->back
;
3381 return hdev
->rss_size_max
;
3384 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3386 struct hclge_vport
*vport
= hdev
->vport
;
3387 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3388 u16 rss_size
= vport
[0].alloc_rss_size
;
3389 u8
*key
= vport
[0].rss_hash_key
;
3390 u8 hfunc
= vport
[0].rss_algo
;
3391 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3392 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3393 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3397 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3401 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3405 ret
= hclge_set_rss_input_tuple(hdev
);
3409 /* Each TC have the same queue size, and tc_size set to hardware is
3410 * the log2 of roundup power of two of rss_size, the acutal queue
3411 * size is limited by indirection table.
3413 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3414 dev_err(&hdev
->pdev
->dev
,
3415 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3420 roundup_size
= roundup_pow_of_two(rss_size
);
3421 roundup_size
= ilog2(roundup_size
);
3423 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3426 if (!(hdev
->hw_tc_map
& BIT(i
)))
3430 tc_size
[i
] = roundup_size
;
3431 tc_offset
[i
] = rss_size
* i
;
3434 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3437 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3439 struct hclge_vport
*vport
= hdev
->vport
;
3442 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3443 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3444 vport
[j
].rss_indirection_tbl
[i
] =
3445 i
% vport
[j
].alloc_rss_size
;
3449 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3451 struct hclge_vport
*vport
= hdev
->vport
;
3454 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3455 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3456 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3457 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3458 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3459 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3460 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3461 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3462 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3463 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3464 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3465 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3466 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3467 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3468 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3469 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3470 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3472 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3474 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3477 hclge_rss_indir_init_cfg(hdev
);
3480 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3481 int vector_id
, bool en
,
3482 struct hnae3_ring_chain_node
*ring_chain
)
3484 struct hclge_dev
*hdev
= vport
->back
;
3485 struct hnae3_ring_chain_node
*node
;
3486 struct hclge_desc desc
;
3487 struct hclge_ctrl_vector_chain_cmd
*req
3488 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3489 enum hclge_cmd_status status
;
3490 enum hclge_opcode_type op
;
3491 u16 tqp_type_and_id
;
3494 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3495 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3496 req
->int_vector_id
= vector_id
;
3499 for (node
= ring_chain
; node
; node
= node
->next
) {
3500 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3501 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3503 hnae3_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3504 hnae3_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3505 HCLGE_TQP_ID_S
, node
->tqp_index
);
3506 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3508 hnae3_get_field(node
->int_gl_idx
,
3509 HNAE3_RING_GL_IDX_M
,
3510 HNAE3_RING_GL_IDX_S
));
3511 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3512 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3513 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3514 req
->vfid
= vport
->vport_id
;
3516 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3518 dev_err(&hdev
->pdev
->dev
,
3519 "Map TQP fail, status is %d.\n",
3525 hclge_cmd_setup_basic_desc(&desc
,
3528 req
->int_vector_id
= vector_id
;
3533 req
->int_cause_num
= i
;
3534 req
->vfid
= vport
->vport_id
;
3535 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3537 dev_err(&hdev
->pdev
->dev
,
3538 "Map TQP fail, status is %d.\n", status
);
3546 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3548 struct hnae3_ring_chain_node
*ring_chain
)
3550 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3551 struct hclge_dev
*hdev
= vport
->back
;
3554 vector_id
= hclge_get_vector_index(hdev
, vector
);
3555 if (vector_id
< 0) {
3556 dev_err(&hdev
->pdev
->dev
,
3557 "Get vector index fail. vector_id =%d\n", vector_id
);
3561 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3564 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3566 struct hnae3_ring_chain_node
*ring_chain
)
3568 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3569 struct hclge_dev
*hdev
= vport
->back
;
3572 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3575 vector_id
= hclge_get_vector_index(hdev
, vector
);
3576 if (vector_id
< 0) {
3577 dev_err(&handle
->pdev
->dev
,
3578 "Get vector index fail. ret =%d\n", vector_id
);
3582 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3584 dev_err(&handle
->pdev
->dev
,
3585 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3592 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3593 struct hclge_promisc_param
*param
)
3595 struct hclge_promisc_cfg_cmd
*req
;
3596 struct hclge_desc desc
;
3599 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3601 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3602 req
->vf_id
= param
->vf_id
;
3604 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3605 * pdev revision(0x20), new revision support them. The
3606 * value of this two fields will not return error when driver
3607 * send command to fireware in revision(0x20).
3609 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
) |
3610 HCLGE_PROMISC_TX_EN_B
| HCLGE_PROMISC_RX_EN_B
;
3612 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3614 dev_err(&hdev
->pdev
->dev
,
3615 "Set promisc mode fail, status is %d.\n", ret
);
3620 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3621 bool en_mc
, bool en_bc
, int vport_id
)
3626 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3628 param
->enable
= HCLGE_PROMISC_EN_UC
;
3630 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3632 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3633 param
->vf_id
= vport_id
;
3636 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, bool en_uc_pmc
,
3639 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3640 struct hclge_dev
*hdev
= vport
->back
;
3641 struct hclge_promisc_param param
;
3643 hclge_promisc_param_init(¶m
, en_uc_pmc
, en_mc_pmc
, true,
3645 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3648 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3650 struct hclge_desc desc
;
3651 struct hclge_config_mac_mode_cmd
*req
=
3652 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3656 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3657 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3658 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3659 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3660 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3661 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3662 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3663 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3664 hnae3_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3665 hnae3_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3666 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3667 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3668 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3669 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3670 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3671 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3673 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3675 dev_err(&hdev
->pdev
->dev
,
3676 "mac enable fail, ret =%d.\n", ret
);
3679 static int hclge_set_mac_loopback(struct hclge_dev
*hdev
, bool en
)
3681 struct hclge_config_mac_mode_cmd
*req
;
3682 struct hclge_desc desc
;
3686 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3687 /* 1 Read out the MAC mode config at first */
3688 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, true);
3689 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3691 dev_err(&hdev
->pdev
->dev
,
3692 "mac loopback get fail, ret =%d.\n", ret
);
3696 /* 2 Then setup the loopback flag */
3697 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3698 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, en
? 1 : 0);
3700 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3702 /* 3 Config mac work mode with loopback flag
3703 * and its original configure parameters
3705 hclge_cmd_reuse_desc(&desc
, false);
3706 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3708 dev_err(&hdev
->pdev
->dev
,
3709 "mac loopback set fail, ret =%d.\n", ret
);
3713 static int hclge_set_serdes_loopback(struct hclge_dev
*hdev
, bool en
)
3715 #define HCLGE_SERDES_RETRY_MS 10
3716 #define HCLGE_SERDES_RETRY_NUM 100
3717 struct hclge_serdes_lb_cmd
*req
;
3718 struct hclge_desc desc
;
3721 req
= (struct hclge_serdes_lb_cmd
*)&desc
.data
[0];
3722 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SERDES_LOOPBACK
, false);
3725 req
->enable
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3726 req
->mask
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3728 req
->mask
= HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
;
3731 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3733 dev_err(&hdev
->pdev
->dev
,
3734 "serdes loopback set fail, ret = %d\n", ret
);
3739 msleep(HCLGE_SERDES_RETRY_MS
);
3740 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SERDES_LOOPBACK
,
3742 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3744 dev_err(&hdev
->pdev
->dev
,
3745 "serdes loopback get, ret = %d\n", ret
);
3748 } while (++i
< HCLGE_SERDES_RETRY_NUM
&&
3749 !(req
->result
& HCLGE_CMD_SERDES_DONE_B
));
3751 if (!(req
->result
& HCLGE_CMD_SERDES_DONE_B
)) {
3752 dev_err(&hdev
->pdev
->dev
, "serdes loopback set timeout\n");
3754 } else if (!(req
->result
& HCLGE_CMD_SERDES_SUCCESS_B
)) {
3755 dev_err(&hdev
->pdev
->dev
, "serdes loopback set failed in fw\n");
3762 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3763 enum hnae3_loop loop_mode
, bool en
)
3765 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3766 struct hclge_dev
*hdev
= vport
->back
;
3769 switch (loop_mode
) {
3770 case HNAE3_MAC_INTER_LOOP_MAC
:
3771 ret
= hclge_set_mac_loopback(hdev
, en
);
3773 case HNAE3_MAC_INTER_LOOP_SERDES
:
3774 ret
= hclge_set_serdes_loopback(hdev
, en
);
3778 dev_err(&hdev
->pdev
->dev
,
3779 "loop_mode %d is not supported\n", loop_mode
);
3786 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3787 int stream_id
, bool enable
)
3789 struct hclge_desc desc
;
3790 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3791 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3794 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3795 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3796 req
->stream_id
= cpu_to_le16(stream_id
);
3797 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3799 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3801 dev_err(&hdev
->pdev
->dev
,
3802 "Tqp enable fail, status =%d.\n", ret
);
3806 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3808 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3809 struct hnae3_queue
*queue
;
3810 struct hclge_tqp
*tqp
;
3813 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3814 queue
= handle
->kinfo
.tqp
[i
];
3815 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3816 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3820 static int hclge_ae_start(struct hnae3_handle
*handle
)
3822 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3823 struct hclge_dev
*hdev
= vport
->back
;
3826 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3827 hclge_tqp_enable(hdev
, i
, 0, true);
3830 hclge_cfg_mac_mode(hdev
, true);
3831 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3832 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3833 hdev
->hw
.mac
.link
= 0;
3835 /* reset tqp stats */
3836 hclge_reset_tqp_stats(handle
);
3838 ret
= hclge_mac_start_phy(hdev
);
3845 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3847 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3848 struct hclge_dev
*hdev
= vport
->back
;
3851 del_timer_sync(&hdev
->service_timer
);
3852 cancel_work_sync(&hdev
->service_task
);
3853 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
3855 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
3856 hclge_mac_stop_phy(hdev
);
3860 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3861 hclge_tqp_enable(hdev
, i
, 0, false);
3864 hclge_cfg_mac_mode(hdev
, false);
3866 hclge_mac_stop_phy(hdev
);
3868 /* reset tqp stats */
3869 hclge_reset_tqp_stats(handle
);
3870 del_timer_sync(&hdev
->service_timer
);
3871 cancel_work_sync(&hdev
->service_task
);
3872 hclge_update_link_status(hdev
);
3875 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3876 u16 cmdq_resp
, u8 resp_code
,
3877 enum hclge_mac_vlan_tbl_opcode op
)
3879 struct hclge_dev
*hdev
= vport
->back
;
3880 int return_status
= -EIO
;
3883 dev_err(&hdev
->pdev
->dev
,
3884 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3889 if (op
== HCLGE_MAC_VLAN_ADD
) {
3890 if ((!resp_code
) || (resp_code
== 1)) {
3892 } else if (resp_code
== 2) {
3893 return_status
= -ENOSPC
;
3894 dev_err(&hdev
->pdev
->dev
,
3895 "add mac addr failed for uc_overflow.\n");
3896 } else if (resp_code
== 3) {
3897 return_status
= -ENOSPC
;
3898 dev_err(&hdev
->pdev
->dev
,
3899 "add mac addr failed for mc_overflow.\n");
3901 dev_err(&hdev
->pdev
->dev
,
3902 "add mac addr failed for undefined, code=%d.\n",
3905 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3908 } else if (resp_code
== 1) {
3909 return_status
= -ENOENT
;
3910 dev_dbg(&hdev
->pdev
->dev
,
3911 "remove mac addr failed for miss.\n");
3913 dev_err(&hdev
->pdev
->dev
,
3914 "remove mac addr failed for undefined, code=%d.\n",
3917 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3920 } else if (resp_code
== 1) {
3921 return_status
= -ENOENT
;
3922 dev_dbg(&hdev
->pdev
->dev
,
3923 "lookup mac addr failed for miss.\n");
3925 dev_err(&hdev
->pdev
->dev
,
3926 "lookup mac addr failed for undefined, code=%d.\n",
3930 return_status
= -EINVAL
;
3931 dev_err(&hdev
->pdev
->dev
,
3932 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3936 return return_status
;
3939 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3944 if (vfid
> 255 || vfid
< 0)
3947 if (vfid
>= 0 && vfid
<= 191) {
3948 word_num
= vfid
/ 32;
3949 bit_num
= vfid
% 32;
3951 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3953 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3955 word_num
= (vfid
- 192) / 32;
3956 bit_num
= vfid
% 32;
3958 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3960 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3966 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3968 #define HCLGE_DESC_NUMBER 3
3969 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3972 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3973 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3974 if (desc
[i
].data
[j
])
3980 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3983 const unsigned char *mac_addr
= addr
;
3984 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3985 (mac_addr
[0]) | (mac_addr
[1] << 8);
3986 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3988 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3989 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3992 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3995 u16 high_val
= addr
[1] | (addr
[0] << 8);
3996 struct hclge_dev
*hdev
= vport
->back
;
3997 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3998 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
4003 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
4004 enum hclge_mta_dmac_sel_type mta_mac_sel
,
4007 struct hclge_mta_filter_mode_cmd
*req
;
4008 struct hclge_desc desc
;
4011 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
4012 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
4014 hnae3_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
4016 hnae3_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
4017 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
4019 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4021 dev_err(&hdev
->pdev
->dev
,
4022 "Config mat filter mode failed for cmd_send, ret =%d.\n",
4028 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
4032 struct hclge_cfg_func_mta_filter_cmd
*req
;
4033 struct hclge_desc desc
;
4036 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
4037 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
4039 hnae3_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
4041 req
->function_id
= func_id
;
4043 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4045 dev_err(&hdev
->pdev
->dev
,
4046 "Config func_id enable failed for cmd_send, ret =%d.\n",
4052 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
4056 struct hclge_dev
*hdev
= vport
->back
;
4057 struct hclge_cfg_func_mta_item_cmd
*req
;
4058 struct hclge_desc desc
;
4062 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
4063 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
4064 hnae3_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
4066 hnae3_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
4067 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
4068 req
->item_idx
= cpu_to_le16(item_idx
);
4070 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4072 dev_err(&hdev
->pdev
->dev
,
4073 "Config mta table item failed for cmd_send, ret =%d.\n",
4079 set_bit(idx
, vport
->mta_shadow
);
4081 clear_bit(idx
, vport
->mta_shadow
);
4086 static int hclge_update_mta_status(struct hnae3_handle
*handle
)
4088 unsigned long mta_status
[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE
)];
4089 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4090 struct net_device
*netdev
= handle
->kinfo
.netdev
;
4091 struct netdev_hw_addr
*ha
;
4094 memset(mta_status
, 0, sizeof(mta_status
));
4096 /* update mta_status from mc addr list */
4097 netdev_for_each_mc_addr(ha
, netdev
) {
4098 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, ha
->addr
);
4099 set_bit(tbl_idx
, mta_status
);
4102 return hclge_update_mta_status_common(vport
, mta_status
,
4103 0, HCLGE_MTA_TBL_SIZE
, true);
4106 int hclge_update_mta_status_common(struct hclge_vport
*vport
,
4107 unsigned long *status
,
4112 struct hclge_dev
*hdev
= vport
->back
;
4113 u16 update_max
= idx
+ count
;
4119 /* setup mta check range */
4120 if (update_filter
) {
4122 check_max
= HCLGE_MTA_TBL_SIZE
;
4125 check_max
= update_max
;
4129 /* check and update all mta item */
4130 for (; i
< check_max
; i
++) {
4131 /* ignore unused item */
4132 if (!test_bit(i
, vport
->mta_shadow
))
4135 /* if i in update range then update it */
4136 if (i
>= idx
&& i
< update_max
)
4137 if (!test_bit(i
- idx
, status
))
4138 hclge_set_mta_table_item(vport
, i
, false);
4140 if (!used
&& test_bit(i
, vport
->mta_shadow
))
4144 /* no longer use mta, disable it */
4145 if (vport
->accept_mta_mc
&& update_filter
&& !used
) {
4146 ret
= hclge_cfg_func_mta_filter(hdev
,
4150 dev_err(&hdev
->pdev
->dev
,
4151 "disable func mta filter fail ret=%d\n",
4154 vport
->accept_mta_mc
= false;
4160 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4161 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4163 struct hclge_dev
*hdev
= vport
->back
;
4164 struct hclge_desc desc
;
4169 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4171 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4173 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4175 dev_err(&hdev
->pdev
->dev
,
4176 "del mac addr failed for cmd_send, ret =%d.\n",
4180 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4181 retval
= le16_to_cpu(desc
.retval
);
4183 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4184 HCLGE_MAC_VLAN_REMOVE
);
4187 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4188 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4189 struct hclge_desc
*desc
,
4192 struct hclge_dev
*hdev
= vport
->back
;
4197 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4199 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4200 memcpy(desc
[0].data
,
4202 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4203 hclge_cmd_setup_basic_desc(&desc
[1],
4204 HCLGE_OPC_MAC_VLAN_ADD
,
4206 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4207 hclge_cmd_setup_basic_desc(&desc
[2],
4208 HCLGE_OPC_MAC_VLAN_ADD
,
4210 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4212 memcpy(desc
[0].data
,
4214 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4215 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4218 dev_err(&hdev
->pdev
->dev
,
4219 "lookup mac addr failed for cmd_send, ret =%d.\n",
4223 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4224 retval
= le16_to_cpu(desc
[0].retval
);
4226 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4227 HCLGE_MAC_VLAN_LKUP
);
4230 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4231 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4232 struct hclge_desc
*mc_desc
)
4234 struct hclge_dev
*hdev
= vport
->back
;
4241 struct hclge_desc desc
;
4243 hclge_cmd_setup_basic_desc(&desc
,
4244 HCLGE_OPC_MAC_VLAN_ADD
,
4246 memcpy(desc
.data
, req
,
4247 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4248 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4249 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4250 retval
= le16_to_cpu(desc
.retval
);
4252 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4254 HCLGE_MAC_VLAN_ADD
);
4256 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4257 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4258 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4259 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4260 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4261 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4262 memcpy(mc_desc
[0].data
, req
,
4263 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4264 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4265 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4266 retval
= le16_to_cpu(mc_desc
[0].retval
);
4268 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4270 HCLGE_MAC_VLAN_ADD
);
4274 dev_err(&hdev
->pdev
->dev
,
4275 "add mac addr failed for cmd_send, ret =%d.\n",
4283 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4284 const unsigned char *addr
)
4286 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4288 return hclge_add_uc_addr_common(vport
, addr
);
4291 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4292 const unsigned char *addr
)
4294 struct hclge_dev
*hdev
= vport
->back
;
4295 struct hclge_mac_vlan_tbl_entry_cmd req
;
4296 struct hclge_desc desc
;
4297 u16 egress_port
= 0;
4300 /* mac addr check */
4301 if (is_zero_ether_addr(addr
) ||
4302 is_broadcast_ether_addr(addr
) ||
4303 is_multicast_ether_addr(addr
)) {
4304 dev_err(&hdev
->pdev
->dev
,
4305 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4307 is_zero_ether_addr(addr
),
4308 is_broadcast_ether_addr(addr
),
4309 is_multicast_ether_addr(addr
));
4313 memset(&req
, 0, sizeof(req
));
4314 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4316 hnae3_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4317 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4319 req
.egress_port
= cpu_to_le16(egress_port
);
4321 hclge_prepare_mac_addr(&req
, addr
);
4323 /* Lookup the mac address in the mac_vlan table, and add
4324 * it if the entry is inexistent. Repeated unicast entry
4325 * is not allowed in the mac vlan table.
4327 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4329 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4331 /* check if we just hit the duplicate */
4335 dev_err(&hdev
->pdev
->dev
,
4336 "PF failed to add unicast entry(%pM) in the MAC table\n",
4342 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4343 const unsigned char *addr
)
4345 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4347 return hclge_rm_uc_addr_common(vport
, addr
);
4350 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4351 const unsigned char *addr
)
4353 struct hclge_dev
*hdev
= vport
->back
;
4354 struct hclge_mac_vlan_tbl_entry_cmd req
;
4357 /* mac addr check */
4358 if (is_zero_ether_addr(addr
) ||
4359 is_broadcast_ether_addr(addr
) ||
4360 is_multicast_ether_addr(addr
)) {
4361 dev_dbg(&hdev
->pdev
->dev
,
4362 "Remove mac err! invalid mac:%pM.\n",
4367 memset(&req
, 0, sizeof(req
));
4368 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4369 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4370 hclge_prepare_mac_addr(&req
, addr
);
4371 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4376 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4377 const unsigned char *addr
)
4379 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4381 return hclge_add_mc_addr_common(vport
, addr
);
4384 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4385 const unsigned char *addr
)
4387 struct hclge_dev
*hdev
= vport
->back
;
4388 struct hclge_mac_vlan_tbl_entry_cmd req
;
4389 struct hclge_desc desc
[3];
4393 /* mac addr check */
4394 if (!is_multicast_ether_addr(addr
)) {
4395 dev_err(&hdev
->pdev
->dev
,
4396 "Add mc mac err! invalid mac:%pM.\n",
4400 memset(&req
, 0, sizeof(req
));
4401 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4402 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4403 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4404 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4405 hclge_prepare_mac_addr(&req
, addr
);
4406 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4408 /* This mac addr exist, update VFID for it */
4409 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4410 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4412 /* This mac addr do not exist, add new entry for it */
4413 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4414 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4415 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4416 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4417 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4420 /* If mc mac vlan table is full, use MTA table */
4421 if (status
== -ENOSPC
) {
4422 if (!vport
->accept_mta_mc
) {
4423 status
= hclge_cfg_func_mta_filter(hdev
,
4427 dev_err(&hdev
->pdev
->dev
,
4428 "set mta filter mode fail ret=%d\n",
4432 vport
->accept_mta_mc
= true;
4435 /* Set MTA table for this MAC address */
4436 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4437 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4443 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4444 const unsigned char *addr
)
4446 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4448 return hclge_rm_mc_addr_common(vport
, addr
);
4451 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4452 const unsigned char *addr
)
4454 struct hclge_dev
*hdev
= vport
->back
;
4455 struct hclge_mac_vlan_tbl_entry_cmd req
;
4456 enum hclge_cmd_status status
;
4457 struct hclge_desc desc
[3];
4459 /* mac addr check */
4460 if (!is_multicast_ether_addr(addr
)) {
4461 dev_dbg(&hdev
->pdev
->dev
,
4462 "Remove mc mac err! invalid mac:%pM.\n",
4467 memset(&req
, 0, sizeof(req
));
4468 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4469 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4470 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4471 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4472 hclge_prepare_mac_addr(&req
, addr
);
4473 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4475 /* This mac addr exist, remove this handle's VFID for it */
4476 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4478 if (hclge_is_all_function_id_zero(desc
))
4479 /* All the vfid is zero, so need to delete this entry */
4480 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4482 /* Not all the vfid is zero, update the vfid */
4483 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4486 /* Maybe this mac address is in mta table, but it cannot be
4487 * deleted here because an entry of mta represents an address
4488 * range rather than a specific address. the delete action to
4489 * all entries will take effect in update_mta_status called by
4490 * hns3_nic_set_rx_mode.
4498 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4499 u16 cmdq_resp
, u8 resp_code
)
4501 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4502 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4503 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4504 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4509 dev_err(&hdev
->pdev
->dev
,
4510 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4515 switch (resp_code
) {
4516 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4517 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4520 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4521 dev_err(&hdev
->pdev
->dev
,
4522 "add mac ethertype failed for manager table overflow.\n");
4523 return_status
= -EIO
;
4525 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4526 dev_err(&hdev
->pdev
->dev
,
4527 "add mac ethertype failed for key conflict.\n");
4528 return_status
= -EIO
;
4531 dev_err(&hdev
->pdev
->dev
,
4532 "add mac ethertype failed for undefined, code=%d.\n",
4534 return_status
= -EIO
;
4537 return return_status
;
4540 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4541 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4543 struct hclge_desc desc
;
4548 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4549 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4551 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4553 dev_err(&hdev
->pdev
->dev
,
4554 "add mac ethertype failed for cmd_send, ret =%d.\n",
4559 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4560 retval
= le16_to_cpu(desc
.retval
);
4562 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4565 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4570 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4571 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4573 dev_err(&hdev
->pdev
->dev
,
4574 "add mac ethertype failed, ret =%d.\n",
4583 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4585 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4586 struct hclge_dev
*hdev
= vport
->back
;
4588 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4591 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4594 const unsigned char *new_addr
= (const unsigned char *)p
;
4595 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4596 struct hclge_dev
*hdev
= vport
->back
;
4599 /* mac addr check */
4600 if (is_zero_ether_addr(new_addr
) ||
4601 is_broadcast_ether_addr(new_addr
) ||
4602 is_multicast_ether_addr(new_addr
)) {
4603 dev_err(&hdev
->pdev
->dev
,
4604 "Change uc mac err! invalid mac:%p.\n",
4609 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4610 dev_warn(&hdev
->pdev
->dev
,
4611 "remove old uc mac address fail.\n");
4613 ret
= hclge_add_uc_addr(handle
, new_addr
);
4615 dev_err(&hdev
->pdev
->dev
,
4616 "add uc mac address fail, ret =%d.\n",
4620 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4621 dev_err(&hdev
->pdev
->dev
,
4622 "restore uc mac address fail.\n");
4627 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4629 dev_err(&hdev
->pdev
->dev
,
4630 "configure mac pause address fail, ret =%d.\n",
4635 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4640 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4643 struct hclge_vlan_filter_ctrl_cmd
*req
;
4644 struct hclge_desc desc
;
4647 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4649 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4650 req
->vlan_type
= vlan_type
;
4651 req
->vlan_fe
= filter_en
;
4653 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4655 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4661 #define HCLGE_FILTER_TYPE_VF 0
4662 #define HCLGE_FILTER_TYPE_PORT 1
4664 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4666 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4667 struct hclge_dev
*hdev
= vport
->back
;
4669 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4672 static int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4673 bool is_kill
, u16 vlan
, u8 qos
,
4676 #define HCLGE_MAX_VF_BYTES 16
4677 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4678 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4679 struct hclge_desc desc
[2];
4684 hclge_cmd_setup_basic_desc(&desc
[0],
4685 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4686 hclge_cmd_setup_basic_desc(&desc
[1],
4687 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4689 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4691 vf_byte_off
= vfid
/ 8;
4692 vf_byte_val
= 1 << (vfid
% 8);
4694 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4695 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4697 req0
->vlan_id
= cpu_to_le16(vlan
);
4698 req0
->vlan_cfg
= is_kill
;
4700 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4701 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4703 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4705 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4707 dev_err(&hdev
->pdev
->dev
,
4708 "Send vf vlan command fail, ret =%d.\n",
4714 #define HCLGE_VF_VLAN_NO_ENTRY 2
4715 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4718 if (req0
->resp_code
== HCLGE_VF_VLAN_NO_ENTRY
) {
4719 dev_warn(&hdev
->pdev
->dev
,
4720 "vf vlan table is full, vf vlan filter is disabled\n");
4724 dev_err(&hdev
->pdev
->dev
,
4725 "Add vf vlan filter fail, ret =%d.\n",
4728 if (!req0
->resp_code
)
4731 dev_err(&hdev
->pdev
->dev
,
4732 "Kill vf vlan filter fail, ret =%d.\n",
4739 static int hclge_set_port_vlan_filter(struct hclge_dev
*hdev
, __be16 proto
,
4740 u16 vlan_id
, bool is_kill
)
4742 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4743 struct hclge_desc desc
;
4744 u8 vlan_offset_byte_val
;
4745 u8 vlan_offset_byte
;
4749 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4751 vlan_offset_160
= vlan_id
/ 160;
4752 vlan_offset_byte
= (vlan_id
% 160) / 8;
4753 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4755 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4756 req
->vlan_offset
= vlan_offset_160
;
4757 req
->vlan_cfg
= is_kill
;
4758 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4760 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4762 dev_err(&hdev
->pdev
->dev
,
4763 "port vlan command, send fail, ret =%d.\n", ret
);
4767 static int hclge_set_vlan_filter_hw(struct hclge_dev
*hdev
, __be16 proto
,
4768 u16 vport_id
, u16 vlan_id
, u8 qos
,
4771 u16 vport_idx
, vport_num
= 0;
4774 ret
= hclge_set_vf_vlan_common(hdev
, vport_id
, is_kill
, vlan_id
,
4777 dev_err(&hdev
->pdev
->dev
,
4778 "Set %d vport vlan filter config fail, ret =%d.\n",
4783 /* vlan 0 may be added twice when 8021q module is enabled */
4784 if (!is_kill
&& !vlan_id
&&
4785 test_bit(vport_id
, hdev
->vlan_table
[vlan_id
]))
4788 if (!is_kill
&& test_and_set_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4789 dev_err(&hdev
->pdev
->dev
,
4790 "Add port vlan failed, vport %d is already in vlan %d\n",
4796 !test_and_clear_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4797 dev_err(&hdev
->pdev
->dev
,
4798 "Delete port vlan failed, vport %d is not in vlan %d\n",
4803 for_each_set_bit(vport_idx
, hdev
->vlan_table
[vlan_id
], VLAN_N_VID
)
4806 if ((is_kill
&& vport_num
== 0) || (!is_kill
&& vport_num
== 1))
4807 ret
= hclge_set_port_vlan_filter(hdev
, proto
, vlan_id
,
4813 int hclge_set_vlan_filter(struct hnae3_handle
*handle
, __be16 proto
,
4814 u16 vlan_id
, bool is_kill
)
4816 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4817 struct hclge_dev
*hdev
= vport
->back
;
4819 return hclge_set_vlan_filter_hw(hdev
, proto
, vport
->vport_id
, vlan_id
,
4823 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4824 u16 vlan
, u8 qos
, __be16 proto
)
4826 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4827 struct hclge_dev
*hdev
= vport
->back
;
4829 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4831 if (proto
!= htons(ETH_P_8021Q
))
4832 return -EPROTONOSUPPORT
;
4834 return hclge_set_vlan_filter_hw(hdev
, proto
, vfid
, vlan
, qos
, false);
4837 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4839 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4840 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4841 struct hclge_dev
*hdev
= vport
->back
;
4842 struct hclge_desc desc
;
4845 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4847 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4848 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4849 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4850 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG1_B
,
4851 vcfg
->accept_tag1
? 1 : 0);
4852 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG1_B
,
4853 vcfg
->accept_untag1
? 1 : 0);
4854 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG2_B
,
4855 vcfg
->accept_tag2
? 1 : 0);
4856 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG2_B
,
4857 vcfg
->accept_untag2
? 1 : 0);
4858 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4859 vcfg
->insert_tag1_en
? 1 : 0);
4860 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4861 vcfg
->insert_tag2_en
? 1 : 0);
4862 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4864 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4865 req
->vf_bitmap
[req
->vf_offset
] =
4866 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4868 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4870 dev_err(&hdev
->pdev
->dev
,
4871 "Send port txvlan cfg command fail, ret =%d\n",
4877 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4879 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4880 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4881 struct hclge_dev
*hdev
= vport
->back
;
4882 struct hclge_desc desc
;
4885 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4887 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4888 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4889 vcfg
->strip_tag1_en
? 1 : 0);
4890 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4891 vcfg
->strip_tag2_en
? 1 : 0);
4892 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4893 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4894 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4895 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4897 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4898 req
->vf_bitmap
[req
->vf_offset
] =
4899 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4901 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4903 dev_err(&hdev
->pdev
->dev
,
4904 "Send port rxvlan cfg command fail, ret =%d\n",
4910 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4912 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4913 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4914 struct hclge_desc desc
;
4917 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4918 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4919 rx_req
->ot_fst_vlan_type
=
4920 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4921 rx_req
->ot_sec_vlan_type
=
4922 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4923 rx_req
->in_fst_vlan_type
=
4924 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4925 rx_req
->in_sec_vlan_type
=
4926 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4928 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4930 dev_err(&hdev
->pdev
->dev
,
4931 "Send rxvlan protocol type command fail, ret =%d\n",
4936 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4938 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4939 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4940 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4942 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4944 dev_err(&hdev
->pdev
->dev
,
4945 "Send txvlan protocol type command fail, ret =%d\n",
4951 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4953 #define HCLGE_DEF_VLAN_TYPE 0x8100
4955 struct hnae3_handle
*handle
;
4956 struct hclge_vport
*vport
;
4960 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4964 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4968 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4969 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4970 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4971 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4972 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4973 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4975 ret
= hclge_set_vlan_protocol_type(hdev
);
4979 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4980 vport
= &hdev
->vport
[i
];
4981 vport
->txvlan_cfg
.accept_tag1
= true;
4982 vport
->txvlan_cfg
.accept_untag1
= true;
4984 /* accept_tag2 and accept_untag2 are not supported on
4985 * pdev revision(0x20), new revision support them. The
4986 * value of this two fields will not return error when driver
4987 * send command to fireware in revision(0x20).
4988 * This two fields can not configured by user.
4990 vport
->txvlan_cfg
.accept_tag2
= true;
4991 vport
->txvlan_cfg
.accept_untag2
= true;
4993 vport
->txvlan_cfg
.insert_tag1_en
= false;
4994 vport
->txvlan_cfg
.insert_tag2_en
= false;
4995 vport
->txvlan_cfg
.default_tag1
= 0;
4996 vport
->txvlan_cfg
.default_tag2
= 0;
4998 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
5002 vport
->rxvlan_cfg
.strip_tag1_en
= false;
5003 vport
->rxvlan_cfg
.strip_tag2_en
= true;
5004 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
5005 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
5007 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
5012 handle
= &hdev
->vport
[0].nic
;
5013 return hclge_set_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
5016 int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
5018 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5020 vport
->rxvlan_cfg
.strip_tag1_en
= false;
5021 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
5022 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
5023 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
5025 return hclge_set_vlan_rx_offload_cfg(vport
);
5028 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
5030 struct hclge_config_max_frm_size_cmd
*req
;
5031 struct hclge_desc desc
;
5035 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
5037 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
5038 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
5041 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
5043 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
5045 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
5046 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
5047 req
->min_frm_size
= HCLGE_MAC_MIN_FRAME
;
5049 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5051 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
5053 hdev
->mps
= max_frm_size
;
5058 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
5060 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5061 struct hclge_dev
*hdev
= vport
->back
;
5064 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
5066 dev_err(&hdev
->pdev
->dev
,
5067 "Change mtu fail, ret =%d\n", ret
);
5071 ret
= hclge_buffer_alloc(hdev
);
5073 dev_err(&hdev
->pdev
->dev
,
5074 "Allocate buffer fail, ret =%d\n", ret
);
5079 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
5082 struct hclge_reset_tqp_queue_cmd
*req
;
5083 struct hclge_desc desc
;
5086 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
5088 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5089 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5090 hnae3_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
5092 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5094 dev_err(&hdev
->pdev
->dev
,
5095 "Send tqp reset cmd error, status =%d\n", ret
);
5102 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
5104 struct hclge_reset_tqp_queue_cmd
*req
;
5105 struct hclge_desc desc
;
5108 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
5110 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5111 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5113 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5115 dev_err(&hdev
->pdev
->dev
,
5116 "Get reset status error, status =%d\n", ret
);
5120 return hnae3_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
5123 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
5126 struct hnae3_queue
*queue
;
5127 struct hclge_tqp
*tqp
;
5129 queue
= handle
->kinfo
.tqp
[queue_id
];
5130 tqp
= container_of(queue
, struct hclge_tqp
, q
);
5135 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
5137 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5138 struct hclge_dev
*hdev
= vport
->back
;
5139 int reset_try_times
= 0;
5144 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
5147 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
5149 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
5151 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
5155 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5157 dev_warn(&hdev
->pdev
->dev
,
5158 "Send reset tqp cmd fail, ret = %d\n", ret
);
5162 reset_try_times
= 0;
5163 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5164 /* Wait for tqp hw reset */
5166 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5171 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5172 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5176 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5178 dev_warn(&hdev
->pdev
->dev
,
5179 "Deassert the soft reset fail, ret = %d\n", ret
);
5184 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
5186 struct hclge_dev
*hdev
= vport
->back
;
5187 int reset_try_times
= 0;
5192 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5194 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5196 dev_warn(&hdev
->pdev
->dev
,
5197 "Send reset tqp cmd fail, ret = %d\n", ret
);
5201 reset_try_times
= 0;
5202 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5203 /* Wait for tqp hw reset */
5205 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5210 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5211 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5215 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5217 dev_warn(&hdev
->pdev
->dev
,
5218 "Deassert the soft reset fail, ret = %d\n", ret
);
5221 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5223 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5224 struct hclge_dev
*hdev
= vport
->back
;
5226 return hdev
->fw_version
;
5229 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5232 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5233 struct hclge_dev
*hdev
= vport
->back
;
5234 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5239 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5240 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5243 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5245 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5250 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5253 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5256 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5259 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5264 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5265 else if (rx_en
&& !tx_en
)
5266 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5267 else if (!rx_en
&& tx_en
)
5268 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5270 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5272 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5275 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5277 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5282 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5287 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5289 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5290 u16 remote_advertising
= 0;
5291 u16 local_advertising
= 0;
5292 u32 rx_pause
, tx_pause
;
5295 if (!phydev
->link
|| !phydev
->autoneg
)
5298 if (phydev
->advertising
& ADVERTISED_Pause
)
5299 local_advertising
= ADVERTISE_PAUSE_CAP
;
5301 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5302 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5305 remote_advertising
= LPA_PAUSE_CAP
;
5307 if (phydev
->asym_pause
)
5308 remote_advertising
|= LPA_PAUSE_ASYM
;
5310 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5311 remote_advertising
);
5312 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5313 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5315 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5320 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5323 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5324 u32
*rx_en
, u32
*tx_en
)
5326 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5327 struct hclge_dev
*hdev
= vport
->back
;
5329 *auto_neg
= hclge_get_autoneg(handle
);
5331 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5337 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5340 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5343 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5352 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5353 u32 rx_en
, u32 tx_en
)
5355 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5356 struct hclge_dev
*hdev
= vport
->back
;
5357 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5360 fc_autoneg
= hclge_get_autoneg(handle
);
5361 if (auto_neg
!= fc_autoneg
) {
5362 dev_info(&hdev
->pdev
->dev
,
5363 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5367 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5368 dev_info(&hdev
->pdev
->dev
,
5369 "Priority flow control enabled. Cannot set link flow control.\n");
5373 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5376 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5378 /* Only support flow control negotiation for netdev with
5379 * phy attached for now.
5384 return phy_start_aneg(phydev
);
5387 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5388 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5390 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5391 struct hclge_dev
*hdev
= vport
->back
;
5394 *speed
= hdev
->hw
.mac
.speed
;
5396 *duplex
= hdev
->hw
.mac
.duplex
;
5398 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5401 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5403 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5404 struct hclge_dev
*hdev
= vport
->back
;
5407 *media_type
= hdev
->hw
.mac
.media_type
;
5410 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5411 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5413 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5414 struct hclge_dev
*hdev
= vport
->back
;
5415 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5416 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5419 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5420 *tp_mdix
= ETH_TP_MDI_INVALID
;
5424 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5426 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5427 mdix_ctrl
= hnae3_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5428 HCLGE_PHY_MDIX_CTRL_S
);
5430 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5431 mdix
= hnae3_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5432 is_resolved
= hnae3_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5434 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5436 switch (mdix_ctrl
) {
5438 *tp_mdix_ctrl
= ETH_TP_MDI
;
5441 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5444 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5447 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5452 *tp_mdix
= ETH_TP_MDI_INVALID
;
5454 *tp_mdix
= ETH_TP_MDI_X
;
5456 *tp_mdix
= ETH_TP_MDI
;
5459 static int hclge_init_client_instance(struct hnae3_client
*client
,
5460 struct hnae3_ae_dev
*ae_dev
)
5462 struct hclge_dev
*hdev
= ae_dev
->priv
;
5463 struct hclge_vport
*vport
;
5466 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5467 vport
= &hdev
->vport
[i
];
5469 switch (client
->type
) {
5470 case HNAE3_CLIENT_KNIC
:
5472 hdev
->nic_client
= client
;
5473 vport
->nic
.client
= client
;
5474 ret
= client
->ops
->init_instance(&vport
->nic
);
5478 if (hdev
->roce_client
&&
5479 hnae3_dev_roce_supported(hdev
)) {
5480 struct hnae3_client
*rc
= hdev
->roce_client
;
5482 ret
= hclge_init_roce_base_info(vport
);
5486 ret
= rc
->ops
->init_instance(&vport
->roce
);
5492 case HNAE3_CLIENT_UNIC
:
5493 hdev
->nic_client
= client
;
5494 vport
->nic
.client
= client
;
5496 ret
= client
->ops
->init_instance(&vport
->nic
);
5501 case HNAE3_CLIENT_ROCE
:
5502 if (hnae3_dev_roce_supported(hdev
)) {
5503 hdev
->roce_client
= client
;
5504 vport
->roce
.client
= client
;
5507 if (hdev
->roce_client
&& hdev
->nic_client
) {
5508 ret
= hclge_init_roce_base_info(vport
);
5512 ret
= client
->ops
->init_instance(&vport
->roce
);
5522 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5523 struct hnae3_ae_dev
*ae_dev
)
5525 struct hclge_dev
*hdev
= ae_dev
->priv
;
5526 struct hclge_vport
*vport
;
5529 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5530 vport
= &hdev
->vport
[i
];
5531 if (hdev
->roce_client
) {
5532 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5534 hdev
->roce_client
= NULL
;
5535 vport
->roce
.client
= NULL
;
5537 if (client
->type
== HNAE3_CLIENT_ROCE
)
5539 if (client
->ops
->uninit_instance
) {
5540 client
->ops
->uninit_instance(&vport
->nic
, 0);
5541 hdev
->nic_client
= NULL
;
5542 vport
->nic
.client
= NULL
;
5547 static int hclge_pci_init(struct hclge_dev
*hdev
)
5549 struct pci_dev
*pdev
= hdev
->pdev
;
5550 struct hclge_hw
*hw
;
5553 ret
= pci_enable_device(pdev
);
5555 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5559 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5561 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5564 "can't set consistent PCI DMA");
5565 goto err_disable_device
;
5567 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5570 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5572 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5573 goto err_disable_device
;
5576 pci_set_master(pdev
);
5578 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5580 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5582 goto err_clr_master
;
5585 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5589 pci_clear_master(pdev
);
5590 pci_release_regions(pdev
);
5592 pci_disable_device(pdev
);
5597 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5599 struct pci_dev
*pdev
= hdev
->pdev
;
5601 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5602 pci_free_irq_vectors(pdev
);
5603 pci_clear_master(pdev
);
5604 pci_release_mem_regions(pdev
);
5605 pci_disable_device(pdev
);
5608 static void hclge_state_init(struct hclge_dev
*hdev
)
5610 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5611 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5612 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5613 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5614 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5615 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5618 static void hclge_state_uninit(struct hclge_dev
*hdev
)
5620 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5622 if (hdev
->service_timer
.function
)
5623 del_timer_sync(&hdev
->service_timer
);
5624 if (hdev
->service_task
.func
)
5625 cancel_work_sync(&hdev
->service_task
);
5626 if (hdev
->rst_service_task
.func
)
5627 cancel_work_sync(&hdev
->rst_service_task
);
5628 if (hdev
->mbx_service_task
.func
)
5629 cancel_work_sync(&hdev
->mbx_service_task
);
5632 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5634 struct pci_dev
*pdev
= ae_dev
->pdev
;
5635 struct hclge_dev
*hdev
;
5638 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5645 hdev
->ae_dev
= ae_dev
;
5646 hdev
->reset_type
= HNAE3_NONE_RESET
;
5647 ae_dev
->priv
= hdev
;
5649 ret
= hclge_pci_init(hdev
);
5651 dev_err(&pdev
->dev
, "PCI init failed\n");
5655 /* Firmware command queue initialize */
5656 ret
= hclge_cmd_queue_init(hdev
);
5658 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5659 goto err_pci_uninit
;
5662 /* Firmware command initialize */
5663 ret
= hclge_cmd_init(hdev
);
5665 goto err_cmd_uninit
;
5667 ret
= hclge_get_cap(hdev
);
5669 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5671 goto err_cmd_uninit
;
5674 ret
= hclge_configure(hdev
);
5676 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5677 goto err_cmd_uninit
;
5680 ret
= hclge_init_msi(hdev
);
5682 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5683 goto err_cmd_uninit
;
5686 ret
= hclge_misc_irq_init(hdev
);
5689 "Misc IRQ(vector0) init error, ret = %d.\n",
5691 goto err_msi_uninit
;
5694 ret
= hclge_alloc_tqps(hdev
);
5696 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5697 goto err_msi_irq_uninit
;
5700 ret
= hclge_alloc_vport(hdev
);
5702 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5703 goto err_msi_irq_uninit
;
5706 ret
= hclge_map_tqp(hdev
);
5708 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5709 goto err_msi_irq_uninit
;
5712 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5713 ret
= hclge_mac_mdio_config(hdev
);
5715 dev_err(&hdev
->pdev
->dev
,
5716 "mdio config fail ret=%d\n", ret
);
5717 goto err_msi_irq_uninit
;
5721 ret
= hclge_mac_init(hdev
);
5723 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5724 goto err_mdiobus_unreg
;
5727 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5729 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5730 goto err_mdiobus_unreg
;
5733 ret
= hclge_init_vlan_config(hdev
);
5735 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5736 goto err_mdiobus_unreg
;
5739 ret
= hclge_tm_schd_init(hdev
);
5741 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5742 goto err_mdiobus_unreg
;
5745 hclge_rss_init_cfg(hdev
);
5746 ret
= hclge_rss_init_hw(hdev
);
5748 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5749 goto err_mdiobus_unreg
;
5752 ret
= init_mgr_tbl(hdev
);
5754 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5755 goto err_mdiobus_unreg
;
5758 hclge_dcb_ops_set(hdev
);
5760 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5761 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5762 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5763 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5765 hclge_clear_all_event_cause(hdev
);
5767 /* Enable MISC vector(vector0) */
5768 hclge_enable_vector(&hdev
->misc_vector
, true);
5770 hclge_state_init(hdev
);
5772 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5776 if (hdev
->hw
.mac
.phydev
)
5777 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5779 hclge_misc_irq_uninit(hdev
);
5781 pci_free_irq_vectors(pdev
);
5783 hclge_destroy_cmd_queue(&hdev
->hw
);
5785 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5786 pci_clear_master(pdev
);
5787 pci_release_regions(pdev
);
5788 pci_disable_device(pdev
);
5793 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5795 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5798 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5800 struct hclge_dev
*hdev
= ae_dev
->priv
;
5801 struct pci_dev
*pdev
= ae_dev
->pdev
;
5804 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5806 hclge_stats_clear(hdev
);
5807 memset(hdev
->vlan_table
, 0, sizeof(hdev
->vlan_table
));
5809 ret
= hclge_cmd_init(hdev
);
5811 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5815 ret
= hclge_get_cap(hdev
);
5817 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5822 ret
= hclge_configure(hdev
);
5824 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5828 ret
= hclge_map_tqp(hdev
);
5830 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5834 ret
= hclge_mac_init(hdev
);
5836 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5840 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5842 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5846 ret
= hclge_init_vlan_config(hdev
);
5848 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5852 ret
= hclge_tm_init_hw(hdev
);
5854 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5858 ret
= hclge_rss_init_hw(hdev
);
5860 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5864 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5870 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5872 struct hclge_dev
*hdev
= ae_dev
->priv
;
5873 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5875 hclge_state_uninit(hdev
);
5878 mdiobus_unregister(mac
->mdio_bus
);
5880 /* Disable MISC vector(vector0) */
5881 hclge_enable_vector(&hdev
->misc_vector
, false);
5882 synchronize_irq(hdev
->misc_vector
.vector_irq
);
5884 hclge_destroy_cmd_queue(&hdev
->hw
);
5885 hclge_misc_irq_uninit(hdev
);
5886 hclge_pci_uninit(hdev
);
5887 ae_dev
->priv
= NULL
;
5890 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5892 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5893 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5894 struct hclge_dev
*hdev
= vport
->back
;
5896 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5899 static void hclge_get_channels(struct hnae3_handle
*handle
,
5900 struct ethtool_channels
*ch
)
5902 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5904 ch
->max_combined
= hclge_get_max_channels(handle
);
5905 ch
->other_count
= 1;
5907 ch
->combined_count
= vport
->alloc_tqps
;
5910 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5911 u16
*free_tqps
, u16
*max_rss_size
)
5913 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5914 struct hclge_dev
*hdev
= vport
->back
;
5918 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5919 if (!hdev
->htqp
[i
].alloced
)
5922 *free_tqps
= temp_tqps
;
5923 *max_rss_size
= hdev
->rss_size_max
;
5926 static void hclge_release_tqp(struct hclge_vport
*vport
)
5928 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5929 struct hclge_dev
*hdev
= vport
->back
;
5932 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5933 struct hclge_tqp
*tqp
=
5934 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5936 tqp
->q
.handle
= NULL
;
5937 tqp
->q
.tqp_index
= 0;
5938 tqp
->alloced
= false;
5941 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5945 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5947 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5948 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5949 struct hclge_dev
*hdev
= vport
->back
;
5950 int cur_rss_size
= kinfo
->rss_size
;
5951 int cur_tqps
= kinfo
->num_tqps
;
5952 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5953 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5954 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5959 /* Free old tqps, and reallocate with new tqp number when nic setup */
5960 hclge_release_tqp(vport
);
5962 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5964 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5968 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5970 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5974 ret
= hclge_tm_schd_init(hdev
);
5976 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5980 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5981 roundup_size
= ilog2(roundup_size
);
5982 /* Set the RSS TC mode according to the new RSS size */
5983 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5986 if (!(hdev
->hw_tc_map
& BIT(i
)))
5990 tc_size
[i
] = roundup_size
;
5991 tc_offset
[i
] = kinfo
->rss_size
* i
;
5993 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5997 /* Reinitializes the rss indirect table according to the new RSS size */
5998 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
6002 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
6003 rss_indir
[i
] = i
% kinfo
->rss_size
;
6005 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
6007 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
6013 dev_info(&hdev
->pdev
->dev
,
6014 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
6015 cur_rss_size
, kinfo
->rss_size
,
6016 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
6021 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
6022 u32
*regs_num_64_bit
)
6024 struct hclge_desc desc
;
6028 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
6029 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6031 dev_err(&hdev
->pdev
->dev
,
6032 "Query register number cmd failed, ret = %d.\n", ret
);
6036 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
6037 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
6039 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
6046 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6049 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6051 struct hclge_desc
*desc
;
6052 u32
*reg_val
= data
;
6061 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
6062 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6066 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
6067 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6069 dev_err(&hdev
->pdev
->dev
,
6070 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
6075 for (i
= 0; i
< cmd_num
; i
++) {
6077 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
6078 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
6080 desc_data
= (__le32
*)(&desc
[i
]);
6081 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
6083 for (k
= 0; k
< n
; k
++) {
6084 *reg_val
++ = le32_to_cpu(*desc_data
++);
6096 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6099 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6101 struct hclge_desc
*desc
;
6102 u64
*reg_val
= data
;
6111 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
6112 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6116 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
6117 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6119 dev_err(&hdev
->pdev
->dev
,
6120 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
6125 for (i
= 0; i
< cmd_num
; i
++) {
6127 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
6128 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
6130 desc_data
= (__le64
*)(&desc
[i
]);
6131 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
6133 for (k
= 0; k
< n
; k
++) {
6134 *reg_val
++ = le64_to_cpu(*desc_data
++);
6146 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
6148 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6149 struct hclge_dev
*hdev
= vport
->back
;
6150 u32 regs_num_32_bit
, regs_num_64_bit
;
6153 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6155 dev_err(&hdev
->pdev
->dev
,
6156 "Get register number failed, ret = %d.\n", ret
);
6160 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
6163 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
6166 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6167 struct hclge_dev
*hdev
= vport
->back
;
6168 u32 regs_num_32_bit
, regs_num_64_bit
;
6171 *version
= hdev
->fw_version
;
6173 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6175 dev_err(&hdev
->pdev
->dev
,
6176 "Get register number failed, ret = %d.\n", ret
);
6180 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
6182 dev_err(&hdev
->pdev
->dev
,
6183 "Get 32 bit register failed, ret = %d.\n", ret
);
6187 data
= (u32
*)data
+ regs_num_32_bit
;
6188 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
6191 dev_err(&hdev
->pdev
->dev
,
6192 "Get 64 bit register failed, ret = %d.\n", ret
);
6195 static int hclge_set_led_status(struct hclge_dev
*hdev
, u8 locate_led_status
)
6197 struct hclge_set_led_state_cmd
*req
;
6198 struct hclge_desc desc
;
6201 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6203 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6204 hnae3_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6205 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6207 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6209 dev_err(&hdev
->pdev
->dev
,
6210 "Send set led state cmd error, ret =%d\n", ret
);
6215 enum hclge_led_status
{
6218 HCLGE_LED_NO_CHANGE
= 0xFF,
6221 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6222 enum ethtool_phys_id_state status
)
6224 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6225 struct hclge_dev
*hdev
= vport
->back
;
6228 case ETHTOOL_ID_ACTIVE
:
6229 return hclge_set_led_status(hdev
, HCLGE_LED_ON
);
6230 case ETHTOOL_ID_INACTIVE
:
6231 return hclge_set_led_status(hdev
, HCLGE_LED_OFF
);
6237 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6238 unsigned long *supported
,
6239 unsigned long *advertising
)
6241 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6242 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6243 struct hclge_dev
*hdev
= vport
->back
;
6244 unsigned int idx
= 0;
6246 for (; idx
< size
; idx
++) {
6247 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6248 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6252 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6255 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6256 struct hclge_dev
*hdev
= vport
->back
;
6257 u8 media_type
= hdev
->hw
.mac
.media_type
;
6259 switch (media_type
) {
6260 case HNAE3_MEDIA_TYPE_FIBER
:
6261 *port_type
= PORT_FIBRE
;
6263 case HNAE3_MEDIA_TYPE_COPPER
:
6264 *port_type
= PORT_TP
;
6266 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6268 *port_type
= PORT_OTHER
;
6273 static const struct hnae3_ae_ops hclge_ops
= {
6274 .init_ae_dev
= hclge_init_ae_dev
,
6275 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6276 .init_client_instance
= hclge_init_client_instance
,
6277 .uninit_client_instance
= hclge_uninit_client_instance
,
6278 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6279 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6280 .get_vector
= hclge_get_vector
,
6281 .put_vector
= hclge_put_vector
,
6282 .set_promisc_mode
= hclge_set_promisc_mode
,
6283 .set_loopback
= hclge_set_loopback
,
6284 .start
= hclge_ae_start
,
6285 .stop
= hclge_ae_stop
,
6286 .get_status
= hclge_get_status
,
6287 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6288 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6289 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6290 .get_media_type
= hclge_get_media_type
,
6291 .get_rss_key_size
= hclge_get_rss_key_size
,
6292 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6293 .get_rss
= hclge_get_rss
,
6294 .set_rss
= hclge_set_rss
,
6295 .set_rss_tuple
= hclge_set_rss_tuple
,
6296 .get_rss_tuple
= hclge_get_rss_tuple
,
6297 .get_tc_size
= hclge_get_tc_size
,
6298 .get_mac_addr
= hclge_get_mac_addr
,
6299 .set_mac_addr
= hclge_set_mac_addr
,
6300 .add_uc_addr
= hclge_add_uc_addr
,
6301 .rm_uc_addr
= hclge_rm_uc_addr
,
6302 .add_mc_addr
= hclge_add_mc_addr
,
6303 .rm_mc_addr
= hclge_rm_mc_addr
,
6304 .update_mta_status
= hclge_update_mta_status
,
6305 .set_autoneg
= hclge_set_autoneg
,
6306 .get_autoneg
= hclge_get_autoneg
,
6307 .get_pauseparam
= hclge_get_pauseparam
,
6308 .set_pauseparam
= hclge_set_pauseparam
,
6309 .set_mtu
= hclge_set_mtu
,
6310 .reset_queue
= hclge_reset_tqp
,
6311 .get_stats
= hclge_get_stats
,
6312 .update_stats
= hclge_update_stats
,
6313 .get_strings
= hclge_get_strings
,
6314 .get_sset_count
= hclge_get_sset_count
,
6315 .get_fw_version
= hclge_get_fw_version
,
6316 .get_mdix_mode
= hclge_get_mdix_mode
,
6317 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6318 .set_vlan_filter
= hclge_set_vlan_filter
,
6319 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6320 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6321 .reset_event
= hclge_reset_event
,
6322 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6323 .set_channels
= hclge_set_channels
,
6324 .get_channels
= hclge_get_channels
,
6325 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6326 .get_regs_len
= hclge_get_regs_len
,
6327 .get_regs
= hclge_get_regs
,
6328 .set_led_id
= hclge_set_led_id
,
6329 .get_link_mode
= hclge_get_link_mode
,
6330 .get_port_type
= hclge_get_port_type
,
6333 static struct hnae3_ae_algo ae_algo
= {
6335 .pdev_id_table
= ae_algo_pci_tbl
,
6338 static int hclge_init(void)
6340 pr_info("%s is initializing\n", HCLGE_NAME
);
6342 hnae3_register_ae_algo(&ae_algo
);
6347 static void hclge_exit(void)
6349 hnae3_unregister_ae_algo(&ae_algo
);
6351 module_init(hclge_init
);
6352 module_exit(hclge_exit
);
6354 MODULE_LICENSE("GPL");
6355 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6356 MODULE_DESCRIPTION("HCLGE Driver");
6357 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob