2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <net/rtnetlink.h>
21 #include "hclge_cmd.h"
22 #include "hclge_dcb.h"
23 #include "hclge_main.h"
24 #include "hclge_mbx.h"
25 #include "hclge_mdio.h"
29 #define HCLGE_NAME "hclge"
30 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
31 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
32 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
33 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
36 enum hclge_mta_dmac_sel_type mta_mac_sel
,
38 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
39 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
41 static struct hnae3_ae_algo ae_algo
;
43 static const struct pci_device_id ae_algo_pci_tbl
[] = {
44 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
45 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
51 /* required last entry */
55 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
57 "Serdes Loopback test",
61 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
62 {"igu_rx_oversize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
64 {"igu_rx_undersize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
66 {"igu_rx_out_all_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
74 {"egu_tx_out_all_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
82 {"ssu_ppp_mac_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
84 {"ssu_ppp_host_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
86 {"ppp_ssu_mac_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
88 {"ppp_ssu_host_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
100 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
103 {"igu_rx_no_eof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
105 {"igu_rx_no_sof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
108 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
109 {"ssu_full_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
111 {"ssu_part_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
125 {"qcn_fb_invaild_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
127 {"rx_packet_tc0_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
129 {"rx_packet_tc1_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
131 {"rx_packet_tc2_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
133 {"rx_packet_tc3_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
135 {"rx_packet_tc4_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
137 {"rx_packet_tc5_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
139 {"rx_packet_tc6_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
141 {"rx_packet_tc7_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
143 {"rx_packet_tc0_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
145 {"rx_packet_tc1_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
147 {"rx_packet_tc2_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
149 {"rx_packet_tc3_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
151 {"rx_packet_tc4_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
153 {"rx_packet_tc5_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
155 {"rx_packet_tc6_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
157 {"rx_packet_tc7_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
159 {"tx_packet_tc0_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
161 {"tx_packet_tc1_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
163 {"tx_packet_tc2_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
165 {"tx_packet_tc3_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
167 {"tx_packet_tc4_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
169 {"tx_packet_tc5_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
171 {"tx_packet_tc6_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
173 {"tx_packet_tc7_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
175 {"tx_packet_tc0_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
177 {"tx_packet_tc1_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
179 {"tx_packet_tc2_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
181 {"tx_packet_tc3_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
183 {"tx_packet_tc4_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
185 {"tx_packet_tc5_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
187 {"tx_packet_tc6_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
189 {"tx_packet_tc7_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
191 {"pkt_curr_buf_tc0_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
193 {"pkt_curr_buf_tc1_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
195 {"pkt_curr_buf_tc2_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
197 {"pkt_curr_buf_tc3_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
199 {"pkt_curr_buf_tc4_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
201 {"pkt_curr_buf_tc5_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
203 {"pkt_curr_buf_tc6_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
205 {"pkt_curr_buf_tc7_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
208 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
209 {"lo_pri_unicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
211 {"hi_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
213 {"lo_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
215 {"rx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
217 {"tx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
219 {"nic_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
221 {"roc_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
225 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
226 {"mac_tx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
228 {"mac_rx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
230 {"mac_tx_pfc_pri0_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
232 {"mac_tx_pfc_pri1_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
234 {"mac_tx_pfc_pri2_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
236 {"mac_tx_pfc_pri3_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
238 {"mac_tx_pfc_pri4_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
240 {"mac_tx_pfc_pri5_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
242 {"mac_tx_pfc_pri6_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
244 {"mac_tx_pfc_pri7_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
246 {"mac_rx_pfc_pri0_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
248 {"mac_rx_pfc_pri1_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
250 {"mac_rx_pfc_pri2_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
252 {"mac_rx_pfc_pri3_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
254 {"mac_rx_pfc_pri4_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
256 {"mac_rx_pfc_pri5_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
258 {"mac_rx_pfc_pri6_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
260 {"mac_rx_pfc_pri7_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
262 {"mac_tx_total_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
264 {"mac_tx_total_oct_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
266 {"mac_tx_good_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
268 {"mac_tx_bad_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
270 {"mac_tx_good_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
272 {"mac_tx_bad_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
274 {"mac_tx_uni_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
276 {"mac_tx_multi_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
278 {"mac_tx_broad_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
280 {"mac_tx_undersize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
282 {"mac_tx_oversize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
284 {"mac_tx_64_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
286 {"mac_tx_65_127_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
288 {"mac_tx_128_255_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
290 {"mac_tx_256_511_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
292 {"mac_tx_512_1023_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
294 {"mac_tx_1024_1518_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
296 {"mac_tx_1519_max_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num
)},
298 {"mac_rx_total_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
300 {"mac_rx_total_oct_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
302 {"mac_rx_good_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
304 {"mac_rx_bad_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
306 {"mac_rx_good_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
308 {"mac_rx_bad_oct_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
310 {"mac_rx_uni_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
312 {"mac_rx_multi_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
314 {"mac_rx_broad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
316 {"mac_rx_undersize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
318 {"mac_rx_oversize_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
320 {"mac_rx_64_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
322 {"mac_rx_65_127_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
324 {"mac_rx_128_255_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
326 {"mac_rx_256_511_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
328 {"mac_rx_512_1023_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
330 {"mac_rx_1024_1518_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
332 {"mac_rx_1519_max_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num
)},
335 {"mac_tx_fragment_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
337 {"mac_tx_undermin_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
339 {"mac_tx_jabber_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
341 {"mac_tx_err_all_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
343 {"mac_tx_from_app_good_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
345 {"mac_tx_from_app_bad_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
347 {"mac_rx_fragment_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
349 {"mac_rx_undermin_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
351 {"mac_rx_jabber_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
353 {"mac_rx_fcs_err_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
355 {"mac_rx_send_app_good_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
357 {"mac_rx_send_app_bad_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
361 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
363 #define HCLGE_64_BIT_CMD_NUM 5
364 #define HCLGE_64_BIT_RTN_DATANUM 4
365 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
366 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
371 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
372 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
374 dev_err(&hdev
->pdev
->dev
,
375 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
379 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
380 if (unlikely(i
== 0)) {
381 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
382 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
384 desc_data
= (__le64
*)(&desc
[i
]);
385 n
= HCLGE_64_BIT_RTN_DATANUM
;
387 for (k
= 0; k
< n
; k
++) {
388 *data
++ += le64_to_cpu(*desc_data
);
396 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
398 stats
->pkt_curr_buf_cnt
= 0;
399 stats
->pkt_curr_buf_tc0_cnt
= 0;
400 stats
->pkt_curr_buf_tc1_cnt
= 0;
401 stats
->pkt_curr_buf_tc2_cnt
= 0;
402 stats
->pkt_curr_buf_tc3_cnt
= 0;
403 stats
->pkt_curr_buf_tc4_cnt
= 0;
404 stats
->pkt_curr_buf_tc5_cnt
= 0;
405 stats
->pkt_curr_buf_tc6_cnt
= 0;
406 stats
->pkt_curr_buf_tc7_cnt
= 0;
409 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
411 #define HCLGE_32_BIT_CMD_NUM 8
412 #define HCLGE_32_BIT_RTN_DATANUM 8
414 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
415 struct hclge_32_bit_stats
*all_32_bit_stats
;
421 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
422 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
424 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
425 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
427 dev_err(&hdev
->pdev
->dev
,
428 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
433 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
434 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
435 if (unlikely(i
== 0)) {
436 __le16
*desc_data_16bit
;
438 all_32_bit_stats
->igu_rx_err_pkt
+=
439 le32_to_cpu(desc
[i
].data
[0]);
441 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
442 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
443 le16_to_cpu(*desc_data_16bit
);
446 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
447 le16_to_cpu(*desc_data_16bit
);
449 desc_data
= &desc
[i
].data
[2];
450 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
452 desc_data
= (__le32
*)&desc
[i
];
453 n
= HCLGE_32_BIT_RTN_DATANUM
;
455 for (k
= 0; k
< n
; k
++) {
456 *data
++ += le32_to_cpu(*desc_data
);
464 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
466 #define HCLGE_MAC_CMD_NUM 17
467 #define HCLGE_RTN_DATA_NUM 4
469 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
470 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
475 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
476 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
478 dev_err(&hdev
->pdev
->dev
,
479 "Get MAC pkt stats fail, status = %d.\n", ret
);
484 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
485 if (unlikely(i
== 0)) {
486 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
487 n
= HCLGE_RTN_DATA_NUM
- 2;
489 desc_data
= (__le64
*)(&desc
[i
]);
490 n
= HCLGE_RTN_DATA_NUM
;
492 for (k
= 0; k
< n
; k
++) {
493 *data
++ += le64_to_cpu(*desc_data
);
501 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
503 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
504 struct hclge_vport
*vport
= hclge_get_vport(handle
);
505 struct hclge_dev
*hdev
= vport
->back
;
506 struct hnae3_queue
*queue
;
507 struct hclge_desc desc
[1];
508 struct hclge_tqp
*tqp
;
511 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
512 queue
= handle
->kinfo
.tqp
[i
];
513 tqp
= container_of(queue
, struct hclge_tqp
, q
);
514 /* command : HCLGE_OPC_QUERY_IGU_STAT */
515 hclge_cmd_setup_basic_desc(&desc
[0],
516 HCLGE_OPC_QUERY_RX_STATUS
,
519 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
520 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
522 dev_err(&hdev
->pdev
->dev
,
523 "Query tqp stat fail, status = %d,queue = %d\n",
527 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
528 le32_to_cpu(desc
[0].data
[4]);
531 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
532 queue
= handle
->kinfo
.tqp
[i
];
533 tqp
= container_of(queue
, struct hclge_tqp
, q
);
534 /* command : HCLGE_OPC_QUERY_IGU_STAT */
535 hclge_cmd_setup_basic_desc(&desc
[0],
536 HCLGE_OPC_QUERY_TX_STATUS
,
539 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
540 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
542 dev_err(&hdev
->pdev
->dev
,
543 "Query tqp stat fail, status = %d,queue = %d\n",
547 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
548 le32_to_cpu(desc
[0].data
[4]);
554 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
556 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
557 struct hclge_tqp
*tqp
;
561 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
562 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
563 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
566 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
567 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
568 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
574 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
576 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
578 return kinfo
->num_tqps
* (2);
581 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
583 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
587 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
588 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
589 struct hclge_tqp
, q
);
590 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
592 buff
= buff
+ ETH_GSTRING_LEN
;
595 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
596 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
597 struct hclge_tqp
, q
);
598 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
600 buff
= buff
+ ETH_GSTRING_LEN
;
606 static u64
*hclge_comm_get_stats(void *comm_stats
,
607 const struct hclge_comm_stats_str strs
[],
613 for (i
= 0; i
< size
; i
++)
614 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
619 static u8
*hclge_comm_get_strings(u32 stringset
,
620 const struct hclge_comm_stats_str strs
[],
623 char *buff
= (char *)data
;
626 if (stringset
!= ETH_SS_STATS
)
629 for (i
= 0; i
< size
; i
++) {
630 snprintf(buff
, ETH_GSTRING_LEN
,
632 buff
= buff
+ ETH_GSTRING_LEN
;
638 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
639 struct net_device_stats
*net_stats
)
641 net_stats
->tx_dropped
= 0;
642 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
643 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
644 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
646 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
647 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
648 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_err_pkt
;
649 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
650 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
651 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
653 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
654 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
656 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
657 net_stats
->rx_length_errors
=
658 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
659 net_stats
->rx_length_errors
+=
660 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
661 net_stats
->rx_over_errors
=
662 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
665 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
667 struct hnae3_handle
*handle
;
670 handle
= &hdev
->vport
[0].nic
;
671 if (handle
->client
) {
672 status
= hclge_tqps_update_stats(handle
);
674 dev_err(&hdev
->pdev
->dev
,
675 "Update TQPS stats fail, status = %d.\n",
680 status
= hclge_mac_update_stats(hdev
);
682 dev_err(&hdev
->pdev
->dev
,
683 "Update MAC stats fail, status = %d.\n", status
);
685 status
= hclge_32_bit_update_stats(hdev
);
687 dev_err(&hdev
->pdev
->dev
,
688 "Update 32 bit stats fail, status = %d.\n",
691 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
694 static void hclge_update_stats(struct hnae3_handle
*handle
,
695 struct net_device_stats
*net_stats
)
697 struct hclge_vport
*vport
= hclge_get_vport(handle
);
698 struct hclge_dev
*hdev
= vport
->back
;
699 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
702 status
= hclge_mac_update_stats(hdev
);
704 dev_err(&hdev
->pdev
->dev
,
705 "Update MAC stats fail, status = %d.\n",
708 status
= hclge_32_bit_update_stats(hdev
);
710 dev_err(&hdev
->pdev
->dev
,
711 "Update 32 bit stats fail, status = %d.\n",
714 status
= hclge_64_bit_update_stats(hdev
);
716 dev_err(&hdev
->pdev
->dev
,
717 "Update 64 bit stats fail, status = %d.\n",
720 status
= hclge_tqps_update_stats(handle
);
722 dev_err(&hdev
->pdev
->dev
,
723 "Update TQPS stats fail, status = %d.\n",
726 hclge_update_netstat(hw_stats
, net_stats
);
729 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
731 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
733 struct hclge_vport
*vport
= hclge_get_vport(handle
);
734 struct hclge_dev
*hdev
= vport
->back
;
737 /* Loopback test support rules:
738 * mac: only GE mode support
739 * serdes: all mac mode will support include GE/XGE/LGE/CGE
740 * phy: only support when phy device exist on board
742 if (stringset
== ETH_SS_TEST
) {
743 /* clear loopback bit flags at first */
744 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
745 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
746 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
747 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
749 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
753 } else if (stringset
== ETH_SS_STATS
) {
754 count
= ARRAY_SIZE(g_mac_stats_string
) +
755 ARRAY_SIZE(g_all_32bit_stats_string
) +
756 ARRAY_SIZE(g_all_64bit_stats_string
) +
757 hclge_tqps_get_sset_count(handle
, stringset
);
763 static void hclge_get_strings(struct hnae3_handle
*handle
,
767 u8
*p
= (char *)data
;
770 if (stringset
== ETH_SS_STATS
) {
771 size
= ARRAY_SIZE(g_mac_stats_string
);
772 p
= hclge_comm_get_strings(stringset
,
776 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
777 p
= hclge_comm_get_strings(stringset
,
778 g_all_32bit_stats_string
,
781 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
782 p
= hclge_comm_get_strings(stringset
,
783 g_all_64bit_stats_string
,
786 p
= hclge_tqps_get_strings(handle
, p
);
787 } else if (stringset
== ETH_SS_TEST
) {
788 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
790 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
792 p
+= ETH_GSTRING_LEN
;
794 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
796 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
798 p
+= ETH_GSTRING_LEN
;
800 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
802 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
804 p
+= ETH_GSTRING_LEN
;
809 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
811 struct hclge_vport
*vport
= hclge_get_vport(handle
);
812 struct hclge_dev
*hdev
= vport
->back
;
815 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
817 ARRAY_SIZE(g_mac_stats_string
),
819 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
820 g_all_32bit_stats_string
,
821 ARRAY_SIZE(g_all_32bit_stats_string
),
823 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
824 g_all_64bit_stats_string
,
825 ARRAY_SIZE(g_all_64bit_stats_string
),
827 p
= hclge_tqps_get_stats(handle
, p
);
830 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
831 struct hclge_func_status_cmd
*status
)
833 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
836 /* Set the pf to main pf */
837 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
838 hdev
->flag
|= HCLGE_FLAG_MAIN
;
840 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
845 static int hclge_query_function_status(struct hclge_dev
*hdev
)
847 struct hclge_func_status_cmd
*req
;
848 struct hclge_desc desc
;
852 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
853 req
= (struct hclge_func_status_cmd
*)desc
.data
;
856 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
858 dev_err(&hdev
->pdev
->dev
,
859 "query function status failed %d.\n",
865 /* Check pf reset is done */
868 usleep_range(1000, 2000);
869 } while (timeout
++ < 5);
871 ret
= hclge_parse_func_status(hdev
, req
);
876 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
878 struct hclge_pf_res_cmd
*req
;
879 struct hclge_desc desc
;
882 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
883 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
885 dev_err(&hdev
->pdev
->dev
,
886 "query pf resource failed %d.\n", ret
);
890 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
891 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
892 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
894 if (hnae3_dev_roce_supported(hdev
)) {
896 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
897 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
899 /* PF should have NIC vectors and Roce vectors,
900 * NIC vectors are queued before Roce vectors.
902 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
905 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
906 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
912 static int hclge_parse_speed(int speed_cmd
, int *speed
)
916 *speed
= HCLGE_MAC_SPEED_10M
;
919 *speed
= HCLGE_MAC_SPEED_100M
;
922 *speed
= HCLGE_MAC_SPEED_1G
;
925 *speed
= HCLGE_MAC_SPEED_10G
;
928 *speed
= HCLGE_MAC_SPEED_25G
;
931 *speed
= HCLGE_MAC_SPEED_40G
;
934 *speed
= HCLGE_MAC_SPEED_50G
;
937 *speed
= HCLGE_MAC_SPEED_100G
;
946 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
948 struct hclge_cfg_param_cmd
*req
;
949 u64 mac_addr_tmp_high
;
953 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
955 /* get the configuration */
956 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
959 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
960 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
961 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
962 HCLGE_CFG_TQP_DESC_N_M
,
963 HCLGE_CFG_TQP_DESC_N_S
);
965 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
966 HCLGE_CFG_PHY_ADDR_M
,
967 HCLGE_CFG_PHY_ADDR_S
);
968 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
969 HCLGE_CFG_MEDIA_TP_M
,
970 HCLGE_CFG_MEDIA_TP_S
);
971 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
972 HCLGE_CFG_RX_BUF_LEN_M
,
973 HCLGE_CFG_RX_BUF_LEN_S
);
974 /* get mac_address */
975 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
976 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
977 HCLGE_CFG_MAC_ADDR_H_M
,
978 HCLGE_CFG_MAC_ADDR_H_S
);
980 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
982 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
983 HCLGE_CFG_DEFAULT_SPEED_M
,
984 HCLGE_CFG_DEFAULT_SPEED_S
);
985 cfg
->rss_size_max
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
986 HCLGE_CFG_RSS_SIZE_M
,
987 HCLGE_CFG_RSS_SIZE_S
);
989 for (i
= 0; i
< ETH_ALEN
; i
++)
990 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
992 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
993 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
996 /* hclge_get_cfg: query the static parameter from flash
997 * @hdev: pointer to struct hclge_dev
998 * @hcfg: the config structure to be getted
1000 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1002 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1003 struct hclge_cfg_param_cmd
*req
;
1006 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1009 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1010 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1012 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1013 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1014 /* Len should be united by 4 bytes when send to hardware */
1015 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1016 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1017 req
->offset
= cpu_to_le32(offset
);
1020 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1022 dev_err(&hdev
->pdev
->dev
,
1023 "get config failed %d.\n", ret
);
1027 hclge_parse_cfg(hcfg
, desc
);
1031 static int hclge_get_cap(struct hclge_dev
*hdev
)
1035 ret
= hclge_query_function_status(hdev
);
1037 dev_err(&hdev
->pdev
->dev
,
1038 "query function status error %d.\n", ret
);
1042 /* get pf resource */
1043 ret
= hclge_query_pf_resource(hdev
);
1045 dev_err(&hdev
->pdev
->dev
,
1046 "query pf resource error %d.\n", ret
);
1053 static int hclge_configure(struct hclge_dev
*hdev
)
1055 struct hclge_cfg cfg
;
1058 ret
= hclge_get_cfg(hdev
, &cfg
);
1060 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1064 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1065 hdev
->base_tqp_pid
= 0;
1066 hdev
->rss_size_max
= cfg
.rss_size_max
;
1067 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1068 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1069 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1070 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1071 hdev
->num_desc
= cfg
.tqp_desc_num
;
1072 hdev
->tm_info
.num_pg
= 1;
1073 hdev
->tc_max
= cfg
.tc_num
;
1074 hdev
->tm_info
.hw_pfc_map
= 0;
1076 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1078 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1082 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1083 (hdev
->tc_max
< 1)) {
1084 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1089 /* Dev does not support DCB */
1090 if (!hnae3_dev_dcb_supported(hdev
)) {
1094 hdev
->pfc_max
= hdev
->tc_max
;
1097 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1099 /* Currently not support uncontiuous tc */
1100 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1101 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1103 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1108 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1111 struct hclge_cfg_tso_status_cmd
*req
;
1112 struct hclge_desc desc
;
1115 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1117 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1120 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1121 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1122 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1125 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1126 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1127 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1129 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1132 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1134 struct hclge_tqp
*tqp
;
1137 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1138 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1144 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1145 tqp
->dev
= &hdev
->pdev
->dev
;
1148 tqp
->q
.ae_algo
= &ae_algo
;
1149 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1150 tqp
->q
.desc_num
= hdev
->num_desc
;
1151 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1152 i
* HCLGE_TQP_REG_SIZE
;
1160 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1161 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1163 struct hclge_tqp_map_cmd
*req
;
1164 struct hclge_desc desc
;
1167 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1169 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1170 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1171 req
->tqp_vf
= func_id
;
1172 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1173 1 << HCLGE_TQP_MAP_EN_B
;
1174 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1176 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1178 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1186 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1187 struct hnae3_queue
**tqp
, u16 num_tqps
)
1189 struct hclge_dev
*hdev
= vport
->back
;
1192 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1193 alloced
< num_tqps
; i
++) {
1194 if (!hdev
->htqp
[i
].alloced
) {
1195 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1196 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1197 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1198 hdev
->htqp
[i
].alloced
= true;
1202 vport
->alloc_tqps
= num_tqps
;
1207 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1209 struct hnae3_handle
*nic
= &vport
->nic
;
1210 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1211 struct hclge_dev
*hdev
= vport
->back
;
1214 kinfo
->num_desc
= hdev
->num_desc
;
1215 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1216 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1218 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1219 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1221 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1222 if (hdev
->hw_tc_map
& BIT(i
)) {
1223 kinfo
->tc_info
[i
].enable
= true;
1224 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1225 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1226 kinfo
->tc_info
[i
].tc
= i
;
1228 /* Set to default queue if TC is disable */
1229 kinfo
->tc_info
[i
].enable
= false;
1230 kinfo
->tc_info
[i
].tqp_offset
= 0;
1231 kinfo
->tc_info
[i
].tqp_count
= 1;
1232 kinfo
->tc_info
[i
].tc
= 0;
1236 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1237 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1241 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1243 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1250 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1251 struct hclge_vport
*vport
)
1253 struct hnae3_handle
*nic
= &vport
->nic
;
1254 struct hnae3_knic_private_info
*kinfo
;
1257 kinfo
= &nic
->kinfo
;
1258 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1259 struct hclge_tqp
*q
=
1260 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1264 is_pf
= !(vport
->vport_id
);
1265 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1274 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1276 struct hclge_vport
*vport
= hdev
->vport
;
1279 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1280 for (i
= 0; i
< num_vport
; i
++) {
1283 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1293 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1295 /* this would be initialized later */
1298 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1300 struct hnae3_handle
*nic
= &vport
->nic
;
1301 struct hclge_dev
*hdev
= vport
->back
;
1304 nic
->pdev
= hdev
->pdev
;
1305 nic
->ae_algo
= &ae_algo
;
1306 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1308 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1309 ret
= hclge_knic_setup(vport
, num_tqps
);
1311 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1316 hclge_unic_setup(vport
, num_tqps
);
1322 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1324 struct pci_dev
*pdev
= hdev
->pdev
;
1325 struct hclge_vport
*vport
;
1331 /* We need to alloc a vport for main NIC of PF */
1332 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1334 if (hdev
->num_tqps
< num_vport
)
1335 num_vport
= hdev
->num_tqps
;
1337 /* Alloc the same number of TQPs for every vport */
1338 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1339 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1341 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1346 hdev
->vport
= vport
;
1347 hdev
->num_alloc_vport
= num_vport
;
1349 #ifdef CONFIG_PCI_IOV
1351 if (hdev
->num_req_vfs
) {
1352 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1354 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1356 hdev
->num_alloc_vfs
= 0;
1357 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1362 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1365 for (i
= 0; i
< num_vport
; i
++) {
1367 vport
->vport_id
= i
;
1370 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1372 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1375 "vport setup failed for vport %d, %d\n",
1386 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1387 struct hclge_pkt_buf_alloc
*buf_alloc
)
1389 /* TX buffer size is unit by 128 byte */
1390 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1391 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1392 struct hclge_tx_buff_alloc_cmd
*req
;
1393 struct hclge_desc desc
;
1397 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1399 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1400 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1401 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1403 req
->tx_pkt_buff
[i
] =
1404 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1405 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1408 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1410 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1418 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1419 struct hclge_pkt_buf_alloc
*buf_alloc
)
1421 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1424 dev_err(&hdev
->pdev
->dev
,
1425 "tx buffer alloc failed %d\n", ret
);
1432 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1436 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1437 if (hdev
->hw_tc_map
& BIT(i
))
1442 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1446 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1447 if (hdev
->hw_tc_map
& BIT(i
) &&
1448 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1453 /* Get the number of pfc enabled TCs, which have private buffer */
1454 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1455 struct hclge_pkt_buf_alloc
*buf_alloc
)
1457 struct hclge_priv_buf
*priv
;
1460 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1461 priv
= &buf_alloc
->priv_buf
[i
];
1462 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1470 /* Get the number of pfc disabled TCs, which have private buffer */
1471 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1472 struct hclge_pkt_buf_alloc
*buf_alloc
)
1474 struct hclge_priv_buf
*priv
;
1477 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1478 priv
= &buf_alloc
->priv_buf
[i
];
1479 if (hdev
->hw_tc_map
& BIT(i
) &&
1480 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1488 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1490 struct hclge_priv_buf
*priv
;
1494 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1495 priv
= &buf_alloc
->priv_buf
[i
];
1497 rx_priv
+= priv
->buf_size
;
1502 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1504 u32 i
, total_tx_size
= 0;
1506 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1507 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1509 return total_tx_size
;
1512 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1513 struct hclge_pkt_buf_alloc
*buf_alloc
,
1516 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1517 int tc_num
, pfc_enable_num
;
1522 tc_num
= hclge_get_tc_num(hdev
);
1523 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1525 if (hnae3_dev_dcb_supported(hdev
))
1526 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1528 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1530 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1531 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1533 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1535 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1536 if (rx_all
<= rx_priv
+ shared_std
)
1539 shared_buf
= rx_all
- rx_priv
;
1540 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1541 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1542 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1544 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1545 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1546 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1547 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1548 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1550 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1551 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1558 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1559 struct hclge_pkt_buf_alloc
*buf_alloc
)
1563 total_size
= hdev
->pkt_buf_size
;
1565 /* alloc tx buffer for all enabled tc */
1566 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1567 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1569 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1572 if (hdev
->hw_tc_map
& BIT(i
))
1573 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1575 priv
->tx_buf_size
= 0;
1577 total_size
-= priv
->tx_buf_size
;
1583 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1584 * @hdev: pointer to struct hclge_dev
1585 * @buf_alloc: pointer to buffer calculation data
1586 * @return: 0: calculate sucessful, negative: fail
1588 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1589 struct hclge_pkt_buf_alloc
*buf_alloc
)
1591 u32 rx_all
= hdev
->pkt_buf_size
;
1592 int no_pfc_priv_num
, pfc_priv_num
;
1593 struct hclge_priv_buf
*priv
;
1596 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1598 /* When DCB is not supported, rx private
1599 * buffer is not allocated.
1601 if (!hnae3_dev_dcb_supported(hdev
)) {
1602 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1608 /* step 1, try to alloc private buffer for all enabled tc */
1609 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1610 priv
= &buf_alloc
->priv_buf
[i
];
1611 if (hdev
->hw_tc_map
& BIT(i
)) {
1613 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1614 priv
->wl
.low
= hdev
->mps
;
1615 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1616 priv
->buf_size
= priv
->wl
.high
+
1620 priv
->wl
.high
= 2 * hdev
->mps
;
1621 priv
->buf_size
= priv
->wl
.high
;
1631 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1634 /* step 2, try to decrease the buffer size of
1635 * no pfc TC's private buffer
1637 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1638 priv
= &buf_alloc
->priv_buf
[i
];
1645 if (!(hdev
->hw_tc_map
& BIT(i
)))
1650 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1652 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1653 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1656 priv
->wl
.high
= hdev
->mps
;
1657 priv
->buf_size
= priv
->wl
.high
;
1661 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1664 /* step 3, try to reduce the number of pfc disabled TCs,
1665 * which have private buffer
1667 /* get the total no pfc enable TC number, which have private buffer */
1668 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1670 /* let the last to be cleared first */
1671 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1672 priv
= &buf_alloc
->priv_buf
[i
];
1674 if (hdev
->hw_tc_map
& BIT(i
) &&
1675 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1676 /* Clear the no pfc TC private buffer */
1684 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1685 no_pfc_priv_num
== 0)
1689 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1692 /* step 4, try to reduce the number of pfc enabled TCs
1693 * which have private buffer.
1695 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1697 /* let the last to be cleared first */
1698 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1699 priv
= &buf_alloc
->priv_buf
[i
];
1701 if (hdev
->hw_tc_map
& BIT(i
) &&
1702 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1703 /* Reduce the number of pfc TC with private buffer */
1711 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1715 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1721 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1722 struct hclge_pkt_buf_alloc
*buf_alloc
)
1724 struct hclge_rx_priv_buff_cmd
*req
;
1725 struct hclge_desc desc
;
1729 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1730 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1732 /* Alloc private buffer TCs */
1733 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1734 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1737 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1739 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1743 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1744 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1746 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1748 dev_err(&hdev
->pdev
->dev
,
1749 "rx private buffer alloc cmd failed %d\n", ret
);
1756 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1758 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1759 struct hclge_pkt_buf_alloc
*buf_alloc
)
1761 struct hclge_rx_priv_wl_buf
*req
;
1762 struct hclge_priv_buf
*priv
;
1763 struct hclge_desc desc
[2];
1767 for (i
= 0; i
< 2; i
++) {
1768 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1770 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1772 /* The first descriptor set the NEXT bit to 1 */
1774 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1776 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1778 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1779 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1781 priv
= &buf_alloc
->priv_buf
[idx
];
1782 req
->tc_wl
[j
].high
=
1783 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1784 req
->tc_wl
[j
].high
|=
1785 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1786 HCLGE_RX_PRIV_EN_B
);
1788 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1789 req
->tc_wl
[j
].low
|=
1790 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1791 HCLGE_RX_PRIV_EN_B
);
1795 /* Send 2 descriptor at one time */
1796 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1798 dev_err(&hdev
->pdev
->dev
,
1799 "rx private waterline config cmd failed %d\n",
1806 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1807 struct hclge_pkt_buf_alloc
*buf_alloc
)
1809 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1810 struct hclge_rx_com_thrd
*req
;
1811 struct hclge_desc desc
[2];
1812 struct hclge_tc_thrd
*tc
;
1816 for (i
= 0; i
< 2; i
++) {
1817 hclge_cmd_setup_basic_desc(&desc
[i
],
1818 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1819 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1821 /* The first descriptor set the NEXT bit to 1 */
1823 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1825 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1827 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1828 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1830 req
->com_thrd
[j
].high
=
1831 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1832 req
->com_thrd
[j
].high
|=
1833 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1834 HCLGE_RX_PRIV_EN_B
);
1835 req
->com_thrd
[j
].low
=
1836 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1837 req
->com_thrd
[j
].low
|=
1838 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1839 HCLGE_RX_PRIV_EN_B
);
1843 /* Send 2 descriptors at one time */
1844 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1846 dev_err(&hdev
->pdev
->dev
,
1847 "common threshold config cmd failed %d\n", ret
);
1853 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1854 struct hclge_pkt_buf_alloc
*buf_alloc
)
1856 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1857 struct hclge_rx_com_wl
*req
;
1858 struct hclge_desc desc
;
1861 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1863 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1864 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1866 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1867 HCLGE_RX_PRIV_EN_B
);
1869 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1871 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1872 HCLGE_RX_PRIV_EN_B
);
1874 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1876 dev_err(&hdev
->pdev
->dev
,
1877 "common waterline config cmd failed %d\n", ret
);
1884 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1886 struct hclge_pkt_buf_alloc
*pkt_buf
;
1889 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1893 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1895 dev_err(&hdev
->pdev
->dev
,
1896 "could not calc tx buffer size for all TCs %d\n", ret
);
1900 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1902 dev_err(&hdev
->pdev
->dev
,
1903 "could not alloc tx buffers %d\n", ret
);
1907 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1909 dev_err(&hdev
->pdev
->dev
,
1910 "could not calc rx priv buffer size for all TCs %d\n",
1915 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1917 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1922 if (hnae3_dev_dcb_supported(hdev
)) {
1923 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1925 dev_err(&hdev
->pdev
->dev
,
1926 "could not configure rx private waterline %d\n",
1931 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
1933 dev_err(&hdev
->pdev
->dev
,
1934 "could not configure common threshold %d\n",
1940 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
1942 dev_err(&hdev
->pdev
->dev
,
1943 "could not configure common waterline %d\n", ret
);
1950 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
1952 struct hnae3_handle
*roce
= &vport
->roce
;
1953 struct hnae3_handle
*nic
= &vport
->nic
;
1955 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
1957 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
1958 vport
->back
->num_msi_left
== 0)
1961 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
1963 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
1964 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
1966 roce
->pdev
= nic
->pdev
;
1967 roce
->ae_algo
= nic
->ae_algo
;
1968 roce
->numa_node_mask
= nic
->numa_node_mask
;
1973 static int hclge_init_msi(struct hclge_dev
*hdev
)
1975 struct pci_dev
*pdev
= hdev
->pdev
;
1979 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
1980 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
1983 "failed(%d) to allocate MSI/MSI-X vectors\n",
1987 if (vectors
< hdev
->num_msi
)
1988 dev_warn(&hdev
->pdev
->dev
,
1989 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1990 hdev
->num_msi
, vectors
);
1992 hdev
->num_msi
= vectors
;
1993 hdev
->num_msi_left
= vectors
;
1994 hdev
->base_msi_vector
= pdev
->irq
;
1995 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
1996 HCLGE_ROCE_VECTOR_OFFSET
;
1998 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1999 sizeof(u16
), GFP_KERNEL
);
2000 if (!hdev
->vector_status
) {
2001 pci_free_irq_vectors(pdev
);
2005 for (i
= 0; i
< hdev
->num_msi
; i
++)
2006 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2008 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2009 sizeof(int), GFP_KERNEL
);
2010 if (!hdev
->vector_irq
) {
2011 pci_free_irq_vectors(pdev
);
2018 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2020 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2022 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2023 mac
->duplex
= (u8
)duplex
;
2025 mac
->duplex
= HCLGE_MAC_FULL
;
2030 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2032 struct hclge_config_mac_speed_dup_cmd
*req
;
2033 struct hclge_desc desc
;
2036 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2038 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2040 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2043 case HCLGE_MAC_SPEED_10M
:
2044 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2045 HCLGE_CFG_SPEED_S
, 6);
2047 case HCLGE_MAC_SPEED_100M
:
2048 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2049 HCLGE_CFG_SPEED_S
, 7);
2051 case HCLGE_MAC_SPEED_1G
:
2052 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2053 HCLGE_CFG_SPEED_S
, 0);
2055 case HCLGE_MAC_SPEED_10G
:
2056 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2057 HCLGE_CFG_SPEED_S
, 1);
2059 case HCLGE_MAC_SPEED_25G
:
2060 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2061 HCLGE_CFG_SPEED_S
, 2);
2063 case HCLGE_MAC_SPEED_40G
:
2064 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2065 HCLGE_CFG_SPEED_S
, 3);
2067 case HCLGE_MAC_SPEED_50G
:
2068 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2069 HCLGE_CFG_SPEED_S
, 4);
2071 case HCLGE_MAC_SPEED_100G
:
2072 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2073 HCLGE_CFG_SPEED_S
, 5);
2076 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2080 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2083 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2085 dev_err(&hdev
->pdev
->dev
,
2086 "mac speed/duplex config cmd failed %d.\n", ret
);
2090 hclge_check_speed_dup(hdev
, duplex
, speed
);
2095 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2098 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2099 struct hclge_dev
*hdev
= vport
->back
;
2101 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2104 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2107 struct hclge_query_an_speed_dup_cmd
*req
;
2108 struct hclge_desc desc
;
2112 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2114 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2115 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2117 dev_err(&hdev
->pdev
->dev
,
2118 "mac speed/autoneg/duplex query cmd failed %d\n",
2123 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2124 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2125 HCLGE_QUERY_SPEED_S
);
2127 ret
= hclge_parse_speed(speed_tmp
, speed
);
2129 dev_err(&hdev
->pdev
->dev
,
2130 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2137 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2139 struct hclge_config_auto_neg_cmd
*req
;
2140 struct hclge_desc desc
;
2144 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2146 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2147 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2148 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2150 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2152 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2160 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2162 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2163 struct hclge_dev
*hdev
= vport
->back
;
2165 return hclge_set_autoneg_en(hdev
, enable
);
2168 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2170 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2171 struct hclge_dev
*hdev
= vport
->back
;
2172 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2175 return phydev
->autoneg
;
2177 return hdev
->hw
.mac
.autoneg
;
2180 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2184 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2185 struct hclge_desc desc
;
2188 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2189 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2191 hnae_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2193 ether_addr_copy(req
->mac_mask
, mac_mask
);
2195 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2197 dev_err(&hdev
->pdev
->dev
,
2198 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2204 static int hclge_mac_init(struct hclge_dev
*hdev
)
2206 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2207 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2210 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2212 dev_err(&hdev
->pdev
->dev
,
2213 "Config mac speed dup fail ret=%d\n", ret
);
2219 /* Initialize the MTA table work mode */
2220 hdev
->accept_mta_mc
= true;
2221 hdev
->enable_mta
= true;
2222 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2224 ret
= hclge_set_mta_filter_mode(hdev
,
2225 hdev
->mta_mac_sel_type
,
2228 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2233 ret
= hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2235 dev_err(&hdev
->pdev
->dev
,
2236 "set mta filter mode fail ret=%d\n", ret
);
2240 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2242 dev_err(&hdev
->pdev
->dev
,
2243 "set default mac_vlan_mask fail ret=%d\n", ret
);
2248 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2250 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2251 schedule_work(&hdev
->mbx_service_task
);
2254 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2256 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2257 schedule_work(&hdev
->rst_service_task
);
2260 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2262 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2263 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2264 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2265 (void)schedule_work(&hdev
->service_task
);
2268 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2270 struct hclge_link_status_cmd
*req
;
2271 struct hclge_desc desc
;
2275 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2276 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2278 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2283 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2284 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2286 return !!link_status
;
2289 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2294 mac_state
= hclge_get_mac_link_status(hdev
);
2296 if (hdev
->hw
.mac
.phydev
) {
2297 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2298 link_stat
= mac_state
&
2299 hdev
->hw
.mac
.phydev
->link
;
2304 link_stat
= mac_state
;
2310 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2312 struct hnae3_client
*client
= hdev
->nic_client
;
2313 struct hnae3_handle
*handle
;
2319 state
= hclge_get_mac_phy_link(hdev
);
2320 if (state
!= hdev
->hw
.mac
.link
) {
2321 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2322 handle
= &hdev
->vport
[i
].nic
;
2323 client
->ops
->link_status_change(handle
, state
);
2325 hdev
->hw
.mac
.link
= state
;
2329 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2331 struct hclge_mac mac
= hdev
->hw
.mac
;
2336 /* get the speed and duplex as autoneg'result from mac cmd when phy
2339 if (mac
.phydev
|| !mac
.autoneg
)
2342 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2344 dev_err(&hdev
->pdev
->dev
,
2345 "mac autoneg/speed/duplex query failed %d\n", ret
);
2349 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2350 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2352 dev_err(&hdev
->pdev
->dev
,
2353 "mac speed/duplex config failed %d\n", ret
);
2361 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2363 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2364 struct hclge_dev
*hdev
= vport
->back
;
2366 return hclge_update_speed_duplex(hdev
);
2369 static int hclge_get_status(struct hnae3_handle
*handle
)
2371 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2372 struct hclge_dev
*hdev
= vport
->back
;
2374 hclge_update_link_status(hdev
);
2376 return hdev
->hw
.mac
.link
;
2379 static void hclge_service_timer(struct timer_list
*t
)
2381 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2383 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2384 hclge_task_schedule(hdev
);
2387 static void hclge_service_complete(struct hclge_dev
*hdev
)
2389 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2391 /* Flush memory before next watchdog */
2392 smp_mb__before_atomic();
2393 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2396 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2401 /* fetch the events from their corresponding regs */
2402 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2403 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2405 /* Assumption: If by any chance reset and mailbox events are reported
2406 * together then we will only process reset event in this go and will
2407 * defer the processing of the mailbox events. Since, we would have not
2408 * cleared RX CMDQ event this time we would receive again another
2409 * interrupt from H/W just for the mailbox.
2412 /* check for vector0 reset event sources */
2413 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2414 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2415 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2416 return HCLGE_VECTOR0_EVENT_RST
;
2419 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2420 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2421 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2422 return HCLGE_VECTOR0_EVENT_RST
;
2425 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2426 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2427 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2428 return HCLGE_VECTOR0_EVENT_RST
;
2431 /* check for vector0 mailbox(=CMDQ RX) event source */
2432 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2433 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2434 *clearval
= cmdq_src_reg
;
2435 return HCLGE_VECTOR0_EVENT_MBX
;
2438 return HCLGE_VECTOR0_EVENT_OTHER
;
2441 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2444 switch (event_type
) {
2445 case HCLGE_VECTOR0_EVENT_RST
:
2446 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2448 case HCLGE_VECTOR0_EVENT_MBX
:
2449 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2454 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2456 writel(enable
? 1 : 0, vector
->addr
);
2459 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2461 struct hclge_dev
*hdev
= data
;
2465 hclge_enable_vector(&hdev
->misc_vector
, false);
2466 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2468 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2469 switch (event_cause
) {
2470 case HCLGE_VECTOR0_EVENT_RST
:
2471 hclge_reset_task_schedule(hdev
);
2473 case HCLGE_VECTOR0_EVENT_MBX
:
2474 /* If we are here then,
2475 * 1. Either we are not handling any mbx task and we are not
2478 * 2. We could be handling a mbx task but nothing more is
2480 * In both cases, we should schedule mbx task as there are more
2481 * mbx messages reported by this interrupt.
2483 hclge_mbx_task_schedule(hdev
);
2486 dev_dbg(&hdev
->pdev
->dev
,
2487 "received unknown or unhandled event of vector0\n");
2491 /* we should clear the source of interrupt */
2492 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2493 hclge_enable_vector(&hdev
->misc_vector
, true);
2498 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2500 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2501 hdev
->num_msi_left
+= 1;
2502 hdev
->num_msi_used
-= 1;
2505 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2507 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2509 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2511 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2512 hdev
->vector_status
[0] = 0;
2514 hdev
->num_msi_left
-= 1;
2515 hdev
->num_msi_used
+= 1;
2518 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2522 hclge_get_misc_vector(hdev
);
2524 /* this would be explicitly freed in the end */
2525 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2526 0, "hclge_misc", hdev
);
2528 hclge_free_vector(hdev
, 0);
2529 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2530 hdev
->misc_vector
.vector_irq
);
2536 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2538 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2539 hclge_free_vector(hdev
, 0);
2542 static int hclge_notify_client(struct hclge_dev
*hdev
,
2543 enum hnae3_reset_notify_type type
)
2545 struct hnae3_client
*client
= hdev
->nic_client
;
2548 if (!client
->ops
->reset_notify
)
2551 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2552 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2555 ret
= client
->ops
->reset_notify(handle
, type
);
2563 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2565 #define HCLGE_RESET_WATI_MS 100
2566 #define HCLGE_RESET_WAIT_CNT 5
2567 u32 val
, reg
, reg_bit
;
2570 switch (hdev
->reset_type
) {
2571 case HNAE3_GLOBAL_RESET
:
2572 reg
= HCLGE_GLOBAL_RESET_REG
;
2573 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2575 case HNAE3_CORE_RESET
:
2576 reg
= HCLGE_GLOBAL_RESET_REG
;
2577 reg_bit
= HCLGE_CORE_RESET_BIT
;
2579 case HNAE3_FUNC_RESET
:
2580 reg
= HCLGE_FUN_RST_ING
;
2581 reg_bit
= HCLGE_FUN_RST_ING_B
;
2584 dev_err(&hdev
->pdev
->dev
,
2585 "Wait for unsupported reset type: %d\n",
2590 val
= hclge_read_dev(&hdev
->hw
, reg
);
2591 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2592 msleep(HCLGE_RESET_WATI_MS
);
2593 val
= hclge_read_dev(&hdev
->hw
, reg
);
2597 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2598 dev_warn(&hdev
->pdev
->dev
,
2599 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2606 static int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2608 struct hclge_desc desc
;
2609 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2612 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2613 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_MAC_B
, 0);
2614 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2615 req
->fun_reset_vfid
= func_id
;
2617 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2619 dev_err(&hdev
->pdev
->dev
,
2620 "send function reset cmd fail, status =%d\n", ret
);
2625 static void hclge_do_reset(struct hclge_dev
*hdev
)
2627 struct pci_dev
*pdev
= hdev
->pdev
;
2630 switch (hdev
->reset_type
) {
2631 case HNAE3_GLOBAL_RESET
:
2632 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2633 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2634 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2635 dev_info(&pdev
->dev
, "Global Reset requested\n");
2637 case HNAE3_CORE_RESET
:
2638 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2639 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2640 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2641 dev_info(&pdev
->dev
, "Core Reset requested\n");
2643 case HNAE3_FUNC_RESET
:
2644 dev_info(&pdev
->dev
, "PF Reset requested\n");
2645 hclge_func_reset_cmd(hdev
, 0);
2646 /* schedule again to check later */
2647 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2648 hclge_reset_task_schedule(hdev
);
2651 dev_warn(&pdev
->dev
,
2652 "Unsupported reset type: %d\n", hdev
->reset_type
);
2657 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2658 unsigned long *addr
)
2660 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2662 /* return the highest priority reset level amongst all */
2663 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2664 rst_level
= HNAE3_GLOBAL_RESET
;
2665 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2666 rst_level
= HNAE3_CORE_RESET
;
2667 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2668 rst_level
= HNAE3_IMP_RESET
;
2669 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2670 rst_level
= HNAE3_FUNC_RESET
;
2672 /* now, clear all other resets */
2673 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2674 clear_bit(HNAE3_CORE_RESET
, addr
);
2675 clear_bit(HNAE3_IMP_RESET
, addr
);
2676 clear_bit(HNAE3_FUNC_RESET
, addr
);
2681 static void hclge_reset(struct hclge_dev
*hdev
)
2683 /* perform reset of the stack & ae device for a client */
2685 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2687 if (!hclge_reset_wait(hdev
)) {
2689 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2690 hclge_reset_ae_dev(hdev
->ae_dev
);
2691 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2694 /* schedule again to check pending resets later */
2695 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2696 hclge_reset_task_schedule(hdev
);
2699 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2702 static void hclge_reset_event(struct hnae3_handle
*handle
,
2703 enum hnae3_reset_type reset
)
2705 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2706 struct hclge_dev
*hdev
= vport
->back
;
2708 dev_info(&hdev
->pdev
->dev
,
2709 "Receive reset event , reset_type is %d", reset
);
2712 case HNAE3_FUNC_RESET
:
2713 case HNAE3_CORE_RESET
:
2714 case HNAE3_GLOBAL_RESET
:
2715 /* request reset & schedule reset task */
2716 set_bit(reset
, &hdev
->reset_request
);
2717 hclge_reset_task_schedule(hdev
);
2720 dev_warn(&hdev
->pdev
->dev
, "Unsupported reset event:%d", reset
);
2725 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2727 /* check if there is any ongoing reset in the hardware. This status can
2728 * be checked from reset_pending. If there is then, we need to wait for
2729 * hardware to complete reset.
2730 * a. If we are able to figure out in reasonable time that hardware
2731 * has fully resetted then, we can proceed with driver, client
2733 * b. else, we can come back later to check this status so re-sched
2736 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2737 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2740 /* check if we got any *new* reset requests to be honored */
2741 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2742 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2743 hclge_do_reset(hdev
);
2745 hdev
->reset_type
= HNAE3_NONE_RESET
;
2748 static void hclge_reset_service_task(struct work_struct
*work
)
2750 struct hclge_dev
*hdev
=
2751 container_of(work
, struct hclge_dev
, rst_service_task
);
2753 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2756 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2758 hclge_reset_subtask(hdev
);
2760 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2763 static void hclge_mailbox_service_task(struct work_struct
*work
)
2765 struct hclge_dev
*hdev
=
2766 container_of(work
, struct hclge_dev
, mbx_service_task
);
2768 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2771 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2773 hclge_mbx_handler(hdev
);
2775 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2778 static void hclge_service_task(struct work_struct
*work
)
2780 struct hclge_dev
*hdev
=
2781 container_of(work
, struct hclge_dev
, service_task
);
2783 hclge_update_speed_duplex(hdev
);
2784 hclge_update_link_status(hdev
);
2785 hclge_update_stats_for_all(hdev
);
2786 hclge_service_complete(hdev
);
2789 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2791 /* If our VFs are assigned we cannot shut down SR-IOV
2792 * without causing issues, so just leave the hardware
2793 * available but disabled
2795 if (pci_vfs_assigned(hdev
->pdev
)) {
2796 dev_warn(&hdev
->pdev
->dev
,
2797 "disabling driver while VFs are assigned\n");
2801 pci_disable_sriov(hdev
->pdev
);
2804 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2806 /* VF handle has no client */
2807 if (!handle
->client
)
2808 return container_of(handle
, struct hclge_vport
, nic
);
2809 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2810 return container_of(handle
, struct hclge_vport
, roce
);
2812 return container_of(handle
, struct hclge_vport
, nic
);
2815 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2816 struct hnae3_vector_info
*vector_info
)
2818 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2819 struct hnae3_vector_info
*vector
= vector_info
;
2820 struct hclge_dev
*hdev
= vport
->back
;
2824 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2826 for (j
= 0; j
< vector_num
; j
++) {
2827 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2828 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2829 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2830 vector
->io_addr
= hdev
->hw
.io_base
+
2831 HCLGE_VECTOR_REG_BASE
+
2832 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2834 HCLGE_VECTOR_VF_OFFSET
;
2835 hdev
->vector_status
[i
] = vport
->vport_id
;
2836 hdev
->vector_irq
[i
] = vector
->vector
;
2845 hdev
->num_msi_left
-= alloc
;
2846 hdev
->num_msi_used
+= alloc
;
2851 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2855 for (i
= 0; i
< hdev
->num_msi
; i
++)
2856 if (vector
== hdev
->vector_irq
[i
])
2862 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
2864 return HCLGE_RSS_KEY_SIZE
;
2867 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
2869 return HCLGE_RSS_IND_TBL_SIZE
;
2872 static int hclge_get_rss_algo(struct hclge_dev
*hdev
)
2874 struct hclge_rss_config_cmd
*req
;
2875 struct hclge_desc desc
;
2879 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
, true);
2881 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2883 dev_err(&hdev
->pdev
->dev
,
2884 "Get link status error, status =%d\n", ret
);
2888 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
2889 rss_hash_algo
= (req
->hash_config
& HCLGE_RSS_HASH_ALGO_MASK
);
2891 if (rss_hash_algo
== HCLGE_RSS_HASH_ALGO_TOEPLITZ
)
2892 return ETH_RSS_HASH_TOP
;
2897 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
2898 const u8 hfunc
, const u8
*key
)
2900 struct hclge_rss_config_cmd
*req
;
2901 struct hclge_desc desc
;
2906 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
2908 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
2909 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
2912 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
2913 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
2915 if (key_offset
== 2)
2917 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
2919 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
2921 memcpy(req
->hash_key
,
2922 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
2924 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2926 dev_err(&hdev
->pdev
->dev
,
2927 "Configure RSS config fail, status = %d\n",
2935 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u32
*indir
)
2937 struct hclge_rss_indirection_table_cmd
*req
;
2938 struct hclge_desc desc
;
2942 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
2944 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
2945 hclge_cmd_setup_basic_desc
2946 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
2948 req
->start_table_index
=
2949 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
2950 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
2952 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
2953 req
->rss_result
[j
] =
2954 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
2956 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2958 dev_err(&hdev
->pdev
->dev
,
2959 "Configure rss indir table fail,status = %d\n",
2967 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
2968 u16
*tc_size
, u16
*tc_offset
)
2970 struct hclge_rss_tc_mode_cmd
*req
;
2971 struct hclge_desc desc
;
2975 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
2976 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
2978 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
2981 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
2982 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
2983 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
2984 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
2985 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
2987 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
2990 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2992 dev_err(&hdev
->pdev
->dev
,
2993 "Configure rss tc mode fail, status = %d\n", ret
);
3000 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3002 struct hclge_rss_input_tuple_cmd
*req
;
3003 struct hclge_desc desc
;
3006 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3008 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3009 req
->ipv4_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3010 req
->ipv4_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3011 req
->ipv4_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
3012 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3013 req
->ipv6_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3014 req
->ipv6_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3015 req
->ipv6_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
3016 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3017 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3019 dev_err(&hdev
->pdev
->dev
,
3020 "Configure rss input fail, status = %d\n", ret
);
3027 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3030 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3031 struct hclge_dev
*hdev
= vport
->back
;
3034 /* Get hash algorithm */
3036 *hfunc
= hclge_get_rss_algo(hdev
);
3038 /* Get the RSS Key required by the user */
3040 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3042 /* Get indirect table */
3044 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3045 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3050 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3051 const u8
*key
, const u8 hfunc
)
3053 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3054 struct hclge_dev
*hdev
= vport
->back
;
3058 /* Set the RSS Hash Key if specififed by the user */
3060 /* Update the shadow RSS key with user specified qids */
3061 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3063 if (hfunc
== ETH_RSS_HASH_TOP
||
3064 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3065 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3068 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3073 /* Update the shadow RSS table with user specified qids */
3074 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3075 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3077 /* Update the hardware */
3078 ret
= hclge_set_rss_indir_table(hdev
, indir
);
3082 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3084 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3086 if (nfc
->data
& RXH_L4_B_2_3
)
3087 hash_sets
|= HCLGE_D_PORT_BIT
;
3089 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3091 if (nfc
->data
& RXH_IP_SRC
)
3092 hash_sets
|= HCLGE_S_IP_BIT
;
3094 hash_sets
&= ~HCLGE_S_IP_BIT
;
3096 if (nfc
->data
& RXH_IP_DST
)
3097 hash_sets
|= HCLGE_D_IP_BIT
;
3099 hash_sets
&= ~HCLGE_D_IP_BIT
;
3101 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3102 hash_sets
|= HCLGE_V_TAG_BIT
;
3107 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3108 struct ethtool_rxnfc
*nfc
)
3110 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3111 struct hclge_dev
*hdev
= vport
->back
;
3112 struct hclge_rss_input_tuple_cmd
*req
;
3113 struct hclge_desc desc
;
3117 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3118 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3121 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3122 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, true);
3123 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3125 dev_err(&hdev
->pdev
->dev
,
3126 "Read rss tuple fail, status = %d\n", ret
);
3130 hclge_cmd_reuse_desc(&desc
, false);
3132 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3133 switch (nfc
->flow_type
) {
3135 req
->ipv4_tcp_en
= tuple_sets
;
3138 req
->ipv6_tcp_en
= tuple_sets
;
3141 req
->ipv4_udp_en
= tuple_sets
;
3144 req
->ipv6_udp_en
= tuple_sets
;
3147 req
->ipv4_sctp_en
= tuple_sets
;
3150 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3151 (nfc
->data
& RXH_L4_B_2_3
))
3154 req
->ipv6_sctp_en
= tuple_sets
;
3157 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3160 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3166 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3168 dev_err(&hdev
->pdev
->dev
,
3169 "Set rss tuple fail, status = %d\n", ret
);
3174 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3175 struct ethtool_rxnfc
*nfc
)
3177 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3178 struct hclge_dev
*hdev
= vport
->back
;
3179 struct hclge_rss_input_tuple_cmd
*req
;
3180 struct hclge_desc desc
;
3186 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3187 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, true);
3188 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3190 dev_err(&hdev
->pdev
->dev
,
3191 "Read rss tuple fail, status = %d\n", ret
);
3195 switch (nfc
->flow_type
) {
3197 tuple_sets
= req
->ipv4_tcp_en
;
3200 tuple_sets
= req
->ipv4_udp_en
;
3203 tuple_sets
= req
->ipv6_tcp_en
;
3206 tuple_sets
= req
->ipv6_udp_en
;
3209 tuple_sets
= req
->ipv4_sctp_en
;
3212 tuple_sets
= req
->ipv6_sctp_en
;
3216 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3225 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3226 nfc
->data
|= RXH_L4_B_2_3
;
3227 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3228 nfc
->data
|= RXH_L4_B_0_1
;
3229 if (tuple_sets
& HCLGE_D_IP_BIT
)
3230 nfc
->data
|= RXH_IP_DST
;
3231 if (tuple_sets
& HCLGE_S_IP_BIT
)
3232 nfc
->data
|= RXH_IP_SRC
;
3237 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3239 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3240 struct hclge_dev
*hdev
= vport
->back
;
3242 return hdev
->rss_size_max
;
3245 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3247 const u8 hfunc
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3248 struct hclge_vport
*vport
= hdev
->vport
;
3249 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3250 u8 rss_key
[HCLGE_RSS_KEY_SIZE
];
3251 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3252 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3253 u32
*rss_indir
= NULL
;
3254 u16 rss_size
= 0, roundup_size
;
3258 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
3262 /* Get default RSS key */
3263 netdev_rss_key_fill(rss_key
, HCLGE_RSS_KEY_SIZE
);
3265 /* Initialize RSS indirect table for each vport */
3266 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3267 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++) {
3268 vport
[j
].rss_indirection_tbl
[i
] =
3269 i
% vport
[j
].alloc_rss_size
;
3271 /* vport 0 is for PF */
3275 rss_size
= vport
[j
].alloc_rss_size
;
3276 rss_indir
[i
] = vport
[j
].rss_indirection_tbl
[i
];
3279 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3284 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3288 ret
= hclge_set_rss_input_tuple(hdev
);
3292 /* Each TC have the same queue size, and tc_size set to hardware is
3293 * the log2 of roundup power of two of rss_size, the acutal queue
3294 * size is limited by indirection table.
3296 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3297 dev_err(&hdev
->pdev
->dev
,
3298 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3304 roundup_size
= roundup_pow_of_two(rss_size
);
3305 roundup_size
= ilog2(roundup_size
);
3307 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3310 if (!(hdev
->hw_tc_map
& BIT(i
)))
3314 tc_size
[i
] = roundup_size
;
3315 tc_offset
[i
] = rss_size
* i
;
3318 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3326 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3327 int vector_id
, bool en
,
3328 struct hnae3_ring_chain_node
*ring_chain
)
3330 struct hclge_dev
*hdev
= vport
->back
;
3331 struct hnae3_ring_chain_node
*node
;
3332 struct hclge_desc desc
;
3333 struct hclge_ctrl_vector_chain_cmd
*req
3334 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3335 enum hclge_cmd_status status
;
3336 enum hclge_opcode_type op
;
3337 u16 tqp_type_and_id
;
3340 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3341 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3342 req
->int_vector_id
= vector_id
;
3345 for (node
= ring_chain
; node
; node
= node
->next
) {
3346 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3347 hnae_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3349 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3350 hnae_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3351 HCLGE_TQP_ID_S
, node
->tqp_index
);
3352 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3353 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3354 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3355 req
->vfid
= vport
->vport_id
;
3357 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3359 dev_err(&hdev
->pdev
->dev
,
3360 "Map TQP fail, status is %d.\n",
3366 hclge_cmd_setup_basic_desc(&desc
,
3369 req
->int_vector_id
= vector_id
;
3374 req
->int_cause_num
= i
;
3375 req
->vfid
= vport
->vport_id
;
3376 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3378 dev_err(&hdev
->pdev
->dev
,
3379 "Map TQP fail, status is %d.\n", status
);
3387 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3389 struct hnae3_ring_chain_node
*ring_chain
)
3391 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3392 struct hclge_dev
*hdev
= vport
->back
;
3395 vector_id
= hclge_get_vector_index(hdev
, vector
);
3396 if (vector_id
< 0) {
3397 dev_err(&hdev
->pdev
->dev
,
3398 "Get vector index fail. vector_id =%d\n", vector_id
);
3402 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3405 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3407 struct hnae3_ring_chain_node
*ring_chain
)
3409 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3410 struct hclge_dev
*hdev
= vport
->back
;
3413 vector_id
= hclge_get_vector_index(hdev
, vector
);
3414 if (vector_id
< 0) {
3415 dev_err(&handle
->pdev
->dev
,
3416 "Get vector index fail. ret =%d\n", vector_id
);
3420 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3422 dev_err(&handle
->pdev
->dev
,
3423 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3429 /* Free this MSIX or MSI vector */
3430 hclge_free_vector(hdev
, vector_id
);
3435 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3436 struct hclge_promisc_param
*param
)
3438 struct hclge_promisc_cfg_cmd
*req
;
3439 struct hclge_desc desc
;
3442 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3444 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3445 req
->vf_id
= param
->vf_id
;
3446 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
3448 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3450 dev_err(&hdev
->pdev
->dev
,
3451 "Set promisc mode fail, status is %d.\n", ret
);
3457 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3458 bool en_mc
, bool en_bc
, int vport_id
)
3463 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3465 param
->enable
= HCLGE_PROMISC_EN_UC
;
3467 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3469 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3470 param
->vf_id
= vport_id
;
3473 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
3475 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3476 struct hclge_dev
*hdev
= vport
->back
;
3477 struct hclge_promisc_param param
;
3479 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
3480 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3483 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3485 struct hclge_desc desc
;
3486 struct hclge_config_mac_mode_cmd
*req
=
3487 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3491 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3492 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3493 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3494 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3495 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3496 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3497 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3498 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3499 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3500 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3501 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3502 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3503 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3504 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3505 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3506 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3508 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3510 dev_err(&hdev
->pdev
->dev
,
3511 "mac enable fail, ret =%d.\n", ret
);
3514 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3515 enum hnae3_loop loop_mode
, bool en
)
3517 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3518 struct hclge_config_mac_mode_cmd
*req
;
3519 struct hclge_dev
*hdev
= vport
->back
;
3520 struct hclge_desc desc
;
3524 switch (loop_mode
) {
3525 case HNAE3_MAC_INTER_LOOP_MAC
:
3526 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3527 /* 1 Read out the MAC mode config at first */
3528 hclge_cmd_setup_basic_desc(&desc
,
3529 HCLGE_OPC_CONFIG_MAC_MODE
,
3531 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3533 dev_err(&hdev
->pdev
->dev
,
3534 "mac loopback get fail, ret =%d.\n",
3539 /* 2 Then setup the loopback flag */
3540 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3542 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 1);
3544 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3546 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3548 /* 3 Config mac work mode with loopback flag
3549 * and its original configure parameters
3551 hclge_cmd_reuse_desc(&desc
, false);
3552 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3554 dev_err(&hdev
->pdev
->dev
,
3555 "mac loopback set fail, ret =%d.\n", ret
);
3559 dev_err(&hdev
->pdev
->dev
,
3560 "loop_mode %d is not supported\n", loop_mode
);
3567 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3568 int stream_id
, bool enable
)
3570 struct hclge_desc desc
;
3571 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3572 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3575 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3576 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3577 req
->stream_id
= cpu_to_le16(stream_id
);
3578 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3580 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3582 dev_err(&hdev
->pdev
->dev
,
3583 "Tqp enable fail, status =%d.\n", ret
);
3587 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3589 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3590 struct hnae3_queue
*queue
;
3591 struct hclge_tqp
*tqp
;
3594 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3595 queue
= handle
->kinfo
.tqp
[i
];
3596 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3597 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3601 static int hclge_ae_start(struct hnae3_handle
*handle
)
3603 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3604 struct hclge_dev
*hdev
= vport
->back
;
3605 int i
, queue_id
, ret
;
3607 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3608 /* todo clear interrupt */
3610 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
3612 dev_warn(&hdev
->pdev
->dev
,
3613 "Get invalid queue id, ignore it\n");
3617 hclge_tqp_enable(hdev
, queue_id
, 0, true);
3620 hclge_cfg_mac_mode(hdev
, true);
3621 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3622 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3624 ret
= hclge_mac_start_phy(hdev
);
3628 /* reset tqp stats */
3629 hclge_reset_tqp_stats(handle
);
3634 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3636 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3637 struct hclge_dev
*hdev
= vport
->back
;
3640 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3642 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
3644 dev_warn(&hdev
->pdev
->dev
,
3645 "Get invalid queue id, ignore it\n");
3649 hclge_tqp_enable(hdev
, queue_id
, 0, false);
3652 hclge_cfg_mac_mode(hdev
, false);
3654 hclge_mac_stop_phy(hdev
);
3656 /* reset tqp stats */
3657 hclge_reset_tqp_stats(handle
);
3660 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3661 u16 cmdq_resp
, u8 resp_code
,
3662 enum hclge_mac_vlan_tbl_opcode op
)
3664 struct hclge_dev
*hdev
= vport
->back
;
3665 int return_status
= -EIO
;
3668 dev_err(&hdev
->pdev
->dev
,
3669 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3674 if (op
== HCLGE_MAC_VLAN_ADD
) {
3675 if ((!resp_code
) || (resp_code
== 1)) {
3677 } else if (resp_code
== 2) {
3678 return_status
= -EIO
;
3679 dev_err(&hdev
->pdev
->dev
,
3680 "add mac addr failed for uc_overflow.\n");
3681 } else if (resp_code
== 3) {
3682 return_status
= -EIO
;
3683 dev_err(&hdev
->pdev
->dev
,
3684 "add mac addr failed for mc_overflow.\n");
3686 dev_err(&hdev
->pdev
->dev
,
3687 "add mac addr failed for undefined, code=%d.\n",
3690 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3693 } else if (resp_code
== 1) {
3694 return_status
= -EIO
;
3695 dev_dbg(&hdev
->pdev
->dev
,
3696 "remove mac addr failed for miss.\n");
3698 dev_err(&hdev
->pdev
->dev
,
3699 "remove mac addr failed for undefined, code=%d.\n",
3702 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3705 } else if (resp_code
== 1) {
3706 return_status
= -EIO
;
3707 dev_dbg(&hdev
->pdev
->dev
,
3708 "lookup mac addr failed for miss.\n");
3710 dev_err(&hdev
->pdev
->dev
,
3711 "lookup mac addr failed for undefined, code=%d.\n",
3715 return_status
= -EIO
;
3716 dev_err(&hdev
->pdev
->dev
,
3717 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3721 return return_status
;
3724 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3729 if (vfid
> 255 || vfid
< 0)
3732 if (vfid
>= 0 && vfid
<= 191) {
3733 word_num
= vfid
/ 32;
3734 bit_num
= vfid
% 32;
3736 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3738 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3740 word_num
= (vfid
- 192) / 32;
3741 bit_num
= vfid
% 32;
3743 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3745 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3751 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3753 #define HCLGE_DESC_NUMBER 3
3754 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3757 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3758 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3759 if (desc
[i
].data
[j
])
3765 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3768 const unsigned char *mac_addr
= addr
;
3769 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3770 (mac_addr
[0]) | (mac_addr
[1] << 8);
3771 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3773 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3774 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3777 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3780 u16 high_val
= addr
[1] | (addr
[0] << 8);
3781 struct hclge_dev
*hdev
= vport
->back
;
3782 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3783 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3788 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3789 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3792 struct hclge_mta_filter_mode_cmd
*req
;
3793 struct hclge_desc desc
;
3796 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3797 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3799 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3801 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3802 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3804 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3806 dev_err(&hdev
->pdev
->dev
,
3807 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3815 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3819 struct hclge_cfg_func_mta_filter_cmd
*req
;
3820 struct hclge_desc desc
;
3823 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3824 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3826 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3828 req
->function_id
= func_id
;
3830 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3832 dev_err(&hdev
->pdev
->dev
,
3833 "Config func_id enable failed for cmd_send, ret =%d.\n",
3841 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
3845 struct hclge_dev
*hdev
= vport
->back
;
3846 struct hclge_cfg_func_mta_item_cmd
*req
;
3847 struct hclge_desc desc
;
3851 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
3852 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
3853 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
3855 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
3856 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
3857 req
->item_idx
= cpu_to_le16(item_idx
);
3859 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3861 dev_err(&hdev
->pdev
->dev
,
3862 "Config mta table item failed for cmd_send, ret =%d.\n",
3870 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
3871 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
3873 struct hclge_dev
*hdev
= vport
->back
;
3874 struct hclge_desc desc
;
3879 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
3881 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3883 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3885 dev_err(&hdev
->pdev
->dev
,
3886 "del mac addr failed for cmd_send, ret =%d.\n",
3890 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
3891 retval
= le16_to_cpu(desc
.retval
);
3893 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
3894 HCLGE_MAC_VLAN_REMOVE
);
3897 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
3898 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
3899 struct hclge_desc
*desc
,
3902 struct hclge_dev
*hdev
= vport
->back
;
3907 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
3909 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3910 memcpy(desc
[0].data
,
3912 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3913 hclge_cmd_setup_basic_desc(&desc
[1],
3914 HCLGE_OPC_MAC_VLAN_ADD
,
3916 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3917 hclge_cmd_setup_basic_desc(&desc
[2],
3918 HCLGE_OPC_MAC_VLAN_ADD
,
3920 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
3922 memcpy(desc
[0].data
,
3924 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3925 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
3928 dev_err(&hdev
->pdev
->dev
,
3929 "lookup mac addr failed for cmd_send, ret =%d.\n",
3933 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
3934 retval
= le16_to_cpu(desc
[0].retval
);
3936 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
3937 HCLGE_MAC_VLAN_LKUP
);
3940 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
3941 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
3942 struct hclge_desc
*mc_desc
)
3944 struct hclge_dev
*hdev
= vport
->back
;
3951 struct hclge_desc desc
;
3953 hclge_cmd_setup_basic_desc(&desc
,
3954 HCLGE_OPC_MAC_VLAN_ADD
,
3956 memcpy(desc
.data
, req
,
3957 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3958 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3959 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
3960 retval
= le16_to_cpu(desc
.retval
);
3962 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
3964 HCLGE_MAC_VLAN_ADD
);
3966 hclge_cmd_reuse_desc(&mc_desc
[0], false);
3967 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3968 hclge_cmd_reuse_desc(&mc_desc
[1], false);
3969 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3970 hclge_cmd_reuse_desc(&mc_desc
[2], false);
3971 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
3972 memcpy(mc_desc
[0].data
, req
,
3973 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3974 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
3975 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
3976 retval
= le16_to_cpu(mc_desc
[0].retval
);
3978 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
3980 HCLGE_MAC_VLAN_ADD
);
3984 dev_err(&hdev
->pdev
->dev
,
3985 "add mac addr failed for cmd_send, ret =%d.\n",
3993 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
3994 const unsigned char *addr
)
3996 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3998 return hclge_add_uc_addr_common(vport
, addr
);
4001 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4002 const unsigned char *addr
)
4004 struct hclge_dev
*hdev
= vport
->back
;
4005 struct hclge_mac_vlan_tbl_entry_cmd req
;
4006 enum hclge_cmd_status status
;
4007 u16 egress_port
= 0;
4009 /* mac addr check */
4010 if (is_zero_ether_addr(addr
) ||
4011 is_broadcast_ether_addr(addr
) ||
4012 is_multicast_ether_addr(addr
)) {
4013 dev_err(&hdev
->pdev
->dev
,
4014 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4016 is_zero_ether_addr(addr
),
4017 is_broadcast_ether_addr(addr
),
4018 is_multicast_ether_addr(addr
));
4022 memset(&req
, 0, sizeof(req
));
4023 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4024 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4025 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
4026 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4028 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_SW_EN_B
, 0);
4029 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_TYPE_B
, 0);
4030 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4031 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4032 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_PFID_M
,
4033 HCLGE_MAC_EPORT_PFID_S
, 0);
4035 req
.egress_port
= cpu_to_le16(egress_port
);
4037 hclge_prepare_mac_addr(&req
, addr
);
4039 status
= hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4044 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4045 const unsigned char *addr
)
4047 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4049 return hclge_rm_uc_addr_common(vport
, addr
);
4052 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4053 const unsigned char *addr
)
4055 struct hclge_dev
*hdev
= vport
->back
;
4056 struct hclge_mac_vlan_tbl_entry_cmd req
;
4057 enum hclge_cmd_status status
;
4059 /* mac addr check */
4060 if (is_zero_ether_addr(addr
) ||
4061 is_broadcast_ether_addr(addr
) ||
4062 is_multicast_ether_addr(addr
)) {
4063 dev_dbg(&hdev
->pdev
->dev
,
4064 "Remove mac err! invalid mac:%pM.\n",
4069 memset(&req
, 0, sizeof(req
));
4070 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4071 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4072 hclge_prepare_mac_addr(&req
, addr
);
4073 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4078 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4079 const unsigned char *addr
)
4081 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4083 return hclge_add_mc_addr_common(vport
, addr
);
4086 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4087 const unsigned char *addr
)
4089 struct hclge_dev
*hdev
= vport
->back
;
4090 struct hclge_mac_vlan_tbl_entry_cmd req
;
4091 struct hclge_desc desc
[3];
4095 /* mac addr check */
4096 if (!is_multicast_ether_addr(addr
)) {
4097 dev_err(&hdev
->pdev
->dev
,
4098 "Add mc mac err! invalid mac:%pM.\n",
4102 memset(&req
, 0, sizeof(req
));
4103 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4104 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4105 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4106 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4107 hclge_prepare_mac_addr(&req
, addr
);
4108 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4110 /* This mac addr exist, update VFID for it */
4111 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4112 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4114 /* This mac addr do not exist, add new entry for it */
4115 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4116 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4117 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4118 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4119 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4122 /* Set MTA table for this MAC address */
4123 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4124 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4129 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4130 const unsigned char *addr
)
4132 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4134 return hclge_rm_mc_addr_common(vport
, addr
);
4137 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4138 const unsigned char *addr
)
4140 struct hclge_dev
*hdev
= vport
->back
;
4141 struct hclge_mac_vlan_tbl_entry_cmd req
;
4142 enum hclge_cmd_status status
;
4143 struct hclge_desc desc
[3];
4146 /* mac addr check */
4147 if (!is_multicast_ether_addr(addr
)) {
4148 dev_dbg(&hdev
->pdev
->dev
,
4149 "Remove mc mac err! invalid mac:%pM.\n",
4154 memset(&req
, 0, sizeof(req
));
4155 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4156 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4157 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4158 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4159 hclge_prepare_mac_addr(&req
, addr
);
4160 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4162 /* This mac addr exist, remove this handle's VFID for it */
4163 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4165 if (hclge_is_all_function_id_zero(desc
))
4166 /* All the vfid is zero, so need to delete this entry */
4167 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4169 /* Not all the vfid is zero, update the vfid */
4170 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4173 /* This mac addr do not exist, can't delete it */
4174 dev_err(&hdev
->pdev
->dev
,
4175 "Rm multicast mac addr failed, ret = %d.\n",
4180 /* Set MTB table for this MAC address */
4181 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4182 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
4187 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4189 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4190 struct hclge_dev
*hdev
= vport
->back
;
4192 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4195 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
)
4197 const unsigned char *new_addr
= (const unsigned char *)p
;
4198 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4199 struct hclge_dev
*hdev
= vport
->back
;
4201 /* mac addr check */
4202 if (is_zero_ether_addr(new_addr
) ||
4203 is_broadcast_ether_addr(new_addr
) ||
4204 is_multicast_ether_addr(new_addr
)) {
4205 dev_err(&hdev
->pdev
->dev
,
4206 "Change uc mac err! invalid mac:%p.\n",
4211 hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
);
4213 if (!hclge_add_uc_addr(handle
, new_addr
)) {
4214 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4221 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4224 struct hclge_vlan_filter_ctrl_cmd
*req
;
4225 struct hclge_desc desc
;
4228 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4230 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4231 req
->vlan_type
= vlan_type
;
4232 req
->vlan_fe
= filter_en
;
4234 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4236 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4244 #define HCLGE_FILTER_TYPE_VF 0
4245 #define HCLGE_FILTER_TYPE_PORT 1
4247 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4249 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4250 struct hclge_dev
*hdev
= vport
->back
;
4252 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4255 int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4256 bool is_kill
, u16 vlan
, u8 qos
, __be16 proto
)
4258 #define HCLGE_MAX_VF_BYTES 16
4259 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4260 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4261 struct hclge_desc desc
[2];
4266 hclge_cmd_setup_basic_desc(&desc
[0],
4267 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4268 hclge_cmd_setup_basic_desc(&desc
[1],
4269 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4271 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4273 vf_byte_off
= vfid
/ 8;
4274 vf_byte_val
= 1 << (vfid
% 8);
4276 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4277 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4279 req0
->vlan_id
= cpu_to_le16(vlan
);
4280 req0
->vlan_cfg
= is_kill
;
4282 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4283 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4285 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4287 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4289 dev_err(&hdev
->pdev
->dev
,
4290 "Send vf vlan command fail, ret =%d.\n",
4296 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4299 dev_err(&hdev
->pdev
->dev
,
4300 "Add vf vlan filter fail, ret =%d.\n",
4303 if (!req0
->resp_code
)
4306 dev_err(&hdev
->pdev
->dev
,
4307 "Kill vf vlan filter fail, ret =%d.\n",
4314 static int hclge_set_port_vlan_filter(struct hnae3_handle
*handle
,
4315 __be16 proto
, u16 vlan_id
,
4318 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4319 struct hclge_dev
*hdev
= vport
->back
;
4320 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4321 struct hclge_desc desc
;
4322 u8 vlan_offset_byte_val
;
4323 u8 vlan_offset_byte
;
4327 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4329 vlan_offset_160
= vlan_id
/ 160;
4330 vlan_offset_byte
= (vlan_id
% 160) / 8;
4331 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4333 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4334 req
->vlan_offset
= vlan_offset_160
;
4335 req
->vlan_cfg
= is_kill
;
4336 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4338 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4340 dev_err(&hdev
->pdev
->dev
,
4341 "port vlan command, send fail, ret =%d.\n",
4346 ret
= hclge_set_vf_vlan_common(hdev
, 0, is_kill
, vlan_id
, 0, proto
);
4348 dev_err(&hdev
->pdev
->dev
,
4349 "Set pf vlan filter config fail, ret =%d.\n",
4357 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4358 u16 vlan
, u8 qos
, __be16 proto
)
4360 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4361 struct hclge_dev
*hdev
= vport
->back
;
4363 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4365 if (proto
!= htons(ETH_P_8021Q
))
4366 return -EPROTONOSUPPORT
;
4368 return hclge_set_vf_vlan_common(hdev
, vfid
, false, vlan
, qos
, proto
);
4371 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4373 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4374 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4375 struct hclge_dev
*hdev
= vport
->back
;
4376 struct hclge_desc desc
;
4379 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4381 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4382 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4383 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4384 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG_B
,
4385 vcfg
->accept_tag
? 1 : 0);
4386 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG_B
,
4387 vcfg
->accept_untag
? 1 : 0);
4388 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4389 vcfg
->insert_tag1_en
? 1 : 0);
4390 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4391 vcfg
->insert_tag2_en
? 1 : 0);
4392 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4394 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4395 req
->vf_bitmap
[req
->vf_offset
] =
4396 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4398 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4400 dev_err(&hdev
->pdev
->dev
,
4401 "Send port txvlan cfg command fail, ret =%d\n",
4407 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4409 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4410 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4411 struct hclge_dev
*hdev
= vport
->back
;
4412 struct hclge_desc desc
;
4415 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4417 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4418 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4419 vcfg
->strip_tag1_en
? 1 : 0);
4420 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4421 vcfg
->strip_tag2_en
? 1 : 0);
4422 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4423 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4424 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4425 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4427 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4428 req
->vf_bitmap
[req
->vf_offset
] =
4429 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4431 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4433 dev_err(&hdev
->pdev
->dev
,
4434 "Send port rxvlan cfg command fail, ret =%d\n",
4440 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4442 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4443 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4444 struct hclge_desc desc
;
4447 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4448 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4449 rx_req
->ot_fst_vlan_type
=
4450 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4451 rx_req
->ot_sec_vlan_type
=
4452 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4453 rx_req
->in_fst_vlan_type
=
4454 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4455 rx_req
->in_sec_vlan_type
=
4456 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4458 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4460 dev_err(&hdev
->pdev
->dev
,
4461 "Send rxvlan protocol type command fail, ret =%d\n",
4466 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4468 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4469 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4470 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4472 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4474 dev_err(&hdev
->pdev
->dev
,
4475 "Send txvlan protocol type command fail, ret =%d\n",
4481 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4483 #define HCLGE_DEF_VLAN_TYPE 0x8100
4485 struct hnae3_handle
*handle
;
4486 struct hclge_vport
*vport
;
4490 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4494 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4498 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4499 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4500 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4501 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4502 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4503 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4505 ret
= hclge_set_vlan_protocol_type(hdev
);
4509 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4510 vport
= &hdev
->vport
[i
];
4511 vport
->txvlan_cfg
.accept_tag
= true;
4512 vport
->txvlan_cfg
.accept_untag
= true;
4513 vport
->txvlan_cfg
.insert_tag1_en
= false;
4514 vport
->txvlan_cfg
.insert_tag2_en
= false;
4515 vport
->txvlan_cfg
.default_tag1
= 0;
4516 vport
->txvlan_cfg
.default_tag2
= 0;
4518 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4522 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4523 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4524 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4525 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4527 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4532 handle
= &hdev
->vport
[0].nic
;
4533 return hclge_set_port_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4536 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4538 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4540 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4541 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4542 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4543 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4545 return hclge_set_vlan_rx_offload_cfg(vport
);
4548 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4550 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4551 struct hclge_config_max_frm_size_cmd
*req
;
4552 struct hclge_dev
*hdev
= vport
->back
;
4553 struct hclge_desc desc
;
4556 if ((new_mtu
< HCLGE_MAC_MIN_MTU
) || (new_mtu
> HCLGE_MAC_MAX_MTU
))
4559 hdev
->mps
= new_mtu
;
4560 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4562 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4563 req
->max_frm_size
= cpu_to_le16(new_mtu
);
4565 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4567 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4574 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
4577 struct hclge_reset_tqp_queue_cmd
*req
;
4578 struct hclge_desc desc
;
4581 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
4583 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4584 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4585 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
4587 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4589 dev_err(&hdev
->pdev
->dev
,
4590 "Send tqp reset cmd error, status =%d\n", ret
);
4597 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
4599 struct hclge_reset_tqp_queue_cmd
*req
;
4600 struct hclge_desc desc
;
4603 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
4605 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4606 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4608 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4610 dev_err(&hdev
->pdev
->dev
,
4611 "Get reset status error, status =%d\n", ret
);
4615 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
4618 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
4620 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4621 struct hclge_dev
*hdev
= vport
->back
;
4622 int reset_try_times
= 0;
4626 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
4628 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
4632 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, true);
4634 dev_warn(&hdev
->pdev
->dev
,
4635 "Send reset tqp cmd fail, ret = %d\n", ret
);
4639 reset_try_times
= 0;
4640 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
4641 /* Wait for tqp hw reset */
4643 reset_status
= hclge_get_reset_status(hdev
, queue_id
);
4648 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
4649 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
4653 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, false);
4655 dev_warn(&hdev
->pdev
->dev
,
4656 "Deassert the soft reset fail, ret = %d\n", ret
);
4661 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
4663 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4664 struct hclge_dev
*hdev
= vport
->back
;
4666 return hdev
->fw_version
;
4669 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
4672 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4673 struct hclge_dev
*hdev
= vport
->back
;
4674 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4679 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
4680 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
4683 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
4685 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4690 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
4693 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
4696 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
4699 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
4701 enum hclge_fc_mode fc_mode
;
4705 fc_mode
= HCLGE_FC_FULL
;
4706 else if (rx_en
&& !tx_en
)
4707 fc_mode
= HCLGE_FC_RX_PAUSE
;
4708 else if (!rx_en
&& tx_en
)
4709 fc_mode
= HCLGE_FC_TX_PAUSE
;
4711 fc_mode
= HCLGE_FC_NONE
;
4713 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
4714 hdev
->fc_mode_last_time
= fc_mode
;
4718 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
4720 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
4725 hdev
->tm_info
.fc_mode
= fc_mode
;
4730 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
4732 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4733 u16 remote_advertising
= 0;
4734 u16 local_advertising
= 0;
4735 u32 rx_pause
, tx_pause
;
4738 if (!phydev
->link
|| !phydev
->autoneg
)
4741 if (phydev
->advertising
& ADVERTISED_Pause
)
4742 local_advertising
= ADVERTISE_PAUSE_CAP
;
4744 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
4745 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
4748 remote_advertising
= LPA_PAUSE_CAP
;
4750 if (phydev
->asym_pause
)
4751 remote_advertising
|= LPA_PAUSE_ASYM
;
4753 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
4754 remote_advertising
);
4755 tx_pause
= flowctl
& FLOW_CTRL_TX
;
4756 rx_pause
= flowctl
& FLOW_CTRL_RX
;
4758 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
4763 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
4766 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
4767 u32
*rx_en
, u32
*tx_en
)
4769 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4770 struct hclge_dev
*hdev
= vport
->back
;
4772 *auto_neg
= hclge_get_autoneg(handle
);
4774 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
4780 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
4783 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
4786 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
4795 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
4796 u32 rx_en
, u32 tx_en
)
4798 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4799 struct hclge_dev
*hdev
= vport
->back
;
4800 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4803 /* Only support flow control negotiation for netdev with
4804 * phy attached for now.
4809 fc_autoneg
= hclge_get_autoneg(handle
);
4810 if (auto_neg
!= fc_autoneg
) {
4811 dev_info(&hdev
->pdev
->dev
,
4812 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
4816 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
4817 dev_info(&hdev
->pdev
->dev
,
4818 "Priority flow control enabled. Cannot set link flow control.\n");
4822 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
4825 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
4827 return phy_start_aneg(phydev
);
4830 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
4831 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
4833 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4834 struct hclge_dev
*hdev
= vport
->back
;
4837 *speed
= hdev
->hw
.mac
.speed
;
4839 *duplex
= hdev
->hw
.mac
.duplex
;
4841 *auto_neg
= hdev
->hw
.mac
.autoneg
;
4844 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
4846 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4847 struct hclge_dev
*hdev
= vport
->back
;
4850 *media_type
= hdev
->hw
.mac
.media_type
;
4853 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
4854 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
4856 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4857 struct hclge_dev
*hdev
= vport
->back
;
4858 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4859 int mdix_ctrl
, mdix
, retval
, is_resolved
;
4862 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
4863 *tp_mdix
= ETH_TP_MDI_INVALID
;
4867 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
4869 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
4870 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
4871 HCLGE_PHY_MDIX_CTRL_S
);
4873 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
4874 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
4875 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
4877 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
4879 switch (mdix_ctrl
) {
4881 *tp_mdix_ctrl
= ETH_TP_MDI
;
4884 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
4887 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
4890 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
4895 *tp_mdix
= ETH_TP_MDI_INVALID
;
4897 *tp_mdix
= ETH_TP_MDI_X
;
4899 *tp_mdix
= ETH_TP_MDI
;
4902 static int hclge_init_client_instance(struct hnae3_client
*client
,
4903 struct hnae3_ae_dev
*ae_dev
)
4905 struct hclge_dev
*hdev
= ae_dev
->priv
;
4906 struct hclge_vport
*vport
;
4909 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4910 vport
= &hdev
->vport
[i
];
4912 switch (client
->type
) {
4913 case HNAE3_CLIENT_KNIC
:
4915 hdev
->nic_client
= client
;
4916 vport
->nic
.client
= client
;
4917 ret
= client
->ops
->init_instance(&vport
->nic
);
4921 if (hdev
->roce_client
&&
4922 hnae3_dev_roce_supported(hdev
)) {
4923 struct hnae3_client
*rc
= hdev
->roce_client
;
4925 ret
= hclge_init_roce_base_info(vport
);
4929 ret
= rc
->ops
->init_instance(&vport
->roce
);
4935 case HNAE3_CLIENT_UNIC
:
4936 hdev
->nic_client
= client
;
4937 vport
->nic
.client
= client
;
4939 ret
= client
->ops
->init_instance(&vport
->nic
);
4944 case HNAE3_CLIENT_ROCE
:
4945 if (hnae3_dev_roce_supported(hdev
)) {
4946 hdev
->roce_client
= client
;
4947 vport
->roce
.client
= client
;
4950 if (hdev
->roce_client
&& hdev
->nic_client
) {
4951 ret
= hclge_init_roce_base_info(vport
);
4955 ret
= client
->ops
->init_instance(&vport
->roce
);
4967 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
4968 struct hnae3_ae_dev
*ae_dev
)
4970 struct hclge_dev
*hdev
= ae_dev
->priv
;
4971 struct hclge_vport
*vport
;
4974 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4975 vport
= &hdev
->vport
[i
];
4976 if (hdev
->roce_client
) {
4977 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
4979 hdev
->roce_client
= NULL
;
4980 vport
->roce
.client
= NULL
;
4982 if (client
->type
== HNAE3_CLIENT_ROCE
)
4984 if (client
->ops
->uninit_instance
) {
4985 client
->ops
->uninit_instance(&vport
->nic
, 0);
4986 hdev
->nic_client
= NULL
;
4987 vport
->nic
.client
= NULL
;
4992 static int hclge_pci_init(struct hclge_dev
*hdev
)
4994 struct pci_dev
*pdev
= hdev
->pdev
;
4995 struct hclge_hw
*hw
;
4998 ret
= pci_enable_device(pdev
);
5000 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5001 goto err_no_drvdata
;
5004 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5006 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5009 "can't set consistent PCI DMA");
5010 goto err_disable_device
;
5012 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5015 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5017 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5018 goto err_disable_device
;
5021 pci_set_master(pdev
);
5024 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5026 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5028 goto err_clr_master
;
5031 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5035 pci_clear_master(pdev
);
5036 pci_release_regions(pdev
);
5038 pci_disable_device(pdev
);
5040 pci_set_drvdata(pdev
, NULL
);
5045 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5047 struct pci_dev
*pdev
= hdev
->pdev
;
5049 pci_free_irq_vectors(pdev
);
5050 pci_clear_master(pdev
);
5051 pci_release_mem_regions(pdev
);
5052 pci_disable_device(pdev
);
5055 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5057 struct pci_dev
*pdev
= ae_dev
->pdev
;
5058 struct hclge_dev
*hdev
;
5061 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5068 hdev
->ae_dev
= ae_dev
;
5069 hdev
->reset_type
= HNAE3_NONE_RESET
;
5070 hdev
->reset_request
= 0;
5071 hdev
->reset_pending
= 0;
5072 ae_dev
->priv
= hdev
;
5074 ret
= hclge_pci_init(hdev
);
5076 dev_err(&pdev
->dev
, "PCI init failed\n");
5080 /* Firmware command queue initialize */
5081 ret
= hclge_cmd_queue_init(hdev
);
5083 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5087 /* Firmware command initialize */
5088 ret
= hclge_cmd_init(hdev
);
5092 ret
= hclge_get_cap(hdev
);
5094 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5099 ret
= hclge_configure(hdev
);
5101 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5105 ret
= hclge_init_msi(hdev
);
5107 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5111 ret
= hclge_misc_irq_init(hdev
);
5114 "Misc IRQ(vector0) init error, ret = %d.\n",
5119 ret
= hclge_alloc_tqps(hdev
);
5121 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5125 ret
= hclge_alloc_vport(hdev
);
5127 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5131 ret
= hclge_map_tqp(hdev
);
5133 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5137 ret
= hclge_mac_mdio_config(hdev
);
5139 dev_warn(&hdev
->pdev
->dev
,
5140 "mdio config fail ret=%d\n", ret
);
5144 ret
= hclge_mac_init(hdev
);
5146 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5149 ret
= hclge_buffer_alloc(hdev
);
5151 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
5155 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5157 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5161 ret
= hclge_init_vlan_config(hdev
);
5163 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5167 ret
= hclge_tm_schd_init(hdev
);
5169 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5173 ret
= hclge_rss_init_hw(hdev
);
5175 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5179 hclge_dcb_ops_set(hdev
);
5181 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5182 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5183 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5184 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5186 /* Enable MISC vector(vector0) */
5187 hclge_enable_vector(&hdev
->misc_vector
, true);
5189 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5190 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5191 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5192 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5193 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5194 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5196 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5200 pci_release_regions(pdev
);
5202 pci_set_drvdata(pdev
, NULL
);
5207 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5209 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5212 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5214 struct hclge_dev
*hdev
= ae_dev
->priv
;
5215 struct pci_dev
*pdev
= ae_dev
->pdev
;
5218 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5220 hclge_stats_clear(hdev
);
5222 ret
= hclge_cmd_init(hdev
);
5224 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5228 ret
= hclge_get_cap(hdev
);
5230 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5235 ret
= hclge_configure(hdev
);
5237 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5241 ret
= hclge_map_tqp(hdev
);
5243 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5247 ret
= hclge_mac_init(hdev
);
5249 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5253 ret
= hclge_buffer_alloc(hdev
);
5255 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
5259 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5261 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5265 ret
= hclge_init_vlan_config(hdev
);
5267 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5271 ret
= hclge_tm_schd_init(hdev
);
5273 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5277 ret
= hclge_rss_init_hw(hdev
);
5279 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5283 /* Enable MISC vector(vector0) */
5284 hclge_enable_vector(&hdev
->misc_vector
, true);
5286 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5292 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5294 struct hclge_dev
*hdev
= ae_dev
->priv
;
5295 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5297 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5299 if (IS_ENABLED(CONFIG_PCI_IOV
))
5300 hclge_disable_sriov(hdev
);
5302 if (hdev
->service_timer
.function
)
5303 del_timer_sync(&hdev
->service_timer
);
5304 if (hdev
->service_task
.func
)
5305 cancel_work_sync(&hdev
->service_task
);
5306 if (hdev
->rst_service_task
.func
)
5307 cancel_work_sync(&hdev
->rst_service_task
);
5308 if (hdev
->mbx_service_task
.func
)
5309 cancel_work_sync(&hdev
->mbx_service_task
);
5312 mdiobus_unregister(mac
->mdio_bus
);
5314 /* Disable MISC vector(vector0) */
5315 hclge_enable_vector(&hdev
->misc_vector
, false);
5316 hclge_destroy_cmd_queue(&hdev
->hw
);
5317 hclge_misc_irq_uninit(hdev
);
5318 hclge_pci_uninit(hdev
);
5319 ae_dev
->priv
= NULL
;
5322 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5324 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5325 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5326 struct hclge_dev
*hdev
= vport
->back
;
5328 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5331 static void hclge_get_channels(struct hnae3_handle
*handle
,
5332 struct ethtool_channels
*ch
)
5334 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5336 ch
->max_combined
= hclge_get_max_channels(handle
);
5337 ch
->other_count
= 1;
5339 ch
->combined_count
= vport
->alloc_tqps
;
5342 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5343 u16
*free_tqps
, u16
*max_rss_size
)
5345 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5346 struct hclge_dev
*hdev
= vport
->back
;
5350 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5351 if (!hdev
->htqp
[i
].alloced
)
5354 *free_tqps
= temp_tqps
;
5355 *max_rss_size
= hdev
->rss_size_max
;
5358 static void hclge_release_tqp(struct hclge_vport
*vport
)
5360 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5361 struct hclge_dev
*hdev
= vport
->back
;
5364 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5365 struct hclge_tqp
*tqp
=
5366 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5368 tqp
->q
.handle
= NULL
;
5369 tqp
->q
.tqp_index
= 0;
5370 tqp
->alloced
= false;
5373 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5377 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5379 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5380 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5381 struct hclge_dev
*hdev
= vport
->back
;
5382 int cur_rss_size
= kinfo
->rss_size
;
5383 int cur_tqps
= kinfo
->num_tqps
;
5384 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5385 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5386 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5391 hclge_release_tqp(vport
);
5393 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5395 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5399 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5401 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5405 ret
= hclge_tm_schd_init(hdev
);
5407 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5411 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5412 roundup_size
= ilog2(roundup_size
);
5413 /* Set the RSS TC mode according to the new RSS size */
5414 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5417 if (!(hdev
->hw_tc_map
& BIT(i
)))
5421 tc_size
[i
] = roundup_size
;
5422 tc_offset
[i
] = kinfo
->rss_size
* i
;
5424 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5428 /* Reinitializes the rss indirect table according to the new RSS size */
5429 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5433 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5434 rss_indir
[i
] = i
% kinfo
->rss_size
;
5436 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5438 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5444 dev_info(&hdev
->pdev
->dev
,
5445 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5446 cur_rss_size
, kinfo
->rss_size
,
5447 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5452 static const struct hnae3_ae_ops hclge_ops
= {
5453 .init_ae_dev
= hclge_init_ae_dev
,
5454 .uninit_ae_dev
= hclge_uninit_ae_dev
,
5455 .init_client_instance
= hclge_init_client_instance
,
5456 .uninit_client_instance
= hclge_uninit_client_instance
,
5457 .map_ring_to_vector
= hclge_map_ring_to_vector
,
5458 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
5459 .get_vector
= hclge_get_vector
,
5460 .set_promisc_mode
= hclge_set_promisc_mode
,
5461 .set_loopback
= hclge_set_loopback
,
5462 .start
= hclge_ae_start
,
5463 .stop
= hclge_ae_stop
,
5464 .get_status
= hclge_get_status
,
5465 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
5466 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
5467 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
5468 .get_media_type
= hclge_get_media_type
,
5469 .get_rss_key_size
= hclge_get_rss_key_size
,
5470 .get_rss_indir_size
= hclge_get_rss_indir_size
,
5471 .get_rss
= hclge_get_rss
,
5472 .set_rss
= hclge_set_rss
,
5473 .set_rss_tuple
= hclge_set_rss_tuple
,
5474 .get_rss_tuple
= hclge_get_rss_tuple
,
5475 .get_tc_size
= hclge_get_tc_size
,
5476 .get_mac_addr
= hclge_get_mac_addr
,
5477 .set_mac_addr
= hclge_set_mac_addr
,
5478 .add_uc_addr
= hclge_add_uc_addr
,
5479 .rm_uc_addr
= hclge_rm_uc_addr
,
5480 .add_mc_addr
= hclge_add_mc_addr
,
5481 .rm_mc_addr
= hclge_rm_mc_addr
,
5482 .set_autoneg
= hclge_set_autoneg
,
5483 .get_autoneg
= hclge_get_autoneg
,
5484 .get_pauseparam
= hclge_get_pauseparam
,
5485 .set_pauseparam
= hclge_set_pauseparam
,
5486 .set_mtu
= hclge_set_mtu
,
5487 .reset_queue
= hclge_reset_tqp
,
5488 .get_stats
= hclge_get_stats
,
5489 .update_stats
= hclge_update_stats
,
5490 .get_strings
= hclge_get_strings
,
5491 .get_sset_count
= hclge_get_sset_count
,
5492 .get_fw_version
= hclge_get_fw_version
,
5493 .get_mdix_mode
= hclge_get_mdix_mode
,
5494 .enable_vlan_filter
= hclge_enable_vlan_filter
,
5495 .set_vlan_filter
= hclge_set_port_vlan_filter
,
5496 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
5497 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
5498 .reset_event
= hclge_reset_event
,
5499 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
5500 .set_channels
= hclge_set_channels
,
5501 .get_channels
= hclge_get_channels
,
5502 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
5505 static struct hnae3_ae_algo ae_algo
= {
5508 .pdev_id_table
= ae_algo_pci_tbl
,
5511 static int hclge_init(void)
5513 pr_info("%s is initializing\n", HCLGE_NAME
);
5515 return hnae3_register_ae_algo(&ae_algo
);
5518 static void hclge_exit(void)
5520 hnae3_unregister_ae_algo(&ae_algo
);
5522 module_init(hclge_init
);
5523 module_exit(hclge_exit
);
5525 MODULE_LICENSE("GPL");
5526 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5527 MODULE_DESCRIPTION("HCLGE Driver");
5528 MODULE_VERSION(HCLGE_MOD_VERSION
);