2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
43 static struct hnae3_ae_algo ae_algo
;
45 static const struct pci_device_id ae_algo_pci_tbl
[] = {
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
53 /* required last entry */
57 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
59 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
61 "Serdes Loopback test",
65 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
104 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
229 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
393 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
395 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
396 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
397 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap
= 0x1,
403 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
405 #define HCLGE_64_BIT_CMD_NUM 5
406 #define HCLGE_64_BIT_RTN_DATANUM 4
407 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
408 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
413 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
414 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
416 dev_err(&hdev
->pdev
->dev
,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
421 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
422 if (unlikely(i
== 0)) {
423 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
424 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
426 desc_data
= (__le64
*)(&desc
[i
]);
427 n
= HCLGE_64_BIT_RTN_DATANUM
;
429 for (k
= 0; k
< n
; k
++) {
430 *data
++ += le64_to_cpu(*desc_data
);
438 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
440 stats
->pkt_curr_buf_cnt
= 0;
441 stats
->pkt_curr_buf_tc0_cnt
= 0;
442 stats
->pkt_curr_buf_tc1_cnt
= 0;
443 stats
->pkt_curr_buf_tc2_cnt
= 0;
444 stats
->pkt_curr_buf_tc3_cnt
= 0;
445 stats
->pkt_curr_buf_tc4_cnt
= 0;
446 stats
->pkt_curr_buf_tc5_cnt
= 0;
447 stats
->pkt_curr_buf_tc6_cnt
= 0;
448 stats
->pkt_curr_buf_tc7_cnt
= 0;
451 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
453 #define HCLGE_32_BIT_CMD_NUM 8
454 #define HCLGE_32_BIT_RTN_DATANUM 8
456 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
457 struct hclge_32_bit_stats
*all_32_bit_stats
;
463 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
464 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
466 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
467 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
469 dev_err(&hdev
->pdev
->dev
,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
475 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
476 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
477 if (unlikely(i
== 0)) {
478 __le16
*desc_data_16bit
;
480 all_32_bit_stats
->igu_rx_err_pkt
+=
481 le32_to_cpu(desc
[i
].data
[0]);
483 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
484 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
485 le16_to_cpu(*desc_data_16bit
);
488 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
489 le16_to_cpu(*desc_data_16bit
);
491 desc_data
= &desc
[i
].data
[2];
492 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
494 desc_data
= (__le32
*)&desc
[i
];
495 n
= HCLGE_32_BIT_RTN_DATANUM
;
497 for (k
= 0; k
< n
; k
++) {
498 *data
++ += le32_to_cpu(*desc_data
);
506 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
508 #define HCLGE_MAC_CMD_NUM 21
509 #define HCLGE_RTN_DATA_NUM 4
511 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
512 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
517 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
518 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
520 dev_err(&hdev
->pdev
->dev
,
521 "Get MAC pkt stats fail, status = %d.\n", ret
);
526 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
527 if (unlikely(i
== 0)) {
528 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
529 n
= HCLGE_RTN_DATA_NUM
- 2;
531 desc_data
= (__le64
*)(&desc
[i
]);
532 n
= HCLGE_RTN_DATA_NUM
;
534 for (k
= 0; k
< n
; k
++) {
535 *data
++ += le64_to_cpu(*desc_data
);
543 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
545 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
546 struct hclge_vport
*vport
= hclge_get_vport(handle
);
547 struct hclge_dev
*hdev
= vport
->back
;
548 struct hnae3_queue
*queue
;
549 struct hclge_desc desc
[1];
550 struct hclge_tqp
*tqp
;
553 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
554 queue
= handle
->kinfo
.tqp
[i
];
555 tqp
= container_of(queue
, struct hclge_tqp
, q
);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc
[0],
558 HCLGE_OPC_QUERY_RX_STATUS
,
561 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
562 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
564 dev_err(&hdev
->pdev
->dev
,
565 "Query tqp stat fail, status = %d,queue = %d\n",
569 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
570 le32_to_cpu(desc
[0].data
[1]);
573 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
574 queue
= handle
->kinfo
.tqp
[i
];
575 tqp
= container_of(queue
, struct hclge_tqp
, q
);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc
[0],
578 HCLGE_OPC_QUERY_TX_STATUS
,
581 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
582 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
584 dev_err(&hdev
->pdev
->dev
,
585 "Query tqp stat fail, status = %d,queue = %d\n",
589 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
590 le32_to_cpu(desc
[0].data
[1]);
596 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
598 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
599 struct hclge_tqp
*tqp
;
603 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
604 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
605 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
608 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
609 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
610 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
616 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
618 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
620 return kinfo
->num_tqps
* (2);
623 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
625 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
629 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
630 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
631 struct hclge_tqp
, q
);
632 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
634 buff
= buff
+ ETH_GSTRING_LEN
;
637 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
638 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
639 struct hclge_tqp
, q
);
640 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
642 buff
= buff
+ ETH_GSTRING_LEN
;
648 static u64
*hclge_comm_get_stats(void *comm_stats
,
649 const struct hclge_comm_stats_str strs
[],
655 for (i
= 0; i
< size
; i
++)
656 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
661 static u8
*hclge_comm_get_strings(u32 stringset
,
662 const struct hclge_comm_stats_str strs
[],
665 char *buff
= (char *)data
;
668 if (stringset
!= ETH_SS_STATS
)
671 for (i
= 0; i
< size
; i
++) {
672 snprintf(buff
, ETH_GSTRING_LEN
,
674 buff
= buff
+ ETH_GSTRING_LEN
;
680 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
681 struct net_device_stats
*net_stats
)
683 net_stats
->tx_dropped
= 0;
684 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
685 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
686 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
688 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
689 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
690 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
691 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
692 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
694 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
695 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
697 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
698 net_stats
->rx_length_errors
=
699 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
700 net_stats
->rx_length_errors
+=
701 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
702 net_stats
->rx_over_errors
=
703 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
706 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
708 struct hnae3_handle
*handle
;
711 handle
= &hdev
->vport
[0].nic
;
712 if (handle
->client
) {
713 status
= hclge_tqps_update_stats(handle
);
715 dev_err(&hdev
->pdev
->dev
,
716 "Update TQPS stats fail, status = %d.\n",
721 status
= hclge_mac_update_stats(hdev
);
723 dev_err(&hdev
->pdev
->dev
,
724 "Update MAC stats fail, status = %d.\n", status
);
726 status
= hclge_32_bit_update_stats(hdev
);
728 dev_err(&hdev
->pdev
->dev
,
729 "Update 32 bit stats fail, status = %d.\n",
732 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
735 static void hclge_update_stats(struct hnae3_handle
*handle
,
736 struct net_device_stats
*net_stats
)
738 struct hclge_vport
*vport
= hclge_get_vport(handle
);
739 struct hclge_dev
*hdev
= vport
->back
;
740 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
746 status
= hclge_mac_update_stats(hdev
);
748 dev_err(&hdev
->pdev
->dev
,
749 "Update MAC stats fail, status = %d.\n",
752 status
= hclge_32_bit_update_stats(hdev
);
754 dev_err(&hdev
->pdev
->dev
,
755 "Update 32 bit stats fail, status = %d.\n",
758 status
= hclge_64_bit_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update 64 bit stats fail, status = %d.\n",
764 status
= hclge_tqps_update_stats(handle
);
766 dev_err(&hdev
->pdev
->dev
,
767 "Update TQPS stats fail, status = %d.\n",
770 hclge_update_netstat(hw_stats
, net_stats
);
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
775 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
777 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
779 struct hclge_vport
*vport
= hclge_get_vport(handle
);
780 struct hclge_dev
*hdev
= vport
->back
;
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
788 if (stringset
== ETH_SS_TEST
) {
789 /* clear loopback bit flags at first */
790 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
791 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
792 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
793 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
795 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
799 } else if (stringset
== ETH_SS_STATS
) {
800 count
= ARRAY_SIZE(g_mac_stats_string
) +
801 ARRAY_SIZE(g_all_32bit_stats_string
) +
802 ARRAY_SIZE(g_all_64bit_stats_string
) +
803 hclge_tqps_get_sset_count(handle
, stringset
);
809 static void hclge_get_strings(struct hnae3_handle
*handle
,
813 u8
*p
= (char *)data
;
816 if (stringset
== ETH_SS_STATS
) {
817 size
= ARRAY_SIZE(g_mac_stats_string
);
818 p
= hclge_comm_get_strings(stringset
,
822 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
823 p
= hclge_comm_get_strings(stringset
,
824 g_all_32bit_stats_string
,
827 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
828 p
= hclge_comm_get_strings(stringset
,
829 g_all_64bit_stats_string
,
832 p
= hclge_tqps_get_strings(handle
, p
);
833 } else if (stringset
== ETH_SS_TEST
) {
834 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
836 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
838 p
+= ETH_GSTRING_LEN
;
840 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
842 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
844 p
+= ETH_GSTRING_LEN
;
846 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
848 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
850 p
+= ETH_GSTRING_LEN
;
855 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
857 struct hclge_vport
*vport
= hclge_get_vport(handle
);
858 struct hclge_dev
*hdev
= vport
->back
;
861 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
863 ARRAY_SIZE(g_mac_stats_string
),
865 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
866 g_all_32bit_stats_string
,
867 ARRAY_SIZE(g_all_32bit_stats_string
),
869 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
870 g_all_64bit_stats_string
,
871 ARRAY_SIZE(g_all_64bit_stats_string
),
873 p
= hclge_tqps_get_stats(handle
, p
);
876 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
877 struct hclge_func_status_cmd
*status
)
879 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
882 /* Set the pf to main pf */
883 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
884 hdev
->flag
|= HCLGE_FLAG_MAIN
;
886 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
891 static int hclge_query_function_status(struct hclge_dev
*hdev
)
893 struct hclge_func_status_cmd
*req
;
894 struct hclge_desc desc
;
898 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
899 req
= (struct hclge_func_status_cmd
*)desc
.data
;
902 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
904 dev_err(&hdev
->pdev
->dev
,
905 "query function status failed %d.\n",
911 /* Check pf reset is done */
914 usleep_range(1000, 2000);
915 } while (timeout
++ < 5);
917 ret
= hclge_parse_func_status(hdev
, req
);
922 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
924 struct hclge_pf_res_cmd
*req
;
925 struct hclge_desc desc
;
928 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
929 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
931 dev_err(&hdev
->pdev
->dev
,
932 "query pf resource failed %d.\n", ret
);
936 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
937 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
938 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
940 if (hnae3_dev_roce_supported(hdev
)) {
942 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
943 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
945 /* PF should have NIC vectors and Roce vectors,
946 * NIC vectors are queued before Roce vectors.
948 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
951 hnae3_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
952 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
958 static int hclge_parse_speed(int speed_cmd
, int *speed
)
962 *speed
= HCLGE_MAC_SPEED_10M
;
965 *speed
= HCLGE_MAC_SPEED_100M
;
968 *speed
= HCLGE_MAC_SPEED_1G
;
971 *speed
= HCLGE_MAC_SPEED_10G
;
974 *speed
= HCLGE_MAC_SPEED_25G
;
977 *speed
= HCLGE_MAC_SPEED_40G
;
980 *speed
= HCLGE_MAC_SPEED_50G
;
983 *speed
= HCLGE_MAC_SPEED_100G
;
992 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
995 unsigned long *supported
= hdev
->hw
.mac
.supported
;
997 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
998 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1001 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1002 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1005 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1006 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1009 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1010 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1013 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1014 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1017 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1018 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1021 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1023 u8 media_type
= hdev
->hw
.mac
.media_type
;
1025 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1028 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1031 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1033 struct hclge_cfg_param_cmd
*req
;
1034 u64 mac_addr_tmp_high
;
1038 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1040 /* get the configuration */
1041 cfg
->vmdq_vport_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1044 cfg
->tc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1045 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1046 cfg
->tqp_desc_num
= hnae3_get_field(__le32_to_cpu(req
->param
[0]),
1047 HCLGE_CFG_TQP_DESC_N_M
,
1048 HCLGE_CFG_TQP_DESC_N_S
);
1050 cfg
->phy_addr
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1051 HCLGE_CFG_PHY_ADDR_M
,
1052 HCLGE_CFG_PHY_ADDR_S
);
1053 cfg
->media_type
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1054 HCLGE_CFG_MEDIA_TP_M
,
1055 HCLGE_CFG_MEDIA_TP_S
);
1056 cfg
->rx_buf_len
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1057 HCLGE_CFG_RX_BUF_LEN_M
,
1058 HCLGE_CFG_RX_BUF_LEN_S
);
1059 /* get mac_address */
1060 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1061 mac_addr_tmp_high
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1062 HCLGE_CFG_MAC_ADDR_H_M
,
1063 HCLGE_CFG_MAC_ADDR_H_S
);
1065 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1067 cfg
->default_speed
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1068 HCLGE_CFG_DEFAULT_SPEED_M
,
1069 HCLGE_CFG_DEFAULT_SPEED_S
);
1070 cfg
->rss_size_max
= hnae3_get_field(__le32_to_cpu(req
->param
[3]),
1071 HCLGE_CFG_RSS_SIZE_M
,
1072 HCLGE_CFG_RSS_SIZE_S
);
1074 for (i
= 0; i
< ETH_ALEN
; i
++)
1075 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1077 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1078 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1080 cfg
->speed_ability
= hnae3_get_field(__le32_to_cpu(req
->param
[1]),
1081 HCLGE_CFG_SPEED_ABILITY_M
,
1082 HCLGE_CFG_SPEED_ABILITY_S
);
1085 /* hclge_get_cfg: query the static parameter from flash
1086 * @hdev: pointer to struct hclge_dev
1087 * @hcfg: the config structure to be getted
1089 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1091 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1092 struct hclge_cfg_param_cmd
*req
;
1095 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1098 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1099 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1101 hnae3_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1102 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1103 /* Len should be united by 4 bytes when send to hardware */
1104 hnae3_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1105 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1106 req
->offset
= cpu_to_le32(offset
);
1109 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1111 dev_err(&hdev
->pdev
->dev
, "get config failed %d.\n", ret
);
1115 hclge_parse_cfg(hcfg
, desc
);
1120 static int hclge_get_cap(struct hclge_dev
*hdev
)
1124 ret
= hclge_query_function_status(hdev
);
1126 dev_err(&hdev
->pdev
->dev
,
1127 "query function status error %d.\n", ret
);
1131 /* get pf resource */
1132 ret
= hclge_query_pf_resource(hdev
);
1134 dev_err(&hdev
->pdev
->dev
, "query pf resource error %d.\n", ret
);
1139 static int hclge_configure(struct hclge_dev
*hdev
)
1141 struct hclge_cfg cfg
;
1144 ret
= hclge_get_cfg(hdev
, &cfg
);
1146 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1150 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1151 hdev
->base_tqp_pid
= 0;
1152 hdev
->rss_size_max
= cfg
.rss_size_max
;
1153 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1154 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1155 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1156 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1157 hdev
->num_desc
= cfg
.tqp_desc_num
;
1158 hdev
->tm_info
.num_pg
= 1;
1159 hdev
->tc_max
= cfg
.tc_num
;
1160 hdev
->tm_info
.hw_pfc_map
= 0;
1162 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1164 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1168 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1170 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1171 (hdev
->tc_max
< 1)) {
1172 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1177 /* Dev does not support DCB */
1178 if (!hnae3_dev_dcb_supported(hdev
)) {
1182 hdev
->pfc_max
= hdev
->tc_max
;
1185 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1187 /* Currently not support uncontiuous tc */
1188 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1189 hnae3_set_bit(hdev
->hw_tc_map
, i
, 1);
1191 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1196 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1199 struct hclge_cfg_tso_status_cmd
*req
;
1200 struct hclge_desc desc
;
1203 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1205 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1208 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1209 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1210 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1213 hnae3_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1214 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1215 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1217 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1220 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1222 struct hclge_tqp
*tqp
;
1225 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1226 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1232 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1233 tqp
->dev
= &hdev
->pdev
->dev
;
1236 tqp
->q
.ae_algo
= &ae_algo
;
1237 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1238 tqp
->q
.desc_num
= hdev
->num_desc
;
1239 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1240 i
* HCLGE_TQP_REG_SIZE
;
1248 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1249 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1251 struct hclge_tqp_map_cmd
*req
;
1252 struct hclge_desc desc
;
1255 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1257 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1258 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1259 req
->tqp_vf
= func_id
;
1260 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1261 1 << HCLGE_TQP_MAP_EN_B
;
1262 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1264 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1266 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n", ret
);
1271 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1272 struct hnae3_queue
**tqp
, u16 num_tqps
)
1274 struct hclge_dev
*hdev
= vport
->back
;
1277 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1278 alloced
< num_tqps
; i
++) {
1279 if (!hdev
->htqp
[i
].alloced
) {
1280 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1281 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1282 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1283 hdev
->htqp
[i
].alloced
= true;
1287 vport
->alloc_tqps
= num_tqps
;
1292 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1294 struct hnae3_handle
*nic
= &vport
->nic
;
1295 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1296 struct hclge_dev
*hdev
= vport
->back
;
1299 kinfo
->num_desc
= hdev
->num_desc
;
1300 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1301 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1303 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1304 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1306 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1307 if (hdev
->hw_tc_map
& BIT(i
)) {
1308 kinfo
->tc_info
[i
].enable
= true;
1309 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1310 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1311 kinfo
->tc_info
[i
].tc
= i
;
1313 /* Set to default queue if TC is disable */
1314 kinfo
->tc_info
[i
].enable
= false;
1315 kinfo
->tc_info
[i
].tqp_offset
= 0;
1316 kinfo
->tc_info
[i
].tqp_count
= 1;
1317 kinfo
->tc_info
[i
].tc
= 0;
1321 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1322 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1326 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1328 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1333 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1334 struct hclge_vport
*vport
)
1336 struct hnae3_handle
*nic
= &vport
->nic
;
1337 struct hnae3_knic_private_info
*kinfo
;
1340 kinfo
= &nic
->kinfo
;
1341 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1342 struct hclge_tqp
*q
=
1343 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1347 is_pf
= !(vport
->vport_id
);
1348 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1357 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1359 struct hclge_vport
*vport
= hdev
->vport
;
1362 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1363 for (i
= 0; i
< num_vport
; i
++) {
1366 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1376 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1378 /* this would be initialized later */
1381 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1383 struct hnae3_handle
*nic
= &vport
->nic
;
1384 struct hclge_dev
*hdev
= vport
->back
;
1387 nic
->pdev
= hdev
->pdev
;
1388 nic
->ae_algo
= &ae_algo
;
1389 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1391 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1392 ret
= hclge_knic_setup(vport
, num_tqps
);
1394 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1399 hclge_unic_setup(vport
, num_tqps
);
1405 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1407 struct pci_dev
*pdev
= hdev
->pdev
;
1408 struct hclge_vport
*vport
;
1414 /* We need to alloc a vport for main NIC of PF */
1415 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1417 if (hdev
->num_tqps
< num_vport
) {
1418 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1419 hdev
->num_tqps
, num_vport
);
1423 /* Alloc the same number of TQPs for every vport */
1424 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1425 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1427 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1432 hdev
->vport
= vport
;
1433 hdev
->num_alloc_vport
= num_vport
;
1435 if (IS_ENABLED(CONFIG_PCI_IOV
))
1436 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1438 for (i
= 0; i
< num_vport
; i
++) {
1440 vport
->vport_id
= i
;
1443 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1445 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1448 "vport setup failed for vport %d, %d\n",
1459 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1460 struct hclge_pkt_buf_alloc
*buf_alloc
)
1462 /* TX buffer size is unit by 128 byte */
1463 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1464 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1465 struct hclge_tx_buff_alloc_cmd
*req
;
1466 struct hclge_desc desc
;
1470 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1472 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1473 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1474 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1476 req
->tx_pkt_buff
[i
] =
1477 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1478 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1481 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1483 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1489 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1490 struct hclge_pkt_buf_alloc
*buf_alloc
)
1492 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1495 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc failed %d\n", ret
);
1500 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1504 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1505 if (hdev
->hw_tc_map
& BIT(i
))
1510 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1514 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1515 if (hdev
->hw_tc_map
& BIT(i
) &&
1516 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1521 /* Get the number of pfc enabled TCs, which have private buffer */
1522 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1523 struct hclge_pkt_buf_alloc
*buf_alloc
)
1525 struct hclge_priv_buf
*priv
;
1528 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1529 priv
= &buf_alloc
->priv_buf
[i
];
1530 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1538 /* Get the number of pfc disabled TCs, which have private buffer */
1539 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1540 struct hclge_pkt_buf_alloc
*buf_alloc
)
1542 struct hclge_priv_buf
*priv
;
1545 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1546 priv
= &buf_alloc
->priv_buf
[i
];
1547 if (hdev
->hw_tc_map
& BIT(i
) &&
1548 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1556 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1558 struct hclge_priv_buf
*priv
;
1562 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1563 priv
= &buf_alloc
->priv_buf
[i
];
1565 rx_priv
+= priv
->buf_size
;
1570 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1572 u32 i
, total_tx_size
= 0;
1574 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1575 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1577 return total_tx_size
;
1580 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1581 struct hclge_pkt_buf_alloc
*buf_alloc
,
1584 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1585 int tc_num
, pfc_enable_num
;
1590 tc_num
= hclge_get_tc_num(hdev
);
1591 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1593 if (hnae3_dev_dcb_supported(hdev
))
1594 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1596 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1598 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1599 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1601 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1603 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1604 if (rx_all
<= rx_priv
+ shared_std
)
1607 shared_buf
= rx_all
- rx_priv
;
1608 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1609 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1610 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1612 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1613 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1614 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1615 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1616 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1618 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1619 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1626 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1627 struct hclge_pkt_buf_alloc
*buf_alloc
)
1631 total_size
= hdev
->pkt_buf_size
;
1633 /* alloc tx buffer for all enabled tc */
1634 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1635 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1637 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1640 if (hdev
->hw_tc_map
& BIT(i
))
1641 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1643 priv
->tx_buf_size
= 0;
1645 total_size
-= priv
->tx_buf_size
;
1651 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1652 * @hdev: pointer to struct hclge_dev
1653 * @buf_alloc: pointer to buffer calculation data
1654 * @return: 0: calculate sucessful, negative: fail
1656 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1657 struct hclge_pkt_buf_alloc
*buf_alloc
)
1659 u32 rx_all
= hdev
->pkt_buf_size
;
1660 int no_pfc_priv_num
, pfc_priv_num
;
1661 struct hclge_priv_buf
*priv
;
1664 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1666 /* When DCB is not supported, rx private
1667 * buffer is not allocated.
1669 if (!hnae3_dev_dcb_supported(hdev
)) {
1670 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1676 /* step 1, try to alloc private buffer for all enabled tc */
1677 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1678 priv
= &buf_alloc
->priv_buf
[i
];
1679 if (hdev
->hw_tc_map
& BIT(i
)) {
1681 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1682 priv
->wl
.low
= hdev
->mps
;
1683 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1684 priv
->buf_size
= priv
->wl
.high
+
1688 priv
->wl
.high
= 2 * hdev
->mps
;
1689 priv
->buf_size
= priv
->wl
.high
;
1699 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1702 /* step 2, try to decrease the buffer size of
1703 * no pfc TC's private buffer
1705 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1706 priv
= &buf_alloc
->priv_buf
[i
];
1713 if (!(hdev
->hw_tc_map
& BIT(i
)))
1718 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1720 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1721 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1724 priv
->wl
.high
= hdev
->mps
;
1725 priv
->buf_size
= priv
->wl
.high
;
1729 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1732 /* step 3, try to reduce the number of pfc disabled TCs,
1733 * which have private buffer
1735 /* get the total no pfc enable TC number, which have private buffer */
1736 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1738 /* let the last to be cleared first */
1739 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1740 priv
= &buf_alloc
->priv_buf
[i
];
1742 if (hdev
->hw_tc_map
& BIT(i
) &&
1743 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1744 /* Clear the no pfc TC private buffer */
1752 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1753 no_pfc_priv_num
== 0)
1757 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1760 /* step 4, try to reduce the number of pfc enabled TCs
1761 * which have private buffer.
1763 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1765 /* let the last to be cleared first */
1766 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1767 priv
= &buf_alloc
->priv_buf
[i
];
1769 if (hdev
->hw_tc_map
& BIT(i
) &&
1770 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1771 /* Reduce the number of pfc TC with private buffer */
1779 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1783 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1789 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1790 struct hclge_pkt_buf_alloc
*buf_alloc
)
1792 struct hclge_rx_priv_buff_cmd
*req
;
1793 struct hclge_desc desc
;
1797 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1798 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1800 /* Alloc private buffer TCs */
1801 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1802 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1805 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1807 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1811 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1812 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1814 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1816 dev_err(&hdev
->pdev
->dev
,
1817 "rx private buffer alloc cmd failed %d\n", ret
);
1822 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1823 struct hclge_pkt_buf_alloc
*buf_alloc
)
1825 struct hclge_rx_priv_wl_buf
*req
;
1826 struct hclge_priv_buf
*priv
;
1827 struct hclge_desc desc
[2];
1831 for (i
= 0; i
< 2; i
++) {
1832 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1834 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1836 /* The first descriptor set the NEXT bit to 1 */
1838 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1840 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1842 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1843 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1845 priv
= &buf_alloc
->priv_buf
[idx
];
1846 req
->tc_wl
[j
].high
=
1847 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1848 req
->tc_wl
[j
].high
|=
1849 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1851 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1852 req
->tc_wl
[j
].low
|=
1853 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1857 /* Send 2 descriptor at one time */
1858 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1860 dev_err(&hdev
->pdev
->dev
,
1861 "rx private waterline config cmd failed %d\n",
1866 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1867 struct hclge_pkt_buf_alloc
*buf_alloc
)
1869 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1870 struct hclge_rx_com_thrd
*req
;
1871 struct hclge_desc desc
[2];
1872 struct hclge_tc_thrd
*tc
;
1876 for (i
= 0; i
< 2; i
++) {
1877 hclge_cmd_setup_basic_desc(&desc
[i
],
1878 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1879 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1881 /* The first descriptor set the NEXT bit to 1 */
1883 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1885 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1887 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1888 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1890 req
->com_thrd
[j
].high
=
1891 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1892 req
->com_thrd
[j
].high
|=
1893 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1894 req
->com_thrd
[j
].low
=
1895 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1896 req
->com_thrd
[j
].low
|=
1897 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1901 /* Send 2 descriptors at one time */
1902 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1904 dev_err(&hdev
->pdev
->dev
,
1905 "common threshold config cmd failed %d\n", ret
);
1909 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1910 struct hclge_pkt_buf_alloc
*buf_alloc
)
1912 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1913 struct hclge_rx_com_wl
*req
;
1914 struct hclge_desc desc
;
1917 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1919 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1920 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1921 req
->com_wl
.high
|= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1923 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1924 req
->com_wl
.low
|= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B
));
1926 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1928 dev_err(&hdev
->pdev
->dev
,
1929 "common waterline config cmd failed %d\n", ret
);
1934 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1936 struct hclge_pkt_buf_alloc
*pkt_buf
;
1939 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1943 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1945 dev_err(&hdev
->pdev
->dev
,
1946 "could not calc tx buffer size for all TCs %d\n", ret
);
1950 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1952 dev_err(&hdev
->pdev
->dev
,
1953 "could not alloc tx buffers %d\n", ret
);
1957 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1959 dev_err(&hdev
->pdev
->dev
,
1960 "could not calc rx priv buffer size for all TCs %d\n",
1965 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1967 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1972 if (hnae3_dev_dcb_supported(hdev
)) {
1973 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1975 dev_err(&hdev
->pdev
->dev
,
1976 "could not configure rx private waterline %d\n",
1981 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
1983 dev_err(&hdev
->pdev
->dev
,
1984 "could not configure common threshold %d\n",
1990 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
1992 dev_err(&hdev
->pdev
->dev
,
1993 "could not configure common waterline %d\n", ret
);
2000 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2002 struct hnae3_handle
*roce
= &vport
->roce
;
2003 struct hnae3_handle
*nic
= &vport
->nic
;
2005 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2007 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2008 vport
->back
->num_msi_left
== 0)
2011 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2013 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2014 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2016 roce
->pdev
= nic
->pdev
;
2017 roce
->ae_algo
= nic
->ae_algo
;
2018 roce
->numa_node_mask
= nic
->numa_node_mask
;
2023 static int hclge_init_msi(struct hclge_dev
*hdev
)
2025 struct pci_dev
*pdev
= hdev
->pdev
;
2029 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2030 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2033 "failed(%d) to allocate MSI/MSI-X vectors\n",
2037 if (vectors
< hdev
->num_msi
)
2038 dev_warn(&hdev
->pdev
->dev
,
2039 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2040 hdev
->num_msi
, vectors
);
2042 hdev
->num_msi
= vectors
;
2043 hdev
->num_msi_left
= vectors
;
2044 hdev
->base_msi_vector
= pdev
->irq
;
2045 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2046 HCLGE_ROCE_VECTOR_OFFSET
;
2048 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2049 sizeof(u16
), GFP_KERNEL
);
2050 if (!hdev
->vector_status
) {
2051 pci_free_irq_vectors(pdev
);
2055 for (i
= 0; i
< hdev
->num_msi
; i
++)
2056 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2058 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2059 sizeof(int), GFP_KERNEL
);
2060 if (!hdev
->vector_irq
) {
2061 pci_free_irq_vectors(pdev
);
2068 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2070 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2072 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2073 mac
->duplex
= (u8
)duplex
;
2075 mac
->duplex
= HCLGE_MAC_FULL
;
2080 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2082 struct hclge_config_mac_speed_dup_cmd
*req
;
2083 struct hclge_desc desc
;
2086 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2088 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2090 hnae3_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2093 case HCLGE_MAC_SPEED_10M
:
2094 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2095 HCLGE_CFG_SPEED_S
, 6);
2097 case HCLGE_MAC_SPEED_100M
:
2098 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2099 HCLGE_CFG_SPEED_S
, 7);
2101 case HCLGE_MAC_SPEED_1G
:
2102 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2103 HCLGE_CFG_SPEED_S
, 0);
2105 case HCLGE_MAC_SPEED_10G
:
2106 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2107 HCLGE_CFG_SPEED_S
, 1);
2109 case HCLGE_MAC_SPEED_25G
:
2110 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2111 HCLGE_CFG_SPEED_S
, 2);
2113 case HCLGE_MAC_SPEED_40G
:
2114 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2115 HCLGE_CFG_SPEED_S
, 3);
2117 case HCLGE_MAC_SPEED_50G
:
2118 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2119 HCLGE_CFG_SPEED_S
, 4);
2121 case HCLGE_MAC_SPEED_100G
:
2122 hnae3_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2123 HCLGE_CFG_SPEED_S
, 5);
2126 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2130 hnae3_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2133 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2135 dev_err(&hdev
->pdev
->dev
,
2136 "mac speed/duplex config cmd failed %d.\n", ret
);
2140 hclge_check_speed_dup(hdev
, duplex
, speed
);
2145 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2148 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2149 struct hclge_dev
*hdev
= vport
->back
;
2151 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2154 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2157 struct hclge_query_an_speed_dup_cmd
*req
;
2158 struct hclge_desc desc
;
2162 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2164 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2165 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2167 dev_err(&hdev
->pdev
->dev
,
2168 "mac speed/autoneg/duplex query cmd failed %d\n",
2173 *duplex
= hnae3_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2174 speed_tmp
= hnae3_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2175 HCLGE_QUERY_SPEED_S
);
2177 ret
= hclge_parse_speed(speed_tmp
, speed
);
2179 dev_err(&hdev
->pdev
->dev
,
2180 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2185 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2187 struct hclge_config_auto_neg_cmd
*req
;
2188 struct hclge_desc desc
;
2192 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2194 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2195 hnae3_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2196 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2198 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2200 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2206 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2208 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2209 struct hclge_dev
*hdev
= vport
->back
;
2211 return hclge_set_autoneg_en(hdev
, enable
);
2214 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2216 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2217 struct hclge_dev
*hdev
= vport
->back
;
2218 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2221 return phydev
->autoneg
;
2223 return hdev
->hw
.mac
.autoneg
;
2226 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2230 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2231 struct hclge_desc desc
;
2234 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2235 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2237 hnae3_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2239 ether_addr_copy(req
->mac_mask
, mac_mask
);
2241 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2243 dev_err(&hdev
->pdev
->dev
,
2244 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2250 static int hclge_mac_init(struct hclge_dev
*hdev
)
2252 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2253 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2254 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2255 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2256 struct hclge_vport
*vport
;
2261 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2263 dev_err(&hdev
->pdev
->dev
,
2264 "Config mac speed dup fail ret=%d\n", ret
);
2270 /* Initialize the MTA table work mode */
2271 hdev
->enable_mta
= true;
2272 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2274 ret
= hclge_set_mta_filter_mode(hdev
,
2275 hdev
->mta_mac_sel_type
,
2278 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2283 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
2284 vport
= &hdev
->vport
[i
];
2285 vport
->accept_mta_mc
= false;
2287 memset(vport
->mta_shadow
, 0, sizeof(vport
->mta_shadow
));
2288 ret
= hclge_cfg_func_mta_filter(hdev
, vport
->vport_id
, false);
2290 dev_err(&hdev
->pdev
->dev
,
2291 "set mta filter mode fail ret=%d\n", ret
);
2296 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2298 dev_err(&hdev
->pdev
->dev
,
2299 "set default mac_vlan_mask fail ret=%d\n", ret
);
2308 ret
= hclge_set_mtu(handle
, mtu
);
2310 dev_err(&hdev
->pdev
->dev
,
2311 "set mtu failed ret=%d\n", ret
);
2316 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2318 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2319 schedule_work(&hdev
->mbx_service_task
);
2322 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2324 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2325 schedule_work(&hdev
->rst_service_task
);
2328 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2330 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2331 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2332 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2333 (void)schedule_work(&hdev
->service_task
);
2336 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2338 struct hclge_link_status_cmd
*req
;
2339 struct hclge_desc desc
;
2343 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2344 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2346 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2351 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2352 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2354 return !!link_status
;
2357 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2362 mac_state
= hclge_get_mac_link_status(hdev
);
2364 if (hdev
->hw
.mac
.phydev
) {
2365 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2366 link_stat
= mac_state
&
2367 hdev
->hw
.mac
.phydev
->link
;
2372 link_stat
= mac_state
;
2378 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2380 struct hnae3_client
*rclient
= hdev
->roce_client
;
2381 struct hnae3_client
*client
= hdev
->nic_client
;
2382 struct hnae3_handle
*rhandle
;
2383 struct hnae3_handle
*handle
;
2389 state
= hclge_get_mac_phy_link(hdev
);
2390 if (state
!= hdev
->hw
.mac
.link
) {
2391 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2392 handle
= &hdev
->vport
[i
].nic
;
2393 client
->ops
->link_status_change(handle
, state
);
2394 rhandle
= &hdev
->vport
[i
].roce
;
2395 if (rclient
&& rclient
->ops
->link_status_change
)
2396 rclient
->ops
->link_status_change(rhandle
,
2399 hdev
->hw
.mac
.link
= state
;
2403 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2405 struct hclge_mac mac
= hdev
->hw
.mac
;
2410 /* get the speed and duplex as autoneg'result from mac cmd when phy
2413 if (mac
.phydev
|| !mac
.autoneg
)
2416 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2418 dev_err(&hdev
->pdev
->dev
,
2419 "mac autoneg/speed/duplex query failed %d\n", ret
);
2423 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2424 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2426 dev_err(&hdev
->pdev
->dev
,
2427 "mac speed/duplex config failed %d\n", ret
);
2435 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2437 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2438 struct hclge_dev
*hdev
= vport
->back
;
2440 return hclge_update_speed_duplex(hdev
);
2443 static int hclge_get_status(struct hnae3_handle
*handle
)
2445 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2446 struct hclge_dev
*hdev
= vport
->back
;
2448 hclge_update_link_status(hdev
);
2450 return hdev
->hw
.mac
.link
;
2453 static void hclge_service_timer(struct timer_list
*t
)
2455 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2457 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2458 hdev
->hw_stats
.stats_timer
++;
2459 hclge_task_schedule(hdev
);
2462 static void hclge_service_complete(struct hclge_dev
*hdev
)
2464 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2466 /* Flush memory before next watchdog */
2467 smp_mb__before_atomic();
2468 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2471 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2476 /* fetch the events from their corresponding regs */
2477 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_VECTOR_INT_STS
);
2478 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2480 /* Assumption: If by any chance reset and mailbox events are reported
2481 * together then we will only process reset event in this go and will
2482 * defer the processing of the mailbox events. Since, we would have not
2483 * cleared RX CMDQ event this time we would receive again another
2484 * interrupt from H/W just for the mailbox.
2487 /* check for vector0 reset event sources */
2488 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2489 set_bit(HCLGE_STATE_CMD_DISABLE
, &hdev
->state
);
2490 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2491 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2492 return HCLGE_VECTOR0_EVENT_RST
;
2495 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2496 set_bit(HCLGE_STATE_CMD_DISABLE
, &hdev
->state
);
2497 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2498 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2499 return HCLGE_VECTOR0_EVENT_RST
;
2502 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2503 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2504 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2505 return HCLGE_VECTOR0_EVENT_RST
;
2508 /* check for vector0 mailbox(=CMDQ RX) event source */
2509 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2510 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2511 *clearval
= cmdq_src_reg
;
2512 return HCLGE_VECTOR0_EVENT_MBX
;
2515 return HCLGE_VECTOR0_EVENT_OTHER
;
2518 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2521 switch (event_type
) {
2522 case HCLGE_VECTOR0_EVENT_RST
:
2523 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2525 case HCLGE_VECTOR0_EVENT_MBX
:
2526 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2531 static void hclge_clear_all_event_cause(struct hclge_dev
*hdev
)
2533 hclge_clear_event_cause(hdev
, HCLGE_VECTOR0_EVENT_RST
,
2534 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) |
2535 BIT(HCLGE_VECTOR0_CORERESET_INT_B
) |
2536 BIT(HCLGE_VECTOR0_IMPRESET_INT_B
));
2537 hclge_clear_event_cause(hdev
, HCLGE_VECTOR0_EVENT_MBX
, 0);
2540 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2542 writel(enable
? 1 : 0, vector
->addr
);
2545 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2547 struct hclge_dev
*hdev
= data
;
2551 hclge_enable_vector(&hdev
->misc_vector
, false);
2552 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2554 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2555 switch (event_cause
) {
2556 case HCLGE_VECTOR0_EVENT_RST
:
2557 hclge_reset_task_schedule(hdev
);
2559 case HCLGE_VECTOR0_EVENT_MBX
:
2560 /* If we are here then,
2561 * 1. Either we are not handling any mbx task and we are not
2564 * 2. We could be handling a mbx task but nothing more is
2566 * In both cases, we should schedule mbx task as there are more
2567 * mbx messages reported by this interrupt.
2569 hclge_mbx_task_schedule(hdev
);
2572 dev_warn(&hdev
->pdev
->dev
,
2573 "received unknown or unhandled event of vector0\n");
2577 /* clear the source of interrupt if it is not cause by reset */
2578 if (event_cause
!= HCLGE_VECTOR0_EVENT_RST
) {
2579 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2580 hclge_enable_vector(&hdev
->misc_vector
, true);
2586 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2588 if (hdev
->vector_status
[vector_id
] == HCLGE_INVALID_VPORT
) {
2589 dev_warn(&hdev
->pdev
->dev
,
2590 "vector(vector_id %d) has been freed.\n", vector_id
);
2594 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2595 hdev
->num_msi_left
+= 1;
2596 hdev
->num_msi_used
-= 1;
2599 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2601 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2603 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2605 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2606 hdev
->vector_status
[0] = 0;
2608 hdev
->num_msi_left
-= 1;
2609 hdev
->num_msi_used
+= 1;
2612 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2616 hclge_get_misc_vector(hdev
);
2618 /* this would be explicitly freed in the end */
2619 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2620 0, "hclge_misc", hdev
);
2622 hclge_free_vector(hdev
, 0);
2623 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2624 hdev
->misc_vector
.vector_irq
);
2630 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2632 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2633 hclge_free_vector(hdev
, 0);
2636 static int hclge_notify_client(struct hclge_dev
*hdev
,
2637 enum hnae3_reset_notify_type type
)
2639 struct hnae3_client
*rclient
= hdev
->roce_client
;
2640 struct hnae3_client
*client
= hdev
->nic_client
;
2641 struct hnae3_handle
*handle
;
2645 if (!client
->ops
->reset_notify
)
2648 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2649 handle
= &hdev
->vport
[i
].nic
;
2650 ret
= client
->ops
->reset_notify(handle
, type
);
2652 dev_err(&hdev
->pdev
->dev
,
2653 "notify nic client failed %d", ret
);
2657 if (rclient
&& rclient
->ops
->reset_notify
) {
2658 handle
= &hdev
->vport
[i
].roce
;
2659 ret
= rclient
->ops
->reset_notify(handle
, type
);
2661 dev_err(&hdev
->pdev
->dev
,
2662 "notify roce client failed %d", ret
);
2671 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2673 #define HCLGE_RESET_WATI_MS 100
2674 #define HCLGE_RESET_WAIT_CNT 5
2675 u32 val
, reg
, reg_bit
;
2678 switch (hdev
->reset_type
) {
2679 case HNAE3_GLOBAL_RESET
:
2680 reg
= HCLGE_GLOBAL_RESET_REG
;
2681 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2683 case HNAE3_CORE_RESET
:
2684 reg
= HCLGE_GLOBAL_RESET_REG
;
2685 reg_bit
= HCLGE_CORE_RESET_BIT
;
2687 case HNAE3_FUNC_RESET
:
2688 reg
= HCLGE_FUN_RST_ING
;
2689 reg_bit
= HCLGE_FUN_RST_ING_B
;
2692 dev_err(&hdev
->pdev
->dev
,
2693 "Wait for unsupported reset type: %d\n",
2698 val
= hclge_read_dev(&hdev
->hw
, reg
);
2699 while (hnae3_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2700 msleep(HCLGE_RESET_WATI_MS
);
2701 val
= hclge_read_dev(&hdev
->hw
, reg
);
2705 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2706 dev_warn(&hdev
->pdev
->dev
,
2707 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2714 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2716 struct hclge_desc desc
;
2717 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2720 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2721 hnae3_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2722 req
->fun_reset_vfid
= func_id
;
2724 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2726 dev_err(&hdev
->pdev
->dev
,
2727 "send function reset cmd fail, status =%d\n", ret
);
2732 static void hclge_do_reset(struct hclge_dev
*hdev
)
2734 struct pci_dev
*pdev
= hdev
->pdev
;
2737 switch (hdev
->reset_type
) {
2738 case HNAE3_GLOBAL_RESET
:
2739 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2740 hnae3_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2741 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2742 dev_info(&pdev
->dev
, "Global Reset requested\n");
2744 case HNAE3_CORE_RESET
:
2745 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2746 hnae3_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2747 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2748 dev_info(&pdev
->dev
, "Core Reset requested\n");
2750 case HNAE3_FUNC_RESET
:
2751 dev_info(&pdev
->dev
, "PF Reset requested\n");
2752 hclge_func_reset_cmd(hdev
, 0);
2753 /* schedule again to check later */
2754 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2755 hclge_reset_task_schedule(hdev
);
2758 dev_warn(&pdev
->dev
,
2759 "Unsupported reset type: %d\n", hdev
->reset_type
);
2764 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2765 unsigned long *addr
)
2767 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2769 /* return the highest priority reset level amongst all */
2770 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2771 rst_level
= HNAE3_GLOBAL_RESET
;
2772 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2773 rst_level
= HNAE3_CORE_RESET
;
2774 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2775 rst_level
= HNAE3_IMP_RESET
;
2776 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2777 rst_level
= HNAE3_FUNC_RESET
;
2779 /* now, clear all other resets */
2780 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2781 clear_bit(HNAE3_CORE_RESET
, addr
);
2782 clear_bit(HNAE3_IMP_RESET
, addr
);
2783 clear_bit(HNAE3_FUNC_RESET
, addr
);
2788 static void hclge_clear_reset_cause(struct hclge_dev
*hdev
)
2792 switch (hdev
->reset_type
) {
2793 case HNAE3_IMP_RESET
:
2794 clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2796 case HNAE3_GLOBAL_RESET
:
2797 clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2799 case HNAE3_CORE_RESET
:
2800 clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2809 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, clearval
);
2810 hclge_enable_vector(&hdev
->misc_vector
, true);
2813 static void hclge_reset(struct hclge_dev
*hdev
)
2815 struct hnae3_handle
*handle
;
2817 /* perform reset of the stack & ae device for a client */
2818 handle
= &hdev
->vport
[0].nic
;
2820 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2822 if (!hclge_reset_wait(hdev
)) {
2823 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2824 hclge_reset_ae_dev(hdev
->ae_dev
);
2825 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2827 hclge_clear_reset_cause(hdev
);
2829 /* schedule again to check pending resets later */
2830 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2831 hclge_reset_task_schedule(hdev
);
2834 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2835 handle
->last_reset_time
= jiffies
;
2839 static void hclge_reset_event(struct hnae3_handle
*handle
)
2841 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2842 struct hclge_dev
*hdev
= vport
->back
;
2844 /* check if this is a new reset request and we are not here just because
2845 * last reset attempt did not succeed and watchdog hit us again. We will
2846 * know this if last reset request did not occur very recently (watchdog
2847 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2848 * In case of new request we reset the "reset level" to PF reset.
2849 * And if it is a repeat reset request of the most recent one then we
2850 * want to make sure we throttle the reset request. Therefore, we will
2851 * not allow it again before 3*HZ times.
2853 if (time_before(jiffies
, (handle
->last_reset_time
+ 3 * HZ
)))
2855 else if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2856 handle
->reset_level
= HNAE3_FUNC_RESET
;
2858 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2859 handle
->reset_level
);
2861 /* request reset & schedule reset task */
2862 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2863 hclge_reset_task_schedule(hdev
);
2865 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2866 handle
->reset_level
++;
2869 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2871 /* check if there is any ongoing reset in the hardware. This status can
2872 * be checked from reset_pending. If there is then, we need to wait for
2873 * hardware to complete reset.
2874 * a. If we are able to figure out in reasonable time that hardware
2875 * has fully resetted then, we can proceed with driver, client
2877 * b. else, we can come back later to check this status so re-sched
2880 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2881 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2884 /* check if we got any *new* reset requests to be honored */
2885 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2886 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2887 hclge_do_reset(hdev
);
2889 hdev
->reset_type
= HNAE3_NONE_RESET
;
2892 static void hclge_reset_service_task(struct work_struct
*work
)
2894 struct hclge_dev
*hdev
=
2895 container_of(work
, struct hclge_dev
, rst_service_task
);
2897 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2900 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2902 hclge_reset_subtask(hdev
);
2904 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2907 static void hclge_mailbox_service_task(struct work_struct
*work
)
2909 struct hclge_dev
*hdev
=
2910 container_of(work
, struct hclge_dev
, mbx_service_task
);
2912 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2915 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2917 hclge_mbx_handler(hdev
);
2919 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2922 static void hclge_service_task(struct work_struct
*work
)
2924 struct hclge_dev
*hdev
=
2925 container_of(work
, struct hclge_dev
, service_task
);
2927 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2928 hclge_update_stats_for_all(hdev
);
2929 hdev
->hw_stats
.stats_timer
= 0;
2932 hclge_update_speed_duplex(hdev
);
2933 hclge_update_link_status(hdev
);
2934 hclge_service_complete(hdev
);
2937 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2939 /* VF handle has no client */
2940 if (!handle
->client
)
2941 return container_of(handle
, struct hclge_vport
, nic
);
2942 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2943 return container_of(handle
, struct hclge_vport
, roce
);
2945 return container_of(handle
, struct hclge_vport
, nic
);
2948 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2949 struct hnae3_vector_info
*vector_info
)
2951 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2952 struct hnae3_vector_info
*vector
= vector_info
;
2953 struct hclge_dev
*hdev
= vport
->back
;
2957 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2959 for (j
= 0; j
< vector_num
; j
++) {
2960 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2961 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2962 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2963 vector
->io_addr
= hdev
->hw
.io_base
+
2964 HCLGE_VECTOR_REG_BASE
+
2965 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2967 HCLGE_VECTOR_VF_OFFSET
;
2968 hdev
->vector_status
[i
] = vport
->vport_id
;
2969 hdev
->vector_irq
[i
] = vector
->vector
;
2978 hdev
->num_msi_left
-= alloc
;
2979 hdev
->num_msi_used
+= alloc
;
2984 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2988 for (i
= 0; i
< hdev
->num_msi
; i
++)
2989 if (vector
== hdev
->vector_irq
[i
])
2995 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
2997 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2998 struct hclge_dev
*hdev
= vport
->back
;
3001 vector_id
= hclge_get_vector_index(hdev
, vector
);
3002 if (vector_id
< 0) {
3003 dev_err(&hdev
->pdev
->dev
,
3004 "Get vector index fail. vector_id =%d\n", vector_id
);
3008 hclge_free_vector(hdev
, vector_id
);
3013 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
3015 return HCLGE_RSS_KEY_SIZE
;
3018 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
3020 return HCLGE_RSS_IND_TBL_SIZE
;
3023 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3024 const u8 hfunc
, const u8
*key
)
3026 struct hclge_rss_config_cmd
*req
;
3027 struct hclge_desc desc
;
3032 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3034 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3035 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3038 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3039 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3041 if (key_offset
== 2)
3043 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3045 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3047 memcpy(req
->hash_key
,
3048 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3050 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3052 dev_err(&hdev
->pdev
->dev
,
3053 "Configure RSS config fail, status = %d\n",
3061 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3063 struct hclge_rss_indirection_table_cmd
*req
;
3064 struct hclge_desc desc
;
3068 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3070 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3071 hclge_cmd_setup_basic_desc
3072 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3074 req
->start_table_index
=
3075 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3076 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3078 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3079 req
->rss_result
[j
] =
3080 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3082 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3084 dev_err(&hdev
->pdev
->dev
,
3085 "Configure rss indir table fail,status = %d\n",
3093 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3094 u16
*tc_size
, u16
*tc_offset
)
3096 struct hclge_rss_tc_mode_cmd
*req
;
3097 struct hclge_desc desc
;
3101 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3102 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3104 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3107 hnae3_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3108 hnae3_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3109 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3110 hnae3_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3111 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3113 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3116 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3118 dev_err(&hdev
->pdev
->dev
,
3119 "Configure rss tc mode fail, status = %d\n", ret
);
3124 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3126 struct hclge_rss_input_tuple_cmd
*req
;
3127 struct hclge_desc desc
;
3130 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3132 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3134 /* Get the tuple cfg from pf */
3135 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3136 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3137 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3138 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3139 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3140 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3141 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3142 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3143 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3145 dev_err(&hdev
->pdev
->dev
,
3146 "Configure rss input fail, status = %d\n", ret
);
3150 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3153 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3156 /* Get hash algorithm */
3158 *hfunc
= vport
->rss_algo
;
3160 /* Get the RSS Key required by the user */
3162 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3164 /* Get indirect table */
3166 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3167 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3172 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3173 const u8
*key
, const u8 hfunc
)
3175 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3176 struct hclge_dev
*hdev
= vport
->back
;
3180 /* Set the RSS Hash Key if specififed by the user */
3183 if (hfunc
== ETH_RSS_HASH_TOP
||
3184 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3185 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3188 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3192 /* Update the shadow RSS key with user specified qids */
3193 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3194 vport
->rss_algo
= hash_algo
;
3197 /* Update the shadow RSS table with user specified qids */
3198 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3199 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3201 /* Update the hardware */
3202 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3205 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3207 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3209 if (nfc
->data
& RXH_L4_B_2_3
)
3210 hash_sets
|= HCLGE_D_PORT_BIT
;
3212 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3214 if (nfc
->data
& RXH_IP_SRC
)
3215 hash_sets
|= HCLGE_S_IP_BIT
;
3217 hash_sets
&= ~HCLGE_S_IP_BIT
;
3219 if (nfc
->data
& RXH_IP_DST
)
3220 hash_sets
|= HCLGE_D_IP_BIT
;
3222 hash_sets
&= ~HCLGE_D_IP_BIT
;
3224 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3225 hash_sets
|= HCLGE_V_TAG_BIT
;
3230 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3231 struct ethtool_rxnfc
*nfc
)
3233 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3234 struct hclge_dev
*hdev
= vport
->back
;
3235 struct hclge_rss_input_tuple_cmd
*req
;
3236 struct hclge_desc desc
;
3240 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3241 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3244 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3245 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3247 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3248 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3249 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3250 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3251 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3252 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3253 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3254 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3256 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3257 switch (nfc
->flow_type
) {
3259 req
->ipv4_tcp_en
= tuple_sets
;
3262 req
->ipv6_tcp_en
= tuple_sets
;
3265 req
->ipv4_udp_en
= tuple_sets
;
3268 req
->ipv6_udp_en
= tuple_sets
;
3271 req
->ipv4_sctp_en
= tuple_sets
;
3274 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3275 (nfc
->data
& RXH_L4_B_2_3
))
3278 req
->ipv6_sctp_en
= tuple_sets
;
3281 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3284 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3290 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3292 dev_err(&hdev
->pdev
->dev
,
3293 "Set rss tuple fail, status = %d\n", ret
);
3297 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3298 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3299 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3300 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3301 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3302 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3303 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3304 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3308 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3309 struct ethtool_rxnfc
*nfc
)
3311 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3316 switch (nfc
->flow_type
) {
3318 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3321 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3324 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3327 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3330 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3333 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3337 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3346 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3347 nfc
->data
|= RXH_L4_B_2_3
;
3348 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3349 nfc
->data
|= RXH_L4_B_0_1
;
3350 if (tuple_sets
& HCLGE_D_IP_BIT
)
3351 nfc
->data
|= RXH_IP_DST
;
3352 if (tuple_sets
& HCLGE_S_IP_BIT
)
3353 nfc
->data
|= RXH_IP_SRC
;
3358 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3360 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3361 struct hclge_dev
*hdev
= vport
->back
;
3363 return hdev
->rss_size_max
;
3366 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3368 struct hclge_vport
*vport
= hdev
->vport
;
3369 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3370 u16 rss_size
= vport
[0].alloc_rss_size
;
3371 u8
*key
= vport
[0].rss_hash_key
;
3372 u8 hfunc
= vport
[0].rss_algo
;
3373 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3374 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3375 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3379 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3383 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3387 ret
= hclge_set_rss_input_tuple(hdev
);
3391 /* Each TC have the same queue size, and tc_size set to hardware is
3392 * the log2 of roundup power of two of rss_size, the acutal queue
3393 * size is limited by indirection table.
3395 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3396 dev_err(&hdev
->pdev
->dev
,
3397 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3402 roundup_size
= roundup_pow_of_two(rss_size
);
3403 roundup_size
= ilog2(roundup_size
);
3405 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3408 if (!(hdev
->hw_tc_map
& BIT(i
)))
3412 tc_size
[i
] = roundup_size
;
3413 tc_offset
[i
] = rss_size
* i
;
3416 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3419 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3421 struct hclge_vport
*vport
= hdev
->vport
;
3424 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3425 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3426 vport
[j
].rss_indirection_tbl
[i
] =
3427 i
% vport
[j
].alloc_rss_size
;
3431 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3433 struct hclge_vport
*vport
= hdev
->vport
;
3436 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3437 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3438 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3439 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3440 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3441 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3442 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3443 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3444 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3445 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3446 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3447 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3448 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3449 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3450 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3451 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3452 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3454 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3456 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3459 hclge_rss_indir_init_cfg(hdev
);
3462 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3463 int vector_id
, bool en
,
3464 struct hnae3_ring_chain_node
*ring_chain
)
3466 struct hclge_dev
*hdev
= vport
->back
;
3467 struct hnae3_ring_chain_node
*node
;
3468 struct hclge_desc desc
;
3469 struct hclge_ctrl_vector_chain_cmd
*req
3470 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3471 enum hclge_cmd_status status
;
3472 enum hclge_opcode_type op
;
3473 u16 tqp_type_and_id
;
3476 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3477 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3478 req
->int_vector_id
= vector_id
;
3481 for (node
= ring_chain
; node
; node
= node
->next
) {
3482 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3483 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3485 hnae3_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3486 hnae3_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3487 HCLGE_TQP_ID_S
, node
->tqp_index
);
3488 hnae3_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3490 hnae3_get_field(node
->int_gl_idx
,
3491 HNAE3_RING_GL_IDX_M
,
3492 HNAE3_RING_GL_IDX_S
));
3493 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3494 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3495 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3496 req
->vfid
= vport
->vport_id
;
3498 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3500 dev_err(&hdev
->pdev
->dev
,
3501 "Map TQP fail, status is %d.\n",
3507 hclge_cmd_setup_basic_desc(&desc
,
3510 req
->int_vector_id
= vector_id
;
3515 req
->int_cause_num
= i
;
3516 req
->vfid
= vport
->vport_id
;
3517 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3519 dev_err(&hdev
->pdev
->dev
,
3520 "Map TQP fail, status is %d.\n", status
);
3528 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3530 struct hnae3_ring_chain_node
*ring_chain
)
3532 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3533 struct hclge_dev
*hdev
= vport
->back
;
3536 vector_id
= hclge_get_vector_index(hdev
, vector
);
3537 if (vector_id
< 0) {
3538 dev_err(&hdev
->pdev
->dev
,
3539 "Get vector index fail. vector_id =%d\n", vector_id
);
3543 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3546 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3548 struct hnae3_ring_chain_node
*ring_chain
)
3550 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3551 struct hclge_dev
*hdev
= vport
->back
;
3554 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3557 vector_id
= hclge_get_vector_index(hdev
, vector
);
3558 if (vector_id
< 0) {
3559 dev_err(&handle
->pdev
->dev
,
3560 "Get vector index fail. ret =%d\n", vector_id
);
3564 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3566 dev_err(&handle
->pdev
->dev
,
3567 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3574 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3575 struct hclge_promisc_param
*param
)
3577 struct hclge_promisc_cfg_cmd
*req
;
3578 struct hclge_desc desc
;
3581 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3583 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3584 req
->vf_id
= param
->vf_id
;
3586 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3587 * pdev revision(0x20), new revision support them. The
3588 * value of this two fields will not return error when driver
3589 * send command to fireware in revision(0x20).
3591 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
) |
3592 HCLGE_PROMISC_TX_EN_B
| HCLGE_PROMISC_RX_EN_B
;
3594 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3596 dev_err(&hdev
->pdev
->dev
,
3597 "Set promisc mode fail, status is %d.\n", ret
);
3602 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3603 bool en_mc
, bool en_bc
, int vport_id
)
3608 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3610 param
->enable
= HCLGE_PROMISC_EN_UC
;
3612 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3614 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3615 param
->vf_id
= vport_id
;
3618 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, bool en_uc_pmc
,
3621 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3622 struct hclge_dev
*hdev
= vport
->back
;
3623 struct hclge_promisc_param param
;
3625 hclge_promisc_param_init(¶m
, en_uc_pmc
, en_mc_pmc
, true,
3627 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3630 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3632 struct hclge_desc desc
;
3633 struct hclge_config_mac_mode_cmd
*req
=
3634 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3638 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3639 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3640 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3641 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3642 hnae3_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3643 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3644 hnae3_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3645 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3646 hnae3_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3647 hnae3_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3648 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3649 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3650 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3651 hnae3_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3652 hnae3_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3653 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3655 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3657 dev_err(&hdev
->pdev
->dev
,
3658 "mac enable fail, ret =%d.\n", ret
);
3661 static int hclge_set_mac_loopback(struct hclge_dev
*hdev
, bool en
)
3663 struct hclge_config_mac_mode_cmd
*req
;
3664 struct hclge_desc desc
;
3668 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3669 /* 1 Read out the MAC mode config at first */
3670 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, true);
3671 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3673 dev_err(&hdev
->pdev
->dev
,
3674 "mac loopback get fail, ret =%d.\n", ret
);
3678 /* 2 Then setup the loopback flag */
3679 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3680 hnae3_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, en
? 1 : 0);
3682 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3684 /* 3 Config mac work mode with loopback flag
3685 * and its original configure parameters
3687 hclge_cmd_reuse_desc(&desc
, false);
3688 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3690 dev_err(&hdev
->pdev
->dev
,
3691 "mac loopback set fail, ret =%d.\n", ret
);
3695 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3696 enum hnae3_loop loop_mode
, bool en
)
3698 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3699 struct hclge_dev
*hdev
= vport
->back
;
3702 switch (loop_mode
) {
3703 case HNAE3_MAC_INTER_LOOP_MAC
:
3704 ret
= hclge_set_mac_loopback(hdev
, en
);
3708 dev_err(&hdev
->pdev
->dev
,
3709 "loop_mode %d is not supported\n", loop_mode
);
3716 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3717 int stream_id
, bool enable
)
3719 struct hclge_desc desc
;
3720 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3721 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3724 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3725 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3726 req
->stream_id
= cpu_to_le16(stream_id
);
3727 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3729 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3731 dev_err(&hdev
->pdev
->dev
,
3732 "Tqp enable fail, status =%d.\n", ret
);
3736 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3738 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3739 struct hnae3_queue
*queue
;
3740 struct hclge_tqp
*tqp
;
3743 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3744 queue
= handle
->kinfo
.tqp
[i
];
3745 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3746 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3750 static int hclge_ae_start(struct hnae3_handle
*handle
)
3752 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3753 struct hclge_dev
*hdev
= vport
->back
;
3756 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3757 hclge_tqp_enable(hdev
, i
, 0, true);
3760 hclge_cfg_mac_mode(hdev
, true);
3761 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3762 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3763 hdev
->hw
.mac
.link
= 0;
3765 /* reset tqp stats */
3766 hclge_reset_tqp_stats(handle
);
3768 ret
= hclge_mac_start_phy(hdev
);
3775 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3777 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3778 struct hclge_dev
*hdev
= vport
->back
;
3781 del_timer_sync(&hdev
->service_timer
);
3782 cancel_work_sync(&hdev
->service_task
);
3783 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
3785 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
)) {
3786 hclge_mac_stop_phy(hdev
);
3790 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3791 hclge_tqp_enable(hdev
, i
, 0, false);
3794 hclge_cfg_mac_mode(hdev
, false);
3796 hclge_mac_stop_phy(hdev
);
3798 /* reset tqp stats */
3799 hclge_reset_tqp_stats(handle
);
3800 del_timer_sync(&hdev
->service_timer
);
3801 cancel_work_sync(&hdev
->service_task
);
3802 hclge_update_link_status(hdev
);
3805 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3806 u16 cmdq_resp
, u8 resp_code
,
3807 enum hclge_mac_vlan_tbl_opcode op
)
3809 struct hclge_dev
*hdev
= vport
->back
;
3810 int return_status
= -EIO
;
3813 dev_err(&hdev
->pdev
->dev
,
3814 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3819 if (op
== HCLGE_MAC_VLAN_ADD
) {
3820 if ((!resp_code
) || (resp_code
== 1)) {
3822 } else if (resp_code
== 2) {
3823 return_status
= -ENOSPC
;
3824 dev_err(&hdev
->pdev
->dev
,
3825 "add mac addr failed for uc_overflow.\n");
3826 } else if (resp_code
== 3) {
3827 return_status
= -ENOSPC
;
3828 dev_err(&hdev
->pdev
->dev
,
3829 "add mac addr failed for mc_overflow.\n");
3831 dev_err(&hdev
->pdev
->dev
,
3832 "add mac addr failed for undefined, code=%d.\n",
3835 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3838 } else if (resp_code
== 1) {
3839 return_status
= -ENOENT
;
3840 dev_dbg(&hdev
->pdev
->dev
,
3841 "remove mac addr failed for miss.\n");
3843 dev_err(&hdev
->pdev
->dev
,
3844 "remove mac addr failed for undefined, code=%d.\n",
3847 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3850 } else if (resp_code
== 1) {
3851 return_status
= -ENOENT
;
3852 dev_dbg(&hdev
->pdev
->dev
,
3853 "lookup mac addr failed for miss.\n");
3855 dev_err(&hdev
->pdev
->dev
,
3856 "lookup mac addr failed for undefined, code=%d.\n",
3860 return_status
= -EINVAL
;
3861 dev_err(&hdev
->pdev
->dev
,
3862 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3866 return return_status
;
3869 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3874 if (vfid
> 255 || vfid
< 0)
3877 if (vfid
>= 0 && vfid
<= 191) {
3878 word_num
= vfid
/ 32;
3879 bit_num
= vfid
% 32;
3881 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3883 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3885 word_num
= (vfid
- 192) / 32;
3886 bit_num
= vfid
% 32;
3888 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3890 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3896 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3898 #define HCLGE_DESC_NUMBER 3
3899 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3902 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3903 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3904 if (desc
[i
].data
[j
])
3910 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3913 const unsigned char *mac_addr
= addr
;
3914 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3915 (mac_addr
[0]) | (mac_addr
[1] << 8);
3916 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3918 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3919 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3922 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3925 u16 high_val
= addr
[1] | (addr
[0] << 8);
3926 struct hclge_dev
*hdev
= vport
->back
;
3927 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3928 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3933 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3934 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3937 struct hclge_mta_filter_mode_cmd
*req
;
3938 struct hclge_desc desc
;
3941 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3942 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3944 hnae3_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3946 hnae3_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3947 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3949 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3951 dev_err(&hdev
->pdev
->dev
,
3952 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3958 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3962 struct hclge_cfg_func_mta_filter_cmd
*req
;
3963 struct hclge_desc desc
;
3966 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3967 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3969 hnae3_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3971 req
->function_id
= func_id
;
3973 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3975 dev_err(&hdev
->pdev
->dev
,
3976 "Config func_id enable failed for cmd_send, ret =%d.\n",
3982 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
3986 struct hclge_dev
*hdev
= vport
->back
;
3987 struct hclge_cfg_func_mta_item_cmd
*req
;
3988 struct hclge_desc desc
;
3992 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
3993 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
3994 hnae3_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
3996 hnae3_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
3997 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
3998 req
->item_idx
= cpu_to_le16(item_idx
);
4000 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4002 dev_err(&hdev
->pdev
->dev
,
4003 "Config mta table item failed for cmd_send, ret =%d.\n",
4009 set_bit(idx
, vport
->mta_shadow
);
4011 clear_bit(idx
, vport
->mta_shadow
);
4016 static int hclge_update_mta_status(struct hnae3_handle
*handle
)
4018 unsigned long mta_status
[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE
)];
4019 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4020 struct net_device
*netdev
= handle
->kinfo
.netdev
;
4021 struct netdev_hw_addr
*ha
;
4024 memset(mta_status
, 0, sizeof(mta_status
));
4026 /* update mta_status from mc addr list */
4027 netdev_for_each_mc_addr(ha
, netdev
) {
4028 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, ha
->addr
);
4029 set_bit(tbl_idx
, mta_status
);
4032 return hclge_update_mta_status_common(vport
, mta_status
,
4033 0, HCLGE_MTA_TBL_SIZE
, true);
4036 int hclge_update_mta_status_common(struct hclge_vport
*vport
,
4037 unsigned long *status
,
4042 struct hclge_dev
*hdev
= vport
->back
;
4043 u16 update_max
= idx
+ count
;
4049 /* setup mta check range */
4050 if (update_filter
) {
4052 check_max
= HCLGE_MTA_TBL_SIZE
;
4055 check_max
= update_max
;
4059 /* check and update all mta item */
4060 for (; i
< check_max
; i
++) {
4061 /* ignore unused item */
4062 if (!test_bit(i
, vport
->mta_shadow
))
4065 /* if i in update range then update it */
4066 if (i
>= idx
&& i
< update_max
)
4067 if (!test_bit(i
- idx
, status
))
4068 hclge_set_mta_table_item(vport
, i
, false);
4070 if (!used
&& test_bit(i
, vport
->mta_shadow
))
4074 /* no longer use mta, disable it */
4075 if (vport
->accept_mta_mc
&& update_filter
&& !used
) {
4076 ret
= hclge_cfg_func_mta_filter(hdev
,
4080 dev_err(&hdev
->pdev
->dev
,
4081 "disable func mta filter fail ret=%d\n",
4084 vport
->accept_mta_mc
= false;
4090 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4091 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4093 struct hclge_dev
*hdev
= vport
->back
;
4094 struct hclge_desc desc
;
4099 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4101 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4103 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4105 dev_err(&hdev
->pdev
->dev
,
4106 "del mac addr failed for cmd_send, ret =%d.\n",
4110 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4111 retval
= le16_to_cpu(desc
.retval
);
4113 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4114 HCLGE_MAC_VLAN_REMOVE
);
4117 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4118 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4119 struct hclge_desc
*desc
,
4122 struct hclge_dev
*hdev
= vport
->back
;
4127 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4129 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4130 memcpy(desc
[0].data
,
4132 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4133 hclge_cmd_setup_basic_desc(&desc
[1],
4134 HCLGE_OPC_MAC_VLAN_ADD
,
4136 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4137 hclge_cmd_setup_basic_desc(&desc
[2],
4138 HCLGE_OPC_MAC_VLAN_ADD
,
4140 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4142 memcpy(desc
[0].data
,
4144 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4145 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4148 dev_err(&hdev
->pdev
->dev
,
4149 "lookup mac addr failed for cmd_send, ret =%d.\n",
4153 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4154 retval
= le16_to_cpu(desc
[0].retval
);
4156 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4157 HCLGE_MAC_VLAN_LKUP
);
4160 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4161 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4162 struct hclge_desc
*mc_desc
)
4164 struct hclge_dev
*hdev
= vport
->back
;
4171 struct hclge_desc desc
;
4173 hclge_cmd_setup_basic_desc(&desc
,
4174 HCLGE_OPC_MAC_VLAN_ADD
,
4176 memcpy(desc
.data
, req
,
4177 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4178 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4179 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4180 retval
= le16_to_cpu(desc
.retval
);
4182 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4184 HCLGE_MAC_VLAN_ADD
);
4186 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4187 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4188 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4189 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4190 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4191 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4192 memcpy(mc_desc
[0].data
, req
,
4193 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4194 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4195 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4196 retval
= le16_to_cpu(mc_desc
[0].retval
);
4198 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4200 HCLGE_MAC_VLAN_ADD
);
4204 dev_err(&hdev
->pdev
->dev
,
4205 "add mac addr failed for cmd_send, ret =%d.\n",
4213 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4214 const unsigned char *addr
)
4216 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4218 return hclge_add_uc_addr_common(vport
, addr
);
4221 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4222 const unsigned char *addr
)
4224 struct hclge_dev
*hdev
= vport
->back
;
4225 struct hclge_mac_vlan_tbl_entry_cmd req
;
4226 struct hclge_desc desc
;
4227 u16 egress_port
= 0;
4230 /* mac addr check */
4231 if (is_zero_ether_addr(addr
) ||
4232 is_broadcast_ether_addr(addr
) ||
4233 is_multicast_ether_addr(addr
)) {
4234 dev_err(&hdev
->pdev
->dev
,
4235 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4237 is_zero_ether_addr(addr
),
4238 is_broadcast_ether_addr(addr
),
4239 is_multicast_ether_addr(addr
));
4243 memset(&req
, 0, sizeof(req
));
4244 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4246 hnae3_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4247 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4249 req
.egress_port
= cpu_to_le16(egress_port
);
4251 hclge_prepare_mac_addr(&req
, addr
);
4253 /* Lookup the mac address in the mac_vlan table, and add
4254 * it if the entry is inexistent. Repeated unicast entry
4255 * is not allowed in the mac vlan table.
4257 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4259 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4261 /* check if we just hit the duplicate */
4265 dev_err(&hdev
->pdev
->dev
,
4266 "PF failed to add unicast entry(%pM) in the MAC table\n",
4272 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4273 const unsigned char *addr
)
4275 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4277 return hclge_rm_uc_addr_common(vport
, addr
);
4280 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4281 const unsigned char *addr
)
4283 struct hclge_dev
*hdev
= vport
->back
;
4284 struct hclge_mac_vlan_tbl_entry_cmd req
;
4287 /* mac addr check */
4288 if (is_zero_ether_addr(addr
) ||
4289 is_broadcast_ether_addr(addr
) ||
4290 is_multicast_ether_addr(addr
)) {
4291 dev_dbg(&hdev
->pdev
->dev
,
4292 "Remove mac err! invalid mac:%pM.\n",
4297 memset(&req
, 0, sizeof(req
));
4298 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4299 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4300 hclge_prepare_mac_addr(&req
, addr
);
4301 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4306 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4307 const unsigned char *addr
)
4309 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4311 return hclge_add_mc_addr_common(vport
, addr
);
4314 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4315 const unsigned char *addr
)
4317 struct hclge_dev
*hdev
= vport
->back
;
4318 struct hclge_mac_vlan_tbl_entry_cmd req
;
4319 struct hclge_desc desc
[3];
4323 /* mac addr check */
4324 if (!is_multicast_ether_addr(addr
)) {
4325 dev_err(&hdev
->pdev
->dev
,
4326 "Add mc mac err! invalid mac:%pM.\n",
4330 memset(&req
, 0, sizeof(req
));
4331 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4332 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4333 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4334 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4335 hclge_prepare_mac_addr(&req
, addr
);
4336 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4338 /* This mac addr exist, update VFID for it */
4339 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4340 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4342 /* This mac addr do not exist, add new entry for it */
4343 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4344 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4345 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4346 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4347 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4350 /* If mc mac vlan table is full, use MTA table */
4351 if (status
== -ENOSPC
) {
4352 if (!vport
->accept_mta_mc
) {
4353 status
= hclge_cfg_func_mta_filter(hdev
,
4357 dev_err(&hdev
->pdev
->dev
,
4358 "set mta filter mode fail ret=%d\n",
4362 vport
->accept_mta_mc
= true;
4365 /* Set MTA table for this MAC address */
4366 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4367 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4373 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4374 const unsigned char *addr
)
4376 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4378 return hclge_rm_mc_addr_common(vport
, addr
);
4381 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4382 const unsigned char *addr
)
4384 struct hclge_dev
*hdev
= vport
->back
;
4385 struct hclge_mac_vlan_tbl_entry_cmd req
;
4386 enum hclge_cmd_status status
;
4387 struct hclge_desc desc
[3];
4389 /* mac addr check */
4390 if (!is_multicast_ether_addr(addr
)) {
4391 dev_dbg(&hdev
->pdev
->dev
,
4392 "Remove mc mac err! invalid mac:%pM.\n",
4397 memset(&req
, 0, sizeof(req
));
4398 hnae3_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4399 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4400 hnae3_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4401 hnae3_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4402 hclge_prepare_mac_addr(&req
, addr
);
4403 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4405 /* This mac addr exist, remove this handle's VFID for it */
4406 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4408 if (hclge_is_all_function_id_zero(desc
))
4409 /* All the vfid is zero, so need to delete this entry */
4410 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4412 /* Not all the vfid is zero, update the vfid */
4413 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4416 /* Maybe this mac address is in mta table, but it cannot be
4417 * deleted here because an entry of mta represents an address
4418 * range rather than a specific address. the delete action to
4419 * all entries will take effect in update_mta_status called by
4420 * hns3_nic_set_rx_mode.
4428 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4429 u16 cmdq_resp
, u8 resp_code
)
4431 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4432 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4433 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4434 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4439 dev_err(&hdev
->pdev
->dev
,
4440 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4445 switch (resp_code
) {
4446 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4447 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4450 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4451 dev_err(&hdev
->pdev
->dev
,
4452 "add mac ethertype failed for manager table overflow.\n");
4453 return_status
= -EIO
;
4455 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4456 dev_err(&hdev
->pdev
->dev
,
4457 "add mac ethertype failed for key conflict.\n");
4458 return_status
= -EIO
;
4461 dev_err(&hdev
->pdev
->dev
,
4462 "add mac ethertype failed for undefined, code=%d.\n",
4464 return_status
= -EIO
;
4467 return return_status
;
4470 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4471 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4473 struct hclge_desc desc
;
4478 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4479 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4481 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4483 dev_err(&hdev
->pdev
->dev
,
4484 "add mac ethertype failed for cmd_send, ret =%d.\n",
4489 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4490 retval
= le16_to_cpu(desc
.retval
);
4492 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4495 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4500 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4501 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4503 dev_err(&hdev
->pdev
->dev
,
4504 "add mac ethertype failed, ret =%d.\n",
4513 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4515 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4516 struct hclge_dev
*hdev
= vport
->back
;
4518 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4521 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4524 const unsigned char *new_addr
= (const unsigned char *)p
;
4525 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4526 struct hclge_dev
*hdev
= vport
->back
;
4529 /* mac addr check */
4530 if (is_zero_ether_addr(new_addr
) ||
4531 is_broadcast_ether_addr(new_addr
) ||
4532 is_multicast_ether_addr(new_addr
)) {
4533 dev_err(&hdev
->pdev
->dev
,
4534 "Change uc mac err! invalid mac:%p.\n",
4539 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4540 dev_warn(&hdev
->pdev
->dev
,
4541 "remove old uc mac address fail.\n");
4543 ret
= hclge_add_uc_addr(handle
, new_addr
);
4545 dev_err(&hdev
->pdev
->dev
,
4546 "add uc mac address fail, ret =%d.\n",
4550 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4551 dev_err(&hdev
->pdev
->dev
,
4552 "restore uc mac address fail.\n");
4557 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4559 dev_err(&hdev
->pdev
->dev
,
4560 "configure mac pause address fail, ret =%d.\n",
4565 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4570 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4573 struct hclge_vlan_filter_ctrl_cmd
*req
;
4574 struct hclge_desc desc
;
4577 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4579 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4580 req
->vlan_type
= vlan_type
;
4581 req
->vlan_fe
= filter_en
;
4583 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4585 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4591 #define HCLGE_FILTER_TYPE_VF 0
4592 #define HCLGE_FILTER_TYPE_PORT 1
4594 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4596 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4597 struct hclge_dev
*hdev
= vport
->back
;
4599 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4602 static int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4603 bool is_kill
, u16 vlan
, u8 qos
,
4606 #define HCLGE_MAX_VF_BYTES 16
4607 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4608 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4609 struct hclge_desc desc
[2];
4614 hclge_cmd_setup_basic_desc(&desc
[0],
4615 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4616 hclge_cmd_setup_basic_desc(&desc
[1],
4617 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4619 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4621 vf_byte_off
= vfid
/ 8;
4622 vf_byte_val
= 1 << (vfid
% 8);
4624 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4625 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4627 req0
->vlan_id
= cpu_to_le16(vlan
);
4628 req0
->vlan_cfg
= is_kill
;
4630 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4631 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4633 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4635 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4637 dev_err(&hdev
->pdev
->dev
,
4638 "Send vf vlan command fail, ret =%d.\n",
4644 #define HCLGE_VF_VLAN_NO_ENTRY 2
4645 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4648 if (req0
->resp_code
== HCLGE_VF_VLAN_NO_ENTRY
) {
4649 dev_warn(&hdev
->pdev
->dev
,
4650 "vf vlan table is full, vf vlan filter is disabled\n");
4654 dev_err(&hdev
->pdev
->dev
,
4655 "Add vf vlan filter fail, ret =%d.\n",
4658 if (!req0
->resp_code
)
4661 dev_err(&hdev
->pdev
->dev
,
4662 "Kill vf vlan filter fail, ret =%d.\n",
4669 static int hclge_set_port_vlan_filter(struct hclge_dev
*hdev
, __be16 proto
,
4670 u16 vlan_id
, bool is_kill
)
4672 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4673 struct hclge_desc desc
;
4674 u8 vlan_offset_byte_val
;
4675 u8 vlan_offset_byte
;
4679 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4681 vlan_offset_160
= vlan_id
/ 160;
4682 vlan_offset_byte
= (vlan_id
% 160) / 8;
4683 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4685 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4686 req
->vlan_offset
= vlan_offset_160
;
4687 req
->vlan_cfg
= is_kill
;
4688 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4690 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4692 dev_err(&hdev
->pdev
->dev
,
4693 "port vlan command, send fail, ret =%d.\n", ret
);
4697 static int hclge_set_vlan_filter_hw(struct hclge_dev
*hdev
, __be16 proto
,
4698 u16 vport_id
, u16 vlan_id
, u8 qos
,
4701 u16 vport_idx
, vport_num
= 0;
4704 ret
= hclge_set_vf_vlan_common(hdev
, vport_id
, is_kill
, vlan_id
,
4707 dev_err(&hdev
->pdev
->dev
,
4708 "Set %d vport vlan filter config fail, ret =%d.\n",
4713 /* vlan 0 may be added twice when 8021q module is enabled */
4714 if (!is_kill
&& !vlan_id
&&
4715 test_bit(vport_id
, hdev
->vlan_table
[vlan_id
]))
4718 if (!is_kill
&& test_and_set_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4719 dev_err(&hdev
->pdev
->dev
,
4720 "Add port vlan failed, vport %d is already in vlan %d\n",
4726 !test_and_clear_bit(vport_id
, hdev
->vlan_table
[vlan_id
])) {
4727 dev_err(&hdev
->pdev
->dev
,
4728 "Delete port vlan failed, vport %d is not in vlan %d\n",
4733 for_each_set_bit(vport_idx
, hdev
->vlan_table
[vlan_id
], VLAN_N_VID
)
4736 if ((is_kill
&& vport_num
== 0) || (!is_kill
&& vport_num
== 1))
4737 ret
= hclge_set_port_vlan_filter(hdev
, proto
, vlan_id
,
4743 int hclge_set_vlan_filter(struct hnae3_handle
*handle
, __be16 proto
,
4744 u16 vlan_id
, bool is_kill
)
4746 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4747 struct hclge_dev
*hdev
= vport
->back
;
4749 return hclge_set_vlan_filter_hw(hdev
, proto
, vport
->vport_id
, vlan_id
,
4753 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4754 u16 vlan
, u8 qos
, __be16 proto
)
4756 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4757 struct hclge_dev
*hdev
= vport
->back
;
4759 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4761 if (proto
!= htons(ETH_P_8021Q
))
4762 return -EPROTONOSUPPORT
;
4764 return hclge_set_vlan_filter_hw(hdev
, proto
, vfid
, vlan
, qos
, false);
4767 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4769 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4770 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4771 struct hclge_dev
*hdev
= vport
->back
;
4772 struct hclge_desc desc
;
4775 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4777 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4778 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4779 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4780 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG1_B
,
4781 vcfg
->accept_tag1
? 1 : 0);
4782 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG1_B
,
4783 vcfg
->accept_untag1
? 1 : 0);
4784 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG2_B
,
4785 vcfg
->accept_tag2
? 1 : 0);
4786 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG2_B
,
4787 vcfg
->accept_untag2
? 1 : 0);
4788 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4789 vcfg
->insert_tag1_en
? 1 : 0);
4790 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4791 vcfg
->insert_tag2_en
? 1 : 0);
4792 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4794 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4795 req
->vf_bitmap
[req
->vf_offset
] =
4796 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4798 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4800 dev_err(&hdev
->pdev
->dev
,
4801 "Send port txvlan cfg command fail, ret =%d\n",
4807 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4809 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4810 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4811 struct hclge_dev
*hdev
= vport
->back
;
4812 struct hclge_desc desc
;
4815 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4817 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4818 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4819 vcfg
->strip_tag1_en
? 1 : 0);
4820 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4821 vcfg
->strip_tag2_en
? 1 : 0);
4822 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4823 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4824 hnae3_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4825 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4827 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4828 req
->vf_bitmap
[req
->vf_offset
] =
4829 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4831 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4833 dev_err(&hdev
->pdev
->dev
,
4834 "Send port rxvlan cfg command fail, ret =%d\n",
4840 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4842 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4843 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4844 struct hclge_desc desc
;
4847 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4848 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4849 rx_req
->ot_fst_vlan_type
=
4850 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4851 rx_req
->ot_sec_vlan_type
=
4852 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4853 rx_req
->in_fst_vlan_type
=
4854 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4855 rx_req
->in_sec_vlan_type
=
4856 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4858 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4860 dev_err(&hdev
->pdev
->dev
,
4861 "Send rxvlan protocol type command fail, ret =%d\n",
4866 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4868 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4869 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4870 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4872 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4874 dev_err(&hdev
->pdev
->dev
,
4875 "Send txvlan protocol type command fail, ret =%d\n",
4881 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4883 #define HCLGE_DEF_VLAN_TYPE 0x8100
4885 struct hnae3_handle
*handle
;
4886 struct hclge_vport
*vport
;
4890 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4894 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4898 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4899 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4900 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4901 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4902 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4903 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4905 ret
= hclge_set_vlan_protocol_type(hdev
);
4909 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4910 vport
= &hdev
->vport
[i
];
4911 vport
->txvlan_cfg
.accept_tag1
= true;
4912 vport
->txvlan_cfg
.accept_untag1
= true;
4914 /* accept_tag2 and accept_untag2 are not supported on
4915 * pdev revision(0x20), new revision support them. The
4916 * value of this two fields will not return error when driver
4917 * send command to fireware in revision(0x20).
4918 * This two fields can not configured by user.
4920 vport
->txvlan_cfg
.accept_tag2
= true;
4921 vport
->txvlan_cfg
.accept_untag2
= true;
4923 vport
->txvlan_cfg
.insert_tag1_en
= false;
4924 vport
->txvlan_cfg
.insert_tag2_en
= false;
4925 vport
->txvlan_cfg
.default_tag1
= 0;
4926 vport
->txvlan_cfg
.default_tag2
= 0;
4928 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4932 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4933 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4934 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4935 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4937 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4942 handle
= &hdev
->vport
[0].nic
;
4943 return hclge_set_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4946 int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4948 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4950 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4951 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4952 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4953 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4955 return hclge_set_vlan_rx_offload_cfg(vport
);
4958 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
4960 struct hclge_config_max_frm_size_cmd
*req
;
4961 struct hclge_desc desc
;
4965 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
4967 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
4968 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
4971 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
4973 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4975 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4976 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
4977 req
->min_frm_size
= HCLGE_MAC_MIN_FRAME
;
4979 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4981 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4983 hdev
->mps
= max_frm_size
;
4988 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4990 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4991 struct hclge_dev
*hdev
= vport
->back
;
4994 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
4996 dev_err(&hdev
->pdev
->dev
,
4997 "Change mtu fail, ret =%d\n", ret
);
5001 ret
= hclge_buffer_alloc(hdev
);
5003 dev_err(&hdev
->pdev
->dev
,
5004 "Allocate buffer fail, ret =%d\n", ret
);
5009 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
5012 struct hclge_reset_tqp_queue_cmd
*req
;
5013 struct hclge_desc desc
;
5016 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
5018 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5019 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5020 hnae3_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
5022 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5024 dev_err(&hdev
->pdev
->dev
,
5025 "Send tqp reset cmd error, status =%d\n", ret
);
5032 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
5034 struct hclge_reset_tqp_queue_cmd
*req
;
5035 struct hclge_desc desc
;
5038 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
5040 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
5041 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
5043 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5045 dev_err(&hdev
->pdev
->dev
,
5046 "Get reset status error, status =%d\n", ret
);
5050 return hnae3_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
5053 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
5056 struct hnae3_queue
*queue
;
5057 struct hclge_tqp
*tqp
;
5059 queue
= handle
->kinfo
.tqp
[queue_id
];
5060 tqp
= container_of(queue
, struct hclge_tqp
, q
);
5065 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
5067 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5068 struct hclge_dev
*hdev
= vport
->back
;
5069 int reset_try_times
= 0;
5074 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
5077 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
5079 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
5081 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
5085 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5087 dev_warn(&hdev
->pdev
->dev
,
5088 "Send reset tqp cmd fail, ret = %d\n", ret
);
5092 reset_try_times
= 0;
5093 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5094 /* Wait for tqp hw reset */
5096 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5101 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5102 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5106 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5108 dev_warn(&hdev
->pdev
->dev
,
5109 "Deassert the soft reset fail, ret = %d\n", ret
);
5114 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
5116 struct hclge_dev
*hdev
= vport
->back
;
5117 int reset_try_times
= 0;
5122 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5124 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5126 dev_warn(&hdev
->pdev
->dev
,
5127 "Send reset tqp cmd fail, ret = %d\n", ret
);
5131 reset_try_times
= 0;
5132 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5133 /* Wait for tqp hw reset */
5135 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5140 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5141 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5145 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5147 dev_warn(&hdev
->pdev
->dev
,
5148 "Deassert the soft reset fail, ret = %d\n", ret
);
5151 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5153 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5154 struct hclge_dev
*hdev
= vport
->back
;
5156 return hdev
->fw_version
;
5159 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5162 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5163 struct hclge_dev
*hdev
= vport
->back
;
5164 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5169 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5170 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5173 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5175 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5180 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5183 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5186 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5189 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5194 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5195 else if (rx_en
&& !tx_en
)
5196 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5197 else if (!rx_en
&& tx_en
)
5198 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5200 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5202 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5205 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5207 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5212 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5217 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5219 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5220 u16 remote_advertising
= 0;
5221 u16 local_advertising
= 0;
5222 u32 rx_pause
, tx_pause
;
5225 if (!phydev
->link
|| !phydev
->autoneg
)
5228 if (phydev
->advertising
& ADVERTISED_Pause
)
5229 local_advertising
= ADVERTISE_PAUSE_CAP
;
5231 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5232 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5235 remote_advertising
= LPA_PAUSE_CAP
;
5237 if (phydev
->asym_pause
)
5238 remote_advertising
|= LPA_PAUSE_ASYM
;
5240 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5241 remote_advertising
);
5242 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5243 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5245 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5250 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5253 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5254 u32
*rx_en
, u32
*tx_en
)
5256 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5257 struct hclge_dev
*hdev
= vport
->back
;
5259 *auto_neg
= hclge_get_autoneg(handle
);
5261 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5267 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5270 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5273 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5282 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5283 u32 rx_en
, u32 tx_en
)
5285 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5286 struct hclge_dev
*hdev
= vport
->back
;
5287 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5290 fc_autoneg
= hclge_get_autoneg(handle
);
5291 if (auto_neg
!= fc_autoneg
) {
5292 dev_info(&hdev
->pdev
->dev
,
5293 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5297 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5298 dev_info(&hdev
->pdev
->dev
,
5299 "Priority flow control enabled. Cannot set link flow control.\n");
5303 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5306 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5308 /* Only support flow control negotiation for netdev with
5309 * phy attached for now.
5314 return phy_start_aneg(phydev
);
5317 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5318 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5320 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5321 struct hclge_dev
*hdev
= vport
->back
;
5324 *speed
= hdev
->hw
.mac
.speed
;
5326 *duplex
= hdev
->hw
.mac
.duplex
;
5328 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5331 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5333 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5334 struct hclge_dev
*hdev
= vport
->back
;
5337 *media_type
= hdev
->hw
.mac
.media_type
;
5340 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5341 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5343 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5344 struct hclge_dev
*hdev
= vport
->back
;
5345 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5346 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5349 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5350 *tp_mdix
= ETH_TP_MDI_INVALID
;
5354 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5356 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5357 mdix_ctrl
= hnae3_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5358 HCLGE_PHY_MDIX_CTRL_S
);
5360 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5361 mdix
= hnae3_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5362 is_resolved
= hnae3_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5364 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5366 switch (mdix_ctrl
) {
5368 *tp_mdix_ctrl
= ETH_TP_MDI
;
5371 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5374 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5377 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5382 *tp_mdix
= ETH_TP_MDI_INVALID
;
5384 *tp_mdix
= ETH_TP_MDI_X
;
5386 *tp_mdix
= ETH_TP_MDI
;
5389 static int hclge_init_client_instance(struct hnae3_client
*client
,
5390 struct hnae3_ae_dev
*ae_dev
)
5392 struct hclge_dev
*hdev
= ae_dev
->priv
;
5393 struct hclge_vport
*vport
;
5396 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5397 vport
= &hdev
->vport
[i
];
5399 switch (client
->type
) {
5400 case HNAE3_CLIENT_KNIC
:
5402 hdev
->nic_client
= client
;
5403 vport
->nic
.client
= client
;
5404 ret
= client
->ops
->init_instance(&vport
->nic
);
5408 if (hdev
->roce_client
&&
5409 hnae3_dev_roce_supported(hdev
)) {
5410 struct hnae3_client
*rc
= hdev
->roce_client
;
5412 ret
= hclge_init_roce_base_info(vport
);
5416 ret
= rc
->ops
->init_instance(&vport
->roce
);
5422 case HNAE3_CLIENT_UNIC
:
5423 hdev
->nic_client
= client
;
5424 vport
->nic
.client
= client
;
5426 ret
= client
->ops
->init_instance(&vport
->nic
);
5431 case HNAE3_CLIENT_ROCE
:
5432 if (hnae3_dev_roce_supported(hdev
)) {
5433 hdev
->roce_client
= client
;
5434 vport
->roce
.client
= client
;
5437 if (hdev
->roce_client
&& hdev
->nic_client
) {
5438 ret
= hclge_init_roce_base_info(vport
);
5442 ret
= client
->ops
->init_instance(&vport
->roce
);
5452 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5453 struct hnae3_ae_dev
*ae_dev
)
5455 struct hclge_dev
*hdev
= ae_dev
->priv
;
5456 struct hclge_vport
*vport
;
5459 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5460 vport
= &hdev
->vport
[i
];
5461 if (hdev
->roce_client
) {
5462 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5464 hdev
->roce_client
= NULL
;
5465 vport
->roce
.client
= NULL
;
5467 if (client
->type
== HNAE3_CLIENT_ROCE
)
5469 if (client
->ops
->uninit_instance
) {
5470 client
->ops
->uninit_instance(&vport
->nic
, 0);
5471 hdev
->nic_client
= NULL
;
5472 vport
->nic
.client
= NULL
;
5477 static int hclge_pci_init(struct hclge_dev
*hdev
)
5479 struct pci_dev
*pdev
= hdev
->pdev
;
5480 struct hclge_hw
*hw
;
5483 ret
= pci_enable_device(pdev
);
5485 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5489 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5491 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5494 "can't set consistent PCI DMA");
5495 goto err_disable_device
;
5497 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5500 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5502 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5503 goto err_disable_device
;
5506 pci_set_master(pdev
);
5508 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5510 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5512 goto err_clr_master
;
5515 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5519 pci_clear_master(pdev
);
5520 pci_release_regions(pdev
);
5522 pci_disable_device(pdev
);
5527 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5529 struct pci_dev
*pdev
= hdev
->pdev
;
5531 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5532 pci_free_irq_vectors(pdev
);
5533 pci_clear_master(pdev
);
5534 pci_release_mem_regions(pdev
);
5535 pci_disable_device(pdev
);
5538 static void hclge_state_init(struct hclge_dev
*hdev
)
5540 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5541 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5542 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5543 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5544 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5545 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5548 static void hclge_state_uninit(struct hclge_dev
*hdev
)
5550 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5552 if (hdev
->service_timer
.function
)
5553 del_timer_sync(&hdev
->service_timer
);
5554 if (hdev
->service_task
.func
)
5555 cancel_work_sync(&hdev
->service_task
);
5556 if (hdev
->rst_service_task
.func
)
5557 cancel_work_sync(&hdev
->rst_service_task
);
5558 if (hdev
->mbx_service_task
.func
)
5559 cancel_work_sync(&hdev
->mbx_service_task
);
5562 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5564 struct pci_dev
*pdev
= ae_dev
->pdev
;
5565 struct hclge_dev
*hdev
;
5568 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5575 hdev
->ae_dev
= ae_dev
;
5576 hdev
->reset_type
= HNAE3_NONE_RESET
;
5577 ae_dev
->priv
= hdev
;
5579 ret
= hclge_pci_init(hdev
);
5581 dev_err(&pdev
->dev
, "PCI init failed\n");
5585 /* Firmware command queue initialize */
5586 ret
= hclge_cmd_queue_init(hdev
);
5588 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5589 goto err_pci_uninit
;
5592 /* Firmware command initialize */
5593 ret
= hclge_cmd_init(hdev
);
5595 goto err_cmd_uninit
;
5597 ret
= hclge_get_cap(hdev
);
5599 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5601 goto err_cmd_uninit
;
5604 ret
= hclge_configure(hdev
);
5606 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5607 goto err_cmd_uninit
;
5610 ret
= hclge_init_msi(hdev
);
5612 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5613 goto err_cmd_uninit
;
5616 ret
= hclge_misc_irq_init(hdev
);
5619 "Misc IRQ(vector0) init error, ret = %d.\n",
5621 goto err_msi_uninit
;
5624 ret
= hclge_alloc_tqps(hdev
);
5626 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5627 goto err_msi_irq_uninit
;
5630 ret
= hclge_alloc_vport(hdev
);
5632 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5633 goto err_msi_irq_uninit
;
5636 ret
= hclge_map_tqp(hdev
);
5638 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5639 goto err_msi_irq_uninit
;
5642 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5643 ret
= hclge_mac_mdio_config(hdev
);
5645 dev_err(&hdev
->pdev
->dev
,
5646 "mdio config fail ret=%d\n", ret
);
5647 goto err_msi_irq_uninit
;
5651 ret
= hclge_mac_init(hdev
);
5653 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5654 goto err_mdiobus_unreg
;
5657 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5659 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5660 goto err_mdiobus_unreg
;
5663 ret
= hclge_init_vlan_config(hdev
);
5665 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5666 goto err_mdiobus_unreg
;
5669 ret
= hclge_tm_schd_init(hdev
);
5671 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5672 goto err_mdiobus_unreg
;
5675 hclge_rss_init_cfg(hdev
);
5676 ret
= hclge_rss_init_hw(hdev
);
5678 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5679 goto err_mdiobus_unreg
;
5682 ret
= init_mgr_tbl(hdev
);
5684 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5685 goto err_mdiobus_unreg
;
5688 hclge_dcb_ops_set(hdev
);
5690 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5691 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5692 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5693 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5695 hclge_clear_all_event_cause(hdev
);
5697 /* Enable MISC vector(vector0) */
5698 hclge_enable_vector(&hdev
->misc_vector
, true);
5700 hclge_state_init(hdev
);
5702 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5706 if (hdev
->hw
.mac
.phydev
)
5707 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5709 hclge_misc_irq_uninit(hdev
);
5711 pci_free_irq_vectors(pdev
);
5713 hclge_destroy_cmd_queue(&hdev
->hw
);
5715 pcim_iounmap(pdev
, hdev
->hw
.io_base
);
5716 pci_clear_master(pdev
);
5717 pci_release_regions(pdev
);
5718 pci_disable_device(pdev
);
5723 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5725 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5728 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5730 struct hclge_dev
*hdev
= ae_dev
->priv
;
5731 struct pci_dev
*pdev
= ae_dev
->pdev
;
5734 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5736 hclge_stats_clear(hdev
);
5737 memset(hdev
->vlan_table
, 0, sizeof(hdev
->vlan_table
));
5739 ret
= hclge_cmd_init(hdev
);
5741 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5745 ret
= hclge_get_cap(hdev
);
5747 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5752 ret
= hclge_configure(hdev
);
5754 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5758 ret
= hclge_map_tqp(hdev
);
5760 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5764 ret
= hclge_mac_init(hdev
);
5766 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5770 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5772 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5776 ret
= hclge_init_vlan_config(hdev
);
5778 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5782 ret
= hclge_tm_init_hw(hdev
);
5784 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5788 ret
= hclge_rss_init_hw(hdev
);
5790 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5794 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5800 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5802 struct hclge_dev
*hdev
= ae_dev
->priv
;
5803 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5805 hclge_state_uninit(hdev
);
5808 mdiobus_unregister(mac
->mdio_bus
);
5810 /* Disable MISC vector(vector0) */
5811 hclge_enable_vector(&hdev
->misc_vector
, false);
5812 synchronize_irq(hdev
->misc_vector
.vector_irq
);
5814 hclge_destroy_cmd_queue(&hdev
->hw
);
5815 hclge_misc_irq_uninit(hdev
);
5816 hclge_pci_uninit(hdev
);
5817 ae_dev
->priv
= NULL
;
5820 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5822 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5823 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5824 struct hclge_dev
*hdev
= vport
->back
;
5826 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5829 static void hclge_get_channels(struct hnae3_handle
*handle
,
5830 struct ethtool_channels
*ch
)
5832 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5834 ch
->max_combined
= hclge_get_max_channels(handle
);
5835 ch
->other_count
= 1;
5837 ch
->combined_count
= vport
->alloc_tqps
;
5840 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5841 u16
*free_tqps
, u16
*max_rss_size
)
5843 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5844 struct hclge_dev
*hdev
= vport
->back
;
5848 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5849 if (!hdev
->htqp
[i
].alloced
)
5852 *free_tqps
= temp_tqps
;
5853 *max_rss_size
= hdev
->rss_size_max
;
5856 static void hclge_release_tqp(struct hclge_vport
*vport
)
5858 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5859 struct hclge_dev
*hdev
= vport
->back
;
5862 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5863 struct hclge_tqp
*tqp
=
5864 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5866 tqp
->q
.handle
= NULL
;
5867 tqp
->q
.tqp_index
= 0;
5868 tqp
->alloced
= false;
5871 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5875 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5877 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5878 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5879 struct hclge_dev
*hdev
= vport
->back
;
5880 int cur_rss_size
= kinfo
->rss_size
;
5881 int cur_tqps
= kinfo
->num_tqps
;
5882 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5883 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5884 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5889 /* Free old tqps, and reallocate with new tqp number when nic setup */
5890 hclge_release_tqp(vport
);
5892 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5894 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5898 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5900 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5904 ret
= hclge_tm_schd_init(hdev
);
5906 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5910 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5911 roundup_size
= ilog2(roundup_size
);
5912 /* Set the RSS TC mode according to the new RSS size */
5913 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5916 if (!(hdev
->hw_tc_map
& BIT(i
)))
5920 tc_size
[i
] = roundup_size
;
5921 tc_offset
[i
] = kinfo
->rss_size
* i
;
5923 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5927 /* Reinitializes the rss indirect table according to the new RSS size */
5928 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5932 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5933 rss_indir
[i
] = i
% kinfo
->rss_size
;
5935 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5937 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5943 dev_info(&hdev
->pdev
->dev
,
5944 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5945 cur_rss_size
, kinfo
->rss_size
,
5946 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5951 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5952 u32
*regs_num_64_bit
)
5954 struct hclge_desc desc
;
5958 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
5959 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5961 dev_err(&hdev
->pdev
->dev
,
5962 "Query register number cmd failed, ret = %d.\n", ret
);
5966 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
5967 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
5969 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
5976 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5979 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
5981 struct hclge_desc
*desc
;
5982 u32
*reg_val
= data
;
5991 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
5992 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5996 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
5997 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5999 dev_err(&hdev
->pdev
->dev
,
6000 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
6005 for (i
= 0; i
< cmd_num
; i
++) {
6007 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
6008 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
6010 desc_data
= (__le32
*)(&desc
[i
]);
6011 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
6013 for (k
= 0; k
< n
; k
++) {
6014 *reg_val
++ = le32_to_cpu(*desc_data
++);
6026 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
6029 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6031 struct hclge_desc
*desc
;
6032 u64
*reg_val
= data
;
6041 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
6042 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
6046 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
6047 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
6049 dev_err(&hdev
->pdev
->dev
,
6050 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
6055 for (i
= 0; i
< cmd_num
; i
++) {
6057 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
6058 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
6060 desc_data
= (__le64
*)(&desc
[i
]);
6061 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
6063 for (k
= 0; k
< n
; k
++) {
6064 *reg_val
++ = le64_to_cpu(*desc_data
++);
6076 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
6078 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6079 struct hclge_dev
*hdev
= vport
->back
;
6080 u32 regs_num_32_bit
, regs_num_64_bit
;
6083 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6085 dev_err(&hdev
->pdev
->dev
,
6086 "Get register number failed, ret = %d.\n", ret
);
6090 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
6093 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
6096 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6097 struct hclge_dev
*hdev
= vport
->back
;
6098 u32 regs_num_32_bit
, regs_num_64_bit
;
6101 *version
= hdev
->fw_version
;
6103 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
6105 dev_err(&hdev
->pdev
->dev
,
6106 "Get register number failed, ret = %d.\n", ret
);
6110 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
6112 dev_err(&hdev
->pdev
->dev
,
6113 "Get 32 bit register failed, ret = %d.\n", ret
);
6117 data
= (u32
*)data
+ regs_num_32_bit
;
6118 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
6121 dev_err(&hdev
->pdev
->dev
,
6122 "Get 64 bit register failed, ret = %d.\n", ret
);
6125 static int hclge_set_led_status(struct hclge_dev
*hdev
, u8 locate_led_status
)
6127 struct hclge_set_led_state_cmd
*req
;
6128 struct hclge_desc desc
;
6131 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6133 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6134 hnae3_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6135 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6137 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6139 dev_err(&hdev
->pdev
->dev
,
6140 "Send set led state cmd error, ret =%d\n", ret
);
6145 enum hclge_led_status
{
6148 HCLGE_LED_NO_CHANGE
= 0xFF,
6151 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6152 enum ethtool_phys_id_state status
)
6154 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6155 struct hclge_dev
*hdev
= vport
->back
;
6158 case ETHTOOL_ID_ACTIVE
:
6159 return hclge_set_led_status(hdev
, HCLGE_LED_ON
);
6160 case ETHTOOL_ID_INACTIVE
:
6161 return hclge_set_led_status(hdev
, HCLGE_LED_OFF
);
6167 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6168 unsigned long *supported
,
6169 unsigned long *advertising
)
6171 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6172 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6173 struct hclge_dev
*hdev
= vport
->back
;
6174 unsigned int idx
= 0;
6176 for (; idx
< size
; idx
++) {
6177 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6178 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6182 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6185 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6186 struct hclge_dev
*hdev
= vport
->back
;
6187 u8 media_type
= hdev
->hw
.mac
.media_type
;
6189 switch (media_type
) {
6190 case HNAE3_MEDIA_TYPE_FIBER
:
6191 *port_type
= PORT_FIBRE
;
6193 case HNAE3_MEDIA_TYPE_COPPER
:
6194 *port_type
= PORT_TP
;
6196 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6198 *port_type
= PORT_OTHER
;
6203 static const struct hnae3_ae_ops hclge_ops
= {
6204 .init_ae_dev
= hclge_init_ae_dev
,
6205 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6206 .init_client_instance
= hclge_init_client_instance
,
6207 .uninit_client_instance
= hclge_uninit_client_instance
,
6208 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6209 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6210 .get_vector
= hclge_get_vector
,
6211 .put_vector
= hclge_put_vector
,
6212 .set_promisc_mode
= hclge_set_promisc_mode
,
6213 .set_loopback
= hclge_set_loopback
,
6214 .start
= hclge_ae_start
,
6215 .stop
= hclge_ae_stop
,
6216 .get_status
= hclge_get_status
,
6217 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6218 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6219 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6220 .get_media_type
= hclge_get_media_type
,
6221 .get_rss_key_size
= hclge_get_rss_key_size
,
6222 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6223 .get_rss
= hclge_get_rss
,
6224 .set_rss
= hclge_set_rss
,
6225 .set_rss_tuple
= hclge_set_rss_tuple
,
6226 .get_rss_tuple
= hclge_get_rss_tuple
,
6227 .get_tc_size
= hclge_get_tc_size
,
6228 .get_mac_addr
= hclge_get_mac_addr
,
6229 .set_mac_addr
= hclge_set_mac_addr
,
6230 .add_uc_addr
= hclge_add_uc_addr
,
6231 .rm_uc_addr
= hclge_rm_uc_addr
,
6232 .add_mc_addr
= hclge_add_mc_addr
,
6233 .rm_mc_addr
= hclge_rm_mc_addr
,
6234 .update_mta_status
= hclge_update_mta_status
,
6235 .set_autoneg
= hclge_set_autoneg
,
6236 .get_autoneg
= hclge_get_autoneg
,
6237 .get_pauseparam
= hclge_get_pauseparam
,
6238 .set_pauseparam
= hclge_set_pauseparam
,
6239 .set_mtu
= hclge_set_mtu
,
6240 .reset_queue
= hclge_reset_tqp
,
6241 .get_stats
= hclge_get_stats
,
6242 .update_stats
= hclge_update_stats
,
6243 .get_strings
= hclge_get_strings
,
6244 .get_sset_count
= hclge_get_sset_count
,
6245 .get_fw_version
= hclge_get_fw_version
,
6246 .get_mdix_mode
= hclge_get_mdix_mode
,
6247 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6248 .set_vlan_filter
= hclge_set_vlan_filter
,
6249 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6250 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6251 .reset_event
= hclge_reset_event
,
6252 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6253 .set_channels
= hclge_set_channels
,
6254 .get_channels
= hclge_get_channels
,
6255 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6256 .get_regs_len
= hclge_get_regs_len
,
6257 .get_regs
= hclge_get_regs
,
6258 .set_led_id
= hclge_set_led_id
,
6259 .get_link_mode
= hclge_get_link_mode
,
6260 .get_port_type
= hclge_get_port_type
,
6263 static struct hnae3_ae_algo ae_algo
= {
6265 .pdev_id_table
= ae_algo_pci_tbl
,
6268 static int hclge_init(void)
6270 pr_info("%s is initializing\n", HCLGE_NAME
);
6272 hnae3_register_ae_algo(&ae_algo
);
6277 static void hclge_exit(void)
6279 hnae3_unregister_ae_algo(&ae_algo
);
6281 module_init(hclge_init
);
6282 module_exit(hclge_exit
);
6284 MODULE_LICENSE("GPL");
6285 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6286 MODULE_DESCRIPTION("HCLGE Driver");
6287 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob