drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

   1 /*
   2  * Copyright (c) 2016~2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __HCLGE_MAIN_H
  11 #define __HCLGE_MAIN_H
  12 #include <linux/fs.h>
  13 #include <linux/types.h>
  14 #include <linux/phy.h>
  15 #include "hclge_cmd.h"
  16 #include "hnae3.h"
  17
  18 #define HCLGE_MOD_VERSION "v1.0"
  19 #define HCLGE_DRIVER_NAME "hclge"
  20
  21 #define HCLGE_INVALID_VPORT 0xffff
  22
  23 #define HCLGE_ROCE_VECTOR_OFFSET        96
  24
  25 #define HCLGE_PF_CFG_BLOCK_SIZE         32
  26 #define HCLGE_PF_CFG_DESC_NUM \
  27         (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
  28
  29 #define HCLGE_VECTOR_REG_BASE           0x20000
  30 #define HCLGE_MISC_VECTOR_REG_BASE      0x20400
  31
  32 #define HCLGE_VECTOR_REG_OFFSET         0x4
  33 #define HCLGE_VECTOR_VF_OFFSET          0x100000
  34
  35 #define HCLGE_RSS_IND_TBL_SIZE          512
  36 #define HCLGE_RSS_SET_BITMAP_MSK        GENMASK(15, 0)
  37 #define HCLGE_RSS_KEY_SIZE              40
  38 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ    0
  39 #define HCLGE_RSS_HASH_ALGO_SIMPLE      1
  40 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC   2
  41 #define HCLGE_RSS_HASH_ALGO_MASK        0xf
  42 #define HCLGE_RSS_CFG_TBL_NUM \
  43         (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
  44
  45 #define HCLGE_RSS_INPUT_TUPLE_OTHER     GENMASK(3, 0)
  46 #define HCLGE_RSS_INPUT_TUPLE_SCTP      GENMASK(4, 0)
  47 #define HCLGE_D_PORT_BIT                BIT(0)
  48 #define HCLGE_S_PORT_BIT                BIT(1)
  49 #define HCLGE_D_IP_BIT                  BIT(2)
  50 #define HCLGE_S_IP_BIT                  BIT(3)
  51 #define HCLGE_V_TAG_BIT                 BIT(4)
  52
  53 #define HCLGE_RSS_TC_SIZE_0             1
  54 #define HCLGE_RSS_TC_SIZE_1             2
  55 #define HCLGE_RSS_TC_SIZE_2             4
  56 #define HCLGE_RSS_TC_SIZE_3             8
  57 #define HCLGE_RSS_TC_SIZE_4             16
  58 #define HCLGE_RSS_TC_SIZE_5             32
  59 #define HCLGE_RSS_TC_SIZE_6             64
  60 #define HCLGE_RSS_TC_SIZE_7             128
  61
  62 #define HCLGE_TQP_RESET_TRY_TIMES       10
  63
  64 #define HCLGE_PHY_PAGE_MDIX             0
  65 #define HCLGE_PHY_PAGE_COPPER           0
  66
  67 /* Page Selection Reg. */
  68 #define HCLGE_PHY_PAGE_REG              22
  69
  70 /* Copper Specific Control Register */
  71 #define HCLGE_PHY_CSC_REG               16
  72
  73 /* Copper Specific Status Register */
  74 #define HCLGE_PHY_CSS_REG               17
  75
  76 #define HCLGE_PHY_MDIX_CTRL_S           (5)
  77 #define HCLGE_PHY_MDIX_CTRL_M           GENMASK(6, 5)
  78
  79 #define HCLGE_PHY_MDIX_STATUS_B (6)
  80 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B   (11)
  81
  82 /* Factor used to calculate offset and bitmap of VF num */
  83 #define HCLGE_VF_NUM_PER_CMD           64
  84 #define HCLGE_VF_NUM_PER_BYTE          8
  85
  86 /* Reset related Registers */
  87 #define HCLGE_MISC_RESET_STS_REG        0x20700
  88 #define HCLGE_GLOBAL_RESET_REG          0x20A00
  89 #define HCLGE_GLOBAL_RESET_BIT          0x0
  90 #define HCLGE_CORE_RESET_BIT            0x1
  91 #define HCLGE_FUN_RST_ING               0x20C00
  92 #define HCLGE_FUN_RST_ING_B             0
  93
  94 /* Vector0 register bits define */
  95 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
  96 #define HCLGE_VECTOR0_CORERESET_INT_B   6
  97 #define HCLGE_VECTOR0_IMPRESET_INT_B    7
  98
  99 /* Vector0 interrupt CMDQ event source register(RW) */
 100 #define HCLGE_VECTOR0_CMDQ_SRC_REG      0x27100
 101 /* CMDQ register bits for RX event(=MBX event) */
 102 #define HCLGE_VECTOR0_RX_CMDQ_INT_B     1
 103
 104 #define HCLGE_MAC_DEFAULT_FRAME \
 105         (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN + ETH_DATA_LEN)
 106 #define HCLGE_MAC_MIN_FRAME             64
 107 #define HCLGE_MAC_MAX_FRAME             9728
 108
 109 enum HCLGE_DEV_STATE {
 110         HCLGE_STATE_REINITING,
 111         HCLGE_STATE_DOWN,
 112         HCLGE_STATE_DISABLED,
 113         HCLGE_STATE_REMOVING,
 114         HCLGE_STATE_SERVICE_INITED,
 115         HCLGE_STATE_SERVICE_SCHED,
 116         HCLGE_STATE_RST_SERVICE_SCHED,
 117         HCLGE_STATE_RST_HANDLING,
 118         HCLGE_STATE_MBX_SERVICE_SCHED,
 119         HCLGE_STATE_MBX_HANDLING,
 120         HCLGE_STATE_STATISTICS_UPDATING,
 121         HCLGE_STATE_MAX
 122 };
 123
 124 enum hclge_evt_cause {
 125         HCLGE_VECTOR0_EVENT_RST,
 126         HCLGE_VECTOR0_EVENT_MBX,
 127         HCLGE_VECTOR0_EVENT_OTHER,
 128 };
 129
 130 #define HCLGE_MPF_ENBALE 1
 131 struct hclge_caps {
 132         u16 num_tqp;
 133         u16 num_buffer_cell;
 134         u32 flag;
 135         u16 vmdq;
 136 };
 137
 138 enum HCLGE_MAC_SPEED {
 139         HCLGE_MAC_SPEED_10M     = 10,           /* 10 Mbps */
 140         HCLGE_MAC_SPEED_100M    = 100,          /* 100 Mbps */
 141         HCLGE_MAC_SPEED_1G      = 1000,         /* 1000 Mbps   = 1 Gbps */
 142         HCLGE_MAC_SPEED_10G     = 10000,        /* 10000 Mbps  = 10 Gbps */
 143         HCLGE_MAC_SPEED_25G     = 25000,        /* 25000 Mbps  = 25 Gbps */
 144         HCLGE_MAC_SPEED_40G     = 40000,        /* 40000 Mbps  = 40 Gbps */
 145         HCLGE_MAC_SPEED_50G     = 50000,        /* 50000 Mbps  = 50 Gbps */
 146         HCLGE_MAC_SPEED_100G    = 100000        /* 100000 Mbps = 100 Gbps */
 147 };
 148
 149 enum HCLGE_MAC_DUPLEX {
 150         HCLGE_MAC_HALF,
 151         HCLGE_MAC_FULL
 152 };
 153
 154 enum hclge_mta_dmac_sel_type {
 155         HCLGE_MAC_ADDR_47_36,
 156         HCLGE_MAC_ADDR_46_35,
 157         HCLGE_MAC_ADDR_45_34,
 158         HCLGE_MAC_ADDR_44_33,
 159 };
 160
 161 struct hclge_mac {
 162         u8 phy_addr;
 163         u8 flag;
 164         u8 media_type;
 165         u8 mac_addr[ETH_ALEN];
 166         u8 autoneg;
 167         u8 duplex;
 168         u32 speed;
 169         int link;       /* store the link status of mac & phy (if phy exit)*/
 170         struct phy_device *phydev;
 171         struct mii_bus *mdio_bus;
 172         phy_interface_t phy_if;
 173 };
 174
 175 struct hclge_hw {
 176         void __iomem *io_base;
 177         struct hclge_mac mac;
 178         int num_vec;
 179         struct hclge_cmq cmq;
 180         struct hclge_caps caps;
 181         void *back;
 182 };
 183
 184 /* TQP stats */
 185 struct hlcge_tqp_stats {
 186         /* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
 187         u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
 188         /* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
 189         u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
 190 };
 191
 192 struct hclge_tqp {
 193         struct device *dev;     /* Device for DMA mapping */
 194         struct hnae3_queue q;
 195         struct hlcge_tqp_stats tqp_stats;
 196         u16 index;      /* Global index in a NIC controller */
 197
 198         bool alloced;
 199 };
 200
 201 enum hclge_fc_mode {
 202         HCLGE_FC_NONE,
 203         HCLGE_FC_RX_PAUSE,
 204         HCLGE_FC_TX_PAUSE,
 205         HCLGE_FC_FULL,
 206         HCLGE_FC_PFC,
 207         HCLGE_FC_DEFAULT
 208 };
 209
 210 #define HCLGE_PG_NUM            4
 211 #define HCLGE_SCH_MODE_SP       0
 212 #define HCLGE_SCH_MODE_DWRR     1
 213 struct hclge_pg_info {
 214         u8 pg_id;
 215         u8 pg_sch_mode;         /* 0: sp; 1: dwrr */
 216         u8 tc_bit_map;
 217         u32 bw_limit;
 218         u8 tc_dwrr[HNAE3_MAX_TC];
 219 };
 220
 221 struct hclge_tc_info {
 222         u8 tc_id;
 223         u8 tc_sch_mode;         /* 0: sp; 1: dwrr */
 224         u8 pgid;
 225         u32 bw_limit;
 226 };
 227
 228 struct hclge_cfg {
 229         u8 vmdq_vport_num;
 230         u8 tc_num;
 231         u16 tqp_desc_num;
 232         u16 rx_buf_len;
 233         u16 rss_size_max;
 234         u8 phy_addr;
 235         u8 media_type;
 236         u8 mac_addr[ETH_ALEN];
 237         u8 default_speed;
 238         u32 numa_node_map;
 239 };
 240
 241 struct hclge_tm_info {
 242         u8 num_tc;
 243         u8 num_pg;      /* It must be 1 if vNET-Base schd */
 244         u8 pg_dwrr[HCLGE_PG_NUM];
 245         u8 prio_tc[HNAE3_MAX_USER_PRIO];
 246         struct hclge_pg_info pg_info[HCLGE_PG_NUM];
 247         struct hclge_tc_info tc_info[HNAE3_MAX_TC];
 248         enum hclge_fc_mode fc_mode;
 249         u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
 250 };
 251
 252 struct hclge_comm_stats_str {
 253         char desc[ETH_GSTRING_LEN];
 254         unsigned long offset;
 255 };
 256
 257 /* all 64bit stats, opcode id: 0x0030 */
 258 struct hclge_64_bit_stats {
 259         /* query_igu_stat */
 260         u64 igu_rx_oversize_pkt;
 261         u64 igu_rx_undersize_pkt;
 262         u64 igu_rx_out_all_pkt;
 263         u64 igu_rx_uni_pkt;
 264         u64 igu_rx_multi_pkt;
 265         u64 igu_rx_broad_pkt;
 266         u64 rsv0;
 267
 268         /* query_egu_stat */
 269         u64 egu_tx_out_all_pkt;
 270         u64 egu_tx_uni_pkt;
 271         u64 egu_tx_multi_pkt;
 272         u64 egu_tx_broad_pkt;
 273
 274         /* ssu_ppp packet stats */
 275         u64 ssu_ppp_mac_key_num;
 276         u64 ssu_ppp_host_key_num;
 277         u64 ppp_ssu_mac_rlt_num;
 278         u64 ppp_ssu_host_rlt_num;
 279
 280         /* ssu_tx_in_out_dfx_stats */
 281         u64 ssu_tx_in_num;
 282         u64 ssu_tx_out_num;
 283         /* ssu_rx_in_out_dfx_stats */
 284         u64 ssu_rx_in_num;
 285         u64 ssu_rx_out_num;
 286 };
 287
 288 /* all 32bit stats, opcode id: 0x0031 */
 289 struct hclge_32_bit_stats {
 290         u64 igu_rx_err_pkt;
 291         u64 igu_rx_no_eof_pkt;
 292         u64 igu_rx_no_sof_pkt;
 293         u64 egu_tx_1588_pkt;
 294         u64 egu_tx_err_pkt;
 295         u64 ssu_full_drop_num;
 296         u64 ssu_part_drop_num;
 297         u64 ppp_key_drop_num;
 298         u64 ppp_rlt_drop_num;
 299         u64 ssu_key_drop_num;
 300         u64 pkt_curr_buf_cnt;
 301         u64 qcn_fb_rcv_cnt;
 302         u64 qcn_fb_drop_cnt;
 303         u64 qcn_fb_invaild_cnt;
 304         u64 rsv0;
 305         u64 rx_packet_tc0_in_cnt;
 306         u64 rx_packet_tc1_in_cnt;
 307         u64 rx_packet_tc2_in_cnt;
 308         u64 rx_packet_tc3_in_cnt;
 309         u64 rx_packet_tc4_in_cnt;
 310         u64 rx_packet_tc5_in_cnt;
 311         u64 rx_packet_tc6_in_cnt;
 312         u64 rx_packet_tc7_in_cnt;
 313         u64 rx_packet_tc0_out_cnt;
 314         u64 rx_packet_tc1_out_cnt;
 315         u64 rx_packet_tc2_out_cnt;
 316         u64 rx_packet_tc3_out_cnt;
 317         u64 rx_packet_tc4_out_cnt;
 318         u64 rx_packet_tc5_out_cnt;
 319         u64 rx_packet_tc6_out_cnt;
 320         u64 rx_packet_tc7_out_cnt;
 321
 322         /* Tx packet level statistics */
 323         u64 tx_packet_tc0_in_cnt;
 324         u64 tx_packet_tc1_in_cnt;
 325         u64 tx_packet_tc2_in_cnt;
 326         u64 tx_packet_tc3_in_cnt;
 327         u64 tx_packet_tc4_in_cnt;
 328         u64 tx_packet_tc5_in_cnt;
 329         u64 tx_packet_tc6_in_cnt;
 330         u64 tx_packet_tc7_in_cnt;
 331         u64 tx_packet_tc0_out_cnt;
 332         u64 tx_packet_tc1_out_cnt;
 333         u64 tx_packet_tc2_out_cnt;
 334         u64 tx_packet_tc3_out_cnt;
 335         u64 tx_packet_tc4_out_cnt;
 336         u64 tx_packet_tc5_out_cnt;
 337         u64 tx_packet_tc6_out_cnt;
 338         u64 tx_packet_tc7_out_cnt;
 339
 340         /* packet buffer statistics */
 341         u64 pkt_curr_buf_tc0_cnt;
 342         u64 pkt_curr_buf_tc1_cnt;
 343         u64 pkt_curr_buf_tc2_cnt;
 344         u64 pkt_curr_buf_tc3_cnt;
 345         u64 pkt_curr_buf_tc4_cnt;
 346         u64 pkt_curr_buf_tc5_cnt;
 347         u64 pkt_curr_buf_tc6_cnt;
 348         u64 pkt_curr_buf_tc7_cnt;
 349
 350         u64 mb_uncopy_num;
 351         u64 lo_pri_unicast_rlt_drop_num;
 352         u64 hi_pri_multicast_rlt_drop_num;
 353         u64 lo_pri_multicast_rlt_drop_num;
 354         u64 rx_oq_drop_pkt_cnt;
 355         u64 tx_oq_drop_pkt_cnt;
 356         u64 nic_l2_err_drop_pkt_cnt;
 357         u64 roc_l2_err_drop_pkt_cnt;
 358 };
 359
 360 /* mac stats ,opcode id: 0x0032 */
 361 struct hclge_mac_stats {
 362         u64 mac_tx_mac_pause_num;
 363         u64 mac_rx_mac_pause_num;
 364         u64 mac_tx_pfc_pri0_pkt_num;
 365         u64 mac_tx_pfc_pri1_pkt_num;
 366         u64 mac_tx_pfc_pri2_pkt_num;
 367         u64 mac_tx_pfc_pri3_pkt_num;
 368         u64 mac_tx_pfc_pri4_pkt_num;
 369         u64 mac_tx_pfc_pri5_pkt_num;
 370         u64 mac_tx_pfc_pri6_pkt_num;
 371         u64 mac_tx_pfc_pri7_pkt_num;
 372         u64 mac_rx_pfc_pri0_pkt_num;
 373         u64 mac_rx_pfc_pri1_pkt_num;
 374         u64 mac_rx_pfc_pri2_pkt_num;
 375         u64 mac_rx_pfc_pri3_pkt_num;
 376         u64 mac_rx_pfc_pri4_pkt_num;
 377         u64 mac_rx_pfc_pri5_pkt_num;
 378         u64 mac_rx_pfc_pri6_pkt_num;
 379         u64 mac_rx_pfc_pri7_pkt_num;
 380         u64 mac_tx_total_pkt_num;
 381         u64 mac_tx_total_oct_num;
 382         u64 mac_tx_good_pkt_num;
 383         u64 mac_tx_bad_pkt_num;
 384         u64 mac_tx_good_oct_num;
 385         u64 mac_tx_bad_oct_num;
 386         u64 mac_tx_uni_pkt_num;
 387         u64 mac_tx_multi_pkt_num;
 388         u64 mac_tx_broad_pkt_num;
 389         u64 mac_tx_undersize_pkt_num;
 390         u64 mac_tx_oversize_pkt_num;
 391         u64 mac_tx_64_oct_pkt_num;
 392         u64 mac_tx_65_127_oct_pkt_num;
 393         u64 mac_tx_128_255_oct_pkt_num;
 394         u64 mac_tx_256_511_oct_pkt_num;
 395         u64 mac_tx_512_1023_oct_pkt_num;
 396         u64 mac_tx_1024_1518_oct_pkt_num;
 397         u64 mac_tx_1519_2047_oct_pkt_num;
 398         u64 mac_tx_2048_4095_oct_pkt_num;
 399         u64 mac_tx_4096_8191_oct_pkt_num;
 400         u64 mac_tx_8192_12287_oct_pkt_num; /* valid for GE MAC only */
 401         u64 mac_tx_8192_9216_oct_pkt_num; /* valid for LGE & CGE MAC only */
 402         u64 mac_tx_9217_12287_oct_pkt_num; /* valid for LGE & CGE MAC */
 403         u64 mac_tx_12288_16383_oct_pkt_num;
 404         u64 mac_tx_1519_max_good_oct_pkt_num;
 405         u64 mac_tx_1519_max_bad_oct_pkt_num;
 406
 407         u64 mac_rx_total_pkt_num;
 408         u64 mac_rx_total_oct_num;
 409         u64 mac_rx_good_pkt_num;
 410         u64 mac_rx_bad_pkt_num;
 411         u64 mac_rx_good_oct_num;
 412         u64 mac_rx_bad_oct_num;
 413         u64 mac_rx_uni_pkt_num;
 414         u64 mac_rx_multi_pkt_num;
 415         u64 mac_rx_broad_pkt_num;
 416         u64 mac_rx_undersize_pkt_num;
 417         u64 mac_rx_oversize_pkt_num;
 418         u64 mac_rx_64_oct_pkt_num;
 419         u64 mac_rx_65_127_oct_pkt_num;
 420         u64 mac_rx_128_255_oct_pkt_num;
 421         u64 mac_rx_256_511_oct_pkt_num;
 422         u64 mac_rx_512_1023_oct_pkt_num;
 423         u64 mac_rx_1024_1518_oct_pkt_num;
 424         u64 mac_rx_1519_2047_oct_pkt_num;
 425         u64 mac_rx_2048_4095_oct_pkt_num;
 426         u64 mac_rx_4096_8191_oct_pkt_num;
 427         u64 mac_rx_8192_12287_oct_pkt_num;/* valid for GE MAC only */
 428         u64 mac_rx_8192_9216_oct_pkt_num; /* valid for LGE & CGE MAC only */
 429         u64 mac_rx_9217_12287_oct_pkt_num; /* valid for LGE & CGE MAC only */
 430         u64 mac_rx_12288_16383_oct_pkt_num;
 431         u64 mac_rx_1519_max_good_oct_pkt_num;
 432         u64 mac_rx_1519_max_bad_oct_pkt_num;
 433
 434         u64 mac_tx_fragment_pkt_num;
 435         u64 mac_tx_undermin_pkt_num;
 436         u64 mac_tx_jabber_pkt_num;
 437         u64 mac_tx_err_all_pkt_num;
 438         u64 mac_tx_from_app_good_pkt_num;
 439         u64 mac_tx_from_app_bad_pkt_num;
 440         u64 mac_rx_fragment_pkt_num;
 441         u64 mac_rx_undermin_pkt_num;
 442         u64 mac_rx_jabber_pkt_num;
 443         u64 mac_rx_fcs_err_pkt_num;
 444         u64 mac_rx_send_app_good_pkt_num;
 445         u64 mac_rx_send_app_bad_pkt_num;
 446 };
 447
 448 #define HCLGE_STATS_TIMER_INTERVAL      (60 * 5)
 449 struct hclge_hw_stats {
 450         struct hclge_mac_stats      mac_stats;
 451         struct hclge_64_bit_stats   all_64_bit_stats;
 452         struct hclge_32_bit_stats   all_32_bit_stats;
 453         u32 stats_timer;
 454 };
 455
 456 struct hclge_vlan_type_cfg {
 457         u16 rx_ot_fst_vlan_type;
 458         u16 rx_ot_sec_vlan_type;
 459         u16 rx_in_fst_vlan_type;
 460         u16 rx_in_sec_vlan_type;
 461         u16 tx_ot_vlan_type;
 462         u16 tx_in_vlan_type;
 463 };
 464
 465 struct hclge_dev {
 466         struct pci_dev *pdev;
 467         struct hnae3_ae_dev *ae_dev;
 468         struct hclge_hw hw;
 469         struct hclge_misc_vector misc_vector;
 470         struct hclge_hw_stats hw_stats;
 471         unsigned long state;
 472
 473         enum hnae3_reset_type reset_type;
 474         unsigned long reset_request;    /* reset has been requested */
 475         unsigned long reset_pending;    /* client rst is pending to be served */
 476         u32 fw_version;
 477         u16 num_vmdq_vport;             /* Num vmdq vport this PF has set up */
 478         u16 num_tqps;                   /* Num task queue pairs of this PF */
 479         u16 num_req_vfs;                /* Num VFs requested for this PF */
 480
 481         /* Base task tqp physical id of this PF */
 482         u16 base_tqp_pid;
 483         u16 alloc_rss_size;             /* Allocated RSS task queue */
 484         u16 rss_size_max;               /* HW defined max RSS task queue */
 485
 486         /* Num of guaranteed filters for this PF */
 487         u16 fdir_pf_filter_count;
 488         u16 num_alloc_vport;            /* Num vports this driver supports */
 489         u32 numa_node_mask;
 490         u16 rx_buf_len;
 491         u16 num_desc;
 492         u8 hw_tc_map;
 493         u8 tc_num_last_time;
 494         enum hclge_fc_mode fc_mode_last_time;
 495
 496 #define HCLGE_FLAG_TC_BASE_SCH_MODE             1
 497 #define HCLGE_FLAG_VNET_BASE_SCH_MODE           2
 498         u8 tx_sch_mode;
 499         u8 tc_max;
 500         u8 pfc_max;
 501
 502         u8 default_up;
 503         u8 dcbx_cap;
 504         struct hclge_tm_info tm_info;
 505
 506         u16 num_msi;
 507         u16 num_msi_left;
 508         u16 num_msi_used;
 509         u32 base_msi_vector;
 510         u16 *vector_status;
 511         int *vector_irq;
 512         u16 num_roce_msi;       /* Num of roce vectors for this PF */
 513         int roce_base_vector;
 514
 515         u16 pending_udp_bitmap;
 516
 517         u16 rx_itr_default;
 518         u16 tx_itr_default;
 519
 520         u16 adminq_work_limit; /* Num of admin receive queue desc to process */
 521         unsigned long service_timer_period;
 522         unsigned long service_timer_previous;
 523         struct timer_list service_timer;
 524         struct work_struct service_task;
 525         struct work_struct rst_service_task;
 526         struct work_struct mbx_service_task;
 527
 528         bool cur_promisc;
 529         int num_alloc_vfs;      /* Actual number of VFs allocated */
 530
 531         struct hclge_tqp *htqp;
 532         struct hclge_vport *vport;
 533
 534         struct dentry *hclge_dbgfs;
 535
 536         struct hnae3_client *nic_client;
 537         struct hnae3_client *roce_client;
 538
 539 #define HCLGE_FLAG_MAIN                 BIT(0)
 540 #define HCLGE_FLAG_DCB_CAPABLE          BIT(1)
 541 #define HCLGE_FLAG_DCB_ENABLE           BIT(2)
 542 #define HCLGE_FLAG_MQPRIO_ENABLE        BIT(3)
 543         u32 flag;
 544
 545         u32 pkt_buf_size; /* Total pf buf size for tx/rx */
 546         u32 mps; /* Max packet size */
 547
 548         enum hclge_mta_dmac_sel_type mta_mac_sel_type;
 549         bool enable_mta; /* Mutilcast filter enable */
 550         bool accept_mta_mc; /* Whether accept mta filter multicast */
 551
 552         struct hclge_vlan_type_cfg vlan_type_cfg;
 553
 554         u64 rx_pkts_for_led;
 555         u64 tx_pkts_for_led;
 556 };
 557
 558 /* VPort level vlan tag configuration for TX direction */
 559 struct hclge_tx_vtag_cfg {
 560         bool accept_tag;        /* Whether accept tagged packet from host */
 561         bool accept_untag;      /* Whether accept untagged packet from host */
 562         bool insert_tag1_en;    /* Whether insert inner vlan tag */
 563         bool insert_tag2_en;    /* Whether insert outer vlan tag */
 564         u16  default_tag1;      /* The default inner vlan tag to insert */
 565         u16  default_tag2;      /* The default outer vlan tag to insert */
 566 };
 567
 568 /* VPort level vlan tag configuration for RX direction */
 569 struct hclge_rx_vtag_cfg {
 570         bool strip_tag1_en;     /* Whether strip inner vlan tag */
 571         bool strip_tag2_en;     /* Whether strip outer vlan tag */
 572         bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */
 573         bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */
 574 };
 575
 576 struct hclge_vport {
 577         u16 alloc_tqps; /* Allocated Tx/Rx queues */
 578
 579         u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
 580         /* User configured lookup table entries */
 581         u8  rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
 582         int rss_algo;           /* User configured hash algorithm */
 583
 584         u16 alloc_rss_size;
 585
 586         u16 qs_offset;
 587         u16 bw_limit;           /* VSI BW Limit (0 = disabled) */
 588         u8  dwrr;
 589
 590         struct hclge_tx_vtag_cfg  txvlan_cfg;
 591         struct hclge_rx_vtag_cfg  rxvlan_cfg;
 592
 593         int vport_id;
 594         struct hclge_dev *back;  /* Back reference to associated dev */
 595         struct hnae3_handle nic;
 596         struct hnae3_handle roce;
 597 };
 598
 599 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
 600                               bool en_mc, bool en_bc, int vport_id);
 601
 602 int hclge_add_uc_addr_common(struct hclge_vport *vport,
 603                              const unsigned char *addr);
 604 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
 605                             const unsigned char *addr);
 606 int hclge_add_mc_addr_common(struct hclge_vport *vport,
 607                              const unsigned char *addr);
 608 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
 609                             const unsigned char *addr);
 610
 611 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
 612                               u8 func_id,
 613                               bool enable);
 614 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
 615 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
 616                                 int vector_id, bool en,
 617                                 struct hnae3_ring_chain_node *ring_chain);
 618
 619 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
 620 {
 621         struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
 622
 623         return tqp->index;
 624 }
 625
 626 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
 627 int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid,
 628                              bool is_kill, u16 vlan, u8 qos, __be16 proto);
 629
 630 int hclge_buffer_alloc(struct hclge_dev *hdev);
 631 int hclge_rss_init_hw(struct hclge_dev *hdev);
 632
 633 void hclge_mbx_handler(struct hclge_dev *hdev);
 634 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
 635 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
 636 #endif