drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

   1 /*
   2  * Copyright (c) 2016~2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __HCLGE_MAIN_H
  11 #define __HCLGE_MAIN_H
  12 #include <linux/fs.h>
  13 #include <linux/types.h>
  14 #include <linux/phy.h>
  15 #include "hclge_cmd.h"
  16 #include "hnae3.h"
  17
  18 #define HCLGE_MOD_VERSION "v1.0"
  19 #define HCLGE_DRIVER_NAME "hclge"
  20
  21 #define HCLGE_INVALID_VPORT 0xffff
  22
  23 #define HCLGE_ROCE_VECTOR_OFFSET        96
  24
  25 #define HCLGE_PF_CFG_BLOCK_SIZE         32
  26 #define HCLGE_PF_CFG_DESC_NUM \
  27         (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
  28
  29 #define HCLGE_VECTOR_REG_BASE           0x20000
  30
  31 #define HCLGE_VECTOR_REG_OFFSET         0x4
  32 #define HCLGE_VECTOR_VF_OFFSET          0x100000
  33
  34 #define HCLGE_RSS_IND_TBL_SIZE          512
  35 #define HCLGE_RSS_SET_BITMAP_MSK        0xffff
  36 #define HCLGE_RSS_KEY_SIZE              40
  37 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ    0
  38 #define HCLGE_RSS_HASH_ALGO_SIMPLE      1
  39 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC   2
  40 #define HCLGE_RSS_HASH_ALGO_MASK        0xf
  41 #define HCLGE_RSS_CFG_TBL_NUM \
  42         (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
  43
  44 #define HCLGE_RSS_TC_SIZE_0             1
  45 #define HCLGE_RSS_TC_SIZE_1             2
  46 #define HCLGE_RSS_TC_SIZE_2             4
  47 #define HCLGE_RSS_TC_SIZE_3             8
  48 #define HCLGE_RSS_TC_SIZE_4             16
  49 #define HCLGE_RSS_TC_SIZE_5             32
  50 #define HCLGE_RSS_TC_SIZE_6             64
  51 #define HCLGE_RSS_TC_SIZE_7             128
  52
  53 #define HCLGE_TQP_RESET_TRY_TIMES       10
  54
  55 #define HCLGE_PHY_PAGE_MDIX             0
  56 #define HCLGE_PHY_PAGE_COPPER           0
  57
  58 /* Page Selection Reg. */
  59 #define HCLGE_PHY_PAGE_REG              22
  60
  61 /* Copper Specific Control Register */
  62 #define HCLGE_PHY_CSC_REG               16
  63
  64 /* Copper Specific Status Register */
  65 #define HCLGE_PHY_CSS_REG               17
  66
  67 #define HCLGE_PHY_MDIX_CTRL_S           (5)
  68 #define HCLGE_PHY_MDIX_CTRL_M           (3 << HCLGE_PHY_MDIX_CTRL_S)
  69
  70 #define HCLGE_PHY_MDIX_STATUS_B (6)
  71 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B   (11)
  72
  73 enum HCLGE_DEV_STATE {
  74         HCLGE_STATE_REINITING,
  75         HCLGE_STATE_DOWN,
  76         HCLGE_STATE_DISABLED,
  77         HCLGE_STATE_REMOVING,
  78         HCLGE_STATE_SERVICE_INITED,
  79         HCLGE_STATE_SERVICE_SCHED,
  80         HCLGE_STATE_MBX_HANDLING,
  81         HCLGE_STATE_MBX_IRQ,
  82         HCLGE_STATE_MAX
  83 };
  84
  85 #define HCLGE_MPF_ENBALE 1
  86 struct hclge_caps {
  87         u16 num_tqp;
  88         u16 num_buffer_cell;
  89         u32 flag;
  90         u16 vmdq;
  91 };
  92
  93 enum HCLGE_MAC_SPEED {
  94         HCLGE_MAC_SPEED_10M     = 10,           /* 10 Mbps */
  95         HCLGE_MAC_SPEED_100M    = 100,          /* 100 Mbps */
  96         HCLGE_MAC_SPEED_1G      = 1000,         /* 1000 Mbps   = 1 Gbps */
  97         HCLGE_MAC_SPEED_10G     = 10000,        /* 10000 Mbps  = 10 Gbps */
  98         HCLGE_MAC_SPEED_25G     = 25000,        /* 25000 Mbps  = 25 Gbps */
  99         HCLGE_MAC_SPEED_40G     = 40000,        /* 40000 Mbps  = 40 Gbps */
 100         HCLGE_MAC_SPEED_50G     = 50000,        /* 50000 Mbps  = 50 Gbps */
 101         HCLGE_MAC_SPEED_100G    = 100000        /* 100000 Mbps = 100 Gbps */
 102 };
 103
 104 enum HCLGE_MAC_DUPLEX {
 105         HCLGE_MAC_HALF,
 106         HCLGE_MAC_FULL
 107 };
 108
 109 enum hclge_mta_dmac_sel_type {
 110         HCLGE_MAC_ADDR_47_36,
 111         HCLGE_MAC_ADDR_46_35,
 112         HCLGE_MAC_ADDR_45_34,
 113         HCLGE_MAC_ADDR_44_33,
 114 };
 115
 116 struct hclge_mac {
 117         u8 phy_addr;
 118         u8 flag;
 119         u8 media_type;
 120         u8 mac_addr[ETH_ALEN];
 121         u8 autoneg;
 122         u8 duplex;
 123         u32 speed;
 124         int link;       /* store the link status of mac & phy (if phy exit)*/
 125         struct phy_device *phydev;
 126         struct mii_bus *mdio_bus;
 127         phy_interface_t phy_if;
 128 };
 129
 130 struct hclge_hw {
 131         void __iomem *io_base;
 132         struct hclge_mac mac;
 133         int num_vec;
 134         struct hclge_cmq cmq;
 135         struct hclge_caps caps;
 136         void *back;
 137 };
 138
 139 /* TQP stats */
 140 struct hlcge_tqp_stats {
 141         /* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
 142         u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
 143         /* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
 144         u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
 145 };
 146
 147 struct hclge_tqp {
 148         struct device *dev;     /* Device for DMA mapping */
 149         struct hnae3_queue q;
 150         struct hlcge_tqp_stats tqp_stats;
 151         u16 index;      /* Global index in a NIC controller */
 152
 153         bool alloced;
 154 };
 155
 156 enum hclge_fc_mode {
 157         HCLGE_FC_NONE,
 158         HCLGE_FC_RX_PAUSE,
 159         HCLGE_FC_TX_PAUSE,
 160         HCLGE_FC_FULL,
 161         HCLGE_FC_PFC,
 162         HCLGE_FC_DEFAULT
 163 };
 164
 165 #define HCLGE_PG_NUM            4
 166 #define HCLGE_SCH_MODE_SP       0
 167 #define HCLGE_SCH_MODE_DWRR     1
 168 struct hclge_pg_info {
 169         u8 pg_id;
 170         u8 pg_sch_mode;         /* 0: sp; 1: dwrr */
 171         u8 tc_bit_map;
 172         u32 bw_limit;
 173         u8 tc_dwrr[HNAE3_MAX_TC];
 174 };
 175
 176 struct hclge_tc_info {
 177         u8 tc_id;
 178         u8 tc_sch_mode;         /* 0: sp; 1: dwrr */
 179         u8 pgid;
 180         u32 bw_limit;
 181 };
 182
 183 struct hclge_cfg {
 184         u8 vmdq_vport_num;
 185         u8 tc_num;
 186         u16 tqp_desc_num;
 187         u16 rx_buf_len;
 188         u8 phy_addr;
 189         u8 media_type;
 190         u8 mac_addr[ETH_ALEN];
 191         u8 default_speed;
 192         u32 numa_node_map;
 193 };
 194
 195 struct hclge_tm_info {
 196         u8 num_tc;
 197         u8 num_pg;      /* It must be 1 if vNET-Base schd */
 198         u8 pg_dwrr[HCLGE_PG_NUM];
 199         u8 prio_tc[HNAE3_MAX_USER_PRIO];
 200         struct hclge_pg_info pg_info[HCLGE_PG_NUM];
 201         struct hclge_tc_info tc_info[HNAE3_MAX_TC];
 202         enum hclge_fc_mode fc_mode;
 203         u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
 204 };
 205
 206 struct hclge_comm_stats_str {
 207         char desc[ETH_GSTRING_LEN];
 208         unsigned long offset;
 209 };
 210
 211 /* all 64bit stats, opcode id: 0x0030 */
 212 struct hclge_64_bit_stats {
 213         /* query_igu_stat */
 214         u64 igu_rx_oversize_pkt;
 215         u64 igu_rx_undersize_pkt;
 216         u64 igu_rx_out_all_pkt;
 217         u64 igu_rx_uni_pkt;
 218         u64 igu_rx_multi_pkt;
 219         u64 igu_rx_broad_pkt;
 220         u64 rsv0;
 221
 222         /* query_egu_stat */
 223         u64 egu_tx_out_all_pkt;
 224         u64 egu_tx_uni_pkt;
 225         u64 egu_tx_multi_pkt;
 226         u64 egu_tx_broad_pkt;
 227
 228         /* ssu_ppp packet stats */
 229         u64 ssu_ppp_mac_key_num;
 230         u64 ssu_ppp_host_key_num;
 231         u64 ppp_ssu_mac_rlt_num;
 232         u64 ppp_ssu_host_rlt_num;
 233
 234         /* ssu_tx_in_out_dfx_stats */
 235         u64 ssu_tx_in_num;
 236         u64 ssu_tx_out_num;
 237         /* ssu_rx_in_out_dfx_stats */
 238         u64 ssu_rx_in_num;
 239         u64 ssu_rx_out_num;
 240 };
 241
 242 /* all 32bit stats, opcode id: 0x0031 */
 243 struct hclge_32_bit_stats {
 244         u64 igu_rx_err_pkt;
 245         u64 igu_rx_no_eof_pkt;
 246         u64 igu_rx_no_sof_pkt;
 247         u64 egu_tx_1588_pkt;
 248         u64 egu_tx_err_pkt;
 249         u64 ssu_full_drop_num;
 250         u64 ssu_part_drop_num;
 251         u64 ppp_key_drop_num;
 252         u64 ppp_rlt_drop_num;
 253         u64 ssu_key_drop_num;
 254         u64 pkt_curr_buf_cnt;
 255         u64 qcn_fb_rcv_cnt;
 256         u64 qcn_fb_drop_cnt;
 257         u64 qcn_fb_invaild_cnt;
 258         u64 rsv0;
 259         u64 rx_packet_tc0_in_cnt;
 260         u64 rx_packet_tc1_in_cnt;
 261         u64 rx_packet_tc2_in_cnt;
 262         u64 rx_packet_tc3_in_cnt;
 263         u64 rx_packet_tc4_in_cnt;
 264         u64 rx_packet_tc5_in_cnt;
 265         u64 rx_packet_tc6_in_cnt;
 266         u64 rx_packet_tc7_in_cnt;
 267         u64 rx_packet_tc0_out_cnt;
 268         u64 rx_packet_tc1_out_cnt;
 269         u64 rx_packet_tc2_out_cnt;
 270         u64 rx_packet_tc3_out_cnt;
 271         u64 rx_packet_tc4_out_cnt;
 272         u64 rx_packet_tc5_out_cnt;
 273         u64 rx_packet_tc6_out_cnt;
 274         u64 rx_packet_tc7_out_cnt;
 275
 276         /* Tx packet level statistics */
 277         u64 tx_packet_tc0_in_cnt;
 278         u64 tx_packet_tc1_in_cnt;
 279         u64 tx_packet_tc2_in_cnt;
 280         u64 tx_packet_tc3_in_cnt;
 281         u64 tx_packet_tc4_in_cnt;
 282         u64 tx_packet_tc5_in_cnt;
 283         u64 tx_packet_tc6_in_cnt;
 284         u64 tx_packet_tc7_in_cnt;
 285         u64 tx_packet_tc0_out_cnt;
 286         u64 tx_packet_tc1_out_cnt;
 287         u64 tx_packet_tc2_out_cnt;
 288         u64 tx_packet_tc3_out_cnt;
 289         u64 tx_packet_tc4_out_cnt;
 290         u64 tx_packet_tc5_out_cnt;
 291         u64 tx_packet_tc6_out_cnt;
 292         u64 tx_packet_tc7_out_cnt;
 293
 294         /* packet buffer statistics */
 295         u64 pkt_curr_buf_tc0_cnt;
 296         u64 pkt_curr_buf_tc1_cnt;
 297         u64 pkt_curr_buf_tc2_cnt;
 298         u64 pkt_curr_buf_tc3_cnt;
 299         u64 pkt_curr_buf_tc4_cnt;
 300         u64 pkt_curr_buf_tc5_cnt;
 301         u64 pkt_curr_buf_tc6_cnt;
 302         u64 pkt_curr_buf_tc7_cnt;
 303
 304         u64 mb_uncopy_num;
 305         u64 lo_pri_unicast_rlt_drop_num;
 306         u64 hi_pri_multicast_rlt_drop_num;
 307         u64 lo_pri_multicast_rlt_drop_num;
 308         u64 rx_oq_drop_pkt_cnt;
 309         u64 tx_oq_drop_pkt_cnt;
 310         u64 nic_l2_err_drop_pkt_cnt;
 311         u64 roc_l2_err_drop_pkt_cnt;
 312 };
 313
 314 /* mac stats ,opcode id: 0x0032 */
 315 struct hclge_mac_stats {
 316         u64 mac_tx_mac_pause_num;
 317         u64 mac_rx_mac_pause_num;
 318         u64 mac_tx_pfc_pri0_pkt_num;
 319         u64 mac_tx_pfc_pri1_pkt_num;
 320         u64 mac_tx_pfc_pri2_pkt_num;
 321         u64 mac_tx_pfc_pri3_pkt_num;
 322         u64 mac_tx_pfc_pri4_pkt_num;
 323         u64 mac_tx_pfc_pri5_pkt_num;
 324         u64 mac_tx_pfc_pri6_pkt_num;
 325         u64 mac_tx_pfc_pri7_pkt_num;
 326         u64 mac_rx_pfc_pri0_pkt_num;
 327         u64 mac_rx_pfc_pri1_pkt_num;
 328         u64 mac_rx_pfc_pri2_pkt_num;
 329         u64 mac_rx_pfc_pri3_pkt_num;
 330         u64 mac_rx_pfc_pri4_pkt_num;
 331         u64 mac_rx_pfc_pri5_pkt_num;
 332         u64 mac_rx_pfc_pri6_pkt_num;
 333         u64 mac_rx_pfc_pri7_pkt_num;
 334         u64 mac_tx_total_pkt_num;
 335         u64 mac_tx_total_oct_num;
 336         u64 mac_tx_good_pkt_num;
 337         u64 mac_tx_bad_pkt_num;
 338         u64 mac_tx_good_oct_num;
 339         u64 mac_tx_bad_oct_num;
 340         u64 mac_tx_uni_pkt_num;
 341         u64 mac_tx_multi_pkt_num;
 342         u64 mac_tx_broad_pkt_num;
 343         u64 mac_tx_undersize_pkt_num;
 344         u64 mac_tx_overrsize_pkt_num;
 345         u64 mac_tx_64_oct_pkt_num;
 346         u64 mac_tx_65_127_oct_pkt_num;
 347         u64 mac_tx_128_255_oct_pkt_num;
 348         u64 mac_tx_256_511_oct_pkt_num;
 349         u64 mac_tx_512_1023_oct_pkt_num;
 350         u64 mac_tx_1024_1518_oct_pkt_num;
 351         u64 mac_tx_1519_max_oct_pkt_num;
 352         u64 mac_rx_total_pkt_num;
 353         u64 mac_rx_total_oct_num;
 354         u64 mac_rx_good_pkt_num;
 355         u64 mac_rx_bad_pkt_num;
 356         u64 mac_rx_good_oct_num;
 357         u64 mac_rx_bad_oct_num;
 358         u64 mac_rx_uni_pkt_num;
 359         u64 mac_rx_multi_pkt_num;
 360         u64 mac_rx_broad_pkt_num;
 361         u64 mac_rx_undersize_pkt_num;
 362         u64 mac_rx_overrsize_pkt_num;
 363         u64 mac_rx_64_oct_pkt_num;
 364         u64 mac_rx_65_127_oct_pkt_num;
 365         u64 mac_rx_128_255_oct_pkt_num;
 366         u64 mac_rx_256_511_oct_pkt_num;
 367         u64 mac_rx_512_1023_oct_pkt_num;
 368         u64 mac_rx_1024_1518_oct_pkt_num;
 369         u64 mac_rx_1519_max_oct_pkt_num;
 370
 371         u64 mac_trans_fragment_pkt_num;
 372         u64 mac_trans_undermin_pkt_num;
 373         u64 mac_trans_jabber_pkt_num;
 374         u64 mac_trans_err_all_pkt_num;
 375         u64 mac_trans_from_app_good_pkt_num;
 376         u64 mac_trans_from_app_bad_pkt_num;
 377         u64 mac_rcv_fragment_pkt_num;
 378         u64 mac_rcv_undermin_pkt_num;
 379         u64 mac_rcv_jabber_pkt_num;
 380         u64 mac_rcv_fcs_err_pkt_num;
 381         u64 mac_rcv_send_app_good_pkt_num;
 382         u64 mac_rcv_send_app_bad_pkt_num;
 383 };
 384
 385 struct hclge_hw_stats {
 386         struct hclge_mac_stats      mac_stats;
 387         struct hclge_64_bit_stats   all_64_bit_stats;
 388         struct hclge_32_bit_stats   all_32_bit_stats;
 389 };
 390
 391 struct hclge_dev {
 392         struct pci_dev *pdev;
 393         struct hnae3_ae_dev *ae_dev;
 394         struct hclge_hw hw;
 395         struct hclge_hw_stats hw_stats;
 396         unsigned long state;
 397
 398         u32 fw_version;
 399         u16 num_vmdq_vport;             /* Num vmdq vport this PF has set up */
 400         u16 num_tqps;                   /* Num task queue pairs of this PF */
 401         u16 num_req_vfs;                /* Num VFs requested for this PF */
 402
 403         u16 num_roce_msix;              /* Num of roce vectors for this PF */
 404         int roce_base_vector;
 405
 406         /* Base task tqp physical id of this PF */
 407         u16 base_tqp_pid;
 408         u16 alloc_rss_size;             /* Allocated RSS task queue */
 409         u16 rss_size_max;               /* HW defined max RSS task queue */
 410
 411         /* Num of guaranteed filters for this PF */
 412         u16 fdir_pf_filter_count;
 413         u16 num_alloc_vport;            /* Num vports this driver supports */
 414         u32 numa_node_mask;
 415         u16 rx_buf_len;
 416         u16 num_desc;
 417         u8 hw_tc_map;
 418         u8 tc_num_last_time;
 419         enum hclge_fc_mode fc_mode_last_time;
 420
 421 #define HCLGE_FLAG_TC_BASE_SCH_MODE             1
 422 #define HCLGE_FLAG_VNET_BASE_SCH_MODE           2
 423         u8 tx_sch_mode;
 424
 425         u8 default_up;
 426         struct hclge_tm_info tm_info;
 427
 428         u16 num_msi;
 429         u16 num_msi_left;
 430         u16 num_msi_used;
 431         u32 base_msi_vector;
 432         struct msix_entry *msix_entries;
 433         u16 *vector_status;
 434
 435         u16 pending_udp_bitmap;
 436
 437         u16 rx_itr_default;
 438         u16 tx_itr_default;
 439
 440         u16 adminq_work_limit; /* Num of admin receive queue desc to process */
 441         unsigned long service_timer_period;
 442         unsigned long service_timer_previous;
 443         struct timer_list service_timer;
 444         struct work_struct service_task;
 445
 446         bool cur_promisc;
 447         int num_alloc_vfs;      /* Actual number of VFs allocated */
 448
 449         struct hclge_tqp *htqp;
 450         struct hclge_vport *vport;
 451
 452         struct dentry *hclge_dbgfs;
 453
 454         struct hnae3_client *nic_client;
 455         struct hnae3_client *roce_client;
 456
 457 #define HCLGE_FLAG_USE_MSI      0x00000001
 458 #define HCLGE_FLAG_USE_MSIX     0x00000002
 459 #define HCLGE_FLAG_MAIN         0x00000004
 460 #define HCLGE_FLAG_DCB_CAPABLE  0x00000008
 461 #define HCLGE_FLAG_DCB_ENABLE   0x00000010
 462         u32 flag;
 463
 464         u32 pkt_buf_size; /* Total pf buf size for tx/rx */
 465         u32 mps; /* Max packet size */
 466         struct hclge_priv_buf *priv_buf;
 467         struct hclge_shared_buf s_buf;
 468
 469         enum hclge_mta_dmac_sel_type mta_mac_sel_type;
 470         bool enable_mta; /* Mutilcast filter enable */
 471         bool accept_mta_mc; /* Whether accept mta filter multicast */
 472 };
 473
 474 struct hclge_vport {
 475         u16 alloc_tqps; /* Allocated Tx/Rx queues */
 476
 477         u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
 478         /* User configured lookup table entries */
 479         u8  rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
 480         u16 alloc_rss_size;
 481
 482         u16 qs_offset;
 483         u16 bw_limit;           /* VSI BW Limit (0 = disabled) */
 484         u8  dwrr;
 485
 486         int vport_id;
 487         struct hclge_dev *back;  /* Back reference to associated dev */
 488         struct hnae3_handle nic;
 489         struct hnae3_handle roce;
 490 };
 491
 492 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
 493                               bool en_mc, bool en_bc, int vport_id);
 494
 495 int hclge_add_uc_addr_common(struct hclge_vport *vport,
 496                              const unsigned char *addr);
 497 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
 498                             const unsigned char *addr);
 499 int hclge_add_mc_addr_common(struct hclge_vport *vport,
 500                              const unsigned char *addr);
 501 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
 502                             const unsigned char *addr);
 503
 504 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
 505                               u8 func_id,
 506                               bool enable);
 507 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
 508 int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector,
 509                                    struct hnae3_ring_chain_node *ring_chain);
 510 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
 511 {
 512         struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
 513
 514         return tqp->index;
 515 }
 516
 517 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
 518 int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid,
 519                              bool is_kill, u16 vlan, u8 qos, __be16 proto);
 520 #endif