drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

   1 /*
   2  * Copyright (c) 2016~2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __HCLGE_MAIN_H
  11 #define __HCLGE_MAIN_H
  12 #include <linux/fs.h>
  13 #include <linux/types.h>
  14 #include <linux/phy.h>
  15 #include "hclge_cmd.h"
  16 #include "hnae3.h"
  17
  18 #define HCLGE_MOD_VERSION "v1.0"
  19 #define HCLGE_DRIVER_NAME "hclge"
  20
  21 #define HCLGE_INVALID_VPORT 0xffff
  22
  23 #define HCLGE_ROCE_VECTOR_OFFSET        96
  24
  25 #define HCLGE_PF_CFG_BLOCK_SIZE         32
  26 #define HCLGE_PF_CFG_DESC_NUM \
  27         (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
  28
  29 #define HCLGE_VECTOR_REG_BASE           0x20000
  30 #define HCLGE_MISC_VECTOR_REG_BASE      0x20400
  31
  32 #define HCLGE_VECTOR_REG_OFFSET         0x4
  33 #define HCLGE_VECTOR_VF_OFFSET          0x100000
  34
  35 #define HCLGE_RSS_IND_TBL_SIZE          512
  36 #define HCLGE_RSS_SET_BITMAP_MSK        GENMASK(15, 0)
  37 #define HCLGE_RSS_KEY_SIZE              40
  38 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ    0
  39 #define HCLGE_RSS_HASH_ALGO_SIMPLE      1
  40 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC   2
  41 #define HCLGE_RSS_HASH_ALGO_MASK        0xf
  42 #define HCLGE_RSS_CFG_TBL_NUM \
  43         (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
  44
  45 #define HCLGE_RSS_INPUT_TUPLE_OTHER     GENMASK(3, 0)
  46 #define HCLGE_RSS_INPUT_TUPLE_SCTP      GENMASK(4, 0)
  47 #define HCLGE_D_PORT_BIT                BIT(0)
  48 #define HCLGE_S_PORT_BIT                BIT(1)
  49 #define HCLGE_D_IP_BIT                  BIT(2)
  50 #define HCLGE_S_IP_BIT                  BIT(3)
  51 #define HCLGE_V_TAG_BIT                 BIT(4)
  52
  53 #define HCLGE_RSS_TC_SIZE_0             1
  54 #define HCLGE_RSS_TC_SIZE_1             2
  55 #define HCLGE_RSS_TC_SIZE_2             4
  56 #define HCLGE_RSS_TC_SIZE_3             8
  57 #define HCLGE_RSS_TC_SIZE_4             16
  58 #define HCLGE_RSS_TC_SIZE_5             32
  59 #define HCLGE_RSS_TC_SIZE_6             64
  60 #define HCLGE_RSS_TC_SIZE_7             128
  61
  62 #define HCLGE_TQP_RESET_TRY_TIMES       10
  63
  64 #define HCLGE_PHY_PAGE_MDIX             0
  65 #define HCLGE_PHY_PAGE_COPPER           0
  66
  67 /* Page Selection Reg. */
  68 #define HCLGE_PHY_PAGE_REG              22
  69
  70 /* Copper Specific Control Register */
  71 #define HCLGE_PHY_CSC_REG               16
  72
  73 /* Copper Specific Status Register */
  74 #define HCLGE_PHY_CSS_REG               17
  75
  76 #define HCLGE_PHY_MDIX_CTRL_S           (5)
  77 #define HCLGE_PHY_MDIX_CTRL_M           GENMASK(6, 5)
  78
  79 #define HCLGE_PHY_MDIX_STATUS_B (6)
  80 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B   (11)
  81
  82 /* Reset related Registers */
  83 #define HCLGE_MISC_RESET_STS_REG        0x20700
  84 #define HCLGE_GLOBAL_RESET_REG          0x20A00
  85 #define HCLGE_GLOBAL_RESET_BIT          0x0
  86 #define HCLGE_CORE_RESET_BIT            0x1
  87 #define HCLGE_FUN_RST_ING               0x20C00
  88 #define HCLGE_FUN_RST_ING_B             0
  89
  90 /* Vector0 register bits define */
  91 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
  92 #define HCLGE_VECTOR0_CORERESET_INT_B   6
  93 #define HCLGE_VECTOR0_IMPRESET_INT_B    7
  94
  95 enum HCLGE_DEV_STATE {
  96         HCLGE_STATE_REINITING,
  97         HCLGE_STATE_DOWN,
  98         HCLGE_STATE_DISABLED,
  99         HCLGE_STATE_REMOVING,
 100         HCLGE_STATE_SERVICE_INITED,
 101         HCLGE_STATE_SERVICE_SCHED,
 102         HCLGE_STATE_RST_SERVICE_SCHED,
 103         HCLGE_STATE_RST_HANDLING,
 104         HCLGE_STATE_MBX_HANDLING,
 105         HCLGE_STATE_MBX_IRQ,
 106         HCLGE_STATE_RESET_INT,
 107         HCLGE_STATE_MAX
 108 };
 109
 110 enum hclge_evt_cause {
 111         HCLGE_VECTOR0_EVENT_RST,
 112         HCLGE_VECTOR0_EVENT_MBX,
 113         HCLGE_VECTOR0_EVENT_OTHER,
 114 };
 115
 116 #define HCLGE_MPF_ENBALE 1
 117 struct hclge_caps {
 118         u16 num_tqp;
 119         u16 num_buffer_cell;
 120         u32 flag;
 121         u16 vmdq;
 122 };
 123
 124 enum HCLGE_MAC_SPEED {
 125         HCLGE_MAC_SPEED_10M     = 10,           /* 10 Mbps */
 126         HCLGE_MAC_SPEED_100M    = 100,          /* 100 Mbps */
 127         HCLGE_MAC_SPEED_1G      = 1000,         /* 1000 Mbps   = 1 Gbps */
 128         HCLGE_MAC_SPEED_10G     = 10000,        /* 10000 Mbps  = 10 Gbps */
 129         HCLGE_MAC_SPEED_25G     = 25000,        /* 25000 Mbps  = 25 Gbps */
 130         HCLGE_MAC_SPEED_40G     = 40000,        /* 40000 Mbps  = 40 Gbps */
 131         HCLGE_MAC_SPEED_50G     = 50000,        /* 50000 Mbps  = 50 Gbps */
 132         HCLGE_MAC_SPEED_100G    = 100000        /* 100000 Mbps = 100 Gbps */
 133 };
 134
 135 enum HCLGE_MAC_DUPLEX {
 136         HCLGE_MAC_HALF,
 137         HCLGE_MAC_FULL
 138 };
 139
 140 enum hclge_mta_dmac_sel_type {
 141         HCLGE_MAC_ADDR_47_36,
 142         HCLGE_MAC_ADDR_46_35,
 143         HCLGE_MAC_ADDR_45_34,
 144         HCLGE_MAC_ADDR_44_33,
 145 };
 146
 147 struct hclge_mac {
 148         u8 phy_addr;
 149         u8 flag;
 150         u8 media_type;
 151         u8 mac_addr[ETH_ALEN];
 152         u8 autoneg;
 153         u8 duplex;
 154         u32 speed;
 155         int link;       /* store the link status of mac & phy (if phy exit)*/
 156         struct phy_device *phydev;
 157         struct mii_bus *mdio_bus;
 158         phy_interface_t phy_if;
 159 };
 160
 161 struct hclge_hw {
 162         void __iomem *io_base;
 163         struct hclge_mac mac;
 164         int num_vec;
 165         struct hclge_cmq cmq;
 166         struct hclge_caps caps;
 167         void *back;
 168 };
 169
 170 /* TQP stats */
 171 struct hlcge_tqp_stats {
 172         /* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
 173         u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
 174         /* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
 175         u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
 176 };
 177
 178 struct hclge_tqp {
 179         struct device *dev;     /* Device for DMA mapping */
 180         struct hnae3_queue q;
 181         struct hlcge_tqp_stats tqp_stats;
 182         u16 index;      /* Global index in a NIC controller */
 183
 184         bool alloced;
 185 };
 186
 187 enum hclge_fc_mode {
 188         HCLGE_FC_NONE,
 189         HCLGE_FC_RX_PAUSE,
 190         HCLGE_FC_TX_PAUSE,
 191         HCLGE_FC_FULL,
 192         HCLGE_FC_PFC,
 193         HCLGE_FC_DEFAULT
 194 };
 195
 196 #define HCLGE_PG_NUM            4
 197 #define HCLGE_SCH_MODE_SP       0
 198 #define HCLGE_SCH_MODE_DWRR     1
 199 struct hclge_pg_info {
 200         u8 pg_id;
 201         u8 pg_sch_mode;         /* 0: sp; 1: dwrr */
 202         u8 tc_bit_map;
 203         u32 bw_limit;
 204         u8 tc_dwrr[HNAE3_MAX_TC];
 205 };
 206
 207 struct hclge_tc_info {
 208         u8 tc_id;
 209         u8 tc_sch_mode;         /* 0: sp; 1: dwrr */
 210         u8 pgid;
 211         u32 bw_limit;
 212 };
 213
 214 struct hclge_cfg {
 215         u8 vmdq_vport_num;
 216         u8 tc_num;
 217         u16 tqp_desc_num;
 218         u16 rx_buf_len;
 219         u8 phy_addr;
 220         u8 media_type;
 221         u8 mac_addr[ETH_ALEN];
 222         u8 default_speed;
 223         u32 numa_node_map;
 224 };
 225
 226 struct hclge_tm_info {
 227         u8 num_tc;
 228         u8 num_pg;      /* It must be 1 if vNET-Base schd */
 229         u8 pg_dwrr[HCLGE_PG_NUM];
 230         u8 prio_tc[HNAE3_MAX_USER_PRIO];
 231         struct hclge_pg_info pg_info[HCLGE_PG_NUM];
 232         struct hclge_tc_info tc_info[HNAE3_MAX_TC];
 233         enum hclge_fc_mode fc_mode;
 234         u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
 235 };
 236
 237 struct hclge_comm_stats_str {
 238         char desc[ETH_GSTRING_LEN];
 239         unsigned long offset;
 240 };
 241
 242 /* all 64bit stats, opcode id: 0x0030 */
 243 struct hclge_64_bit_stats {
 244         /* query_igu_stat */
 245         u64 igu_rx_oversize_pkt;
 246         u64 igu_rx_undersize_pkt;
 247         u64 igu_rx_out_all_pkt;
 248         u64 igu_rx_uni_pkt;
 249         u64 igu_rx_multi_pkt;
 250         u64 igu_rx_broad_pkt;
 251         u64 rsv0;
 252
 253         /* query_egu_stat */
 254         u64 egu_tx_out_all_pkt;
 255         u64 egu_tx_uni_pkt;
 256         u64 egu_tx_multi_pkt;
 257         u64 egu_tx_broad_pkt;
 258
 259         /* ssu_ppp packet stats */
 260         u64 ssu_ppp_mac_key_num;
 261         u64 ssu_ppp_host_key_num;
 262         u64 ppp_ssu_mac_rlt_num;
 263         u64 ppp_ssu_host_rlt_num;
 264
 265         /* ssu_tx_in_out_dfx_stats */
 266         u64 ssu_tx_in_num;
 267         u64 ssu_tx_out_num;
 268         /* ssu_rx_in_out_dfx_stats */
 269         u64 ssu_rx_in_num;
 270         u64 ssu_rx_out_num;
 271 };
 272
 273 /* all 32bit stats, opcode id: 0x0031 */
 274 struct hclge_32_bit_stats {
 275         u64 igu_rx_err_pkt;
 276         u64 igu_rx_no_eof_pkt;
 277         u64 igu_rx_no_sof_pkt;
 278         u64 egu_tx_1588_pkt;
 279         u64 egu_tx_err_pkt;
 280         u64 ssu_full_drop_num;
 281         u64 ssu_part_drop_num;
 282         u64 ppp_key_drop_num;
 283         u64 ppp_rlt_drop_num;
 284         u64 ssu_key_drop_num;
 285         u64 pkt_curr_buf_cnt;
 286         u64 qcn_fb_rcv_cnt;
 287         u64 qcn_fb_drop_cnt;
 288         u64 qcn_fb_invaild_cnt;
 289         u64 rsv0;
 290         u64 rx_packet_tc0_in_cnt;
 291         u64 rx_packet_tc1_in_cnt;
 292         u64 rx_packet_tc2_in_cnt;
 293         u64 rx_packet_tc3_in_cnt;
 294         u64 rx_packet_tc4_in_cnt;
 295         u64 rx_packet_tc5_in_cnt;
 296         u64 rx_packet_tc6_in_cnt;
 297         u64 rx_packet_tc7_in_cnt;
 298         u64 rx_packet_tc0_out_cnt;
 299         u64 rx_packet_tc1_out_cnt;
 300         u64 rx_packet_tc2_out_cnt;
 301         u64 rx_packet_tc3_out_cnt;
 302         u64 rx_packet_tc4_out_cnt;
 303         u64 rx_packet_tc5_out_cnt;
 304         u64 rx_packet_tc6_out_cnt;
 305         u64 rx_packet_tc7_out_cnt;
 306
 307         /* Tx packet level statistics */
 308         u64 tx_packet_tc0_in_cnt;
 309         u64 tx_packet_tc1_in_cnt;
 310         u64 tx_packet_tc2_in_cnt;
 311         u64 tx_packet_tc3_in_cnt;
 312         u64 tx_packet_tc4_in_cnt;
 313         u64 tx_packet_tc5_in_cnt;
 314         u64 tx_packet_tc6_in_cnt;
 315         u64 tx_packet_tc7_in_cnt;
 316         u64 tx_packet_tc0_out_cnt;
 317         u64 tx_packet_tc1_out_cnt;
 318         u64 tx_packet_tc2_out_cnt;
 319         u64 tx_packet_tc3_out_cnt;
 320         u64 tx_packet_tc4_out_cnt;
 321         u64 tx_packet_tc5_out_cnt;
 322         u64 tx_packet_tc6_out_cnt;
 323         u64 tx_packet_tc7_out_cnt;
 324
 325         /* packet buffer statistics */
 326         u64 pkt_curr_buf_tc0_cnt;
 327         u64 pkt_curr_buf_tc1_cnt;
 328         u64 pkt_curr_buf_tc2_cnt;
 329         u64 pkt_curr_buf_tc3_cnt;
 330         u64 pkt_curr_buf_tc4_cnt;
 331         u64 pkt_curr_buf_tc5_cnt;
 332         u64 pkt_curr_buf_tc6_cnt;
 333         u64 pkt_curr_buf_tc7_cnt;
 334
 335         u64 mb_uncopy_num;
 336         u64 lo_pri_unicast_rlt_drop_num;
 337         u64 hi_pri_multicast_rlt_drop_num;
 338         u64 lo_pri_multicast_rlt_drop_num;
 339         u64 rx_oq_drop_pkt_cnt;
 340         u64 tx_oq_drop_pkt_cnt;
 341         u64 nic_l2_err_drop_pkt_cnt;
 342         u64 roc_l2_err_drop_pkt_cnt;
 343 };
 344
 345 /* mac stats ,opcode id: 0x0032 */
 346 struct hclge_mac_stats {
 347         u64 mac_tx_mac_pause_num;
 348         u64 mac_rx_mac_pause_num;
 349         u64 mac_tx_pfc_pri0_pkt_num;
 350         u64 mac_tx_pfc_pri1_pkt_num;
 351         u64 mac_tx_pfc_pri2_pkt_num;
 352         u64 mac_tx_pfc_pri3_pkt_num;
 353         u64 mac_tx_pfc_pri4_pkt_num;
 354         u64 mac_tx_pfc_pri5_pkt_num;
 355         u64 mac_tx_pfc_pri6_pkt_num;
 356         u64 mac_tx_pfc_pri7_pkt_num;
 357         u64 mac_rx_pfc_pri0_pkt_num;
 358         u64 mac_rx_pfc_pri1_pkt_num;
 359         u64 mac_rx_pfc_pri2_pkt_num;
 360         u64 mac_rx_pfc_pri3_pkt_num;
 361         u64 mac_rx_pfc_pri4_pkt_num;
 362         u64 mac_rx_pfc_pri5_pkt_num;
 363         u64 mac_rx_pfc_pri6_pkt_num;
 364         u64 mac_rx_pfc_pri7_pkt_num;
 365         u64 mac_tx_total_pkt_num;
 366         u64 mac_tx_total_oct_num;
 367         u64 mac_tx_good_pkt_num;
 368         u64 mac_tx_bad_pkt_num;
 369         u64 mac_tx_good_oct_num;
 370         u64 mac_tx_bad_oct_num;
 371         u64 mac_tx_uni_pkt_num;
 372         u64 mac_tx_multi_pkt_num;
 373         u64 mac_tx_broad_pkt_num;
 374         u64 mac_tx_undersize_pkt_num;
 375         u64 mac_tx_overrsize_pkt_num;
 376         u64 mac_tx_64_oct_pkt_num;
 377         u64 mac_tx_65_127_oct_pkt_num;
 378         u64 mac_tx_128_255_oct_pkt_num;
 379         u64 mac_tx_256_511_oct_pkt_num;
 380         u64 mac_tx_512_1023_oct_pkt_num;
 381         u64 mac_tx_1024_1518_oct_pkt_num;
 382         u64 mac_tx_1519_max_oct_pkt_num;
 383         u64 mac_rx_total_pkt_num;
 384         u64 mac_rx_total_oct_num;
 385         u64 mac_rx_good_pkt_num;
 386         u64 mac_rx_bad_pkt_num;
 387         u64 mac_rx_good_oct_num;
 388         u64 mac_rx_bad_oct_num;
 389         u64 mac_rx_uni_pkt_num;
 390         u64 mac_rx_multi_pkt_num;
 391         u64 mac_rx_broad_pkt_num;
 392         u64 mac_rx_undersize_pkt_num;
 393         u64 mac_rx_overrsize_pkt_num;
 394         u64 mac_rx_64_oct_pkt_num;
 395         u64 mac_rx_65_127_oct_pkt_num;
 396         u64 mac_rx_128_255_oct_pkt_num;
 397         u64 mac_rx_256_511_oct_pkt_num;
 398         u64 mac_rx_512_1023_oct_pkt_num;
 399         u64 mac_rx_1024_1518_oct_pkt_num;
 400         u64 mac_rx_1519_max_oct_pkt_num;
 401
 402         u64 mac_trans_fragment_pkt_num;
 403         u64 mac_trans_undermin_pkt_num;
 404         u64 mac_trans_jabber_pkt_num;
 405         u64 mac_trans_err_all_pkt_num;
 406         u64 mac_trans_from_app_good_pkt_num;
 407         u64 mac_trans_from_app_bad_pkt_num;
 408         u64 mac_rcv_fragment_pkt_num;
 409         u64 mac_rcv_undermin_pkt_num;
 410         u64 mac_rcv_jabber_pkt_num;
 411         u64 mac_rcv_fcs_err_pkt_num;
 412         u64 mac_rcv_send_app_good_pkt_num;
 413         u64 mac_rcv_send_app_bad_pkt_num;
 414 };
 415
 416 struct hclge_hw_stats {
 417         struct hclge_mac_stats      mac_stats;
 418         struct hclge_64_bit_stats   all_64_bit_stats;
 419         struct hclge_32_bit_stats   all_32_bit_stats;
 420 };
 421
 422 struct hclge_dev {
 423         struct pci_dev *pdev;
 424         struct hnae3_ae_dev *ae_dev;
 425         struct hclge_hw hw;
 426         struct hclge_misc_vector misc_vector;
 427         struct hclge_hw_stats hw_stats;
 428         unsigned long state;
 429
 430         enum hnae3_reset_type reset_type;
 431         unsigned long reset_request;    /* reset has been requested */
 432         unsigned long reset_pending;    /* client rst is pending to be served */
 433         u32 fw_version;
 434         u16 num_vmdq_vport;             /* Num vmdq vport this PF has set up */
 435         u16 num_tqps;                   /* Num task queue pairs of this PF */
 436         u16 num_req_vfs;                /* Num VFs requested for this PF */
 437
 438         /* Base task tqp physical id of this PF */
 439         u16 base_tqp_pid;
 440         u16 alloc_rss_size;             /* Allocated RSS task queue */
 441         u16 rss_size_max;               /* HW defined max RSS task queue */
 442
 443         /* Num of guaranteed filters for this PF */
 444         u16 fdir_pf_filter_count;
 445         u16 num_alloc_vport;            /* Num vports this driver supports */
 446         u32 numa_node_mask;
 447         u16 rx_buf_len;
 448         u16 num_desc;
 449         u8 hw_tc_map;
 450         u8 tc_num_last_time;
 451         enum hclge_fc_mode fc_mode_last_time;
 452
 453 #define HCLGE_FLAG_TC_BASE_SCH_MODE             1
 454 #define HCLGE_FLAG_VNET_BASE_SCH_MODE           2
 455         u8 tx_sch_mode;
 456         u8 tc_max;
 457         u8 pfc_max;
 458
 459         u8 default_up;
 460         u8 dcbx_cap;
 461         struct hclge_tm_info tm_info;
 462
 463         u16 num_msi;
 464         u16 num_msi_left;
 465         u16 num_msi_used;
 466         u32 base_msi_vector;
 467         u16 *vector_status;
 468         int *vector_irq;
 469         u16 num_roce_msi;       /* Num of roce vectors for this PF */
 470         int roce_base_vector;
 471
 472         u16 pending_udp_bitmap;
 473
 474         u16 rx_itr_default;
 475         u16 tx_itr_default;
 476
 477         u16 adminq_work_limit; /* Num of admin receive queue desc to process */
 478         unsigned long service_timer_period;
 479         unsigned long service_timer_previous;
 480         struct timer_list service_timer;
 481         struct work_struct service_task;
 482         struct work_struct rst_service_task;
 483
 484         bool cur_promisc;
 485         int num_alloc_vfs;      /* Actual number of VFs allocated */
 486
 487         struct hclge_tqp *htqp;
 488         struct hclge_vport *vport;
 489
 490         struct dentry *hclge_dbgfs;
 491
 492         struct hnae3_client *nic_client;
 493         struct hnae3_client *roce_client;
 494
 495 #define HCLGE_FLAG_MAIN                 BIT(0)
 496 #define HCLGE_FLAG_DCB_CAPABLE          BIT(1)
 497 #define HCLGE_FLAG_DCB_ENABLE           BIT(2)
 498 #define HCLGE_FLAG_MQPRIO_ENABLE        BIT(3)
 499         u32 flag;
 500
 501         u32 pkt_buf_size; /* Total pf buf size for tx/rx */
 502         u32 mps; /* Max packet size */
 503
 504         enum hclge_mta_dmac_sel_type mta_mac_sel_type;
 505         bool enable_mta; /* Mutilcast filter enable */
 506         bool accept_mta_mc; /* Whether accept mta filter multicast */
 507 };
 508
 509 struct hclge_vport {
 510         u16 alloc_tqps; /* Allocated Tx/Rx queues */
 511
 512         u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
 513         /* User configured lookup table entries */
 514         u8  rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
 515         u16 alloc_rss_size;
 516
 517         u16 qs_offset;
 518         u16 bw_limit;           /* VSI BW Limit (0 = disabled) */
 519         u8  dwrr;
 520
 521         int vport_id;
 522         struct hclge_dev *back;  /* Back reference to associated dev */
 523         struct hnae3_handle nic;
 524         struct hnae3_handle roce;
 525 };
 526
 527 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
 528                               bool en_mc, bool en_bc, int vport_id);
 529
 530 int hclge_add_uc_addr_common(struct hclge_vport *vport,
 531                              const unsigned char *addr);
 532 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
 533                             const unsigned char *addr);
 534 int hclge_add_mc_addr_common(struct hclge_vport *vport,
 535                              const unsigned char *addr);
 536 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
 537                             const unsigned char *addr);
 538
 539 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
 540                               u8 func_id,
 541                               bool enable);
 542 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
 543 int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector,
 544                                    struct hnae3_ring_chain_node *ring_chain);
 545 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
 546 {
 547         struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
 548
 549         return tqp->index;
 550 }
 551
 552 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
 553 int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid,
 554                              bool is_kill, u16 vlan, u8 qos, __be16 proto);
 555
 556 int hclge_buffer_alloc(struct hclge_dev *hdev);
 557 int hclge_rss_init_hw(struct hclge_dev *hdev);
 558 #endif