drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/device.h>
   5 #include <linux/dma-direction.h>
   6 #include <linux/dma-mapping.h>
   7 #include <linux/err.h>
   8 #include <linux/pci.h>
   9 #include <linux/slab.h>
  10 #include "hclgevf_cmd.h"
  11 #include "hclgevf_main.h"
  12 #include "hnae3.h"
  13
  14 #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
  15
  16 static int hclgevf_ring_space(struct hclgevf_cmq_ring *ring)
  17 {
  18         int ntc = ring->next_to_clean;
  19         int ntu = ring->next_to_use;
  20         int used;
  21
  22         used = (ntu - ntc + ring->desc_num) % ring->desc_num;
  23
  24         return ring->desc_num - used - 1;
  25 }
  26
  27 static int hclgevf_is_valid_csq_clean_head(struct hclgevf_cmq_ring *ring,
  28                                            int head)
  29 {
  30         int ntu = ring->next_to_use;
  31         int ntc = ring->next_to_clean;
  32
  33         if (ntu > ntc)
  34                 return head >= ntc && head <= ntu;
  35
  36         return head >= ntc || head <= ntu;
  37 }
  38
  39 static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw)
  40 {
  41         struct hclgevf_dev *hdev = container_of(hw, struct hclgevf_dev, hw);
  42         struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
  43         int clean;
  44         u32 head;
  45
  46         head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
  47         rmb(); /* Make sure head is ready before touch any data */
  48
  49         if (!hclgevf_is_valid_csq_clean_head(csq, head)) {
  50                 dev_warn(&hdev->pdev->dev, "wrong cmd head (%u, %d-%d)\n", head,
  51                          csq->next_to_use, csq->next_to_clean);
  52                 dev_warn(&hdev->pdev->dev,
  53                          "Disabling any further commands to IMP firmware\n");
  54                 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
  55                 return -EIO;
  56         }
  57
  58         clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
  59         csq->next_to_clean = head;
  60         return clean;
  61 }
  62
  63 static bool hclgevf_cmd_csq_done(struct hclgevf_hw *hw)
  64 {
  65         u32 head;
  66
  67         head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
  68
  69         return head == hw->cmq.csq.next_to_use;
  70 }
  71
  72 static bool hclgevf_is_special_opcode(u16 opcode)
  73 {
  74         static const u16 spec_opcode[] = {0x30, 0x31, 0x32};
  75         int i;
  76
  77         for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
  78                 if (spec_opcode[i] == opcode)
  79                         return true;
  80         }
  81
  82         return false;
  83 }
  84
  85 static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring)
  86 {
  87         struct hclgevf_dev *hdev = ring->dev;
  88         struct hclgevf_hw *hw = &hdev->hw;
  89         u32 reg_val;
  90
  91         if (ring->flag == HCLGEVF_TYPE_CSQ) {
  92                 reg_val = lower_32_bits(ring->desc_dma_addr);
  93                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
  94                 reg_val = upper_32_bits(ring->desc_dma_addr);
  95                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val);
  96
  97                 reg_val = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
  98                 reg_val &= HCLGEVF_NIC_SW_RST_RDY;
  99                 reg_val |= (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
 100                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, reg_val);
 101
 102                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
 103                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
 104         } else {
 105                 reg_val = lower_32_bits(ring->desc_dma_addr);
 106                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val);
 107                 reg_val = upper_32_bits(ring->desc_dma_addr);
 108                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val);
 109
 110                 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
 111                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, reg_val);
 112
 113                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
 114                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
 115         }
 116 }
 117
 118 static void hclgevf_cmd_init_regs(struct hclgevf_hw *hw)
 119 {
 120         hclgevf_cmd_config_regs(&hw->cmq.csq);
 121         hclgevf_cmd_config_regs(&hw->cmq.crq);
 122 }
 123
 124 static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
 125 {
 126         int size = ring->desc_num * sizeof(struct hclgevf_desc);
 127
 128         ring->desc = dma_alloc_coherent(cmq_ring_to_dev(ring), size,
 129                                         &ring->desc_dma_addr, GFP_KERNEL);
 130         if (!ring->desc)
 131                 return -ENOMEM;
 132
 133         return 0;
 134 }
 135
 136 static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
 137 {
 138         int size  = ring->desc_num * sizeof(struct hclgevf_desc);
 139
 140         if (ring->desc) {
 141                 dma_free_coherent(cmq_ring_to_dev(ring), size,
 142                                   ring->desc, ring->desc_dma_addr);
 143                 ring->desc = NULL;
 144         }
 145 }
 146
 147 static int hclgevf_alloc_cmd_queue(struct hclgevf_dev *hdev, int ring_type)
 148 {
 149         struct hclgevf_hw *hw = &hdev->hw;
 150         struct hclgevf_cmq_ring *ring =
 151                 (ring_type == HCLGEVF_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
 152         int ret;
 153
 154         ring->dev = hdev;
 155         ring->flag = ring_type;
 156
 157         /* allocate CSQ/CRQ descriptor */
 158         ret = hclgevf_alloc_cmd_desc(ring);
 159         if (ret)
 160                 dev_err(&hdev->pdev->dev, "failed(%d) to alloc %s desc\n", ret,
 161                         (ring_type == HCLGEVF_TYPE_CSQ) ? "CSQ" : "CRQ");
 162
 163         return ret;
 164 }
 165
 166 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
 167                                   enum hclgevf_opcode_type opcode, bool is_read)
 168 {
 169         memset(desc, 0, sizeof(struct hclgevf_desc));
 170         desc->opcode = cpu_to_le16(opcode);
 171         desc->flag = cpu_to_le16(HCLGEVF_CMD_FLAG_NO_INTR |
 172                                  HCLGEVF_CMD_FLAG_IN);
 173         if (is_read)
 174                 desc->flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_WR);
 175         else
 176                 desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
 177 }
 178
 179 static int hclgevf_cmd_convert_err_code(u16 desc_ret)
 180 {
 181         switch (desc_ret) {
 182         case HCLGEVF_CMD_EXEC_SUCCESS:
 183                 return 0;
 184         case HCLGEVF_CMD_NO_AUTH:
 185                 return -EPERM;
 186         case HCLGEVF_CMD_NOT_SUPPORTED:
 187                 return -EOPNOTSUPP;
 188         case HCLGEVF_CMD_QUEUE_FULL:
 189                 return -EXFULL;
 190         case HCLGEVF_CMD_NEXT_ERR:
 191                 return -ENOSR;
 192         case HCLGEVF_CMD_UNEXE_ERR:
 193                 return -ENOTBLK;
 194         case HCLGEVF_CMD_PARA_ERR:
 195                 return -EINVAL;
 196         case HCLGEVF_CMD_RESULT_ERR:
 197                 return -ERANGE;
 198         case HCLGEVF_CMD_TIMEOUT:
 199                 return -ETIME;
 200         case HCLGEVF_CMD_HILINK_ERR:
 201                 return -ENOLINK;
 202         case HCLGEVF_CMD_QUEUE_ILLEGAL:
 203                 return -ENXIO;
 204         case HCLGEVF_CMD_INVALID:
 205                 return -EBADR;
 206         default:
 207                 return -EIO;
 208         }
 209 }
 210
 211 /* hclgevf_cmd_send - send command to command queue
 212  * @hw: pointer to the hw struct
 213  * @desc: prefilled descriptor for describing the command
 214  * @num : the number of descriptors to be sent
 215  *
 216  * This is the main send command for command queue, it
 217  * sends the queue, cleans the queue, etc
 218  */
 219 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
 220 {
 221         struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
 222         struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
 223         struct hclgevf_desc *desc_to_use;
 224         bool complete = false;
 225         u32 timeout = 0;
 226         int handle = 0;
 227         int status = 0;
 228         u16 retval;
 229         u16 opcode;
 230         int ntc;
 231
 232         spin_lock_bh(&hw->cmq.csq.lock);
 233
 234         if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
 235                 spin_unlock_bh(&hw->cmq.csq.lock);
 236                 return -EBUSY;
 237         }
 238
 239         if (num > hclgevf_ring_space(&hw->cmq.csq)) {
 240                 /* If CMDQ ring is full, SW HEAD and HW HEAD may be different,
 241                  * need update the SW HEAD pointer csq->next_to_clean
 242                  */
 243                 csq->next_to_clean = hclgevf_read_dev(hw,
 244                                                       HCLGEVF_NIC_CSQ_HEAD_REG);
 245                 spin_unlock_bh(&hw->cmq.csq.lock);
 246                 return -EBUSY;
 247         }
 248
 249         /* Record the location of desc in the ring for this time
 250          * which will be use for hardware to write back
 251          */
 252         ntc = hw->cmq.csq.next_to_use;
 253         opcode = le16_to_cpu(desc[0].opcode);
 254         while (handle < num) {
 255                 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
 256                 *desc_to_use = desc[handle];
 257                 (hw->cmq.csq.next_to_use)++;
 258                 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
 259                         hw->cmq.csq.next_to_use = 0;
 260                 handle++;
 261         }
 262
 263         /* Write to hardware */
 264         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG,
 265                           hw->cmq.csq.next_to_use);
 266
 267         /* If the command is sync, wait for the firmware to write back,
 268          * if multi descriptors to be sent, use the first one to check
 269          */
 270         if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
 271                 do {
 272                         if (hclgevf_cmd_csq_done(hw))
 273                                 break;
 274                         udelay(1);
 275                         timeout++;
 276                 } while (timeout < hw->cmq.tx_timeout);
 277         }
 278
 279         if (hclgevf_cmd_csq_done(hw)) {
 280                 complete = true;
 281                 handle = 0;
 282
 283                 while (handle < num) {
 284                         /* Get the result of hardware write back */
 285                         desc_to_use = &hw->cmq.csq.desc[ntc];
 286                         desc[handle] = *desc_to_use;
 287
 288                         if (likely(!hclgevf_is_special_opcode(opcode)))
 289                                 retval = le16_to_cpu(desc[handle].retval);
 290                         else
 291                                 retval = le16_to_cpu(desc[0].retval);
 292
 293                         status = hclgevf_cmd_convert_err_code(retval);
 294                         hw->cmq.last_status = (enum hclgevf_cmd_status)retval;
 295                         ntc++;
 296                         handle++;
 297                         if (ntc == hw->cmq.csq.desc_num)
 298                                 ntc = 0;
 299                 }
 300         }
 301
 302         if (!complete)
 303                 status = -EBADE;
 304
 305         /* Clean the command send queue */
 306         handle = hclgevf_cmd_csq_clean(hw);
 307         if (handle != num)
 308                 dev_warn(&hdev->pdev->dev,
 309                          "cleaned %d, need to clean %d\n", handle, num);
 310
 311         spin_unlock_bh(&hw->cmq.csq.lock);
 312
 313         return status;
 314 }
 315
 316 static void hclgevf_set_default_capability(struct hclgevf_dev *hdev)
 317 {
 318         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
 319
 320         set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
 321         set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
 322         set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
 323 }
 324
 325 static void hclgevf_parse_capability(struct hclgevf_dev *hdev,
 326                                      struct hclgevf_query_version_cmd *cmd)
 327 {
 328         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
 329         u32 caps;
 330
 331         caps = __le32_to_cpu(cmd->caps[0]);
 332
 333         if (hnae3_get_bit(caps, HCLGEVF_CAP_UDP_GSO_B))
 334                 set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
 335         if (hnae3_get_bit(caps, HCLGEVF_CAP_INT_QL_B))
 336                 set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
 337         if (hnae3_get_bit(caps, HCLGEVF_CAP_TQP_TXRX_INDEP_B))
 338                 set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
 339         if (hnae3_get_bit(caps, HCLGEVF_CAP_HW_TX_CSUM_B))
 340                 set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
 341         if (hnae3_get_bit(caps, HCLGEVF_CAP_UDP_TUNNEL_CSUM_B))
 342                 set_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps);
 343 }
 344
 345 static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
 346 {
 347         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
 348         struct hclgevf_query_version_cmd *resp;
 349         struct hclgevf_desc desc;
 350         int status;
 351
 352         resp = (struct hclgevf_query_version_cmd *)desc.data;
 353
 354         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_FW_VER, 1);
 355         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 356         if (status)
 357                 return status;
 358
 359         hdev->fw_version = le32_to_cpu(resp->firmware);
 360
 361         ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
 362                                  HNAE3_PCI_REVISION_BIT_SIZE;
 363         ae_dev->dev_version |= hdev->pdev->revision;
 364
 365         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
 366                 hclgevf_set_default_capability(hdev);
 367
 368         hclgevf_parse_capability(hdev, resp);
 369
 370         return status;
 371 }
 372
 373 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
 374 {
 375         int ret;
 376
 377         /* Setup the lock for command queue */
 378         spin_lock_init(&hdev->hw.cmq.csq.lock);
 379         spin_lock_init(&hdev->hw.cmq.crq.lock);
 380
 381         hdev->hw.cmq.tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
 382         hdev->hw.cmq.csq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
 383         hdev->hw.cmq.crq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
 384
 385         ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CSQ);
 386         if (ret) {
 387                 dev_err(&hdev->pdev->dev,
 388                         "CSQ ring setup error %d\n", ret);
 389                 return ret;
 390         }
 391
 392         ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CRQ);
 393         if (ret) {
 394                 dev_err(&hdev->pdev->dev,
 395                         "CRQ ring setup error %d\n", ret);
 396                 goto err_csq;
 397         }
 398
 399         return 0;
 400 err_csq:
 401         hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
 402         return ret;
 403 }
 404
 405 int hclgevf_cmd_init(struct hclgevf_dev *hdev)
 406 {
 407         int ret;
 408
 409         spin_lock_bh(&hdev->hw.cmq.csq.lock);
 410         spin_lock(&hdev->hw.cmq.crq.lock);
 411
 412         /* initialize the pointers of async rx queue of mailbox */
 413         hdev->arq.hdev = hdev;
 414         hdev->arq.head = 0;
 415         hdev->arq.tail = 0;
 416         atomic_set(&hdev->arq.count, 0);
 417         hdev->hw.cmq.csq.next_to_clean = 0;
 418         hdev->hw.cmq.csq.next_to_use = 0;
 419         hdev->hw.cmq.crq.next_to_clean = 0;
 420         hdev->hw.cmq.crq.next_to_use = 0;
 421
 422         hclgevf_cmd_init_regs(&hdev->hw);
 423
 424         spin_unlock(&hdev->hw.cmq.crq.lock);
 425         spin_unlock_bh(&hdev->hw.cmq.csq.lock);
 426
 427         clear_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 428
 429         /* Check if there is new reset pending, because the higher level
 430          * reset may happen when lower level reset is being processed.
 431          */
 432         if (hclgevf_is_reset_pending(hdev)) {
 433                 ret = -EBUSY;
 434                 goto err_cmd_init;
 435         }
 436
 437         /* get version and device capabilities */
 438         ret = hclgevf_cmd_query_version_and_capability(hdev);
 439         if (ret) {
 440                 dev_err(&hdev->pdev->dev,
 441                         "failed to query version and capabilities, ret = %d\n", ret);
 442                 goto err_cmd_init;
 443         }
 444
 445         dev_info(&hdev->pdev->dev, "The firmware version is %lu.%lu.%lu.%lu\n",
 446                  hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE3_MASK,
 447                                  HNAE3_FW_VERSION_BYTE3_SHIFT),
 448                  hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE2_MASK,
 449                                  HNAE3_FW_VERSION_BYTE2_SHIFT),
 450                  hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE1_MASK,
 451                                  HNAE3_FW_VERSION_BYTE1_SHIFT),
 452                  hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
 453                                  HNAE3_FW_VERSION_BYTE0_SHIFT));
 454
 455         return 0;
 456
 457 err_cmd_init:
 458         set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 459
 460         return ret;
 461 }
 462
 463 static void hclgevf_cmd_uninit_regs(struct hclgevf_hw *hw)
 464 {
 465         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, 0);
 466         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, 0);
 467         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 0);
 468         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
 469         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
 470         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, 0);
 471         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, 0);
 472         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, 0);
 473         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
 474         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
 475 }
 476
 477 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
 478 {
 479         spin_lock_bh(&hdev->hw.cmq.csq.lock);
 480         spin_lock(&hdev->hw.cmq.crq.lock);
 481         set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 482         hclgevf_cmd_uninit_regs(&hdev->hw);
 483         spin_unlock(&hdev->hw.cmq.crq.lock);
 484         spin_unlock_bh(&hdev->hw.cmq.csq.lock);
 485         hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
 486         hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);
 487 }