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net: hns3: Add mtu setting support for vf
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3vf / hclgevf_main.c
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/etherdevice.h>
5 #include <linux/iopoll.h>
6 #include <net/rtnetlink.h>
7 #include "hclgevf_cmd.h"
8 #include "hclgevf_main.h"
9 #include "hclge_mbx.h"
10 #include "hnae3.h"
11
12 #define HCLGEVF_NAME "hclgevf"
13
14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
15 static struct hnae3_ae_algo ae_algovf;
16
17 static const struct pci_device_id ae_algovf_pci_tbl[] = {
18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
20 /* required last entry */
21 {0, }
22 };
23
24 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
25
26 static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
27 struct hnae3_handle *handle)
28 {
29 return container_of(handle, struct hclgevf_dev, nic);
30 }
31
32 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
33 {
34 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
35 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
36 struct hclgevf_desc desc;
37 struct hclgevf_tqp *tqp;
38 int status;
39 int i;
40
41 for (i = 0; i < kinfo->num_tqps; i++) {
42 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
43 hclgevf_cmd_setup_basic_desc(&desc,
44 HCLGEVF_OPC_QUERY_RX_STATUS,
45 true);
46
47 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
48 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
49 if (status) {
50 dev_err(&hdev->pdev->dev,
51 "Query tqp stat fail, status = %d,queue = %d\n",
52 status, i);
53 return status;
54 }
55 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
56 le32_to_cpu(desc.data[1]);
57
58 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
59 true);
60
61 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
62 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
63 if (status) {
64 dev_err(&hdev->pdev->dev,
65 "Query tqp stat fail, status = %d,queue = %d\n",
66 status, i);
67 return status;
68 }
69 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
70 le32_to_cpu(desc.data[1]);
71 }
72
73 return 0;
74 }
75
76 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
77 {
78 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
79 struct hclgevf_tqp *tqp;
80 u64 *buff = data;
81 int i;
82
83 for (i = 0; i < kinfo->num_tqps; i++) {
84 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
85 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
86 }
87 for (i = 0; i < kinfo->num_tqps; i++) {
88 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
89 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
90 }
91
92 return buff;
93 }
94
95 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
96 {
97 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
98
99 return kinfo->num_tqps * 2;
100 }
101
102 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
103 {
104 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
105 u8 *buff = data;
106 int i = 0;
107
108 for (i = 0; i < kinfo->num_tqps; i++) {
109 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
110 struct hclgevf_tqp, q);
111 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
112 tqp->index);
113 buff += ETH_GSTRING_LEN;
114 }
115
116 for (i = 0; i < kinfo->num_tqps; i++) {
117 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
118 struct hclgevf_tqp, q);
119 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
120 tqp->index);
121 buff += ETH_GSTRING_LEN;
122 }
123
124 return buff;
125 }
126
127 static void hclgevf_update_stats(struct hnae3_handle *handle,
128 struct net_device_stats *net_stats)
129 {
130 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
131 int status;
132
133 status = hclgevf_tqps_update_stats(handle);
134 if (status)
135 dev_err(&hdev->pdev->dev,
136 "VF update of TQPS stats fail, status = %d.\n",
137 status);
138 }
139
140 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
141 {
142 if (strset == ETH_SS_TEST)
143 return -EOPNOTSUPP;
144 else if (strset == ETH_SS_STATS)
145 return hclgevf_tqps_get_sset_count(handle, strset);
146
147 return 0;
148 }
149
150 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
151 u8 *data)
152 {
153 u8 *p = (char *)data;
154
155 if (strset == ETH_SS_STATS)
156 p = hclgevf_tqps_get_strings(handle, p);
157 }
158
159 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
160 {
161 hclgevf_tqps_get_stats(handle, data);
162 }
163
164 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
165 {
166 u8 resp_msg;
167 int status;
168
169 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0,
170 true, &resp_msg, sizeof(u8));
171 if (status) {
172 dev_err(&hdev->pdev->dev,
173 "VF request to get TC info from PF failed %d",
174 status);
175 return status;
176 }
177
178 hdev->hw_tc_map = resp_msg;
179
180 return 0;
181 }
182
183 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
184 {
185 #define HCLGEVF_TQPS_RSS_INFO_LEN 8
186 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
187 int status;
188
189 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0,
190 true, resp_msg,
191 HCLGEVF_TQPS_RSS_INFO_LEN);
192 if (status) {
193 dev_err(&hdev->pdev->dev,
194 "VF request to get tqp info from PF failed %d",
195 status);
196 return status;
197 }
198
199 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16));
200 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16));
201 memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16));
202 memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16));
203
204 return 0;
205 }
206
207 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
208 {
209 struct hclgevf_tqp *tqp;
210 int i;
211
212 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
213 sizeof(struct hclgevf_tqp), GFP_KERNEL);
214 if (!hdev->htqp)
215 return -ENOMEM;
216
217 tqp = hdev->htqp;
218
219 for (i = 0; i < hdev->num_tqps; i++) {
220 tqp->dev = &hdev->pdev->dev;
221 tqp->index = i;
222
223 tqp->q.ae_algo = &ae_algovf;
224 tqp->q.buf_size = hdev->rx_buf_len;
225 tqp->q.desc_num = hdev->num_desc;
226 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
227 i * HCLGEVF_TQP_REG_SIZE;
228
229 tqp++;
230 }
231
232 return 0;
233 }
234
235 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
236 {
237 struct hnae3_handle *nic = &hdev->nic;
238 struct hnae3_knic_private_info *kinfo;
239 u16 new_tqps = hdev->num_tqps;
240 int i;
241
242 kinfo = &nic->kinfo;
243 kinfo->num_tc = 0;
244 kinfo->num_desc = hdev->num_desc;
245 kinfo->rx_buf_len = hdev->rx_buf_len;
246 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
247 if (hdev->hw_tc_map & BIT(i))
248 kinfo->num_tc++;
249
250 kinfo->rss_size
251 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
252 new_tqps = kinfo->rss_size * kinfo->num_tc;
253 kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
254
255 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
256 sizeof(struct hnae3_queue *), GFP_KERNEL);
257 if (!kinfo->tqp)
258 return -ENOMEM;
259
260 for (i = 0; i < kinfo->num_tqps; i++) {
261 hdev->htqp[i].q.handle = &hdev->nic;
262 hdev->htqp[i].q.tqp_index = i;
263 kinfo->tqp[i] = &hdev->htqp[i].q;
264 }
265
266 return 0;
267 }
268
269 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
270 {
271 int status;
272 u8 resp_msg;
273
274 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL,
275 0, false, &resp_msg, sizeof(u8));
276 if (status)
277 dev_err(&hdev->pdev->dev,
278 "VF failed to fetch link status(%d) from PF", status);
279 }
280
281 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
282 {
283 struct hnae3_handle *handle = &hdev->nic;
284 struct hnae3_client *client;
285
286 client = handle->client;
287
288 link_state =
289 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
290
291 if (link_state != hdev->hw.mac.link) {
292 client->ops->link_status_change(handle, !!link_state);
293 hdev->hw.mac.link = link_state;
294 }
295 }
296
297 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
298 {
299 struct hnae3_handle *nic = &hdev->nic;
300 int ret;
301
302 nic->ae_algo = &ae_algovf;
303 nic->pdev = hdev->pdev;
304 nic->numa_node_mask = hdev->numa_node_mask;
305 nic->flags |= HNAE3_SUPPORT_VF;
306
307 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) {
308 dev_err(&hdev->pdev->dev, "unsupported device type %d\n",
309 hdev->ae_dev->dev_type);
310 return -EINVAL;
311 }
312
313 ret = hclgevf_knic_setup(hdev);
314 if (ret)
315 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
316 ret);
317 return ret;
318 }
319
320 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
321 {
322 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
323 dev_warn(&hdev->pdev->dev,
324 "vector(vector_id %d) has been freed.\n", vector_id);
325 return;
326 }
327
328 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
329 hdev->num_msi_left += 1;
330 hdev->num_msi_used -= 1;
331 }
332
333 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
334 struct hnae3_vector_info *vector_info)
335 {
336 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
337 struct hnae3_vector_info *vector = vector_info;
338 int alloc = 0;
339 int i, j;
340
341 vector_num = min(hdev->num_msi_left, vector_num);
342
343 for (j = 0; j < vector_num; j++) {
344 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
345 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
346 vector->vector = pci_irq_vector(hdev->pdev, i);
347 vector->io_addr = hdev->hw.io_base +
348 HCLGEVF_VECTOR_REG_BASE +
349 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
350 hdev->vector_status[i] = 0;
351 hdev->vector_irq[i] = vector->vector;
352
353 vector++;
354 alloc++;
355
356 break;
357 }
358 }
359 }
360 hdev->num_msi_left -= alloc;
361 hdev->num_msi_used += alloc;
362
363 return alloc;
364 }
365
366 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
367 {
368 int i;
369
370 for (i = 0; i < hdev->num_msi; i++)
371 if (vector == hdev->vector_irq[i])
372 return i;
373
374 return -EINVAL;
375 }
376
377 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
378 const u8 hfunc, const u8 *key)
379 {
380 struct hclgevf_rss_config_cmd *req;
381 struct hclgevf_desc desc;
382 int key_offset;
383 int key_size;
384 int ret;
385
386 req = (struct hclgevf_rss_config_cmd *)desc.data;
387
388 for (key_offset = 0; key_offset < 3; key_offset++) {
389 hclgevf_cmd_setup_basic_desc(&desc,
390 HCLGEVF_OPC_RSS_GENERIC_CONFIG,
391 false);
392
393 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
394 req->hash_config |=
395 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
396
397 if (key_offset == 2)
398 key_size =
399 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2;
400 else
401 key_size = HCLGEVF_RSS_HASH_KEY_NUM;
402
403 memcpy(req->hash_key,
404 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
405
406 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
407 if (ret) {
408 dev_err(&hdev->pdev->dev,
409 "Configure RSS config fail, status = %d\n",
410 ret);
411 return ret;
412 }
413 }
414
415 return 0;
416 }
417
418 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
419 {
420 return HCLGEVF_RSS_KEY_SIZE;
421 }
422
423 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
424 {
425 return HCLGEVF_RSS_IND_TBL_SIZE;
426 }
427
428 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
429 {
430 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
431 struct hclgevf_rss_indirection_table_cmd *req;
432 struct hclgevf_desc desc;
433 int status;
434 int i, j;
435
436 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
437
438 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
439 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
440 false);
441 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
442 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
443 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
444 req->rss_result[j] =
445 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
446
447 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
448 if (status) {
449 dev_err(&hdev->pdev->dev,
450 "VF failed(=%d) to set RSS indirection table\n",
451 status);
452 return status;
453 }
454 }
455
456 return 0;
457 }
458
459 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size)
460 {
461 struct hclgevf_rss_tc_mode_cmd *req;
462 u16 tc_offset[HCLGEVF_MAX_TC_NUM];
463 u16 tc_valid[HCLGEVF_MAX_TC_NUM];
464 u16 tc_size[HCLGEVF_MAX_TC_NUM];
465 struct hclgevf_desc desc;
466 u16 roundup_size;
467 int status;
468 int i;
469
470 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
471
472 roundup_size = roundup_pow_of_two(rss_size);
473 roundup_size = ilog2(roundup_size);
474
475 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
476 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
477 tc_size[i] = roundup_size;
478 tc_offset[i] = rss_size * i;
479 }
480
481 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
482 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
483 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
484 (tc_valid[i] & 0x1));
485 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
486 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
487 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
488 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
489 }
490 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
491 if (status)
492 dev_err(&hdev->pdev->dev,
493 "VF failed(=%d) to set rss tc mode\n", status);
494
495 return status;
496 }
497
498 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
499 u8 *hfunc)
500 {
501 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
502 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
503 int i;
504
505 if (handle->pdev->revision >= 0x21) {
506 /* Get hash algorithm */
507 if (hfunc) {
508 switch (rss_cfg->hash_algo) {
509 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
510 *hfunc = ETH_RSS_HASH_TOP;
511 break;
512 case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
513 *hfunc = ETH_RSS_HASH_XOR;
514 break;
515 default:
516 *hfunc = ETH_RSS_HASH_UNKNOWN;
517 break;
518 }
519 }
520
521 /* Get the RSS Key required by the user */
522 if (key)
523 memcpy(key, rss_cfg->rss_hash_key,
524 HCLGEVF_RSS_KEY_SIZE);
525 }
526
527 if (indir)
528 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
529 indir[i] = rss_cfg->rss_indirection_tbl[i];
530
531 return 0;
532 }
533
534 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
535 const u8 *key, const u8 hfunc)
536 {
537 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
538 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
539 int ret, i;
540
541 if (handle->pdev->revision >= 0x21) {
542 /* Set the RSS Hash Key if specififed by the user */
543 if (key) {
544 switch (hfunc) {
545 case ETH_RSS_HASH_TOP:
546 rss_cfg->hash_algo =
547 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
548 break;
549 case ETH_RSS_HASH_XOR:
550 rss_cfg->hash_algo =
551 HCLGEVF_RSS_HASH_ALGO_SIMPLE;
552 break;
553 case ETH_RSS_HASH_NO_CHANGE:
554 break;
555 default:
556 return -EINVAL;
557 }
558
559 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
560 key);
561 if (ret)
562 return ret;
563
564 /* Update the shadow RSS key with user specified qids */
565 memcpy(rss_cfg->rss_hash_key, key,
566 HCLGEVF_RSS_KEY_SIZE);
567 }
568 }
569
570 /* update the shadow RSS table with user specified qids */
571 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
572 rss_cfg->rss_indirection_tbl[i] = indir[i];
573
574 /* update the hardware */
575 return hclgevf_set_rss_indir_table(hdev);
576 }
577
578 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
579 {
580 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
581
582 if (nfc->data & RXH_L4_B_2_3)
583 hash_sets |= HCLGEVF_D_PORT_BIT;
584 else
585 hash_sets &= ~HCLGEVF_D_PORT_BIT;
586
587 if (nfc->data & RXH_IP_SRC)
588 hash_sets |= HCLGEVF_S_IP_BIT;
589 else
590 hash_sets &= ~HCLGEVF_S_IP_BIT;
591
592 if (nfc->data & RXH_IP_DST)
593 hash_sets |= HCLGEVF_D_IP_BIT;
594 else
595 hash_sets &= ~HCLGEVF_D_IP_BIT;
596
597 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
598 hash_sets |= HCLGEVF_V_TAG_BIT;
599
600 return hash_sets;
601 }
602
603 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
604 struct ethtool_rxnfc *nfc)
605 {
606 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
607 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
608 struct hclgevf_rss_input_tuple_cmd *req;
609 struct hclgevf_desc desc;
610 u8 tuple_sets;
611 int ret;
612
613 if (handle->pdev->revision == 0x20)
614 return -EOPNOTSUPP;
615
616 if (nfc->data &
617 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
618 return -EINVAL;
619
620 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
621 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
622
623 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
624 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
625 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
626 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
627 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
628 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
629 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
630 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
631
632 tuple_sets = hclgevf_get_rss_hash_bits(nfc);
633 switch (nfc->flow_type) {
634 case TCP_V4_FLOW:
635 req->ipv4_tcp_en = tuple_sets;
636 break;
637 case TCP_V6_FLOW:
638 req->ipv6_tcp_en = tuple_sets;
639 break;
640 case UDP_V4_FLOW:
641 req->ipv4_udp_en = tuple_sets;
642 break;
643 case UDP_V6_FLOW:
644 req->ipv6_udp_en = tuple_sets;
645 break;
646 case SCTP_V4_FLOW:
647 req->ipv4_sctp_en = tuple_sets;
648 break;
649 case SCTP_V6_FLOW:
650 if ((nfc->data & RXH_L4_B_0_1) ||
651 (nfc->data & RXH_L4_B_2_3))
652 return -EINVAL;
653
654 req->ipv6_sctp_en = tuple_sets;
655 break;
656 case IPV4_FLOW:
657 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
658 break;
659 case IPV6_FLOW:
660 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
661 break;
662 default:
663 return -EINVAL;
664 }
665
666 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
667 if (ret) {
668 dev_err(&hdev->pdev->dev,
669 "Set rss tuple fail, status = %d\n", ret);
670 return ret;
671 }
672
673 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
674 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
675 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
676 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
677 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
678 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
679 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
680 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
681 return 0;
682 }
683
684 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
685 struct ethtool_rxnfc *nfc)
686 {
687 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
688 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
689 u8 tuple_sets;
690
691 if (handle->pdev->revision == 0x20)
692 return -EOPNOTSUPP;
693
694 nfc->data = 0;
695
696 switch (nfc->flow_type) {
697 case TCP_V4_FLOW:
698 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
699 break;
700 case UDP_V4_FLOW:
701 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en;
702 break;
703 case TCP_V6_FLOW:
704 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
705 break;
706 case UDP_V6_FLOW:
707 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en;
708 break;
709 case SCTP_V4_FLOW:
710 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
711 break;
712 case SCTP_V6_FLOW:
713 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
714 break;
715 case IPV4_FLOW:
716 case IPV6_FLOW:
717 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
718 break;
719 default:
720 return -EINVAL;
721 }
722
723 if (!tuple_sets)
724 return 0;
725
726 if (tuple_sets & HCLGEVF_D_PORT_BIT)
727 nfc->data |= RXH_L4_B_2_3;
728 if (tuple_sets & HCLGEVF_S_PORT_BIT)
729 nfc->data |= RXH_L4_B_0_1;
730 if (tuple_sets & HCLGEVF_D_IP_BIT)
731 nfc->data |= RXH_IP_DST;
732 if (tuple_sets & HCLGEVF_S_IP_BIT)
733 nfc->data |= RXH_IP_SRC;
734
735 return 0;
736 }
737
738 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
739 struct hclgevf_rss_cfg *rss_cfg)
740 {
741 struct hclgevf_rss_input_tuple_cmd *req;
742 struct hclgevf_desc desc;
743 int ret;
744
745 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
746
747 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
748
749 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
750 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
751 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
752 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
753 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
754 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
755 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
756 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
757
758 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
759 if (ret)
760 dev_err(&hdev->pdev->dev,
761 "Configure rss input fail, status = %d\n", ret);
762 return ret;
763 }
764
765 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
766 {
767 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
768 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
769
770 return rss_cfg->rss_size;
771 }
772
773 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
774 int vector_id,
775 struct hnae3_ring_chain_node *ring_chain)
776 {
777 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
778 struct hnae3_ring_chain_node *node;
779 struct hclge_mbx_vf_to_pf_cmd *req;
780 struct hclgevf_desc desc;
781 int i = 0;
782 int status;
783 u8 type;
784
785 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
786
787 for (node = ring_chain; node; node = node->next) {
788 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM +
789 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i;
790
791 if (i == 0) {
792 hclgevf_cmd_setup_basic_desc(&desc,
793 HCLGEVF_OPC_MBX_VF_TO_PF,
794 false);
795 type = en ?
796 HCLGE_MBX_MAP_RING_TO_VECTOR :
797 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
798 req->msg[0] = type;
799 req->msg[1] = vector_id;
800 }
801
802 req->msg[idx_offset] =
803 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
804 req->msg[idx_offset + 1] = node->tqp_index;
805 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx,
806 HNAE3_RING_GL_IDX_M,
807 HNAE3_RING_GL_IDX_S);
808
809 i++;
810 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM -
811 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) /
812 HCLGE_MBX_RING_NODE_VARIABLE_NUM) ||
813 !node->next) {
814 req->msg[2] = i;
815
816 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
817 if (status) {
818 dev_err(&hdev->pdev->dev,
819 "Map TQP fail, status is %d.\n",
820 status);
821 return status;
822 }
823 i = 0;
824 hclgevf_cmd_setup_basic_desc(&desc,
825 HCLGEVF_OPC_MBX_VF_TO_PF,
826 false);
827 req->msg[0] = type;
828 req->msg[1] = vector_id;
829 }
830 }
831
832 return 0;
833 }
834
835 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
836 struct hnae3_ring_chain_node *ring_chain)
837 {
838 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
839 int vector_id;
840
841 vector_id = hclgevf_get_vector_index(hdev, vector);
842 if (vector_id < 0) {
843 dev_err(&handle->pdev->dev,
844 "Get vector index fail. ret =%d\n", vector_id);
845 return vector_id;
846 }
847
848 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
849 }
850
851 static int hclgevf_unmap_ring_from_vector(
852 struct hnae3_handle *handle,
853 int vector,
854 struct hnae3_ring_chain_node *ring_chain)
855 {
856 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
857 int ret, vector_id;
858
859 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
860 return 0;
861
862 vector_id = hclgevf_get_vector_index(hdev, vector);
863 if (vector_id < 0) {
864 dev_err(&handle->pdev->dev,
865 "Get vector index fail. ret =%d\n", vector_id);
866 return vector_id;
867 }
868
869 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
870 if (ret)
871 dev_err(&handle->pdev->dev,
872 "Unmap ring from vector fail. vector=%d, ret =%d\n",
873 vector_id,
874 ret);
875
876 return ret;
877 }
878
879 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
880 {
881 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
882 int vector_id;
883
884 vector_id = hclgevf_get_vector_index(hdev, vector);
885 if (vector_id < 0) {
886 dev_err(&handle->pdev->dev,
887 "hclgevf_put_vector get vector index fail. ret =%d\n",
888 vector_id);
889 return vector_id;
890 }
891
892 hclgevf_free_vector(hdev, vector_id);
893
894 return 0;
895 }
896
897 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
898 bool en_uc_pmc, bool en_mc_pmc)
899 {
900 struct hclge_mbx_vf_to_pf_cmd *req;
901 struct hclgevf_desc desc;
902 int status;
903
904 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
905
906 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false);
907 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE;
908 req->msg[1] = en_uc_pmc ? 1 : 0;
909 req->msg[2] = en_mc_pmc ? 1 : 0;
910
911 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
912 if (status)
913 dev_err(&hdev->pdev->dev,
914 "Set promisc mode fail, status is %d.\n", status);
915
916 return status;
917 }
918
919 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle,
920 bool en_uc_pmc, bool en_mc_pmc)
921 {
922 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
923
924 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc);
925 }
926
927 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id,
928 int stream_id, bool enable)
929 {
930 struct hclgevf_cfg_com_tqp_queue_cmd *req;
931 struct hclgevf_desc desc;
932 int status;
933
934 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
935
936 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
937 false);
938 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
939 req->stream_id = cpu_to_le16(stream_id);
940 req->enable |= enable << HCLGEVF_TQP_ENABLE_B;
941
942 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
943 if (status)
944 dev_err(&hdev->pdev->dev,
945 "TQP enable fail, status =%d.\n", status);
946
947 return status;
948 }
949
950 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
951 {
952 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
953 struct hclgevf_tqp *tqp;
954 int i;
955
956 for (i = 0; i < kinfo->num_tqps; i++) {
957 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
958 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
959 }
960 }
961
962 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
963 {
964 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
965
966 ether_addr_copy(p, hdev->hw.mac.mac_addr);
967 }
968
969 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
970 bool is_first)
971 {
972 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
973 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
974 u8 *new_mac_addr = (u8 *)p;
975 u8 msg_data[ETH_ALEN * 2];
976 u16 subcode;
977 int status;
978
979 ether_addr_copy(msg_data, new_mac_addr);
980 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr);
981
982 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD :
983 HCLGE_MBX_MAC_VLAN_UC_MODIFY;
984
985 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
986 subcode, msg_data, ETH_ALEN * 2,
987 true, NULL, 0);
988 if (!status)
989 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
990
991 return status;
992 }
993
994 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
995 const unsigned char *addr)
996 {
997 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
998
999 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1000 HCLGE_MBX_MAC_VLAN_UC_ADD,
1001 addr, ETH_ALEN, false, NULL, 0);
1002 }
1003
1004 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1005 const unsigned char *addr)
1006 {
1007 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1008
1009 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1010 HCLGE_MBX_MAC_VLAN_UC_REMOVE,
1011 addr, ETH_ALEN, false, NULL, 0);
1012 }
1013
1014 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1015 const unsigned char *addr)
1016 {
1017 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1018
1019 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
1020 HCLGE_MBX_MAC_VLAN_MC_ADD,
1021 addr, ETH_ALEN, false, NULL, 0);
1022 }
1023
1024 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1025 const unsigned char *addr)
1026 {
1027 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1028
1029 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
1030 HCLGE_MBX_MAC_VLAN_MC_REMOVE,
1031 addr, ETH_ALEN, false, NULL, 0);
1032 }
1033
1034 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1035 __be16 proto, u16 vlan_id,
1036 bool is_kill)
1037 {
1038 #define HCLGEVF_VLAN_MBX_MSG_LEN 5
1039 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1040 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN];
1041
1042 if (vlan_id > 4095)
1043 return -EINVAL;
1044
1045 if (proto != htons(ETH_P_8021Q))
1046 return -EPROTONOSUPPORT;
1047
1048 msg_data[0] = is_kill;
1049 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1050 memcpy(&msg_data[3], &proto, sizeof(proto));
1051 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
1052 HCLGE_MBX_VLAN_FILTER, msg_data,
1053 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0);
1054 }
1055
1056 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1057 {
1058 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1059 u8 msg_data;
1060
1061 msg_data = enable ? 1 : 0;
1062 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
1063 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data,
1064 1, false, NULL, 0);
1065 }
1066
1067 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
1068 {
1069 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1070 u8 msg_data[2];
1071 int ret;
1072
1073 memcpy(&msg_data[0], &queue_id, sizeof(queue_id));
1074
1075 /* disable vf queue before send queue reset msg to PF */
1076 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
1077 if (ret)
1078 return ret;
1079
1080 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data,
1081 2, true, NULL, 0);
1082 }
1083
1084 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1085 {
1086 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1087
1088 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu,
1089 sizeof(new_mtu), true, NULL, 0);
1090 }
1091
1092 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1093 enum hnae3_reset_notify_type type)
1094 {
1095 struct hnae3_client *client = hdev->nic_client;
1096 struct hnae3_handle *handle = &hdev->nic;
1097 int ret;
1098
1099 if (!client->ops->reset_notify)
1100 return -EOPNOTSUPP;
1101
1102 ret = client->ops->reset_notify(handle, type);
1103 if (ret)
1104 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1105 type, ret);
1106
1107 return ret;
1108 }
1109
1110 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev)
1111 {
1112 struct hclgevf_dev *hdev = ae_dev->priv;
1113
1114 set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
1115 }
1116
1117 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev,
1118 unsigned long delay_us,
1119 unsigned long wait_cnt)
1120 {
1121 unsigned long cnt = 0;
1122
1123 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
1124 cnt++ < wait_cnt)
1125 usleep_range(delay_us, delay_us * 2);
1126
1127 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
1128 dev_err(&hdev->pdev->dev,
1129 "flr wait timeout\n");
1130 return -ETIMEDOUT;
1131 }
1132
1133 return 0;
1134 }
1135
1136 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1137 {
1138 #define HCLGEVF_RESET_WAIT_US 20000
1139 #define HCLGEVF_RESET_WAIT_CNT 2000
1140 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \
1141 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1142
1143 u32 val;
1144 int ret;
1145
1146 /* wait to check the hardware reset completion status */
1147 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
1148 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val);
1149
1150 if (hdev->reset_type == HNAE3_FLR_RESET)
1151 return hclgevf_flr_poll_timeout(hdev,
1152 HCLGEVF_RESET_WAIT_US,
1153 HCLGEVF_RESET_WAIT_CNT);
1154
1155 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val,
1156 !(val & HCLGEVF_RST_ING_BITS),
1157 HCLGEVF_RESET_WAIT_US,
1158 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1159
1160 /* hardware completion status should be available by this time */
1161 if (ret) {
1162 dev_err(&hdev->pdev->dev,
1163 "could'nt get reset done status from h/w, timeout!\n");
1164 return ret;
1165 }
1166
1167 /* we will wait a bit more to let reset of the stack to complete. This
1168 * might happen in case reset assertion was made by PF. Yes, this also
1169 * means we might end up waiting bit more even for VF reset.
1170 */
1171 msleep(5000);
1172
1173 return 0;
1174 }
1175
1176 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1177 {
1178 int ret;
1179
1180 /* uninitialize the nic client */
1181 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1182 if (ret)
1183 return ret;
1184
1185 /* re-initialize the hclge device */
1186 ret = hclgevf_reset_hdev(hdev);
1187 if (ret) {
1188 dev_err(&hdev->pdev->dev,
1189 "hclge device re-init failed, VF is disabled!\n");
1190 return ret;
1191 }
1192
1193 /* bring up the nic client again */
1194 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1195 if (ret)
1196 return ret;
1197
1198 return 0;
1199 }
1200
1201 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1202 {
1203 int ret = 0;
1204
1205 switch (hdev->reset_type) {
1206 case HNAE3_VF_FUNC_RESET:
1207 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL,
1208 0, true, NULL, sizeof(u8));
1209 break;
1210 case HNAE3_FLR_RESET:
1211 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
1212 break;
1213 default:
1214 break;
1215 }
1216
1217 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1218
1219 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n",
1220 hdev->reset_type, ret);
1221
1222 return ret;
1223 }
1224
1225 static int hclgevf_reset(struct hclgevf_dev *hdev)
1226 {
1227 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1228 int ret;
1229
1230 /* Initialize ae_dev reset status as well, in case enet layer wants to
1231 * know if device is undergoing reset
1232 */
1233 ae_dev->reset_type = hdev->reset_type;
1234 hdev->reset_count++;
1235 rtnl_lock();
1236
1237 /* bring down the nic to stop any ongoing TX/RX */
1238 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1239 if (ret)
1240 goto err_reset_lock;
1241
1242 rtnl_unlock();
1243
1244 ret = hclgevf_reset_prepare_wait(hdev);
1245 if (ret)
1246 goto err_reset;
1247
1248 /* check if VF could successfully fetch the hardware reset completion
1249 * status from the hardware
1250 */
1251 ret = hclgevf_reset_wait(hdev);
1252 if (ret) {
1253 /* can't do much in this situation, will disable VF */
1254 dev_err(&hdev->pdev->dev,
1255 "VF failed(=%d) to fetch H/W reset completion status\n",
1256 ret);
1257 goto err_reset;
1258 }
1259
1260 rtnl_lock();
1261
1262 /* now, re-initialize the nic client and ae device*/
1263 ret = hclgevf_reset_stack(hdev);
1264 if (ret) {
1265 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1266 goto err_reset_lock;
1267 }
1268
1269 /* bring up the nic to enable TX/RX again */
1270 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1271 if (ret)
1272 goto err_reset_lock;
1273
1274 rtnl_unlock();
1275
1276 return ret;
1277 err_reset_lock:
1278 rtnl_unlock();
1279 err_reset:
1280 /* When VF reset failed, only the higher level reset asserted by PF
1281 * can restore it, so re-initialize the command queue to receive
1282 * this higher reset event.
1283 */
1284 hclgevf_cmd_init(hdev);
1285 dev_err(&hdev->pdev->dev, "failed to reset VF\n");
1286
1287 return ret;
1288 }
1289
1290 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
1291 unsigned long *addr)
1292 {
1293 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
1294
1295 /* return the highest priority reset level amongst all */
1296 if (test_bit(HNAE3_VF_RESET, addr)) {
1297 rst_level = HNAE3_VF_RESET;
1298 clear_bit(HNAE3_VF_RESET, addr);
1299 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1300 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1301 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
1302 rst_level = HNAE3_VF_FULL_RESET;
1303 clear_bit(HNAE3_VF_FULL_RESET, addr);
1304 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1305 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
1306 rst_level = HNAE3_VF_PF_FUNC_RESET;
1307 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1308 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1309 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
1310 rst_level = HNAE3_VF_FUNC_RESET;
1311 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1312 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
1313 rst_level = HNAE3_FLR_RESET;
1314 clear_bit(HNAE3_FLR_RESET, addr);
1315 }
1316
1317 return rst_level;
1318 }
1319
1320 static void hclgevf_reset_event(struct pci_dev *pdev,
1321 struct hnae3_handle *handle)
1322 {
1323 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1324 struct hclgevf_dev *hdev = ae_dev->priv;
1325
1326 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1327
1328 if (hdev->default_reset_request)
1329 hdev->reset_level =
1330 hclgevf_get_reset_level(hdev,
1331 &hdev->default_reset_request);
1332 else
1333 hdev->reset_level = HNAE3_VF_FUNC_RESET;
1334
1335 /* reset of this VF requested */
1336 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1337 hclgevf_reset_task_schedule(hdev);
1338
1339 hdev->last_reset_time = jiffies;
1340 }
1341
1342 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
1343 enum hnae3_reset_type rst_type)
1344 {
1345 struct hclgevf_dev *hdev = ae_dev->priv;
1346
1347 set_bit(rst_type, &hdev->default_reset_request);
1348 }
1349
1350 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev)
1351 {
1352 #define HCLGEVF_FLR_WAIT_MS 100
1353 #define HCLGEVF_FLR_WAIT_CNT 50
1354 struct hclgevf_dev *hdev = ae_dev->priv;
1355 int cnt = 0;
1356
1357 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
1358 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
1359 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
1360 hclgevf_reset_event(hdev->pdev, NULL);
1361
1362 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
1363 cnt++ < HCLGEVF_FLR_WAIT_CNT)
1364 msleep(HCLGEVF_FLR_WAIT_MS);
1365
1366 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
1367 dev_err(&hdev->pdev->dev,
1368 "flr wait down timeout: %d\n", cnt);
1369 }
1370
1371 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1372 {
1373 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1374
1375 return hdev->fw_version;
1376 }
1377
1378 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1379 {
1380 struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1381
1382 vector->vector_irq = pci_irq_vector(hdev->pdev,
1383 HCLGEVF_MISC_VECTOR_NUM);
1384 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1385 /* vector status always valid for Vector 0 */
1386 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1387 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1388
1389 hdev->num_msi_left -= 1;
1390 hdev->num_msi_used += 1;
1391 }
1392
1393 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1394 {
1395 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) &&
1396 !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) {
1397 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1398 schedule_work(&hdev->rst_service_task);
1399 }
1400 }
1401
1402 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
1403 {
1404 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) &&
1405 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) {
1406 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1407 schedule_work(&hdev->mbx_service_task);
1408 }
1409 }
1410
1411 static void hclgevf_task_schedule(struct hclgevf_dev *hdev)
1412 {
1413 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) &&
1414 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state))
1415 schedule_work(&hdev->service_task);
1416 }
1417
1418 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev)
1419 {
1420 /* if we have any pending mailbox event then schedule the mbx task */
1421 if (hdev->mbx_event_pending)
1422 hclgevf_mbx_task_schedule(hdev);
1423
1424 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state))
1425 hclgevf_reset_task_schedule(hdev);
1426 }
1427
1428 static void hclgevf_service_timer(struct timer_list *t)
1429 {
1430 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer);
1431
1432 mod_timer(&hdev->service_timer, jiffies + 5 * HZ);
1433
1434 hclgevf_task_schedule(hdev);
1435 }
1436
1437 static void hclgevf_reset_service_task(struct work_struct *work)
1438 {
1439 struct hclgevf_dev *hdev =
1440 container_of(work, struct hclgevf_dev, rst_service_task);
1441 int ret;
1442
1443 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1444 return;
1445
1446 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1447
1448 if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1449 &hdev->reset_state)) {
1450 /* PF has initmated that it is about to reset the hardware.
1451 * We now have to poll & check if harware has actually completed
1452 * the reset sequence. On hardware reset completion, VF needs to
1453 * reset the client and ae device.
1454 */
1455 hdev->reset_attempts = 0;
1456
1457 hdev->last_reset_time = jiffies;
1458 while ((hdev->reset_type =
1459 hclgevf_get_reset_level(hdev, &hdev->reset_pending))
1460 != HNAE3_NONE_RESET) {
1461 ret = hclgevf_reset(hdev);
1462 if (ret)
1463 dev_err(&hdev->pdev->dev,
1464 "VF stack reset failed %d.\n", ret);
1465 }
1466 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1467 &hdev->reset_state)) {
1468 /* we could be here when either of below happens:
1469 * 1. reset was initiated due to watchdog timeout due to
1470 * a. IMP was earlier reset and our TX got choked down and
1471 * which resulted in watchdog reacting and inducing VF
1472 * reset. This also means our cmdq would be unreliable.
1473 * b. problem in TX due to other lower layer(example link
1474 * layer not functioning properly etc.)
1475 * 2. VF reset might have been initiated due to some config
1476 * change.
1477 *
1478 * NOTE: Theres no clear way to detect above cases than to react
1479 * to the response of PF for this reset request. PF will ack the
1480 * 1b and 2. cases but we will not get any intimation about 1a
1481 * from PF as cmdq would be in unreliable state i.e. mailbox
1482 * communication between PF and VF would be broken.
1483 */
1484
1485 /* if we are never geting into pending state it means either:
1486 * 1. PF is not receiving our request which could be due to IMP
1487 * reset
1488 * 2. PF is screwed
1489 * We cannot do much for 2. but to check first we can try reset
1490 * our PCIe + stack and see if it alleviates the problem.
1491 */
1492 if (hdev->reset_attempts > 3) {
1493 /* prepare for full reset of stack + pcie interface */
1494 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
1495
1496 /* "defer" schedule the reset task again */
1497 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1498 } else {
1499 hdev->reset_attempts++;
1500
1501 set_bit(hdev->reset_level, &hdev->reset_pending);
1502 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1503 }
1504 hclgevf_reset_task_schedule(hdev);
1505 }
1506
1507 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1508 }
1509
1510 static void hclgevf_mailbox_service_task(struct work_struct *work)
1511 {
1512 struct hclgevf_dev *hdev;
1513
1514 hdev = container_of(work, struct hclgevf_dev, mbx_service_task);
1515
1516 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1517 return;
1518
1519 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1520
1521 hclgevf_mbx_async_handler(hdev);
1522
1523 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1524 }
1525
1526 static void hclgevf_keep_alive_timer(struct timer_list *t)
1527 {
1528 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer);
1529
1530 schedule_work(&hdev->keep_alive_task);
1531 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ);
1532 }
1533
1534 static void hclgevf_keep_alive_task(struct work_struct *work)
1535 {
1536 struct hclgevf_dev *hdev;
1537 u8 respmsg;
1538 int ret;
1539
1540 hdev = container_of(work, struct hclgevf_dev, keep_alive_task);
1541 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL,
1542 0, false, &respmsg, sizeof(u8));
1543 if (ret)
1544 dev_err(&hdev->pdev->dev,
1545 "VF sends keep alive cmd failed(=%d)\n", ret);
1546 }
1547
1548 static void hclgevf_service_task(struct work_struct *work)
1549 {
1550 struct hclgevf_dev *hdev;
1551
1552 hdev = container_of(work, struct hclgevf_dev, service_task);
1553
1554 /* request the link status from the PF. PF would be able to tell VF
1555 * about such updates in future so we might remove this later
1556 */
1557 hclgevf_request_link_info(hdev);
1558
1559 hclgevf_deferred_task_schedule(hdev);
1560
1561 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1562 }
1563
1564 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1565 {
1566 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
1567 }
1568
1569 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
1570 u32 *clearval)
1571 {
1572 u32 cmdq_src_reg, rst_ing_reg;
1573
1574 /* fetch the events from their corresponding regs */
1575 cmdq_src_reg = hclgevf_read_dev(&hdev->hw,
1576 HCLGEVF_VECTOR0_CMDQ_SRC_REG);
1577
1578 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) {
1579 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
1580 dev_info(&hdev->pdev->dev,
1581 "receive reset interrupt 0x%x!\n", rst_ing_reg);
1582 set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
1583 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1584 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1585 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B);
1586 *clearval = cmdq_src_reg;
1587 return HCLGEVF_VECTOR0_EVENT_RST;
1588 }
1589
1590 /* check for vector0 mailbox(=CMDQ RX) event source */
1591 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
1592 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1593 *clearval = cmdq_src_reg;
1594 return HCLGEVF_VECTOR0_EVENT_MBX;
1595 }
1596
1597 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n");
1598
1599 return HCLGEVF_VECTOR0_EVENT_OTHER;
1600 }
1601
1602 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1603 {
1604 writel(en ? 1 : 0, vector->addr);
1605 }
1606
1607 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
1608 {
1609 enum hclgevf_evt_cause event_cause;
1610 struct hclgevf_dev *hdev = data;
1611 u32 clearval;
1612
1613 hclgevf_enable_vector(&hdev->misc_vector, false);
1614 event_cause = hclgevf_check_evt_cause(hdev, &clearval);
1615
1616 switch (event_cause) {
1617 case HCLGEVF_VECTOR0_EVENT_RST:
1618 hclgevf_reset_task_schedule(hdev);
1619 break;
1620 case HCLGEVF_VECTOR0_EVENT_MBX:
1621 hclgevf_mbx_handler(hdev);
1622 break;
1623 default:
1624 break;
1625 }
1626
1627 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) {
1628 hclgevf_clear_event_cause(hdev, clearval);
1629 hclgevf_enable_vector(&hdev->misc_vector, true);
1630 }
1631
1632 return IRQ_HANDLED;
1633 }
1634
1635 static int hclgevf_configure(struct hclgevf_dev *hdev)
1636 {
1637 int ret;
1638
1639 hdev->hw.mac.media_type = HNAE3_MEDIA_TYPE_NONE;
1640
1641 /* get queue configuration from PF */
1642 ret = hclgevf_get_queue_info(hdev);
1643 if (ret)
1644 return ret;
1645 /* get tc configuration from PF */
1646 return hclgevf_get_tc_info(hdev);
1647 }
1648
1649 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
1650 {
1651 struct pci_dev *pdev = ae_dev->pdev;
1652 struct hclgevf_dev *hdev = ae_dev->priv;
1653
1654 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
1655 if (!hdev)
1656 return -ENOMEM;
1657
1658 hdev->pdev = pdev;
1659 hdev->ae_dev = ae_dev;
1660 ae_dev->priv = hdev;
1661
1662 return 0;
1663 }
1664
1665 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
1666 {
1667 struct hnae3_handle *roce = &hdev->roce;
1668 struct hnae3_handle *nic = &hdev->nic;
1669
1670 roce->rinfo.num_vectors = hdev->num_roce_msix;
1671
1672 if (hdev->num_msi_left < roce->rinfo.num_vectors ||
1673 hdev->num_msi_left == 0)
1674 return -EINVAL;
1675
1676 roce->rinfo.base_vector = hdev->roce_base_vector;
1677
1678 roce->rinfo.netdev = nic->kinfo.netdev;
1679 roce->rinfo.roce_io_base = hdev->hw.io_base;
1680
1681 roce->pdev = nic->pdev;
1682 roce->ae_algo = nic->ae_algo;
1683 roce->numa_node_mask = nic->numa_node_mask;
1684
1685 return 0;
1686 }
1687
1688 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
1689 {
1690 struct hclgevf_cfg_gro_status_cmd *req;
1691 struct hclgevf_desc desc;
1692 int ret;
1693
1694 if (!hnae3_dev_gro_supported(hdev))
1695 return 0;
1696
1697 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
1698 false);
1699 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
1700
1701 req->gro_en = cpu_to_le16(en ? 1 : 0);
1702
1703 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1704 if (ret)
1705 dev_err(&hdev->pdev->dev,
1706 "VF GRO hardware config cmd failed, ret = %d.\n", ret);
1707
1708 return ret;
1709 }
1710
1711 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
1712 {
1713 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1714 int i, ret;
1715
1716 rss_cfg->rss_size = hdev->rss_size_max;
1717
1718 if (hdev->pdev->revision >= 0x21) {
1719 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
1720 netdev_rss_key_fill(rss_cfg->rss_hash_key,
1721 HCLGEVF_RSS_KEY_SIZE);
1722
1723 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
1724 rss_cfg->rss_hash_key);
1725 if (ret)
1726 return ret;
1727
1728 rss_cfg->rss_tuple_sets.ipv4_tcp_en =
1729 HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1730 rss_cfg->rss_tuple_sets.ipv4_udp_en =
1731 HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1732 rss_cfg->rss_tuple_sets.ipv4_sctp_en =
1733 HCLGEVF_RSS_INPUT_TUPLE_SCTP;
1734 rss_cfg->rss_tuple_sets.ipv4_fragment_en =
1735 HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1736 rss_cfg->rss_tuple_sets.ipv6_tcp_en =
1737 HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1738 rss_cfg->rss_tuple_sets.ipv6_udp_en =
1739 HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1740 rss_cfg->rss_tuple_sets.ipv6_sctp_en =
1741 HCLGEVF_RSS_INPUT_TUPLE_SCTP;
1742 rss_cfg->rss_tuple_sets.ipv6_fragment_en =
1743 HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1744
1745 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
1746 if (ret)
1747 return ret;
1748
1749 }
1750
1751 /* Initialize RSS indirect table for each vport */
1752 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
1753 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max;
1754
1755 ret = hclgevf_set_rss_indir_table(hdev);
1756 if (ret)
1757 return ret;
1758
1759 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max);
1760 }
1761
1762 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
1763 {
1764 /* other vlan config(like, VLAN TX/RX offload) would also be added
1765 * here later
1766 */
1767 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
1768 false);
1769 }
1770
1771 static int hclgevf_ae_start(struct hnae3_handle *handle)
1772 {
1773 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1774
1775 /* reset tqp stats */
1776 hclgevf_reset_tqp_stats(handle);
1777
1778 hclgevf_request_link_info(hdev);
1779
1780 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1781 mod_timer(&hdev->service_timer, jiffies + HZ);
1782
1783 return 0;
1784 }
1785
1786 static void hclgevf_ae_stop(struct hnae3_handle *handle)
1787 {
1788 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1789
1790 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1791
1792 /* reset tqp stats */
1793 hclgevf_reset_tqp_stats(handle);
1794 del_timer_sync(&hdev->service_timer);
1795 cancel_work_sync(&hdev->service_task);
1796 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1797 hclgevf_update_link_status(hdev, 0);
1798 }
1799
1800 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
1801 {
1802 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1803 u8 msg_data;
1804
1805 msg_data = alive ? 1 : 0;
1806 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE,
1807 0, &msg_data, 1, false, NULL, 0);
1808 }
1809
1810 static int hclgevf_client_start(struct hnae3_handle *handle)
1811 {
1812 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1813
1814 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ);
1815 return hclgevf_set_alive(handle, true);
1816 }
1817
1818 static void hclgevf_client_stop(struct hnae3_handle *handle)
1819 {
1820 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1821 int ret;
1822
1823 ret = hclgevf_set_alive(handle, false);
1824 if (ret)
1825 dev_warn(&hdev->pdev->dev,
1826 "%s failed %d\n", __func__, ret);
1827
1828 del_timer_sync(&hdev->keep_alive_timer);
1829 cancel_work_sync(&hdev->keep_alive_task);
1830 }
1831
1832 static void hclgevf_state_init(struct hclgevf_dev *hdev)
1833 {
1834 /* setup tasks for the MBX */
1835 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task);
1836 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1837 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1838
1839 /* setup tasks for service timer */
1840 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0);
1841
1842 INIT_WORK(&hdev->service_task, hclgevf_service_task);
1843 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1844
1845 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task);
1846
1847 mutex_init(&hdev->mbx_resp.mbx_mutex);
1848
1849 /* bring the device down */
1850 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1851 }
1852
1853 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
1854 {
1855 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1856
1857 if (hdev->service_timer.function)
1858 del_timer_sync(&hdev->service_timer);
1859 if (hdev->service_task.func)
1860 cancel_work_sync(&hdev->service_task);
1861 if (hdev->mbx_service_task.func)
1862 cancel_work_sync(&hdev->mbx_service_task);
1863 if (hdev->rst_service_task.func)
1864 cancel_work_sync(&hdev->rst_service_task);
1865
1866 mutex_destroy(&hdev->mbx_resp.mbx_mutex);
1867 }
1868
1869 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
1870 {
1871 struct pci_dev *pdev = hdev->pdev;
1872 int vectors;
1873 int i;
1874
1875 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B))
1876 vectors = pci_alloc_irq_vectors(pdev,
1877 hdev->roce_base_msix_offset + 1,
1878 hdev->num_msi,
1879 PCI_IRQ_MSIX);
1880 else
1881 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1882 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1883
1884 if (vectors < 0) {
1885 dev_err(&pdev->dev,
1886 "failed(%d) to allocate MSI/MSI-X vectors\n",
1887 vectors);
1888 return vectors;
1889 }
1890 if (vectors < hdev->num_msi)
1891 dev_warn(&hdev->pdev->dev,
1892 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1893 hdev->num_msi, vectors);
1894
1895 hdev->num_msi = vectors;
1896 hdev->num_msi_left = vectors;
1897 hdev->base_msi_vector = pdev->irq;
1898 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
1899
1900 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1901 sizeof(u16), GFP_KERNEL);
1902 if (!hdev->vector_status) {
1903 pci_free_irq_vectors(pdev);
1904 return -ENOMEM;
1905 }
1906
1907 for (i = 0; i < hdev->num_msi; i++)
1908 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
1909
1910 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1911 sizeof(int), GFP_KERNEL);
1912 if (!hdev->vector_irq) {
1913 devm_kfree(&pdev->dev, hdev->vector_status);
1914 pci_free_irq_vectors(pdev);
1915 return -ENOMEM;
1916 }
1917
1918 return 0;
1919 }
1920
1921 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
1922 {
1923 struct pci_dev *pdev = hdev->pdev;
1924
1925 devm_kfree(&pdev->dev, hdev->vector_status);
1926 devm_kfree(&pdev->dev, hdev->vector_irq);
1927 pci_free_irq_vectors(pdev);
1928 }
1929
1930 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
1931 {
1932 int ret = 0;
1933
1934 hclgevf_get_misc_vector(hdev);
1935
1936 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
1937 0, "hclgevf_cmd", hdev);
1938 if (ret) {
1939 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
1940 hdev->misc_vector.vector_irq);
1941 return ret;
1942 }
1943
1944 hclgevf_clear_event_cause(hdev, 0);
1945
1946 /* enable misc. vector(vector 0) */
1947 hclgevf_enable_vector(&hdev->misc_vector, true);
1948
1949 return ret;
1950 }
1951
1952 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
1953 {
1954 /* disable misc vector(vector 0) */
1955 hclgevf_enable_vector(&hdev->misc_vector, false);
1956 synchronize_irq(hdev->misc_vector.vector_irq);
1957 free_irq(hdev->misc_vector.vector_irq, hdev);
1958 hclgevf_free_vector(hdev, 0);
1959 }
1960
1961 static int hclgevf_init_client_instance(struct hnae3_client *client,
1962 struct hnae3_ae_dev *ae_dev)
1963 {
1964 struct hclgevf_dev *hdev = ae_dev->priv;
1965 int ret;
1966
1967 switch (client->type) {
1968 case HNAE3_CLIENT_KNIC:
1969 hdev->nic_client = client;
1970 hdev->nic.client = client;
1971
1972 ret = client->ops->init_instance(&hdev->nic);
1973 if (ret)
1974 goto clear_nic;
1975
1976 hnae3_set_client_init_flag(client, ae_dev, 1);
1977
1978 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) {
1979 struct hnae3_client *rc = hdev->roce_client;
1980
1981 ret = hclgevf_init_roce_base_info(hdev);
1982 if (ret)
1983 goto clear_roce;
1984 ret = rc->ops->init_instance(&hdev->roce);
1985 if (ret)
1986 goto clear_roce;
1987
1988 hnae3_set_client_init_flag(hdev->roce_client, ae_dev,
1989 1);
1990 }
1991 break;
1992 case HNAE3_CLIENT_UNIC:
1993 hdev->nic_client = client;
1994 hdev->nic.client = client;
1995
1996 ret = client->ops->init_instance(&hdev->nic);
1997 if (ret)
1998 goto clear_nic;
1999
2000 hnae3_set_client_init_flag(client, ae_dev, 1);
2001 break;
2002 case HNAE3_CLIENT_ROCE:
2003 if (hnae3_dev_roce_supported(hdev)) {
2004 hdev->roce_client = client;
2005 hdev->roce.client = client;
2006 }
2007
2008 if (hdev->roce_client && hdev->nic_client) {
2009 ret = hclgevf_init_roce_base_info(hdev);
2010 if (ret)
2011 goto clear_roce;
2012
2013 ret = client->ops->init_instance(&hdev->roce);
2014 if (ret)
2015 goto clear_roce;
2016 }
2017
2018 hnae3_set_client_init_flag(client, ae_dev, 1);
2019 break;
2020 default:
2021 return -EINVAL;
2022 }
2023
2024 return 0;
2025
2026 clear_nic:
2027 hdev->nic_client = NULL;
2028 hdev->nic.client = NULL;
2029 return ret;
2030 clear_roce:
2031 hdev->roce_client = NULL;
2032 hdev->roce.client = NULL;
2033 return ret;
2034 }
2035
2036 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2037 struct hnae3_ae_dev *ae_dev)
2038 {
2039 struct hclgevf_dev *hdev = ae_dev->priv;
2040
2041 /* un-init roce, if it exists */
2042 if (hdev->roce_client) {
2043 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
2044 hdev->roce_client = NULL;
2045 hdev->roce.client = NULL;
2046 }
2047
2048 /* un-init nic/unic, if this was not called by roce client */
2049 if (client->ops->uninit_instance && hdev->nic_client &&
2050 client->type != HNAE3_CLIENT_ROCE) {
2051 client->ops->uninit_instance(&hdev->nic, 0);
2052 hdev->nic_client = NULL;
2053 hdev->nic.client = NULL;
2054 }
2055 }
2056
2057 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
2058 {
2059 struct pci_dev *pdev = hdev->pdev;
2060 struct hclgevf_hw *hw;
2061 int ret;
2062
2063 ret = pci_enable_device(pdev);
2064 if (ret) {
2065 dev_err(&pdev->dev, "failed to enable PCI device\n");
2066 return ret;
2067 }
2068
2069 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2070 if (ret) {
2071 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
2072 goto err_disable_device;
2073 }
2074
2075 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
2076 if (ret) {
2077 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
2078 goto err_disable_device;
2079 }
2080
2081 pci_set_master(pdev);
2082 hw = &hdev->hw;
2083 hw->hdev = hdev;
2084 hw->io_base = pci_iomap(pdev, 2, 0);
2085 if (!hw->io_base) {
2086 dev_err(&pdev->dev, "can't map configuration register space\n");
2087 ret = -ENOMEM;
2088 goto err_clr_master;
2089 }
2090
2091 return 0;
2092
2093 err_clr_master:
2094 pci_clear_master(pdev);
2095 pci_release_regions(pdev);
2096 err_disable_device:
2097 pci_disable_device(pdev);
2098
2099 return ret;
2100 }
2101
2102 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
2103 {
2104 struct pci_dev *pdev = hdev->pdev;
2105
2106 pci_iounmap(pdev, hdev->hw.io_base);
2107 pci_clear_master(pdev);
2108 pci_release_regions(pdev);
2109 pci_disable_device(pdev);
2110 }
2111
2112 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
2113 {
2114 struct hclgevf_query_res_cmd *req;
2115 struct hclgevf_desc desc;
2116 int ret;
2117
2118 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
2119 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2120 if (ret) {
2121 dev_err(&hdev->pdev->dev,
2122 "query vf resource failed, ret = %d.\n", ret);
2123 return ret;
2124 }
2125
2126 req = (struct hclgevf_query_res_cmd *)desc.data;
2127
2128 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) {
2129 hdev->roce_base_msix_offset =
2130 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
2131 HCLGEVF_MSIX_OFT_ROCEE_M,
2132 HCLGEVF_MSIX_OFT_ROCEE_S);
2133 hdev->num_roce_msix =
2134 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
2135 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2136
2137 /* VF should have NIC vectors and Roce vectors, NIC vectors
2138 * are queued before Roce vectors. The offset is fixed to 64.
2139 */
2140 hdev->num_msi = hdev->num_roce_msix +
2141 hdev->roce_base_msix_offset;
2142 } else {
2143 hdev->num_msi =
2144 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
2145 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2146 }
2147
2148 return 0;
2149 }
2150
2151 static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
2152 {
2153 struct pci_dev *pdev = hdev->pdev;
2154 int ret = 0;
2155
2156 if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
2157 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2158 hclgevf_misc_irq_uninit(hdev);
2159 hclgevf_uninit_msi(hdev);
2160 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2161 }
2162
2163 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2164 pci_set_master(pdev);
2165 ret = hclgevf_init_msi(hdev);
2166 if (ret) {
2167 dev_err(&pdev->dev,
2168 "failed(%d) to init MSI/MSI-X\n", ret);
2169 return ret;
2170 }
2171
2172 ret = hclgevf_misc_irq_init(hdev);
2173 if (ret) {
2174 hclgevf_uninit_msi(hdev);
2175 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
2176 ret);
2177 return ret;
2178 }
2179
2180 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2181 }
2182
2183 return ret;
2184 }
2185
2186 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
2187 {
2188 struct pci_dev *pdev = hdev->pdev;
2189 int ret;
2190
2191 ret = hclgevf_pci_reset(hdev);
2192 if (ret) {
2193 dev_err(&pdev->dev, "pci reset failed %d\n", ret);
2194 return ret;
2195 }
2196
2197 ret = hclgevf_cmd_init(hdev);
2198 if (ret) {
2199 dev_err(&pdev->dev, "cmd failed %d\n", ret);
2200 return ret;
2201 }
2202
2203 ret = hclgevf_rss_init_hw(hdev);
2204 if (ret) {
2205 dev_err(&hdev->pdev->dev,
2206 "failed(%d) to initialize RSS\n", ret);
2207 return ret;
2208 }
2209
2210 ret = hclgevf_config_gro(hdev, true);
2211 if (ret)
2212 return ret;
2213
2214 ret = hclgevf_init_vlan_config(hdev);
2215 if (ret) {
2216 dev_err(&hdev->pdev->dev,
2217 "failed(%d) to initialize VLAN config\n", ret);
2218 return ret;
2219 }
2220
2221 dev_info(&hdev->pdev->dev, "Reset done\n");
2222
2223 return 0;
2224 }
2225
2226 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
2227 {
2228 struct pci_dev *pdev = hdev->pdev;
2229 int ret;
2230
2231 ret = hclgevf_pci_init(hdev);
2232 if (ret) {
2233 dev_err(&pdev->dev, "PCI initialization failed\n");
2234 return ret;
2235 }
2236
2237 ret = hclgevf_cmd_queue_init(hdev);
2238 if (ret) {
2239 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret);
2240 goto err_cmd_queue_init;
2241 }
2242
2243 ret = hclgevf_cmd_init(hdev);
2244 if (ret)
2245 goto err_cmd_init;
2246
2247 /* Get vf resource */
2248 ret = hclgevf_query_vf_resource(hdev);
2249 if (ret) {
2250 dev_err(&hdev->pdev->dev,
2251 "Query vf status error, ret = %d.\n", ret);
2252 goto err_cmd_init;
2253 }
2254
2255 ret = hclgevf_init_msi(hdev);
2256 if (ret) {
2257 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
2258 goto err_cmd_init;
2259 }
2260
2261 hclgevf_state_init(hdev);
2262 hdev->reset_level = HNAE3_VF_FUNC_RESET;
2263
2264 ret = hclgevf_misc_irq_init(hdev);
2265 if (ret) {
2266 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
2267 ret);
2268 goto err_misc_irq_init;
2269 }
2270
2271 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2272
2273 ret = hclgevf_configure(hdev);
2274 if (ret) {
2275 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
2276 goto err_config;
2277 }
2278
2279 ret = hclgevf_alloc_tqps(hdev);
2280 if (ret) {
2281 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
2282 goto err_config;
2283 }
2284
2285 ret = hclgevf_set_handle_info(hdev);
2286 if (ret) {
2287 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret);
2288 goto err_config;
2289 }
2290
2291 ret = hclgevf_config_gro(hdev, true);
2292 if (ret)
2293 goto err_config;
2294
2295 /* Initialize RSS for this VF */
2296 ret = hclgevf_rss_init_hw(hdev);
2297 if (ret) {
2298 dev_err(&hdev->pdev->dev,
2299 "failed(%d) to initialize RSS\n", ret);
2300 goto err_config;
2301 }
2302
2303 ret = hclgevf_init_vlan_config(hdev);
2304 if (ret) {
2305 dev_err(&hdev->pdev->dev,
2306 "failed(%d) to initialize VLAN config\n", ret);
2307 goto err_config;
2308 }
2309
2310 hdev->last_reset_time = jiffies;
2311 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME);
2312
2313 return 0;
2314
2315 err_config:
2316 hclgevf_misc_irq_uninit(hdev);
2317 err_misc_irq_init:
2318 hclgevf_state_uninit(hdev);
2319 hclgevf_uninit_msi(hdev);
2320 err_cmd_init:
2321 hclgevf_cmd_uninit(hdev);
2322 err_cmd_queue_init:
2323 hclgevf_pci_uninit(hdev);
2324 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2325 return ret;
2326 }
2327
2328 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
2329 {
2330 hclgevf_state_uninit(hdev);
2331
2332 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2333 hclgevf_misc_irq_uninit(hdev);
2334 hclgevf_uninit_msi(hdev);
2335 hclgevf_pci_uninit(hdev);
2336 }
2337
2338 hclgevf_cmd_uninit(hdev);
2339 }
2340
2341 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
2342 {
2343 struct pci_dev *pdev = ae_dev->pdev;
2344 struct hclgevf_dev *hdev;
2345 int ret;
2346
2347 ret = hclgevf_alloc_hdev(ae_dev);
2348 if (ret) {
2349 dev_err(&pdev->dev, "hclge device allocation failed\n");
2350 return ret;
2351 }
2352
2353 ret = hclgevf_init_hdev(ae_dev->priv);
2354 if (ret) {
2355 dev_err(&pdev->dev, "hclge device initialization failed\n");
2356 return ret;
2357 }
2358
2359 hdev = ae_dev->priv;
2360 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0);
2361 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task);
2362
2363 return 0;
2364 }
2365
2366 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
2367 {
2368 struct hclgevf_dev *hdev = ae_dev->priv;
2369
2370 hclgevf_uninit_hdev(hdev);
2371 ae_dev->priv = NULL;
2372 }
2373
2374 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
2375 {
2376 struct hnae3_handle *nic = &hdev->nic;
2377 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
2378
2379 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
2380 }
2381
2382 /**
2383 * hclgevf_get_channels - Get the current channels enabled and max supported.
2384 * @handle: hardware information for network interface
2385 * @ch: ethtool channels structure
2386 *
2387 * We don't support separate tx and rx queues as channels. The other count
2388 * represents how many queues are being used for control. max_combined counts
2389 * how many queue pairs we can support. They may not be mapped 1 to 1 with
2390 * q_vectors since we support a lot more queue pairs than q_vectors.
2391 **/
2392 static void hclgevf_get_channels(struct hnae3_handle *handle,
2393 struct ethtool_channels *ch)
2394 {
2395 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2396
2397 ch->max_combined = hclgevf_get_max_channels(hdev);
2398 ch->other_count = 0;
2399 ch->max_other = 0;
2400 ch->combined_count = hdev->num_tqps;
2401 }
2402
2403 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
2404 u16 *alloc_tqps, u16 *max_rss_size)
2405 {
2406 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2407
2408 *alloc_tqps = hdev->num_tqps;
2409 *max_rss_size = hdev->rss_size_max;
2410 }
2411
2412 static int hclgevf_get_status(struct hnae3_handle *handle)
2413 {
2414 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2415
2416 return hdev->hw.mac.link;
2417 }
2418
2419 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
2420 u8 *auto_neg, u32 *speed,
2421 u8 *duplex)
2422 {
2423 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2424
2425 if (speed)
2426 *speed = hdev->hw.mac.speed;
2427 if (duplex)
2428 *duplex = hdev->hw.mac.duplex;
2429 if (auto_neg)
2430 *auto_neg = AUTONEG_DISABLE;
2431 }
2432
2433 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
2434 u8 duplex)
2435 {
2436 hdev->hw.mac.speed = speed;
2437 hdev->hw.mac.duplex = duplex;
2438 }
2439
2440 static void hclgevf_get_media_type(struct hnae3_handle *handle,
2441 u8 *media_type)
2442 {
2443 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2444 if (media_type)
2445 *media_type = hdev->hw.mac.media_type;
2446 }
2447
2448 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
2449 {
2450 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2451
2452 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
2453 }
2454
2455 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
2456 {
2457 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2458
2459 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2460 }
2461
2462 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
2463 {
2464 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2465
2466 return hdev->reset_count;
2467 }
2468
2469 static const struct hnae3_ae_ops hclgevf_ops = {
2470 .init_ae_dev = hclgevf_init_ae_dev,
2471 .uninit_ae_dev = hclgevf_uninit_ae_dev,
2472 .flr_prepare = hclgevf_flr_prepare,
2473 .flr_done = hclgevf_flr_done,
2474 .init_client_instance = hclgevf_init_client_instance,
2475 .uninit_client_instance = hclgevf_uninit_client_instance,
2476 .start = hclgevf_ae_start,
2477 .stop = hclgevf_ae_stop,
2478 .client_start = hclgevf_client_start,
2479 .client_stop = hclgevf_client_stop,
2480 .map_ring_to_vector = hclgevf_map_ring_to_vector,
2481 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
2482 .get_vector = hclgevf_get_vector,
2483 .put_vector = hclgevf_put_vector,
2484 .reset_queue = hclgevf_reset_tqp,
2485 .set_promisc_mode = hclgevf_set_promisc_mode,
2486 .get_mac_addr = hclgevf_get_mac_addr,
2487 .set_mac_addr = hclgevf_set_mac_addr,
2488 .add_uc_addr = hclgevf_add_uc_addr,
2489 .rm_uc_addr = hclgevf_rm_uc_addr,
2490 .add_mc_addr = hclgevf_add_mc_addr,
2491 .rm_mc_addr = hclgevf_rm_mc_addr,
2492 .get_stats = hclgevf_get_stats,
2493 .update_stats = hclgevf_update_stats,
2494 .get_strings = hclgevf_get_strings,
2495 .get_sset_count = hclgevf_get_sset_count,
2496 .get_rss_key_size = hclgevf_get_rss_key_size,
2497 .get_rss_indir_size = hclgevf_get_rss_indir_size,
2498 .get_rss = hclgevf_get_rss,
2499 .set_rss = hclgevf_set_rss,
2500 .get_rss_tuple = hclgevf_get_rss_tuple,
2501 .set_rss_tuple = hclgevf_set_rss_tuple,
2502 .get_tc_size = hclgevf_get_tc_size,
2503 .get_fw_version = hclgevf_get_fw_version,
2504 .set_vlan_filter = hclgevf_set_vlan_filter,
2505 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
2506 .reset_event = hclgevf_reset_event,
2507 .set_default_reset_request = hclgevf_set_def_reset_request,
2508 .get_channels = hclgevf_get_channels,
2509 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
2510 .get_status = hclgevf_get_status,
2511 .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
2512 .get_media_type = hclgevf_get_media_type,
2513 .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
2514 .ae_dev_resetting = hclgevf_ae_dev_resetting,
2515 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
2516 .set_mtu = hclgevf_set_mtu,
2517 };
2518
2519 static struct hnae3_ae_algo ae_algovf = {
2520 .ops = &hclgevf_ops,
2521 .pdev_id_table = ae_algovf_pci_tbl,
2522 };
2523
2524 static int hclgevf_init(void)
2525 {
2526 pr_info("%s is initializing\n", HCLGEVF_NAME);
2527
2528 hnae3_register_ae_algo(&ae_algovf);
2529
2530 return 0;
2531 }
2532
2533 static void hclgevf_exit(void)
2534 {
2535 hnae3_unregister_ae_algo(&ae_algovf);
2536 }
2537 module_init(hclgevf_init);
2538 module_exit(hclgevf_exit);
2539
2540 MODULE_LICENSE("GPL");
2541 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2542 MODULE_DESCRIPTION("HCLGEVF Driver");
2543 MODULE_VERSION(HCLGEVF_MOD_VERSION);
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