1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/etherdevice.h>
5 #include <net/rtnetlink.h>
6 #include "hclgevf_cmd.h"
7 #include "hclgevf_main.h"
11 #define HCLGEVF_NAME "hclgevf"
13 static int hclgevf_init_hdev(struct hclgevf_dev
*hdev
);
14 static void hclgevf_uninit_hdev(struct hclgevf_dev
*hdev
);
15 static struct hnae3_ae_algo ae_algovf
;
17 static const struct pci_device_id ae_algovf_pci_tbl
[] = {
18 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_VF
), 0},
19 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF
), 0},
20 /* required last entry */
24 MODULE_DEVICE_TABLE(pci
, ae_algovf_pci_tbl
);
26 static inline struct hclgevf_dev
*hclgevf_ae_get_hdev(
27 struct hnae3_handle
*handle
)
29 return container_of(handle
, struct hclgevf_dev
, nic
);
32 static int hclgevf_tqps_update_stats(struct hnae3_handle
*handle
)
34 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
35 struct hnae3_queue
*queue
;
36 struct hclgevf_desc desc
;
37 struct hclgevf_tqp
*tqp
;
41 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
42 queue
= handle
->kinfo
.tqp
[i
];
43 tqp
= container_of(queue
, struct hclgevf_tqp
, q
);
44 hclgevf_cmd_setup_basic_desc(&desc
,
45 HCLGEVF_OPC_QUERY_RX_STATUS
,
48 desc
.data
[0] = cpu_to_le32(tqp
->index
& 0x1ff);
49 status
= hclgevf_cmd_send(&hdev
->hw
, &desc
, 1);
51 dev_err(&hdev
->pdev
->dev
,
52 "Query tqp stat fail, status = %d,queue = %d\n",
56 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
57 le32_to_cpu(desc
.data
[1]);
59 hclgevf_cmd_setup_basic_desc(&desc
, HCLGEVF_OPC_QUERY_TX_STATUS
,
62 desc
.data
[0] = cpu_to_le32(tqp
->index
& 0x1ff);
63 status
= hclgevf_cmd_send(&hdev
->hw
, &desc
, 1);
65 dev_err(&hdev
->pdev
->dev
,
66 "Query tqp stat fail, status = %d,queue = %d\n",
70 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
71 le32_to_cpu(desc
.data
[1]);
77 static u64
*hclgevf_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
79 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
80 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
81 struct hclgevf_tqp
*tqp
;
85 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
86 tqp
= container_of(handle
->kinfo
.tqp
[i
], struct hclgevf_tqp
, q
);
87 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
89 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
90 tqp
= container_of(handle
->kinfo
.tqp
[i
], struct hclgevf_tqp
, q
);
91 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
97 static int hclgevf_tqps_get_sset_count(struct hnae3_handle
*handle
, int strset
)
99 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
101 return hdev
->num_tqps
* 2;
104 static u8
*hclgevf_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
106 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
110 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
111 struct hclgevf_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
112 struct hclgevf_tqp
, q
);
113 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
115 buff
+= ETH_GSTRING_LEN
;
118 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
119 struct hclgevf_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
120 struct hclgevf_tqp
, q
);
121 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
123 buff
+= ETH_GSTRING_LEN
;
129 static void hclgevf_update_stats(struct hnae3_handle
*handle
,
130 struct net_device_stats
*net_stats
)
132 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
135 status
= hclgevf_tqps_update_stats(handle
);
137 dev_err(&hdev
->pdev
->dev
,
138 "VF update of TQPS stats fail, status = %d.\n",
142 static int hclgevf_get_sset_count(struct hnae3_handle
*handle
, int strset
)
144 if (strset
== ETH_SS_TEST
)
146 else if (strset
== ETH_SS_STATS
)
147 return hclgevf_tqps_get_sset_count(handle
, strset
);
152 static void hclgevf_get_strings(struct hnae3_handle
*handle
, u32 strset
,
155 u8
*p
= (char *)data
;
157 if (strset
== ETH_SS_STATS
)
158 p
= hclgevf_tqps_get_strings(handle
, p
);
161 static void hclgevf_get_stats(struct hnae3_handle
*handle
, u64
*data
)
163 hclgevf_tqps_get_stats(handle
, data
);
166 static int hclgevf_get_tc_info(struct hclgevf_dev
*hdev
)
171 status
= hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_GET_TCINFO
, 0, NULL
, 0,
172 true, &resp_msg
, sizeof(u8
));
174 dev_err(&hdev
->pdev
->dev
,
175 "VF request to get TC info from PF failed %d",
180 hdev
->hw_tc_map
= resp_msg
;
185 static int hclge_get_queue_info(struct hclgevf_dev
*hdev
)
187 #define HCLGEVF_TQPS_RSS_INFO_LEN 8
188 u8 resp_msg
[HCLGEVF_TQPS_RSS_INFO_LEN
];
191 status
= hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_GET_QINFO
, 0, NULL
, 0,
193 HCLGEVF_TQPS_RSS_INFO_LEN
);
195 dev_err(&hdev
->pdev
->dev
,
196 "VF request to get tqp info from PF failed %d",
201 memcpy(&hdev
->num_tqps
, &resp_msg
[0], sizeof(u16
));
202 memcpy(&hdev
->rss_size_max
, &resp_msg
[2], sizeof(u16
));
203 memcpy(&hdev
->num_desc
, &resp_msg
[4], sizeof(u16
));
204 memcpy(&hdev
->rx_buf_len
, &resp_msg
[6], sizeof(u16
));
209 static int hclgevf_alloc_tqps(struct hclgevf_dev
*hdev
)
211 struct hclgevf_tqp
*tqp
;
214 /* if this is on going reset then we need to re-allocate the TPQs
215 * since we cannot assume we would get same number of TPQs back from PF
217 if (hclgevf_dev_ongoing_reset(hdev
))
218 devm_kfree(&hdev
->pdev
->dev
, hdev
->htqp
);
220 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
221 sizeof(struct hclgevf_tqp
), GFP_KERNEL
);
227 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
228 tqp
->dev
= &hdev
->pdev
->dev
;
231 tqp
->q
.ae_algo
= &ae_algovf
;
232 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
233 tqp
->q
.desc_num
= hdev
->num_desc
;
234 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGEVF_TQP_REG_OFFSET
+
235 i
* HCLGEVF_TQP_REG_SIZE
;
243 static int hclgevf_knic_setup(struct hclgevf_dev
*hdev
)
245 struct hnae3_handle
*nic
= &hdev
->nic
;
246 struct hnae3_knic_private_info
*kinfo
;
247 u16 new_tqps
= hdev
->num_tqps
;
252 kinfo
->num_desc
= hdev
->num_desc
;
253 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
254 for (i
= 0; i
< HCLGEVF_MAX_TC_NUM
; i
++)
255 if (hdev
->hw_tc_map
& BIT(i
))
259 = min_t(u16
, hdev
->rss_size_max
, new_tqps
/ kinfo
->num_tc
);
260 new_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
261 kinfo
->num_tqps
= min(new_tqps
, hdev
->num_tqps
);
263 /* if this is on going reset then we need to re-allocate the hnae queues
264 * as well since number of TPQs from PF might have changed.
266 if (hclgevf_dev_ongoing_reset(hdev
))
267 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
269 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
270 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
274 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
275 hdev
->htqp
[i
].q
.handle
= &hdev
->nic
;
276 hdev
->htqp
[i
].q
.tqp_index
= i
;
277 kinfo
->tqp
[i
] = &hdev
->htqp
[i
].q
;
283 static void hclgevf_request_link_info(struct hclgevf_dev
*hdev
)
288 status
= hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_GET_LINK_STATUS
, 0, NULL
,
289 0, false, &resp_msg
, sizeof(u8
));
291 dev_err(&hdev
->pdev
->dev
,
292 "VF failed to fetch link status(%d) from PF", status
);
295 void hclgevf_update_link_status(struct hclgevf_dev
*hdev
, int link_state
)
297 struct hnae3_handle
*handle
= &hdev
->nic
;
298 struct hnae3_client
*client
;
300 client
= handle
->client
;
302 if (link_state
!= hdev
->hw
.mac
.link
) {
303 client
->ops
->link_status_change(handle
, !!link_state
);
304 hdev
->hw
.mac
.link
= link_state
;
308 static int hclgevf_set_handle_info(struct hclgevf_dev
*hdev
)
310 struct hnae3_handle
*nic
= &hdev
->nic
;
313 nic
->ae_algo
= &ae_algovf
;
314 nic
->pdev
= hdev
->pdev
;
315 nic
->numa_node_mask
= hdev
->numa_node_mask
;
316 nic
->flags
|= HNAE3_SUPPORT_VF
;
318 if (hdev
->ae_dev
->dev_type
!= HNAE3_DEV_KNIC
) {
319 dev_err(&hdev
->pdev
->dev
, "unsupported device type %d\n",
320 hdev
->ae_dev
->dev_type
);
324 ret
= hclgevf_knic_setup(hdev
);
326 dev_err(&hdev
->pdev
->dev
, "VF knic setup failed %d\n",
331 static void hclgevf_free_vector(struct hclgevf_dev
*hdev
, int vector_id
)
333 hdev
->vector_status
[vector_id
] = HCLGEVF_INVALID_VPORT
;
334 hdev
->num_msi_left
+= 1;
335 hdev
->num_msi_used
-= 1;
338 static int hclgevf_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
339 struct hnae3_vector_info
*vector_info
)
341 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
342 struct hnae3_vector_info
*vector
= vector_info
;
346 vector_num
= min(hdev
->num_msi_left
, vector_num
);
348 for (j
= 0; j
< vector_num
; j
++) {
349 for (i
= HCLGEVF_MISC_VECTOR_NUM
+ 1; i
< hdev
->num_msi
; i
++) {
350 if (hdev
->vector_status
[i
] == HCLGEVF_INVALID_VPORT
) {
351 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
352 vector
->io_addr
= hdev
->hw
.io_base
+
353 HCLGEVF_VECTOR_REG_BASE
+
354 (i
- 1) * HCLGEVF_VECTOR_REG_OFFSET
;
355 hdev
->vector_status
[i
] = 0;
356 hdev
->vector_irq
[i
] = vector
->vector
;
365 hdev
->num_msi_left
-= alloc
;
366 hdev
->num_msi_used
+= alloc
;
371 static int hclgevf_get_vector_index(struct hclgevf_dev
*hdev
, int vector
)
375 for (i
= 0; i
< hdev
->num_msi
; i
++)
376 if (vector
== hdev
->vector_irq
[i
])
382 static u32
hclgevf_get_rss_key_size(struct hnae3_handle
*handle
)
384 return HCLGEVF_RSS_KEY_SIZE
;
387 static u32
hclgevf_get_rss_indir_size(struct hnae3_handle
*handle
)
389 return HCLGEVF_RSS_IND_TBL_SIZE
;
392 static int hclgevf_set_rss_indir_table(struct hclgevf_dev
*hdev
)
394 const u8
*indir
= hdev
->rss_cfg
.rss_indirection_tbl
;
395 struct hclgevf_rss_indirection_table_cmd
*req
;
396 struct hclgevf_desc desc
;
400 req
= (struct hclgevf_rss_indirection_table_cmd
*)desc
.data
;
402 for (i
= 0; i
< HCLGEVF_RSS_CFG_TBL_NUM
; i
++) {
403 hclgevf_cmd_setup_basic_desc(&desc
, HCLGEVF_OPC_RSS_INDIR_TABLE
,
405 req
->start_table_index
= i
* HCLGEVF_RSS_CFG_TBL_SIZE
;
406 req
->rss_set_bitmap
= HCLGEVF_RSS_SET_BITMAP_MSK
;
407 for (j
= 0; j
< HCLGEVF_RSS_CFG_TBL_SIZE
; j
++)
409 indir
[i
* HCLGEVF_RSS_CFG_TBL_SIZE
+ j
];
411 status
= hclgevf_cmd_send(&hdev
->hw
, &desc
, 1);
413 dev_err(&hdev
->pdev
->dev
,
414 "VF failed(=%d) to set RSS indirection table\n",
423 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev
*hdev
, u16 rss_size
)
425 struct hclgevf_rss_tc_mode_cmd
*req
;
426 u16 tc_offset
[HCLGEVF_MAX_TC_NUM
];
427 u16 tc_valid
[HCLGEVF_MAX_TC_NUM
];
428 u16 tc_size
[HCLGEVF_MAX_TC_NUM
];
429 struct hclgevf_desc desc
;
434 req
= (struct hclgevf_rss_tc_mode_cmd
*)desc
.data
;
436 roundup_size
= roundup_pow_of_two(rss_size
);
437 roundup_size
= ilog2(roundup_size
);
439 for (i
= 0; i
< HCLGEVF_MAX_TC_NUM
; i
++) {
440 tc_valid
[i
] = !!(hdev
->hw_tc_map
& BIT(i
));
441 tc_size
[i
] = roundup_size
;
442 tc_offset
[i
] = rss_size
* i
;
445 hclgevf_cmd_setup_basic_desc(&desc
, HCLGEVF_OPC_RSS_TC_MODE
, false);
446 for (i
= 0; i
< HCLGEVF_MAX_TC_NUM
; i
++) {
447 hnae_set_bit(req
->rss_tc_mode
[i
], HCLGEVF_RSS_TC_VALID_B
,
448 (tc_valid
[i
] & 0x1));
449 hnae_set_field(req
->rss_tc_mode
[i
], HCLGEVF_RSS_TC_SIZE_M
,
450 HCLGEVF_RSS_TC_SIZE_S
, tc_size
[i
]);
451 hnae_set_field(req
->rss_tc_mode
[i
], HCLGEVF_RSS_TC_OFFSET_M
,
452 HCLGEVF_RSS_TC_OFFSET_S
, tc_offset
[i
]);
454 status
= hclgevf_cmd_send(&hdev
->hw
, &desc
, 1);
456 dev_err(&hdev
->pdev
->dev
,
457 "VF failed(=%d) to set rss tc mode\n", status
);
462 static int hclgevf_get_rss_hw_cfg(struct hnae3_handle
*handle
, u8
*hash
,
465 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
466 struct hclgevf_rss_config_cmd
*req
;
467 int lkup_times
= key
? 3 : 1;
468 struct hclgevf_desc desc
;
473 req
= (struct hclgevf_rss_config_cmd
*)desc
.data
;
474 lkup_times
= (lkup_times
== 3) ? 3 : ((hash
) ? 1 : 0);
476 for (key_offset
= 0; key_offset
< lkup_times
; key_offset
++) {
477 hclgevf_cmd_setup_basic_desc(&desc
,
478 HCLGEVF_OPC_RSS_GENERIC_CONFIG
,
480 req
->hash_config
|= (key_offset
<< HCLGEVF_RSS_HASH_KEY_OFFSET
);
482 status
= hclgevf_cmd_send(&hdev
->hw
, &desc
, 1);
484 dev_err(&hdev
->pdev
->dev
,
485 "failed to get hardware RSS cfg, status = %d\n",
492 HCLGEVF_RSS_KEY_SIZE
- HCLGEVF_RSS_HASH_KEY_NUM
* 2;
494 key_size
= HCLGEVF_RSS_HASH_KEY_NUM
;
497 memcpy(key
+ key_offset
* HCLGEVF_RSS_HASH_KEY_NUM
,
503 if ((req
->hash_config
& 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ
)
504 *hash
= ETH_RSS_HASH_TOP
;
506 *hash
= ETH_RSS_HASH_UNKNOWN
;
512 static int hclgevf_get_rss(struct hnae3_handle
*handle
, u32
*indir
, u8
*key
,
515 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
516 struct hclgevf_rss_cfg
*rss_cfg
= &hdev
->rss_cfg
;
520 for (i
= 0; i
< HCLGEVF_RSS_IND_TBL_SIZE
; i
++)
521 indir
[i
] = rss_cfg
->rss_indirection_tbl
[i
];
523 return hclgevf_get_rss_hw_cfg(handle
, hfunc
, key
);
526 static int hclgevf_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
527 const u8
*key
, const u8 hfunc
)
529 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
530 struct hclgevf_rss_cfg
*rss_cfg
= &hdev
->rss_cfg
;
533 /* update the shadow RSS table with user specified qids */
534 for (i
= 0; i
< HCLGEVF_RSS_IND_TBL_SIZE
; i
++)
535 rss_cfg
->rss_indirection_tbl
[i
] = indir
[i
];
537 /* update the hardware */
538 return hclgevf_set_rss_indir_table(hdev
);
541 static int hclgevf_get_tc_size(struct hnae3_handle
*handle
)
543 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
544 struct hclgevf_rss_cfg
*rss_cfg
= &hdev
->rss_cfg
;
546 return rss_cfg
->rss_size
;
549 static int hclgevf_bind_ring_to_vector(struct hnae3_handle
*handle
, bool en
,
551 struct hnae3_ring_chain_node
*ring_chain
)
553 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
554 struct hnae3_ring_chain_node
*node
;
555 struct hclge_mbx_vf_to_pf_cmd
*req
;
556 struct hclgevf_desc desc
;
557 int i
= 0, vector_id
;
561 req
= (struct hclge_mbx_vf_to_pf_cmd
*)desc
.data
;
562 vector_id
= hclgevf_get_vector_index(hdev
, vector
);
564 dev_err(&handle
->pdev
->dev
,
565 "Get vector index fail. ret =%d\n", vector_id
);
569 for (node
= ring_chain
; node
; node
= node
->next
) {
570 int idx_offset
= HCLGE_MBX_RING_MAP_BASIC_MSG_NUM
+
571 HCLGE_MBX_RING_NODE_VARIABLE_NUM
* i
;
574 hclgevf_cmd_setup_basic_desc(&desc
,
575 HCLGEVF_OPC_MBX_VF_TO_PF
,
578 HCLGE_MBX_MAP_RING_TO_VECTOR
:
579 HCLGE_MBX_UNMAP_RING_TO_VECTOR
;
581 req
->msg
[1] = vector_id
;
584 req
->msg
[idx_offset
] =
585 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
);
586 req
->msg
[idx_offset
+ 1] = node
->tqp_index
;
587 req
->msg
[idx_offset
+ 2] = hnae_get_field(node
->int_gl_idx
,
589 HNAE3_RING_GL_IDX_S
);
592 if ((i
== (HCLGE_MBX_VF_MSG_DATA_NUM
-
593 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM
) /
594 HCLGE_MBX_RING_NODE_VARIABLE_NUM
) ||
598 status
= hclgevf_cmd_send(&hdev
->hw
, &desc
, 1);
600 dev_err(&hdev
->pdev
->dev
,
601 "Map TQP fail, status is %d.\n",
606 hclgevf_cmd_setup_basic_desc(&desc
,
607 HCLGEVF_OPC_MBX_VF_TO_PF
,
610 req
->msg
[1] = vector_id
;
617 static int hclgevf_map_ring_to_vector(struct hnae3_handle
*handle
, int vector
,
618 struct hnae3_ring_chain_node
*ring_chain
)
620 return hclgevf_bind_ring_to_vector(handle
, true, vector
, ring_chain
);
623 static int hclgevf_unmap_ring_from_vector(
624 struct hnae3_handle
*handle
,
626 struct hnae3_ring_chain_node
*ring_chain
)
628 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
631 vector_id
= hclgevf_get_vector_index(hdev
, vector
);
633 dev_err(&handle
->pdev
->dev
,
634 "Get vector index fail. ret =%d\n", vector_id
);
638 ret
= hclgevf_bind_ring_to_vector(handle
, false, vector
, ring_chain
);
640 dev_err(&handle
->pdev
->dev
,
641 "Unmap ring from vector fail. vector=%d, ret =%d\n",
648 static int hclgevf_put_vector(struct hnae3_handle
*handle
, int vector
)
650 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
652 hclgevf_free_vector(hdev
, vector
);
657 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev
*hdev
,
658 bool en_uc_pmc
, bool en_mc_pmc
)
660 struct hclge_mbx_vf_to_pf_cmd
*req
;
661 struct hclgevf_desc desc
;
664 req
= (struct hclge_mbx_vf_to_pf_cmd
*)desc
.data
;
666 hclgevf_cmd_setup_basic_desc(&desc
, HCLGEVF_OPC_MBX_VF_TO_PF
, false);
667 req
->msg
[0] = HCLGE_MBX_SET_PROMISC_MODE
;
668 req
->msg
[1] = en_uc_pmc
? 1 : 0;
669 req
->msg
[2] = en_mc_pmc
? 1 : 0;
671 status
= hclgevf_cmd_send(&hdev
->hw
, &desc
, 1);
673 dev_err(&hdev
->pdev
->dev
,
674 "Set promisc mode fail, status is %d.\n", status
);
679 static void hclgevf_set_promisc_mode(struct hnae3_handle
*handle
,
680 bool en_uc_pmc
, bool en_mc_pmc
)
682 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
684 hclgevf_cmd_set_promisc_mode(hdev
, en_uc_pmc
, en_mc_pmc
);
687 static int hclgevf_tqp_enable(struct hclgevf_dev
*hdev
, int tqp_id
,
688 int stream_id
, bool enable
)
690 struct hclgevf_cfg_com_tqp_queue_cmd
*req
;
691 struct hclgevf_desc desc
;
694 req
= (struct hclgevf_cfg_com_tqp_queue_cmd
*)desc
.data
;
696 hclgevf_cmd_setup_basic_desc(&desc
, HCLGEVF_OPC_CFG_COM_TQP_QUEUE
,
698 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGEVF_RING_ID_MASK
);
699 req
->stream_id
= cpu_to_le16(stream_id
);
700 req
->enable
|= enable
<< HCLGEVF_TQP_ENABLE_B
;
702 status
= hclgevf_cmd_send(&hdev
->hw
, &desc
, 1);
704 dev_err(&hdev
->pdev
->dev
,
705 "TQP enable fail, status =%d.\n", status
);
710 static int hclgevf_get_queue_id(struct hnae3_queue
*queue
)
712 struct hclgevf_tqp
*tqp
= container_of(queue
, struct hclgevf_tqp
, q
);
717 static void hclgevf_reset_tqp_stats(struct hnae3_handle
*handle
)
719 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
720 struct hnae3_queue
*queue
;
721 struct hclgevf_tqp
*tqp
;
724 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
725 queue
= handle
->kinfo
.tqp
[i
];
726 tqp
= container_of(queue
, struct hclgevf_tqp
, q
);
727 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
731 static int hclgevf_cfg_func_mta_filter(struct hnae3_handle
*handle
, bool en
)
733 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
737 return hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_SET_MULTICAST
,
738 HCLGE_MBX_MAC_VLAN_MC_FUNC_MTA_ENABLE
,
739 msg
, 1, false, NULL
, 0);
742 static void hclgevf_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
744 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
746 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
749 static int hclgevf_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
752 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
753 u8
*old_mac_addr
= (u8
*)hdev
->hw
.mac
.mac_addr
;
754 u8
*new_mac_addr
= (u8
*)p
;
755 u8 msg_data
[ETH_ALEN
* 2];
759 ether_addr_copy(msg_data
, new_mac_addr
);
760 ether_addr_copy(&msg_data
[ETH_ALEN
], old_mac_addr
);
762 subcode
= is_first
? HCLGE_MBX_MAC_VLAN_UC_ADD
:
763 HCLGE_MBX_MAC_VLAN_UC_MODIFY
;
765 status
= hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_SET_UNICAST
,
766 subcode
, msg_data
, ETH_ALEN
* 2,
769 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_mac_addr
);
774 static int hclgevf_add_uc_addr(struct hnae3_handle
*handle
,
775 const unsigned char *addr
)
777 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
779 return hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_SET_UNICAST
,
780 HCLGE_MBX_MAC_VLAN_UC_ADD
,
781 addr
, ETH_ALEN
, false, NULL
, 0);
784 static int hclgevf_rm_uc_addr(struct hnae3_handle
*handle
,
785 const unsigned char *addr
)
787 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
789 return hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_SET_UNICAST
,
790 HCLGE_MBX_MAC_VLAN_UC_REMOVE
,
791 addr
, ETH_ALEN
, false, NULL
, 0);
794 static int hclgevf_add_mc_addr(struct hnae3_handle
*handle
,
795 const unsigned char *addr
)
797 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
799 return hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_SET_MULTICAST
,
800 HCLGE_MBX_MAC_VLAN_MC_ADD
,
801 addr
, ETH_ALEN
, false, NULL
, 0);
804 static int hclgevf_rm_mc_addr(struct hnae3_handle
*handle
,
805 const unsigned char *addr
)
807 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
809 return hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_SET_MULTICAST
,
810 HCLGE_MBX_MAC_VLAN_MC_REMOVE
,
811 addr
, ETH_ALEN
, false, NULL
, 0);
814 static int hclgevf_set_vlan_filter(struct hnae3_handle
*handle
,
815 __be16 proto
, u16 vlan_id
,
818 #define HCLGEVF_VLAN_MBX_MSG_LEN 5
819 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
820 u8 msg_data
[HCLGEVF_VLAN_MBX_MSG_LEN
];
825 if (proto
!= htons(ETH_P_8021Q
))
826 return -EPROTONOSUPPORT
;
828 msg_data
[0] = is_kill
;
829 memcpy(&msg_data
[1], &vlan_id
, sizeof(vlan_id
));
830 memcpy(&msg_data
[3], &proto
, sizeof(proto
));
831 return hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_SET_VLAN
,
832 HCLGE_MBX_VLAN_FILTER
, msg_data
,
833 HCLGEVF_VLAN_MBX_MSG_LEN
, false, NULL
, 0);
836 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
838 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
841 msg_data
= enable
? 1 : 0;
842 return hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_SET_VLAN
,
843 HCLGE_MBX_VLAN_RX_OFF_CFG
, &msg_data
,
847 static void hclgevf_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
849 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
853 memcpy(&msg_data
[0], &queue_id
, sizeof(queue_id
));
855 /* disable vf queue before send queue reset msg to PF */
856 ret
= hclgevf_tqp_enable(hdev
, queue_id
, 0, false);
860 hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_QUEUE_RESET
, 0, msg_data
,
864 static int hclgevf_notify_client(struct hclgevf_dev
*hdev
,
865 enum hnae3_reset_notify_type type
)
867 struct hnae3_client
*client
= hdev
->nic_client
;
868 struct hnae3_handle
*handle
= &hdev
->nic
;
870 if (!client
->ops
->reset_notify
)
873 return client
->ops
->reset_notify(handle
, type
);
876 static int hclgevf_reset_wait(struct hclgevf_dev
*hdev
)
878 #define HCLGEVF_RESET_WAIT_MS 500
879 #define HCLGEVF_RESET_WAIT_CNT 20
882 /* wait to check the hardware reset completion status */
883 val
= hclgevf_read_dev(&hdev
->hw
, HCLGEVF_FUN_RST_ING
);
884 while (hnae_get_bit(val
, HCLGEVF_FUN_RST_ING_B
) &&
885 (cnt
< HCLGEVF_RESET_WAIT_CNT
)) {
886 msleep(HCLGEVF_RESET_WAIT_MS
);
887 val
= hclgevf_read_dev(&hdev
->hw
, HCLGEVF_FUN_RST_ING
);
891 /* hardware completion status should be available by this time */
892 if (cnt
>= HCLGEVF_RESET_WAIT_CNT
) {
893 dev_warn(&hdev
->pdev
->dev
,
894 "could'nt get reset done status from h/w, timeout!\n");
898 /* we will wait a bit more to let reset of the stack to complete. This
899 * might happen in case reset assertion was made by PF. Yes, this also
900 * means we might end up waiting bit more even for VF reset.
907 static int hclgevf_reset_stack(struct hclgevf_dev
*hdev
)
911 /* uninitialize the nic client */
912 hclgevf_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
914 /* re-initialize the hclge device */
915 ret
= hclgevf_init_hdev(hdev
);
917 dev_err(&hdev
->pdev
->dev
,
918 "hclge device re-init failed, VF is disabled!\n");
922 /* bring up the nic client again */
923 hclgevf_notify_client(hdev
, HNAE3_INIT_CLIENT
);
928 static int hclgevf_reset(struct hclgevf_dev
*hdev
)
934 /* bring down the nic to stop any ongoing TX/RX */
935 hclgevf_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
937 /* check if VF could successfully fetch the hardware reset completion
938 * status from the hardware
940 ret
= hclgevf_reset_wait(hdev
);
942 /* can't do much in this situation, will disable VF */
943 dev_err(&hdev
->pdev
->dev
,
944 "VF failed(=%d) to fetch H/W reset completion status\n",
947 dev_warn(&hdev
->pdev
->dev
, "VF reset failed, disabling VF!\n");
948 hclgevf_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
954 /* now, re-initialize the nic client and ae device*/
955 ret
= hclgevf_reset_stack(hdev
);
957 dev_err(&hdev
->pdev
->dev
, "failed to reset VF stack\n");
959 /* bring up the nic to enable TX/RX again */
960 hclgevf_notify_client(hdev
, HNAE3_UP_CLIENT
);
967 static int hclgevf_do_reset(struct hclgevf_dev
*hdev
)
972 status
= hclgevf_send_mbx_msg(hdev
, HCLGE_MBX_RESET
, 0, NULL
,
973 0, false, &respmsg
, sizeof(u8
));
975 dev_err(&hdev
->pdev
->dev
,
976 "VF reset request to PF failed(=%d)\n", status
);
981 static void hclgevf_reset_event(struct hnae3_handle
*handle
)
983 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
985 dev_info(&hdev
->pdev
->dev
, "received reset request from VF enet\n");
987 handle
->reset_level
= HNAE3_VF_RESET
;
989 /* reset of this VF requested */
990 set_bit(HCLGEVF_RESET_REQUESTED
, &hdev
->reset_state
);
991 hclgevf_reset_task_schedule(hdev
);
993 handle
->last_reset_time
= jiffies
;
996 static u32
hclgevf_get_fw_version(struct hnae3_handle
*handle
)
998 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
1000 return hdev
->fw_version
;
1003 static void hclgevf_get_misc_vector(struct hclgevf_dev
*hdev
)
1005 struct hclgevf_misc_vector
*vector
= &hdev
->misc_vector
;
1007 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
,
1008 HCLGEVF_MISC_VECTOR_NUM
);
1009 vector
->addr
= hdev
->hw
.io_base
+ HCLGEVF_MISC_VECTOR_REG_BASE
;
1010 /* vector status always valid for Vector 0 */
1011 hdev
->vector_status
[HCLGEVF_MISC_VECTOR_NUM
] = 0;
1012 hdev
->vector_irq
[HCLGEVF_MISC_VECTOR_NUM
] = vector
->vector_irq
;
1014 hdev
->num_msi_left
-= 1;
1015 hdev
->num_msi_used
+= 1;
1018 void hclgevf_reset_task_schedule(struct hclgevf_dev
*hdev
)
1020 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED
, &hdev
->state
) &&
1021 !test_bit(HCLGEVF_STATE_RST_HANDLING
, &hdev
->state
)) {
1022 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
1023 schedule_work(&hdev
->rst_service_task
);
1027 void hclgevf_mbx_task_schedule(struct hclgevf_dev
*hdev
)
1029 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED
, &hdev
->state
) &&
1030 !test_bit(HCLGEVF_STATE_MBX_HANDLING
, &hdev
->state
)) {
1031 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
1032 schedule_work(&hdev
->mbx_service_task
);
1036 static void hclgevf_task_schedule(struct hclgevf_dev
*hdev
)
1038 if (!test_bit(HCLGEVF_STATE_DOWN
, &hdev
->state
) &&
1039 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED
, &hdev
->state
))
1040 schedule_work(&hdev
->service_task
);
1043 static void hclgevf_deferred_task_schedule(struct hclgevf_dev
*hdev
)
1045 /* if we have any pending mailbox event then schedule the mbx task */
1046 if (hdev
->mbx_event_pending
)
1047 hclgevf_mbx_task_schedule(hdev
);
1049 if (test_bit(HCLGEVF_RESET_PENDING
, &hdev
->reset_state
))
1050 hclgevf_reset_task_schedule(hdev
);
1053 static void hclgevf_service_timer(struct timer_list
*t
)
1055 struct hclgevf_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
1057 mod_timer(&hdev
->service_timer
, jiffies
+ 5 * HZ
);
1059 hclgevf_task_schedule(hdev
);
1062 static void hclgevf_reset_service_task(struct work_struct
*work
)
1064 struct hclgevf_dev
*hdev
=
1065 container_of(work
, struct hclgevf_dev
, rst_service_task
);
1068 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING
, &hdev
->state
))
1071 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
1073 if (test_and_clear_bit(HCLGEVF_RESET_PENDING
,
1074 &hdev
->reset_state
)) {
1075 /* PF has initmated that it is about to reset the hardware.
1076 * We now have to poll & check if harware has actually completed
1077 * the reset sequence. On hardware reset completion, VF needs to
1078 * reset the client and ae device.
1080 hdev
->reset_attempts
= 0;
1082 ret
= hclgevf_reset(hdev
);
1084 dev_err(&hdev
->pdev
->dev
, "VF stack reset failed.\n");
1085 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED
,
1086 &hdev
->reset_state
)) {
1087 /* we could be here when either of below happens:
1088 * 1. reset was initiated due to watchdog timeout due to
1089 * a. IMP was earlier reset and our TX got choked down and
1090 * which resulted in watchdog reacting and inducing VF
1091 * reset. This also means our cmdq would be unreliable.
1092 * b. problem in TX due to other lower layer(example link
1093 * layer not functioning properly etc.)
1094 * 2. VF reset might have been initiated due to some config
1097 * NOTE: Theres no clear way to detect above cases than to react
1098 * to the response of PF for this reset request. PF will ack the
1099 * 1b and 2. cases but we will not get any intimation about 1a
1100 * from PF as cmdq would be in unreliable state i.e. mailbox
1101 * communication between PF and VF would be broken.
1104 /* if we are never geting into pending state it means either:
1105 * 1. PF is not receiving our request which could be due to IMP
1108 * We cannot do much for 2. but to check first we can try reset
1109 * our PCIe + stack and see if it alleviates the problem.
1111 if (hdev
->reset_attempts
> 3) {
1112 /* prepare for full reset of stack + pcie interface */
1113 hdev
->nic
.reset_level
= HNAE3_VF_FULL_RESET
;
1115 /* "defer" schedule the reset task again */
1116 set_bit(HCLGEVF_RESET_PENDING
, &hdev
->reset_state
);
1118 hdev
->reset_attempts
++;
1120 /* request PF for resetting this VF via mailbox */
1121 ret
= hclgevf_do_reset(hdev
);
1123 dev_warn(&hdev
->pdev
->dev
,
1124 "VF rst fail, stack will call\n");
1128 clear_bit(HCLGEVF_STATE_RST_HANDLING
, &hdev
->state
);
1131 static void hclgevf_mailbox_service_task(struct work_struct
*work
)
1133 struct hclgevf_dev
*hdev
;
1135 hdev
= container_of(work
, struct hclgevf_dev
, mbx_service_task
);
1137 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING
, &hdev
->state
))
1140 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
1142 hclgevf_mbx_async_handler(hdev
);
1144 clear_bit(HCLGEVF_STATE_MBX_HANDLING
, &hdev
->state
);
1147 static void hclgevf_service_task(struct work_struct
*work
)
1149 struct hclgevf_dev
*hdev
;
1151 hdev
= container_of(work
, struct hclgevf_dev
, service_task
);
1153 /* request the link status from the PF. PF would be able to tell VF
1154 * about such updates in future so we might remove this later
1156 hclgevf_request_link_info(hdev
);
1158 hclgevf_deferred_task_schedule(hdev
);
1160 clear_bit(HCLGEVF_STATE_SERVICE_SCHED
, &hdev
->state
);
1163 static void hclgevf_clear_event_cause(struct hclgevf_dev
*hdev
, u32 regclr
)
1165 hclgevf_write_dev(&hdev
->hw
, HCLGEVF_VECTOR0_CMDQ_SRC_REG
, regclr
);
1168 static bool hclgevf_check_event_cause(struct hclgevf_dev
*hdev
, u32
*clearval
)
1172 /* fetch the events from their corresponding regs */
1173 cmdq_src_reg
= hclgevf_read_dev(&hdev
->hw
,
1174 HCLGEVF_VECTOR0_CMDQ_SRC_REG
);
1176 /* check for vector0 mailbox(=CMDQ RX) event source */
1177 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
1178 cmdq_src_reg
&= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B
);
1179 *clearval
= cmdq_src_reg
;
1183 dev_dbg(&hdev
->pdev
->dev
, "vector 0 interrupt from unknown source\n");
1188 static void hclgevf_enable_vector(struct hclgevf_misc_vector
*vector
, bool en
)
1190 writel(en
? 1 : 0, vector
->addr
);
1193 static irqreturn_t
hclgevf_misc_irq_handle(int irq
, void *data
)
1195 struct hclgevf_dev
*hdev
= data
;
1198 hclgevf_enable_vector(&hdev
->misc_vector
, false);
1199 if (!hclgevf_check_event_cause(hdev
, &clearval
))
1202 hclgevf_mbx_handler(hdev
);
1204 hclgevf_clear_event_cause(hdev
, clearval
);
1207 hclgevf_enable_vector(&hdev
->misc_vector
, true);
1212 static int hclgevf_configure(struct hclgevf_dev
*hdev
)
1216 /* get queue configuration from PF */
1217 ret
= hclge_get_queue_info(hdev
);
1220 /* get tc configuration from PF */
1221 return hclgevf_get_tc_info(hdev
);
1224 static int hclgevf_alloc_hdev(struct hnae3_ae_dev
*ae_dev
)
1226 struct pci_dev
*pdev
= ae_dev
->pdev
;
1227 struct hclgevf_dev
*hdev
= ae_dev
->priv
;
1229 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
1234 hdev
->ae_dev
= ae_dev
;
1235 ae_dev
->priv
= hdev
;
1240 static int hclgevf_init_roce_base_info(struct hclgevf_dev
*hdev
)
1242 struct hnae3_handle
*roce
= &hdev
->roce
;
1243 struct hnae3_handle
*nic
= &hdev
->nic
;
1245 roce
->rinfo
.num_vectors
= HCLGEVF_ROCEE_VECTOR_NUM
;
1247 if (hdev
->num_msi_left
< roce
->rinfo
.num_vectors
||
1248 hdev
->num_msi_left
== 0)
1251 roce
->rinfo
.base_vector
=
1252 hdev
->vector_status
[hdev
->num_msi_used
];
1254 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
1255 roce
->rinfo
.roce_io_base
= hdev
->hw
.io_base
;
1257 roce
->pdev
= nic
->pdev
;
1258 roce
->ae_algo
= nic
->ae_algo
;
1259 roce
->numa_node_mask
= nic
->numa_node_mask
;
1264 static int hclgevf_rss_init_hw(struct hclgevf_dev
*hdev
)
1266 struct hclgevf_rss_cfg
*rss_cfg
= &hdev
->rss_cfg
;
1269 rss_cfg
->rss_size
= hdev
->rss_size_max
;
1271 /* Initialize RSS indirect table for each vport */
1272 for (i
= 0; i
< HCLGEVF_RSS_IND_TBL_SIZE
; i
++)
1273 rss_cfg
->rss_indirection_tbl
[i
] = i
% hdev
->rss_size_max
;
1275 ret
= hclgevf_set_rss_indir_table(hdev
);
1279 return hclgevf_set_rss_tc_mode(hdev
, hdev
->rss_size_max
);
1282 static int hclgevf_init_vlan_config(struct hclgevf_dev
*hdev
)
1284 /* other vlan config(like, VLAN TX/RX offload) would also be added
1287 return hclgevf_set_vlan_filter(&hdev
->nic
, htons(ETH_P_8021Q
), 0,
1291 static int hclgevf_ae_start(struct hnae3_handle
*handle
)
1293 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
1296 for (i
= 0; i
< handle
->kinfo
.num_tqps
; i
++) {
1298 queue_id
= hclgevf_get_queue_id(handle
->kinfo
.tqp
[i
]);
1300 dev_warn(&hdev
->pdev
->dev
,
1301 "Get invalid queue id, ignore it\n");
1305 hclgevf_tqp_enable(hdev
, queue_id
, 0, true);
1308 /* reset tqp stats */
1309 hclgevf_reset_tqp_stats(handle
);
1311 hclgevf_request_link_info(hdev
);
1313 clear_bit(HCLGEVF_STATE_DOWN
, &hdev
->state
);
1314 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
1319 static void hclgevf_ae_stop(struct hnae3_handle
*handle
)
1321 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
1324 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1326 queue_id
= hclgevf_get_queue_id(handle
->kinfo
.tqp
[i
]);
1328 dev_warn(&hdev
->pdev
->dev
,
1329 "Get invalid queue id, ignore it\n");
1333 hclgevf_tqp_enable(hdev
, queue_id
, 0, false);
1336 /* reset tqp stats */
1337 hclgevf_reset_tqp_stats(handle
);
1338 del_timer_sync(&hdev
->service_timer
);
1339 cancel_work_sync(&hdev
->service_task
);
1340 hclgevf_update_link_status(hdev
, 0);
1343 static void hclgevf_state_init(struct hclgevf_dev
*hdev
)
1345 /* if this is on going reset then skip this initialization */
1346 if (hclgevf_dev_ongoing_reset(hdev
))
1349 /* setup tasks for the MBX */
1350 INIT_WORK(&hdev
->mbx_service_task
, hclgevf_mailbox_service_task
);
1351 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
1352 clear_bit(HCLGEVF_STATE_MBX_HANDLING
, &hdev
->state
);
1354 /* setup tasks for service timer */
1355 timer_setup(&hdev
->service_timer
, hclgevf_service_timer
, 0);
1357 INIT_WORK(&hdev
->service_task
, hclgevf_service_task
);
1358 clear_bit(HCLGEVF_STATE_SERVICE_SCHED
, &hdev
->state
);
1360 INIT_WORK(&hdev
->rst_service_task
, hclgevf_reset_service_task
);
1362 mutex_init(&hdev
->mbx_resp
.mbx_mutex
);
1364 /* bring the device down */
1365 set_bit(HCLGEVF_STATE_DOWN
, &hdev
->state
);
1368 static void hclgevf_state_uninit(struct hclgevf_dev
*hdev
)
1370 set_bit(HCLGEVF_STATE_DOWN
, &hdev
->state
);
1372 if (hdev
->service_timer
.function
)
1373 del_timer_sync(&hdev
->service_timer
);
1374 if (hdev
->service_task
.func
)
1375 cancel_work_sync(&hdev
->service_task
);
1376 if (hdev
->mbx_service_task
.func
)
1377 cancel_work_sync(&hdev
->mbx_service_task
);
1378 if (hdev
->rst_service_task
.func
)
1379 cancel_work_sync(&hdev
->rst_service_task
);
1381 mutex_destroy(&hdev
->mbx_resp
.mbx_mutex
);
1384 static int hclgevf_init_msi(struct hclgevf_dev
*hdev
)
1386 struct pci_dev
*pdev
= hdev
->pdev
;
1390 /* if this is on going reset then skip this initialization */
1391 if (hclgevf_dev_ongoing_reset(hdev
))
1394 hdev
->num_msi
= HCLGEVF_MAX_VF_VECTOR_NUM
;
1396 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
1397 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
1400 "failed(%d) to allocate MSI/MSI-X vectors\n",
1404 if (vectors
< hdev
->num_msi
)
1405 dev_warn(&hdev
->pdev
->dev
,
1406 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1407 hdev
->num_msi
, vectors
);
1409 hdev
->num_msi
= vectors
;
1410 hdev
->num_msi_left
= vectors
;
1411 hdev
->base_msi_vector
= pdev
->irq
;
1413 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1414 sizeof(u16
), GFP_KERNEL
);
1415 if (!hdev
->vector_status
) {
1416 pci_free_irq_vectors(pdev
);
1420 for (i
= 0; i
< hdev
->num_msi
; i
++)
1421 hdev
->vector_status
[i
] = HCLGEVF_INVALID_VPORT
;
1423 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1424 sizeof(int), GFP_KERNEL
);
1425 if (!hdev
->vector_irq
) {
1426 pci_free_irq_vectors(pdev
);
1433 static void hclgevf_uninit_msi(struct hclgevf_dev
*hdev
)
1435 struct pci_dev
*pdev
= hdev
->pdev
;
1437 pci_free_irq_vectors(pdev
);
1440 static int hclgevf_misc_irq_init(struct hclgevf_dev
*hdev
)
1444 /* if this is on going reset then skip this initialization */
1445 if (hclgevf_dev_ongoing_reset(hdev
))
1448 hclgevf_get_misc_vector(hdev
);
1450 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclgevf_misc_irq_handle
,
1451 0, "hclgevf_cmd", hdev
);
1453 dev_err(&hdev
->pdev
->dev
, "VF failed to request misc irq(%d)\n",
1454 hdev
->misc_vector
.vector_irq
);
1458 /* enable misc. vector(vector 0) */
1459 hclgevf_enable_vector(&hdev
->misc_vector
, true);
1464 static void hclgevf_misc_irq_uninit(struct hclgevf_dev
*hdev
)
1466 /* disable misc vector(vector 0) */
1467 hclgevf_enable_vector(&hdev
->misc_vector
, false);
1468 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
1469 hclgevf_free_vector(hdev
, 0);
1472 static int hclgevf_init_instance(struct hclgevf_dev
*hdev
,
1473 struct hnae3_client
*client
)
1477 switch (client
->type
) {
1478 case HNAE3_CLIENT_KNIC
:
1479 hdev
->nic_client
= client
;
1480 hdev
->nic
.client
= client
;
1482 ret
= client
->ops
->init_instance(&hdev
->nic
);
1486 if (hdev
->roce_client
&& hnae3_dev_roce_supported(hdev
)) {
1487 struct hnae3_client
*rc
= hdev
->roce_client
;
1489 ret
= hclgevf_init_roce_base_info(hdev
);
1492 ret
= rc
->ops
->init_instance(&hdev
->roce
);
1497 case HNAE3_CLIENT_UNIC
:
1498 hdev
->nic_client
= client
;
1499 hdev
->nic
.client
= client
;
1501 ret
= client
->ops
->init_instance(&hdev
->nic
);
1505 case HNAE3_CLIENT_ROCE
:
1506 if (hnae3_dev_roce_supported(hdev
)) {
1507 hdev
->roce_client
= client
;
1508 hdev
->roce
.client
= client
;
1511 if (hdev
->roce_client
&& hdev
->nic_client
) {
1512 ret
= hclgevf_init_roce_base_info(hdev
);
1516 ret
= client
->ops
->init_instance(&hdev
->roce
);
1525 static void hclgevf_uninit_instance(struct hclgevf_dev
*hdev
,
1526 struct hnae3_client
*client
)
1528 /* un-init roce, if it exists */
1529 if (hdev
->roce_client
)
1530 hdev
->roce_client
->ops
->uninit_instance(&hdev
->roce
, 0);
1532 /* un-init nic/unic, if this was not called by roce client */
1533 if ((client
->ops
->uninit_instance
) &&
1534 (client
->type
!= HNAE3_CLIENT_ROCE
))
1535 client
->ops
->uninit_instance(&hdev
->nic
, 0);
1538 static int hclgevf_register_client(struct hnae3_client
*client
,
1539 struct hnae3_ae_dev
*ae_dev
)
1541 struct hclgevf_dev
*hdev
= ae_dev
->priv
;
1543 return hclgevf_init_instance(hdev
, client
);
1546 static void hclgevf_unregister_client(struct hnae3_client
*client
,
1547 struct hnae3_ae_dev
*ae_dev
)
1549 struct hclgevf_dev
*hdev
= ae_dev
->priv
;
1551 hclgevf_uninit_instance(hdev
, client
);
1554 static int hclgevf_pci_init(struct hclgevf_dev
*hdev
)
1556 struct pci_dev
*pdev
= hdev
->pdev
;
1557 struct hclgevf_hw
*hw
;
1560 /* check if we need to skip initialization of pci. This will happen if
1561 * device is undergoing VF reset. Otherwise, we would need to
1562 * re-initialize pci interface again i.e. when device is not going
1563 * through *any* reset or actually undergoing full reset.
1565 if (hclgevf_dev_ongoing_reset(hdev
))
1568 ret
= pci_enable_device(pdev
);
1570 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
1574 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
1576 dev_err(&pdev
->dev
, "can't set consistent PCI DMA, exiting");
1577 goto err_disable_device
;
1580 ret
= pci_request_regions(pdev
, HCLGEVF_DRIVER_NAME
);
1582 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
1583 goto err_disable_device
;
1586 pci_set_master(pdev
);
1589 hw
->io_base
= pci_iomap(pdev
, 2, 0);
1591 dev_err(&pdev
->dev
, "can't map configuration register space\n");
1593 goto err_clr_master
;
1599 pci_clear_master(pdev
);
1600 pci_release_regions(pdev
);
1602 pci_disable_device(pdev
);
1607 static void hclgevf_pci_uninit(struct hclgevf_dev
*hdev
)
1609 struct pci_dev
*pdev
= hdev
->pdev
;
1611 pci_iounmap(pdev
, hdev
->hw
.io_base
);
1612 pci_clear_master(pdev
);
1613 pci_release_regions(pdev
);
1614 pci_disable_device(pdev
);
1617 static int hclgevf_init_hdev(struct hclgevf_dev
*hdev
)
1619 struct pci_dev
*pdev
= hdev
->pdev
;
1622 /* check if device is on-going full reset(i.e. pcie as well) */
1623 if (hclgevf_dev_ongoing_full_reset(hdev
)) {
1624 dev_warn(&pdev
->dev
, "device is going full reset\n");
1625 hclgevf_uninit_hdev(hdev
);
1628 ret
= hclgevf_pci_init(hdev
);
1630 dev_err(&pdev
->dev
, "PCI initialization failed\n");
1634 ret
= hclgevf_init_msi(hdev
);
1636 dev_err(&pdev
->dev
, "failed(%d) to init MSI/MSI-X\n", ret
);
1640 hclgevf_state_init(hdev
);
1642 ret
= hclgevf_cmd_init(hdev
);
1646 ret
= hclgevf_misc_irq_init(hdev
);
1648 dev_err(&pdev
->dev
, "failed(%d) to init Misc IRQ(vector0)\n",
1650 goto err_misc_irq_init
;
1653 ret
= hclgevf_configure(hdev
);
1655 dev_err(&pdev
->dev
, "failed(%d) to fetch configuration\n", ret
);
1659 ret
= hclgevf_alloc_tqps(hdev
);
1661 dev_err(&pdev
->dev
, "failed(%d) to allocate TQPs\n", ret
);
1665 ret
= hclgevf_set_handle_info(hdev
);
1667 dev_err(&pdev
->dev
, "failed(%d) to set handle info\n", ret
);
1671 /* Initialize VF's MTA */
1672 hdev
->accept_mta_mc
= true;
1673 ret
= hclgevf_cfg_func_mta_filter(&hdev
->nic
, hdev
->accept_mta_mc
);
1675 dev_err(&hdev
->pdev
->dev
,
1676 "failed(%d) to set mta filter mode\n", ret
);
1680 /* Initialize RSS for this VF */
1681 ret
= hclgevf_rss_init_hw(hdev
);
1683 dev_err(&hdev
->pdev
->dev
,
1684 "failed(%d) to initialize RSS\n", ret
);
1688 ret
= hclgevf_init_vlan_config(hdev
);
1690 dev_err(&hdev
->pdev
->dev
,
1691 "failed(%d) to initialize VLAN config\n", ret
);
1695 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME
);
1700 hclgevf_misc_irq_uninit(hdev
);
1702 hclgevf_cmd_uninit(hdev
);
1704 hclgevf_state_uninit(hdev
);
1705 hclgevf_uninit_msi(hdev
);
1707 hclgevf_pci_uninit(hdev
);
1711 static void hclgevf_uninit_hdev(struct hclgevf_dev
*hdev
)
1713 hclgevf_state_uninit(hdev
);
1714 hclgevf_misc_irq_uninit(hdev
);
1715 hclgevf_cmd_uninit(hdev
);
1716 hclgevf_uninit_msi(hdev
);
1717 hclgevf_pci_uninit(hdev
);
1720 static int hclgevf_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
1722 struct pci_dev
*pdev
= ae_dev
->pdev
;
1725 ret
= hclgevf_alloc_hdev(ae_dev
);
1727 dev_err(&pdev
->dev
, "hclge device allocation failed\n");
1731 ret
= hclgevf_init_hdev(ae_dev
->priv
);
1733 dev_err(&pdev
->dev
, "hclge device initialization failed\n");
1738 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
1740 struct hclgevf_dev
*hdev
= ae_dev
->priv
;
1742 hclgevf_uninit_hdev(hdev
);
1743 ae_dev
->priv
= NULL
;
1746 static u32
hclgevf_get_max_channels(struct hclgevf_dev
*hdev
)
1748 struct hnae3_handle
*nic
= &hdev
->nic
;
1749 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1751 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
1755 * hclgevf_get_channels - Get the current channels enabled and max supported.
1756 * @handle: hardware information for network interface
1757 * @ch: ethtool channels structure
1759 * We don't support separate tx and rx queues as channels. The other count
1760 * represents how many queues are being used for control. max_combined counts
1761 * how many queue pairs we can support. They may not be mapped 1 to 1 with
1762 * q_vectors since we support a lot more queue pairs than q_vectors.
1764 static void hclgevf_get_channels(struct hnae3_handle
*handle
,
1765 struct ethtool_channels
*ch
)
1767 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
1769 ch
->max_combined
= hclgevf_get_max_channels(hdev
);
1770 ch
->other_count
= 0;
1772 ch
->combined_count
= hdev
->num_tqps
;
1775 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
1776 u16
*free_tqps
, u16
*max_rss_size
)
1778 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
1781 *max_rss_size
= hdev
->rss_size_max
;
1784 static int hclgevf_get_status(struct hnae3_handle
*handle
)
1786 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
1788 return hdev
->hw
.mac
.link
;
1791 static void hclgevf_get_ksettings_an_result(struct hnae3_handle
*handle
,
1792 u8
*auto_neg
, u32
*speed
,
1795 struct hclgevf_dev
*hdev
= hclgevf_ae_get_hdev(handle
);
1798 *speed
= hdev
->hw
.mac
.speed
;
1800 *duplex
= hdev
->hw
.mac
.duplex
;
1802 *auto_neg
= AUTONEG_DISABLE
;
1805 void hclgevf_update_speed_duplex(struct hclgevf_dev
*hdev
, u32 speed
,
1808 hdev
->hw
.mac
.speed
= speed
;
1809 hdev
->hw
.mac
.duplex
= duplex
;
1812 static const struct hnae3_ae_ops hclgevf_ops
= {
1813 .init_ae_dev
= hclgevf_init_ae_dev
,
1814 .uninit_ae_dev
= hclgevf_uninit_ae_dev
,
1815 .init_client_instance
= hclgevf_register_client
,
1816 .uninit_client_instance
= hclgevf_unregister_client
,
1817 .start
= hclgevf_ae_start
,
1818 .stop
= hclgevf_ae_stop
,
1819 .map_ring_to_vector
= hclgevf_map_ring_to_vector
,
1820 .unmap_ring_from_vector
= hclgevf_unmap_ring_from_vector
,
1821 .get_vector
= hclgevf_get_vector
,
1822 .put_vector
= hclgevf_put_vector
,
1823 .reset_queue
= hclgevf_reset_tqp
,
1824 .set_promisc_mode
= hclgevf_set_promisc_mode
,
1825 .get_mac_addr
= hclgevf_get_mac_addr
,
1826 .set_mac_addr
= hclgevf_set_mac_addr
,
1827 .add_uc_addr
= hclgevf_add_uc_addr
,
1828 .rm_uc_addr
= hclgevf_rm_uc_addr
,
1829 .add_mc_addr
= hclgevf_add_mc_addr
,
1830 .rm_mc_addr
= hclgevf_rm_mc_addr
,
1831 .get_stats
= hclgevf_get_stats
,
1832 .update_stats
= hclgevf_update_stats
,
1833 .get_strings
= hclgevf_get_strings
,
1834 .get_sset_count
= hclgevf_get_sset_count
,
1835 .get_rss_key_size
= hclgevf_get_rss_key_size
,
1836 .get_rss_indir_size
= hclgevf_get_rss_indir_size
,
1837 .get_rss
= hclgevf_get_rss
,
1838 .set_rss
= hclgevf_set_rss
,
1839 .get_tc_size
= hclgevf_get_tc_size
,
1840 .get_fw_version
= hclgevf_get_fw_version
,
1841 .set_vlan_filter
= hclgevf_set_vlan_filter
,
1842 .enable_hw_strip_rxvtag
= hclgevf_en_hw_strip_rxvtag
,
1843 .reset_event
= hclgevf_reset_event
,
1844 .get_channels
= hclgevf_get_channels
,
1845 .get_tqps_and_rss_info
= hclgevf_get_tqps_and_rss_info
,
1846 .get_status
= hclgevf_get_status
,
1847 .get_ksettings_an_result
= hclgevf_get_ksettings_an_result
,
1850 static struct hnae3_ae_algo ae_algovf
= {
1851 .ops
= &hclgevf_ops
,
1852 .name
= HCLGEVF_NAME
,
1853 .pdev_id_table
= ae_algovf_pci_tbl
,
1856 static int hclgevf_init(void)
1858 pr_info("%s is initializing\n", HCLGEVF_NAME
);
1860 hnae3_register_ae_algo(&ae_algovf
);
1865 static void hclgevf_exit(void)
1867 hnae3_unregister_ae_algo(&ae_algovf
);
1869 module_init(hclgevf_init
);
1870 module_exit(hclgevf_exit
);
1872 MODULE_LICENSE("GPL");
1873 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
1874 MODULE_DESCRIPTION("HCLGEVF Driver");
1875 MODULE_VERSION(HCLGEVF_MOD_VERSION
);