drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
   3
   4 #ifndef __HCLGEVF_MAIN_H
   5 #define __HCLGEVF_MAIN_H
   6 #include <linux/fs.h>
   7 #include <linux/if_vlan.h>
   8 #include <linux/types.h>
   9 #include "hclge_mbx.h"
  10 #include "hclgevf_cmd.h"
  11 #include "hnae3.h"
  12
  13 #define HCLGEVF_MOD_VERSION "1.0"
  14 #define HCLGEVF_DRIVER_NAME "hclgevf"
  15
  16 #define HCLGEVF_MAX_VLAN_ID     4095
  17 #define HCLGEVF_MISC_VECTOR_NUM         0
  18
  19 #define HCLGEVF_INVALID_VPORT           0xffff
  20 #define HCLGEVF_GENERAL_TASK_INTERVAL     5
  21 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL  2
  22
  23 /* This number in actual depends upon the total number of VFs
  24  * created by physical function. But the maximum number of
  25  * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
  26  */
  27 #define HCLGEVF_MAX_VF_VECTOR_NUM       (32 + 1)
  28
  29 #define HCLGEVF_VECTOR_REG_BASE         0x20000
  30 #define HCLGEVF_MISC_VECTOR_REG_BASE    0x20400
  31 #define HCLGEVF_VECTOR_REG_OFFSET       0x4
  32 #define HCLGEVF_VECTOR_VF_OFFSET                0x100000
  33
  34 /* bar registers for cmdq */
  35 #define HCLGEVF_CMDQ_TX_ADDR_L_REG              0x27000
  36 #define HCLGEVF_CMDQ_TX_ADDR_H_REG              0x27004
  37 #define HCLGEVF_CMDQ_TX_DEPTH_REG               0x27008
  38 #define HCLGEVF_CMDQ_TX_TAIL_REG                0x27010
  39 #define HCLGEVF_CMDQ_TX_HEAD_REG                0x27014
  40 #define HCLGEVF_CMDQ_RX_ADDR_L_REG              0x27018
  41 #define HCLGEVF_CMDQ_RX_ADDR_H_REG              0x2701C
  42 #define HCLGEVF_CMDQ_RX_DEPTH_REG               0x27020
  43 #define HCLGEVF_CMDQ_RX_TAIL_REG                0x27024
  44 #define HCLGEVF_CMDQ_RX_HEAD_REG                0x27028
  45 #define HCLGEVF_CMDQ_INTR_SRC_REG               0x27100
  46 #define HCLGEVF_CMDQ_INTR_STS_REG               0x27104
  47 #define HCLGEVF_CMDQ_INTR_EN_REG                0x27108
  48 #define HCLGEVF_CMDQ_INTR_GEN_REG               0x2710C
  49
  50 /* bar registers for common func */
  51 #define HCLGEVF_GRO_EN_REG                      0x28000
  52
  53 /* bar registers for rcb */
  54 #define HCLGEVF_RING_RX_ADDR_L_REG              0x80000
  55 #define HCLGEVF_RING_RX_ADDR_H_REG              0x80004
  56 #define HCLGEVF_RING_RX_BD_NUM_REG              0x80008
  57 #define HCLGEVF_RING_RX_BD_LENGTH_REG           0x8000C
  58 #define HCLGEVF_RING_RX_MERGE_EN_REG            0x80014
  59 #define HCLGEVF_RING_RX_TAIL_REG                0x80018
  60 #define HCLGEVF_RING_RX_HEAD_REG                0x8001C
  61 #define HCLGEVF_RING_RX_FBD_NUM_REG             0x80020
  62 #define HCLGEVF_RING_RX_OFFSET_REG              0x80024
  63 #define HCLGEVF_RING_RX_FBD_OFFSET_REG          0x80028
  64 #define HCLGEVF_RING_RX_STASH_REG               0x80030
  65 #define HCLGEVF_RING_RX_BD_ERR_REG              0x80034
  66 #define HCLGEVF_RING_TX_ADDR_L_REG              0x80040
  67 #define HCLGEVF_RING_TX_ADDR_H_REG              0x80044
  68 #define HCLGEVF_RING_TX_BD_NUM_REG              0x80048
  69 #define HCLGEVF_RING_TX_PRIORITY_REG            0x8004C
  70 #define HCLGEVF_RING_TX_TC_REG                  0x80050
  71 #define HCLGEVF_RING_TX_MERGE_EN_REG            0x80054
  72 #define HCLGEVF_RING_TX_TAIL_REG                0x80058
  73 #define HCLGEVF_RING_TX_HEAD_REG                0x8005C
  74 #define HCLGEVF_RING_TX_FBD_NUM_REG             0x80060
  75 #define HCLGEVF_RING_TX_OFFSET_REG              0x80064
  76 #define HCLGEVF_RING_TX_EBD_NUM_REG             0x80068
  77 #define HCLGEVF_RING_TX_EBD_OFFSET_REG          0x80070
  78 #define HCLGEVF_RING_TX_BD_ERR_REG              0x80074
  79 #define HCLGEVF_RING_EN_REG                     0x80090
  80
  81 /* bar registers for tqp interrupt */
  82 #define HCLGEVF_TQP_INTR_CTRL_REG               0x20000
  83 #define HCLGEVF_TQP_INTR_GL0_REG                0x20100
  84 #define HCLGEVF_TQP_INTR_GL1_REG                0x20200
  85 #define HCLGEVF_TQP_INTR_GL2_REG                0x20300
  86 #define HCLGEVF_TQP_INTR_RL_REG                 0x20900
  87
  88 /* Vector0 interrupt CMDQ event source register(RW) */
  89 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG    0x27100
  90 /* CMDQ register bits for RX event(=MBX event) */
  91 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B   1
  92 /* RST register bits for RESET event */
  93 #define HCLGEVF_VECTOR0_RST_INT_B       2
  94
  95 #define HCLGEVF_TQP_RESET_TRY_TIMES     10
  96 /* Reset related Registers */
  97 #define HCLGEVF_RST_ING                 0x20C00
  98 #define HCLGEVF_FUN_RST_ING_BIT         BIT(0)
  99 #define HCLGEVF_GLOBAL_RST_ING_BIT      BIT(5)
 100 #define HCLGEVF_CORE_RST_ING_BIT        BIT(6)
 101 #define HCLGEVF_IMP_RST_ING_BIT         BIT(7)
 102 #define HCLGEVF_RST_ING_BITS \
 103         (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
 104          HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)
 105
 106 #define HCLGEVF_RSS_IND_TBL_SIZE                512
 107 #define HCLGEVF_RSS_SET_BITMAP_MSK      0xffff
 108 #define HCLGEVF_RSS_KEY_SIZE            40
 109 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ  0
 110 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE    1
 111 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2
 112 #define HCLGEVF_RSS_HASH_ALGO_MASK      0xf
 113 #define HCLGEVF_RSS_CFG_TBL_NUM \
 114         (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE)
 115 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER   GENMASK(3, 0)
 116 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP    GENMASK(4, 0)
 117 #define HCLGEVF_D_PORT_BIT              BIT(0)
 118 #define HCLGEVF_S_PORT_BIT              BIT(1)
 119 #define HCLGEVF_D_IP_BIT                BIT(2)
 120 #define HCLGEVF_S_IP_BIT                BIT(3)
 121 #define HCLGEVF_V_TAG_BIT               BIT(4)
 122
 123 #define HCLGEVF_STATS_TIMER_INTERVAL    (36)
 124
 125 enum hclgevf_evt_cause {
 126         HCLGEVF_VECTOR0_EVENT_RST,
 127         HCLGEVF_VECTOR0_EVENT_MBX,
 128         HCLGEVF_VECTOR0_EVENT_OTHER,
 129 };
 130
 131 /* states of hclgevf device & tasks */
 132 enum hclgevf_states {
 133         /* device states */
 134         HCLGEVF_STATE_DOWN,
 135         HCLGEVF_STATE_DISABLED,
 136         HCLGEVF_STATE_IRQ_INITED,
 137         HCLGEVF_STATE_REMOVING,
 138         HCLGEVF_STATE_NIC_REGISTERED,
 139         /* task states */
 140         HCLGEVF_STATE_SERVICE_SCHED,
 141         HCLGEVF_STATE_RST_SERVICE_SCHED,
 142         HCLGEVF_STATE_RST_HANDLING,
 143         HCLGEVF_STATE_MBX_SERVICE_SCHED,
 144         HCLGEVF_STATE_MBX_HANDLING,
 145         HCLGEVF_STATE_CMD_DISABLE,
 146 };
 147
 148 #define HCLGEVF_MPF_ENBALE 1
 149
 150 struct hclgevf_mac {
 151         u8 media_type;
 152         u8 module_type;
 153         u8 mac_addr[ETH_ALEN];
 154         int link;
 155         u8 duplex;
 156         u32 speed;
 157         u64 supported;
 158         u64 advertising;
 159 };
 160
 161 struct hclgevf_hw {
 162         void __iomem *io_base;
 163         int num_vec;
 164         struct hclgevf_cmq cmq;
 165         struct hclgevf_mac mac;
 166         void *hdev; /* hchgevf device it is part of */
 167 };
 168
 169 /* TQP stats */
 170 struct hlcgevf_tqp_stats {
 171         /* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
 172         u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
 173         /* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
 174         u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
 175 };
 176
 177 struct hclgevf_tqp {
 178         struct device *dev;     /* device for DMA mapping */
 179         struct hnae3_queue q;
 180         struct hlcgevf_tqp_stats tqp_stats;
 181         u16 index;              /* global index in a NIC controller */
 182
 183         bool alloced;
 184 };
 185
 186 struct hclgevf_cfg {
 187         u8 vmdq_vport_num;
 188         u8 tc_num;
 189         u16 tqp_desc_num;
 190         u16 rx_buf_len;
 191         u8 phy_addr;
 192         u8 media_type;
 193         u8 mac_addr[ETH_ALEN];
 194         u32 numa_node_map;
 195 };
 196
 197 struct hclgevf_rss_tuple_cfg {
 198         u8 ipv4_tcp_en;
 199         u8 ipv4_udp_en;
 200         u8 ipv4_sctp_en;
 201         u8 ipv4_fragment_en;
 202         u8 ipv6_tcp_en;
 203         u8 ipv6_udp_en;
 204         u8 ipv6_sctp_en;
 205         u8 ipv6_fragment_en;
 206 };
 207
 208 struct hclgevf_rss_cfg {
 209         u8  rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */
 210         u32 hash_algo;
 211         u32 rss_size;
 212         u8 hw_tc_map;
 213         u8  rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */
 214         struct hclgevf_rss_tuple_cfg rss_tuple_sets;
 215 };
 216
 217 struct hclgevf_misc_vector {
 218         u8 __iomem *addr;
 219         int vector_irq;
 220 };
 221
 222 struct hclgevf_rst_stats {
 223         u32 rst_cnt;                    /* the number of reset */
 224         u32 vf_func_rst_cnt;            /* the number of VF function reset */
 225         u32 flr_rst_cnt;                /* the number of FLR */
 226         u32 vf_rst_cnt;                 /* the number of VF reset */
 227         u32 rst_done_cnt;               /* the number of reset completed */
 228         u32 hw_rst_done_cnt;            /* the number of HW reset completed */
 229         u32 rst_fail_cnt;               /* the number of VF reset fail */
 230 };
 231
 232 struct hclgevf_dev {
 233         struct pci_dev *pdev;
 234         struct hnae3_ae_dev *ae_dev;
 235         struct hclgevf_hw hw;
 236         struct hclgevf_misc_vector misc_vector;
 237         struct hclgevf_rss_cfg rss_cfg;
 238         unsigned long state;
 239         unsigned long flr_state;
 240         unsigned long default_reset_request;
 241         unsigned long last_reset_time;
 242         enum hnae3_reset_type reset_level;
 243         unsigned long reset_pending;
 244         enum hnae3_reset_type reset_type;
 245
 246 #define HCLGEVF_RESET_REQUESTED         0
 247 #define HCLGEVF_RESET_PENDING           1
 248         unsigned long reset_state;      /* requested, pending */
 249         struct hclgevf_rst_stats rst_stats;
 250         u32 reset_attempts;
 251
 252         u32 fw_version;
 253         u16 num_tqps;           /* num task queue pairs of this PF */
 254
 255         u16 alloc_rss_size;     /* allocated RSS task queue */
 256         u16 rss_size_max;       /* HW defined max RSS task queue */
 257
 258         u16 num_alloc_vport;    /* num vports this driver supports */
 259         u32 numa_node_mask;
 260         u16 rx_buf_len;
 261         u16 num_tx_desc;        /* desc num of per tx queue */
 262         u16 num_rx_desc;        /* desc num of per rx queue */
 263         u8 hw_tc_map;
 264
 265         u16 num_msi;
 266         u16 num_msi_left;
 267         u16 num_msi_used;
 268         u16 num_roce_msix;      /* Num of roce vectors for this VF */
 269         u16 roce_base_msix_offset;
 270         int roce_base_vector;
 271         u32 base_msi_vector;
 272         u16 *vector_status;
 273         int *vector_irq;
 274
 275         unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
 276
 277         bool mbx_event_pending;
 278         struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
 279         struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
 280
 281         struct timer_list service_timer;
 282         struct timer_list keep_alive_timer;
 283         struct work_struct service_task;
 284         struct work_struct keep_alive_task;
 285         struct work_struct rst_service_task;
 286         struct work_struct mbx_service_task;
 287
 288         struct hclgevf_tqp *htqp;
 289
 290         struct hnae3_handle nic;
 291         struct hnae3_handle roce;
 292
 293         struct hnae3_client *nic_client;
 294         struct hnae3_client *roce_client;
 295         u32 flag;
 296         u32 stats_timer;
 297 };
 298
 299 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
 300 {
 301         return !!hdev->reset_pending;
 302 }
 303
 304 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode,
 305                          const u8 *msg_data, u8 msg_len, bool need_resp,
 306                          u8 *resp_data, u16 resp_len);
 307 void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
 308 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
 309
 310 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
 311 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
 312                                  u8 duplex);
 313 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
 314 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
 315 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
 316                                         u8 *port_base_vlan_info, u8 data_size);
 317 #endif