drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Huawei HiNIC PCI Express Linux driver
   4  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   5  */
   6
   7 #ifndef HINIC_HW_DEV_H
   8 #define HINIC_HW_DEV_H
   9
  10 #include <linux/pci.h>
  11 #include <linux/types.h>
  12 #include <linux/bitops.h>
  13
  14 #include "hinic_hw_if.h"
  15 #include "hinic_hw_eqs.h"
  16 #include "hinic_hw_mgmt.h"
  17 #include "hinic_hw_qp.h"
  18 #include "hinic_hw_io.h"
  19
  20 #define HINIC_MAX_QPS   32
  21
  22 #define HINIC_MGMT_NUM_MSG_CMD  (HINIC_MGMT_MSG_CMD_MAX - \
  23                                  HINIC_MGMT_MSG_CMD_BASE)
  24
  25 struct hinic_cap {
  26         u16     max_qps;
  27         u16     num_qps;
  28 };
  29
  30 enum hinic_port_cmd {
  31         HINIC_PORT_CMD_CHANGE_MTU       = 2,
  32
  33         HINIC_PORT_CMD_ADD_VLAN         = 3,
  34         HINIC_PORT_CMD_DEL_VLAN         = 4,
  35
  36         HINIC_PORT_CMD_SET_MAC          = 9,
  37         HINIC_PORT_CMD_GET_MAC          = 10,
  38         HINIC_PORT_CMD_DEL_MAC          = 11,
  39
  40         HINIC_PORT_CMD_SET_RX_MODE      = 12,
  41
  42         HINIC_PORT_CMD_GET_LINK_STATE   = 24,
  43
  44         HINIC_PORT_CMD_SET_RX_CSUM      = 26,
  45
  46         HINIC_PORT_CMD_SET_PORT_STATE   = 41,
  47
  48         HINIC_PORT_CMD_FWCTXT_INIT      = 69,
  49
  50         HINIC_PORT_CMD_SET_FUNC_STATE   = 93,
  51
  52         HINIC_PORT_CMD_GET_GLOBAL_QPN   = 102,
  53
  54         HINIC_PORT_CMD_SET_TSO          = 112,
  55
  56         HINIC_PORT_CMD_GET_CAP          = 170,
  57 };
  58
  59 enum hinic_mgmt_msg_cmd {
  60         HINIC_MGMT_MSG_CMD_BASE         = 160,
  61
  62         HINIC_MGMT_MSG_CMD_LINK_STATUS  = 160,
  63
  64         HINIC_MGMT_MSG_CMD_MAX,
  65 };
  66
  67 enum hinic_cb_state {
  68         HINIC_CB_ENABLED = BIT(0),
  69         HINIC_CB_RUNNING = BIT(1),
  70 };
  71
  72 enum hinic_res_state {
  73         HINIC_RES_CLEAN         = 0,
  74         HINIC_RES_ACTIVE        = 1,
  75 };
  76
  77 struct hinic_cmd_fw_ctxt {
  78         u8      status;
  79         u8      version;
  80         u8      rsvd0[6];
  81
  82         u16     func_idx;
  83         u16     rx_buf_sz;
  84
  85         u32     rsvd1;
  86 };
  87
  88 struct hinic_cmd_hw_ioctxt {
  89         u8      status;
  90         u8      version;
  91         u8      rsvd0[6];
  92
  93         u16     func_idx;
  94
  95         u16     rsvd1;
  96
  97         u8      set_cmdq_depth;
  98         u8      cmdq_depth;
  99
 100         u8      rsvd2;
 101         u8      rsvd3;
 102         u8      rsvd4;
 103         u8      rsvd5;
 104
 105         u16     rq_depth;
 106         u16     rx_buf_sz_idx;
 107         u16     sq_depth;
 108 };
 109
 110 struct hinic_cmd_io_status {
 111         u8      status;
 112         u8      version;
 113         u8      rsvd0[6];
 114
 115         u16     func_idx;
 116         u8      rsvd1;
 117         u8      rsvd2;
 118         u32     io_status;
 119 };
 120
 121 struct hinic_cmd_clear_io_res {
 122         u8      status;
 123         u8      version;
 124         u8      rsvd0[6];
 125
 126         u16     func_idx;
 127         u8      rsvd1;
 128         u8      rsvd2;
 129 };
 130
 131 struct hinic_cmd_set_res_state {
 132         u8      status;
 133         u8      version;
 134         u8      rsvd0[6];
 135
 136         u16     func_idx;
 137         u8      state;
 138         u8      rsvd1;
 139         u32     rsvd2;
 140 };
 141
 142 struct hinic_cmd_base_qpn {
 143         u8      status;
 144         u8      version;
 145         u8      rsvd0[6];
 146
 147         u16     func_idx;
 148         u16     qpn;
 149 };
 150
 151 struct hinic_cmd_hw_ci {
 152         u8      status;
 153         u8      version;
 154         u8      rsvd0[6];
 155
 156         u16     func_idx;
 157
 158         u8      dma_attr_off;
 159         u8      pending_limit;
 160         u8      coalesc_timer;
 161
 162         u8      msix_en;
 163         u16     msix_entry_idx;
 164
 165         u32     sq_id;
 166         u32     rsvd1;
 167         u64     ci_addr;
 168 };
 169
 170 struct hinic_hwdev {
 171         struct hinic_hwif               *hwif;
 172         struct msix_entry               *msix_entries;
 173
 174         struct hinic_aeqs               aeqs;
 175         struct hinic_func_to_io         func_to_io;
 176
 177         struct hinic_cap                nic_cap;
 178 };
 179
 180 struct hinic_nic_cb {
 181         void    (*handler)(void *handle, void *buf_in,
 182                            u16 in_size, void *buf_out,
 183                            u16 *out_size);
 184
 185         void            *handle;
 186         unsigned long   cb_state;
 187 };
 188
 189 struct hinic_pfhwdev {
 190         struct hinic_hwdev              hwdev;
 191
 192         struct hinic_pf_to_mgmt         pf_to_mgmt;
 193
 194         struct hinic_nic_cb             nic_cb[HINIC_MGMT_NUM_MSG_CMD];
 195 };
 196
 197 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
 198                              enum hinic_mgmt_msg_cmd cmd, void *handle,
 199                              void (*handler)(void *handle, void *buf_in,
 200                                              u16 in_size, void *buf_out,
 201                                              u16 *out_size));
 202
 203 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
 204                                enum hinic_mgmt_msg_cmd cmd);
 205
 206 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
 207                        void *buf_in, u16 in_size, void *buf_out,
 208                        u16 *out_size);
 209
 210 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev);
 211
 212 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);
 213
 214 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev);
 215
 216 void hinic_free_hwdev(struct hinic_hwdev *hwdev);
 217
 218 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);
 219
 220 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);
 221
 222 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);
 223
 224 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);
 225
 226 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
 227                          u8 pending_limit, u8 coalesc_timer,
 228                          u8 lli_timer_cfg, u8 lli_credit_limit,
 229                          u8 resend_timer);
 230
 231 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
 232                                u8 pending_limit, u8 coalesc_timer);
 233
 234 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
 235                                 enum hinic_msix_state flag);
 236
 237 #endif