drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h

   1 /*
   2  * Huawei HiNIC PCI Express Linux driver
   3  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  */
  15
  16 #ifndef HINIC_HW_DEV_H
  17 #define HINIC_HW_DEV_H
  18
  19 #include <linux/pci.h>
  20 #include <linux/types.h>
  21 #include <linux/bitops.h>
  22
  23 #include "hinic_hw_if.h"
  24 #include "hinic_hw_eqs.h"
  25 #include "hinic_hw_mgmt.h"
  26 #include "hinic_hw_qp.h"
  27 #include "hinic_hw_io.h"
  28
  29 #define HINIC_MAX_QPS   32
  30
  31 #define HINIC_MGMT_NUM_MSG_CMD  (HINIC_MGMT_MSG_CMD_MAX - \
  32                                  HINIC_MGMT_MSG_CMD_BASE)
  33
  34 struct hinic_cap {
  35         u16     max_qps;
  36         u16     num_qps;
  37 };
  38
  39 enum hinic_port_cmd {
  40         HINIC_PORT_CMD_CHANGE_MTU       = 2,
  41
  42         HINIC_PORT_CMD_ADD_VLAN         = 3,
  43         HINIC_PORT_CMD_DEL_VLAN         = 4,
  44
  45         HINIC_PORT_CMD_SET_MAC          = 9,
  46         HINIC_PORT_CMD_GET_MAC          = 10,
  47         HINIC_PORT_CMD_DEL_MAC          = 11,
  48
  49         HINIC_PORT_CMD_SET_RX_MODE      = 12,
  50
  51         HINIC_PORT_CMD_GET_LINK_STATE   = 24,
  52
  53         HINIC_PORT_CMD_SET_RX_CSUM      = 26,
  54
  55         HINIC_PORT_CMD_SET_PORT_STATE   = 41,
  56
  57         HINIC_PORT_CMD_FWCTXT_INIT      = 69,
  58
  59         HINIC_PORT_CMD_SET_FUNC_STATE   = 93,
  60
  61         HINIC_PORT_CMD_GET_GLOBAL_QPN   = 102,
  62
  63         HINIC_PORT_CMD_SET_TSO          = 112,
  64
  65         HINIC_PORT_CMD_GET_CAP          = 170,
  66 };
  67
  68 enum hinic_mgmt_msg_cmd {
  69         HINIC_MGMT_MSG_CMD_BASE         = 160,
  70
  71         HINIC_MGMT_MSG_CMD_LINK_STATUS  = 160,
  72
  73         HINIC_MGMT_MSG_CMD_MAX,
  74 };
  75
  76 enum hinic_cb_state {
  77         HINIC_CB_ENABLED = BIT(0),
  78         HINIC_CB_RUNNING = BIT(1),
  79 };
  80
  81 enum hinic_res_state {
  82         HINIC_RES_CLEAN         = 0,
  83         HINIC_RES_ACTIVE        = 1,
  84 };
  85
  86 struct hinic_cmd_fw_ctxt {
  87         u8      status;
  88         u8      version;
  89         u8      rsvd0[6];
  90
  91         u16     func_idx;
  92         u16     rx_buf_sz;
  93
  94         u32     rsvd1;
  95 };
  96
  97 struct hinic_cmd_hw_ioctxt {
  98         u8      status;
  99         u8      version;
 100         u8      rsvd0[6];
 101
 102         u16     func_idx;
 103
 104         u16     rsvd1;
 105
 106         u8      set_cmdq_depth;
 107         u8      cmdq_depth;
 108
 109         u8      rsvd2;
 110         u8      rsvd3;
 111         u8      rsvd4;
 112         u8      rsvd5;
 113
 114         u16     rq_depth;
 115         u16     rx_buf_sz_idx;
 116         u16     sq_depth;
 117 };
 118
 119 struct hinic_cmd_io_status {
 120         u8      status;
 121         u8      version;
 122         u8      rsvd0[6];
 123
 124         u16     func_idx;
 125         u8      rsvd1;
 126         u8      rsvd2;
 127         u32     io_status;
 128 };
 129
 130 struct hinic_cmd_clear_io_res {
 131         u8      status;
 132         u8      version;
 133         u8      rsvd0[6];
 134
 135         u16     func_idx;
 136         u8      rsvd1;
 137         u8      rsvd2;
 138 };
 139
 140 struct hinic_cmd_set_res_state {
 141         u8      status;
 142         u8      version;
 143         u8      rsvd0[6];
 144
 145         u16     func_idx;
 146         u8      state;
 147         u8      rsvd1;
 148         u32     rsvd2;
 149 };
 150
 151 struct hinic_cmd_base_qpn {
 152         u8      status;
 153         u8      version;
 154         u8      rsvd0[6];
 155
 156         u16     func_idx;
 157         u16     qpn;
 158 };
 159
 160 struct hinic_cmd_hw_ci {
 161         u8      status;
 162         u8      version;
 163         u8      rsvd0[6];
 164
 165         u16     func_idx;
 166
 167         u8      dma_attr_off;
 168         u8      pending_limit;
 169         u8      coalesc_timer;
 170
 171         u8      msix_en;
 172         u16     msix_entry_idx;
 173
 174         u32     sq_id;
 175         u32     rsvd1;
 176         u64     ci_addr;
 177 };
 178
 179 struct hinic_hwdev {
 180         struct hinic_hwif               *hwif;
 181         struct msix_entry               *msix_entries;
 182
 183         struct hinic_aeqs               aeqs;
 184         struct hinic_func_to_io         func_to_io;
 185
 186         struct hinic_cap                nic_cap;
 187 };
 188
 189 struct hinic_nic_cb {
 190         void    (*handler)(void *handle, void *buf_in,
 191                            u16 in_size, void *buf_out,
 192                            u16 *out_size);
 193
 194         void            *handle;
 195         unsigned long   cb_state;
 196 };
 197
 198 struct hinic_pfhwdev {
 199         struct hinic_hwdev              hwdev;
 200
 201         struct hinic_pf_to_mgmt         pf_to_mgmt;
 202
 203         struct hinic_nic_cb             nic_cb[HINIC_MGMT_NUM_MSG_CMD];
 204 };
 205
 206 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
 207                              enum hinic_mgmt_msg_cmd cmd, void *handle,
 208                              void (*handler)(void *handle, void *buf_in,
 209                                              u16 in_size, void *buf_out,
 210                                              u16 *out_size));
 211
 212 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
 213                                enum hinic_mgmt_msg_cmd cmd);
 214
 215 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
 216                        void *buf_in, u16 in_size, void *buf_out,
 217                        u16 *out_size);
 218
 219 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev);
 220
 221 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);
 222
 223 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev);
 224
 225 void hinic_free_hwdev(struct hinic_hwdev *hwdev);
 226
 227 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);
 228
 229 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);
 230
 231 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);
 232
 233 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);
 234
 235 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
 236                          u8 pending_limit, u8 coalesc_timer,
 237                          u8 lli_timer_cfg, u8 lli_credit_limit,
 238                          u8 resend_timer);
 239
 240 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
 241                                u8 pending_limit, u8 coalesc_timer);
 242
 243 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
 244                                 enum hinic_msix_state flag);
 245
 246 #endif