1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
12 #define E1000_DEV_ID_82571EB_COPPER 0x105E
13 #define E1000_DEV_ID_82571EB_FIBER 0x105F
14 #define E1000_DEV_ID_82571EB_SERDES 0x1060
15 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
16 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
17 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
19 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
20 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
21 #define E1000_DEV_ID_82572EI_COPPER 0x107D
22 #define E1000_DEV_ID_82572EI_FIBER 0x107E
23 #define E1000_DEV_ID_82572EI_SERDES 0x107F
24 #define E1000_DEV_ID_82572EI 0x10B9
25 #define E1000_DEV_ID_82573E 0x108B
26 #define E1000_DEV_ID_82573E_IAMT 0x108C
27 #define E1000_DEV_ID_82573L 0x109A
28 #define E1000_DEV_ID_82574L 0x10D3
29 #define E1000_DEV_ID_82574LA 0x10F6
30 #define E1000_DEV_ID_82583V 0x150C
31 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
32 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
33 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
34 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
35 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
36 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
37 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
38 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
39 #define E1000_DEV_ID_ICH8_IFE 0x104C
40 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
41 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
42 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
43 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
44 #define E1000_DEV_ID_ICH9_BM 0x10E5
45 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
46 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
47 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
48 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
49 #define E1000_DEV_ID_ICH9_IFE 0x10C0
50 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
51 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
52 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
53 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
54 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
55 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
56 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
57 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
58 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
59 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
60 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
61 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
62 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
63 #define E1000_DEV_ID_PCH2_LV_V 0x1503
64 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
65 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
66 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
67 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
68 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
69 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
70 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
71 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
72 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
73 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
74 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
75 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
76 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */
77 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
78 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
79 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
80 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
81 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
82 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
83 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
84 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
85 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF
86 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
87 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
88 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
89 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E
90 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F
91 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C
92 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D
93 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53
94 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55
95 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB
96 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC
97 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9
98 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA
99 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4
100 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5
101 #define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5
102 #define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6
103 #define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E
104 #define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F
105 #define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C
106 #define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D
107 #define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7
108 #define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8
109 #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A
110 #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B
111 #define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C
112 #define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D
113 #define E1000_DEV_ID_PCH_LNP_I219_LM20 0x550E
114 #define E1000_DEV_ID_PCH_LNP_I219_V20 0x550F
115 #define E1000_DEV_ID_PCH_LNP_I219_LM21 0x5510
116 #define E1000_DEV_ID_PCH_LNP_I219_V21 0x5511
118 #define E1000_REVISION_4 4
120 #define E1000_FUNC_1 1
122 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
123 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
125 enum e1000_mac_type
{
146 enum e1000_media_type
{
147 e1000_media_type_unknown
= 0,
148 e1000_media_type_copper
= 1,
149 e1000_media_type_fiber
= 2,
150 e1000_media_type_internal_serdes
= 3,
151 e1000_num_media_types
154 enum e1000_nvm_type
{
155 e1000_nvm_unknown
= 0,
157 e1000_nvm_eeprom_spi
,
162 enum e1000_nvm_override
{
163 e1000_nvm_override_none
= 0,
164 e1000_nvm_override_spi_small
,
165 e1000_nvm_override_spi_large
168 enum e1000_phy_type
{
169 e1000_phy_unknown
= 0,
184 enum e1000_bus_width
{
185 e1000_bus_width_unknown
= 0,
186 e1000_bus_width_pcie_x1
,
187 e1000_bus_width_pcie_x2
,
188 e1000_bus_width_pcie_x4
= 4,
189 e1000_bus_width_pcie_x8
= 8,
192 e1000_bus_width_reserved
195 enum e1000_1000t_rx_status
{
196 e1000_1000t_rx_status_not_ok
= 0,
197 e1000_1000t_rx_status_ok
,
198 e1000_1000t_rx_status_undefined
= 0xFF
201 enum e1000_rev_polarity
{
202 e1000_rev_polarity_normal
= 0,
203 e1000_rev_polarity_reversed
,
204 e1000_rev_polarity_undefined
= 0xFF
212 e1000_fc_default
= 0xFF
216 e1000_ms_hw_default
= 0,
217 e1000_ms_force_master
,
218 e1000_ms_force_slave
,
222 enum e1000_smart_speed
{
223 e1000_smart_speed_default
= 0,
224 e1000_smart_speed_on
,
225 e1000_smart_speed_off
228 enum e1000_serdes_link_state
{
229 e1000_serdes_link_down
= 0,
230 e1000_serdes_link_autoneg_progress
,
231 e1000_serdes_link_autoneg_complete
,
232 e1000_serdes_link_forced_up
235 /* Receive Descriptor - Extended */
236 union e1000_rx_desc_extended
{
243 __le32 mrq
; /* Multiple Rx Queues */
245 __le32 rss
; /* RSS Hash */
247 __le16 ip_id
; /* IP id */
248 __le16 csum
; /* Packet Checksum */
253 __le32 status_error
; /* ext status/error */
255 __le16 vlan
; /* VLAN tag */
257 } wb
; /* writeback */
260 #define MAX_PS_BUFFERS 4
262 /* Number of packet split data buffers (not including the header buffer) */
263 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
265 /* Receive Descriptor - Packet Split */
266 union e1000_rx_desc_packet_split
{
268 /* one buffer for protocol header(s), three data buffers */
269 __le64 buffer_addr
[MAX_PS_BUFFERS
];
273 __le32 mrq
; /* Multiple Rx Queues */
275 __le32 rss
; /* RSS Hash */
277 __le16 ip_id
; /* IP id */
278 __le16 csum
; /* Packet Checksum */
283 __le32 status_error
; /* ext status/error */
284 __le16 length0
; /* length of buffer 0 */
285 __le16 vlan
; /* VLAN tag */
288 __le16 header_status
;
289 /* length of buffers 1-3 */
290 __le16 length
[PS_PAGE_BUFFERS
];
293 } wb
; /* writeback */
296 /* Transmit Descriptor */
297 struct e1000_tx_desc
{
298 __le64 buffer_addr
; /* Address of the descriptor's data buffer */
302 __le16 length
; /* Data buffer length */
303 u8 cso
; /* Checksum offset */
304 u8 cmd
; /* Descriptor control */
310 u8 status
; /* Descriptor status */
311 u8 css
; /* Checksum start */
317 /* Offload Context Descriptor */
318 struct e1000_context_desc
{
322 u8 ipcss
; /* IP checksum start */
323 u8 ipcso
; /* IP checksum offset */
324 __le16 ipcse
; /* IP checksum end */
330 u8 tucss
; /* TCP checksum start */
331 u8 tucso
; /* TCP checksum offset */
332 __le16 tucse
; /* TCP checksum end */
335 __le32 cmd_and_length
;
339 u8 status
; /* Descriptor status */
340 u8 hdr_len
; /* Header length */
341 __le16 mss
; /* Maximum segment size */
346 /* Offload data descriptor */
347 struct e1000_data_desc
{
348 __le64 buffer_addr
; /* Address of the descriptor's buffer address */
352 __le16 length
; /* Data buffer length */
360 u8 status
; /* Descriptor status */
361 u8 popts
; /* Packet Options */
367 /* Statistics counters collected by the MAC */
368 struct e1000_hw_stats
{
434 struct e1000_phy_stats
{
439 struct e1000_host_mng_dhcp_cookie
{
450 /* Host Interface "Rev 1" */
451 struct e1000_host_command_header
{
458 #define E1000_HI_MAX_DATA_LENGTH 252
459 struct e1000_host_command_info
{
460 struct e1000_host_command_header command_header
;
461 u8 command_data
[E1000_HI_MAX_DATA_LENGTH
];
464 /* Host Interface "Rev 2" */
465 struct e1000_host_mng_command_header
{
473 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
474 struct e1000_host_mng_command_info
{
475 struct e1000_host_mng_command_header command_header
;
476 u8 command_data
[E1000_HI_MAX_MNG_DATA_LENGTH
];
484 /* Function pointers for the MAC. */
485 struct e1000_mac_operations
{
486 s32 (*id_led_init
)(struct e1000_hw
*);
487 s32 (*blink_led
)(struct e1000_hw
*);
488 bool (*check_mng_mode
)(struct e1000_hw
*);
489 s32 (*check_for_link
)(struct e1000_hw
*);
490 s32 (*cleanup_led
)(struct e1000_hw
*);
491 void (*clear_hw_cntrs
)(struct e1000_hw
*);
492 void (*clear_vfta
)(struct e1000_hw
*);
493 s32 (*get_bus_info
)(struct e1000_hw
*);
494 void (*set_lan_id
)(struct e1000_hw
*);
495 s32 (*get_link_up_info
)(struct e1000_hw
*, u16
*, u16
*);
496 s32 (*led_on
)(struct e1000_hw
*);
497 s32 (*led_off
)(struct e1000_hw
*);
498 void (*update_mc_addr_list
)(struct e1000_hw
*, u8
*, u32
);
499 s32 (*reset_hw
)(struct e1000_hw
*);
500 s32 (*init_hw
)(struct e1000_hw
*);
501 s32 (*setup_link
)(struct e1000_hw
*);
502 s32 (*setup_physical_interface
)(struct e1000_hw
*);
503 s32 (*setup_led
)(struct e1000_hw
*);
504 void (*write_vfta
)(struct e1000_hw
*, u32
, u32
);
505 void (*config_collision_dist
)(struct e1000_hw
*);
506 int (*rar_set
)(struct e1000_hw
*, u8
*, u32
);
507 s32 (*read_mac_addr
)(struct e1000_hw
*);
508 u32 (*rar_get_count
)(struct e1000_hw
*);
511 /* When to use various PHY register access functions:
514 * Function Does Does When to use
515 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
516 * X_reg L,P,A n/a for simple PHY reg accesses
517 * X_reg_locked P,A L for multiple accesses of different regs
519 * X_reg_page A L,P for multiple accesses of different regs
522 * Where X=[read|write], L=locking, P=sets page, A=register access
525 struct e1000_phy_operations
{
526 s32 (*acquire
)(struct e1000_hw
*);
527 s32 (*cfg_on_link_up
)(struct e1000_hw
*);
528 s32 (*check_polarity
)(struct e1000_hw
*);
529 s32 (*check_reset_block
)(struct e1000_hw
*);
530 s32 (*commit
)(struct e1000_hw
*);
531 s32 (*force_speed_duplex
)(struct e1000_hw
*);
532 s32 (*get_cfg_done
)(struct e1000_hw
*hw
);
533 s32 (*get_cable_length
)(struct e1000_hw
*);
534 s32 (*get_info
)(struct e1000_hw
*);
535 s32 (*set_page
)(struct e1000_hw
*, u16
);
536 s32 (*read_reg
)(struct e1000_hw
*, u32
, u16
*);
537 s32 (*read_reg_locked
)(struct e1000_hw
*, u32
, u16
*);
538 s32 (*read_reg_page
)(struct e1000_hw
*, u32
, u16
*);
539 void (*release
)(struct e1000_hw
*);
540 s32 (*reset
)(struct e1000_hw
*);
541 s32 (*set_d0_lplu_state
)(struct e1000_hw
*, bool);
542 s32 (*set_d3_lplu_state
)(struct e1000_hw
*, bool);
543 s32 (*write_reg
)(struct e1000_hw
*, u32
, u16
);
544 s32 (*write_reg_locked
)(struct e1000_hw
*, u32
, u16
);
545 s32 (*write_reg_page
)(struct e1000_hw
*, u32
, u16
);
546 void (*power_up
)(struct e1000_hw
*);
547 void (*power_down
)(struct e1000_hw
*);
550 /* Function pointers for the NVM. */
551 struct e1000_nvm_operations
{
552 s32 (*acquire
)(struct e1000_hw
*);
553 s32 (*read
)(struct e1000_hw
*, u16
, u16
, u16
*);
554 void (*release
)(struct e1000_hw
*);
555 void (*reload
)(struct e1000_hw
*);
556 s32 (*update
)(struct e1000_hw
*);
557 s32 (*valid_led_default
)(struct e1000_hw
*, u16
*);
558 s32 (*validate
)(struct e1000_hw
*);
559 s32 (*write
)(struct e1000_hw
*, u16
, u16
, u16
*);
562 struct e1000_mac_info
{
563 struct e1000_mac_operations ops
;
565 u8 perm_addr
[ETH_ALEN
];
567 enum e1000_mac_type type
;
584 /* Maximum size of the MTA register table in all supported adapters */
585 #define MAX_MTA_REG 128
586 u32 mta_shadow
[MAX_MTA_REG
];
589 u8 forced_speed_duplex
;
593 bool arc_subsystem_valid
;
596 bool get_link_status
;
598 bool serdes_has_link
;
599 bool tx_pkt_filtering
;
600 enum e1000_serdes_link_state serdes_link_state
;
603 struct e1000_phy_info
{
604 struct e1000_phy_operations ops
;
606 enum e1000_phy_type type
;
608 enum e1000_1000t_rx_status local_rx
;
609 enum e1000_1000t_rx_status remote_rx
;
610 enum e1000_ms_type ms_type
;
611 enum e1000_ms_type original_ms_type
;
612 enum e1000_rev_polarity cable_polarity
;
613 enum e1000_smart_speed smart_speed
;
617 u32 reset_delay_us
; /* in usec */
620 enum e1000_media_type media_type
;
622 u16 autoneg_advertised
;
625 u16 max_cable_length
;
626 u16 min_cable_length
;
630 bool disable_polarity_correction
;
632 bool polarity_correction
;
633 bool speed_downgraded
;
634 bool autoneg_wait_to_complete
;
637 struct e1000_nvm_info
{
638 struct e1000_nvm_operations ops
;
640 enum e1000_nvm_type type
;
641 enum e1000_nvm_override override
;
653 struct e1000_bus_info
{
654 enum e1000_bus_width width
;
659 struct e1000_fc_info
{
660 u32 high_water
; /* Flow control high-water mark */
661 u32 low_water
; /* Flow control low-water mark */
662 u16 pause_time
; /* Flow control pause timer */
663 u16 refresh_time
; /* Flow control refresh timer */
664 bool send_xon
; /* Flow control send XON */
665 bool strict_ieee
; /* Strict IEEE mode */
666 enum e1000_fc_mode current_mode
; /* FC mode in effect */
667 enum e1000_fc_mode requested_mode
; /* FC mode requested by caller */
670 struct e1000_dev_spec_82571
{
675 struct e1000_dev_spec_80003es2lan
{
679 struct e1000_shadow_ram
{
684 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
686 /* I218 PHY Ultra Low Power (ULP) states */
687 enum e1000_ulp_state
{
688 e1000_ulp_state_unknown
,
693 struct e1000_dev_spec_ich8lan
{
694 bool kmrn_lock_loss_workaround_enabled
;
695 struct e1000_shadow_ram shadow_ram
[E1000_ICH8_SHADOW_RAM_WORDS
];
699 enum e1000_ulp_state ulp_state
;
703 struct e1000_adapter
*adapter
;
705 void __iomem
*hw_addr
;
706 void __iomem
*flash_address
;
708 struct e1000_mac_info mac
;
709 struct e1000_fc_info fc
;
710 struct e1000_phy_info phy
;
711 struct e1000_nvm_info nvm
;
712 struct e1000_bus_info bus
;
713 struct e1000_host_mng_dhcp_cookie mng_cookie
;
716 struct e1000_dev_spec_82571 e82571
;
717 struct e1000_dev_spec_80003es2lan e80003es2lan
;
718 struct e1000_dev_spec_ich8lan ich8lan
;
723 #include "80003es2lan.h"
726 #endif /* _E1000E_HW_H_ */