1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
12 #define E1000_DEV_ID_82571EB_COPPER 0x105E
13 #define E1000_DEV_ID_82571EB_FIBER 0x105F
14 #define E1000_DEV_ID_82571EB_SERDES 0x1060
15 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
16 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
17 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
19 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
20 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
21 #define E1000_DEV_ID_82572EI_COPPER 0x107D
22 #define E1000_DEV_ID_82572EI_FIBER 0x107E
23 #define E1000_DEV_ID_82572EI_SERDES 0x107F
24 #define E1000_DEV_ID_82572EI 0x10B9
25 #define E1000_DEV_ID_82573E 0x108B
26 #define E1000_DEV_ID_82573E_IAMT 0x108C
27 #define E1000_DEV_ID_82573L 0x109A
28 #define E1000_DEV_ID_82574L 0x10D3
29 #define E1000_DEV_ID_82574LA 0x10F6
30 #define E1000_DEV_ID_82583V 0x150C
31 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
32 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
33 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
34 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
35 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
36 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
37 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
38 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
39 #define E1000_DEV_ID_ICH8_IFE 0x104C
40 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
41 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
42 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
43 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
44 #define E1000_DEV_ID_ICH9_BM 0x10E5
45 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
46 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
47 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
48 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
49 #define E1000_DEV_ID_ICH9_IFE 0x10C0
50 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
51 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
52 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
53 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
54 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
55 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
56 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
57 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
58 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
59 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
60 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
61 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
62 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
63 #define E1000_DEV_ID_PCH2_LV_V 0x1503
64 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
65 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
66 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
67 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
68 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
69 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
70 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
71 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
72 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
73 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
74 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
75 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
76 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */
77 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
78 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
79 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
80 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
81 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
82 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
83 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
84 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
85 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF
86 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
87 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
88 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
89 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E
90 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F
91 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C
92 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D
93 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53
94 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55
95 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB
96 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC
97 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9
98 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA
99 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4
101 #define E1000_REVISION_4 4
103 #define E1000_FUNC_1 1
105 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
106 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
108 enum e1000_mac_type
{
126 enum e1000_media_type
{
127 e1000_media_type_unknown
= 0,
128 e1000_media_type_copper
= 1,
129 e1000_media_type_fiber
= 2,
130 e1000_media_type_internal_serdes
= 3,
131 e1000_num_media_types
134 enum e1000_nvm_type
{
135 e1000_nvm_unknown
= 0,
137 e1000_nvm_eeprom_spi
,
142 enum e1000_nvm_override
{
143 e1000_nvm_override_none
= 0,
144 e1000_nvm_override_spi_small
,
145 e1000_nvm_override_spi_large
148 enum e1000_phy_type
{
149 e1000_phy_unknown
= 0,
164 enum e1000_bus_width
{
165 e1000_bus_width_unknown
= 0,
166 e1000_bus_width_pcie_x1
,
167 e1000_bus_width_pcie_x2
,
168 e1000_bus_width_pcie_x4
= 4,
169 e1000_bus_width_pcie_x8
= 8,
172 e1000_bus_width_reserved
175 enum e1000_1000t_rx_status
{
176 e1000_1000t_rx_status_not_ok
= 0,
177 e1000_1000t_rx_status_ok
,
178 e1000_1000t_rx_status_undefined
= 0xFF
181 enum e1000_rev_polarity
{
182 e1000_rev_polarity_normal
= 0,
183 e1000_rev_polarity_reversed
,
184 e1000_rev_polarity_undefined
= 0xFF
192 e1000_fc_default
= 0xFF
196 e1000_ms_hw_default
= 0,
197 e1000_ms_force_master
,
198 e1000_ms_force_slave
,
202 enum e1000_smart_speed
{
203 e1000_smart_speed_default
= 0,
204 e1000_smart_speed_on
,
205 e1000_smart_speed_off
208 enum e1000_serdes_link_state
{
209 e1000_serdes_link_down
= 0,
210 e1000_serdes_link_autoneg_progress
,
211 e1000_serdes_link_autoneg_complete
,
212 e1000_serdes_link_forced_up
215 /* Receive Descriptor - Extended */
216 union e1000_rx_desc_extended
{
223 __le32 mrq
; /* Multiple Rx Queues */
225 __le32 rss
; /* RSS Hash */
227 __le16 ip_id
; /* IP id */
228 __le16 csum
; /* Packet Checksum */
233 __le32 status_error
; /* ext status/error */
235 __le16 vlan
; /* VLAN tag */
237 } wb
; /* writeback */
240 #define MAX_PS_BUFFERS 4
242 /* Number of packet split data buffers (not including the header buffer) */
243 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
245 /* Receive Descriptor - Packet Split */
246 union e1000_rx_desc_packet_split
{
248 /* one buffer for protocol header(s), three data buffers */
249 __le64 buffer_addr
[MAX_PS_BUFFERS
];
253 __le32 mrq
; /* Multiple Rx Queues */
255 __le32 rss
; /* RSS Hash */
257 __le16 ip_id
; /* IP id */
258 __le16 csum
; /* Packet Checksum */
263 __le32 status_error
; /* ext status/error */
264 __le16 length0
; /* length of buffer 0 */
265 __le16 vlan
; /* VLAN tag */
268 __le16 header_status
;
269 /* length of buffers 1-3 */
270 __le16 length
[PS_PAGE_BUFFERS
];
273 } wb
; /* writeback */
276 /* Transmit Descriptor */
277 struct e1000_tx_desc
{
278 __le64 buffer_addr
; /* Address of the descriptor's data buffer */
282 __le16 length
; /* Data buffer length */
283 u8 cso
; /* Checksum offset */
284 u8 cmd
; /* Descriptor control */
290 u8 status
; /* Descriptor status */
291 u8 css
; /* Checksum start */
297 /* Offload Context Descriptor */
298 struct e1000_context_desc
{
302 u8 ipcss
; /* IP checksum start */
303 u8 ipcso
; /* IP checksum offset */
304 __le16 ipcse
; /* IP checksum end */
310 u8 tucss
; /* TCP checksum start */
311 u8 tucso
; /* TCP checksum offset */
312 __le16 tucse
; /* TCP checksum end */
315 __le32 cmd_and_length
;
319 u8 status
; /* Descriptor status */
320 u8 hdr_len
; /* Header length */
321 __le16 mss
; /* Maximum segment size */
326 /* Offload data descriptor */
327 struct e1000_data_desc
{
328 __le64 buffer_addr
; /* Address of the descriptor's buffer address */
332 __le16 length
; /* Data buffer length */
340 u8 status
; /* Descriptor status */
341 u8 popts
; /* Packet Options */
347 /* Statistics counters collected by the MAC */
348 struct e1000_hw_stats
{
414 struct e1000_phy_stats
{
419 struct e1000_host_mng_dhcp_cookie
{
430 /* Host Interface "Rev 1" */
431 struct e1000_host_command_header
{
438 #define E1000_HI_MAX_DATA_LENGTH 252
439 struct e1000_host_command_info
{
440 struct e1000_host_command_header command_header
;
441 u8 command_data
[E1000_HI_MAX_DATA_LENGTH
];
444 /* Host Interface "Rev 2" */
445 struct e1000_host_mng_command_header
{
453 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
454 struct e1000_host_mng_command_info
{
455 struct e1000_host_mng_command_header command_header
;
456 u8 command_data
[E1000_HI_MAX_MNG_DATA_LENGTH
];
464 /* Function pointers for the MAC. */
465 struct e1000_mac_operations
{
466 s32 (*id_led_init
)(struct e1000_hw
*);
467 s32 (*blink_led
)(struct e1000_hw
*);
468 bool (*check_mng_mode
)(struct e1000_hw
*);
469 s32 (*check_for_link
)(struct e1000_hw
*);
470 s32 (*cleanup_led
)(struct e1000_hw
*);
471 void (*clear_hw_cntrs
)(struct e1000_hw
*);
472 void (*clear_vfta
)(struct e1000_hw
*);
473 s32 (*get_bus_info
)(struct e1000_hw
*);
474 void (*set_lan_id
)(struct e1000_hw
*);
475 s32 (*get_link_up_info
)(struct e1000_hw
*, u16
*, u16
*);
476 s32 (*led_on
)(struct e1000_hw
*);
477 s32 (*led_off
)(struct e1000_hw
*);
478 void (*update_mc_addr_list
)(struct e1000_hw
*, u8
*, u32
);
479 s32 (*reset_hw
)(struct e1000_hw
*);
480 s32 (*init_hw
)(struct e1000_hw
*);
481 s32 (*setup_link
)(struct e1000_hw
*);
482 s32 (*setup_physical_interface
)(struct e1000_hw
*);
483 s32 (*setup_led
)(struct e1000_hw
*);
484 void (*write_vfta
)(struct e1000_hw
*, u32
, u32
);
485 void (*config_collision_dist
)(struct e1000_hw
*);
486 int (*rar_set
)(struct e1000_hw
*, u8
*, u32
);
487 s32 (*read_mac_addr
)(struct e1000_hw
*);
488 u32 (*rar_get_count
)(struct e1000_hw
*);
491 /* When to use various PHY register access functions:
494 * Function Does Does When to use
495 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
496 * X_reg L,P,A n/a for simple PHY reg accesses
497 * X_reg_locked P,A L for multiple accesses of different regs
499 * X_reg_page A L,P for multiple accesses of different regs
502 * Where X=[read|write], L=locking, P=sets page, A=register access
505 struct e1000_phy_operations
{
506 s32 (*acquire
)(struct e1000_hw
*);
507 s32 (*cfg_on_link_up
)(struct e1000_hw
*);
508 s32 (*check_polarity
)(struct e1000_hw
*);
509 s32 (*check_reset_block
)(struct e1000_hw
*);
510 s32 (*commit
)(struct e1000_hw
*);
511 s32 (*force_speed_duplex
)(struct e1000_hw
*);
512 s32 (*get_cfg_done
)(struct e1000_hw
*hw
);
513 s32 (*get_cable_length
)(struct e1000_hw
*);
514 s32 (*get_info
)(struct e1000_hw
*);
515 s32 (*set_page
)(struct e1000_hw
*, u16
);
516 s32 (*read_reg
)(struct e1000_hw
*, u32
, u16
*);
517 s32 (*read_reg_locked
)(struct e1000_hw
*, u32
, u16
*);
518 s32 (*read_reg_page
)(struct e1000_hw
*, u32
, u16
*);
519 void (*release
)(struct e1000_hw
*);
520 s32 (*reset
)(struct e1000_hw
*);
521 s32 (*set_d0_lplu_state
)(struct e1000_hw
*, bool);
522 s32 (*set_d3_lplu_state
)(struct e1000_hw
*, bool);
523 s32 (*write_reg
)(struct e1000_hw
*, u32
, u16
);
524 s32 (*write_reg_locked
)(struct e1000_hw
*, u32
, u16
);
525 s32 (*write_reg_page
)(struct e1000_hw
*, u32
, u16
);
526 void (*power_up
)(struct e1000_hw
*);
527 void (*power_down
)(struct e1000_hw
*);
530 /* Function pointers for the NVM. */
531 struct e1000_nvm_operations
{
532 s32 (*acquire
)(struct e1000_hw
*);
533 s32 (*read
)(struct e1000_hw
*, u16
, u16
, u16
*);
534 void (*release
)(struct e1000_hw
*);
535 void (*reload
)(struct e1000_hw
*);
536 s32 (*update
)(struct e1000_hw
*);
537 s32 (*valid_led_default
)(struct e1000_hw
*, u16
*);
538 s32 (*validate
)(struct e1000_hw
*);
539 s32 (*write
)(struct e1000_hw
*, u16
, u16
, u16
*);
542 struct e1000_mac_info
{
543 struct e1000_mac_operations ops
;
545 u8 perm_addr
[ETH_ALEN
];
547 enum e1000_mac_type type
;
564 /* Maximum size of the MTA register table in all supported adapters */
565 #define MAX_MTA_REG 128
566 u32 mta_shadow
[MAX_MTA_REG
];
569 u8 forced_speed_duplex
;
573 bool arc_subsystem_valid
;
576 bool get_link_status
;
578 bool serdes_has_link
;
579 bool tx_pkt_filtering
;
580 enum e1000_serdes_link_state serdes_link_state
;
583 struct e1000_phy_info
{
584 struct e1000_phy_operations ops
;
586 enum e1000_phy_type type
;
588 enum e1000_1000t_rx_status local_rx
;
589 enum e1000_1000t_rx_status remote_rx
;
590 enum e1000_ms_type ms_type
;
591 enum e1000_ms_type original_ms_type
;
592 enum e1000_rev_polarity cable_polarity
;
593 enum e1000_smart_speed smart_speed
;
597 u32 reset_delay_us
; /* in usec */
600 enum e1000_media_type media_type
;
602 u16 autoneg_advertised
;
605 u16 max_cable_length
;
606 u16 min_cable_length
;
610 bool disable_polarity_correction
;
612 bool polarity_correction
;
613 bool speed_downgraded
;
614 bool autoneg_wait_to_complete
;
617 struct e1000_nvm_info
{
618 struct e1000_nvm_operations ops
;
620 enum e1000_nvm_type type
;
621 enum e1000_nvm_override override
;
633 struct e1000_bus_info
{
634 enum e1000_bus_width width
;
639 struct e1000_fc_info
{
640 u32 high_water
; /* Flow control high-water mark */
641 u32 low_water
; /* Flow control low-water mark */
642 u16 pause_time
; /* Flow control pause timer */
643 u16 refresh_time
; /* Flow control refresh timer */
644 bool send_xon
; /* Flow control send XON */
645 bool strict_ieee
; /* Strict IEEE mode */
646 enum e1000_fc_mode current_mode
; /* FC mode in effect */
647 enum e1000_fc_mode requested_mode
; /* FC mode requested by caller */
650 struct e1000_dev_spec_82571
{
655 struct e1000_dev_spec_80003es2lan
{
659 struct e1000_shadow_ram
{
664 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
666 /* I218 PHY Ultra Low Power (ULP) states */
667 enum e1000_ulp_state
{
668 e1000_ulp_state_unknown
,
673 struct e1000_dev_spec_ich8lan
{
674 bool kmrn_lock_loss_workaround_enabled
;
675 struct e1000_shadow_ram shadow_ram
[E1000_ICH8_SHADOW_RAM_WORDS
];
679 enum e1000_ulp_state ulp_state
;
683 struct e1000_adapter
*adapter
;
685 void __iomem
*hw_addr
;
686 void __iomem
*flash_address
;
688 struct e1000_mac_info mac
;
689 struct e1000_fc_info fc
;
690 struct e1000_phy_info phy
;
691 struct e1000_nvm_info nvm
;
692 struct e1000_bus_info bus
;
693 struct e1000_host_mng_dhcp_cookie mng_cookie
;
696 struct e1000_dev_spec_82571 e82571
;
697 struct e1000_dev_spec_80003es2lan e80003es2lan
;
698 struct e1000_dev_spec_ich8lan ich8lan
;
703 #include "80003es2lan.h"