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e1000e: bump up timeout to wait when ME un-configures ULP mode
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
18 * 82567V Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
39 */
40
41 #include "e1000.h"
42
43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44 /* Offset 04h HSFSTS */
45 union ich8_hws_flash_status {
46 struct ich8_hsfsts {
47 u16 flcdone:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr:1; /* bit 1 Flash Cycle Error */
49 u16 dael:1; /* bit 2 Direct Access error Log */
50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1:2; /* bit 13:6 Reserved */
53 u16 reserved2:6; /* bit 13:6 Reserved */
54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
56 } hsf_status;
57 u16 regval;
58 };
59
60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61 /* Offset 06h FLCTL */
62 union ich8_hws_flash_ctrl {
63 struct ich8_hsflctl {
64 u16 flcgo:1; /* 0 Flash Cycle Go */
65 u16 flcycle:2; /* 2:1 Flash Cycle */
66 u16 reserved:5; /* 7:3 Reserved */
67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn:6; /* 15:10 Reserved */
69 } hsf_ctrl;
70 u16 regval;
71 };
72
73 /* ICH Flash Region Access Permissions */
74 union ich8_hws_flash_regacc {
75 struct ich8_flracc {
76 u32 grra:8; /* 0:7 GbE region Read Access */
77 u32 grwa:8; /* 8:15 GbE region Write Access */
78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
80 } hsf_flregacc;
81 u16 regval;
82 };
83
84 /* ICH Flash Protected Region */
85 union ich8_flash_protected_range {
86 struct ich8_pr {
87 u32 base:13; /* 0:12 Protected Range Base */
88 u32 reserved1:2; /* 13:14 Reserved */
89 u32 rpe:1; /* 15 Read Protection Enable */
90 u32 limit:13; /* 16:28 Protected Range Limit */
91 u32 reserved2:2; /* 29:30 Reserved */
92 u32 wpe:1; /* 31 Write Protection Enable */
93 } range;
94 u32 regval;
95 };
96
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 u32 offset, u8 byte);
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103 u8 *data);
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105 u16 *data);
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107 u8 size, u16 *data);
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109 u32 *data);
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 u32 offset, u32 *data);
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 u32 offset, u32 data);
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 u32 offset, u32 dword);
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140
141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142 {
143 return readw(hw->flash_address + reg);
144 }
145
146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147 {
148 return readl(hw->flash_address + reg);
149 }
150
151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152 {
153 writew(val, hw->flash_address + reg);
154 }
155
156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157 {
158 writel(val, hw->flash_address + reg);
159 }
160
161 #define er16flash(reg) __er16flash(hw, (reg))
162 #define er32flash(reg) __er32flash(hw, (reg))
163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
165
166 /**
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
169 *
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
173 *
174 * Assumes the sw/fw/hw semaphore is already acquired.
175 **/
176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177 {
178 u16 phy_reg = 0;
179 u32 phy_id = 0;
180 s32 ret_val = 0;
181 u16 retry_count;
182 u32 mac_reg = 0;
183
184 for (retry_count = 0; retry_count < 2; retry_count++) {
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
187 continue;
188 phy_id = (u32)(phy_reg << 16);
189
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
192 phy_id = 0;
193 continue;
194 }
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 break;
197 }
198
199 if (hw->phy.id) {
200 if (hw->phy.id == phy_id)
201 goto out;
202 } else if (phy_id) {
203 hw->phy.id = phy_id;
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205 goto out;
206 }
207
208 /* In case the PHY needs to be in mdio slow mode,
209 * set slow mode and try to get the PHY id again.
210 */
211 if (hw->mac.type < e1000_pch_lpt) {
212 hw->phy.ops.release(hw);
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
216 hw->phy.ops.acquire(hw);
217 }
218
219 if (ret_val)
220 return false;
221 out:
222 if (hw->mac.type >= e1000_pch_lpt) {
223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 /* Unforce SMBus mode in PHY */
226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
229
230 /* Unforce SMBus mode in MAC */
231 mac_reg = er32(CTRL_EXT);
232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233 ew32(CTRL_EXT, mac_reg);
234 }
235 }
236
237 return true;
238 }
239
240 /**
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242 * @hw: pointer to the HW structure
243 *
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245 * used to reset the PHY to a quiescent state when necessary.
246 **/
247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248 {
249 u32 mac_reg;
250
251 /* Set Phy Config Counter to 50msec */
252 mac_reg = er32(FEXTNVM3);
253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255 ew32(FEXTNVM3, mac_reg);
256
257 /* Toggle LANPHYPC Value bit */
258 mac_reg = er32(CTRL);
259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
261 ew32(CTRL, mac_reg);
262 e1e_flush();
263 usleep_range(10, 20);
264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
265 ew32(CTRL, mac_reg);
266 e1e_flush();
267
268 if (hw->mac.type < e1000_pch_lpt) {
269 msleep(50);
270 } else {
271 u16 count = 20;
272
273 do {
274 usleep_range(5000, 6000);
275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276
277 msleep(30);
278 }
279 }
280
281 /**
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
284 *
285 * Workarounds/flow necessary for PHY initialization during driver load
286 * and resume paths.
287 **/
288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
289 {
290 struct e1000_adapter *adapter = hw->adapter;
291 u32 mac_reg, fwsm = er32(FWSM);
292 s32 ret_val;
293
294 /* Gate automatic PHY configuration by hardware on managed and
295 * non-managed 82579 and newer adapters.
296 */
297 e1000_gate_hw_phy_config_ich8lan(hw, true);
298
299 /* It is not possible to be certain of the current state of ULP
300 * so forcibly disable it.
301 */
302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
304 if (ret_val)
305 e_warn("Failed to disable ULP\n");
306
307 ret_val = hw->phy.ops.acquire(hw);
308 if (ret_val) {
309 e_dbg("Failed to initialize PHY flow\n");
310 goto out;
311 }
312
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
316 */
317 switch (hw->mac.type) {
318 case e1000_pch_lpt:
319 case e1000_pch_spt:
320 case e1000_pch_cnp:
321 case e1000_pch_tgp:
322 case e1000_pch_adp:
323 case e1000_pch_mtp:
324 if (e1000_phy_is_accessible_pchlan(hw))
325 break;
326
327 /* Before toggling LANPHYPC, see if PHY is accessible by
328 * forcing MAC to SMBus mode first.
329 */
330 mac_reg = er32(CTRL_EXT);
331 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
332 ew32(CTRL_EXT, mac_reg);
333
334 /* Wait 50 milliseconds for MAC to finish any retries
335 * that it might be trying to perform from previous
336 * attempts to acknowledge any phy read requests.
337 */
338 msleep(50);
339
340 fallthrough;
341 case e1000_pch2lan:
342 if (e1000_phy_is_accessible_pchlan(hw))
343 break;
344
345 fallthrough;
346 case e1000_pchlan:
347 if ((hw->mac.type == e1000_pchlan) &&
348 (fwsm & E1000_ICH_FWSM_FW_VALID))
349 break;
350
351 if (hw->phy.ops.check_reset_block(hw)) {
352 e_dbg("Required LANPHYPC toggle blocked by ME\n");
353 ret_val = -E1000_ERR_PHY;
354 break;
355 }
356
357 /* Toggle LANPHYPC Value bit */
358 e1000_toggle_lanphypc_pch_lpt(hw);
359 if (hw->mac.type >= e1000_pch_lpt) {
360 if (e1000_phy_is_accessible_pchlan(hw))
361 break;
362
363 /* Toggling LANPHYPC brings the PHY out of SMBus mode
364 * so ensure that the MAC is also out of SMBus mode
365 */
366 mac_reg = er32(CTRL_EXT);
367 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
368 ew32(CTRL_EXT, mac_reg);
369
370 if (e1000_phy_is_accessible_pchlan(hw))
371 break;
372
373 ret_val = -E1000_ERR_PHY;
374 }
375 break;
376 default:
377 break;
378 }
379
380 hw->phy.ops.release(hw);
381 if (!ret_val) {
382
383 /* Check to see if able to reset PHY. Print error if not */
384 if (hw->phy.ops.check_reset_block(hw)) {
385 e_err("Reset blocked by ME\n");
386 goto out;
387 }
388
389 /* Reset the PHY before any access to it. Doing so, ensures
390 * that the PHY is in a known good state before we read/write
391 * PHY registers. The generic reset is sufficient here,
392 * because we haven't determined the PHY type yet.
393 */
394 ret_val = e1000e_phy_hw_reset_generic(hw);
395 if (ret_val)
396 goto out;
397
398 /* On a successful reset, possibly need to wait for the PHY
399 * to quiesce to an accessible state before returning control
400 * to the calling function. If the PHY does not quiesce, then
401 * return E1000E_BLK_PHY_RESET, as this is the condition that
402 * the PHY is in.
403 */
404 ret_val = hw->phy.ops.check_reset_block(hw);
405 if (ret_val)
406 e_err("ME blocked access to PHY after reset\n");
407 }
408
409 out:
410 /* Ungate automatic PHY configuration on non-managed 82579 */
411 if ((hw->mac.type == e1000_pch2lan) &&
412 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
413 usleep_range(10000, 11000);
414 e1000_gate_hw_phy_config_ich8lan(hw, false);
415 }
416
417 return ret_val;
418 }
419
420 /**
421 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
422 * @hw: pointer to the HW structure
423 *
424 * Initialize family-specific PHY parameters and function pointers.
425 **/
426 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
427 {
428 struct e1000_phy_info *phy = &hw->phy;
429 s32 ret_val;
430
431 phy->addr = 1;
432 phy->reset_delay_us = 100;
433
434 phy->ops.set_page = e1000_set_page_igp;
435 phy->ops.read_reg = e1000_read_phy_reg_hv;
436 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
437 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
438 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
439 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
440 phy->ops.write_reg = e1000_write_phy_reg_hv;
441 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
442 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
443 phy->ops.power_up = e1000_power_up_phy_copper;
444 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
445 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
446
447 phy->id = e1000_phy_unknown;
448
449 ret_val = e1000_init_phy_workarounds_pchlan(hw);
450 if (ret_val)
451 return ret_val;
452
453 if (phy->id == e1000_phy_unknown)
454 switch (hw->mac.type) {
455 default:
456 ret_val = e1000e_get_phy_id(hw);
457 if (ret_val)
458 return ret_val;
459 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
460 break;
461 fallthrough;
462 case e1000_pch2lan:
463 case e1000_pch_lpt:
464 case e1000_pch_spt:
465 case e1000_pch_cnp:
466 case e1000_pch_tgp:
467 case e1000_pch_adp:
468 case e1000_pch_mtp:
469 /* In case the PHY needs to be in mdio slow mode,
470 * set slow mode and try to get the PHY id again.
471 */
472 ret_val = e1000_set_mdio_slow_mode_hv(hw);
473 if (ret_val)
474 return ret_val;
475 ret_val = e1000e_get_phy_id(hw);
476 if (ret_val)
477 return ret_val;
478 break;
479 }
480 phy->type = e1000e_get_phy_type_from_id(phy->id);
481
482 switch (phy->type) {
483 case e1000_phy_82577:
484 case e1000_phy_82579:
485 case e1000_phy_i217:
486 phy->ops.check_polarity = e1000_check_polarity_82577;
487 phy->ops.force_speed_duplex =
488 e1000_phy_force_speed_duplex_82577;
489 phy->ops.get_cable_length = e1000_get_cable_length_82577;
490 phy->ops.get_info = e1000_get_phy_info_82577;
491 phy->ops.commit = e1000e_phy_sw_reset;
492 break;
493 case e1000_phy_82578:
494 phy->ops.check_polarity = e1000_check_polarity_m88;
495 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
496 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
497 phy->ops.get_info = e1000e_get_phy_info_m88;
498 break;
499 default:
500 ret_val = -E1000_ERR_PHY;
501 break;
502 }
503
504 return ret_val;
505 }
506
507 /**
508 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
509 * @hw: pointer to the HW structure
510 *
511 * Initialize family-specific PHY parameters and function pointers.
512 **/
513 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
514 {
515 struct e1000_phy_info *phy = &hw->phy;
516 s32 ret_val;
517 u16 i = 0;
518
519 phy->addr = 1;
520 phy->reset_delay_us = 100;
521
522 phy->ops.power_up = e1000_power_up_phy_copper;
523 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
524
525 /* We may need to do this twice - once for IGP and if that fails,
526 * we'll set BM func pointers and try again
527 */
528 ret_val = e1000e_determine_phy_address(hw);
529 if (ret_val) {
530 phy->ops.write_reg = e1000e_write_phy_reg_bm;
531 phy->ops.read_reg = e1000e_read_phy_reg_bm;
532 ret_val = e1000e_determine_phy_address(hw);
533 if (ret_val) {
534 e_dbg("Cannot determine PHY addr. Erroring out\n");
535 return ret_val;
536 }
537 }
538
539 phy->id = 0;
540 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
541 (i++ < 100)) {
542 usleep_range(1000, 1100);
543 ret_val = e1000e_get_phy_id(hw);
544 if (ret_val)
545 return ret_val;
546 }
547
548 /* Verify phy id */
549 switch (phy->id) {
550 case IGP03E1000_E_PHY_ID:
551 phy->type = e1000_phy_igp_3;
552 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
553 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
554 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
555 phy->ops.get_info = e1000e_get_phy_info_igp;
556 phy->ops.check_polarity = e1000_check_polarity_igp;
557 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
558 break;
559 case IFE_E_PHY_ID:
560 case IFE_PLUS_E_PHY_ID:
561 case IFE_C_E_PHY_ID:
562 phy->type = e1000_phy_ife;
563 phy->autoneg_mask = E1000_ALL_NOT_GIG;
564 phy->ops.get_info = e1000_get_phy_info_ife;
565 phy->ops.check_polarity = e1000_check_polarity_ife;
566 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
567 break;
568 case BME1000_E_PHY_ID:
569 phy->type = e1000_phy_bm;
570 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
571 phy->ops.read_reg = e1000e_read_phy_reg_bm;
572 phy->ops.write_reg = e1000e_write_phy_reg_bm;
573 phy->ops.commit = e1000e_phy_sw_reset;
574 phy->ops.get_info = e1000e_get_phy_info_m88;
575 phy->ops.check_polarity = e1000_check_polarity_m88;
576 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
577 break;
578 default:
579 return -E1000_ERR_PHY;
580 }
581
582 return 0;
583 }
584
585 /**
586 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
587 * @hw: pointer to the HW structure
588 *
589 * Initialize family-specific NVM parameters and function
590 * pointers.
591 **/
592 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
593 {
594 struct e1000_nvm_info *nvm = &hw->nvm;
595 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
596 u32 gfpreg, sector_base_addr, sector_end_addr;
597 u16 i;
598 u32 nvm_size;
599
600 nvm->type = e1000_nvm_flash_sw;
601
602 if (hw->mac.type >= e1000_pch_spt) {
603 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
604 * STRAP register. This is because in SPT the GbE Flash region
605 * is no longer accessed through the flash registers. Instead,
606 * the mechanism has changed, and the Flash region access
607 * registers are now implemented in GbE memory space.
608 */
609 nvm->flash_base_addr = 0;
610 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
611 * NVM_SIZE_MULTIPLIER;
612 nvm->flash_bank_size = nvm_size / 2;
613 /* Adjust to word count */
614 nvm->flash_bank_size /= sizeof(u16);
615 /* Set the base address for flash register access */
616 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
617 } else {
618 /* Can't read flash registers if register set isn't mapped. */
619 if (!hw->flash_address) {
620 e_dbg("ERROR: Flash registers not mapped\n");
621 return -E1000_ERR_CONFIG;
622 }
623
624 gfpreg = er32flash(ICH_FLASH_GFPREG);
625
626 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
627 * Add 1 to sector_end_addr since this sector is included in
628 * the overall size.
629 */
630 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
631 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
632
633 /* flash_base_addr is byte-aligned */
634 nvm->flash_base_addr = sector_base_addr
635 << FLASH_SECTOR_ADDR_SHIFT;
636
637 /* find total size of the NVM, then cut in half since the total
638 * size represents two separate NVM banks.
639 */
640 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
641 << FLASH_SECTOR_ADDR_SHIFT);
642 nvm->flash_bank_size /= 2;
643 /* Adjust to word count */
644 nvm->flash_bank_size /= sizeof(u16);
645 }
646
647 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
648
649 /* Clear shadow ram */
650 for (i = 0; i < nvm->word_size; i++) {
651 dev_spec->shadow_ram[i].modified = false;
652 dev_spec->shadow_ram[i].value = 0xFFFF;
653 }
654
655 return 0;
656 }
657
658 /**
659 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
660 * @hw: pointer to the HW structure
661 *
662 * Initialize family-specific MAC parameters and function
663 * pointers.
664 **/
665 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
666 {
667 struct e1000_mac_info *mac = &hw->mac;
668
669 /* Set media type function pointer */
670 hw->phy.media_type = e1000_media_type_copper;
671
672 /* Set mta register count */
673 mac->mta_reg_count = 32;
674 /* Set rar entry count */
675 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
676 if (mac->type == e1000_ich8lan)
677 mac->rar_entry_count--;
678 /* FWSM register */
679 mac->has_fwsm = true;
680 /* ARC subsystem not supported */
681 mac->arc_subsystem_valid = false;
682 /* Adaptive IFS supported */
683 mac->adaptive_ifs = true;
684
685 /* LED and other operations */
686 switch (mac->type) {
687 case e1000_ich8lan:
688 case e1000_ich9lan:
689 case e1000_ich10lan:
690 /* check management mode */
691 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
692 /* ID LED init */
693 mac->ops.id_led_init = e1000e_id_led_init_generic;
694 /* blink LED */
695 mac->ops.blink_led = e1000e_blink_led_generic;
696 /* setup LED */
697 mac->ops.setup_led = e1000e_setup_led_generic;
698 /* cleanup LED */
699 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
700 /* turn on/off LED */
701 mac->ops.led_on = e1000_led_on_ich8lan;
702 mac->ops.led_off = e1000_led_off_ich8lan;
703 break;
704 case e1000_pch2lan:
705 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
706 mac->ops.rar_set = e1000_rar_set_pch2lan;
707 fallthrough;
708 case e1000_pch_lpt:
709 case e1000_pch_spt:
710 case e1000_pch_cnp:
711 case e1000_pch_tgp:
712 case e1000_pch_adp:
713 case e1000_pch_mtp:
714 case e1000_pchlan:
715 /* check management mode */
716 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
717 /* ID LED init */
718 mac->ops.id_led_init = e1000_id_led_init_pchlan;
719 /* setup LED */
720 mac->ops.setup_led = e1000_setup_led_pchlan;
721 /* cleanup LED */
722 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
723 /* turn on/off LED */
724 mac->ops.led_on = e1000_led_on_pchlan;
725 mac->ops.led_off = e1000_led_off_pchlan;
726 break;
727 default:
728 break;
729 }
730
731 if (mac->type >= e1000_pch_lpt) {
732 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
733 mac->ops.rar_set = e1000_rar_set_pch_lpt;
734 mac->ops.setup_physical_interface =
735 e1000_setup_copper_link_pch_lpt;
736 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
737 }
738
739 /* Enable PCS Lock-loss workaround for ICH8 */
740 if (mac->type == e1000_ich8lan)
741 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
742
743 return 0;
744 }
745
746 /**
747 * __e1000_access_emi_reg_locked - Read/write EMI register
748 * @hw: pointer to the HW structure
749 * @address: EMI address to program
750 * @data: pointer to value to read/write from/to the EMI address
751 * @read: boolean flag to indicate read or write
752 *
753 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
754 **/
755 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
756 u16 *data, bool read)
757 {
758 s32 ret_val;
759
760 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
761 if (ret_val)
762 return ret_val;
763
764 if (read)
765 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
766 else
767 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
768
769 return ret_val;
770 }
771
772 /**
773 * e1000_read_emi_reg_locked - Read Extended Management Interface register
774 * @hw: pointer to the HW structure
775 * @addr: EMI address to program
776 * @data: value to be read from the EMI address
777 *
778 * Assumes the SW/FW/HW Semaphore is already acquired.
779 **/
780 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
781 {
782 return __e1000_access_emi_reg_locked(hw, addr, data, true);
783 }
784
785 /**
786 * e1000_write_emi_reg_locked - Write Extended Management Interface register
787 * @hw: pointer to the HW structure
788 * @addr: EMI address to program
789 * @data: value to be written to the EMI address
790 *
791 * Assumes the SW/FW/HW Semaphore is already acquired.
792 **/
793 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
794 {
795 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
796 }
797
798 /**
799 * e1000_set_eee_pchlan - Enable/disable EEE support
800 * @hw: pointer to the HW structure
801 *
802 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
803 * the link and the EEE capabilities of the link partner. The LPI Control
804 * register bits will remain set only if/when link is up.
805 *
806 * EEE LPI must not be asserted earlier than one second after link is up.
807 * On 82579, EEE LPI should not be enabled until such time otherwise there
808 * can be link issues with some switches. Other devices can have EEE LPI
809 * enabled immediately upon link up since they have a timer in hardware which
810 * prevents LPI from being asserted too early.
811 **/
812 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
813 {
814 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
815 s32 ret_val;
816 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
817
818 switch (hw->phy.type) {
819 case e1000_phy_82579:
820 lpa = I82579_EEE_LP_ABILITY;
821 pcs_status = I82579_EEE_PCS_STATUS;
822 adv_addr = I82579_EEE_ADVERTISEMENT;
823 break;
824 case e1000_phy_i217:
825 lpa = I217_EEE_LP_ABILITY;
826 pcs_status = I217_EEE_PCS_STATUS;
827 adv_addr = I217_EEE_ADVERTISEMENT;
828 break;
829 default:
830 return 0;
831 }
832
833 ret_val = hw->phy.ops.acquire(hw);
834 if (ret_val)
835 return ret_val;
836
837 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
838 if (ret_val)
839 goto release;
840
841 /* Clear bits that enable EEE in various speeds */
842 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
843
844 /* Enable EEE if not disabled by user */
845 if (!dev_spec->eee_disable) {
846 /* Save off link partner's EEE ability */
847 ret_val = e1000_read_emi_reg_locked(hw, lpa,
848 &dev_spec->eee_lp_ability);
849 if (ret_val)
850 goto release;
851
852 /* Read EEE advertisement */
853 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
854 if (ret_val)
855 goto release;
856
857 /* Enable EEE only for speeds in which the link partner is
858 * EEE capable and for which we advertise EEE.
859 */
860 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
861 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
862
863 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
864 e1e_rphy_locked(hw, MII_LPA, &data);
865 if (data & LPA_100FULL)
866 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
867 else
868 /* EEE is not supported in 100Half, so ignore
869 * partner's EEE in 100 ability if full-duplex
870 * is not advertised.
871 */
872 dev_spec->eee_lp_ability &=
873 ~I82579_EEE_100_SUPPORTED;
874 }
875 }
876
877 if (hw->phy.type == e1000_phy_82579) {
878 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
879 &data);
880 if (ret_val)
881 goto release;
882
883 data &= ~I82579_LPI_100_PLL_SHUT;
884 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
885 data);
886 }
887
888 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
889 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
890 if (ret_val)
891 goto release;
892
893 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
894 release:
895 hw->phy.ops.release(hw);
896
897 return ret_val;
898 }
899
900 /**
901 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
902 * @hw: pointer to the HW structure
903 * @link: link up bool flag
904 *
905 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
906 * preventing further DMA write requests. Workaround the issue by disabling
907 * the de-assertion of the clock request when in 1Gpbs mode.
908 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
909 * speeds in order to avoid Tx hangs.
910 **/
911 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
912 {
913 u32 fextnvm6 = er32(FEXTNVM6);
914 u32 status = er32(STATUS);
915 s32 ret_val = 0;
916 u16 reg;
917
918 if (link && (status & E1000_STATUS_SPEED_1000)) {
919 ret_val = hw->phy.ops.acquire(hw);
920 if (ret_val)
921 return ret_val;
922
923 ret_val =
924 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
925 &reg);
926 if (ret_val)
927 goto release;
928
929 ret_val =
930 e1000e_write_kmrn_reg_locked(hw,
931 E1000_KMRNCTRLSTA_K1_CONFIG,
932 reg &
933 ~E1000_KMRNCTRLSTA_K1_ENABLE);
934 if (ret_val)
935 goto release;
936
937 usleep_range(10, 20);
938
939 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
940
941 ret_val =
942 e1000e_write_kmrn_reg_locked(hw,
943 E1000_KMRNCTRLSTA_K1_CONFIG,
944 reg);
945 release:
946 hw->phy.ops.release(hw);
947 } else {
948 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
949 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
950
951 if ((hw->phy.revision > 5) || !link ||
952 ((status & E1000_STATUS_SPEED_100) &&
953 (status & E1000_STATUS_FD)))
954 goto update_fextnvm6;
955
956 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
957 if (ret_val)
958 return ret_val;
959
960 /* Clear link status transmit timeout */
961 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
962
963 if (status & E1000_STATUS_SPEED_100) {
964 /* Set inband Tx timeout to 5x10us for 100Half */
965 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
966
967 /* Do not extend the K1 entry latency for 100Half */
968 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
969 } else {
970 /* Set inband Tx timeout to 50x10us for 10Full/Half */
971 reg |= 50 <<
972 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
973
974 /* Extend the K1 entry latency for 10 Mbps */
975 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
976 }
977
978 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
979 if (ret_val)
980 return ret_val;
981
982 update_fextnvm6:
983 ew32(FEXTNVM6, fextnvm6);
984 }
985
986 return ret_val;
987 }
988
989 /**
990 * e1000_platform_pm_pch_lpt - Set platform power management values
991 * @hw: pointer to the HW structure
992 * @link: bool indicating link status
993 *
994 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
995 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
996 * when link is up (which must not exceed the maximum latency supported
997 * by the platform), otherwise specify there is no LTR requirement.
998 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
999 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1000 * Capability register set, on this device LTR is set by writing the
1001 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1002 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1003 * message to the PMC.
1004 **/
1005 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1006 {
1007 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1008 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1009 u16 lat_enc = 0; /* latency encoded */
1010
1011 if (link) {
1012 u16 speed, duplex, scale = 0;
1013 u16 max_snoop, max_nosnoop;
1014 u16 max_ltr_enc; /* max LTR latency encoded */
1015 u64 value;
1016 u32 rxa;
1017
1018 if (!hw->adapter->max_frame_size) {
1019 e_dbg("max_frame_size not set.\n");
1020 return -E1000_ERR_CONFIG;
1021 }
1022
1023 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1024 if (!speed) {
1025 e_dbg("Speed not set.\n");
1026 return -E1000_ERR_CONFIG;
1027 }
1028
1029 /* Rx Packet Buffer Allocation size (KB) */
1030 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1031
1032 /* Determine the maximum latency tolerated by the device.
1033 *
1034 * Per the PCIe spec, the tolerated latencies are encoded as
1035 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1036 * a 10-bit value (0-1023) to provide a range from 1 ns to
1037 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1038 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1039 */
1040 rxa *= 512;
1041 value = (rxa > hw->adapter->max_frame_size) ?
1042 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1043 0;
1044
1045 while (value > PCI_LTR_VALUE_MASK) {
1046 scale++;
1047 value = DIV_ROUND_UP(value, BIT(5));
1048 }
1049 if (scale > E1000_LTRV_SCALE_MAX) {
1050 e_dbg("Invalid LTR latency scale %d\n", scale);
1051 return -E1000_ERR_CONFIG;
1052 }
1053 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1054
1055 /* Determine the maximum latency tolerated by the platform */
1056 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1057 &max_snoop);
1058 pci_read_config_word(hw->adapter->pdev,
1059 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1060 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1061
1062 if (lat_enc > max_ltr_enc)
1063 lat_enc = max_ltr_enc;
1064 }
1065
1066 /* Set Snoop and No-Snoop latencies the same */
1067 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1068 ew32(LTRV, reg);
1069
1070 return 0;
1071 }
1072
1073 /**
1074 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1075 * @hw: pointer to the HW structure
1076 * @to_sx: boolean indicating a system power state transition to Sx
1077 *
1078 * When link is down, configure ULP mode to significantly reduce the power
1079 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1080 * ME firmware to start the ULP configuration. If not on an ME enabled
1081 * system, configure the ULP mode by software.
1082 */
1083 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1084 {
1085 u32 mac_reg;
1086 s32 ret_val = 0;
1087 u16 phy_reg;
1088 u16 oem_reg = 0;
1089
1090 if ((hw->mac.type < e1000_pch_lpt) ||
1091 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1092 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1093 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1094 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1095 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1096 return 0;
1097
1098 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1099 /* Request ME configure ULP mode in the PHY */
1100 mac_reg = er32(H2ME);
1101 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1102 ew32(H2ME, mac_reg);
1103
1104 goto out;
1105 }
1106
1107 if (!to_sx) {
1108 int i = 0;
1109
1110 /* Poll up to 5 seconds for Cable Disconnected indication */
1111 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1112 /* Bail if link is re-acquired */
1113 if (er32(STATUS) & E1000_STATUS_LU)
1114 return -E1000_ERR_PHY;
1115
1116 if (i++ == 100)
1117 break;
1118
1119 msleep(50);
1120 }
1121 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1122 (er32(FEXT) &
1123 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1124 }
1125
1126 ret_val = hw->phy.ops.acquire(hw);
1127 if (ret_val)
1128 goto out;
1129
1130 /* Force SMBus mode in PHY */
1131 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1132 if (ret_val)
1133 goto release;
1134 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1135 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1136
1137 /* Force SMBus mode in MAC */
1138 mac_reg = er32(CTRL_EXT);
1139 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1140 ew32(CTRL_EXT, mac_reg);
1141
1142 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1143 * LPLU and disable Gig speed when entering ULP
1144 */
1145 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1146 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1147 &oem_reg);
1148 if (ret_val)
1149 goto release;
1150
1151 phy_reg = oem_reg;
1152 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1153
1154 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1155 phy_reg);
1156
1157 if (ret_val)
1158 goto release;
1159 }
1160
1161 /* Set Inband ULP Exit, Reset to SMBus mode and
1162 * Disable SMBus Release on PERST# in PHY
1163 */
1164 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1165 if (ret_val)
1166 goto release;
1167 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1168 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1169 if (to_sx) {
1170 if (er32(WUFC) & E1000_WUFC_LNKC)
1171 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1172 else
1173 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1174
1175 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1176 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1177 } else {
1178 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1179 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1180 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1181 }
1182 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1183
1184 /* Set Disable SMBus Release on PERST# in MAC */
1185 mac_reg = er32(FEXTNVM7);
1186 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1187 ew32(FEXTNVM7, mac_reg);
1188
1189 /* Commit ULP changes in PHY by starting auto ULP configuration */
1190 phy_reg |= I218_ULP_CONFIG1_START;
1191 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1192
1193 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1194 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1195 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1196 oem_reg);
1197 if (ret_val)
1198 goto release;
1199 }
1200
1201 release:
1202 hw->phy.ops.release(hw);
1203 out:
1204 if (ret_val)
1205 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1206 else
1207 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1208
1209 return ret_val;
1210 }
1211
1212 /**
1213 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1214 * @hw: pointer to the HW structure
1215 * @force: boolean indicating whether or not to force disabling ULP
1216 *
1217 * Un-configure ULP mode when link is up, the system is transitioned from
1218 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1219 * system, poll for an indication from ME that ULP has been un-configured.
1220 * If not on an ME enabled system, un-configure the ULP mode by software.
1221 *
1222 * During nominal operation, this function is called when link is acquired
1223 * to disable ULP mode (force=false); otherwise, for example when unloading
1224 * the driver or during Sx->S0 transitions, this is called with force=true
1225 * to forcibly disable ULP.
1226 */
1227 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1228 {
1229 s32 ret_val = 0;
1230 u32 mac_reg;
1231 u16 phy_reg;
1232 int i = 0;
1233
1234 if ((hw->mac.type < e1000_pch_lpt) ||
1235 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1236 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1237 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1238 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1239 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1240 return 0;
1241
1242 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1243 struct e1000_adapter *adapter = hw->adapter;
1244 bool firmware_bug = false;
1245
1246 if (force) {
1247 /* Request ME un-configure ULP mode in the PHY */
1248 mac_reg = er32(H2ME);
1249 mac_reg &= ~E1000_H2ME_ULP;
1250 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1251 ew32(H2ME, mac_reg);
1252 }
1253
1254 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1255 * If this takes more than 1 second, show a warning indicating a
1256 * firmware bug
1257 */
1258 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1259 if (i++ == 250) {
1260 ret_val = -E1000_ERR_PHY;
1261 goto out;
1262 }
1263 if (i > 100 && !firmware_bug)
1264 firmware_bug = true;
1265
1266 usleep_range(10000, 11000);
1267 }
1268 if (firmware_bug)
1269 e_warn("ULP_CONFIG_DONE took %dmsec. This is a firmware bug\n", i * 10);
1270 else
1271 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1272
1273 if (force) {
1274 mac_reg = er32(H2ME);
1275 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1276 ew32(H2ME, mac_reg);
1277 } else {
1278 /* Clear H2ME.ULP after ME ULP configuration */
1279 mac_reg = er32(H2ME);
1280 mac_reg &= ~E1000_H2ME_ULP;
1281 ew32(H2ME, mac_reg);
1282 }
1283
1284 goto out;
1285 }
1286
1287 ret_val = hw->phy.ops.acquire(hw);
1288 if (ret_val)
1289 goto out;
1290
1291 if (force)
1292 /* Toggle LANPHYPC Value bit */
1293 e1000_toggle_lanphypc_pch_lpt(hw);
1294
1295 /* Unforce SMBus mode in PHY */
1296 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1297 if (ret_val) {
1298 /* The MAC might be in PCIe mode, so temporarily force to
1299 * SMBus mode in order to access the PHY.
1300 */
1301 mac_reg = er32(CTRL_EXT);
1302 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1303 ew32(CTRL_EXT, mac_reg);
1304
1305 msleep(50);
1306
1307 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1308 &phy_reg);
1309 if (ret_val)
1310 goto release;
1311 }
1312 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1313 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1314
1315 /* Unforce SMBus mode in MAC */
1316 mac_reg = er32(CTRL_EXT);
1317 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1318 ew32(CTRL_EXT, mac_reg);
1319
1320 /* When ULP mode was previously entered, K1 was disabled by the
1321 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1322 */
1323 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1324 if (ret_val)
1325 goto release;
1326 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1327 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1328
1329 /* Clear ULP enabled configuration */
1330 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1331 if (ret_val)
1332 goto release;
1333 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1334 I218_ULP_CONFIG1_STICKY_ULP |
1335 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1336 I218_ULP_CONFIG1_WOL_HOST |
1337 I218_ULP_CONFIG1_INBAND_EXIT |
1338 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1339 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1340 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1341 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1342
1343 /* Commit ULP changes by starting auto ULP configuration */
1344 phy_reg |= I218_ULP_CONFIG1_START;
1345 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1346
1347 /* Clear Disable SMBus Release on PERST# in MAC */
1348 mac_reg = er32(FEXTNVM7);
1349 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1350 ew32(FEXTNVM7, mac_reg);
1351
1352 release:
1353 hw->phy.ops.release(hw);
1354 if (force) {
1355 e1000_phy_hw_reset(hw);
1356 msleep(50);
1357 }
1358 out:
1359 if (ret_val)
1360 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1361 else
1362 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1363
1364 return ret_val;
1365 }
1366
1367 /**
1368 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1369 * @hw: pointer to the HW structure
1370 *
1371 * Checks to see of the link status of the hardware has changed. If a
1372 * change in link status has been detected, then we read the PHY registers
1373 * to get the current speed/duplex if link exists.
1374 **/
1375 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1376 {
1377 struct e1000_mac_info *mac = &hw->mac;
1378 s32 ret_val, tipg_reg = 0;
1379 u16 emi_addr, emi_val = 0;
1380 bool link;
1381 u16 phy_reg;
1382
1383 /* We only want to go out to the PHY registers to see if Auto-Neg
1384 * has completed and/or if our link status has changed. The
1385 * get_link_status flag is set upon receiving a Link Status
1386 * Change or Rx Sequence Error interrupt.
1387 */
1388 if (!mac->get_link_status)
1389 return 0;
1390 mac->get_link_status = false;
1391
1392 /* First we want to see if the MII Status Register reports
1393 * link. If so, then we want to get the current speed/duplex
1394 * of the PHY.
1395 */
1396 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1397 if (ret_val)
1398 goto out;
1399
1400 if (hw->mac.type == e1000_pchlan) {
1401 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1402 if (ret_val)
1403 goto out;
1404 }
1405
1406 /* When connected at 10Mbps half-duplex, some parts are excessively
1407 * aggressive resulting in many collisions. To avoid this, increase
1408 * the IPG and reduce Rx latency in the PHY.
1409 */
1410 if ((hw->mac.type >= e1000_pch2lan) && link) {
1411 u16 speed, duplex;
1412
1413 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1414 tipg_reg = er32(TIPG);
1415 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1416
1417 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1418 tipg_reg |= 0xFF;
1419 /* Reduce Rx latency in analog PHY */
1420 emi_val = 0;
1421 } else if (hw->mac.type >= e1000_pch_spt &&
1422 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1423 tipg_reg |= 0xC;
1424 emi_val = 1;
1425 } else {
1426
1427 /* Roll back the default values */
1428 tipg_reg |= 0x08;
1429 emi_val = 1;
1430 }
1431
1432 ew32(TIPG, tipg_reg);
1433
1434 ret_val = hw->phy.ops.acquire(hw);
1435 if (ret_val)
1436 goto out;
1437
1438 if (hw->mac.type == e1000_pch2lan)
1439 emi_addr = I82579_RX_CONFIG;
1440 else
1441 emi_addr = I217_RX_CONFIG;
1442 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1443
1444 if (hw->mac.type >= e1000_pch_lpt) {
1445 u16 phy_reg;
1446
1447 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1448 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1449 if (speed == SPEED_100 || speed == SPEED_10)
1450 phy_reg |= 0x3E8;
1451 else
1452 phy_reg |= 0xFA;
1453 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1454
1455 if (speed == SPEED_1000) {
1456 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1457 &phy_reg);
1458
1459 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1460
1461 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1462 phy_reg);
1463 }
1464 }
1465 hw->phy.ops.release(hw);
1466
1467 if (ret_val)
1468 goto out;
1469
1470 if (hw->mac.type >= e1000_pch_spt) {
1471 u16 data;
1472 u16 ptr_gap;
1473
1474 if (speed == SPEED_1000) {
1475 ret_val = hw->phy.ops.acquire(hw);
1476 if (ret_val)
1477 goto out;
1478
1479 ret_val = e1e_rphy_locked(hw,
1480 PHY_REG(776, 20),
1481 &data);
1482 if (ret_val) {
1483 hw->phy.ops.release(hw);
1484 goto out;
1485 }
1486
1487 ptr_gap = (data & (0x3FF << 2)) >> 2;
1488 if (ptr_gap < 0x18) {
1489 data &= ~(0x3FF << 2);
1490 data |= (0x18 << 2);
1491 ret_val =
1492 e1e_wphy_locked(hw,
1493 PHY_REG(776, 20),
1494 data);
1495 }
1496 hw->phy.ops.release(hw);
1497 if (ret_val)
1498 goto out;
1499 } else {
1500 ret_val = hw->phy.ops.acquire(hw);
1501 if (ret_val)
1502 goto out;
1503
1504 ret_val = e1e_wphy_locked(hw,
1505 PHY_REG(776, 20),
1506 0xC023);
1507 hw->phy.ops.release(hw);
1508 if (ret_val)
1509 goto out;
1510
1511 }
1512 }
1513 }
1514
1515 /* I217 Packet Loss issue:
1516 * ensure that FEXTNVM4 Beacon Duration is set correctly
1517 * on power up.
1518 * Set the Beacon Duration for I217 to 8 usec
1519 */
1520 if (hw->mac.type >= e1000_pch_lpt) {
1521 u32 mac_reg;
1522
1523 mac_reg = er32(FEXTNVM4);
1524 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1525 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1526 ew32(FEXTNVM4, mac_reg);
1527 }
1528
1529 /* Work-around I218 hang issue */
1530 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1531 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1532 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1533 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1534 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1535 if (ret_val)
1536 goto out;
1537 }
1538 if (hw->mac.type >= e1000_pch_lpt) {
1539 /* Set platform power management values for
1540 * Latency Tolerance Reporting (LTR)
1541 */
1542 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1543 if (ret_val)
1544 goto out;
1545 }
1546
1547 /* Clear link partner's EEE ability */
1548 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1549
1550 if (hw->mac.type >= e1000_pch_lpt) {
1551 u32 fextnvm6 = er32(FEXTNVM6);
1552
1553 if (hw->mac.type == e1000_pch_spt) {
1554 /* FEXTNVM6 K1-off workaround - for SPT only */
1555 u32 pcieanacfg = er32(PCIEANACFG);
1556
1557 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1558 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1559 else
1560 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1561 }
1562
1563 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1564 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1565
1566 ew32(FEXTNVM6, fextnvm6);
1567 }
1568
1569 if (!link)
1570 goto out;
1571
1572 switch (hw->mac.type) {
1573 case e1000_pch2lan:
1574 ret_val = e1000_k1_workaround_lv(hw);
1575 if (ret_val)
1576 return ret_val;
1577 fallthrough;
1578 case e1000_pchlan:
1579 if (hw->phy.type == e1000_phy_82578) {
1580 ret_val = e1000_link_stall_workaround_hv(hw);
1581 if (ret_val)
1582 return ret_val;
1583 }
1584
1585 /* Workaround for PCHx parts in half-duplex:
1586 * Set the number of preambles removed from the packet
1587 * when it is passed from the PHY to the MAC to prevent
1588 * the MAC from misinterpreting the packet type.
1589 */
1590 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1591 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1592
1593 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1594 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1595
1596 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1597 break;
1598 default:
1599 break;
1600 }
1601
1602 /* Check if there was DownShift, must be checked
1603 * immediately after link-up
1604 */
1605 e1000e_check_downshift(hw);
1606
1607 /* Enable/Disable EEE after link up */
1608 if (hw->phy.type > e1000_phy_82579) {
1609 ret_val = e1000_set_eee_pchlan(hw);
1610 if (ret_val)
1611 return ret_val;
1612 }
1613
1614 /* If we are forcing speed/duplex, then we simply return since
1615 * we have already determined whether we have link or not.
1616 */
1617 if (!mac->autoneg)
1618 return -E1000_ERR_CONFIG;
1619
1620 /* Auto-Neg is enabled. Auto Speed Detection takes care
1621 * of MAC speed/duplex configuration. So we only need to
1622 * configure Collision Distance in the MAC.
1623 */
1624 mac->ops.config_collision_dist(hw);
1625
1626 /* Configure Flow Control now that Auto-Neg has completed.
1627 * First, we need to restore the desired flow control
1628 * settings because we may have had to re-autoneg with a
1629 * different link partner.
1630 */
1631 ret_val = e1000e_config_fc_after_link_up(hw);
1632 if (ret_val)
1633 e_dbg("Error configuring flow control\n");
1634
1635 return ret_val;
1636
1637 out:
1638 mac->get_link_status = true;
1639 return ret_val;
1640 }
1641
1642 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1643 {
1644 struct e1000_hw *hw = &adapter->hw;
1645 s32 rc;
1646
1647 rc = e1000_init_mac_params_ich8lan(hw);
1648 if (rc)
1649 return rc;
1650
1651 rc = e1000_init_nvm_params_ich8lan(hw);
1652 if (rc)
1653 return rc;
1654
1655 switch (hw->mac.type) {
1656 case e1000_ich8lan:
1657 case e1000_ich9lan:
1658 case e1000_ich10lan:
1659 rc = e1000_init_phy_params_ich8lan(hw);
1660 break;
1661 case e1000_pchlan:
1662 case e1000_pch2lan:
1663 case e1000_pch_lpt:
1664 case e1000_pch_spt:
1665 case e1000_pch_cnp:
1666 case e1000_pch_tgp:
1667 case e1000_pch_adp:
1668 case e1000_pch_mtp:
1669 rc = e1000_init_phy_params_pchlan(hw);
1670 break;
1671 default:
1672 break;
1673 }
1674 if (rc)
1675 return rc;
1676
1677 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1678 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1679 */
1680 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1681 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1682 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1683 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1684 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1685
1686 hw->mac.ops.blink_led = NULL;
1687 }
1688
1689 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1690 (adapter->hw.phy.type != e1000_phy_ife))
1691 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1692
1693 /* Enable workaround for 82579 w/ ME enabled */
1694 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1695 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1696 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1697
1698 return 0;
1699 }
1700
1701 static DEFINE_MUTEX(nvm_mutex);
1702
1703 /**
1704 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1705 * @hw: pointer to the HW structure
1706 *
1707 * Acquires the mutex for performing NVM operations.
1708 **/
1709 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1710 {
1711 mutex_lock(&nvm_mutex);
1712
1713 return 0;
1714 }
1715
1716 /**
1717 * e1000_release_nvm_ich8lan - Release NVM mutex
1718 * @hw: pointer to the HW structure
1719 *
1720 * Releases the mutex used while performing NVM operations.
1721 **/
1722 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1723 {
1724 mutex_unlock(&nvm_mutex);
1725 }
1726
1727 /**
1728 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1729 * @hw: pointer to the HW structure
1730 *
1731 * Acquires the software control flag for performing PHY and select
1732 * MAC CSR accesses.
1733 **/
1734 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1735 {
1736 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1737 s32 ret_val = 0;
1738
1739 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1740 &hw->adapter->state)) {
1741 e_dbg("contention for Phy access\n");
1742 return -E1000_ERR_PHY;
1743 }
1744
1745 while (timeout) {
1746 extcnf_ctrl = er32(EXTCNF_CTRL);
1747 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1748 break;
1749
1750 mdelay(1);
1751 timeout--;
1752 }
1753
1754 if (!timeout) {
1755 e_dbg("SW has already locked the resource.\n");
1756 ret_val = -E1000_ERR_CONFIG;
1757 goto out;
1758 }
1759
1760 timeout = SW_FLAG_TIMEOUT;
1761
1762 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1763 ew32(EXTCNF_CTRL, extcnf_ctrl);
1764
1765 while (timeout) {
1766 extcnf_ctrl = er32(EXTCNF_CTRL);
1767 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1768 break;
1769
1770 mdelay(1);
1771 timeout--;
1772 }
1773
1774 if (!timeout) {
1775 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1776 er32(FWSM), extcnf_ctrl);
1777 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1778 ew32(EXTCNF_CTRL, extcnf_ctrl);
1779 ret_val = -E1000_ERR_CONFIG;
1780 goto out;
1781 }
1782
1783 out:
1784 if (ret_val)
1785 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1786
1787 return ret_val;
1788 }
1789
1790 /**
1791 * e1000_release_swflag_ich8lan - Release software control flag
1792 * @hw: pointer to the HW structure
1793 *
1794 * Releases the software control flag for performing PHY and select
1795 * MAC CSR accesses.
1796 **/
1797 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1798 {
1799 u32 extcnf_ctrl;
1800
1801 extcnf_ctrl = er32(EXTCNF_CTRL);
1802
1803 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1804 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1805 ew32(EXTCNF_CTRL, extcnf_ctrl);
1806 } else {
1807 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1808 }
1809
1810 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1811 }
1812
1813 /**
1814 * e1000_check_mng_mode_ich8lan - Checks management mode
1815 * @hw: pointer to the HW structure
1816 *
1817 * This checks if the adapter has any manageability enabled.
1818 * This is a function pointer entry point only called by read/write
1819 * routines for the PHY and NVM parts.
1820 **/
1821 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1822 {
1823 u32 fwsm;
1824
1825 fwsm = er32(FWSM);
1826 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1827 ((fwsm & E1000_FWSM_MODE_MASK) ==
1828 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1829 }
1830
1831 /**
1832 * e1000_check_mng_mode_pchlan - Checks management mode
1833 * @hw: pointer to the HW structure
1834 *
1835 * This checks if the adapter has iAMT enabled.
1836 * This is a function pointer entry point only called by read/write
1837 * routines for the PHY and NVM parts.
1838 **/
1839 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1840 {
1841 u32 fwsm;
1842
1843 fwsm = er32(FWSM);
1844 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1845 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1846 }
1847
1848 /**
1849 * e1000_rar_set_pch2lan - Set receive address register
1850 * @hw: pointer to the HW structure
1851 * @addr: pointer to the receive address
1852 * @index: receive address array register
1853 *
1854 * Sets the receive address array register at index to the address passed
1855 * in by addr. For 82579, RAR[0] is the base address register that is to
1856 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1857 * Use SHRA[0-3] in place of those reserved for ME.
1858 **/
1859 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1860 {
1861 u32 rar_low, rar_high;
1862
1863 /* HW expects these in little endian so we reverse the byte order
1864 * from network order (big endian) to little endian
1865 */
1866 rar_low = ((u32)addr[0] |
1867 ((u32)addr[1] << 8) |
1868 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1869
1870 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1871
1872 /* If MAC address zero, no need to set the AV bit */
1873 if (rar_low || rar_high)
1874 rar_high |= E1000_RAH_AV;
1875
1876 if (index == 0) {
1877 ew32(RAL(index), rar_low);
1878 e1e_flush();
1879 ew32(RAH(index), rar_high);
1880 e1e_flush();
1881 return 0;
1882 }
1883
1884 /* RAR[1-6] are owned by manageability. Skip those and program the
1885 * next address into the SHRA register array.
1886 */
1887 if (index < (u32)(hw->mac.rar_entry_count)) {
1888 s32 ret_val;
1889
1890 ret_val = e1000_acquire_swflag_ich8lan(hw);
1891 if (ret_val)
1892 goto out;
1893
1894 ew32(SHRAL(index - 1), rar_low);
1895 e1e_flush();
1896 ew32(SHRAH(index - 1), rar_high);
1897 e1e_flush();
1898
1899 e1000_release_swflag_ich8lan(hw);
1900
1901 /* verify the register updates */
1902 if ((er32(SHRAL(index - 1)) == rar_low) &&
1903 (er32(SHRAH(index - 1)) == rar_high))
1904 return 0;
1905
1906 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1907 (index - 1), er32(FWSM));
1908 }
1909
1910 out:
1911 e_dbg("Failed to write receive address at index %d\n", index);
1912 return -E1000_ERR_CONFIG;
1913 }
1914
1915 /**
1916 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1917 * @hw: pointer to the HW structure
1918 *
1919 * Get the number of available receive registers that the Host can
1920 * program. SHRA[0-10] are the shared receive address registers
1921 * that are shared between the Host and manageability engine (ME).
1922 * ME can reserve any number of addresses and the host needs to be
1923 * able to tell how many available registers it has access to.
1924 **/
1925 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1926 {
1927 u32 wlock_mac;
1928 u32 num_entries;
1929
1930 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1931 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1932
1933 switch (wlock_mac) {
1934 case 0:
1935 /* All SHRA[0..10] and RAR[0] available */
1936 num_entries = hw->mac.rar_entry_count;
1937 break;
1938 case 1:
1939 /* Only RAR[0] available */
1940 num_entries = 1;
1941 break;
1942 default:
1943 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1944 num_entries = wlock_mac + 1;
1945 break;
1946 }
1947
1948 return num_entries;
1949 }
1950
1951 /**
1952 * e1000_rar_set_pch_lpt - Set receive address registers
1953 * @hw: pointer to the HW structure
1954 * @addr: pointer to the receive address
1955 * @index: receive address array register
1956 *
1957 * Sets the receive address register array at index to the address passed
1958 * in by addr. For LPT, RAR[0] is the base address register that is to
1959 * contain the MAC address. SHRA[0-10] are the shared receive address
1960 * registers that are shared between the Host and manageability engine (ME).
1961 **/
1962 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1963 {
1964 u32 rar_low, rar_high;
1965 u32 wlock_mac;
1966
1967 /* HW expects these in little endian so we reverse the byte order
1968 * from network order (big endian) to little endian
1969 */
1970 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1971 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1972
1973 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1974
1975 /* If MAC address zero, no need to set the AV bit */
1976 if (rar_low || rar_high)
1977 rar_high |= E1000_RAH_AV;
1978
1979 if (index == 0) {
1980 ew32(RAL(index), rar_low);
1981 e1e_flush();
1982 ew32(RAH(index), rar_high);
1983 e1e_flush();
1984 return 0;
1985 }
1986
1987 /* The manageability engine (ME) can lock certain SHRAR registers that
1988 * it is using - those registers are unavailable for use.
1989 */
1990 if (index < hw->mac.rar_entry_count) {
1991 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1992 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1993
1994 /* Check if all SHRAR registers are locked */
1995 if (wlock_mac == 1)
1996 goto out;
1997
1998 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1999 s32 ret_val;
2000
2001 ret_val = e1000_acquire_swflag_ich8lan(hw);
2002
2003 if (ret_val)
2004 goto out;
2005
2006 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2007 e1e_flush();
2008 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2009 e1e_flush();
2010
2011 e1000_release_swflag_ich8lan(hw);
2012
2013 /* verify the register updates */
2014 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2015 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2016 return 0;
2017 }
2018 }
2019
2020 out:
2021 e_dbg("Failed to write receive address at index %d\n", index);
2022 return -E1000_ERR_CONFIG;
2023 }
2024
2025 /**
2026 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2027 * @hw: pointer to the HW structure
2028 *
2029 * Checks if firmware is blocking the reset of the PHY.
2030 * This is a function pointer entry point only called by
2031 * reset routines.
2032 **/
2033 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2034 {
2035 bool blocked = false;
2036 int i = 0;
2037
2038 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2039 (i++ < 30))
2040 usleep_range(10000, 11000);
2041 return blocked ? E1000_BLK_PHY_RESET : 0;
2042 }
2043
2044 /**
2045 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2046 * @hw: pointer to the HW structure
2047 *
2048 * Assumes semaphore already acquired.
2049 *
2050 **/
2051 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2052 {
2053 u16 phy_data;
2054 u32 strap = er32(STRAP);
2055 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2056 E1000_STRAP_SMT_FREQ_SHIFT;
2057 s32 ret_val;
2058
2059 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2060
2061 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2062 if (ret_val)
2063 return ret_val;
2064
2065 phy_data &= ~HV_SMB_ADDR_MASK;
2066 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2067 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2068
2069 if (hw->phy.type == e1000_phy_i217) {
2070 /* Restore SMBus frequency */
2071 if (freq--) {
2072 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2073 phy_data |= (freq & BIT(0)) <<
2074 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2075 phy_data |= (freq & BIT(1)) <<
2076 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2077 } else {
2078 e_dbg("Unsupported SMB frequency in PHY\n");
2079 }
2080 }
2081
2082 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2083 }
2084
2085 /**
2086 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2087 * @hw: pointer to the HW structure
2088 *
2089 * SW should configure the LCD from the NVM extended configuration region
2090 * as a workaround for certain parts.
2091 **/
2092 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2093 {
2094 struct e1000_phy_info *phy = &hw->phy;
2095 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2096 s32 ret_val = 0;
2097 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2098
2099 /* Initialize the PHY from the NVM on ICH platforms. This
2100 * is needed due to an issue where the NVM configuration is
2101 * not properly autoloaded after power transitions.
2102 * Therefore, after each PHY reset, we will load the
2103 * configuration data out of the NVM manually.
2104 */
2105 switch (hw->mac.type) {
2106 case e1000_ich8lan:
2107 if (phy->type != e1000_phy_igp_3)
2108 return ret_val;
2109
2110 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2111 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2112 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2113 break;
2114 }
2115 fallthrough;
2116 case e1000_pchlan:
2117 case e1000_pch2lan:
2118 case e1000_pch_lpt:
2119 case e1000_pch_spt:
2120 case e1000_pch_cnp:
2121 case e1000_pch_tgp:
2122 case e1000_pch_adp:
2123 case e1000_pch_mtp:
2124 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2125 break;
2126 default:
2127 return ret_val;
2128 }
2129
2130 ret_val = hw->phy.ops.acquire(hw);
2131 if (ret_val)
2132 return ret_val;
2133
2134 data = er32(FEXTNVM);
2135 if (!(data & sw_cfg_mask))
2136 goto release;
2137
2138 /* Make sure HW does not configure LCD from PHY
2139 * extended configuration before SW configuration
2140 */
2141 data = er32(EXTCNF_CTRL);
2142 if ((hw->mac.type < e1000_pch2lan) &&
2143 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2144 goto release;
2145
2146 cnf_size = er32(EXTCNF_SIZE);
2147 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2148 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2149 if (!cnf_size)
2150 goto release;
2151
2152 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2153 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2154
2155 if (((hw->mac.type == e1000_pchlan) &&
2156 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2157 (hw->mac.type > e1000_pchlan)) {
2158 /* HW configures the SMBus address and LEDs when the
2159 * OEM and LCD Write Enable bits are set in the NVM.
2160 * When both NVM bits are cleared, SW will configure
2161 * them instead.
2162 */
2163 ret_val = e1000_write_smbus_addr(hw);
2164 if (ret_val)
2165 goto release;
2166
2167 data = er32(LEDCTL);
2168 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2169 (u16)data);
2170 if (ret_val)
2171 goto release;
2172 }
2173
2174 /* Configure LCD from extended configuration region. */
2175
2176 /* cnf_base_addr is in DWORD */
2177 word_addr = (u16)(cnf_base_addr << 1);
2178
2179 for (i = 0; i < cnf_size; i++) {
2180 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2181 if (ret_val)
2182 goto release;
2183
2184 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2185 1, &reg_addr);
2186 if (ret_val)
2187 goto release;
2188
2189 /* Save off the PHY page for future writes. */
2190 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2191 phy_page = reg_data;
2192 continue;
2193 }
2194
2195 reg_addr &= PHY_REG_MASK;
2196 reg_addr |= phy_page;
2197
2198 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2199 if (ret_val)
2200 goto release;
2201 }
2202
2203 release:
2204 hw->phy.ops.release(hw);
2205 return ret_val;
2206 }
2207
2208 /**
2209 * e1000_k1_gig_workaround_hv - K1 Si workaround
2210 * @hw: pointer to the HW structure
2211 * @link: link up bool flag
2212 *
2213 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2214 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2215 * If link is down, the function will restore the default K1 setting located
2216 * in the NVM.
2217 **/
2218 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2219 {
2220 s32 ret_val = 0;
2221 u16 status_reg = 0;
2222 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2223
2224 if (hw->mac.type != e1000_pchlan)
2225 return 0;
2226
2227 /* Wrap the whole flow with the sw flag */
2228 ret_val = hw->phy.ops.acquire(hw);
2229 if (ret_val)
2230 return ret_val;
2231
2232 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2233 if (link) {
2234 if (hw->phy.type == e1000_phy_82578) {
2235 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2236 &status_reg);
2237 if (ret_val)
2238 goto release;
2239
2240 status_reg &= (BM_CS_STATUS_LINK_UP |
2241 BM_CS_STATUS_RESOLVED |
2242 BM_CS_STATUS_SPEED_MASK);
2243
2244 if (status_reg == (BM_CS_STATUS_LINK_UP |
2245 BM_CS_STATUS_RESOLVED |
2246 BM_CS_STATUS_SPEED_1000))
2247 k1_enable = false;
2248 }
2249
2250 if (hw->phy.type == e1000_phy_82577) {
2251 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2252 if (ret_val)
2253 goto release;
2254
2255 status_reg &= (HV_M_STATUS_LINK_UP |
2256 HV_M_STATUS_AUTONEG_COMPLETE |
2257 HV_M_STATUS_SPEED_MASK);
2258
2259 if (status_reg == (HV_M_STATUS_LINK_UP |
2260 HV_M_STATUS_AUTONEG_COMPLETE |
2261 HV_M_STATUS_SPEED_1000))
2262 k1_enable = false;
2263 }
2264
2265 /* Link stall fix for link up */
2266 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2267 if (ret_val)
2268 goto release;
2269
2270 } else {
2271 /* Link stall fix for link down */
2272 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2273 if (ret_val)
2274 goto release;
2275 }
2276
2277 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2278
2279 release:
2280 hw->phy.ops.release(hw);
2281
2282 return ret_val;
2283 }
2284
2285 /**
2286 * e1000_configure_k1_ich8lan - Configure K1 power state
2287 * @hw: pointer to the HW structure
2288 * @k1_enable: K1 state to configure
2289 *
2290 * Configure the K1 power state based on the provided parameter.
2291 * Assumes semaphore already acquired.
2292 *
2293 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2294 **/
2295 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2296 {
2297 s32 ret_val;
2298 u32 ctrl_reg = 0;
2299 u32 ctrl_ext = 0;
2300 u32 reg = 0;
2301 u16 kmrn_reg = 0;
2302
2303 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2304 &kmrn_reg);
2305 if (ret_val)
2306 return ret_val;
2307
2308 if (k1_enable)
2309 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2310 else
2311 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2312
2313 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2314 kmrn_reg);
2315 if (ret_val)
2316 return ret_val;
2317
2318 usleep_range(20, 40);
2319 ctrl_ext = er32(CTRL_EXT);
2320 ctrl_reg = er32(CTRL);
2321
2322 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2323 reg |= E1000_CTRL_FRCSPD;
2324 ew32(CTRL, reg);
2325
2326 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2327 e1e_flush();
2328 usleep_range(20, 40);
2329 ew32(CTRL, ctrl_reg);
2330 ew32(CTRL_EXT, ctrl_ext);
2331 e1e_flush();
2332 usleep_range(20, 40);
2333
2334 return 0;
2335 }
2336
2337 /**
2338 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2339 * @hw: pointer to the HW structure
2340 * @d0_state: boolean if entering d0 or d3 device state
2341 *
2342 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2343 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2344 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2345 **/
2346 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2347 {
2348 s32 ret_val = 0;
2349 u32 mac_reg;
2350 u16 oem_reg;
2351
2352 if (hw->mac.type < e1000_pchlan)
2353 return ret_val;
2354
2355 ret_val = hw->phy.ops.acquire(hw);
2356 if (ret_val)
2357 return ret_val;
2358
2359 if (hw->mac.type == e1000_pchlan) {
2360 mac_reg = er32(EXTCNF_CTRL);
2361 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2362 goto release;
2363 }
2364
2365 mac_reg = er32(FEXTNVM);
2366 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2367 goto release;
2368
2369 mac_reg = er32(PHY_CTRL);
2370
2371 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2372 if (ret_val)
2373 goto release;
2374
2375 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2376
2377 if (d0_state) {
2378 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2379 oem_reg |= HV_OEM_BITS_GBE_DIS;
2380
2381 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2382 oem_reg |= HV_OEM_BITS_LPLU;
2383 } else {
2384 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2385 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2386 oem_reg |= HV_OEM_BITS_GBE_DIS;
2387
2388 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2389 E1000_PHY_CTRL_NOND0A_LPLU))
2390 oem_reg |= HV_OEM_BITS_LPLU;
2391 }
2392
2393 /* Set Restart auto-neg to activate the bits */
2394 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2395 !hw->phy.ops.check_reset_block(hw))
2396 oem_reg |= HV_OEM_BITS_RESTART_AN;
2397
2398 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2399
2400 release:
2401 hw->phy.ops.release(hw);
2402
2403 return ret_val;
2404 }
2405
2406 /**
2407 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2408 * @hw: pointer to the HW structure
2409 **/
2410 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2411 {
2412 s32 ret_val;
2413 u16 data;
2414
2415 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2416 if (ret_val)
2417 return ret_val;
2418
2419 data |= HV_KMRN_MDIO_SLOW;
2420
2421 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2422
2423 return ret_val;
2424 }
2425
2426 /**
2427 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2428 * @hw: pointer to the HW structure
2429 *
2430 * A series of PHY workarounds to be done after every PHY reset.
2431 **/
2432 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2433 {
2434 s32 ret_val = 0;
2435 u16 phy_data;
2436
2437 if (hw->mac.type != e1000_pchlan)
2438 return 0;
2439
2440 /* Set MDIO slow mode before any other MDIO access */
2441 if (hw->phy.type == e1000_phy_82577) {
2442 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2443 if (ret_val)
2444 return ret_val;
2445 }
2446
2447 if (((hw->phy.type == e1000_phy_82577) &&
2448 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2449 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2450 /* Disable generation of early preamble */
2451 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2452 if (ret_val)
2453 return ret_val;
2454
2455 /* Preamble tuning for SSC */
2456 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2457 if (ret_val)
2458 return ret_val;
2459 }
2460
2461 if (hw->phy.type == e1000_phy_82578) {
2462 /* Return registers to default by doing a soft reset then
2463 * writing 0x3140 to the control register.
2464 */
2465 if (hw->phy.revision < 2) {
2466 e1000e_phy_sw_reset(hw);
2467 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2468 if (ret_val)
2469 return ret_val;
2470 }
2471 }
2472
2473 /* Select page 0 */
2474 ret_val = hw->phy.ops.acquire(hw);
2475 if (ret_val)
2476 return ret_val;
2477
2478 hw->phy.addr = 1;
2479 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2480 hw->phy.ops.release(hw);
2481 if (ret_val)
2482 return ret_val;
2483
2484 /* Configure the K1 Si workaround during phy reset assuming there is
2485 * link so that it disables K1 if link is in 1Gbps.
2486 */
2487 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2488 if (ret_val)
2489 return ret_val;
2490
2491 /* Workaround for link disconnects on a busy hub in half duplex */
2492 ret_val = hw->phy.ops.acquire(hw);
2493 if (ret_val)
2494 return ret_val;
2495 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2496 if (ret_val)
2497 goto release;
2498 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2499 if (ret_val)
2500 goto release;
2501
2502 /* set MSE higher to enable link to stay up when noise is high */
2503 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2504 release:
2505 hw->phy.ops.release(hw);
2506
2507 return ret_val;
2508 }
2509
2510 /**
2511 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2512 * @hw: pointer to the HW structure
2513 **/
2514 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2515 {
2516 u32 mac_reg;
2517 u16 i, phy_reg = 0;
2518 s32 ret_val;
2519
2520 ret_val = hw->phy.ops.acquire(hw);
2521 if (ret_val)
2522 return;
2523 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2524 if (ret_val)
2525 goto release;
2526
2527 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2528 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2529 mac_reg = er32(RAL(i));
2530 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2531 (u16)(mac_reg & 0xFFFF));
2532 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2533 (u16)((mac_reg >> 16) & 0xFFFF));
2534
2535 mac_reg = er32(RAH(i));
2536 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2537 (u16)(mac_reg & 0xFFFF));
2538 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2539 (u16)((mac_reg & E1000_RAH_AV)
2540 >> 16));
2541 }
2542
2543 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2544
2545 release:
2546 hw->phy.ops.release(hw);
2547 }
2548
2549 /**
2550 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2551 * with 82579 PHY
2552 * @hw: pointer to the HW structure
2553 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2554 **/
2555 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2556 {
2557 s32 ret_val = 0;
2558 u16 phy_reg, data;
2559 u32 mac_reg;
2560 u16 i;
2561
2562 if (hw->mac.type < e1000_pch2lan)
2563 return 0;
2564
2565 /* disable Rx path while enabling/disabling workaround */
2566 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2567 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2568 if (ret_val)
2569 return ret_val;
2570
2571 if (enable) {
2572 /* Write Rx addresses (rar_entry_count for RAL/H, and
2573 * SHRAL/H) and initial CRC values to the MAC
2574 */
2575 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2576 u8 mac_addr[ETH_ALEN] = { 0 };
2577 u32 addr_high, addr_low;
2578
2579 addr_high = er32(RAH(i));
2580 if (!(addr_high & E1000_RAH_AV))
2581 continue;
2582 addr_low = er32(RAL(i));
2583 mac_addr[0] = (addr_low & 0xFF);
2584 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2585 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2586 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2587 mac_addr[4] = (addr_high & 0xFF);
2588 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2589
2590 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2591 }
2592
2593 /* Write Rx addresses to the PHY */
2594 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2595
2596 /* Enable jumbo frame workaround in the MAC */
2597 mac_reg = er32(FFLT_DBG);
2598 mac_reg &= ~BIT(14);
2599 mac_reg |= (7 << 15);
2600 ew32(FFLT_DBG, mac_reg);
2601
2602 mac_reg = er32(RCTL);
2603 mac_reg |= E1000_RCTL_SECRC;
2604 ew32(RCTL, mac_reg);
2605
2606 ret_val = e1000e_read_kmrn_reg(hw,
2607 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2608 &data);
2609 if (ret_val)
2610 return ret_val;
2611 ret_val = e1000e_write_kmrn_reg(hw,
2612 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2613 data | BIT(0));
2614 if (ret_val)
2615 return ret_val;
2616 ret_val = e1000e_read_kmrn_reg(hw,
2617 E1000_KMRNCTRLSTA_HD_CTRL,
2618 &data);
2619 if (ret_val)
2620 return ret_val;
2621 data &= ~(0xF << 8);
2622 data |= (0xB << 8);
2623 ret_val = e1000e_write_kmrn_reg(hw,
2624 E1000_KMRNCTRLSTA_HD_CTRL,
2625 data);
2626 if (ret_val)
2627 return ret_val;
2628
2629 /* Enable jumbo frame workaround in the PHY */
2630 e1e_rphy(hw, PHY_REG(769, 23), &data);
2631 data &= ~(0x7F << 5);
2632 data |= (0x37 << 5);
2633 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2634 if (ret_val)
2635 return ret_val;
2636 e1e_rphy(hw, PHY_REG(769, 16), &data);
2637 data &= ~BIT(13);
2638 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2639 if (ret_val)
2640 return ret_val;
2641 e1e_rphy(hw, PHY_REG(776, 20), &data);
2642 data &= ~(0x3FF << 2);
2643 data |= (E1000_TX_PTR_GAP << 2);
2644 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2645 if (ret_val)
2646 return ret_val;
2647 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2648 if (ret_val)
2649 return ret_val;
2650 e1e_rphy(hw, HV_PM_CTRL, &data);
2651 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2652 if (ret_val)
2653 return ret_val;
2654 } else {
2655 /* Write MAC register values back to h/w defaults */
2656 mac_reg = er32(FFLT_DBG);
2657 mac_reg &= ~(0xF << 14);
2658 ew32(FFLT_DBG, mac_reg);
2659
2660 mac_reg = er32(RCTL);
2661 mac_reg &= ~E1000_RCTL_SECRC;
2662 ew32(RCTL, mac_reg);
2663
2664 ret_val = e1000e_read_kmrn_reg(hw,
2665 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2666 &data);
2667 if (ret_val)
2668 return ret_val;
2669 ret_val = e1000e_write_kmrn_reg(hw,
2670 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2671 data & ~BIT(0));
2672 if (ret_val)
2673 return ret_val;
2674 ret_val = e1000e_read_kmrn_reg(hw,
2675 E1000_KMRNCTRLSTA_HD_CTRL,
2676 &data);
2677 if (ret_val)
2678 return ret_val;
2679 data &= ~(0xF << 8);
2680 data |= (0xB << 8);
2681 ret_val = e1000e_write_kmrn_reg(hw,
2682 E1000_KMRNCTRLSTA_HD_CTRL,
2683 data);
2684 if (ret_val)
2685 return ret_val;
2686
2687 /* Write PHY register values back to h/w defaults */
2688 e1e_rphy(hw, PHY_REG(769, 23), &data);
2689 data &= ~(0x7F << 5);
2690 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2691 if (ret_val)
2692 return ret_val;
2693 e1e_rphy(hw, PHY_REG(769, 16), &data);
2694 data |= BIT(13);
2695 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2696 if (ret_val)
2697 return ret_val;
2698 e1e_rphy(hw, PHY_REG(776, 20), &data);
2699 data &= ~(0x3FF << 2);
2700 data |= (0x8 << 2);
2701 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2702 if (ret_val)
2703 return ret_val;
2704 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2705 if (ret_val)
2706 return ret_val;
2707 e1e_rphy(hw, HV_PM_CTRL, &data);
2708 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2709 if (ret_val)
2710 return ret_val;
2711 }
2712
2713 /* re-enable Rx path after enabling/disabling workaround */
2714 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2715 }
2716
2717 /**
2718 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2719 * @hw: pointer to the HW structure
2720 *
2721 * A series of PHY workarounds to be done after every PHY reset.
2722 **/
2723 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2724 {
2725 s32 ret_val = 0;
2726
2727 if (hw->mac.type != e1000_pch2lan)
2728 return 0;
2729
2730 /* Set MDIO slow mode before any other MDIO access */
2731 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2732 if (ret_val)
2733 return ret_val;
2734
2735 ret_val = hw->phy.ops.acquire(hw);
2736 if (ret_val)
2737 return ret_val;
2738 /* set MSE higher to enable link to stay up when noise is high */
2739 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2740 if (ret_val)
2741 goto release;
2742 /* drop link after 5 times MSE threshold was reached */
2743 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2744 release:
2745 hw->phy.ops.release(hw);
2746
2747 return ret_val;
2748 }
2749
2750 /**
2751 * e1000_k1_gig_workaround_lv - K1 Si workaround
2752 * @hw: pointer to the HW structure
2753 *
2754 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2755 * Disable K1 in 1000Mbps and 100Mbps
2756 **/
2757 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2758 {
2759 s32 ret_val = 0;
2760 u16 status_reg = 0;
2761
2762 if (hw->mac.type != e1000_pch2lan)
2763 return 0;
2764
2765 /* Set K1 beacon duration based on 10Mbs speed */
2766 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2767 if (ret_val)
2768 return ret_val;
2769
2770 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2771 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2772 if (status_reg &
2773 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2774 u16 pm_phy_reg;
2775
2776 /* LV 1G/100 Packet drop issue wa */
2777 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2778 if (ret_val)
2779 return ret_val;
2780 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2781 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2782 if (ret_val)
2783 return ret_val;
2784 } else {
2785 u32 mac_reg;
2786
2787 mac_reg = er32(FEXTNVM4);
2788 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2789 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2790 ew32(FEXTNVM4, mac_reg);
2791 }
2792 }
2793
2794 return ret_val;
2795 }
2796
2797 /**
2798 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2799 * @hw: pointer to the HW structure
2800 * @gate: boolean set to true to gate, false to ungate
2801 *
2802 * Gate/ungate the automatic PHY configuration via hardware; perform
2803 * the configuration via software instead.
2804 **/
2805 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2806 {
2807 u32 extcnf_ctrl;
2808
2809 if (hw->mac.type < e1000_pch2lan)
2810 return;
2811
2812 extcnf_ctrl = er32(EXTCNF_CTRL);
2813
2814 if (gate)
2815 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2816 else
2817 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2818
2819 ew32(EXTCNF_CTRL, extcnf_ctrl);
2820 }
2821
2822 /**
2823 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2824 * @hw: pointer to the HW structure
2825 *
2826 * Check the appropriate indication the MAC has finished configuring the
2827 * PHY after a software reset.
2828 **/
2829 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2830 {
2831 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2832
2833 /* Wait for basic configuration completes before proceeding */
2834 do {
2835 data = er32(STATUS);
2836 data &= E1000_STATUS_LAN_INIT_DONE;
2837 usleep_range(100, 200);
2838 } while ((!data) && --loop);
2839
2840 /* If basic configuration is incomplete before the above loop
2841 * count reaches 0, loading the configuration from NVM will
2842 * leave the PHY in a bad state possibly resulting in no link.
2843 */
2844 if (loop == 0)
2845 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2846
2847 /* Clear the Init Done bit for the next init event */
2848 data = er32(STATUS);
2849 data &= ~E1000_STATUS_LAN_INIT_DONE;
2850 ew32(STATUS, data);
2851 }
2852
2853 /**
2854 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2855 * @hw: pointer to the HW structure
2856 **/
2857 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2858 {
2859 s32 ret_val = 0;
2860 u16 reg;
2861
2862 if (hw->phy.ops.check_reset_block(hw))
2863 return 0;
2864
2865 /* Allow time for h/w to get to quiescent state after reset */
2866 usleep_range(10000, 11000);
2867
2868 /* Perform any necessary post-reset workarounds */
2869 switch (hw->mac.type) {
2870 case e1000_pchlan:
2871 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2872 if (ret_val)
2873 return ret_val;
2874 break;
2875 case e1000_pch2lan:
2876 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2877 if (ret_val)
2878 return ret_val;
2879 break;
2880 default:
2881 break;
2882 }
2883
2884 /* Clear the host wakeup bit after lcd reset */
2885 if (hw->mac.type >= e1000_pchlan) {
2886 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2887 reg &= ~BM_WUC_HOST_WU_BIT;
2888 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2889 }
2890
2891 /* Configure the LCD with the extended configuration region in NVM */
2892 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2893 if (ret_val)
2894 return ret_val;
2895
2896 /* Configure the LCD with the OEM bits in NVM */
2897 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2898
2899 if (hw->mac.type == e1000_pch2lan) {
2900 /* Ungate automatic PHY configuration on non-managed 82579 */
2901 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2902 usleep_range(10000, 11000);
2903 e1000_gate_hw_phy_config_ich8lan(hw, false);
2904 }
2905
2906 /* Set EEE LPI Update Timer to 200usec */
2907 ret_val = hw->phy.ops.acquire(hw);
2908 if (ret_val)
2909 return ret_val;
2910 ret_val = e1000_write_emi_reg_locked(hw,
2911 I82579_LPI_UPDATE_TIMER,
2912 0x1387);
2913 hw->phy.ops.release(hw);
2914 }
2915
2916 return ret_val;
2917 }
2918
2919 /**
2920 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2921 * @hw: pointer to the HW structure
2922 *
2923 * Resets the PHY
2924 * This is a function pointer entry point called by drivers
2925 * or other shared routines.
2926 **/
2927 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2928 {
2929 s32 ret_val = 0;
2930
2931 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2932 if ((hw->mac.type == e1000_pch2lan) &&
2933 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2934 e1000_gate_hw_phy_config_ich8lan(hw, true);
2935
2936 ret_val = e1000e_phy_hw_reset_generic(hw);
2937 if (ret_val)
2938 return ret_val;
2939
2940 return e1000_post_phy_reset_ich8lan(hw);
2941 }
2942
2943 /**
2944 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2945 * @hw: pointer to the HW structure
2946 * @active: true to enable LPLU, false to disable
2947 *
2948 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2949 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2950 * the phy speed. This function will manually set the LPLU bit and restart
2951 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2952 * since it configures the same bit.
2953 **/
2954 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2955 {
2956 s32 ret_val;
2957 u16 oem_reg;
2958
2959 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2960 if (ret_val)
2961 return ret_val;
2962
2963 if (active)
2964 oem_reg |= HV_OEM_BITS_LPLU;
2965 else
2966 oem_reg &= ~HV_OEM_BITS_LPLU;
2967
2968 if (!hw->phy.ops.check_reset_block(hw))
2969 oem_reg |= HV_OEM_BITS_RESTART_AN;
2970
2971 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2972 }
2973
2974 /**
2975 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2976 * @hw: pointer to the HW structure
2977 * @active: true to enable LPLU, false to disable
2978 *
2979 * Sets the LPLU D0 state according to the active flag. When
2980 * activating LPLU this function also disables smart speed
2981 * and vice versa. LPLU will not be activated unless the
2982 * device autonegotiation advertisement meets standards of
2983 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2984 * This is a function pointer entry point only called by
2985 * PHY setup routines.
2986 **/
2987 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2988 {
2989 struct e1000_phy_info *phy = &hw->phy;
2990 u32 phy_ctrl;
2991 s32 ret_val = 0;
2992 u16 data;
2993
2994 if (phy->type == e1000_phy_ife)
2995 return 0;
2996
2997 phy_ctrl = er32(PHY_CTRL);
2998
2999 if (active) {
3000 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3001 ew32(PHY_CTRL, phy_ctrl);
3002
3003 if (phy->type != e1000_phy_igp_3)
3004 return 0;
3005
3006 /* Call gig speed drop workaround on LPLU before accessing
3007 * any PHY registers
3008 */
3009 if (hw->mac.type == e1000_ich8lan)
3010 e1000e_gig_downshift_workaround_ich8lan(hw);
3011
3012 /* When LPLU is enabled, we should disable SmartSpeed */
3013 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3014 if (ret_val)
3015 return ret_val;
3016 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3017 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3018 if (ret_val)
3019 return ret_val;
3020 } else {
3021 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3022 ew32(PHY_CTRL, phy_ctrl);
3023
3024 if (phy->type != e1000_phy_igp_3)
3025 return 0;
3026
3027 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3028 * during Dx states where the power conservation is most
3029 * important. During driver activity we should enable
3030 * SmartSpeed, so performance is maintained.
3031 */
3032 if (phy->smart_speed == e1000_smart_speed_on) {
3033 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3034 &data);
3035 if (ret_val)
3036 return ret_val;
3037
3038 data |= IGP01E1000_PSCFR_SMART_SPEED;
3039 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3040 data);
3041 if (ret_val)
3042 return ret_val;
3043 } else if (phy->smart_speed == e1000_smart_speed_off) {
3044 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3045 &data);
3046 if (ret_val)
3047 return ret_val;
3048
3049 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3050 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3051 data);
3052 if (ret_val)
3053 return ret_val;
3054 }
3055 }
3056
3057 return 0;
3058 }
3059
3060 /**
3061 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3062 * @hw: pointer to the HW structure
3063 * @active: true to enable LPLU, false to disable
3064 *
3065 * Sets the LPLU D3 state according to the active flag. When
3066 * activating LPLU this function also disables smart speed
3067 * and vice versa. LPLU will not be activated unless the
3068 * device autonegotiation advertisement meets standards of
3069 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3070 * This is a function pointer entry point only called by
3071 * PHY setup routines.
3072 **/
3073 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3074 {
3075 struct e1000_phy_info *phy = &hw->phy;
3076 u32 phy_ctrl;
3077 s32 ret_val = 0;
3078 u16 data;
3079
3080 phy_ctrl = er32(PHY_CTRL);
3081
3082 if (!active) {
3083 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3084 ew32(PHY_CTRL, phy_ctrl);
3085
3086 if (phy->type != e1000_phy_igp_3)
3087 return 0;
3088
3089 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3090 * during Dx states where the power conservation is most
3091 * important. During driver activity we should enable
3092 * SmartSpeed, so performance is maintained.
3093 */
3094 if (phy->smart_speed == e1000_smart_speed_on) {
3095 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3096 &data);
3097 if (ret_val)
3098 return ret_val;
3099
3100 data |= IGP01E1000_PSCFR_SMART_SPEED;
3101 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3102 data);
3103 if (ret_val)
3104 return ret_val;
3105 } else if (phy->smart_speed == e1000_smart_speed_off) {
3106 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3107 &data);
3108 if (ret_val)
3109 return ret_val;
3110
3111 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3112 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3113 data);
3114 if (ret_val)
3115 return ret_val;
3116 }
3117 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3118 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3119 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3120 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3121 ew32(PHY_CTRL, phy_ctrl);
3122
3123 if (phy->type != e1000_phy_igp_3)
3124 return 0;
3125
3126 /* Call gig speed drop workaround on LPLU before accessing
3127 * any PHY registers
3128 */
3129 if (hw->mac.type == e1000_ich8lan)
3130 e1000e_gig_downshift_workaround_ich8lan(hw);
3131
3132 /* When LPLU is enabled, we should disable SmartSpeed */
3133 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3134 if (ret_val)
3135 return ret_val;
3136
3137 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3138 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3139 }
3140
3141 return ret_val;
3142 }
3143
3144 /**
3145 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3146 * @hw: pointer to the HW structure
3147 * @bank: pointer to the variable that returns the active bank
3148 *
3149 * Reads signature byte from the NVM using the flash access registers.
3150 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3151 **/
3152 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3153 {
3154 u32 eecd;
3155 struct e1000_nvm_info *nvm = &hw->nvm;
3156 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3157 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3158 u32 nvm_dword = 0;
3159 u8 sig_byte = 0;
3160 s32 ret_val;
3161
3162 switch (hw->mac.type) {
3163 case e1000_pch_spt:
3164 case e1000_pch_cnp:
3165 case e1000_pch_tgp:
3166 case e1000_pch_adp:
3167 case e1000_pch_mtp:
3168 bank1_offset = nvm->flash_bank_size;
3169 act_offset = E1000_ICH_NVM_SIG_WORD;
3170
3171 /* set bank to 0 in case flash read fails */
3172 *bank = 0;
3173
3174 /* Check bank 0 */
3175 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3176 &nvm_dword);
3177 if (ret_val)
3178 return ret_val;
3179 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3180 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3181 E1000_ICH_NVM_SIG_VALUE) {
3182 *bank = 0;
3183 return 0;
3184 }
3185
3186 /* Check bank 1 */
3187 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3188 bank1_offset,
3189 &nvm_dword);
3190 if (ret_val)
3191 return ret_val;
3192 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3193 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3194 E1000_ICH_NVM_SIG_VALUE) {
3195 *bank = 1;
3196 return 0;
3197 }
3198
3199 e_dbg("ERROR: No valid NVM bank present\n");
3200 return -E1000_ERR_NVM;
3201 case e1000_ich8lan:
3202 case e1000_ich9lan:
3203 eecd = er32(EECD);
3204 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3205 E1000_EECD_SEC1VAL_VALID_MASK) {
3206 if (eecd & E1000_EECD_SEC1VAL)
3207 *bank = 1;
3208 else
3209 *bank = 0;
3210
3211 return 0;
3212 }
3213 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3214 fallthrough;
3215 default:
3216 /* set bank to 0 in case flash read fails */
3217 *bank = 0;
3218
3219 /* Check bank 0 */
3220 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3221 &sig_byte);
3222 if (ret_val)
3223 return ret_val;
3224 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3225 E1000_ICH_NVM_SIG_VALUE) {
3226 *bank = 0;
3227 return 0;
3228 }
3229
3230 /* Check bank 1 */
3231 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3232 bank1_offset,
3233 &sig_byte);
3234 if (ret_val)
3235 return ret_val;
3236 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3237 E1000_ICH_NVM_SIG_VALUE) {
3238 *bank = 1;
3239 return 0;
3240 }
3241
3242 e_dbg("ERROR: No valid NVM bank present\n");
3243 return -E1000_ERR_NVM;
3244 }
3245 }
3246
3247 /**
3248 * e1000_read_nvm_spt - NVM access for SPT
3249 * @hw: pointer to the HW structure
3250 * @offset: The offset (in bytes) of the word(s) to read.
3251 * @words: Size of data to read in words.
3252 * @data: pointer to the word(s) to read at offset.
3253 *
3254 * Reads a word(s) from the NVM
3255 **/
3256 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3257 u16 *data)
3258 {
3259 struct e1000_nvm_info *nvm = &hw->nvm;
3260 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3261 u32 act_offset;
3262 s32 ret_val = 0;
3263 u32 bank = 0;
3264 u32 dword = 0;
3265 u16 offset_to_read;
3266 u16 i;
3267
3268 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3269 (words == 0)) {
3270 e_dbg("nvm parameter(s) out of bounds\n");
3271 ret_val = -E1000_ERR_NVM;
3272 goto out;
3273 }
3274
3275 nvm->ops.acquire(hw);
3276
3277 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3278 if (ret_val) {
3279 e_dbg("Could not detect valid bank, assuming bank 0\n");
3280 bank = 0;
3281 }
3282
3283 act_offset = (bank) ? nvm->flash_bank_size : 0;
3284 act_offset += offset;
3285
3286 ret_val = 0;
3287
3288 for (i = 0; i < words; i += 2) {
3289 if (words - i == 1) {
3290 if (dev_spec->shadow_ram[offset + i].modified) {
3291 data[i] =
3292 dev_spec->shadow_ram[offset + i].value;
3293 } else {
3294 offset_to_read = act_offset + i -
3295 ((act_offset + i) % 2);
3296 ret_val =
3297 e1000_read_flash_dword_ich8lan(hw,
3298 offset_to_read,
3299 &dword);
3300 if (ret_val)
3301 break;
3302 if ((act_offset + i) % 2 == 0)
3303 data[i] = (u16)(dword & 0xFFFF);
3304 else
3305 data[i] = (u16)((dword >> 16) & 0xFFFF);
3306 }
3307 } else {
3308 offset_to_read = act_offset + i;
3309 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3310 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3311 ret_val =
3312 e1000_read_flash_dword_ich8lan(hw,
3313 offset_to_read,
3314 &dword);
3315 if (ret_val)
3316 break;
3317 }
3318 if (dev_spec->shadow_ram[offset + i].modified)
3319 data[i] =
3320 dev_spec->shadow_ram[offset + i].value;
3321 else
3322 data[i] = (u16)(dword & 0xFFFF);
3323 if (dev_spec->shadow_ram[offset + i].modified)
3324 data[i + 1] =
3325 dev_spec->shadow_ram[offset + i + 1].value;
3326 else
3327 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3328 }
3329 }
3330
3331 nvm->ops.release(hw);
3332
3333 out:
3334 if (ret_val)
3335 e_dbg("NVM read error: %d\n", ret_val);
3336
3337 return ret_val;
3338 }
3339
3340 /**
3341 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3342 * @hw: pointer to the HW structure
3343 * @offset: The offset (in bytes) of the word(s) to read.
3344 * @words: Size of data to read in words
3345 * @data: Pointer to the word(s) to read at offset.
3346 *
3347 * Reads a word(s) from the NVM using the flash access registers.
3348 **/
3349 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3350 u16 *data)
3351 {
3352 struct e1000_nvm_info *nvm = &hw->nvm;
3353 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3354 u32 act_offset;
3355 s32 ret_val = 0;
3356 u32 bank = 0;
3357 u16 i, word;
3358
3359 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3360 (words == 0)) {
3361 e_dbg("nvm parameter(s) out of bounds\n");
3362 ret_val = -E1000_ERR_NVM;
3363 goto out;
3364 }
3365
3366 nvm->ops.acquire(hw);
3367
3368 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3369 if (ret_val) {
3370 e_dbg("Could not detect valid bank, assuming bank 0\n");
3371 bank = 0;
3372 }
3373
3374 act_offset = (bank) ? nvm->flash_bank_size : 0;
3375 act_offset += offset;
3376
3377 ret_val = 0;
3378 for (i = 0; i < words; i++) {
3379 if (dev_spec->shadow_ram[offset + i].modified) {
3380 data[i] = dev_spec->shadow_ram[offset + i].value;
3381 } else {
3382 ret_val = e1000_read_flash_word_ich8lan(hw,
3383 act_offset + i,
3384 &word);
3385 if (ret_val)
3386 break;
3387 data[i] = word;
3388 }
3389 }
3390
3391 nvm->ops.release(hw);
3392
3393 out:
3394 if (ret_val)
3395 e_dbg("NVM read error: %d\n", ret_val);
3396
3397 return ret_val;
3398 }
3399
3400 /**
3401 * e1000_flash_cycle_init_ich8lan - Initialize flash
3402 * @hw: pointer to the HW structure
3403 *
3404 * This function does initial flash setup so that a new read/write/erase cycle
3405 * can be started.
3406 **/
3407 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3408 {
3409 union ich8_hws_flash_status hsfsts;
3410 s32 ret_val = -E1000_ERR_NVM;
3411
3412 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3413
3414 /* Check if the flash descriptor is valid */
3415 if (!hsfsts.hsf_status.fldesvalid) {
3416 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3417 return -E1000_ERR_NVM;
3418 }
3419
3420 /* Clear FCERR and DAEL in hw status by writing 1 */
3421 hsfsts.hsf_status.flcerr = 1;
3422 hsfsts.hsf_status.dael = 1;
3423 if (hw->mac.type >= e1000_pch_spt)
3424 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3425 else
3426 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3427
3428 /* Either we should have a hardware SPI cycle in progress
3429 * bit to check against, in order to start a new cycle or
3430 * FDONE bit should be changed in the hardware so that it
3431 * is 1 after hardware reset, which can then be used as an
3432 * indication whether a cycle is in progress or has been
3433 * completed.
3434 */
3435
3436 if (!hsfsts.hsf_status.flcinprog) {
3437 /* There is no cycle running at present,
3438 * so we can start a cycle.
3439 * Begin by setting Flash Cycle Done.
3440 */
3441 hsfsts.hsf_status.flcdone = 1;
3442 if (hw->mac.type >= e1000_pch_spt)
3443 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3444 else
3445 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3446 ret_val = 0;
3447 } else {
3448 s32 i;
3449
3450 /* Otherwise poll for sometime so the current
3451 * cycle has a chance to end before giving up.
3452 */
3453 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3454 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3455 if (!hsfsts.hsf_status.flcinprog) {
3456 ret_val = 0;
3457 break;
3458 }
3459 udelay(1);
3460 }
3461 if (!ret_val) {
3462 /* Successful in waiting for previous cycle to timeout,
3463 * now set the Flash Cycle Done.
3464 */
3465 hsfsts.hsf_status.flcdone = 1;
3466 if (hw->mac.type >= e1000_pch_spt)
3467 ew32flash(ICH_FLASH_HSFSTS,
3468 hsfsts.regval & 0xFFFF);
3469 else
3470 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3471 } else {
3472 e_dbg("Flash controller busy, cannot get access\n");
3473 }
3474 }
3475
3476 return ret_val;
3477 }
3478
3479 /**
3480 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3481 * @hw: pointer to the HW structure
3482 * @timeout: maximum time to wait for completion
3483 *
3484 * This function starts a flash cycle and waits for its completion.
3485 **/
3486 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3487 {
3488 union ich8_hws_flash_ctrl hsflctl;
3489 union ich8_hws_flash_status hsfsts;
3490 u32 i = 0;
3491
3492 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3493 if (hw->mac.type >= e1000_pch_spt)
3494 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3495 else
3496 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3497 hsflctl.hsf_ctrl.flcgo = 1;
3498
3499 if (hw->mac.type >= e1000_pch_spt)
3500 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3501 else
3502 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3503
3504 /* wait till FDONE bit is set to 1 */
3505 do {
3506 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3507 if (hsfsts.hsf_status.flcdone)
3508 break;
3509 udelay(1);
3510 } while (i++ < timeout);
3511
3512 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3513 return 0;
3514
3515 return -E1000_ERR_NVM;
3516 }
3517
3518 /**
3519 * e1000_read_flash_dword_ich8lan - Read dword from flash
3520 * @hw: pointer to the HW structure
3521 * @offset: offset to data location
3522 * @data: pointer to the location for storing the data
3523 *
3524 * Reads the flash dword at offset into data. Offset is converted
3525 * to bytes before read.
3526 **/
3527 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3528 u32 *data)
3529 {
3530 /* Must convert word offset into bytes. */
3531 offset <<= 1;
3532 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3533 }
3534
3535 /**
3536 * e1000_read_flash_word_ich8lan - Read word from flash
3537 * @hw: pointer to the HW structure
3538 * @offset: offset to data location
3539 * @data: pointer to the location for storing the data
3540 *
3541 * Reads the flash word at offset into data. Offset is converted
3542 * to bytes before read.
3543 **/
3544 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3545 u16 *data)
3546 {
3547 /* Must convert offset into bytes. */
3548 offset <<= 1;
3549
3550 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3551 }
3552
3553 /**
3554 * e1000_read_flash_byte_ich8lan - Read byte from flash
3555 * @hw: pointer to the HW structure
3556 * @offset: The offset of the byte to read.
3557 * @data: Pointer to a byte to store the value read.
3558 *
3559 * Reads a single byte from the NVM using the flash access registers.
3560 **/
3561 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3562 u8 *data)
3563 {
3564 s32 ret_val;
3565 u16 word = 0;
3566
3567 /* In SPT, only 32 bits access is supported,
3568 * so this function should not be called.
3569 */
3570 if (hw->mac.type >= e1000_pch_spt)
3571 return -E1000_ERR_NVM;
3572 else
3573 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3574
3575 if (ret_val)
3576 return ret_val;
3577
3578 *data = (u8)word;
3579
3580 return 0;
3581 }
3582
3583 /**
3584 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3585 * @hw: pointer to the HW structure
3586 * @offset: The offset (in bytes) of the byte or word to read.
3587 * @size: Size of data to read, 1=byte 2=word
3588 * @data: Pointer to the word to store the value read.
3589 *
3590 * Reads a byte or word from the NVM using the flash access registers.
3591 **/
3592 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3593 u8 size, u16 *data)
3594 {
3595 union ich8_hws_flash_status hsfsts;
3596 union ich8_hws_flash_ctrl hsflctl;
3597 u32 flash_linear_addr;
3598 u32 flash_data = 0;
3599 s32 ret_val = -E1000_ERR_NVM;
3600 u8 count = 0;
3601
3602 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3603 return -E1000_ERR_NVM;
3604
3605 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3606 hw->nvm.flash_base_addr);
3607
3608 do {
3609 udelay(1);
3610 /* Steps */
3611 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3612 if (ret_val)
3613 break;
3614
3615 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3616 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3617 hsflctl.hsf_ctrl.fldbcount = size - 1;
3618 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3619 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3620
3621 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3622
3623 ret_val =
3624 e1000_flash_cycle_ich8lan(hw,
3625 ICH_FLASH_READ_COMMAND_TIMEOUT);
3626
3627 /* Check if FCERR is set to 1, if set to 1, clear it
3628 * and try the whole sequence a few more times, else
3629 * read in (shift in) the Flash Data0, the order is
3630 * least significant byte first msb to lsb
3631 */
3632 if (!ret_val) {
3633 flash_data = er32flash(ICH_FLASH_FDATA0);
3634 if (size == 1)
3635 *data = (u8)(flash_data & 0x000000FF);
3636 else if (size == 2)
3637 *data = (u16)(flash_data & 0x0000FFFF);
3638 break;
3639 } else {
3640 /* If we've gotten here, then things are probably
3641 * completely hosed, but if the error condition is
3642 * detected, it won't hurt to give it another try...
3643 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3644 */
3645 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3646 if (hsfsts.hsf_status.flcerr) {
3647 /* Repeat for some time before giving up. */
3648 continue;
3649 } else if (!hsfsts.hsf_status.flcdone) {
3650 e_dbg("Timeout error - flash cycle did not complete.\n");
3651 break;
3652 }
3653 }
3654 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3655
3656 return ret_val;
3657 }
3658
3659 /**
3660 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3661 * @hw: pointer to the HW structure
3662 * @offset: The offset (in bytes) of the dword to read.
3663 * @data: Pointer to the dword to store the value read.
3664 *
3665 * Reads a byte or word from the NVM using the flash access registers.
3666 **/
3667
3668 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3669 u32 *data)
3670 {
3671 union ich8_hws_flash_status hsfsts;
3672 union ich8_hws_flash_ctrl hsflctl;
3673 u32 flash_linear_addr;
3674 s32 ret_val = -E1000_ERR_NVM;
3675 u8 count = 0;
3676
3677 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3678 return -E1000_ERR_NVM;
3679 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3680 hw->nvm.flash_base_addr);
3681
3682 do {
3683 udelay(1);
3684 /* Steps */
3685 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3686 if (ret_val)
3687 break;
3688 /* In SPT, This register is in Lan memory space, not flash.
3689 * Therefore, only 32 bit access is supported
3690 */
3691 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3692
3693 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3694 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3695 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3696 /* In SPT, This register is in Lan memory space, not flash.
3697 * Therefore, only 32 bit access is supported
3698 */
3699 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3700 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3701
3702 ret_val =
3703 e1000_flash_cycle_ich8lan(hw,
3704 ICH_FLASH_READ_COMMAND_TIMEOUT);
3705
3706 /* Check if FCERR is set to 1, if set to 1, clear it
3707 * and try the whole sequence a few more times, else
3708 * read in (shift in) the Flash Data0, the order is
3709 * least significant byte first msb to lsb
3710 */
3711 if (!ret_val) {
3712 *data = er32flash(ICH_FLASH_FDATA0);
3713 break;
3714 } else {
3715 /* If we've gotten here, then things are probably
3716 * completely hosed, but if the error condition is
3717 * detected, it won't hurt to give it another try...
3718 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3719 */
3720 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3721 if (hsfsts.hsf_status.flcerr) {
3722 /* Repeat for some time before giving up. */
3723 continue;
3724 } else if (!hsfsts.hsf_status.flcdone) {
3725 e_dbg("Timeout error - flash cycle did not complete.\n");
3726 break;
3727 }
3728 }
3729 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3730
3731 return ret_val;
3732 }
3733
3734 /**
3735 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3736 * @hw: pointer to the HW structure
3737 * @offset: The offset (in bytes) of the word(s) to write.
3738 * @words: Size of data to write in words
3739 * @data: Pointer to the word(s) to write at offset.
3740 *
3741 * Writes a byte or word to the NVM using the flash access registers.
3742 **/
3743 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3744 u16 *data)
3745 {
3746 struct e1000_nvm_info *nvm = &hw->nvm;
3747 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3748 u16 i;
3749
3750 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3751 (words == 0)) {
3752 e_dbg("nvm parameter(s) out of bounds\n");
3753 return -E1000_ERR_NVM;
3754 }
3755
3756 nvm->ops.acquire(hw);
3757
3758 for (i = 0; i < words; i++) {
3759 dev_spec->shadow_ram[offset + i].modified = true;
3760 dev_spec->shadow_ram[offset + i].value = data[i];
3761 }
3762
3763 nvm->ops.release(hw);
3764
3765 return 0;
3766 }
3767
3768 /**
3769 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3770 * @hw: pointer to the HW structure
3771 *
3772 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3773 * which writes the checksum to the shadow ram. The changes in the shadow
3774 * ram are then committed to the EEPROM by processing each bank at a time
3775 * checking for the modified bit and writing only the pending changes.
3776 * After a successful commit, the shadow ram is cleared and is ready for
3777 * future writes.
3778 **/
3779 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3780 {
3781 struct e1000_nvm_info *nvm = &hw->nvm;
3782 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3783 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3784 s32 ret_val;
3785 u32 dword = 0;
3786
3787 ret_val = e1000e_update_nvm_checksum_generic(hw);
3788 if (ret_val)
3789 goto out;
3790
3791 if (nvm->type != e1000_nvm_flash_sw)
3792 goto out;
3793
3794 nvm->ops.acquire(hw);
3795
3796 /* We're writing to the opposite bank so if we're on bank 1,
3797 * write to bank 0 etc. We also need to erase the segment that
3798 * is going to be written
3799 */
3800 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3801 if (ret_val) {
3802 e_dbg("Could not detect valid bank, assuming bank 0\n");
3803 bank = 0;
3804 }
3805
3806 if (bank == 0) {
3807 new_bank_offset = nvm->flash_bank_size;
3808 old_bank_offset = 0;
3809 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3810 if (ret_val)
3811 goto release;
3812 } else {
3813 old_bank_offset = nvm->flash_bank_size;
3814 new_bank_offset = 0;
3815 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3816 if (ret_val)
3817 goto release;
3818 }
3819 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3820 /* Determine whether to write the value stored
3821 * in the other NVM bank or a modified value stored
3822 * in the shadow RAM
3823 */
3824 ret_val = e1000_read_flash_dword_ich8lan(hw,
3825 i + old_bank_offset,
3826 &dword);
3827
3828 if (dev_spec->shadow_ram[i].modified) {
3829 dword &= 0xffff0000;
3830 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3831 }
3832 if (dev_spec->shadow_ram[i + 1].modified) {
3833 dword &= 0x0000ffff;
3834 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3835 << 16);
3836 }
3837 if (ret_val)
3838 break;
3839
3840 /* If the word is 0x13, then make sure the signature bits
3841 * (15:14) are 11b until the commit has completed.
3842 * This will allow us to write 10b which indicates the
3843 * signature is valid. We want to do this after the write
3844 * has completed so that we don't mark the segment valid
3845 * while the write is still in progress
3846 */
3847 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3848 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3849
3850 /* Convert offset to bytes. */
3851 act_offset = (i + new_bank_offset) << 1;
3852
3853 usleep_range(100, 200);
3854
3855 /* Write the data to the new bank. Offset in words */
3856 act_offset = i + new_bank_offset;
3857 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3858 dword);
3859 if (ret_val)
3860 break;
3861 }
3862
3863 /* Don't bother writing the segment valid bits if sector
3864 * programming failed.
3865 */
3866 if (ret_val) {
3867 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3868 e_dbg("Flash commit failed.\n");
3869 goto release;
3870 }
3871
3872 /* Finally validate the new segment by setting bit 15:14
3873 * to 10b in word 0x13 , this can be done without an
3874 * erase as well since these bits are 11 to start with
3875 * and we need to change bit 14 to 0b
3876 */
3877 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3878
3879 /*offset in words but we read dword */
3880 --act_offset;
3881 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3882
3883 if (ret_val)
3884 goto release;
3885
3886 dword &= 0xBFFFFFFF;
3887 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3888
3889 if (ret_val)
3890 goto release;
3891
3892 /* And invalidate the previously valid segment by setting
3893 * its signature word (0x13) high_byte to 0b. This can be
3894 * done without an erase because flash erase sets all bits
3895 * to 1's. We can write 1's to 0's without an erase
3896 */
3897 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3898
3899 /* offset in words but we read dword */
3900 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3901 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3902
3903 if (ret_val)
3904 goto release;
3905
3906 dword &= 0x00FFFFFF;
3907 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3908
3909 if (ret_val)
3910 goto release;
3911
3912 /* Great! Everything worked, we can now clear the cached entries. */
3913 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3914 dev_spec->shadow_ram[i].modified = false;
3915 dev_spec->shadow_ram[i].value = 0xFFFF;
3916 }
3917
3918 release:
3919 nvm->ops.release(hw);
3920
3921 /* Reload the EEPROM, or else modifications will not appear
3922 * until after the next adapter reset.
3923 */
3924 if (!ret_val) {
3925 nvm->ops.reload(hw);
3926 usleep_range(10000, 11000);
3927 }
3928
3929 out:
3930 if (ret_val)
3931 e_dbg("NVM update error: %d\n", ret_val);
3932
3933 return ret_val;
3934 }
3935
3936 /**
3937 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3938 * @hw: pointer to the HW structure
3939 *
3940 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3941 * which writes the checksum to the shadow ram. The changes in the shadow
3942 * ram are then committed to the EEPROM by processing each bank at a time
3943 * checking for the modified bit and writing only the pending changes.
3944 * After a successful commit, the shadow ram is cleared and is ready for
3945 * future writes.
3946 **/
3947 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3948 {
3949 struct e1000_nvm_info *nvm = &hw->nvm;
3950 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3951 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3952 s32 ret_val;
3953 u16 data = 0;
3954
3955 ret_val = e1000e_update_nvm_checksum_generic(hw);
3956 if (ret_val)
3957 goto out;
3958
3959 if (nvm->type != e1000_nvm_flash_sw)
3960 goto out;
3961
3962 nvm->ops.acquire(hw);
3963
3964 /* We're writing to the opposite bank so if we're on bank 1,
3965 * write to bank 0 etc. We also need to erase the segment that
3966 * is going to be written
3967 */
3968 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3969 if (ret_val) {
3970 e_dbg("Could not detect valid bank, assuming bank 0\n");
3971 bank = 0;
3972 }
3973
3974 if (bank == 0) {
3975 new_bank_offset = nvm->flash_bank_size;
3976 old_bank_offset = 0;
3977 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3978 if (ret_val)
3979 goto release;
3980 } else {
3981 old_bank_offset = nvm->flash_bank_size;
3982 new_bank_offset = 0;
3983 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3984 if (ret_val)
3985 goto release;
3986 }
3987 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3988 if (dev_spec->shadow_ram[i].modified) {
3989 data = dev_spec->shadow_ram[i].value;
3990 } else {
3991 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3992 old_bank_offset,
3993 &data);
3994 if (ret_val)
3995 break;
3996 }
3997
3998 /* If the word is 0x13, then make sure the signature bits
3999 * (15:14) are 11b until the commit has completed.
4000 * This will allow us to write 10b which indicates the
4001 * signature is valid. We want to do this after the write
4002 * has completed so that we don't mark the segment valid
4003 * while the write is still in progress
4004 */
4005 if (i == E1000_ICH_NVM_SIG_WORD)
4006 data |= E1000_ICH_NVM_SIG_MASK;
4007
4008 /* Convert offset to bytes. */
4009 act_offset = (i + new_bank_offset) << 1;
4010
4011 usleep_range(100, 200);
4012 /* Write the bytes to the new bank. */
4013 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4014 act_offset,
4015 (u8)data);
4016 if (ret_val)
4017 break;
4018
4019 usleep_range(100, 200);
4020 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4021 act_offset + 1,
4022 (u8)(data >> 8));
4023 if (ret_val)
4024 break;
4025 }
4026
4027 /* Don't bother writing the segment valid bits if sector
4028 * programming failed.
4029 */
4030 if (ret_val) {
4031 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4032 e_dbg("Flash commit failed.\n");
4033 goto release;
4034 }
4035
4036 /* Finally validate the new segment by setting bit 15:14
4037 * to 10b in word 0x13 , this can be done without an
4038 * erase as well since these bits are 11 to start with
4039 * and we need to change bit 14 to 0b
4040 */
4041 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4042 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4043 if (ret_val)
4044 goto release;
4045
4046 data &= 0xBFFF;
4047 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4048 act_offset * 2 + 1,
4049 (u8)(data >> 8));
4050 if (ret_val)
4051 goto release;
4052
4053 /* And invalidate the previously valid segment by setting
4054 * its signature word (0x13) high_byte to 0b. This can be
4055 * done without an erase because flash erase sets all bits
4056 * to 1's. We can write 1's to 0's without an erase
4057 */
4058 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4059 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4060 if (ret_val)
4061 goto release;
4062
4063 /* Great! Everything worked, we can now clear the cached entries. */
4064 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4065 dev_spec->shadow_ram[i].modified = false;
4066 dev_spec->shadow_ram[i].value = 0xFFFF;
4067 }
4068
4069 release:
4070 nvm->ops.release(hw);
4071
4072 /* Reload the EEPROM, or else modifications will not appear
4073 * until after the next adapter reset.
4074 */
4075 if (!ret_val) {
4076 nvm->ops.reload(hw);
4077 usleep_range(10000, 11000);
4078 }
4079
4080 out:
4081 if (ret_val)
4082 e_dbg("NVM update error: %d\n", ret_val);
4083
4084 return ret_val;
4085 }
4086
4087 /**
4088 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4089 * @hw: pointer to the HW structure
4090 *
4091 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4092 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4093 * calculated, in which case we need to calculate the checksum and set bit 6.
4094 **/
4095 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4096 {
4097 s32 ret_val;
4098 u16 data;
4099 u16 word;
4100 u16 valid_csum_mask;
4101
4102 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4103 * the checksum needs to be fixed. This bit is an indication that
4104 * the NVM was prepared by OEM software and did not calculate
4105 * the checksum...a likely scenario.
4106 */
4107 switch (hw->mac.type) {
4108 case e1000_pch_lpt:
4109 case e1000_pch_spt:
4110 case e1000_pch_cnp:
4111 case e1000_pch_tgp:
4112 case e1000_pch_adp:
4113 case e1000_pch_mtp:
4114 word = NVM_COMPAT;
4115 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4116 break;
4117 default:
4118 word = NVM_FUTURE_INIT_WORD1;
4119 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4120 break;
4121 }
4122
4123 ret_val = e1000_read_nvm(hw, word, 1, &data);
4124 if (ret_val)
4125 return ret_val;
4126
4127 if (!(data & valid_csum_mask)) {
4128 data |= valid_csum_mask;
4129 ret_val = e1000_write_nvm(hw, word, 1, &data);
4130 if (ret_val)
4131 return ret_val;
4132 ret_val = e1000e_update_nvm_checksum(hw);
4133 if (ret_val)
4134 return ret_val;
4135 }
4136
4137 return e1000e_validate_nvm_checksum_generic(hw);
4138 }
4139
4140 /**
4141 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4142 * @hw: pointer to the HW structure
4143 *
4144 * To prevent malicious write/erase of the NVM, set it to be read-only
4145 * so that the hardware ignores all write/erase cycles of the NVM via
4146 * the flash control registers. The shadow-ram copy of the NVM will
4147 * still be updated, however any updates to this copy will not stick
4148 * across driver reloads.
4149 **/
4150 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4151 {
4152 struct e1000_nvm_info *nvm = &hw->nvm;
4153 union ich8_flash_protected_range pr0;
4154 union ich8_hws_flash_status hsfsts;
4155 u32 gfpreg;
4156
4157 nvm->ops.acquire(hw);
4158
4159 gfpreg = er32flash(ICH_FLASH_GFPREG);
4160
4161 /* Write-protect GbE Sector of NVM */
4162 pr0.regval = er32flash(ICH_FLASH_PR0);
4163 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4164 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4165 pr0.range.wpe = true;
4166 ew32flash(ICH_FLASH_PR0, pr0.regval);
4167
4168 /* Lock down a subset of GbE Flash Control Registers, e.g.
4169 * PR0 to prevent the write-protection from being lifted.
4170 * Once FLOCKDN is set, the registers protected by it cannot
4171 * be written until FLOCKDN is cleared by a hardware reset.
4172 */
4173 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4174 hsfsts.hsf_status.flockdn = true;
4175 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4176
4177 nvm->ops.release(hw);
4178 }
4179
4180 /**
4181 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4182 * @hw: pointer to the HW structure
4183 * @offset: The offset (in bytes) of the byte/word to read.
4184 * @size: Size of data to read, 1=byte 2=word
4185 * @data: The byte(s) to write to the NVM.
4186 *
4187 * Writes one/two bytes to the NVM using the flash access registers.
4188 **/
4189 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4190 u8 size, u16 data)
4191 {
4192 union ich8_hws_flash_status hsfsts;
4193 union ich8_hws_flash_ctrl hsflctl;
4194 u32 flash_linear_addr;
4195 u32 flash_data = 0;
4196 s32 ret_val;
4197 u8 count = 0;
4198
4199 if (hw->mac.type >= e1000_pch_spt) {
4200 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4201 return -E1000_ERR_NVM;
4202 } else {
4203 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4204 return -E1000_ERR_NVM;
4205 }
4206
4207 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4208 hw->nvm.flash_base_addr);
4209
4210 do {
4211 udelay(1);
4212 /* Steps */
4213 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4214 if (ret_val)
4215 break;
4216 /* In SPT, This register is in Lan memory space, not
4217 * flash. Therefore, only 32 bit access is supported
4218 */
4219 if (hw->mac.type >= e1000_pch_spt)
4220 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4221 else
4222 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4223
4224 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4225 hsflctl.hsf_ctrl.fldbcount = size - 1;
4226 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4227 /* In SPT, This register is in Lan memory space,
4228 * not flash. Therefore, only 32 bit access is
4229 * supported
4230 */
4231 if (hw->mac.type >= e1000_pch_spt)
4232 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4233 else
4234 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4235
4236 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4237
4238 if (size == 1)
4239 flash_data = (u32)data & 0x00FF;
4240 else
4241 flash_data = (u32)data;
4242
4243 ew32flash(ICH_FLASH_FDATA0, flash_data);
4244
4245 /* check if FCERR is set to 1 , if set to 1, clear it
4246 * and try the whole sequence a few more times else done
4247 */
4248 ret_val =
4249 e1000_flash_cycle_ich8lan(hw,
4250 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4251 if (!ret_val)
4252 break;
4253
4254 /* If we're here, then things are most likely
4255 * completely hosed, but if the error condition
4256 * is detected, it won't hurt to give it another
4257 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4258 */
4259 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4260 if (hsfsts.hsf_status.flcerr)
4261 /* Repeat for some time before giving up. */
4262 continue;
4263 if (!hsfsts.hsf_status.flcdone) {
4264 e_dbg("Timeout error - flash cycle did not complete.\n");
4265 break;
4266 }
4267 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4268
4269 return ret_val;
4270 }
4271
4272 /**
4273 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4274 * @hw: pointer to the HW structure
4275 * @offset: The offset (in bytes) of the dwords to read.
4276 * @data: The 4 bytes to write to the NVM.
4277 *
4278 * Writes one/two/four bytes to the NVM using the flash access registers.
4279 **/
4280 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4281 u32 data)
4282 {
4283 union ich8_hws_flash_status hsfsts;
4284 union ich8_hws_flash_ctrl hsflctl;
4285 u32 flash_linear_addr;
4286 s32 ret_val;
4287 u8 count = 0;
4288
4289 if (hw->mac.type >= e1000_pch_spt) {
4290 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4291 return -E1000_ERR_NVM;
4292 }
4293 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4294 hw->nvm.flash_base_addr);
4295 do {
4296 udelay(1);
4297 /* Steps */
4298 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4299 if (ret_val)
4300 break;
4301
4302 /* In SPT, This register is in Lan memory space, not
4303 * flash. Therefore, only 32 bit access is supported
4304 */
4305 if (hw->mac.type >= e1000_pch_spt)
4306 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4307 >> 16;
4308 else
4309 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4310
4311 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4312 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4313
4314 /* In SPT, This register is in Lan memory space,
4315 * not flash. Therefore, only 32 bit access is
4316 * supported
4317 */
4318 if (hw->mac.type >= e1000_pch_spt)
4319 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4320 else
4321 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4322
4323 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4324
4325 ew32flash(ICH_FLASH_FDATA0, data);
4326
4327 /* check if FCERR is set to 1 , if set to 1, clear it
4328 * and try the whole sequence a few more times else done
4329 */
4330 ret_val =
4331 e1000_flash_cycle_ich8lan(hw,
4332 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4333
4334 if (!ret_val)
4335 break;
4336
4337 /* If we're here, then things are most likely
4338 * completely hosed, but if the error condition
4339 * is detected, it won't hurt to give it another
4340 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4341 */
4342 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4343
4344 if (hsfsts.hsf_status.flcerr)
4345 /* Repeat for some time before giving up. */
4346 continue;
4347 if (!hsfsts.hsf_status.flcdone) {
4348 e_dbg("Timeout error - flash cycle did not complete.\n");
4349 break;
4350 }
4351 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4352
4353 return ret_val;
4354 }
4355
4356 /**
4357 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4358 * @hw: pointer to the HW structure
4359 * @offset: The index of the byte to read.
4360 * @data: The byte to write to the NVM.
4361 *
4362 * Writes a single byte to the NVM using the flash access registers.
4363 **/
4364 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4365 u8 data)
4366 {
4367 u16 word = (u16)data;
4368
4369 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4370 }
4371
4372 /**
4373 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4374 * @hw: pointer to the HW structure
4375 * @offset: The offset of the word to write.
4376 * @dword: The dword to write to the NVM.
4377 *
4378 * Writes a single dword to the NVM using the flash access registers.
4379 * Goes through a retry algorithm before giving up.
4380 **/
4381 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4382 u32 offset, u32 dword)
4383 {
4384 s32 ret_val;
4385 u16 program_retries;
4386
4387 /* Must convert word offset into bytes. */
4388 offset <<= 1;
4389 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4390
4391 if (!ret_val)
4392 return ret_val;
4393 for (program_retries = 0; program_retries < 100; program_retries++) {
4394 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4395 usleep_range(100, 200);
4396 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4397 if (!ret_val)
4398 break;
4399 }
4400 if (program_retries == 100)
4401 return -E1000_ERR_NVM;
4402
4403 return 0;
4404 }
4405
4406 /**
4407 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4408 * @hw: pointer to the HW structure
4409 * @offset: The offset of the byte to write.
4410 * @byte: The byte to write to the NVM.
4411 *
4412 * Writes a single byte to the NVM using the flash access registers.
4413 * Goes through a retry algorithm before giving up.
4414 **/
4415 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4416 u32 offset, u8 byte)
4417 {
4418 s32 ret_val;
4419 u16 program_retries;
4420
4421 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4422 if (!ret_val)
4423 return ret_val;
4424
4425 for (program_retries = 0; program_retries < 100; program_retries++) {
4426 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4427 usleep_range(100, 200);
4428 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4429 if (!ret_val)
4430 break;
4431 }
4432 if (program_retries == 100)
4433 return -E1000_ERR_NVM;
4434
4435 return 0;
4436 }
4437
4438 /**
4439 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4440 * @hw: pointer to the HW structure
4441 * @bank: 0 for first bank, 1 for second bank, etc.
4442 *
4443 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4444 * bank N is 4096 * N + flash_reg_addr.
4445 **/
4446 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4447 {
4448 struct e1000_nvm_info *nvm = &hw->nvm;
4449 union ich8_hws_flash_status hsfsts;
4450 union ich8_hws_flash_ctrl hsflctl;
4451 u32 flash_linear_addr;
4452 /* bank size is in 16bit words - adjust to bytes */
4453 u32 flash_bank_size = nvm->flash_bank_size * 2;
4454 s32 ret_val;
4455 s32 count = 0;
4456 s32 j, iteration, sector_size;
4457
4458 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4459
4460 /* Determine HW Sector size: Read BERASE bits of hw flash status
4461 * register
4462 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4463 * consecutive sectors. The start index for the nth Hw sector
4464 * can be calculated as = bank * 4096 + n * 256
4465 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4466 * The start index for the nth Hw sector can be calculated
4467 * as = bank * 4096
4468 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4469 * (ich9 only, otherwise error condition)
4470 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4471 */
4472 switch (hsfsts.hsf_status.berasesz) {
4473 case 0:
4474 /* Hw sector size 256 */
4475 sector_size = ICH_FLASH_SEG_SIZE_256;
4476 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4477 break;
4478 case 1:
4479 sector_size = ICH_FLASH_SEG_SIZE_4K;
4480 iteration = 1;
4481 break;
4482 case 2:
4483 sector_size = ICH_FLASH_SEG_SIZE_8K;
4484 iteration = 1;
4485 break;
4486 case 3:
4487 sector_size = ICH_FLASH_SEG_SIZE_64K;
4488 iteration = 1;
4489 break;
4490 default:
4491 return -E1000_ERR_NVM;
4492 }
4493
4494 /* Start with the base address, then add the sector offset. */
4495 flash_linear_addr = hw->nvm.flash_base_addr;
4496 flash_linear_addr += (bank) ? flash_bank_size : 0;
4497
4498 for (j = 0; j < iteration; j++) {
4499 do {
4500 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4501
4502 /* Steps */
4503 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4504 if (ret_val)
4505 return ret_val;
4506
4507 /* Write a value 11 (block Erase) in Flash
4508 * Cycle field in hw flash control
4509 */
4510 if (hw->mac.type >= e1000_pch_spt)
4511 hsflctl.regval =
4512 er32flash(ICH_FLASH_HSFSTS) >> 16;
4513 else
4514 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4515
4516 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4517 if (hw->mac.type >= e1000_pch_spt)
4518 ew32flash(ICH_FLASH_HSFSTS,
4519 hsflctl.regval << 16);
4520 else
4521 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4522
4523 /* Write the last 24 bits of an index within the
4524 * block into Flash Linear address field in Flash
4525 * Address.
4526 */
4527 flash_linear_addr += (j * sector_size);
4528 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4529
4530 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4531 if (!ret_val)
4532 break;
4533
4534 /* Check if FCERR is set to 1. If 1,
4535 * clear it and try the whole sequence
4536 * a few more times else Done
4537 */
4538 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4539 if (hsfsts.hsf_status.flcerr)
4540 /* repeat for some time before giving up */
4541 continue;
4542 else if (!hsfsts.hsf_status.flcdone)
4543 return ret_val;
4544 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4545 }
4546
4547 return 0;
4548 }
4549
4550 /**
4551 * e1000_valid_led_default_ich8lan - Set the default LED settings
4552 * @hw: pointer to the HW structure
4553 * @data: Pointer to the LED settings
4554 *
4555 * Reads the LED default settings from the NVM to data. If the NVM LED
4556 * settings is all 0's or F's, set the LED default to a valid LED default
4557 * setting.
4558 **/
4559 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4560 {
4561 s32 ret_val;
4562
4563 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4564 if (ret_val) {
4565 e_dbg("NVM Read Error\n");
4566 return ret_val;
4567 }
4568
4569 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4570 *data = ID_LED_DEFAULT_ICH8LAN;
4571
4572 return 0;
4573 }
4574
4575 /**
4576 * e1000_id_led_init_pchlan - store LED configurations
4577 * @hw: pointer to the HW structure
4578 *
4579 * PCH does not control LEDs via the LEDCTL register, rather it uses
4580 * the PHY LED configuration register.
4581 *
4582 * PCH also does not have an "always on" or "always off" mode which
4583 * complicates the ID feature. Instead of using the "on" mode to indicate
4584 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4585 * use "link_up" mode. The LEDs will still ID on request if there is no
4586 * link based on logic in e1000_led_[on|off]_pchlan().
4587 **/
4588 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4589 {
4590 struct e1000_mac_info *mac = &hw->mac;
4591 s32 ret_val;
4592 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4593 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4594 u16 data, i, temp, shift;
4595
4596 /* Get default ID LED modes */
4597 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4598 if (ret_val)
4599 return ret_val;
4600
4601 mac->ledctl_default = er32(LEDCTL);
4602 mac->ledctl_mode1 = mac->ledctl_default;
4603 mac->ledctl_mode2 = mac->ledctl_default;
4604
4605 for (i = 0; i < 4; i++) {
4606 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4607 shift = (i * 5);
4608 switch (temp) {
4609 case ID_LED_ON1_DEF2:
4610 case ID_LED_ON1_ON2:
4611 case ID_LED_ON1_OFF2:
4612 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4613 mac->ledctl_mode1 |= (ledctl_on << shift);
4614 break;
4615 case ID_LED_OFF1_DEF2:
4616 case ID_LED_OFF1_ON2:
4617 case ID_LED_OFF1_OFF2:
4618 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4619 mac->ledctl_mode1 |= (ledctl_off << shift);
4620 break;
4621 default:
4622 /* Do nothing */
4623 break;
4624 }
4625 switch (temp) {
4626 case ID_LED_DEF1_ON2:
4627 case ID_LED_ON1_ON2:
4628 case ID_LED_OFF1_ON2:
4629 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4630 mac->ledctl_mode2 |= (ledctl_on << shift);
4631 break;
4632 case ID_LED_DEF1_OFF2:
4633 case ID_LED_ON1_OFF2:
4634 case ID_LED_OFF1_OFF2:
4635 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4636 mac->ledctl_mode2 |= (ledctl_off << shift);
4637 break;
4638 default:
4639 /* Do nothing */
4640 break;
4641 }
4642 }
4643
4644 return 0;
4645 }
4646
4647 /**
4648 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4649 * @hw: pointer to the HW structure
4650 *
4651 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4652 * register, so the the bus width is hard coded.
4653 **/
4654 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4655 {
4656 struct e1000_bus_info *bus = &hw->bus;
4657 s32 ret_val;
4658
4659 ret_val = e1000e_get_bus_info_pcie(hw);
4660
4661 /* ICH devices are "PCI Express"-ish. They have
4662 * a configuration space, but do not contain
4663 * PCI Express Capability registers, so bus width
4664 * must be hardcoded.
4665 */
4666 if (bus->width == e1000_bus_width_unknown)
4667 bus->width = e1000_bus_width_pcie_x1;
4668
4669 return ret_val;
4670 }
4671
4672 /**
4673 * e1000_reset_hw_ich8lan - Reset the hardware
4674 * @hw: pointer to the HW structure
4675 *
4676 * Does a full reset of the hardware which includes a reset of the PHY and
4677 * MAC.
4678 **/
4679 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4680 {
4681 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4682 u16 kum_cfg;
4683 u32 ctrl, reg;
4684 s32 ret_val;
4685
4686 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4687 * on the last TLP read/write transaction when MAC is reset.
4688 */
4689 ret_val = e1000e_disable_pcie_master(hw);
4690 if (ret_val)
4691 e_dbg("PCI-E Master disable polling has failed.\n");
4692
4693 e_dbg("Masking off all interrupts\n");
4694 ew32(IMC, 0xffffffff);
4695
4696 /* Disable the Transmit and Receive units. Then delay to allow
4697 * any pending transactions to complete before we hit the MAC
4698 * with the global reset.
4699 */
4700 ew32(RCTL, 0);
4701 ew32(TCTL, E1000_TCTL_PSP);
4702 e1e_flush();
4703
4704 usleep_range(10000, 11000);
4705
4706 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4707 if (hw->mac.type == e1000_ich8lan) {
4708 /* Set Tx and Rx buffer allocation to 8k apiece. */
4709 ew32(PBA, E1000_PBA_8K);
4710 /* Set Packet Buffer Size to 16k. */
4711 ew32(PBS, E1000_PBS_16K);
4712 }
4713
4714 if (hw->mac.type == e1000_pchlan) {
4715 /* Save the NVM K1 bit setting */
4716 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4717 if (ret_val)
4718 return ret_val;
4719
4720 if (kum_cfg & E1000_NVM_K1_ENABLE)
4721 dev_spec->nvm_k1_enabled = true;
4722 else
4723 dev_spec->nvm_k1_enabled = false;
4724 }
4725
4726 ctrl = er32(CTRL);
4727
4728 if (!hw->phy.ops.check_reset_block(hw)) {
4729 /* Full-chip reset requires MAC and PHY reset at the same
4730 * time to make sure the interface between MAC and the
4731 * external PHY is reset.
4732 */
4733 ctrl |= E1000_CTRL_PHY_RST;
4734
4735 /* Gate automatic PHY configuration by hardware on
4736 * non-managed 82579
4737 */
4738 if ((hw->mac.type == e1000_pch2lan) &&
4739 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4740 e1000_gate_hw_phy_config_ich8lan(hw, true);
4741 }
4742 ret_val = e1000_acquire_swflag_ich8lan(hw);
4743 e_dbg("Issuing a global reset to ich8lan\n");
4744 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4745 /* cannot issue a flush here because it hangs the hardware */
4746 msleep(20);
4747
4748 /* Set Phy Config Counter to 50msec */
4749 if (hw->mac.type == e1000_pch2lan) {
4750 reg = er32(FEXTNVM3);
4751 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4752 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4753 ew32(FEXTNVM3, reg);
4754 }
4755
4756 if (!ret_val)
4757 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4758
4759 if (ctrl & E1000_CTRL_PHY_RST) {
4760 ret_val = hw->phy.ops.get_cfg_done(hw);
4761 if (ret_val)
4762 return ret_val;
4763
4764 ret_val = e1000_post_phy_reset_ich8lan(hw);
4765 if (ret_val)
4766 return ret_val;
4767 }
4768
4769 /* For PCH, this write will make sure that any noise
4770 * will be detected as a CRC error and be dropped rather than show up
4771 * as a bad packet to the DMA engine.
4772 */
4773 if (hw->mac.type == e1000_pchlan)
4774 ew32(CRC_OFFSET, 0x65656565);
4775
4776 ew32(IMC, 0xffffffff);
4777 er32(ICR);
4778
4779 reg = er32(KABGTXD);
4780 reg |= E1000_KABGTXD_BGSQLBIAS;
4781 ew32(KABGTXD, reg);
4782
4783 return 0;
4784 }
4785
4786 /**
4787 * e1000_init_hw_ich8lan - Initialize the hardware
4788 * @hw: pointer to the HW structure
4789 *
4790 * Prepares the hardware for transmit and receive by doing the following:
4791 * - initialize hardware bits
4792 * - initialize LED identification
4793 * - setup receive address registers
4794 * - setup flow control
4795 * - setup transmit descriptors
4796 * - clear statistics
4797 **/
4798 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4799 {
4800 struct e1000_mac_info *mac = &hw->mac;
4801 u32 ctrl_ext, txdctl, snoop;
4802 s32 ret_val;
4803 u16 i;
4804
4805 e1000_initialize_hw_bits_ich8lan(hw);
4806
4807 /* Initialize identification LED */
4808 ret_val = mac->ops.id_led_init(hw);
4809 /* An error is not fatal and we should not stop init due to this */
4810 if (ret_val)
4811 e_dbg("Error initializing identification LED\n");
4812
4813 /* Setup the receive address. */
4814 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4815
4816 /* Zero out the Multicast HASH table */
4817 e_dbg("Zeroing the MTA\n");
4818 for (i = 0; i < mac->mta_reg_count; i++)
4819 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4820
4821 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4822 * the ME. Disable wakeup by clearing the host wakeup bit.
4823 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4824 */
4825 if (hw->phy.type == e1000_phy_82578) {
4826 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4827 i &= ~BM_WUC_HOST_WU_BIT;
4828 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4829 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4830 if (ret_val)
4831 return ret_val;
4832 }
4833
4834 /* Setup link and flow control */
4835 ret_val = mac->ops.setup_link(hw);
4836
4837 /* Set the transmit descriptor write-back policy for both queues */
4838 txdctl = er32(TXDCTL(0));
4839 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4840 E1000_TXDCTL_FULL_TX_DESC_WB);
4841 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4842 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4843 ew32(TXDCTL(0), txdctl);
4844 txdctl = er32(TXDCTL(1));
4845 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4846 E1000_TXDCTL_FULL_TX_DESC_WB);
4847 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4848 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4849 ew32(TXDCTL(1), txdctl);
4850
4851 /* ICH8 has opposite polarity of no_snoop bits.
4852 * By default, we should use snoop behavior.
4853 */
4854 if (mac->type == e1000_ich8lan)
4855 snoop = PCIE_ICH8_SNOOP_ALL;
4856 else
4857 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4858 e1000e_set_pcie_no_snoop(hw, snoop);
4859
4860 ctrl_ext = er32(CTRL_EXT);
4861 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4862 ew32(CTRL_EXT, ctrl_ext);
4863
4864 /* Clear all of the statistics registers (clear on read). It is
4865 * important that we do this after we have tried to establish link
4866 * because the symbol error count will increment wildly if there
4867 * is no link.
4868 */
4869 e1000_clear_hw_cntrs_ich8lan(hw);
4870
4871 return ret_val;
4872 }
4873
4874 /**
4875 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4876 * @hw: pointer to the HW structure
4877 *
4878 * Sets/Clears required hardware bits necessary for correctly setting up the
4879 * hardware for transmit and receive.
4880 **/
4881 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4882 {
4883 u32 reg;
4884
4885 /* Extended Device Control */
4886 reg = er32(CTRL_EXT);
4887 reg |= BIT(22);
4888 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4889 if (hw->mac.type >= e1000_pchlan)
4890 reg |= E1000_CTRL_EXT_PHYPDEN;
4891 ew32(CTRL_EXT, reg);
4892
4893 /* Transmit Descriptor Control 0 */
4894 reg = er32(TXDCTL(0));
4895 reg |= BIT(22);
4896 ew32(TXDCTL(0), reg);
4897
4898 /* Transmit Descriptor Control 1 */
4899 reg = er32(TXDCTL(1));
4900 reg |= BIT(22);
4901 ew32(TXDCTL(1), reg);
4902
4903 /* Transmit Arbitration Control 0 */
4904 reg = er32(TARC(0));
4905 if (hw->mac.type == e1000_ich8lan)
4906 reg |= BIT(28) | BIT(29);
4907 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4908 ew32(TARC(0), reg);
4909
4910 /* Transmit Arbitration Control 1 */
4911 reg = er32(TARC(1));
4912 if (er32(TCTL) & E1000_TCTL_MULR)
4913 reg &= ~BIT(28);
4914 else
4915 reg |= BIT(28);
4916 reg |= BIT(24) | BIT(26) | BIT(30);
4917 ew32(TARC(1), reg);
4918
4919 /* Device Status */
4920 if (hw->mac.type == e1000_ich8lan) {
4921 reg = er32(STATUS);
4922 reg &= ~BIT(31);
4923 ew32(STATUS, reg);
4924 }
4925
4926 /* work-around descriptor data corruption issue during nfs v2 udp
4927 * traffic, just disable the nfs filtering capability
4928 */
4929 reg = er32(RFCTL);
4930 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4931
4932 /* Disable IPv6 extension header parsing because some malformed
4933 * IPv6 headers can hang the Rx.
4934 */
4935 if (hw->mac.type == e1000_ich8lan)
4936 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4937 ew32(RFCTL, reg);
4938
4939 /* Enable ECC on Lynxpoint */
4940 if (hw->mac.type >= e1000_pch_lpt) {
4941 reg = er32(PBECCSTS);
4942 reg |= E1000_PBECCSTS_ECC_ENABLE;
4943 ew32(PBECCSTS, reg);
4944
4945 reg = er32(CTRL);
4946 reg |= E1000_CTRL_MEHE;
4947 ew32(CTRL, reg);
4948 }
4949 }
4950
4951 /**
4952 * e1000_setup_link_ich8lan - Setup flow control and link settings
4953 * @hw: pointer to the HW structure
4954 *
4955 * Determines which flow control settings to use, then configures flow
4956 * control. Calls the appropriate media-specific link configuration
4957 * function. Assuming the adapter has a valid link partner, a valid link
4958 * should be established. Assumes the hardware has previously been reset
4959 * and the transmitter and receiver are not enabled.
4960 **/
4961 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4962 {
4963 s32 ret_val;
4964
4965 if (hw->phy.ops.check_reset_block(hw))
4966 return 0;
4967
4968 /* ICH parts do not have a word in the NVM to determine
4969 * the default flow control setting, so we explicitly
4970 * set it to full.
4971 */
4972 if (hw->fc.requested_mode == e1000_fc_default) {
4973 /* Workaround h/w hang when Tx flow control enabled */
4974 if (hw->mac.type == e1000_pchlan)
4975 hw->fc.requested_mode = e1000_fc_rx_pause;
4976 else
4977 hw->fc.requested_mode = e1000_fc_full;
4978 }
4979
4980 /* Save off the requested flow control mode for use later. Depending
4981 * on the link partner's capabilities, we may or may not use this mode.
4982 */
4983 hw->fc.current_mode = hw->fc.requested_mode;
4984
4985 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4986
4987 /* Continue to configure the copper link. */
4988 ret_val = hw->mac.ops.setup_physical_interface(hw);
4989 if (ret_val)
4990 return ret_val;
4991
4992 ew32(FCTTV, hw->fc.pause_time);
4993 if ((hw->phy.type == e1000_phy_82578) ||
4994 (hw->phy.type == e1000_phy_82579) ||
4995 (hw->phy.type == e1000_phy_i217) ||
4996 (hw->phy.type == e1000_phy_82577)) {
4997 ew32(FCRTV_PCH, hw->fc.refresh_time);
4998
4999 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5000 hw->fc.pause_time);
5001 if (ret_val)
5002 return ret_val;
5003 }
5004
5005 return e1000e_set_fc_watermarks(hw);
5006 }
5007
5008 /**
5009 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5010 * @hw: pointer to the HW structure
5011 *
5012 * Configures the kumeran interface to the PHY to wait the appropriate time
5013 * when polling the PHY, then call the generic setup_copper_link to finish
5014 * configuring the copper link.
5015 **/
5016 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5017 {
5018 u32 ctrl;
5019 s32 ret_val;
5020 u16 reg_data;
5021
5022 ctrl = er32(CTRL);
5023 ctrl |= E1000_CTRL_SLU;
5024 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5025 ew32(CTRL, ctrl);
5026
5027 /* Set the mac to wait the maximum time between each iteration
5028 * and increase the max iterations when polling the phy;
5029 * this fixes erroneous timeouts at 10Mbps.
5030 */
5031 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5032 if (ret_val)
5033 return ret_val;
5034 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5035 &reg_data);
5036 if (ret_val)
5037 return ret_val;
5038 reg_data |= 0x3F;
5039 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5040 reg_data);
5041 if (ret_val)
5042 return ret_val;
5043
5044 switch (hw->phy.type) {
5045 case e1000_phy_igp_3:
5046 ret_val = e1000e_copper_link_setup_igp(hw);
5047 if (ret_val)
5048 return ret_val;
5049 break;
5050 case e1000_phy_bm:
5051 case e1000_phy_82578:
5052 ret_val = e1000e_copper_link_setup_m88(hw);
5053 if (ret_val)
5054 return ret_val;
5055 break;
5056 case e1000_phy_82577:
5057 case e1000_phy_82579:
5058 ret_val = e1000_copper_link_setup_82577(hw);
5059 if (ret_val)
5060 return ret_val;
5061 break;
5062 case e1000_phy_ife:
5063 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5064 if (ret_val)
5065 return ret_val;
5066
5067 reg_data &= ~IFE_PMC_AUTO_MDIX;
5068
5069 switch (hw->phy.mdix) {
5070 case 1:
5071 reg_data &= ~IFE_PMC_FORCE_MDIX;
5072 break;
5073 case 2:
5074 reg_data |= IFE_PMC_FORCE_MDIX;
5075 break;
5076 case 0:
5077 default:
5078 reg_data |= IFE_PMC_AUTO_MDIX;
5079 break;
5080 }
5081 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5082 if (ret_val)
5083 return ret_val;
5084 break;
5085 default:
5086 break;
5087 }
5088
5089 return e1000e_setup_copper_link(hw);
5090 }
5091
5092 /**
5093 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5094 * @hw: pointer to the HW structure
5095 *
5096 * Calls the PHY specific link setup function and then calls the
5097 * generic setup_copper_link to finish configuring the link for
5098 * Lynxpoint PCH devices
5099 **/
5100 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5101 {
5102 u32 ctrl;
5103 s32 ret_val;
5104
5105 ctrl = er32(CTRL);
5106 ctrl |= E1000_CTRL_SLU;
5107 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5108 ew32(CTRL, ctrl);
5109
5110 ret_val = e1000_copper_link_setup_82577(hw);
5111 if (ret_val)
5112 return ret_val;
5113
5114 return e1000e_setup_copper_link(hw);
5115 }
5116
5117 /**
5118 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5119 * @hw: pointer to the HW structure
5120 * @speed: pointer to store current link speed
5121 * @duplex: pointer to store the current link duplex
5122 *
5123 * Calls the generic get_speed_and_duplex to retrieve the current link
5124 * information and then calls the Kumeran lock loss workaround for links at
5125 * gigabit speeds.
5126 **/
5127 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5128 u16 *duplex)
5129 {
5130 s32 ret_val;
5131
5132 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5133 if (ret_val)
5134 return ret_val;
5135
5136 if ((hw->mac.type == e1000_ich8lan) &&
5137 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5138 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5139 }
5140
5141 return ret_val;
5142 }
5143
5144 /**
5145 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5146 * @hw: pointer to the HW structure
5147 *
5148 * Work-around for 82566 Kumeran PCS lock loss:
5149 * On link status change (i.e. PCI reset, speed change) and link is up and
5150 * speed is gigabit-
5151 * 0) if workaround is optionally disabled do nothing
5152 * 1) wait 1ms for Kumeran link to come up
5153 * 2) check Kumeran Diagnostic register PCS lock loss bit
5154 * 3) if not set the link is locked (all is good), otherwise...
5155 * 4) reset the PHY
5156 * 5) repeat up to 10 times
5157 * Note: this is only called for IGP3 copper when speed is 1gb.
5158 **/
5159 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5160 {
5161 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5162 u32 phy_ctrl;
5163 s32 ret_val;
5164 u16 i, data;
5165 bool link;
5166
5167 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5168 return 0;
5169
5170 /* Make sure link is up before proceeding. If not just return.
5171 * Attempting this while link is negotiating fouled up link
5172 * stability
5173 */
5174 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5175 if (!link)
5176 return 0;
5177
5178 for (i = 0; i < 10; i++) {
5179 /* read once to clear */
5180 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5181 if (ret_val)
5182 return ret_val;
5183 /* and again to get new status */
5184 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5185 if (ret_val)
5186 return ret_val;
5187
5188 /* check for PCS lock */
5189 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5190 return 0;
5191
5192 /* Issue PHY reset */
5193 e1000_phy_hw_reset(hw);
5194 mdelay(5);
5195 }
5196 /* Disable GigE link negotiation */
5197 phy_ctrl = er32(PHY_CTRL);
5198 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5199 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5200 ew32(PHY_CTRL, phy_ctrl);
5201
5202 /* Call gig speed drop workaround on Gig disable before accessing
5203 * any PHY registers
5204 */
5205 e1000e_gig_downshift_workaround_ich8lan(hw);
5206
5207 /* unable to acquire PCS lock */
5208 return -E1000_ERR_PHY;
5209 }
5210
5211 /**
5212 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5213 * @hw: pointer to the HW structure
5214 * @state: boolean value used to set the current Kumeran workaround state
5215 *
5216 * If ICH8, set the current Kumeran workaround state (enabled - true
5217 * /disabled - false).
5218 **/
5219 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5220 bool state)
5221 {
5222 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5223
5224 if (hw->mac.type != e1000_ich8lan) {
5225 e_dbg("Workaround applies to ICH8 only.\n");
5226 return;
5227 }
5228
5229 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5230 }
5231
5232 /**
5233 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5234 * @hw: pointer to the HW structure
5235 *
5236 * Workaround for 82566 power-down on D3 entry:
5237 * 1) disable gigabit link
5238 * 2) write VR power-down enable
5239 * 3) read it back
5240 * Continue if successful, else issue LCD reset and repeat
5241 **/
5242 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5243 {
5244 u32 reg;
5245 u16 data;
5246 u8 retry = 0;
5247
5248 if (hw->phy.type != e1000_phy_igp_3)
5249 return;
5250
5251 /* Try the workaround twice (if needed) */
5252 do {
5253 /* Disable link */
5254 reg = er32(PHY_CTRL);
5255 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5256 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5257 ew32(PHY_CTRL, reg);
5258
5259 /* Call gig speed drop workaround on Gig disable before
5260 * accessing any PHY registers
5261 */
5262 if (hw->mac.type == e1000_ich8lan)
5263 e1000e_gig_downshift_workaround_ich8lan(hw);
5264
5265 /* Write VR power-down enable */
5266 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5267 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5268 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5269
5270 /* Read it back and test */
5271 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5272 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5273 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5274 break;
5275
5276 /* Issue PHY reset and repeat at most one more time */
5277 reg = er32(CTRL);
5278 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5279 retry++;
5280 } while (retry);
5281 }
5282
5283 /**
5284 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5285 * @hw: pointer to the HW structure
5286 *
5287 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5288 * LPLU, Gig disable, MDIC PHY reset):
5289 * 1) Set Kumeran Near-end loopback
5290 * 2) Clear Kumeran Near-end loopback
5291 * Should only be called for ICH8[m] devices with any 1G Phy.
5292 **/
5293 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5294 {
5295 s32 ret_val;
5296 u16 reg_data;
5297
5298 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5299 return;
5300
5301 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5302 &reg_data);
5303 if (ret_val)
5304 return;
5305 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5306 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5307 reg_data);
5308 if (ret_val)
5309 return;
5310 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5311 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5312 }
5313
5314 /**
5315 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5316 * @hw: pointer to the HW structure
5317 *
5318 * During S0 to Sx transition, it is possible the link remains at gig
5319 * instead of negotiating to a lower speed. Before going to Sx, set
5320 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5321 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5322 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5323 * needs to be written.
5324 * Parts that support (and are linked to a partner which support) EEE in
5325 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5326 * than 10Mbps w/o EEE.
5327 **/
5328 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5329 {
5330 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5331 u32 phy_ctrl;
5332 s32 ret_val;
5333
5334 phy_ctrl = er32(PHY_CTRL);
5335 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5336
5337 if (hw->phy.type == e1000_phy_i217) {
5338 u16 phy_reg, device_id = hw->adapter->pdev->device;
5339
5340 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5341 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5342 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5343 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5344 (hw->mac.type >= e1000_pch_spt)) {
5345 u32 fextnvm6 = er32(FEXTNVM6);
5346
5347 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5348 }
5349
5350 ret_val = hw->phy.ops.acquire(hw);
5351 if (ret_val)
5352 goto out;
5353
5354 if (!dev_spec->eee_disable) {
5355 u16 eee_advert;
5356
5357 ret_val =
5358 e1000_read_emi_reg_locked(hw,
5359 I217_EEE_ADVERTISEMENT,
5360 &eee_advert);
5361 if (ret_val)
5362 goto release;
5363
5364 /* Disable LPLU if both link partners support 100BaseT
5365 * EEE and 100Full is advertised on both ends of the
5366 * link, and enable Auto Enable LPI since there will
5367 * be no driver to enable LPI while in Sx.
5368 */
5369 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5370 (dev_spec->eee_lp_ability &
5371 I82579_EEE_100_SUPPORTED) &&
5372 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5373 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5374 E1000_PHY_CTRL_NOND0A_LPLU);
5375
5376 /* Set Auto Enable LPI after link up */
5377 e1e_rphy_locked(hw,
5378 I217_LPI_GPIO_CTRL, &phy_reg);
5379 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5380 e1e_wphy_locked(hw,
5381 I217_LPI_GPIO_CTRL, phy_reg);
5382 }
5383 }
5384
5385 /* For i217 Intel Rapid Start Technology support,
5386 * when the system is going into Sx and no manageability engine
5387 * is present, the driver must configure proxy to reset only on
5388 * power good. LPI (Low Power Idle) state must also reset only
5389 * on power good, as well as the MTA (Multicast table array).
5390 * The SMBus release must also be disabled on LCD reset.
5391 */
5392 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5393 /* Enable proxy to reset only on power good. */
5394 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5395 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5396 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5397
5398 /* Set bit enable LPI (EEE) to reset only on
5399 * power good.
5400 */
5401 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5402 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5403 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5404
5405 /* Disable the SMB release on LCD reset. */
5406 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5407 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5408 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5409 }
5410
5411 /* Enable MTA to reset for Intel Rapid Start Technology
5412 * Support
5413 */
5414 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5415 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5416 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5417
5418 release:
5419 hw->phy.ops.release(hw);
5420 }
5421 out:
5422 ew32(PHY_CTRL, phy_ctrl);
5423
5424 if (hw->mac.type == e1000_ich8lan)
5425 e1000e_gig_downshift_workaround_ich8lan(hw);
5426
5427 if (hw->mac.type >= e1000_pchlan) {
5428 e1000_oem_bits_config_ich8lan(hw, false);
5429
5430 /* Reset PHY to activate OEM bits on 82577/8 */
5431 if (hw->mac.type == e1000_pchlan)
5432 e1000e_phy_hw_reset_generic(hw);
5433
5434 ret_val = hw->phy.ops.acquire(hw);
5435 if (ret_val)
5436 return;
5437 e1000_write_smbus_addr(hw);
5438 hw->phy.ops.release(hw);
5439 }
5440 }
5441
5442 /**
5443 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5444 * @hw: pointer to the HW structure
5445 *
5446 * During Sx to S0 transitions on non-managed devices or managed devices
5447 * on which PHY resets are not blocked, if the PHY registers cannot be
5448 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5449 * the PHY.
5450 * On i217, setup Intel Rapid Start Technology.
5451 **/
5452 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5453 {
5454 s32 ret_val;
5455
5456 if (hw->mac.type < e1000_pch2lan)
5457 return;
5458
5459 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5460 if (ret_val) {
5461 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5462 return;
5463 }
5464
5465 /* For i217 Intel Rapid Start Technology support when the system
5466 * is transitioning from Sx and no manageability engine is present
5467 * configure SMBus to restore on reset, disable proxy, and enable
5468 * the reset on MTA (Multicast table array).
5469 */
5470 if (hw->phy.type == e1000_phy_i217) {
5471 u16 phy_reg;
5472
5473 ret_val = hw->phy.ops.acquire(hw);
5474 if (ret_val) {
5475 e_dbg("Failed to setup iRST\n");
5476 return;
5477 }
5478
5479 /* Clear Auto Enable LPI after link up */
5480 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5481 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5482 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5483
5484 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5485 /* Restore clear on SMB if no manageability engine
5486 * is present
5487 */
5488 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5489 if (ret_val)
5490 goto release;
5491 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5492 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5493
5494 /* Disable Proxy */
5495 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5496 }
5497 /* Enable reset on MTA */
5498 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5499 if (ret_val)
5500 goto release;
5501 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5502 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5503 release:
5504 if (ret_val)
5505 e_dbg("Error %d in resume workarounds\n", ret_val);
5506 hw->phy.ops.release(hw);
5507 }
5508 }
5509
5510 /**
5511 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5512 * @hw: pointer to the HW structure
5513 *
5514 * Return the LED back to the default configuration.
5515 **/
5516 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5517 {
5518 if (hw->phy.type == e1000_phy_ife)
5519 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5520
5521 ew32(LEDCTL, hw->mac.ledctl_default);
5522 return 0;
5523 }
5524
5525 /**
5526 * e1000_led_on_ich8lan - Turn LEDs on
5527 * @hw: pointer to the HW structure
5528 *
5529 * Turn on the LEDs.
5530 **/
5531 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5532 {
5533 if (hw->phy.type == e1000_phy_ife)
5534 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5535 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5536
5537 ew32(LEDCTL, hw->mac.ledctl_mode2);
5538 return 0;
5539 }
5540
5541 /**
5542 * e1000_led_off_ich8lan - Turn LEDs off
5543 * @hw: pointer to the HW structure
5544 *
5545 * Turn off the LEDs.
5546 **/
5547 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5548 {
5549 if (hw->phy.type == e1000_phy_ife)
5550 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5551 (IFE_PSCL_PROBE_MODE |
5552 IFE_PSCL_PROBE_LEDS_OFF));
5553
5554 ew32(LEDCTL, hw->mac.ledctl_mode1);
5555 return 0;
5556 }
5557
5558 /**
5559 * e1000_setup_led_pchlan - Configures SW controllable LED
5560 * @hw: pointer to the HW structure
5561 *
5562 * This prepares the SW controllable LED for use.
5563 **/
5564 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5565 {
5566 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5567 }
5568
5569 /**
5570 * e1000_cleanup_led_pchlan - Restore the default LED operation
5571 * @hw: pointer to the HW structure
5572 *
5573 * Return the LED back to the default configuration.
5574 **/
5575 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5576 {
5577 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5578 }
5579
5580 /**
5581 * e1000_led_on_pchlan - Turn LEDs on
5582 * @hw: pointer to the HW structure
5583 *
5584 * Turn on the LEDs.
5585 **/
5586 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5587 {
5588 u16 data = (u16)hw->mac.ledctl_mode2;
5589 u32 i, led;
5590
5591 /* If no link, then turn LED on by setting the invert bit
5592 * for each LED that's mode is "link_up" in ledctl_mode2.
5593 */
5594 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5595 for (i = 0; i < 3; i++) {
5596 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5597 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5598 E1000_LEDCTL_MODE_LINK_UP)
5599 continue;
5600 if (led & E1000_PHY_LED0_IVRT)
5601 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5602 else
5603 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5604 }
5605 }
5606
5607 return e1e_wphy(hw, HV_LED_CONFIG, data);
5608 }
5609
5610 /**
5611 * e1000_led_off_pchlan - Turn LEDs off
5612 * @hw: pointer to the HW structure
5613 *
5614 * Turn off the LEDs.
5615 **/
5616 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5617 {
5618 u16 data = (u16)hw->mac.ledctl_mode1;
5619 u32 i, led;
5620
5621 /* If no link, then turn LED off by clearing the invert bit
5622 * for each LED that's mode is "link_up" in ledctl_mode1.
5623 */
5624 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5625 for (i = 0; i < 3; i++) {
5626 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5627 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5628 E1000_LEDCTL_MODE_LINK_UP)
5629 continue;
5630 if (led & E1000_PHY_LED0_IVRT)
5631 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5632 else
5633 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5634 }
5635 }
5636
5637 return e1e_wphy(hw, HV_LED_CONFIG, data);
5638 }
5639
5640 /**
5641 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5642 * @hw: pointer to the HW structure
5643 *
5644 * Read appropriate register for the config done bit for completion status
5645 * and configure the PHY through s/w for EEPROM-less parts.
5646 *
5647 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5648 * config done bit, so only an error is logged and continues. If we were
5649 * to return with error, EEPROM-less silicon would not be able to be reset
5650 * or change link.
5651 **/
5652 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5653 {
5654 s32 ret_val = 0;
5655 u32 bank = 0;
5656 u32 status;
5657
5658 e1000e_get_cfg_done_generic(hw);
5659
5660 /* Wait for indication from h/w that it has completed basic config */
5661 if (hw->mac.type >= e1000_ich10lan) {
5662 e1000_lan_init_done_ich8lan(hw);
5663 } else {
5664 ret_val = e1000e_get_auto_rd_done(hw);
5665 if (ret_val) {
5666 /* When auto config read does not complete, do not
5667 * return with an error. This can happen in situations
5668 * where there is no eeprom and prevents getting link.
5669 */
5670 e_dbg("Auto Read Done did not complete\n");
5671 ret_val = 0;
5672 }
5673 }
5674
5675 /* Clear PHY Reset Asserted bit */
5676 status = er32(STATUS);
5677 if (status & E1000_STATUS_PHYRA)
5678 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5679 else
5680 e_dbg("PHY Reset Asserted not set - needs delay\n");
5681
5682 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5683 if (hw->mac.type <= e1000_ich9lan) {
5684 if (!(er32(EECD) & E1000_EECD_PRES) &&
5685 (hw->phy.type == e1000_phy_igp_3)) {
5686 e1000e_phy_init_script_igp3(hw);
5687 }
5688 } else {
5689 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5690 /* Maybe we should do a basic PHY config */
5691 e_dbg("EEPROM not present\n");
5692 ret_val = -E1000_ERR_CONFIG;
5693 }
5694 }
5695
5696 return ret_val;
5697 }
5698
5699 /**
5700 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5701 * @hw: pointer to the HW structure
5702 *
5703 * In the case of a PHY power down to save power, or to turn off link during a
5704 * driver unload, or wake on lan is not enabled, remove the link.
5705 **/
5706 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5707 {
5708 /* If the management interface is not enabled, then power down */
5709 if (!(hw->mac.ops.check_mng_mode(hw) ||
5710 hw->phy.ops.check_reset_block(hw)))
5711 e1000_power_down_phy_copper(hw);
5712 }
5713
5714 /**
5715 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5716 * @hw: pointer to the HW structure
5717 *
5718 * Clears hardware counters specific to the silicon family and calls
5719 * clear_hw_cntrs_generic to clear all general purpose counters.
5720 **/
5721 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5722 {
5723 u16 phy_data;
5724 s32 ret_val;
5725
5726 e1000e_clear_hw_cntrs_base(hw);
5727
5728 er32(ALGNERRC);
5729 er32(RXERRC);
5730 er32(TNCRS);
5731 er32(CEXTERR);
5732 er32(TSCTC);
5733 er32(TSCTFC);
5734
5735 er32(MGTPRC);
5736 er32(MGTPDC);
5737 er32(MGTPTC);
5738
5739 er32(IAC);
5740 er32(ICRXOC);
5741
5742 /* Clear PHY statistics registers */
5743 if ((hw->phy.type == e1000_phy_82578) ||
5744 (hw->phy.type == e1000_phy_82579) ||
5745 (hw->phy.type == e1000_phy_i217) ||
5746 (hw->phy.type == e1000_phy_82577)) {
5747 ret_val = hw->phy.ops.acquire(hw);
5748 if (ret_val)
5749 return;
5750 ret_val = hw->phy.ops.set_page(hw,
5751 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5752 if (ret_val)
5753 goto release;
5754 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5755 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5756 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5757 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5758 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5759 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5760 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5761 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5762 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5763 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5764 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5765 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5766 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5767 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5768 release:
5769 hw->phy.ops.release(hw);
5770 }
5771 }
5772
5773 static const struct e1000_mac_operations ich8_mac_ops = {
5774 /* check_mng_mode dependent on mac type */
5775 .check_for_link = e1000_check_for_copper_link_ich8lan,
5776 /* cleanup_led dependent on mac type */
5777 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5778 .get_bus_info = e1000_get_bus_info_ich8lan,
5779 .set_lan_id = e1000_set_lan_id_single_port,
5780 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5781 /* led_on dependent on mac type */
5782 /* led_off dependent on mac type */
5783 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5784 .reset_hw = e1000_reset_hw_ich8lan,
5785 .init_hw = e1000_init_hw_ich8lan,
5786 .setup_link = e1000_setup_link_ich8lan,
5787 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5788 /* id_led_init dependent on mac type */
5789 .config_collision_dist = e1000e_config_collision_dist_generic,
5790 .rar_set = e1000e_rar_set_generic,
5791 .rar_get_count = e1000e_rar_get_count_generic,
5792 };
5793
5794 static const struct e1000_phy_operations ich8_phy_ops = {
5795 .acquire = e1000_acquire_swflag_ich8lan,
5796 .check_reset_block = e1000_check_reset_block_ich8lan,
5797 .commit = NULL,
5798 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5799 .get_cable_length = e1000e_get_cable_length_igp_2,
5800 .read_reg = e1000e_read_phy_reg_igp,
5801 .release = e1000_release_swflag_ich8lan,
5802 .reset = e1000_phy_hw_reset_ich8lan,
5803 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5804 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5805 .write_reg = e1000e_write_phy_reg_igp,
5806 };
5807
5808 static const struct e1000_nvm_operations ich8_nvm_ops = {
5809 .acquire = e1000_acquire_nvm_ich8lan,
5810 .read = e1000_read_nvm_ich8lan,
5811 .release = e1000_release_nvm_ich8lan,
5812 .reload = e1000e_reload_nvm_generic,
5813 .update = e1000_update_nvm_checksum_ich8lan,
5814 .valid_led_default = e1000_valid_led_default_ich8lan,
5815 .validate = e1000_validate_nvm_checksum_ich8lan,
5816 .write = e1000_write_nvm_ich8lan,
5817 };
5818
5819 static const struct e1000_nvm_operations spt_nvm_ops = {
5820 .acquire = e1000_acquire_nvm_ich8lan,
5821 .release = e1000_release_nvm_ich8lan,
5822 .read = e1000_read_nvm_spt,
5823 .update = e1000_update_nvm_checksum_spt,
5824 .reload = e1000e_reload_nvm_generic,
5825 .valid_led_default = e1000_valid_led_default_ich8lan,
5826 .validate = e1000_validate_nvm_checksum_ich8lan,
5827 .write = e1000_write_nvm_ich8lan,
5828 };
5829
5830 const struct e1000_info e1000_ich8_info = {
5831 .mac = e1000_ich8lan,
5832 .flags = FLAG_HAS_WOL
5833 | FLAG_IS_ICH
5834 | FLAG_HAS_CTRLEXT_ON_LOAD
5835 | FLAG_HAS_AMT
5836 | FLAG_HAS_FLASH
5837 | FLAG_APME_IN_WUC,
5838 .pba = 8,
5839 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5840 .get_variants = e1000_get_variants_ich8lan,
5841 .mac_ops = &ich8_mac_ops,
5842 .phy_ops = &ich8_phy_ops,
5843 .nvm_ops = &ich8_nvm_ops,
5844 };
5845
5846 const struct e1000_info e1000_ich9_info = {
5847 .mac = e1000_ich9lan,
5848 .flags = FLAG_HAS_JUMBO_FRAMES
5849 | FLAG_IS_ICH
5850 | FLAG_HAS_WOL
5851 | FLAG_HAS_CTRLEXT_ON_LOAD
5852 | FLAG_HAS_AMT
5853 | FLAG_HAS_FLASH
5854 | FLAG_APME_IN_WUC,
5855 .pba = 18,
5856 .max_hw_frame_size = DEFAULT_JUMBO,
5857 .get_variants = e1000_get_variants_ich8lan,
5858 .mac_ops = &ich8_mac_ops,
5859 .phy_ops = &ich8_phy_ops,
5860 .nvm_ops = &ich8_nvm_ops,
5861 };
5862
5863 const struct e1000_info e1000_ich10_info = {
5864 .mac = e1000_ich10lan,
5865 .flags = FLAG_HAS_JUMBO_FRAMES
5866 | FLAG_IS_ICH
5867 | FLAG_HAS_WOL
5868 | FLAG_HAS_CTRLEXT_ON_LOAD
5869 | FLAG_HAS_AMT
5870 | FLAG_HAS_FLASH
5871 | FLAG_APME_IN_WUC,
5872 .pba = 18,
5873 .max_hw_frame_size = DEFAULT_JUMBO,
5874 .get_variants = e1000_get_variants_ich8lan,
5875 .mac_ops = &ich8_mac_ops,
5876 .phy_ops = &ich8_phy_ops,
5877 .nvm_ops = &ich8_nvm_ops,
5878 };
5879
5880 const struct e1000_info e1000_pch_info = {
5881 .mac = e1000_pchlan,
5882 .flags = FLAG_IS_ICH
5883 | FLAG_HAS_WOL
5884 | FLAG_HAS_CTRLEXT_ON_LOAD
5885 | FLAG_HAS_AMT
5886 | FLAG_HAS_FLASH
5887 | FLAG_HAS_JUMBO_FRAMES
5888 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5889 | FLAG_APME_IN_WUC,
5890 .flags2 = FLAG2_HAS_PHY_STATS,
5891 .pba = 26,
5892 .max_hw_frame_size = 4096,
5893 .get_variants = e1000_get_variants_ich8lan,
5894 .mac_ops = &ich8_mac_ops,
5895 .phy_ops = &ich8_phy_ops,
5896 .nvm_ops = &ich8_nvm_ops,
5897 };
5898
5899 const struct e1000_info e1000_pch2_info = {
5900 .mac = e1000_pch2lan,
5901 .flags = FLAG_IS_ICH
5902 | FLAG_HAS_WOL
5903 | FLAG_HAS_HW_TIMESTAMP
5904 | FLAG_HAS_CTRLEXT_ON_LOAD
5905 | FLAG_HAS_AMT
5906 | FLAG_HAS_FLASH
5907 | FLAG_HAS_JUMBO_FRAMES
5908 | FLAG_APME_IN_WUC,
5909 .flags2 = FLAG2_HAS_PHY_STATS
5910 | FLAG2_HAS_EEE
5911 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5912 .pba = 26,
5913 .max_hw_frame_size = 9022,
5914 .get_variants = e1000_get_variants_ich8lan,
5915 .mac_ops = &ich8_mac_ops,
5916 .phy_ops = &ich8_phy_ops,
5917 .nvm_ops = &ich8_nvm_ops,
5918 };
5919
5920 const struct e1000_info e1000_pch_lpt_info = {
5921 .mac = e1000_pch_lpt,
5922 .flags = FLAG_IS_ICH
5923 | FLAG_HAS_WOL
5924 | FLAG_HAS_HW_TIMESTAMP
5925 | FLAG_HAS_CTRLEXT_ON_LOAD
5926 | FLAG_HAS_AMT
5927 | FLAG_HAS_FLASH
5928 | FLAG_HAS_JUMBO_FRAMES
5929 | FLAG_APME_IN_WUC,
5930 .flags2 = FLAG2_HAS_PHY_STATS
5931 | FLAG2_HAS_EEE
5932 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5933 .pba = 26,
5934 .max_hw_frame_size = 9022,
5935 .get_variants = e1000_get_variants_ich8lan,
5936 .mac_ops = &ich8_mac_ops,
5937 .phy_ops = &ich8_phy_ops,
5938 .nvm_ops = &ich8_nvm_ops,
5939 };
5940
5941 const struct e1000_info e1000_pch_spt_info = {
5942 .mac = e1000_pch_spt,
5943 .flags = FLAG_IS_ICH
5944 | FLAG_HAS_WOL
5945 | FLAG_HAS_HW_TIMESTAMP
5946 | FLAG_HAS_CTRLEXT_ON_LOAD
5947 | FLAG_HAS_AMT
5948 | FLAG_HAS_FLASH
5949 | FLAG_HAS_JUMBO_FRAMES
5950 | FLAG_APME_IN_WUC,
5951 .flags2 = FLAG2_HAS_PHY_STATS
5952 | FLAG2_HAS_EEE,
5953 .pba = 26,
5954 .max_hw_frame_size = 9022,
5955 .get_variants = e1000_get_variants_ich8lan,
5956 .mac_ops = &ich8_mac_ops,
5957 .phy_ops = &ich8_phy_ops,
5958 .nvm_ops = &spt_nvm_ops,
5959 };
5960
5961 const struct e1000_info e1000_pch_cnp_info = {
5962 .mac = e1000_pch_cnp,
5963 .flags = FLAG_IS_ICH
5964 | FLAG_HAS_WOL
5965 | FLAG_HAS_HW_TIMESTAMP
5966 | FLAG_HAS_CTRLEXT_ON_LOAD
5967 | FLAG_HAS_AMT
5968 | FLAG_HAS_FLASH
5969 | FLAG_HAS_JUMBO_FRAMES
5970 | FLAG_APME_IN_WUC,
5971 .flags2 = FLAG2_HAS_PHY_STATS
5972 | FLAG2_HAS_EEE,
5973 .pba = 26,
5974 .max_hw_frame_size = 9022,
5975 .get_variants = e1000_get_variants_ich8lan,
5976 .mac_ops = &ich8_mac_ops,
5977 .phy_ops = &ich8_phy_ops,
5978 .nvm_ops = &spt_nvm_ops,
5979 };
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