1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
18 * 82567V Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44 /* Offset 04h HSFSTS */
45 union ich8_hws_flash_status
{
47 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
49 u16 dael
:1; /* bit 2 Direct Access error Log */
50 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1
:2; /* bit 13:6 Reserved */
53 u16 reserved2
:6; /* bit 13:6 Reserved */
54 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61 /* Offset 06h FLCTL */
62 union ich8_hws_flash_ctrl
{
64 u16 flcgo
:1; /* 0 Flash Cycle Go */
65 u16 flcycle
:2; /* 2:1 Flash Cycle */
66 u16 reserved
:5; /* 7:3 Reserved */
67 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn
:6; /* 15:10 Reserved */
73 /* ICH Flash Region Access Permissions */
74 union ich8_hws_flash_regacc
{
76 u32 grra
:8; /* 0:7 GbE region Read Access */
77 u32 grwa
:8; /* 8:15 GbE region Write Access */
78 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
84 /* ICH Flash Protected Region */
85 union ich8_flash_protected_range
{
87 u32 base
:13; /* 0:12 Protected Range Base */
88 u32 reserved1
:2; /* 13:14 Reserved */
89 u32 rpe
:1; /* 15 Read Protection Enable */
90 u32 limit
:13; /* 16:28 Protected Range Limit */
91 u32 reserved2
:2; /* 29:30 Reserved */
92 u32 wpe
:1; /* 31 Write Protection Enable */
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
99 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
100 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
101 u32 offset
, u8 byte
);
102 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
104 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
106 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
108 static s32
e1000_read_flash_data32_ich8lan(struct e1000_hw
*hw
, u32 offset
,
110 static s32
e1000_read_flash_dword_ich8lan(struct e1000_hw
*hw
,
111 u32 offset
, u32
*data
);
112 static s32
e1000_write_flash_data32_ich8lan(struct e1000_hw
*hw
,
113 u32 offset
, u32 data
);
114 static s32
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw
*hw
,
115 u32 offset
, u32 dword
);
116 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
117 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
118 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
119 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
120 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
121 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
122 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
123 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
124 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
125 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
);
128 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
);
129 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
);
132 static int e1000_rar_set_pch2lan(struct e1000_hw
*hw
, u8
*addr
, u32 index
);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw
*hw
, u8
*addr
, u32 index
);
134 static u32
e1000_rar_get_count_pch_lpt(struct e1000_hw
*hw
);
135 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
);
137 static s32
e1000_disable_ulp_lpt_lp(struct e1000_hw
*hw
, bool force
);
138 static s32
e1000_setup_copper_link_pch_lpt(struct e1000_hw
*hw
);
139 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
);
141 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
143 return readw(hw
->flash_address
+ reg
);
146 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
148 return readl(hw
->flash_address
+ reg
);
151 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
153 writew(val
, hw
->flash_address
+ reg
);
156 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
158 writel(val
, hw
->flash_address
+ reg
);
161 #define er16flash(reg) __er16flash(hw, (reg))
162 #define er32flash(reg) __er32flash(hw, (reg))
163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
174 * Assumes the sw/fw/hw semaphore is already acquired.
176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw
*hw
)
184 for (retry_count
= 0; retry_count
< 2; retry_count
++) {
185 ret_val
= e1e_rphy_locked(hw
, MII_PHYSID1
, &phy_reg
);
186 if (ret_val
|| (phy_reg
== 0xFFFF))
188 phy_id
= (u32
)(phy_reg
<< 16);
190 ret_val
= e1e_rphy_locked(hw
, MII_PHYSID2
, &phy_reg
);
191 if (ret_val
|| (phy_reg
== 0xFFFF)) {
195 phy_id
|= (u32
)(phy_reg
& PHY_REVISION_MASK
);
200 if (hw
->phy
.id
== phy_id
)
204 hw
->phy
.revision
= (u32
)(phy_reg
& ~PHY_REVISION_MASK
);
208 /* In case the PHY needs to be in mdio slow mode,
209 * set slow mode and try to get the PHY id again.
211 if (hw
->mac
.type
< e1000_pch_lpt
) {
212 hw
->phy
.ops
.release(hw
);
213 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
215 ret_val
= e1000e_get_phy_id(hw
);
216 hw
->phy
.ops
.acquire(hw
);
222 if (hw
->mac
.type
>= e1000_pch_lpt
) {
223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
225 /* Unforce SMBus mode in PHY */
226 e1e_rphy_locked(hw
, CV_SMB_CTRL
, &phy_reg
);
227 phy_reg
&= ~CV_SMB_CTRL_FORCE_SMBUS
;
228 e1e_wphy_locked(hw
, CV_SMB_CTRL
, phy_reg
);
230 /* Unforce SMBus mode in MAC */
231 mac_reg
= er32(CTRL_EXT
);
232 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
233 ew32(CTRL_EXT
, mac_reg
);
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242 * @hw: pointer to the HW structure
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245 * used to reset the PHY to a quiescent state when necessary.
247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw
*hw
)
251 /* Set Phy Config Counter to 50msec */
252 mac_reg
= er32(FEXTNVM3
);
253 mac_reg
&= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK
;
254 mac_reg
|= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
;
255 ew32(FEXTNVM3
, mac_reg
);
257 /* Toggle LANPHYPC Value bit */
258 mac_reg
= er32(CTRL
);
259 mac_reg
|= E1000_CTRL_LANPHYPC_OVERRIDE
;
260 mac_reg
&= ~E1000_CTRL_LANPHYPC_VALUE
;
263 usleep_range(10, 20);
264 mac_reg
&= ~E1000_CTRL_LANPHYPC_OVERRIDE
;
268 if (hw
->mac
.type
< e1000_pch_lpt
) {
274 usleep_range(5000, 6000);
275 } while (!(er32(CTRL_EXT
) & E1000_CTRL_EXT_LPCD
) && count
--);
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
285 * Workarounds/flow necessary for PHY initialization during driver load
288 static s32
e1000_init_phy_workarounds_pchlan(struct e1000_hw
*hw
)
290 struct e1000_adapter
*adapter
= hw
->adapter
;
291 u32 mac_reg
, fwsm
= er32(FWSM
);
294 /* Gate automatic PHY configuration by hardware on managed and
295 * non-managed 82579 and newer adapters.
297 e1000_gate_hw_phy_config_ich8lan(hw
, true);
299 /* It is not possible to be certain of the current state of ULP
300 * so forcibly disable it.
302 hw
->dev_spec
.ich8lan
.ulp_state
= e1000_ulp_state_unknown
;
303 ret_val
= e1000_disable_ulp_lpt_lp(hw
, true);
305 e_warn("Failed to disable ULP\n");
307 ret_val
= hw
->phy
.ops
.acquire(hw
);
309 e_dbg("Failed to initialize PHY flow\n");
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
317 switch (hw
->mac
.type
) {
324 if (e1000_phy_is_accessible_pchlan(hw
))
327 /* Before toggling LANPHYPC, see if PHY is accessible by
328 * forcing MAC to SMBus mode first.
330 mac_reg
= er32(CTRL_EXT
);
331 mac_reg
|= E1000_CTRL_EXT_FORCE_SMBUS
;
332 ew32(CTRL_EXT
, mac_reg
);
334 /* Wait 50 milliseconds for MAC to finish any retries
335 * that it might be trying to perform from previous
336 * attempts to acknowledge any phy read requests.
342 if (e1000_phy_is_accessible_pchlan(hw
))
347 if ((hw
->mac
.type
== e1000_pchlan
) &&
348 (fwsm
& E1000_ICH_FWSM_FW_VALID
))
351 if (hw
->phy
.ops
.check_reset_block(hw
)) {
352 e_dbg("Required LANPHYPC toggle blocked by ME\n");
353 ret_val
= -E1000_ERR_PHY
;
357 /* Toggle LANPHYPC Value bit */
358 e1000_toggle_lanphypc_pch_lpt(hw
);
359 if (hw
->mac
.type
>= e1000_pch_lpt
) {
360 if (e1000_phy_is_accessible_pchlan(hw
))
363 /* Toggling LANPHYPC brings the PHY out of SMBus mode
364 * so ensure that the MAC is also out of SMBus mode
366 mac_reg
= er32(CTRL_EXT
);
367 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
368 ew32(CTRL_EXT
, mac_reg
);
370 if (e1000_phy_is_accessible_pchlan(hw
))
373 ret_val
= -E1000_ERR_PHY
;
380 hw
->phy
.ops
.release(hw
);
383 /* Check to see if able to reset PHY. Print error if not */
384 if (hw
->phy
.ops
.check_reset_block(hw
)) {
385 e_err("Reset blocked by ME\n");
389 /* Reset the PHY before any access to it. Doing so, ensures
390 * that the PHY is in a known good state before we read/write
391 * PHY registers. The generic reset is sufficient here,
392 * because we haven't determined the PHY type yet.
394 ret_val
= e1000e_phy_hw_reset_generic(hw
);
398 /* On a successful reset, possibly need to wait for the PHY
399 * to quiesce to an accessible state before returning control
400 * to the calling function. If the PHY does not quiesce, then
401 * return E1000E_BLK_PHY_RESET, as this is the condition that
404 ret_val
= hw
->phy
.ops
.check_reset_block(hw
);
406 e_err("ME blocked access to PHY after reset\n");
410 /* Ungate automatic PHY configuration on non-managed 82579 */
411 if ((hw
->mac
.type
== e1000_pch2lan
) &&
412 !(fwsm
& E1000_ICH_FWSM_FW_VALID
)) {
413 usleep_range(10000, 11000);
414 e1000_gate_hw_phy_config_ich8lan(hw
, false);
421 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
422 * @hw: pointer to the HW structure
424 * Initialize family-specific PHY parameters and function pointers.
426 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
428 struct e1000_phy_info
*phy
= &hw
->phy
;
432 phy
->reset_delay_us
= 100;
434 phy
->ops
.set_page
= e1000_set_page_igp
;
435 phy
->ops
.read_reg
= e1000_read_phy_reg_hv
;
436 phy
->ops
.read_reg_locked
= e1000_read_phy_reg_hv_locked
;
437 phy
->ops
.read_reg_page
= e1000_read_phy_reg_page_hv
;
438 phy
->ops
.set_d0_lplu_state
= e1000_set_lplu_state_pchlan
;
439 phy
->ops
.set_d3_lplu_state
= e1000_set_lplu_state_pchlan
;
440 phy
->ops
.write_reg
= e1000_write_phy_reg_hv
;
441 phy
->ops
.write_reg_locked
= e1000_write_phy_reg_hv_locked
;
442 phy
->ops
.write_reg_page
= e1000_write_phy_reg_page_hv
;
443 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
444 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
445 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
447 phy
->id
= e1000_phy_unknown
;
449 ret_val
= e1000_init_phy_workarounds_pchlan(hw
);
453 if (phy
->id
== e1000_phy_unknown
)
454 switch (hw
->mac
.type
) {
456 ret_val
= e1000e_get_phy_id(hw
);
459 if ((phy
->id
!= 0) && (phy
->id
!= PHY_REVISION_MASK
))
469 /* In case the PHY needs to be in mdio slow mode,
470 * set slow mode and try to get the PHY id again.
472 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
475 ret_val
= e1000e_get_phy_id(hw
);
480 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
483 case e1000_phy_82577
:
484 case e1000_phy_82579
:
486 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
487 phy
->ops
.force_speed_duplex
=
488 e1000_phy_force_speed_duplex_82577
;
489 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
490 phy
->ops
.get_info
= e1000_get_phy_info_82577
;
491 phy
->ops
.commit
= e1000e_phy_sw_reset
;
493 case e1000_phy_82578
:
494 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
495 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
496 phy
->ops
.get_cable_length
= e1000e_get_cable_length_m88
;
497 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
500 ret_val
= -E1000_ERR_PHY
;
508 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
509 * @hw: pointer to the HW structure
511 * Initialize family-specific PHY parameters and function pointers.
513 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
515 struct e1000_phy_info
*phy
= &hw
->phy
;
520 phy
->reset_delay_us
= 100;
522 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
523 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
525 /* We may need to do this twice - once for IGP and if that fails,
526 * we'll set BM func pointers and try again
528 ret_val
= e1000e_determine_phy_address(hw
);
530 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
531 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
532 ret_val
= e1000e_determine_phy_address(hw
);
534 e_dbg("Cannot determine PHY addr. Erroring out\n");
540 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
542 usleep_range(1000, 1100);
543 ret_val
= e1000e_get_phy_id(hw
);
550 case IGP03E1000_E_PHY_ID
:
551 phy
->type
= e1000_phy_igp_3
;
552 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
553 phy
->ops
.read_reg_locked
= e1000e_read_phy_reg_igp_locked
;
554 phy
->ops
.write_reg_locked
= e1000e_write_phy_reg_igp_locked
;
555 phy
->ops
.get_info
= e1000e_get_phy_info_igp
;
556 phy
->ops
.check_polarity
= e1000_check_polarity_igp
;
557 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
;
560 case IFE_PLUS_E_PHY_ID
:
562 phy
->type
= e1000_phy_ife
;
563 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
564 phy
->ops
.get_info
= e1000_get_phy_info_ife
;
565 phy
->ops
.check_polarity
= e1000_check_polarity_ife
;
566 phy
->ops
.force_speed_duplex
= e1000_phy_force_speed_duplex_ife
;
568 case BME1000_E_PHY_ID
:
569 phy
->type
= e1000_phy_bm
;
570 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
571 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
572 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
573 phy
->ops
.commit
= e1000e_phy_sw_reset
;
574 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
575 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
576 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
579 return -E1000_ERR_PHY
;
586 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
587 * @hw: pointer to the HW structure
589 * Initialize family-specific NVM parameters and function
592 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
594 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
595 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
596 u32 gfpreg
, sector_base_addr
, sector_end_addr
;
600 nvm
->type
= e1000_nvm_flash_sw
;
602 if (hw
->mac
.type
>= e1000_pch_spt
) {
603 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
604 * STRAP register. This is because in SPT the GbE Flash region
605 * is no longer accessed through the flash registers. Instead,
606 * the mechanism has changed, and the Flash region access
607 * registers are now implemented in GbE memory space.
609 nvm
->flash_base_addr
= 0;
610 nvm_size
= (((er32(STRAP
) >> 1) & 0x1F) + 1)
611 * NVM_SIZE_MULTIPLIER
;
612 nvm
->flash_bank_size
= nvm_size
/ 2;
613 /* Adjust to word count */
614 nvm
->flash_bank_size
/= sizeof(u16
);
615 /* Set the base address for flash register access */
616 hw
->flash_address
= hw
->hw_addr
+ E1000_FLASH_BASE_ADDR
;
618 /* Can't read flash registers if register set isn't mapped. */
619 if (!hw
->flash_address
) {
620 e_dbg("ERROR: Flash registers not mapped\n");
621 return -E1000_ERR_CONFIG
;
624 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
626 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
627 * Add 1 to sector_end_addr since this sector is included in
630 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
631 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
633 /* flash_base_addr is byte-aligned */
634 nvm
->flash_base_addr
= sector_base_addr
635 << FLASH_SECTOR_ADDR_SHIFT
;
637 /* find total size of the NVM, then cut in half since the total
638 * size represents two separate NVM banks.
640 nvm
->flash_bank_size
= ((sector_end_addr
- sector_base_addr
)
641 << FLASH_SECTOR_ADDR_SHIFT
);
642 nvm
->flash_bank_size
/= 2;
643 /* Adjust to word count */
644 nvm
->flash_bank_size
/= sizeof(u16
);
647 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
649 /* Clear shadow ram */
650 for (i
= 0; i
< nvm
->word_size
; i
++) {
651 dev_spec
->shadow_ram
[i
].modified
= false;
652 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
659 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
660 * @hw: pointer to the HW structure
662 * Initialize family-specific MAC parameters and function
665 static s32
e1000_init_mac_params_ich8lan(struct e1000_hw
*hw
)
667 struct e1000_mac_info
*mac
= &hw
->mac
;
669 /* Set media type function pointer */
670 hw
->phy
.media_type
= e1000_media_type_copper
;
672 /* Set mta register count */
673 mac
->mta_reg_count
= 32;
674 /* Set rar entry count */
675 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
676 if (mac
->type
== e1000_ich8lan
)
677 mac
->rar_entry_count
--;
679 mac
->has_fwsm
= true;
680 /* ARC subsystem not supported */
681 mac
->arc_subsystem_valid
= false;
682 /* Adaptive IFS supported */
683 mac
->adaptive_ifs
= true;
685 /* LED and other operations */
690 /* check management mode */
691 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_ich8lan
;
693 mac
->ops
.id_led_init
= e1000e_id_led_init_generic
;
695 mac
->ops
.blink_led
= e1000e_blink_led_generic
;
697 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
699 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
700 /* turn on/off LED */
701 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
702 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
705 mac
->rar_entry_count
= E1000_PCH2_RAR_ENTRIES
;
706 mac
->ops
.rar_set
= e1000_rar_set_pch2lan
;
715 /* check management mode */
716 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_pchlan
;
718 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
720 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
722 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
723 /* turn on/off LED */
724 mac
->ops
.led_on
= e1000_led_on_pchlan
;
725 mac
->ops
.led_off
= e1000_led_off_pchlan
;
731 if (mac
->type
>= e1000_pch_lpt
) {
732 mac
->rar_entry_count
= E1000_PCH_LPT_RAR_ENTRIES
;
733 mac
->ops
.rar_set
= e1000_rar_set_pch_lpt
;
734 mac
->ops
.setup_physical_interface
=
735 e1000_setup_copper_link_pch_lpt
;
736 mac
->ops
.rar_get_count
= e1000_rar_get_count_pch_lpt
;
739 /* Enable PCS Lock-loss workaround for ICH8 */
740 if (mac
->type
== e1000_ich8lan
)
741 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, true);
747 * __e1000_access_emi_reg_locked - Read/write EMI register
748 * @hw: pointer to the HW structure
749 * @address: EMI address to program
750 * @data: pointer to value to read/write from/to the EMI address
751 * @read: boolean flag to indicate read or write
753 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
755 static s32
__e1000_access_emi_reg_locked(struct e1000_hw
*hw
, u16 address
,
756 u16
*data
, bool read
)
760 ret_val
= e1e_wphy_locked(hw
, I82579_EMI_ADDR
, address
);
765 ret_val
= e1e_rphy_locked(hw
, I82579_EMI_DATA
, data
);
767 ret_val
= e1e_wphy_locked(hw
, I82579_EMI_DATA
, *data
);
773 * e1000_read_emi_reg_locked - Read Extended Management Interface register
774 * @hw: pointer to the HW structure
775 * @addr: EMI address to program
776 * @data: value to be read from the EMI address
778 * Assumes the SW/FW/HW Semaphore is already acquired.
780 s32
e1000_read_emi_reg_locked(struct e1000_hw
*hw
, u16 addr
, u16
*data
)
782 return __e1000_access_emi_reg_locked(hw
, addr
, data
, true);
786 * e1000_write_emi_reg_locked - Write Extended Management Interface register
787 * @hw: pointer to the HW structure
788 * @addr: EMI address to program
789 * @data: value to be written to the EMI address
791 * Assumes the SW/FW/HW Semaphore is already acquired.
793 s32
e1000_write_emi_reg_locked(struct e1000_hw
*hw
, u16 addr
, u16 data
)
795 return __e1000_access_emi_reg_locked(hw
, addr
, &data
, false);
799 * e1000_set_eee_pchlan - Enable/disable EEE support
800 * @hw: pointer to the HW structure
802 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
803 * the link and the EEE capabilities of the link partner. The LPI Control
804 * register bits will remain set only if/when link is up.
806 * EEE LPI must not be asserted earlier than one second after link is up.
807 * On 82579, EEE LPI should not be enabled until such time otherwise there
808 * can be link issues with some switches. Other devices can have EEE LPI
809 * enabled immediately upon link up since they have a timer in hardware which
810 * prevents LPI from being asserted too early.
812 s32
e1000_set_eee_pchlan(struct e1000_hw
*hw
)
814 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
816 u16 lpa
, pcs_status
, adv
, adv_addr
, lpi_ctrl
, data
;
818 switch (hw
->phy
.type
) {
819 case e1000_phy_82579
:
820 lpa
= I82579_EEE_LP_ABILITY
;
821 pcs_status
= I82579_EEE_PCS_STATUS
;
822 adv_addr
= I82579_EEE_ADVERTISEMENT
;
825 lpa
= I217_EEE_LP_ABILITY
;
826 pcs_status
= I217_EEE_PCS_STATUS
;
827 adv_addr
= I217_EEE_ADVERTISEMENT
;
833 ret_val
= hw
->phy
.ops
.acquire(hw
);
837 ret_val
= e1e_rphy_locked(hw
, I82579_LPI_CTRL
, &lpi_ctrl
);
841 /* Clear bits that enable EEE in various speeds */
842 lpi_ctrl
&= ~I82579_LPI_CTRL_ENABLE_MASK
;
844 /* Enable EEE if not disabled by user */
845 if (!dev_spec
->eee_disable
) {
846 /* Save off link partner's EEE ability */
847 ret_val
= e1000_read_emi_reg_locked(hw
, lpa
,
848 &dev_spec
->eee_lp_ability
);
852 /* Read EEE advertisement */
853 ret_val
= e1000_read_emi_reg_locked(hw
, adv_addr
, &adv
);
857 /* Enable EEE only for speeds in which the link partner is
858 * EEE capable and for which we advertise EEE.
860 if (adv
& dev_spec
->eee_lp_ability
& I82579_EEE_1000_SUPPORTED
)
861 lpi_ctrl
|= I82579_LPI_CTRL_1000_ENABLE
;
863 if (adv
& dev_spec
->eee_lp_ability
& I82579_EEE_100_SUPPORTED
) {
864 e1e_rphy_locked(hw
, MII_LPA
, &data
);
865 if (data
& LPA_100FULL
)
866 lpi_ctrl
|= I82579_LPI_CTRL_100_ENABLE
;
868 /* EEE is not supported in 100Half, so ignore
869 * partner's EEE in 100 ability if full-duplex
872 dev_spec
->eee_lp_ability
&=
873 ~I82579_EEE_100_SUPPORTED
;
877 if (hw
->phy
.type
== e1000_phy_82579
) {
878 ret_val
= e1000_read_emi_reg_locked(hw
, I82579_LPI_PLL_SHUT
,
883 data
&= ~I82579_LPI_100_PLL_SHUT
;
884 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_LPI_PLL_SHUT
,
888 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
889 ret_val
= e1000_read_emi_reg_locked(hw
, pcs_status
, &data
);
893 ret_val
= e1e_wphy_locked(hw
, I82579_LPI_CTRL
, lpi_ctrl
);
895 hw
->phy
.ops
.release(hw
);
901 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
902 * @hw: pointer to the HW structure
903 * @link: link up bool flag
905 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
906 * preventing further DMA write requests. Workaround the issue by disabling
907 * the de-assertion of the clock request when in 1Gpbs mode.
908 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
909 * speeds in order to avoid Tx hangs.
911 static s32
e1000_k1_workaround_lpt_lp(struct e1000_hw
*hw
, bool link
)
913 u32 fextnvm6
= er32(FEXTNVM6
);
914 u32 status
= er32(STATUS
);
918 if (link
&& (status
& E1000_STATUS_SPEED_1000
)) {
919 ret_val
= hw
->phy
.ops
.acquire(hw
);
924 e1000e_read_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
930 e1000e_write_kmrn_reg_locked(hw
,
931 E1000_KMRNCTRLSTA_K1_CONFIG
,
933 ~E1000_KMRNCTRLSTA_K1_ENABLE
);
937 usleep_range(10, 20);
939 ew32(FEXTNVM6
, fextnvm6
| E1000_FEXTNVM6_REQ_PLL_CLK
);
942 e1000e_write_kmrn_reg_locked(hw
,
943 E1000_KMRNCTRLSTA_K1_CONFIG
,
946 hw
->phy
.ops
.release(hw
);
948 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
949 fextnvm6
&= ~E1000_FEXTNVM6_REQ_PLL_CLK
;
951 if ((hw
->phy
.revision
> 5) || !link
||
952 ((status
& E1000_STATUS_SPEED_100
) &&
953 (status
& E1000_STATUS_FD
)))
954 goto update_fextnvm6
;
956 ret_val
= e1e_rphy(hw
, I217_INBAND_CTRL
, ®
);
960 /* Clear link status transmit timeout */
961 reg
&= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK
;
963 if (status
& E1000_STATUS_SPEED_100
) {
964 /* Set inband Tx timeout to 5x10us for 100Half */
965 reg
|= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT
;
967 /* Do not extend the K1 entry latency for 100Half */
968 fextnvm6
&= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION
;
970 /* Set inband Tx timeout to 50x10us for 10Full/Half */
972 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT
;
974 /* Extend the K1 entry latency for 10 Mbps */
975 fextnvm6
|= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION
;
978 ret_val
= e1e_wphy(hw
, I217_INBAND_CTRL
, reg
);
983 ew32(FEXTNVM6
, fextnvm6
);
990 * e1000_platform_pm_pch_lpt - Set platform power management values
991 * @hw: pointer to the HW structure
992 * @link: bool indicating link status
994 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
995 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
996 * when link is up (which must not exceed the maximum latency supported
997 * by the platform), otherwise specify there is no LTR requirement.
998 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
999 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1000 * Capability register set, on this device LTR is set by writing the
1001 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1002 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1003 * message to the PMC.
1005 static s32
e1000_platform_pm_pch_lpt(struct e1000_hw
*hw
, bool link
)
1007 u32 reg
= link
<< (E1000_LTRV_REQ_SHIFT
+ E1000_LTRV_NOSNOOP_SHIFT
) |
1008 link
<< E1000_LTRV_REQ_SHIFT
| E1000_LTRV_SEND
;
1009 u16 max_ltr_enc_d
= 0; /* maximum LTR decoded by platform */
1010 u16 lat_enc_d
= 0; /* latency decoded */
1011 u16 lat_enc
= 0; /* latency encoded */
1014 u16 speed
, duplex
, scale
= 0;
1015 u16 max_snoop
, max_nosnoop
;
1016 u16 max_ltr_enc
; /* max LTR latency encoded */
1020 if (!hw
->adapter
->max_frame_size
) {
1021 e_dbg("max_frame_size not set.\n");
1022 return -E1000_ERR_CONFIG
;
1025 hw
->mac
.ops
.get_link_up_info(hw
, &speed
, &duplex
);
1027 e_dbg("Speed not set.\n");
1028 return -E1000_ERR_CONFIG
;
1031 /* Rx Packet Buffer Allocation size (KB) */
1032 rxa
= er32(PBA
) & E1000_PBA_RXA_MASK
;
1034 /* Determine the maximum latency tolerated by the device.
1036 * Per the PCIe spec, the tolerated latencies are encoded as
1037 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1038 * a 10-bit value (0-1023) to provide a range from 1 ns to
1039 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1040 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1043 value
= (rxa
> hw
->adapter
->max_frame_size
) ?
1044 (rxa
- hw
->adapter
->max_frame_size
) * (16000 / speed
) :
1047 while (value
> PCI_LTR_VALUE_MASK
) {
1049 value
= DIV_ROUND_UP(value
, BIT(5));
1051 if (scale
> E1000_LTRV_SCALE_MAX
) {
1052 e_dbg("Invalid LTR latency scale %d\n", scale
);
1053 return -E1000_ERR_CONFIG
;
1055 lat_enc
= (u16
)((scale
<< PCI_LTR_SCALE_SHIFT
) | value
);
1057 /* Determine the maximum latency tolerated by the platform */
1058 pci_read_config_word(hw
->adapter
->pdev
, E1000_PCI_LTR_CAP_LPT
,
1060 pci_read_config_word(hw
->adapter
->pdev
,
1061 E1000_PCI_LTR_CAP_LPT
+ 2, &max_nosnoop
);
1062 max_ltr_enc
= max_t(u16
, max_snoop
, max_nosnoop
);
1064 lat_enc_d
= (lat_enc
& E1000_LTRV_VALUE_MASK
) *
1065 (1U << (E1000_LTRV_SCALE_FACTOR
*
1066 ((lat_enc
& E1000_LTRV_SCALE_MASK
)
1067 >> E1000_LTRV_SCALE_SHIFT
)));
1069 max_ltr_enc_d
= (max_ltr_enc
& E1000_LTRV_VALUE_MASK
) *
1070 (1U << (E1000_LTRV_SCALE_FACTOR
*
1071 ((max_ltr_enc
& E1000_LTRV_SCALE_MASK
)
1072 >> E1000_LTRV_SCALE_SHIFT
)));
1074 if (lat_enc_d
> max_ltr_enc_d
)
1075 lat_enc
= max_ltr_enc
;
1078 /* Set Snoop and No-Snoop latencies the same */
1079 reg
|= lat_enc
| (lat_enc
<< E1000_LTRV_NOSNOOP_SHIFT
);
1086 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1087 * @hw: pointer to the HW structure
1088 * @to_sx: boolean indicating a system power state transition to Sx
1090 * When link is down, configure ULP mode to significantly reduce the power
1091 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1092 * ME firmware to start the ULP configuration. If not on an ME enabled
1093 * system, configure the ULP mode by software.
1095 s32
e1000_enable_ulp_lpt_lp(struct e1000_hw
*hw
, bool to_sx
)
1102 if ((hw
->mac
.type
< e1000_pch_lpt
) ||
1103 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPT_I217_LM
) ||
1104 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPT_I217_V
) ||
1105 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_LM2
) ||
1106 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_V2
) ||
1107 (hw
->dev_spec
.ich8lan
.ulp_state
== e1000_ulp_state_on
))
1110 if (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
) {
1111 /* Request ME configure ULP mode in the PHY */
1112 mac_reg
= er32(H2ME
);
1113 mac_reg
|= E1000_H2ME_ULP
| E1000_H2ME_ENFORCE_SETTINGS
;
1114 ew32(H2ME
, mac_reg
);
1122 /* Poll up to 5 seconds for Cable Disconnected indication */
1123 while (!(er32(FEXT
) & E1000_FEXT_PHY_CABLE_DISCONNECTED
)) {
1124 /* Bail if link is re-acquired */
1125 if (er32(STATUS
) & E1000_STATUS_LU
)
1126 return -E1000_ERR_PHY
;
1133 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1135 E1000_FEXT_PHY_CABLE_DISCONNECTED
) ? "" : "not", i
* 50);
1138 ret_val
= hw
->phy
.ops
.acquire(hw
);
1142 /* Force SMBus mode in PHY */
1143 ret_val
= e1000_read_phy_reg_hv_locked(hw
, CV_SMB_CTRL
, &phy_reg
);
1146 phy_reg
|= CV_SMB_CTRL_FORCE_SMBUS
;
1147 e1000_write_phy_reg_hv_locked(hw
, CV_SMB_CTRL
, phy_reg
);
1149 /* Force SMBus mode in MAC */
1150 mac_reg
= er32(CTRL_EXT
);
1151 mac_reg
|= E1000_CTRL_EXT_FORCE_SMBUS
;
1152 ew32(CTRL_EXT
, mac_reg
);
1154 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1155 * LPLU and disable Gig speed when entering ULP
1157 if ((hw
->phy
.type
== e1000_phy_i217
) && (hw
->phy
.revision
== 6)) {
1158 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_OEM_BITS
,
1164 phy_reg
|= HV_OEM_BITS_LPLU
| HV_OEM_BITS_GBE_DIS
;
1166 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_OEM_BITS
,
1173 /* Set Inband ULP Exit, Reset to SMBus mode and
1174 * Disable SMBus Release on PERST# in PHY
1176 ret_val
= e1000_read_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, &phy_reg
);
1179 phy_reg
|= (I218_ULP_CONFIG1_RESET_TO_SMBUS
|
1180 I218_ULP_CONFIG1_DISABLE_SMB_PERST
);
1182 if (er32(WUFC
) & E1000_WUFC_LNKC
)
1183 phy_reg
|= I218_ULP_CONFIG1_WOL_HOST
;
1185 phy_reg
&= ~I218_ULP_CONFIG1_WOL_HOST
;
1187 phy_reg
|= I218_ULP_CONFIG1_STICKY_ULP
;
1188 phy_reg
&= ~I218_ULP_CONFIG1_INBAND_EXIT
;
1190 phy_reg
|= I218_ULP_CONFIG1_INBAND_EXIT
;
1191 phy_reg
&= ~I218_ULP_CONFIG1_STICKY_ULP
;
1192 phy_reg
&= ~I218_ULP_CONFIG1_WOL_HOST
;
1194 e1000_write_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, phy_reg
);
1196 /* Set Disable SMBus Release on PERST# in MAC */
1197 mac_reg
= er32(FEXTNVM7
);
1198 mac_reg
|= E1000_FEXTNVM7_DISABLE_SMB_PERST
;
1199 ew32(FEXTNVM7
, mac_reg
);
1201 /* Commit ULP changes in PHY by starting auto ULP configuration */
1202 phy_reg
|= I218_ULP_CONFIG1_START
;
1203 e1000_write_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, phy_reg
);
1205 if ((hw
->phy
.type
== e1000_phy_i217
) && (hw
->phy
.revision
== 6) &&
1206 to_sx
&& (er32(STATUS
) & E1000_STATUS_LU
)) {
1207 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_OEM_BITS
,
1214 hw
->phy
.ops
.release(hw
);
1217 e_dbg("Error in ULP enable flow: %d\n", ret_val
);
1219 hw
->dev_spec
.ich8lan
.ulp_state
= e1000_ulp_state_on
;
1225 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1226 * @hw: pointer to the HW structure
1227 * @force: boolean indicating whether or not to force disabling ULP
1229 * Un-configure ULP mode when link is up, the system is transitioned from
1230 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1231 * system, poll for an indication from ME that ULP has been un-configured.
1232 * If not on an ME enabled system, un-configure the ULP mode by software.
1234 * During nominal operation, this function is called when link is acquired
1235 * to disable ULP mode (force=false); otherwise, for example when unloading
1236 * the driver or during Sx->S0 transitions, this is called with force=true
1237 * to forcibly disable ULP.
1239 static s32
e1000_disable_ulp_lpt_lp(struct e1000_hw
*hw
, bool force
)
1246 if ((hw
->mac
.type
< e1000_pch_lpt
) ||
1247 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPT_I217_LM
) ||
1248 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPT_I217_V
) ||
1249 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_LM2
) ||
1250 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_V2
) ||
1251 (hw
->dev_spec
.ich8lan
.ulp_state
== e1000_ulp_state_off
))
1254 if (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
) {
1255 struct e1000_adapter
*adapter
= hw
->adapter
;
1256 bool firmware_bug
= false;
1259 /* Request ME un-configure ULP mode in the PHY */
1260 mac_reg
= er32(H2ME
);
1261 mac_reg
&= ~E1000_H2ME_ULP
;
1262 mac_reg
|= E1000_H2ME_ENFORCE_SETTINGS
;
1263 ew32(H2ME
, mac_reg
);
1266 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1267 * If this takes more than 1 second, show a warning indicating a
1270 while (er32(FWSM
) & E1000_FWSM_ULP_CFG_DONE
) {
1272 ret_val
= -E1000_ERR_PHY
;
1275 if (i
> 100 && !firmware_bug
)
1276 firmware_bug
= true;
1278 usleep_range(10000, 11000);
1281 e_warn("ULP_CONFIG_DONE took %dmsec. This is a firmware bug\n", i
* 10);
1283 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i
* 10);
1286 mac_reg
= er32(H2ME
);
1287 mac_reg
&= ~E1000_H2ME_ENFORCE_SETTINGS
;
1288 ew32(H2ME
, mac_reg
);
1290 /* Clear H2ME.ULP after ME ULP configuration */
1291 mac_reg
= er32(H2ME
);
1292 mac_reg
&= ~E1000_H2ME_ULP
;
1293 ew32(H2ME
, mac_reg
);
1299 ret_val
= hw
->phy
.ops
.acquire(hw
);
1304 /* Toggle LANPHYPC Value bit */
1305 e1000_toggle_lanphypc_pch_lpt(hw
);
1307 /* Unforce SMBus mode in PHY */
1308 ret_val
= e1000_read_phy_reg_hv_locked(hw
, CV_SMB_CTRL
, &phy_reg
);
1310 /* The MAC might be in PCIe mode, so temporarily force to
1311 * SMBus mode in order to access the PHY.
1313 mac_reg
= er32(CTRL_EXT
);
1314 mac_reg
|= E1000_CTRL_EXT_FORCE_SMBUS
;
1315 ew32(CTRL_EXT
, mac_reg
);
1319 ret_val
= e1000_read_phy_reg_hv_locked(hw
, CV_SMB_CTRL
,
1324 phy_reg
&= ~CV_SMB_CTRL_FORCE_SMBUS
;
1325 e1000_write_phy_reg_hv_locked(hw
, CV_SMB_CTRL
, phy_reg
);
1327 /* Unforce SMBus mode in MAC */
1328 mac_reg
= er32(CTRL_EXT
);
1329 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
1330 ew32(CTRL_EXT
, mac_reg
);
1332 /* When ULP mode was previously entered, K1 was disabled by the
1333 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1335 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_PM_CTRL
, &phy_reg
);
1338 phy_reg
|= HV_PM_CTRL_K1_ENABLE
;
1339 e1000_write_phy_reg_hv_locked(hw
, HV_PM_CTRL
, phy_reg
);
1341 /* Clear ULP enabled configuration */
1342 ret_val
= e1000_read_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, &phy_reg
);
1345 phy_reg
&= ~(I218_ULP_CONFIG1_IND
|
1346 I218_ULP_CONFIG1_STICKY_ULP
|
1347 I218_ULP_CONFIG1_RESET_TO_SMBUS
|
1348 I218_ULP_CONFIG1_WOL_HOST
|
1349 I218_ULP_CONFIG1_INBAND_EXIT
|
1350 I218_ULP_CONFIG1_EN_ULP_LANPHYPC
|
1351 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST
|
1352 I218_ULP_CONFIG1_DISABLE_SMB_PERST
);
1353 e1000_write_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, phy_reg
);
1355 /* Commit ULP changes by starting auto ULP configuration */
1356 phy_reg
|= I218_ULP_CONFIG1_START
;
1357 e1000_write_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, phy_reg
);
1359 /* Clear Disable SMBus Release on PERST# in MAC */
1360 mac_reg
= er32(FEXTNVM7
);
1361 mac_reg
&= ~E1000_FEXTNVM7_DISABLE_SMB_PERST
;
1362 ew32(FEXTNVM7
, mac_reg
);
1365 hw
->phy
.ops
.release(hw
);
1367 e1000_phy_hw_reset(hw
);
1372 e_dbg("Error in ULP disable flow: %d\n", ret_val
);
1374 hw
->dev_spec
.ich8lan
.ulp_state
= e1000_ulp_state_off
;
1380 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1381 * @hw: pointer to the HW structure
1383 * Checks to see of the link status of the hardware has changed. If a
1384 * change in link status has been detected, then we read the PHY registers
1385 * to get the current speed/duplex if link exists.
1387 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw
*hw
)
1389 struct e1000_mac_info
*mac
= &hw
->mac
;
1390 s32 ret_val
, tipg_reg
= 0;
1391 u16 emi_addr
, emi_val
= 0;
1395 /* We only want to go out to the PHY registers to see if Auto-Neg
1396 * has completed and/or if our link status has changed. The
1397 * get_link_status flag is set upon receiving a Link Status
1398 * Change or Rx Sequence Error interrupt.
1400 if (!mac
->get_link_status
)
1402 mac
->get_link_status
= false;
1404 /* First we want to see if the MII Status Register reports
1405 * link. If so, then we want to get the current speed/duplex
1408 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1412 if (hw
->mac
.type
== e1000_pchlan
) {
1413 ret_val
= e1000_k1_gig_workaround_hv(hw
, link
);
1418 /* When connected at 10Mbps half-duplex, some parts are excessively
1419 * aggressive resulting in many collisions. To avoid this, increase
1420 * the IPG and reduce Rx latency in the PHY.
1422 if ((hw
->mac
.type
>= e1000_pch2lan
) && link
) {
1425 e1000e_get_speed_and_duplex_copper(hw
, &speed
, &duplex
);
1426 tipg_reg
= er32(TIPG
);
1427 tipg_reg
&= ~E1000_TIPG_IPGT_MASK
;
1429 if (duplex
== HALF_DUPLEX
&& speed
== SPEED_10
) {
1431 /* Reduce Rx latency in analog PHY */
1433 } else if (hw
->mac
.type
>= e1000_pch_spt
&&
1434 duplex
== FULL_DUPLEX
&& speed
!= SPEED_1000
) {
1439 /* Roll back the default values */
1444 ew32(TIPG
, tipg_reg
);
1446 ret_val
= hw
->phy
.ops
.acquire(hw
);
1450 if (hw
->mac
.type
== e1000_pch2lan
)
1451 emi_addr
= I82579_RX_CONFIG
;
1453 emi_addr
= I217_RX_CONFIG
;
1454 ret_val
= e1000_write_emi_reg_locked(hw
, emi_addr
, emi_val
);
1456 if (hw
->mac
.type
>= e1000_pch_lpt
) {
1459 e1e_rphy_locked(hw
, I217_PLL_CLOCK_GATE_REG
, &phy_reg
);
1460 phy_reg
&= ~I217_PLL_CLOCK_GATE_MASK
;
1461 if (speed
== SPEED_100
|| speed
== SPEED_10
)
1465 e1e_wphy_locked(hw
, I217_PLL_CLOCK_GATE_REG
, phy_reg
);
1467 if (speed
== SPEED_1000
) {
1468 hw
->phy
.ops
.read_reg_locked(hw
, HV_PM_CTRL
,
1471 phy_reg
|= HV_PM_CTRL_K1_CLK_REQ
;
1473 hw
->phy
.ops
.write_reg_locked(hw
, HV_PM_CTRL
,
1477 hw
->phy
.ops
.release(hw
);
1482 if (hw
->mac
.type
>= e1000_pch_spt
) {
1486 if (speed
== SPEED_1000
) {
1487 ret_val
= hw
->phy
.ops
.acquire(hw
);
1491 ret_val
= e1e_rphy_locked(hw
,
1495 hw
->phy
.ops
.release(hw
);
1499 ptr_gap
= (data
& (0x3FF << 2)) >> 2;
1500 if (ptr_gap
< 0x18) {
1501 data
&= ~(0x3FF << 2);
1502 data
|= (0x18 << 2);
1508 hw
->phy
.ops
.release(hw
);
1512 ret_val
= hw
->phy
.ops
.acquire(hw
);
1516 ret_val
= e1e_wphy_locked(hw
,
1519 hw
->phy
.ops
.release(hw
);
1527 /* I217 Packet Loss issue:
1528 * ensure that FEXTNVM4 Beacon Duration is set correctly
1530 * Set the Beacon Duration for I217 to 8 usec
1532 if (hw
->mac
.type
>= e1000_pch_lpt
) {
1535 mac_reg
= er32(FEXTNVM4
);
1536 mac_reg
&= ~E1000_FEXTNVM4_BEACON_DURATION_MASK
;
1537 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_8USEC
;
1538 ew32(FEXTNVM4
, mac_reg
);
1541 /* Work-around I218 hang issue */
1542 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPTLP_I218_LM
) ||
1543 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPTLP_I218_V
) ||
1544 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_LM3
) ||
1545 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_V3
)) {
1546 ret_val
= e1000_k1_workaround_lpt_lp(hw
, link
);
1550 if (hw
->mac
.type
>= e1000_pch_lpt
) {
1551 /* Set platform power management values for
1552 * Latency Tolerance Reporting (LTR)
1554 ret_val
= e1000_platform_pm_pch_lpt(hw
, link
);
1559 /* Clear link partner's EEE ability */
1560 hw
->dev_spec
.ich8lan
.eee_lp_ability
= 0;
1562 if (hw
->mac
.type
>= e1000_pch_lpt
) {
1563 u32 fextnvm6
= er32(FEXTNVM6
);
1565 if (hw
->mac
.type
== e1000_pch_spt
) {
1566 /* FEXTNVM6 K1-off workaround - for SPT only */
1567 u32 pcieanacfg
= er32(PCIEANACFG
);
1569 if (pcieanacfg
& E1000_FEXTNVM6_K1_OFF_ENABLE
)
1570 fextnvm6
|= E1000_FEXTNVM6_K1_OFF_ENABLE
;
1572 fextnvm6
&= ~E1000_FEXTNVM6_K1_OFF_ENABLE
;
1575 if (hw
->dev_spec
.ich8lan
.disable_k1_off
== true)
1576 fextnvm6
&= ~E1000_FEXTNVM6_K1_OFF_ENABLE
;
1578 ew32(FEXTNVM6
, fextnvm6
);
1584 switch (hw
->mac
.type
) {
1586 ret_val
= e1000_k1_workaround_lv(hw
);
1591 if (hw
->phy
.type
== e1000_phy_82578
) {
1592 ret_val
= e1000_link_stall_workaround_hv(hw
);
1597 /* Workaround for PCHx parts in half-duplex:
1598 * Set the number of preambles removed from the packet
1599 * when it is passed from the PHY to the MAC to prevent
1600 * the MAC from misinterpreting the packet type.
1602 e1e_rphy(hw
, HV_KMRN_FIFO_CTRLSTA
, &phy_reg
);
1603 phy_reg
&= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK
;
1605 if ((er32(STATUS
) & E1000_STATUS_FD
) != E1000_STATUS_FD
)
1606 phy_reg
|= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT
);
1608 e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, phy_reg
);
1614 /* Check if there was DownShift, must be checked
1615 * immediately after link-up
1617 e1000e_check_downshift(hw
);
1619 /* Enable/Disable EEE after link up */
1620 if (hw
->phy
.type
> e1000_phy_82579
) {
1621 ret_val
= e1000_set_eee_pchlan(hw
);
1626 /* If we are forcing speed/duplex, then we simply return since
1627 * we have already determined whether we have link or not.
1630 return -E1000_ERR_CONFIG
;
1632 /* Auto-Neg is enabled. Auto Speed Detection takes care
1633 * of MAC speed/duplex configuration. So we only need to
1634 * configure Collision Distance in the MAC.
1636 mac
->ops
.config_collision_dist(hw
);
1638 /* Configure Flow Control now that Auto-Neg has completed.
1639 * First, we need to restore the desired flow control
1640 * settings because we may have had to re-autoneg with a
1641 * different link partner.
1643 ret_val
= e1000e_config_fc_after_link_up(hw
);
1645 e_dbg("Error configuring flow control\n");
1650 mac
->get_link_status
= true;
1654 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
1656 struct e1000_hw
*hw
= &adapter
->hw
;
1659 rc
= e1000_init_mac_params_ich8lan(hw
);
1663 rc
= e1000_init_nvm_params_ich8lan(hw
);
1667 switch (hw
->mac
.type
) {
1670 case e1000_ich10lan
:
1671 rc
= e1000_init_phy_params_ich8lan(hw
);
1681 rc
= e1000_init_phy_params_pchlan(hw
);
1689 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1690 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1692 if ((adapter
->hw
.phy
.type
== e1000_phy_ife
) ||
1693 ((adapter
->hw
.mac
.type
>= e1000_pch2lan
) &&
1694 (!(er32(CTRL_EXT
) & E1000_CTRL_EXT_LSECCK
)))) {
1695 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
1696 adapter
->max_hw_frame_size
= VLAN_ETH_FRAME_LEN
+ ETH_FCS_LEN
;
1698 hw
->mac
.ops
.blink_led
= NULL
;
1701 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
1702 (adapter
->hw
.phy
.type
!= e1000_phy_ife
))
1703 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
1705 /* Enable workaround for 82579 w/ ME enabled */
1706 if ((adapter
->hw
.mac
.type
== e1000_pch2lan
) &&
1707 (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
1708 adapter
->flags2
|= FLAG2_PCIM2PCI_ARBITER_WA
;
1713 static DEFINE_MUTEX(nvm_mutex
);
1716 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1717 * @hw: pointer to the HW structure
1719 * Acquires the mutex for performing NVM operations.
1721 static s32
e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused
*hw
)
1723 mutex_lock(&nvm_mutex
);
1729 * e1000_release_nvm_ich8lan - Release NVM mutex
1730 * @hw: pointer to the HW structure
1732 * Releases the mutex used while performing NVM operations.
1734 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused
*hw
)
1736 mutex_unlock(&nvm_mutex
);
1740 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1741 * @hw: pointer to the HW structure
1743 * Acquires the software control flag for performing PHY and select
1746 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
1748 u32 extcnf_ctrl
, timeout
= PHY_CFG_TIMEOUT
;
1751 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE
,
1752 &hw
->adapter
->state
)) {
1753 e_dbg("contention for Phy access\n");
1754 return -E1000_ERR_PHY
;
1758 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1759 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
))
1767 e_dbg("SW has already locked the resource.\n");
1768 ret_val
= -E1000_ERR_CONFIG
;
1772 timeout
= SW_FLAG_TIMEOUT
;
1774 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
1775 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1778 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1779 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
1787 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1788 er32(FWSM
), extcnf_ctrl
);
1789 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
1790 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1791 ret_val
= -E1000_ERR_CONFIG
;
1797 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
1803 * e1000_release_swflag_ich8lan - Release software control flag
1804 * @hw: pointer to the HW structure
1806 * Releases the software control flag for performing PHY and select
1809 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
1813 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1815 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
) {
1816 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
1817 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1819 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1822 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
1826 * e1000_check_mng_mode_ich8lan - Checks management mode
1827 * @hw: pointer to the HW structure
1829 * This checks if the adapter has any manageability enabled.
1830 * This is a function pointer entry point only called by read/write
1831 * routines for the PHY and NVM parts.
1833 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
1838 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
1839 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1840 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
1844 * e1000_check_mng_mode_pchlan - Checks management mode
1845 * @hw: pointer to the HW structure
1847 * This checks if the adapter has iAMT enabled.
1848 * This is a function pointer entry point only called by read/write
1849 * routines for the PHY and NVM parts.
1851 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
)
1856 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
1857 (fwsm
& (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
1861 * e1000_rar_set_pch2lan - Set receive address register
1862 * @hw: pointer to the HW structure
1863 * @addr: pointer to the receive address
1864 * @index: receive address array register
1866 * Sets the receive address array register at index to the address passed
1867 * in by addr. For 82579, RAR[0] is the base address register that is to
1868 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1869 * Use SHRA[0-3] in place of those reserved for ME.
1871 static int e1000_rar_set_pch2lan(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
1873 u32 rar_low
, rar_high
;
1875 /* HW expects these in little endian so we reverse the byte order
1876 * from network order (big endian) to little endian
1878 rar_low
= ((u32
)addr
[0] |
1879 ((u32
)addr
[1] << 8) |
1880 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
1882 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1884 /* If MAC address zero, no need to set the AV bit */
1885 if (rar_low
|| rar_high
)
1886 rar_high
|= E1000_RAH_AV
;
1889 ew32(RAL(index
), rar_low
);
1891 ew32(RAH(index
), rar_high
);
1896 /* RAR[1-6] are owned by manageability. Skip those and program the
1897 * next address into the SHRA register array.
1899 if (index
< (u32
)(hw
->mac
.rar_entry_count
)) {
1902 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1906 ew32(SHRAL(index
- 1), rar_low
);
1908 ew32(SHRAH(index
- 1), rar_high
);
1911 e1000_release_swflag_ich8lan(hw
);
1913 /* verify the register updates */
1914 if ((er32(SHRAL(index
- 1)) == rar_low
) &&
1915 (er32(SHRAH(index
- 1)) == rar_high
))
1918 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1919 (index
- 1), er32(FWSM
));
1923 e_dbg("Failed to write receive address at index %d\n", index
);
1924 return -E1000_ERR_CONFIG
;
1928 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1929 * @hw: pointer to the HW structure
1931 * Get the number of available receive registers that the Host can
1932 * program. SHRA[0-10] are the shared receive address registers
1933 * that are shared between the Host and manageability engine (ME).
1934 * ME can reserve any number of addresses and the host needs to be
1935 * able to tell how many available registers it has access to.
1937 static u32
e1000_rar_get_count_pch_lpt(struct e1000_hw
*hw
)
1942 wlock_mac
= er32(FWSM
) & E1000_FWSM_WLOCK_MAC_MASK
;
1943 wlock_mac
>>= E1000_FWSM_WLOCK_MAC_SHIFT
;
1945 switch (wlock_mac
) {
1947 /* All SHRA[0..10] and RAR[0] available */
1948 num_entries
= hw
->mac
.rar_entry_count
;
1951 /* Only RAR[0] available */
1955 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1956 num_entries
= wlock_mac
+ 1;
1964 * e1000_rar_set_pch_lpt - Set receive address registers
1965 * @hw: pointer to the HW structure
1966 * @addr: pointer to the receive address
1967 * @index: receive address array register
1969 * Sets the receive address register array at index to the address passed
1970 * in by addr. For LPT, RAR[0] is the base address register that is to
1971 * contain the MAC address. SHRA[0-10] are the shared receive address
1972 * registers that are shared between the Host and manageability engine (ME).
1974 static int e1000_rar_set_pch_lpt(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
1976 u32 rar_low
, rar_high
;
1979 /* HW expects these in little endian so we reverse the byte order
1980 * from network order (big endian) to little endian
1982 rar_low
= ((u32
)addr
[0] | ((u32
)addr
[1] << 8) |
1983 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
1985 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1987 /* If MAC address zero, no need to set the AV bit */
1988 if (rar_low
|| rar_high
)
1989 rar_high
|= E1000_RAH_AV
;
1992 ew32(RAL(index
), rar_low
);
1994 ew32(RAH(index
), rar_high
);
1999 /* The manageability engine (ME) can lock certain SHRAR registers that
2000 * it is using - those registers are unavailable for use.
2002 if (index
< hw
->mac
.rar_entry_count
) {
2003 wlock_mac
= er32(FWSM
) & E1000_FWSM_WLOCK_MAC_MASK
;
2004 wlock_mac
>>= E1000_FWSM_WLOCK_MAC_SHIFT
;
2006 /* Check if all SHRAR registers are locked */
2010 if ((wlock_mac
== 0) || (index
<= wlock_mac
)) {
2013 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
2018 ew32(SHRAL_PCH_LPT(index
- 1), rar_low
);
2020 ew32(SHRAH_PCH_LPT(index
- 1), rar_high
);
2023 e1000_release_swflag_ich8lan(hw
);
2025 /* verify the register updates */
2026 if ((er32(SHRAL_PCH_LPT(index
- 1)) == rar_low
) &&
2027 (er32(SHRAH_PCH_LPT(index
- 1)) == rar_high
))
2033 e_dbg("Failed to write receive address at index %d\n", index
);
2034 return -E1000_ERR_CONFIG
;
2038 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2039 * @hw: pointer to the HW structure
2041 * Checks if firmware is blocking the reset of the PHY.
2042 * This is a function pointer entry point only called by
2045 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
2047 bool blocked
= false;
2050 while ((blocked
= !(er32(FWSM
) & E1000_ICH_FWSM_RSPCIPHY
)) &&
2052 usleep_range(10000, 11000);
2053 return blocked
? E1000_BLK_PHY_RESET
: 0;
2057 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2058 * @hw: pointer to the HW structure
2060 * Assumes semaphore already acquired.
2063 static s32
e1000_write_smbus_addr(struct e1000_hw
*hw
)
2066 u32 strap
= er32(STRAP
);
2067 u32 freq
= (strap
& E1000_STRAP_SMT_FREQ_MASK
) >>
2068 E1000_STRAP_SMT_FREQ_SHIFT
;
2071 strap
&= E1000_STRAP_SMBUS_ADDRESS_MASK
;
2073 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, &phy_data
);
2077 phy_data
&= ~HV_SMB_ADDR_MASK
;
2078 phy_data
|= (strap
>> E1000_STRAP_SMBUS_ADDRESS_SHIFT
);
2079 phy_data
|= HV_SMB_ADDR_PEC_EN
| HV_SMB_ADDR_VALID
;
2081 if (hw
->phy
.type
== e1000_phy_i217
) {
2082 /* Restore SMBus frequency */
2084 phy_data
&= ~HV_SMB_ADDR_FREQ_MASK
;
2085 phy_data
|= (freq
& BIT(0)) <<
2086 HV_SMB_ADDR_FREQ_LOW_SHIFT
;
2087 phy_data
|= (freq
& BIT(1)) <<
2088 (HV_SMB_ADDR_FREQ_HIGH_SHIFT
- 1);
2090 e_dbg("Unsupported SMB frequency in PHY\n");
2094 return e1000_write_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, phy_data
);
2098 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2099 * @hw: pointer to the HW structure
2101 * SW should configure the LCD from the NVM extended configuration region
2102 * as a workaround for certain parts.
2104 static s32
e1000_sw_lcd_config_ich8lan(struct e1000_hw
*hw
)
2106 struct e1000_phy_info
*phy
= &hw
->phy
;
2107 u32 i
, data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
2109 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
2111 /* Initialize the PHY from the NVM on ICH platforms. This
2112 * is needed due to an issue where the NVM configuration is
2113 * not properly autoloaded after power transitions.
2114 * Therefore, after each PHY reset, we will load the
2115 * configuration data out of the NVM manually.
2117 switch (hw
->mac
.type
) {
2119 if (phy
->type
!= e1000_phy_igp_3
)
2122 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_AMT
) ||
2123 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_C
)) {
2124 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
2136 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
2142 ret_val
= hw
->phy
.ops
.acquire(hw
);
2146 data
= er32(FEXTNVM
);
2147 if (!(data
& sw_cfg_mask
))
2150 /* Make sure HW does not configure LCD from PHY
2151 * extended configuration before SW configuration
2153 data
= er32(EXTCNF_CTRL
);
2154 if ((hw
->mac
.type
< e1000_pch2lan
) &&
2155 (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
))
2158 cnf_size
= er32(EXTCNF_SIZE
);
2159 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
2160 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
2164 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
2165 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
2167 if (((hw
->mac
.type
== e1000_pchlan
) &&
2168 !(data
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)) ||
2169 (hw
->mac
.type
> e1000_pchlan
)) {
2170 /* HW configures the SMBus address and LEDs when the
2171 * OEM and LCD Write Enable bits are set in the NVM.
2172 * When both NVM bits are cleared, SW will configure
2175 ret_val
= e1000_write_smbus_addr(hw
);
2179 data
= er32(LEDCTL
);
2180 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_LED_CONFIG
,
2186 /* Configure LCD from extended configuration region. */
2188 /* cnf_base_addr is in DWORD */
2189 word_addr
= (u16
)(cnf_base_addr
<< 1);
2191 for (i
= 0; i
< cnf_size
; i
++) {
2192 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2), 1, ®_data
);
2196 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2 + 1),
2201 /* Save off the PHY page for future writes. */
2202 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
2203 phy_page
= reg_data
;
2207 reg_addr
&= PHY_REG_MASK
;
2208 reg_addr
|= phy_page
;
2210 ret_val
= e1e_wphy_locked(hw
, (u32
)reg_addr
, reg_data
);
2216 hw
->phy
.ops
.release(hw
);
2221 * e1000_k1_gig_workaround_hv - K1 Si workaround
2222 * @hw: pointer to the HW structure
2223 * @link: link up bool flag
2225 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2226 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2227 * If link is down, the function will restore the default K1 setting located
2230 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
)
2234 bool k1_enable
= hw
->dev_spec
.ich8lan
.nvm_k1_enabled
;
2236 if (hw
->mac
.type
!= e1000_pchlan
)
2239 /* Wrap the whole flow with the sw flag */
2240 ret_val
= hw
->phy
.ops
.acquire(hw
);
2244 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2246 if (hw
->phy
.type
== e1000_phy_82578
) {
2247 ret_val
= e1e_rphy_locked(hw
, BM_CS_STATUS
,
2252 status_reg
&= (BM_CS_STATUS_LINK_UP
|
2253 BM_CS_STATUS_RESOLVED
|
2254 BM_CS_STATUS_SPEED_MASK
);
2256 if (status_reg
== (BM_CS_STATUS_LINK_UP
|
2257 BM_CS_STATUS_RESOLVED
|
2258 BM_CS_STATUS_SPEED_1000
))
2262 if (hw
->phy
.type
== e1000_phy_82577
) {
2263 ret_val
= e1e_rphy_locked(hw
, HV_M_STATUS
, &status_reg
);
2267 status_reg
&= (HV_M_STATUS_LINK_UP
|
2268 HV_M_STATUS_AUTONEG_COMPLETE
|
2269 HV_M_STATUS_SPEED_MASK
);
2271 if (status_reg
== (HV_M_STATUS_LINK_UP
|
2272 HV_M_STATUS_AUTONEG_COMPLETE
|
2273 HV_M_STATUS_SPEED_1000
))
2277 /* Link stall fix for link up */
2278 ret_val
= e1e_wphy_locked(hw
, PHY_REG(770, 19), 0x0100);
2283 /* Link stall fix for link down */
2284 ret_val
= e1e_wphy_locked(hw
, PHY_REG(770, 19), 0x4100);
2289 ret_val
= e1000_configure_k1_ich8lan(hw
, k1_enable
);
2292 hw
->phy
.ops
.release(hw
);
2298 * e1000_configure_k1_ich8lan - Configure K1 power state
2299 * @hw: pointer to the HW structure
2300 * @k1_enable: K1 state to configure
2302 * Configure the K1 power state based on the provided parameter.
2303 * Assumes semaphore already acquired.
2305 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2307 s32
e1000_configure_k1_ich8lan(struct e1000_hw
*hw
, bool k1_enable
)
2315 ret_val
= e1000e_read_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
2321 kmrn_reg
|= E1000_KMRNCTRLSTA_K1_ENABLE
;
2323 kmrn_reg
&= ~E1000_KMRNCTRLSTA_K1_ENABLE
;
2325 ret_val
= e1000e_write_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
2330 usleep_range(20, 40);
2331 ctrl_ext
= er32(CTRL_EXT
);
2332 ctrl_reg
= er32(CTRL
);
2334 reg
= ctrl_reg
& ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
2335 reg
|= E1000_CTRL_FRCSPD
;
2338 ew32(CTRL_EXT
, ctrl_ext
| E1000_CTRL_EXT_SPD_BYPS
);
2340 usleep_range(20, 40);
2341 ew32(CTRL
, ctrl_reg
);
2342 ew32(CTRL_EXT
, ctrl_ext
);
2344 usleep_range(20, 40);
2350 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2351 * @hw: pointer to the HW structure
2352 * @d0_state: boolean if entering d0 or d3 device state
2354 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2355 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2356 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2358 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
)
2364 if (hw
->mac
.type
< e1000_pchlan
)
2367 ret_val
= hw
->phy
.ops
.acquire(hw
);
2371 if (hw
->mac
.type
== e1000_pchlan
) {
2372 mac_reg
= er32(EXTCNF_CTRL
);
2373 if (mac_reg
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)
2377 mac_reg
= er32(FEXTNVM
);
2378 if (!(mac_reg
& E1000_FEXTNVM_SW_CONFIG_ICH8M
))
2381 mac_reg
= er32(PHY_CTRL
);
2383 ret_val
= e1e_rphy_locked(hw
, HV_OEM_BITS
, &oem_reg
);
2387 oem_reg
&= ~(HV_OEM_BITS_GBE_DIS
| HV_OEM_BITS_LPLU
);
2390 if (mac_reg
& E1000_PHY_CTRL_GBE_DISABLE
)
2391 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
2393 if (mac_reg
& E1000_PHY_CTRL_D0A_LPLU
)
2394 oem_reg
|= HV_OEM_BITS_LPLU
;
2396 if (mac_reg
& (E1000_PHY_CTRL_GBE_DISABLE
|
2397 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
))
2398 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
2400 if (mac_reg
& (E1000_PHY_CTRL_D0A_LPLU
|
2401 E1000_PHY_CTRL_NOND0A_LPLU
))
2402 oem_reg
|= HV_OEM_BITS_LPLU
;
2405 /* Set Restart auto-neg to activate the bits */
2406 if ((d0_state
|| (hw
->mac
.type
!= e1000_pchlan
)) &&
2407 !hw
->phy
.ops
.check_reset_block(hw
))
2408 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
2410 ret_val
= e1e_wphy_locked(hw
, HV_OEM_BITS
, oem_reg
);
2413 hw
->phy
.ops
.release(hw
);
2419 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2420 * @hw: pointer to the HW structure
2422 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
)
2427 ret_val
= e1e_rphy(hw
, HV_KMRN_MODE_CTRL
, &data
);
2431 data
|= HV_KMRN_MDIO_SLOW
;
2433 ret_val
= e1e_wphy(hw
, HV_KMRN_MODE_CTRL
, data
);
2439 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2440 * @hw: pointer to the HW structure
2442 * A series of PHY workarounds to be done after every PHY reset.
2444 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
2449 if (hw
->mac
.type
!= e1000_pchlan
)
2452 /* Set MDIO slow mode before any other MDIO access */
2453 if (hw
->phy
.type
== e1000_phy_82577
) {
2454 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
2459 if (((hw
->phy
.type
== e1000_phy_82577
) &&
2460 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
2461 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
2462 /* Disable generation of early preamble */
2463 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
2467 /* Preamble tuning for SSC */
2468 ret_val
= e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, 0xA204);
2473 if (hw
->phy
.type
== e1000_phy_82578
) {
2474 /* Return registers to default by doing a soft reset then
2475 * writing 0x3140 to the control register.
2477 if (hw
->phy
.revision
< 2) {
2478 e1000e_phy_sw_reset(hw
);
2479 ret_val
= e1e_wphy(hw
, MII_BMCR
, 0x3140);
2486 ret_val
= hw
->phy
.ops
.acquire(hw
);
2491 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
2492 hw
->phy
.ops
.release(hw
);
2496 /* Configure the K1 Si workaround during phy reset assuming there is
2497 * link so that it disables K1 if link is in 1Gbps.
2499 ret_val
= e1000_k1_gig_workaround_hv(hw
, true);
2503 /* Workaround for link disconnects on a busy hub in half duplex */
2504 ret_val
= hw
->phy
.ops
.acquire(hw
);
2507 ret_val
= e1e_rphy_locked(hw
, BM_PORT_GEN_CFG
, &phy_data
);
2510 ret_val
= e1e_wphy_locked(hw
, BM_PORT_GEN_CFG
, phy_data
& 0x00FF);
2514 /* set MSE higher to enable link to stay up when noise is high */
2515 ret_val
= e1000_write_emi_reg_locked(hw
, I82577_MSE_THRESHOLD
, 0x0034);
2517 hw
->phy
.ops
.release(hw
);
2523 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2524 * @hw: pointer to the HW structure
2526 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw
*hw
)
2532 ret_val
= hw
->phy
.ops
.acquire(hw
);
2535 ret_val
= e1000_enable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
2539 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2540 for (i
= 0; i
< (hw
->mac
.rar_entry_count
); i
++) {
2541 mac_reg
= er32(RAL(i
));
2542 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_L(i
),
2543 (u16
)(mac_reg
& 0xFFFF));
2544 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_M(i
),
2545 (u16
)((mac_reg
>> 16) & 0xFFFF));
2547 mac_reg
= er32(RAH(i
));
2548 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_H(i
),
2549 (u16
)(mac_reg
& 0xFFFF));
2550 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_CTRL(i
),
2551 (u16
)((mac_reg
& E1000_RAH_AV
)
2555 e1000_disable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
2558 hw
->phy
.ops
.release(hw
);
2562 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2564 * @hw: pointer to the HW structure
2565 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2567 s32
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
*hw
, bool enable
)
2574 if (hw
->mac
.type
< e1000_pch2lan
)
2577 /* disable Rx path while enabling/disabling workaround */
2578 e1e_rphy(hw
, PHY_REG(769, 20), &phy_reg
);
2579 ret_val
= e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
| BIT(14));
2584 /* Write Rx addresses (rar_entry_count for RAL/H, and
2585 * SHRAL/H) and initial CRC values to the MAC
2587 for (i
= 0; i
< hw
->mac
.rar_entry_count
; i
++) {
2588 u8 mac_addr
[ETH_ALEN
] = { 0 };
2589 u32 addr_high
, addr_low
;
2591 addr_high
= er32(RAH(i
));
2592 if (!(addr_high
& E1000_RAH_AV
))
2594 addr_low
= er32(RAL(i
));
2595 mac_addr
[0] = (addr_low
& 0xFF);
2596 mac_addr
[1] = ((addr_low
>> 8) & 0xFF);
2597 mac_addr
[2] = ((addr_low
>> 16) & 0xFF);
2598 mac_addr
[3] = ((addr_low
>> 24) & 0xFF);
2599 mac_addr
[4] = (addr_high
& 0xFF);
2600 mac_addr
[5] = ((addr_high
>> 8) & 0xFF);
2602 ew32(PCH_RAICC(i
), ~ether_crc_le(ETH_ALEN
, mac_addr
));
2605 /* Write Rx addresses to the PHY */
2606 e1000_copy_rx_addrs_to_phy_ich8lan(hw
);
2608 /* Enable jumbo frame workaround in the MAC */
2609 mac_reg
= er32(FFLT_DBG
);
2610 mac_reg
&= ~BIT(14);
2611 mac_reg
|= (7 << 15);
2612 ew32(FFLT_DBG
, mac_reg
);
2614 mac_reg
= er32(RCTL
);
2615 mac_reg
|= E1000_RCTL_SECRC
;
2616 ew32(RCTL
, mac_reg
);
2618 ret_val
= e1000e_read_kmrn_reg(hw
,
2619 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2623 ret_val
= e1000e_write_kmrn_reg(hw
,
2624 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2628 ret_val
= e1000e_read_kmrn_reg(hw
,
2629 E1000_KMRNCTRLSTA_HD_CTRL
,
2633 data
&= ~(0xF << 8);
2635 ret_val
= e1000e_write_kmrn_reg(hw
,
2636 E1000_KMRNCTRLSTA_HD_CTRL
,
2641 /* Enable jumbo frame workaround in the PHY */
2642 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
2643 data
&= ~(0x7F << 5);
2644 data
|= (0x37 << 5);
2645 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
2648 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
2650 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
2653 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
2654 data
&= ~(0x3FF << 2);
2655 data
|= (E1000_TX_PTR_GAP
<< 2);
2656 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
2659 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0xF100);
2662 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
2663 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
| BIT(10));
2667 /* Write MAC register values back to h/w defaults */
2668 mac_reg
= er32(FFLT_DBG
);
2669 mac_reg
&= ~(0xF << 14);
2670 ew32(FFLT_DBG
, mac_reg
);
2672 mac_reg
= er32(RCTL
);
2673 mac_reg
&= ~E1000_RCTL_SECRC
;
2674 ew32(RCTL
, mac_reg
);
2676 ret_val
= e1000e_read_kmrn_reg(hw
,
2677 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2681 ret_val
= e1000e_write_kmrn_reg(hw
,
2682 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2686 ret_val
= e1000e_read_kmrn_reg(hw
,
2687 E1000_KMRNCTRLSTA_HD_CTRL
,
2691 data
&= ~(0xF << 8);
2693 ret_val
= e1000e_write_kmrn_reg(hw
,
2694 E1000_KMRNCTRLSTA_HD_CTRL
,
2699 /* Write PHY register values back to h/w defaults */
2700 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
2701 data
&= ~(0x7F << 5);
2702 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
2705 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
2707 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
2710 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
2711 data
&= ~(0x3FF << 2);
2713 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
2716 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0x7E00);
2719 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
2720 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
& ~BIT(10));
2725 /* re-enable Rx path after enabling/disabling workaround */
2726 return e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
& ~BIT(14));
2730 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2731 * @hw: pointer to the HW structure
2733 * A series of PHY workarounds to be done after every PHY reset.
2735 static s32
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
2739 if (hw
->mac
.type
!= e1000_pch2lan
)
2742 /* Set MDIO slow mode before any other MDIO access */
2743 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
2747 ret_val
= hw
->phy
.ops
.acquire(hw
);
2750 /* set MSE higher to enable link to stay up when noise is high */
2751 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_MSE_THRESHOLD
, 0x0034);
2754 /* drop link after 5 times MSE threshold was reached */
2755 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_MSE_LINK_DOWN
, 0x0005);
2757 hw
->phy
.ops
.release(hw
);
2763 * e1000_k1_gig_workaround_lv - K1 Si workaround
2764 * @hw: pointer to the HW structure
2766 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2767 * Disable K1 in 1000Mbps and 100Mbps
2769 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
)
2774 if (hw
->mac
.type
!= e1000_pch2lan
)
2777 /* Set K1 beacon duration based on 10Mbs speed */
2778 ret_val
= e1e_rphy(hw
, HV_M_STATUS
, &status_reg
);
2782 if ((status_reg
& (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
))
2783 == (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
)) {
2785 (HV_M_STATUS_SPEED_1000
| HV_M_STATUS_SPEED_100
)) {
2788 /* LV 1G/100 Packet drop issue wa */
2789 ret_val
= e1e_rphy(hw
, HV_PM_CTRL
, &pm_phy_reg
);
2792 pm_phy_reg
&= ~HV_PM_CTRL_K1_ENABLE
;
2793 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, pm_phy_reg
);
2799 mac_reg
= er32(FEXTNVM4
);
2800 mac_reg
&= ~E1000_FEXTNVM4_BEACON_DURATION_MASK
;
2801 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_16USEC
;
2802 ew32(FEXTNVM4
, mac_reg
);
2810 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2811 * @hw: pointer to the HW structure
2812 * @gate: boolean set to true to gate, false to ungate
2814 * Gate/ungate the automatic PHY configuration via hardware; perform
2815 * the configuration via software instead.
2817 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
)
2821 if (hw
->mac
.type
< e1000_pch2lan
)
2824 extcnf_ctrl
= er32(EXTCNF_CTRL
);
2827 extcnf_ctrl
|= E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
2829 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
2831 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
2835 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2836 * @hw: pointer to the HW structure
2838 * Check the appropriate indication the MAC has finished configuring the
2839 * PHY after a software reset.
2841 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
)
2843 u32 data
, loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
2845 /* Wait for basic configuration completes before proceeding */
2847 data
= er32(STATUS
);
2848 data
&= E1000_STATUS_LAN_INIT_DONE
;
2849 usleep_range(100, 200);
2850 } while ((!data
) && --loop
);
2852 /* If basic configuration is incomplete before the above loop
2853 * count reaches 0, loading the configuration from NVM will
2854 * leave the PHY in a bad state possibly resulting in no link.
2857 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2859 /* Clear the Init Done bit for the next init event */
2860 data
= er32(STATUS
);
2861 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
2866 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2867 * @hw: pointer to the HW structure
2869 static s32
e1000_post_phy_reset_ich8lan(struct e1000_hw
*hw
)
2874 if (hw
->phy
.ops
.check_reset_block(hw
))
2877 /* Allow time for h/w to get to quiescent state after reset */
2878 usleep_range(10000, 11000);
2880 /* Perform any necessary post-reset workarounds */
2881 switch (hw
->mac
.type
) {
2883 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
2888 ret_val
= e1000_lv_phy_workarounds_ich8lan(hw
);
2896 /* Clear the host wakeup bit after lcd reset */
2897 if (hw
->mac
.type
>= e1000_pchlan
) {
2898 e1e_rphy(hw
, BM_PORT_GEN_CFG
, ®
);
2899 reg
&= ~BM_WUC_HOST_WU_BIT
;
2900 e1e_wphy(hw
, BM_PORT_GEN_CFG
, reg
);
2903 /* Configure the LCD with the extended configuration region in NVM */
2904 ret_val
= e1000_sw_lcd_config_ich8lan(hw
);
2908 /* Configure the LCD with the OEM bits in NVM */
2909 ret_val
= e1000_oem_bits_config_ich8lan(hw
, true);
2911 if (hw
->mac
.type
== e1000_pch2lan
) {
2912 /* Ungate automatic PHY configuration on non-managed 82579 */
2913 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
2914 usleep_range(10000, 11000);
2915 e1000_gate_hw_phy_config_ich8lan(hw
, false);
2918 /* Set EEE LPI Update Timer to 200usec */
2919 ret_val
= hw
->phy
.ops
.acquire(hw
);
2922 ret_val
= e1000_write_emi_reg_locked(hw
,
2923 I82579_LPI_UPDATE_TIMER
,
2925 hw
->phy
.ops
.release(hw
);
2932 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2933 * @hw: pointer to the HW structure
2936 * This is a function pointer entry point called by drivers
2937 * or other shared routines.
2939 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
2943 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2944 if ((hw
->mac
.type
== e1000_pch2lan
) &&
2945 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
2946 e1000_gate_hw_phy_config_ich8lan(hw
, true);
2948 ret_val
= e1000e_phy_hw_reset_generic(hw
);
2952 return e1000_post_phy_reset_ich8lan(hw
);
2956 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2957 * @hw: pointer to the HW structure
2958 * @active: true to enable LPLU, false to disable
2960 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2961 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2962 * the phy speed. This function will manually set the LPLU bit and restart
2963 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2964 * since it configures the same bit.
2966 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
)
2971 ret_val
= e1e_rphy(hw
, HV_OEM_BITS
, &oem_reg
);
2976 oem_reg
|= HV_OEM_BITS_LPLU
;
2978 oem_reg
&= ~HV_OEM_BITS_LPLU
;
2980 if (!hw
->phy
.ops
.check_reset_block(hw
))
2981 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
2983 return e1e_wphy(hw
, HV_OEM_BITS
, oem_reg
);
2987 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2988 * @hw: pointer to the HW structure
2989 * @active: true to enable LPLU, false to disable
2991 * Sets the LPLU D0 state according to the active flag. When
2992 * activating LPLU this function also disables smart speed
2993 * and vice versa. LPLU will not be activated unless the
2994 * device autonegotiation advertisement meets standards of
2995 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2996 * This is a function pointer entry point only called by
2997 * PHY setup routines.
2999 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
3001 struct e1000_phy_info
*phy
= &hw
->phy
;
3006 if (phy
->type
== e1000_phy_ife
)
3009 phy_ctrl
= er32(PHY_CTRL
);
3012 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
3013 ew32(PHY_CTRL
, phy_ctrl
);
3015 if (phy
->type
!= e1000_phy_igp_3
)
3018 /* Call gig speed drop workaround on LPLU before accessing
3021 if (hw
->mac
.type
== e1000_ich8lan
)
3022 e1000e_gig_downshift_workaround_ich8lan(hw
);
3024 /* When LPLU is enabled, we should disable SmartSpeed */
3025 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
3028 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
3029 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
3033 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
3034 ew32(PHY_CTRL
, phy_ctrl
);
3036 if (phy
->type
!= e1000_phy_igp_3
)
3039 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3040 * during Dx states where the power conservation is most
3041 * important. During driver activity we should enable
3042 * SmartSpeed, so performance is maintained.
3044 if (phy
->smart_speed
== e1000_smart_speed_on
) {
3045 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3050 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
3051 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3055 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
3056 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3061 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
3062 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3073 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3074 * @hw: pointer to the HW structure
3075 * @active: true to enable LPLU, false to disable
3077 * Sets the LPLU D3 state according to the active flag. When
3078 * activating LPLU this function also disables smart speed
3079 * and vice versa. LPLU will not be activated unless the
3080 * device autonegotiation advertisement meets standards of
3081 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3082 * This is a function pointer entry point only called by
3083 * PHY setup routines.
3085 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
3087 struct e1000_phy_info
*phy
= &hw
->phy
;
3092 phy_ctrl
= er32(PHY_CTRL
);
3095 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
3096 ew32(PHY_CTRL
, phy_ctrl
);
3098 if (phy
->type
!= e1000_phy_igp_3
)
3101 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3102 * during Dx states where the power conservation is most
3103 * important. During driver activity we should enable
3104 * SmartSpeed, so performance is maintained.
3106 if (phy
->smart_speed
== e1000_smart_speed_on
) {
3107 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3112 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
3113 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3117 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
3118 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3123 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
3124 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3129 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
3130 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
3131 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
3132 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
3133 ew32(PHY_CTRL
, phy_ctrl
);
3135 if (phy
->type
!= e1000_phy_igp_3
)
3138 /* Call gig speed drop workaround on LPLU before accessing
3141 if (hw
->mac
.type
== e1000_ich8lan
)
3142 e1000e_gig_downshift_workaround_ich8lan(hw
);
3144 /* When LPLU is enabled, we should disable SmartSpeed */
3145 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
3149 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
3150 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
3157 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3158 * @hw: pointer to the HW structure
3159 * @bank: pointer to the variable that returns the active bank
3161 * Reads signature byte from the NVM using the flash access registers.
3162 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3164 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
3167 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3168 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
3169 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
3174 switch (hw
->mac
.type
) {
3180 bank1_offset
= nvm
->flash_bank_size
;
3181 act_offset
= E1000_ICH_NVM_SIG_WORD
;
3183 /* set bank to 0 in case flash read fails */
3187 ret_val
= e1000_read_flash_dword_ich8lan(hw
, act_offset
,
3191 sig_byte
= (u8
)((nvm_dword
& 0xFF00) >> 8);
3192 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
3193 E1000_ICH_NVM_SIG_VALUE
) {
3199 ret_val
= e1000_read_flash_dword_ich8lan(hw
, act_offset
+
3204 sig_byte
= (u8
)((nvm_dword
& 0xFF00) >> 8);
3205 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
3206 E1000_ICH_NVM_SIG_VALUE
) {
3211 e_dbg("ERROR: No valid NVM bank present\n");
3212 return -E1000_ERR_NVM
;
3216 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
3217 E1000_EECD_SEC1VAL_VALID_MASK
) {
3218 if (eecd
& E1000_EECD_SEC1VAL
)
3225 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3228 /* set bank to 0 in case flash read fails */
3232 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
3236 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
3237 E1000_ICH_NVM_SIG_VALUE
) {
3243 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
3248 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
3249 E1000_ICH_NVM_SIG_VALUE
) {
3254 e_dbg("ERROR: No valid NVM bank present\n");
3255 return -E1000_ERR_NVM
;
3260 * e1000_read_nvm_spt - NVM access for SPT
3261 * @hw: pointer to the HW structure
3262 * @offset: The offset (in bytes) of the word(s) to read.
3263 * @words: Size of data to read in words.
3264 * @data: pointer to the word(s) to read at offset.
3266 * Reads a word(s) from the NVM
3268 static s32
e1000_read_nvm_spt(struct e1000_hw
*hw
, u16 offset
, u16 words
,
3271 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3272 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3280 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
3282 e_dbg("nvm parameter(s) out of bounds\n");
3283 ret_val
= -E1000_ERR_NVM
;
3287 nvm
->ops
.acquire(hw
);
3289 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
3291 e_dbg("Could not detect valid bank, assuming bank 0\n");
3295 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
3296 act_offset
+= offset
;
3300 for (i
= 0; i
< words
; i
+= 2) {
3301 if (words
- i
== 1) {
3302 if (dev_spec
->shadow_ram
[offset
+ i
].modified
) {
3304 dev_spec
->shadow_ram
[offset
+ i
].value
;
3306 offset_to_read
= act_offset
+ i
-
3307 ((act_offset
+ i
) % 2);
3309 e1000_read_flash_dword_ich8lan(hw
,
3314 if ((act_offset
+ i
) % 2 == 0)
3315 data
[i
] = (u16
)(dword
& 0xFFFF);
3317 data
[i
] = (u16
)((dword
>> 16) & 0xFFFF);
3320 offset_to_read
= act_offset
+ i
;
3321 if (!(dev_spec
->shadow_ram
[offset
+ i
].modified
) ||
3322 !(dev_spec
->shadow_ram
[offset
+ i
+ 1].modified
)) {
3324 e1000_read_flash_dword_ich8lan(hw
,
3330 if (dev_spec
->shadow_ram
[offset
+ i
].modified
)
3332 dev_spec
->shadow_ram
[offset
+ i
].value
;
3334 data
[i
] = (u16
)(dword
& 0xFFFF);
3335 if (dev_spec
->shadow_ram
[offset
+ i
].modified
)
3337 dev_spec
->shadow_ram
[offset
+ i
+ 1].value
;
3339 data
[i
+ 1] = (u16
)(dword
>> 16 & 0xFFFF);
3343 nvm
->ops
.release(hw
);
3347 e_dbg("NVM read error: %d\n", ret_val
);
3353 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3354 * @hw: pointer to the HW structure
3355 * @offset: The offset (in bytes) of the word(s) to read.
3356 * @words: Size of data to read in words
3357 * @data: Pointer to the word(s) to read at offset.
3359 * Reads a word(s) from the NVM using the flash access registers.
3361 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
3364 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3365 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3371 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
3373 e_dbg("nvm parameter(s) out of bounds\n");
3374 ret_val
= -E1000_ERR_NVM
;
3378 nvm
->ops
.acquire(hw
);
3380 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
3382 e_dbg("Could not detect valid bank, assuming bank 0\n");
3386 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
3387 act_offset
+= offset
;
3390 for (i
= 0; i
< words
; i
++) {
3391 if (dev_spec
->shadow_ram
[offset
+ i
].modified
) {
3392 data
[i
] = dev_spec
->shadow_ram
[offset
+ i
].value
;
3394 ret_val
= e1000_read_flash_word_ich8lan(hw
,
3403 nvm
->ops
.release(hw
);
3407 e_dbg("NVM read error: %d\n", ret_val
);
3413 * e1000_flash_cycle_init_ich8lan - Initialize flash
3414 * @hw: pointer to the HW structure
3416 * This function does initial flash setup so that a new read/write/erase cycle
3419 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
3421 union ich8_hws_flash_status hsfsts
;
3422 s32 ret_val
= -E1000_ERR_NVM
;
3424 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3426 /* Check if the flash descriptor is valid */
3427 if (!hsfsts
.hsf_status
.fldesvalid
) {
3428 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3429 return -E1000_ERR_NVM
;
3432 /* Clear FCERR and DAEL in hw status by writing 1 */
3433 hsfsts
.hsf_status
.flcerr
= 1;
3434 hsfsts
.hsf_status
.dael
= 1;
3435 if (hw
->mac
.type
>= e1000_pch_spt
)
3436 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
& 0xFFFF);
3438 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
3440 /* Either we should have a hardware SPI cycle in progress
3441 * bit to check against, in order to start a new cycle or
3442 * FDONE bit should be changed in the hardware so that it
3443 * is 1 after hardware reset, which can then be used as an
3444 * indication whether a cycle is in progress or has been
3448 if (!hsfsts
.hsf_status
.flcinprog
) {
3449 /* There is no cycle running at present,
3450 * so we can start a cycle.
3451 * Begin by setting Flash Cycle Done.
3453 hsfsts
.hsf_status
.flcdone
= 1;
3454 if (hw
->mac
.type
>= e1000_pch_spt
)
3455 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
& 0xFFFF);
3457 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
3462 /* Otherwise poll for sometime so the current
3463 * cycle has a chance to end before giving up.
3465 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
3466 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3467 if (!hsfsts
.hsf_status
.flcinprog
) {
3474 /* Successful in waiting for previous cycle to timeout,
3475 * now set the Flash Cycle Done.
3477 hsfsts
.hsf_status
.flcdone
= 1;
3478 if (hw
->mac
.type
>= e1000_pch_spt
)
3479 ew32flash(ICH_FLASH_HSFSTS
,
3480 hsfsts
.regval
& 0xFFFF);
3482 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
3484 e_dbg("Flash controller busy, cannot get access\n");
3492 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3493 * @hw: pointer to the HW structure
3494 * @timeout: maximum time to wait for completion
3496 * This function starts a flash cycle and waits for its completion.
3498 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
3500 union ich8_hws_flash_ctrl hsflctl
;
3501 union ich8_hws_flash_status hsfsts
;
3504 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3505 if (hw
->mac
.type
>= e1000_pch_spt
)
3506 hsflctl
.regval
= er32flash(ICH_FLASH_HSFSTS
) >> 16;
3508 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
3509 hsflctl
.hsf_ctrl
.flcgo
= 1;
3511 if (hw
->mac
.type
>= e1000_pch_spt
)
3512 ew32flash(ICH_FLASH_HSFSTS
, hsflctl
.regval
<< 16);
3514 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
3516 /* wait till FDONE bit is set to 1 */
3518 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3519 if (hsfsts
.hsf_status
.flcdone
)
3522 } while (i
++ < timeout
);
3524 if (hsfsts
.hsf_status
.flcdone
&& !hsfsts
.hsf_status
.flcerr
)
3527 return -E1000_ERR_NVM
;
3531 * e1000_read_flash_dword_ich8lan - Read dword from flash
3532 * @hw: pointer to the HW structure
3533 * @offset: offset to data location
3534 * @data: pointer to the location for storing the data
3536 * Reads the flash dword at offset into data. Offset is converted
3537 * to bytes before read.
3539 static s32
e1000_read_flash_dword_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3542 /* Must convert word offset into bytes. */
3544 return e1000_read_flash_data32_ich8lan(hw
, offset
, data
);
3548 * e1000_read_flash_word_ich8lan - Read word from flash
3549 * @hw: pointer to the HW structure
3550 * @offset: offset to data location
3551 * @data: pointer to the location for storing the data
3553 * Reads the flash word at offset into data. Offset is converted
3554 * to bytes before read.
3556 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3559 /* Must convert offset into bytes. */
3562 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
3566 * e1000_read_flash_byte_ich8lan - Read byte from flash
3567 * @hw: pointer to the HW structure
3568 * @offset: The offset of the byte to read.
3569 * @data: Pointer to a byte to store the value read.
3571 * Reads a single byte from the NVM using the flash access registers.
3573 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3579 /* In SPT, only 32 bits access is supported,
3580 * so this function should not be called.
3582 if (hw
->mac
.type
>= e1000_pch_spt
)
3583 return -E1000_ERR_NVM
;
3585 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
3596 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3597 * @hw: pointer to the HW structure
3598 * @offset: The offset (in bytes) of the byte or word to read.
3599 * @size: Size of data to read, 1=byte 2=word
3600 * @data: Pointer to the word to store the value read.
3602 * Reads a byte or word from the NVM using the flash access registers.
3604 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3607 union ich8_hws_flash_status hsfsts
;
3608 union ich8_hws_flash_ctrl hsflctl
;
3609 u32 flash_linear_addr
;
3611 s32 ret_val
= -E1000_ERR_NVM
;
3614 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
3615 return -E1000_ERR_NVM
;
3617 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
3618 hw
->nvm
.flash_base_addr
);
3623 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
3627 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
3628 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3629 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
3630 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
3631 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
3633 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
3636 e1000_flash_cycle_ich8lan(hw
,
3637 ICH_FLASH_READ_COMMAND_TIMEOUT
);
3639 /* Check if FCERR is set to 1, if set to 1, clear it
3640 * and try the whole sequence a few more times, else
3641 * read in (shift in) the Flash Data0, the order is
3642 * least significant byte first msb to lsb
3645 flash_data
= er32flash(ICH_FLASH_FDATA0
);
3647 *data
= (u8
)(flash_data
& 0x000000FF);
3649 *data
= (u16
)(flash_data
& 0x0000FFFF);
3652 /* If we've gotten here, then things are probably
3653 * completely hosed, but if the error condition is
3654 * detected, it won't hurt to give it another try...
3655 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3657 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3658 if (hsfsts
.hsf_status
.flcerr
) {
3659 /* Repeat for some time before giving up. */
3661 } else if (!hsfsts
.hsf_status
.flcdone
) {
3662 e_dbg("Timeout error - flash cycle did not complete.\n");
3666 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
3672 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3673 * @hw: pointer to the HW structure
3674 * @offset: The offset (in bytes) of the dword to read.
3675 * @data: Pointer to the dword to store the value read.
3677 * Reads a byte or word from the NVM using the flash access registers.
3680 static s32
e1000_read_flash_data32_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3683 union ich8_hws_flash_status hsfsts
;
3684 union ich8_hws_flash_ctrl hsflctl
;
3685 u32 flash_linear_addr
;
3686 s32 ret_val
= -E1000_ERR_NVM
;
3689 if (offset
> ICH_FLASH_LINEAR_ADDR_MASK
|| hw
->mac
.type
< e1000_pch_spt
)
3690 return -E1000_ERR_NVM
;
3691 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
3692 hw
->nvm
.flash_base_addr
);
3697 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
3700 /* In SPT, This register is in Lan memory space, not flash.
3701 * Therefore, only 32 bit access is supported
3703 hsflctl
.regval
= er32flash(ICH_FLASH_HSFSTS
) >> 16;
3705 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3706 hsflctl
.hsf_ctrl
.fldbcount
= sizeof(u32
) - 1;
3707 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
3708 /* In SPT, This register is in Lan memory space, not flash.
3709 * Therefore, only 32 bit access is supported
3711 ew32flash(ICH_FLASH_HSFSTS
, (u32
)hsflctl
.regval
<< 16);
3712 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
3715 e1000_flash_cycle_ich8lan(hw
,
3716 ICH_FLASH_READ_COMMAND_TIMEOUT
);
3718 /* Check if FCERR is set to 1, if set to 1, clear it
3719 * and try the whole sequence a few more times, else
3720 * read in (shift in) the Flash Data0, the order is
3721 * least significant byte first msb to lsb
3724 *data
= er32flash(ICH_FLASH_FDATA0
);
3727 /* If we've gotten here, then things are probably
3728 * completely hosed, but if the error condition is
3729 * detected, it won't hurt to give it another try...
3730 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3732 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3733 if (hsfsts
.hsf_status
.flcerr
) {
3734 /* Repeat for some time before giving up. */
3736 } else if (!hsfsts
.hsf_status
.flcdone
) {
3737 e_dbg("Timeout error - flash cycle did not complete.\n");
3741 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
3747 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3748 * @hw: pointer to the HW structure
3749 * @offset: The offset (in bytes) of the word(s) to write.
3750 * @words: Size of data to write in words
3751 * @data: Pointer to the word(s) to write at offset.
3753 * Writes a byte or word to the NVM using the flash access registers.
3755 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
3758 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3759 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3762 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
3764 e_dbg("nvm parameter(s) out of bounds\n");
3765 return -E1000_ERR_NVM
;
3768 nvm
->ops
.acquire(hw
);
3770 for (i
= 0; i
< words
; i
++) {
3771 dev_spec
->shadow_ram
[offset
+ i
].modified
= true;
3772 dev_spec
->shadow_ram
[offset
+ i
].value
= data
[i
];
3775 nvm
->ops
.release(hw
);
3781 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3782 * @hw: pointer to the HW structure
3784 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3785 * which writes the checksum to the shadow ram. The changes in the shadow
3786 * ram are then committed to the EEPROM by processing each bank at a time
3787 * checking for the modified bit and writing only the pending changes.
3788 * After a successful commit, the shadow ram is cleared and is ready for
3791 static s32
e1000_update_nvm_checksum_spt(struct e1000_hw
*hw
)
3793 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3794 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3795 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
3799 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
3803 if (nvm
->type
!= e1000_nvm_flash_sw
)
3806 nvm
->ops
.acquire(hw
);
3808 /* We're writing to the opposite bank so if we're on bank 1,
3809 * write to bank 0 etc. We also need to erase the segment that
3810 * is going to be written
3812 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
3814 e_dbg("Could not detect valid bank, assuming bank 0\n");
3819 new_bank_offset
= nvm
->flash_bank_size
;
3820 old_bank_offset
= 0;
3821 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
3825 old_bank_offset
= nvm
->flash_bank_size
;
3826 new_bank_offset
= 0;
3827 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
3831 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
+= 2) {
3832 /* Determine whether to write the value stored
3833 * in the other NVM bank or a modified value stored
3836 ret_val
= e1000_read_flash_dword_ich8lan(hw
,
3837 i
+ old_bank_offset
,
3840 if (dev_spec
->shadow_ram
[i
].modified
) {
3841 dword
&= 0xffff0000;
3842 dword
|= (dev_spec
->shadow_ram
[i
].value
& 0xffff);
3844 if (dev_spec
->shadow_ram
[i
+ 1].modified
) {
3845 dword
&= 0x0000ffff;
3846 dword
|= ((dev_spec
->shadow_ram
[i
+ 1].value
& 0xffff)
3852 /* If the word is 0x13, then make sure the signature bits
3853 * (15:14) are 11b until the commit has completed.
3854 * This will allow us to write 10b which indicates the
3855 * signature is valid. We want to do this after the write
3856 * has completed so that we don't mark the segment valid
3857 * while the write is still in progress
3859 if (i
== E1000_ICH_NVM_SIG_WORD
- 1)
3860 dword
|= E1000_ICH_NVM_SIG_MASK
<< 16;
3862 /* Convert offset to bytes. */
3863 act_offset
= (i
+ new_bank_offset
) << 1;
3865 usleep_range(100, 200);
3867 /* Write the data to the new bank. Offset in words */
3868 act_offset
= i
+ new_bank_offset
;
3869 ret_val
= e1000_retry_write_flash_dword_ich8lan(hw
, act_offset
,
3875 /* Don't bother writing the segment valid bits if sector
3876 * programming failed.
3879 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3880 e_dbg("Flash commit failed.\n");
3884 /* Finally validate the new segment by setting bit 15:14
3885 * to 10b in word 0x13 , this can be done without an
3886 * erase as well since these bits are 11 to start with
3887 * and we need to change bit 14 to 0b
3889 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
3891 /*offset in words but we read dword */
3893 ret_val
= e1000_read_flash_dword_ich8lan(hw
, act_offset
, &dword
);
3898 dword
&= 0xBFFFFFFF;
3899 ret_val
= e1000_retry_write_flash_dword_ich8lan(hw
, act_offset
, dword
);
3904 /* And invalidate the previously valid segment by setting
3905 * its signature word (0x13) high_byte to 0b. This can be
3906 * done without an erase because flash erase sets all bits
3907 * to 1's. We can write 1's to 0's without an erase
3909 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
3911 /* offset in words but we read dword */
3912 act_offset
= old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
- 1;
3913 ret_val
= e1000_read_flash_dword_ich8lan(hw
, act_offset
, &dword
);
3918 dword
&= 0x00FFFFFF;
3919 ret_val
= e1000_retry_write_flash_dword_ich8lan(hw
, act_offset
, dword
);
3924 /* Great! Everything worked, we can now clear the cached entries. */
3925 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
3926 dev_spec
->shadow_ram
[i
].modified
= false;
3927 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
3931 nvm
->ops
.release(hw
);
3933 /* Reload the EEPROM, or else modifications will not appear
3934 * until after the next adapter reset.
3937 nvm
->ops
.reload(hw
);
3938 usleep_range(10000, 11000);
3943 e_dbg("NVM update error: %d\n", ret_val
);
3949 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3950 * @hw: pointer to the HW structure
3952 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3953 * which writes the checksum to the shadow ram. The changes in the shadow
3954 * ram are then committed to the EEPROM by processing each bank at a time
3955 * checking for the modified bit and writing only the pending changes.
3956 * After a successful commit, the shadow ram is cleared and is ready for
3959 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
3961 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3962 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3963 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
3967 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
3971 if (nvm
->type
!= e1000_nvm_flash_sw
)
3974 nvm
->ops
.acquire(hw
);
3976 /* We're writing to the opposite bank so if we're on bank 1,
3977 * write to bank 0 etc. We also need to erase the segment that
3978 * is going to be written
3980 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
3982 e_dbg("Could not detect valid bank, assuming bank 0\n");
3987 new_bank_offset
= nvm
->flash_bank_size
;
3988 old_bank_offset
= 0;
3989 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
3993 old_bank_offset
= nvm
->flash_bank_size
;
3994 new_bank_offset
= 0;
3995 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
3999 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
4000 if (dev_spec
->shadow_ram
[i
].modified
) {
4001 data
= dev_spec
->shadow_ram
[i
].value
;
4003 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
4010 /* If the word is 0x13, then make sure the signature bits
4011 * (15:14) are 11b until the commit has completed.
4012 * This will allow us to write 10b which indicates the
4013 * signature is valid. We want to do this after the write
4014 * has completed so that we don't mark the segment valid
4015 * while the write is still in progress
4017 if (i
== E1000_ICH_NVM_SIG_WORD
)
4018 data
|= E1000_ICH_NVM_SIG_MASK
;
4020 /* Convert offset to bytes. */
4021 act_offset
= (i
+ new_bank_offset
) << 1;
4023 usleep_range(100, 200);
4024 /* Write the bytes to the new bank. */
4025 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
4031 usleep_range(100, 200);
4032 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
4039 /* Don't bother writing the segment valid bits if sector
4040 * programming failed.
4043 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4044 e_dbg("Flash commit failed.\n");
4048 /* Finally validate the new segment by setting bit 15:14
4049 * to 10b in word 0x13 , this can be done without an
4050 * erase as well since these bits are 11 to start with
4051 * and we need to change bit 14 to 0b
4053 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
4054 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
4059 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
4065 /* And invalidate the previously valid segment by setting
4066 * its signature word (0x13) high_byte to 0b. This can be
4067 * done without an erase because flash erase sets all bits
4068 * to 1's. We can write 1's to 0's without an erase
4070 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
4071 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
4075 /* Great! Everything worked, we can now clear the cached entries. */
4076 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
4077 dev_spec
->shadow_ram
[i
].modified
= false;
4078 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
4082 nvm
->ops
.release(hw
);
4084 /* Reload the EEPROM, or else modifications will not appear
4085 * until after the next adapter reset.
4088 nvm
->ops
.reload(hw
);
4089 usleep_range(10000, 11000);
4094 e_dbg("NVM update error: %d\n", ret_val
);
4100 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4101 * @hw: pointer to the HW structure
4103 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4104 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4105 * calculated, in which case we need to calculate the checksum and set bit 6.
4107 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
4112 u16 valid_csum_mask
;
4114 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4115 * the checksum needs to be fixed. This bit is an indication that
4116 * the NVM was prepared by OEM software and did not calculate
4117 * the checksum...a likely scenario.
4119 switch (hw
->mac
.type
) {
4127 valid_csum_mask
= NVM_COMPAT_VALID_CSUM
;
4130 word
= NVM_FUTURE_INIT_WORD1
;
4131 valid_csum_mask
= NVM_FUTURE_INIT_WORD1_VALID_CSUM
;
4135 ret_val
= e1000_read_nvm(hw
, word
, 1, &data
);
4139 if (!(data
& valid_csum_mask
)) {
4140 e_dbg("NVM Checksum Invalid\n");
4142 if (hw
->mac
.type
< e1000_pch_cnp
) {
4143 data
|= valid_csum_mask
;
4144 ret_val
= e1000_write_nvm(hw
, word
, 1, &data
);
4147 ret_val
= e1000e_update_nvm_checksum(hw
);
4153 return e1000e_validate_nvm_checksum_generic(hw
);
4157 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4158 * @hw: pointer to the HW structure
4160 * To prevent malicious write/erase of the NVM, set it to be read-only
4161 * so that the hardware ignores all write/erase cycles of the NVM via
4162 * the flash control registers. The shadow-ram copy of the NVM will
4163 * still be updated, however any updates to this copy will not stick
4164 * across driver reloads.
4166 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
4168 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
4169 union ich8_flash_protected_range pr0
;
4170 union ich8_hws_flash_status hsfsts
;
4173 nvm
->ops
.acquire(hw
);
4175 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
4177 /* Write-protect GbE Sector of NVM */
4178 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
4179 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
4180 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
4181 pr0
.range
.wpe
= true;
4182 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
4184 /* Lock down a subset of GbE Flash Control Registers, e.g.
4185 * PR0 to prevent the write-protection from being lifted.
4186 * Once FLOCKDN is set, the registers protected by it cannot
4187 * be written until FLOCKDN is cleared by a hardware reset.
4189 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4190 hsfsts
.hsf_status
.flockdn
= true;
4191 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
4193 nvm
->ops
.release(hw
);
4197 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4198 * @hw: pointer to the HW structure
4199 * @offset: The offset (in bytes) of the byte/word to read.
4200 * @size: Size of data to read, 1=byte 2=word
4201 * @data: The byte(s) to write to the NVM.
4203 * Writes one/two bytes to the NVM using the flash access registers.
4205 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
4208 union ich8_hws_flash_status hsfsts
;
4209 union ich8_hws_flash_ctrl hsflctl
;
4210 u32 flash_linear_addr
;
4215 if (hw
->mac
.type
>= e1000_pch_spt
) {
4216 if (size
!= 4 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
4217 return -E1000_ERR_NVM
;
4219 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
4220 return -E1000_ERR_NVM
;
4223 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
4224 hw
->nvm
.flash_base_addr
);
4229 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
4232 /* In SPT, This register is in Lan memory space, not
4233 * flash. Therefore, only 32 bit access is supported
4235 if (hw
->mac
.type
>= e1000_pch_spt
)
4236 hsflctl
.regval
= er32flash(ICH_FLASH_HSFSTS
) >> 16;
4238 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
4240 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4241 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
4242 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
4243 /* In SPT, This register is in Lan memory space,
4244 * not flash. Therefore, only 32 bit access is
4247 if (hw
->mac
.type
>= e1000_pch_spt
)
4248 ew32flash(ICH_FLASH_HSFSTS
, hsflctl
.regval
<< 16);
4250 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
4252 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
4255 flash_data
= (u32
)data
& 0x00FF;
4257 flash_data
= (u32
)data
;
4259 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
4261 /* check if FCERR is set to 1 , if set to 1, clear it
4262 * and try the whole sequence a few more times else done
4265 e1000_flash_cycle_ich8lan(hw
,
4266 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
4270 /* If we're here, then things are most likely
4271 * completely hosed, but if the error condition
4272 * is detected, it won't hurt to give it another
4273 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4275 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4276 if (hsfsts
.hsf_status
.flcerr
)
4277 /* Repeat for some time before giving up. */
4279 if (!hsfsts
.hsf_status
.flcdone
) {
4280 e_dbg("Timeout error - flash cycle did not complete.\n");
4283 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
4289 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4290 * @hw: pointer to the HW structure
4291 * @offset: The offset (in bytes) of the dwords to read.
4292 * @data: The 4 bytes to write to the NVM.
4294 * Writes one/two/four bytes to the NVM using the flash access registers.
4296 static s32
e1000_write_flash_data32_ich8lan(struct e1000_hw
*hw
, u32 offset
,
4299 union ich8_hws_flash_status hsfsts
;
4300 union ich8_hws_flash_ctrl hsflctl
;
4301 u32 flash_linear_addr
;
4305 if (hw
->mac
.type
>= e1000_pch_spt
) {
4306 if (offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
4307 return -E1000_ERR_NVM
;
4309 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
4310 hw
->nvm
.flash_base_addr
);
4314 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
4318 /* In SPT, This register is in Lan memory space, not
4319 * flash. Therefore, only 32 bit access is supported
4321 if (hw
->mac
.type
>= e1000_pch_spt
)
4322 hsflctl
.regval
= er32flash(ICH_FLASH_HSFSTS
)
4325 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
4327 hsflctl
.hsf_ctrl
.fldbcount
= sizeof(u32
) - 1;
4328 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
4330 /* In SPT, This register is in Lan memory space,
4331 * not flash. Therefore, only 32 bit access is
4334 if (hw
->mac
.type
>= e1000_pch_spt
)
4335 ew32flash(ICH_FLASH_HSFSTS
, hsflctl
.regval
<< 16);
4337 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
4339 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
4341 ew32flash(ICH_FLASH_FDATA0
, data
);
4343 /* check if FCERR is set to 1 , if set to 1, clear it
4344 * and try the whole sequence a few more times else done
4347 e1000_flash_cycle_ich8lan(hw
,
4348 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
4353 /* If we're here, then things are most likely
4354 * completely hosed, but if the error condition
4355 * is detected, it won't hurt to give it another
4356 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4358 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4360 if (hsfsts
.hsf_status
.flcerr
)
4361 /* Repeat for some time before giving up. */
4363 if (!hsfsts
.hsf_status
.flcdone
) {
4364 e_dbg("Timeout error - flash cycle did not complete.\n");
4367 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
4373 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4374 * @hw: pointer to the HW structure
4375 * @offset: The index of the byte to read.
4376 * @data: The byte to write to the NVM.
4378 * Writes a single byte to the NVM using the flash access registers.
4380 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
4383 u16 word
= (u16
)data
;
4385 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
4389 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4390 * @hw: pointer to the HW structure
4391 * @offset: The offset of the word to write.
4392 * @dword: The dword to write to the NVM.
4394 * Writes a single dword to the NVM using the flash access registers.
4395 * Goes through a retry algorithm before giving up.
4397 static s32
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw
*hw
,
4398 u32 offset
, u32 dword
)
4401 u16 program_retries
;
4403 /* Must convert word offset into bytes. */
4405 ret_val
= e1000_write_flash_data32_ich8lan(hw
, offset
, dword
);
4409 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
4410 e_dbg("Retrying Byte %8.8X at offset %u\n", dword
, offset
);
4411 usleep_range(100, 200);
4412 ret_val
= e1000_write_flash_data32_ich8lan(hw
, offset
, dword
);
4416 if (program_retries
== 100)
4417 return -E1000_ERR_NVM
;
4423 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4424 * @hw: pointer to the HW structure
4425 * @offset: The offset of the byte to write.
4426 * @byte: The byte to write to the NVM.
4428 * Writes a single byte to the NVM using the flash access registers.
4429 * Goes through a retry algorithm before giving up.
4431 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
4432 u32 offset
, u8 byte
)
4435 u16 program_retries
;
4437 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
4441 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
4442 e_dbg("Retrying Byte %2.2X at offset %u\n", byte
, offset
);
4443 usleep_range(100, 200);
4444 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
4448 if (program_retries
== 100)
4449 return -E1000_ERR_NVM
;
4455 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4456 * @hw: pointer to the HW structure
4457 * @bank: 0 for first bank, 1 for second bank, etc.
4459 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4460 * bank N is 4096 * N + flash_reg_addr.
4462 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
4464 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
4465 union ich8_hws_flash_status hsfsts
;
4466 union ich8_hws_flash_ctrl hsflctl
;
4467 u32 flash_linear_addr
;
4468 /* bank size is in 16bit words - adjust to bytes */
4469 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
4472 s32 j
, iteration
, sector_size
;
4474 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4476 /* Determine HW Sector size: Read BERASE bits of hw flash status
4478 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4479 * consecutive sectors. The start index for the nth Hw sector
4480 * can be calculated as = bank * 4096 + n * 256
4481 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4482 * The start index for the nth Hw sector can be calculated
4484 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4485 * (ich9 only, otherwise error condition)
4486 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4488 switch (hsfsts
.hsf_status
.berasesz
) {
4490 /* Hw sector size 256 */
4491 sector_size
= ICH_FLASH_SEG_SIZE_256
;
4492 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
4495 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
4499 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
4503 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
4507 return -E1000_ERR_NVM
;
4510 /* Start with the base address, then add the sector offset. */
4511 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
4512 flash_linear_addr
+= (bank
) ? flash_bank_size
: 0;
4514 for (j
= 0; j
< iteration
; j
++) {
4516 u32 timeout
= ICH_FLASH_ERASE_COMMAND_TIMEOUT
;
4519 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
4523 /* Write a value 11 (block Erase) in Flash
4524 * Cycle field in hw flash control
4526 if (hw
->mac
.type
>= e1000_pch_spt
)
4528 er32flash(ICH_FLASH_HSFSTS
) >> 16;
4530 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
4532 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
4533 if (hw
->mac
.type
>= e1000_pch_spt
)
4534 ew32flash(ICH_FLASH_HSFSTS
,
4535 hsflctl
.regval
<< 16);
4537 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
4539 /* Write the last 24 bits of an index within the
4540 * block into Flash Linear address field in Flash
4543 flash_linear_addr
+= (j
* sector_size
);
4544 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
4546 ret_val
= e1000_flash_cycle_ich8lan(hw
, timeout
);
4550 /* Check if FCERR is set to 1. If 1,
4551 * clear it and try the whole sequence
4552 * a few more times else Done
4554 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4555 if (hsfsts
.hsf_status
.flcerr
)
4556 /* repeat for some time before giving up */
4558 else if (!hsfsts
.hsf_status
.flcdone
)
4560 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
4567 * e1000_valid_led_default_ich8lan - Set the default LED settings
4568 * @hw: pointer to the HW structure
4569 * @data: Pointer to the LED settings
4571 * Reads the LED default settings from the NVM to data. If the NVM LED
4572 * settings is all 0's or F's, set the LED default to a valid LED default
4575 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
4579 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
4581 e_dbg("NVM Read Error\n");
4585 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
)
4586 *data
= ID_LED_DEFAULT_ICH8LAN
;
4592 * e1000_id_led_init_pchlan - store LED configurations
4593 * @hw: pointer to the HW structure
4595 * PCH does not control LEDs via the LEDCTL register, rather it uses
4596 * the PHY LED configuration register.
4598 * PCH also does not have an "always on" or "always off" mode which
4599 * complicates the ID feature. Instead of using the "on" mode to indicate
4600 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4601 * use "link_up" mode. The LEDs will still ID on request if there is no
4602 * link based on logic in e1000_led_[on|off]_pchlan().
4604 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
4606 struct e1000_mac_info
*mac
= &hw
->mac
;
4608 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
4609 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
4610 u16 data
, i
, temp
, shift
;
4612 /* Get default ID LED modes */
4613 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
4617 mac
->ledctl_default
= er32(LEDCTL
);
4618 mac
->ledctl_mode1
= mac
->ledctl_default
;
4619 mac
->ledctl_mode2
= mac
->ledctl_default
;
4621 for (i
= 0; i
< 4; i
++) {
4622 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
4625 case ID_LED_ON1_DEF2
:
4626 case ID_LED_ON1_ON2
:
4627 case ID_LED_ON1_OFF2
:
4628 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
4629 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
4631 case ID_LED_OFF1_DEF2
:
4632 case ID_LED_OFF1_ON2
:
4633 case ID_LED_OFF1_OFF2
:
4634 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
4635 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
4642 case ID_LED_DEF1_ON2
:
4643 case ID_LED_ON1_ON2
:
4644 case ID_LED_OFF1_ON2
:
4645 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
4646 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
4648 case ID_LED_DEF1_OFF2
:
4649 case ID_LED_ON1_OFF2
:
4650 case ID_LED_OFF1_OFF2
:
4651 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
4652 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
4664 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4665 * @hw: pointer to the HW structure
4667 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4668 * register, so the the bus width is hard coded.
4670 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
4672 struct e1000_bus_info
*bus
= &hw
->bus
;
4675 ret_val
= e1000e_get_bus_info_pcie(hw
);
4677 /* ICH devices are "PCI Express"-ish. They have
4678 * a configuration space, but do not contain
4679 * PCI Express Capability registers, so bus width
4680 * must be hardcoded.
4682 if (bus
->width
== e1000_bus_width_unknown
)
4683 bus
->width
= e1000_bus_width_pcie_x1
;
4689 * e1000_reset_hw_ich8lan - Reset the hardware
4690 * @hw: pointer to the HW structure
4692 * Does a full reset of the hardware which includes a reset of the PHY and
4695 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
4697 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
4702 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4703 * on the last TLP read/write transaction when MAC is reset.
4705 ret_val
= e1000e_disable_pcie_master(hw
);
4707 e_dbg("PCI-E Master disable polling has failed.\n");
4709 e_dbg("Masking off all interrupts\n");
4710 ew32(IMC
, 0xffffffff);
4712 /* Disable the Transmit and Receive units. Then delay to allow
4713 * any pending transactions to complete before we hit the MAC
4714 * with the global reset.
4717 ew32(TCTL
, E1000_TCTL_PSP
);
4720 usleep_range(10000, 11000);
4722 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4723 if (hw
->mac
.type
== e1000_ich8lan
) {
4724 /* Set Tx and Rx buffer allocation to 8k apiece. */
4725 ew32(PBA
, E1000_PBA_8K
);
4726 /* Set Packet Buffer Size to 16k. */
4727 ew32(PBS
, E1000_PBS_16K
);
4730 if (hw
->mac
.type
== e1000_pchlan
) {
4731 /* Save the NVM K1 bit setting */
4732 ret_val
= e1000_read_nvm(hw
, E1000_NVM_K1_CONFIG
, 1, &kum_cfg
);
4736 if (kum_cfg
& E1000_NVM_K1_ENABLE
)
4737 dev_spec
->nvm_k1_enabled
= true;
4739 dev_spec
->nvm_k1_enabled
= false;
4744 if (!hw
->phy
.ops
.check_reset_block(hw
)) {
4745 /* Full-chip reset requires MAC and PHY reset at the same
4746 * time to make sure the interface between MAC and the
4747 * external PHY is reset.
4749 ctrl
|= E1000_CTRL_PHY_RST
;
4751 /* Gate automatic PHY configuration by hardware on
4754 if ((hw
->mac
.type
== e1000_pch2lan
) &&
4755 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
4756 e1000_gate_hw_phy_config_ich8lan(hw
, true);
4758 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
4759 e_dbg("Issuing a global reset to ich8lan\n");
4760 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
4761 /* cannot issue a flush here because it hangs the hardware */
4764 /* Set Phy Config Counter to 50msec */
4765 if (hw
->mac
.type
== e1000_pch2lan
) {
4766 reg
= er32(FEXTNVM3
);
4767 reg
&= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK
;
4768 reg
|= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
;
4769 ew32(FEXTNVM3
, reg
);
4773 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
4775 if (ctrl
& E1000_CTRL_PHY_RST
) {
4776 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
4780 ret_val
= e1000_post_phy_reset_ich8lan(hw
);
4785 /* For PCH, this write will make sure that any noise
4786 * will be detected as a CRC error and be dropped rather than show up
4787 * as a bad packet to the DMA engine.
4789 if (hw
->mac
.type
== e1000_pchlan
)
4790 ew32(CRC_OFFSET
, 0x65656565);
4792 ew32(IMC
, 0xffffffff);
4795 reg
= er32(KABGTXD
);
4796 reg
|= E1000_KABGTXD_BGSQLBIAS
;
4803 * e1000_init_hw_ich8lan - Initialize the hardware
4804 * @hw: pointer to the HW structure
4806 * Prepares the hardware for transmit and receive by doing the following:
4807 * - initialize hardware bits
4808 * - initialize LED identification
4809 * - setup receive address registers
4810 * - setup flow control
4811 * - setup transmit descriptors
4812 * - clear statistics
4814 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
4816 struct e1000_mac_info
*mac
= &hw
->mac
;
4817 u32 ctrl_ext
, txdctl
, snoop
;
4821 e1000_initialize_hw_bits_ich8lan(hw
);
4823 /* Initialize identification LED */
4824 ret_val
= mac
->ops
.id_led_init(hw
);
4825 /* An error is not fatal and we should not stop init due to this */
4827 e_dbg("Error initializing identification LED\n");
4829 /* Setup the receive address. */
4830 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
4832 /* Zero out the Multicast HASH table */
4833 e_dbg("Zeroing the MTA\n");
4834 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
4835 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
4837 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4838 * the ME. Disable wakeup by clearing the host wakeup bit.
4839 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4841 if (hw
->phy
.type
== e1000_phy_82578
) {
4842 e1e_rphy(hw
, BM_PORT_GEN_CFG
, &i
);
4843 i
&= ~BM_WUC_HOST_WU_BIT
;
4844 e1e_wphy(hw
, BM_PORT_GEN_CFG
, i
);
4845 ret_val
= e1000_phy_hw_reset_ich8lan(hw
);
4850 /* Setup link and flow control */
4851 ret_val
= mac
->ops
.setup_link(hw
);
4853 /* Set the transmit descriptor write-back policy for both queues */
4854 txdctl
= er32(TXDCTL(0));
4855 txdctl
= ((txdctl
& ~E1000_TXDCTL_WTHRESH
) |
4856 E1000_TXDCTL_FULL_TX_DESC_WB
);
4857 txdctl
= ((txdctl
& ~E1000_TXDCTL_PTHRESH
) |
4858 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
);
4859 ew32(TXDCTL(0), txdctl
);
4860 txdctl
= er32(TXDCTL(1));
4861 txdctl
= ((txdctl
& ~E1000_TXDCTL_WTHRESH
) |
4862 E1000_TXDCTL_FULL_TX_DESC_WB
);
4863 txdctl
= ((txdctl
& ~E1000_TXDCTL_PTHRESH
) |
4864 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
);
4865 ew32(TXDCTL(1), txdctl
);
4867 /* ICH8 has opposite polarity of no_snoop bits.
4868 * By default, we should use snoop behavior.
4870 if (mac
->type
== e1000_ich8lan
)
4871 snoop
= PCIE_ICH8_SNOOP_ALL
;
4873 snoop
= (u32
)~(PCIE_NO_SNOOP_ALL
);
4874 e1000e_set_pcie_no_snoop(hw
, snoop
);
4876 ctrl_ext
= er32(CTRL_EXT
);
4877 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
4878 ew32(CTRL_EXT
, ctrl_ext
);
4880 /* Clear all of the statistics registers (clear on read). It is
4881 * important that we do this after we have tried to establish link
4882 * because the symbol error count will increment wildly if there
4885 e1000_clear_hw_cntrs_ich8lan(hw
);
4891 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4892 * @hw: pointer to the HW structure
4894 * Sets/Clears required hardware bits necessary for correctly setting up the
4895 * hardware for transmit and receive.
4897 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
4901 /* Extended Device Control */
4902 reg
= er32(CTRL_EXT
);
4904 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4905 if (hw
->mac
.type
>= e1000_pchlan
)
4906 reg
|= E1000_CTRL_EXT_PHYPDEN
;
4907 ew32(CTRL_EXT
, reg
);
4909 /* Transmit Descriptor Control 0 */
4910 reg
= er32(TXDCTL(0));
4912 ew32(TXDCTL(0), reg
);
4914 /* Transmit Descriptor Control 1 */
4915 reg
= er32(TXDCTL(1));
4917 ew32(TXDCTL(1), reg
);
4919 /* Transmit Arbitration Control 0 */
4920 reg
= er32(TARC(0));
4921 if (hw
->mac
.type
== e1000_ich8lan
)
4922 reg
|= BIT(28) | BIT(29);
4923 reg
|= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4926 /* Transmit Arbitration Control 1 */
4927 reg
= er32(TARC(1));
4928 if (er32(TCTL
) & E1000_TCTL_MULR
)
4932 reg
|= BIT(24) | BIT(26) | BIT(30);
4936 if (hw
->mac
.type
== e1000_ich8lan
) {
4942 /* work-around descriptor data corruption issue during nfs v2 udp
4943 * traffic, just disable the nfs filtering capability
4946 reg
|= (E1000_RFCTL_NFSW_DIS
| E1000_RFCTL_NFSR_DIS
);
4948 /* Disable IPv6 extension header parsing because some malformed
4949 * IPv6 headers can hang the Rx.
4951 if (hw
->mac
.type
== e1000_ich8lan
)
4952 reg
|= (E1000_RFCTL_IPV6_EX_DIS
| E1000_RFCTL_NEW_IPV6_EXT_DIS
);
4955 /* Enable ECC on Lynxpoint */
4956 if (hw
->mac
.type
>= e1000_pch_lpt
) {
4957 reg
= er32(PBECCSTS
);
4958 reg
|= E1000_PBECCSTS_ECC_ENABLE
;
4959 ew32(PBECCSTS
, reg
);
4962 reg
|= E1000_CTRL_MEHE
;
4968 * e1000_setup_link_ich8lan - Setup flow control and link settings
4969 * @hw: pointer to the HW structure
4971 * Determines which flow control settings to use, then configures flow
4972 * control. Calls the appropriate media-specific link configuration
4973 * function. Assuming the adapter has a valid link partner, a valid link
4974 * should be established. Assumes the hardware has previously been reset
4975 * and the transmitter and receiver are not enabled.
4977 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
4981 if (hw
->phy
.ops
.check_reset_block(hw
))
4984 /* ICH parts do not have a word in the NVM to determine
4985 * the default flow control setting, so we explicitly
4988 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
4989 /* Workaround h/w hang when Tx flow control enabled */
4990 if (hw
->mac
.type
== e1000_pchlan
)
4991 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
4993 hw
->fc
.requested_mode
= e1000_fc_full
;
4996 /* Save off the requested flow control mode for use later. Depending
4997 * on the link partner's capabilities, we may or may not use this mode.
4999 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
5001 e_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.current_mode
);
5003 /* Continue to configure the copper link. */
5004 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
5008 ew32(FCTTV
, hw
->fc
.pause_time
);
5009 if ((hw
->phy
.type
== e1000_phy_82578
) ||
5010 (hw
->phy
.type
== e1000_phy_82579
) ||
5011 (hw
->phy
.type
== e1000_phy_i217
) ||
5012 (hw
->phy
.type
== e1000_phy_82577
)) {
5013 ew32(FCRTV_PCH
, hw
->fc
.refresh_time
);
5015 ret_val
= e1e_wphy(hw
, PHY_REG(BM_PORT_CTRL_PAGE
, 27),
5021 return e1000e_set_fc_watermarks(hw
);
5025 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5026 * @hw: pointer to the HW structure
5028 * Configures the kumeran interface to the PHY to wait the appropriate time
5029 * when polling the PHY, then call the generic setup_copper_link to finish
5030 * configuring the copper link.
5032 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
5039 ctrl
|= E1000_CTRL_SLU
;
5040 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
5043 /* Set the mac to wait the maximum time between each iteration
5044 * and increase the max iterations when polling the phy;
5045 * this fixes erroneous timeouts at 10Mbps.
5047 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_TIMEOUTS
, 0xFFFF);
5050 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
5055 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
5060 switch (hw
->phy
.type
) {
5061 case e1000_phy_igp_3
:
5062 ret_val
= e1000e_copper_link_setup_igp(hw
);
5067 case e1000_phy_82578
:
5068 ret_val
= e1000e_copper_link_setup_m88(hw
);
5072 case e1000_phy_82577
:
5073 case e1000_phy_82579
:
5074 ret_val
= e1000_copper_link_setup_82577(hw
);
5079 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
5083 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
5085 switch (hw
->phy
.mdix
) {
5087 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
5090 reg_data
|= IFE_PMC_FORCE_MDIX
;
5094 reg_data
|= IFE_PMC_AUTO_MDIX
;
5097 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
5105 return e1000e_setup_copper_link(hw
);
5109 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5110 * @hw: pointer to the HW structure
5112 * Calls the PHY specific link setup function and then calls the
5113 * generic setup_copper_link to finish configuring the link for
5114 * Lynxpoint PCH devices
5116 static s32
e1000_setup_copper_link_pch_lpt(struct e1000_hw
*hw
)
5122 ctrl
|= E1000_CTRL_SLU
;
5123 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
5126 ret_val
= e1000_copper_link_setup_82577(hw
);
5130 return e1000e_setup_copper_link(hw
);
5134 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5135 * @hw: pointer to the HW structure
5136 * @speed: pointer to store current link speed
5137 * @duplex: pointer to store the current link duplex
5139 * Calls the generic get_speed_and_duplex to retrieve the current link
5140 * information and then calls the Kumeran lock loss workaround for links at
5143 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
5148 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
5152 if ((hw
->mac
.type
== e1000_ich8lan
) &&
5153 (hw
->phy
.type
== e1000_phy_igp_3
) && (*speed
== SPEED_1000
)) {
5154 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
5161 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5162 * @hw: pointer to the HW structure
5164 * Work-around for 82566 Kumeran PCS lock loss:
5165 * On link status change (i.e. PCI reset, speed change) and link is up and
5167 * 0) if workaround is optionally disabled do nothing
5168 * 1) wait 1ms for Kumeran link to come up
5169 * 2) check Kumeran Diagnostic register PCS lock loss bit
5170 * 3) if not set the link is locked (all is good), otherwise...
5172 * 5) repeat up to 10 times
5173 * Note: this is only called for IGP3 copper when speed is 1gb.
5175 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
5177 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
5183 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
5186 /* Make sure link is up before proceeding. If not just return.
5187 * Attempting this while link is negotiating fouled up link
5190 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
5194 for (i
= 0; i
< 10; i
++) {
5195 /* read once to clear */
5196 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
5199 /* and again to get new status */
5200 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
5204 /* check for PCS lock */
5205 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
5208 /* Issue PHY reset */
5209 e1000_phy_hw_reset(hw
);
5212 /* Disable GigE link negotiation */
5213 phy_ctrl
= er32(PHY_CTRL
);
5214 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
5215 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
5216 ew32(PHY_CTRL
, phy_ctrl
);
5218 /* Call gig speed drop workaround on Gig disable before accessing
5221 e1000e_gig_downshift_workaround_ich8lan(hw
);
5223 /* unable to acquire PCS lock */
5224 return -E1000_ERR_PHY
;
5228 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5229 * @hw: pointer to the HW structure
5230 * @state: boolean value used to set the current Kumeran workaround state
5232 * If ICH8, set the current Kumeran workaround state (enabled - true
5233 * /disabled - false).
5235 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
5238 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
5240 if (hw
->mac
.type
!= e1000_ich8lan
) {
5241 e_dbg("Workaround applies to ICH8 only.\n");
5245 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
5249 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5250 * @hw: pointer to the HW structure
5252 * Workaround for 82566 power-down on D3 entry:
5253 * 1) disable gigabit link
5254 * 2) write VR power-down enable
5256 * Continue if successful, else issue LCD reset and repeat
5258 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
5264 if (hw
->phy
.type
!= e1000_phy_igp_3
)
5267 /* Try the workaround twice (if needed) */
5270 reg
= er32(PHY_CTRL
);
5271 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
5272 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
5273 ew32(PHY_CTRL
, reg
);
5275 /* Call gig speed drop workaround on Gig disable before
5276 * accessing any PHY registers
5278 if (hw
->mac
.type
== e1000_ich8lan
)
5279 e1000e_gig_downshift_workaround_ich8lan(hw
);
5281 /* Write VR power-down enable */
5282 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
5283 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
5284 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
5286 /* Read it back and test */
5287 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
5288 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
5289 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
5292 /* Issue PHY reset and repeat at most one more time */
5294 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
5300 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5301 * @hw: pointer to the HW structure
5303 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5304 * LPLU, Gig disable, MDIC PHY reset):
5305 * 1) Set Kumeran Near-end loopback
5306 * 2) Clear Kumeran Near-end loopback
5307 * Should only be called for ICH8[m] devices with any 1G Phy.
5309 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
5314 if ((hw
->mac
.type
!= e1000_ich8lan
) || (hw
->phy
.type
== e1000_phy_ife
))
5317 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
5321 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
5322 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
5326 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
5327 e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
, reg_data
);
5331 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5332 * @hw: pointer to the HW structure
5334 * During S0 to Sx transition, it is possible the link remains at gig
5335 * instead of negotiating to a lower speed. Before going to Sx, set
5336 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5337 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5338 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5339 * needs to be written.
5340 * Parts that support (and are linked to a partner which support) EEE in
5341 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5342 * than 10Mbps w/o EEE.
5344 void e1000_suspend_workarounds_ich8lan(struct e1000_hw
*hw
)
5346 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
5350 phy_ctrl
= er32(PHY_CTRL
);
5351 phy_ctrl
|= E1000_PHY_CTRL_GBE_DISABLE
;
5353 if (hw
->phy
.type
== e1000_phy_i217
) {
5354 u16 phy_reg
, device_id
= hw
->adapter
->pdev
->device
;
5356 if ((device_id
== E1000_DEV_ID_PCH_LPTLP_I218_LM
) ||
5357 (device_id
== E1000_DEV_ID_PCH_LPTLP_I218_V
) ||
5358 (device_id
== E1000_DEV_ID_PCH_I218_LM3
) ||
5359 (device_id
== E1000_DEV_ID_PCH_I218_V3
) ||
5360 (hw
->mac
.type
>= e1000_pch_spt
)) {
5361 u32 fextnvm6
= er32(FEXTNVM6
);
5363 ew32(FEXTNVM6
, fextnvm6
& ~E1000_FEXTNVM6_REQ_PLL_CLK
);
5366 ret_val
= hw
->phy
.ops
.acquire(hw
);
5370 if (!dev_spec
->eee_disable
) {
5374 e1000_read_emi_reg_locked(hw
,
5375 I217_EEE_ADVERTISEMENT
,
5380 /* Disable LPLU if both link partners support 100BaseT
5381 * EEE and 100Full is advertised on both ends of the
5382 * link, and enable Auto Enable LPI since there will
5383 * be no driver to enable LPI while in Sx.
5385 if ((eee_advert
& I82579_EEE_100_SUPPORTED
) &&
5386 (dev_spec
->eee_lp_ability
&
5387 I82579_EEE_100_SUPPORTED
) &&
5388 (hw
->phy
.autoneg_advertised
& ADVERTISE_100_FULL
)) {
5389 phy_ctrl
&= ~(E1000_PHY_CTRL_D0A_LPLU
|
5390 E1000_PHY_CTRL_NOND0A_LPLU
);
5392 /* Set Auto Enable LPI after link up */
5394 I217_LPI_GPIO_CTRL
, &phy_reg
);
5395 phy_reg
|= I217_LPI_GPIO_CTRL_AUTO_EN_LPI
;
5397 I217_LPI_GPIO_CTRL
, phy_reg
);
5401 /* For i217 Intel Rapid Start Technology support,
5402 * when the system is going into Sx and no manageability engine
5403 * is present, the driver must configure proxy to reset only on
5404 * power good. LPI (Low Power Idle) state must also reset only
5405 * on power good, as well as the MTA (Multicast table array).
5406 * The SMBus release must also be disabled on LCD reset.
5408 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
5409 /* Enable proxy to reset only on power good. */
5410 e1e_rphy_locked(hw
, I217_PROXY_CTRL
, &phy_reg
);
5411 phy_reg
|= I217_PROXY_CTRL_AUTO_DISABLE
;
5412 e1e_wphy_locked(hw
, I217_PROXY_CTRL
, phy_reg
);
5414 /* Set bit enable LPI (EEE) to reset only on
5417 e1e_rphy_locked(hw
, I217_SxCTRL
, &phy_reg
);
5418 phy_reg
|= I217_SxCTRL_ENABLE_LPI_RESET
;
5419 e1e_wphy_locked(hw
, I217_SxCTRL
, phy_reg
);
5421 /* Disable the SMB release on LCD reset. */
5422 e1e_rphy_locked(hw
, I217_MEMPWR
, &phy_reg
);
5423 phy_reg
&= ~I217_MEMPWR_DISABLE_SMB_RELEASE
;
5424 e1e_wphy_locked(hw
, I217_MEMPWR
, phy_reg
);
5427 /* Enable MTA to reset for Intel Rapid Start Technology
5430 e1e_rphy_locked(hw
, I217_CGFREG
, &phy_reg
);
5431 phy_reg
|= I217_CGFREG_ENABLE_MTA_RESET
;
5432 e1e_wphy_locked(hw
, I217_CGFREG
, phy_reg
);
5435 hw
->phy
.ops
.release(hw
);
5438 ew32(PHY_CTRL
, phy_ctrl
);
5440 if (hw
->mac
.type
== e1000_ich8lan
)
5441 e1000e_gig_downshift_workaround_ich8lan(hw
);
5443 if (hw
->mac
.type
>= e1000_pchlan
) {
5444 e1000_oem_bits_config_ich8lan(hw
, false);
5446 /* Reset PHY to activate OEM bits on 82577/8 */
5447 if (hw
->mac
.type
== e1000_pchlan
)
5448 e1000e_phy_hw_reset_generic(hw
);
5450 ret_val
= hw
->phy
.ops
.acquire(hw
);
5453 e1000_write_smbus_addr(hw
);
5454 hw
->phy
.ops
.release(hw
);
5459 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5460 * @hw: pointer to the HW structure
5462 * During Sx to S0 transitions on non-managed devices or managed devices
5463 * on which PHY resets are not blocked, if the PHY registers cannot be
5464 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5466 * On i217, setup Intel Rapid Start Technology.
5468 void e1000_resume_workarounds_pchlan(struct e1000_hw
*hw
)
5472 if (hw
->mac
.type
< e1000_pch2lan
)
5475 ret_val
= e1000_init_phy_workarounds_pchlan(hw
);
5477 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val
);
5481 /* For i217 Intel Rapid Start Technology support when the system
5482 * is transitioning from Sx and no manageability engine is present
5483 * configure SMBus to restore on reset, disable proxy, and enable
5484 * the reset on MTA (Multicast table array).
5486 if (hw
->phy
.type
== e1000_phy_i217
) {
5489 ret_val
= hw
->phy
.ops
.acquire(hw
);
5491 e_dbg("Failed to setup iRST\n");
5495 /* Clear Auto Enable LPI after link up */
5496 e1e_rphy_locked(hw
, I217_LPI_GPIO_CTRL
, &phy_reg
);
5497 phy_reg
&= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI
;
5498 e1e_wphy_locked(hw
, I217_LPI_GPIO_CTRL
, phy_reg
);
5500 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
5501 /* Restore clear on SMB if no manageability engine
5504 ret_val
= e1e_rphy_locked(hw
, I217_MEMPWR
, &phy_reg
);
5507 phy_reg
|= I217_MEMPWR_DISABLE_SMB_RELEASE
;
5508 e1e_wphy_locked(hw
, I217_MEMPWR
, phy_reg
);
5511 e1e_wphy_locked(hw
, I217_PROXY_CTRL
, 0);
5513 /* Enable reset on MTA */
5514 ret_val
= e1e_rphy_locked(hw
, I217_CGFREG
, &phy_reg
);
5517 phy_reg
&= ~I217_CGFREG_ENABLE_MTA_RESET
;
5518 e1e_wphy_locked(hw
, I217_CGFREG
, phy_reg
);
5521 e_dbg("Error %d in resume workarounds\n", ret_val
);
5522 hw
->phy
.ops
.release(hw
);
5527 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5528 * @hw: pointer to the HW structure
5530 * Return the LED back to the default configuration.
5532 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
5534 if (hw
->phy
.type
== e1000_phy_ife
)
5535 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
5537 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
5542 * e1000_led_on_ich8lan - Turn LEDs on
5543 * @hw: pointer to the HW structure
5547 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
5549 if (hw
->phy
.type
== e1000_phy_ife
)
5550 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
5551 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
5553 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
5558 * e1000_led_off_ich8lan - Turn LEDs off
5559 * @hw: pointer to the HW structure
5561 * Turn off the LEDs.
5563 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
5565 if (hw
->phy
.type
== e1000_phy_ife
)
5566 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
5567 (IFE_PSCL_PROBE_MODE
|
5568 IFE_PSCL_PROBE_LEDS_OFF
));
5570 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
5575 * e1000_setup_led_pchlan - Configures SW controllable LED
5576 * @hw: pointer to the HW structure
5578 * This prepares the SW controllable LED for use.
5580 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
5582 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_mode1
);
5586 * e1000_cleanup_led_pchlan - Restore the default LED operation
5587 * @hw: pointer to the HW structure
5589 * Return the LED back to the default configuration.
5591 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
5593 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_default
);
5597 * e1000_led_on_pchlan - Turn LEDs on
5598 * @hw: pointer to the HW structure
5602 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
5604 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
5607 /* If no link, then turn LED on by setting the invert bit
5608 * for each LED that's mode is "link_up" in ledctl_mode2.
5610 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
5611 for (i
= 0; i
< 3; i
++) {
5612 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
5613 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
5614 E1000_LEDCTL_MODE_LINK_UP
)
5616 if (led
& E1000_PHY_LED0_IVRT
)
5617 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
5619 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
5623 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
5627 * e1000_led_off_pchlan - Turn LEDs off
5628 * @hw: pointer to the HW structure
5630 * Turn off the LEDs.
5632 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
5634 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
5637 /* If no link, then turn LED off by clearing the invert bit
5638 * for each LED that's mode is "link_up" in ledctl_mode1.
5640 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
5641 for (i
= 0; i
< 3; i
++) {
5642 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
5643 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
5644 E1000_LEDCTL_MODE_LINK_UP
)
5646 if (led
& E1000_PHY_LED0_IVRT
)
5647 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
5649 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
5653 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
5657 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5658 * @hw: pointer to the HW structure
5660 * Read appropriate register for the config done bit for completion status
5661 * and configure the PHY through s/w for EEPROM-less parts.
5663 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5664 * config done bit, so only an error is logged and continues. If we were
5665 * to return with error, EEPROM-less silicon would not be able to be reset
5668 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
5674 e1000e_get_cfg_done_generic(hw
);
5676 /* Wait for indication from h/w that it has completed basic config */
5677 if (hw
->mac
.type
>= e1000_ich10lan
) {
5678 e1000_lan_init_done_ich8lan(hw
);
5680 ret_val
= e1000e_get_auto_rd_done(hw
);
5682 /* When auto config read does not complete, do not
5683 * return with an error. This can happen in situations
5684 * where there is no eeprom and prevents getting link.
5686 e_dbg("Auto Read Done did not complete\n");
5691 /* Clear PHY Reset Asserted bit */
5692 status
= er32(STATUS
);
5693 if (status
& E1000_STATUS_PHYRA
)
5694 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
5696 e_dbg("PHY Reset Asserted not set - needs delay\n");
5698 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5699 if (hw
->mac
.type
<= e1000_ich9lan
) {
5700 if (!(er32(EECD
) & E1000_EECD_PRES
) &&
5701 (hw
->phy
.type
== e1000_phy_igp_3
)) {
5702 e1000e_phy_init_script_igp3(hw
);
5705 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
5706 /* Maybe we should do a basic PHY config */
5707 e_dbg("EEPROM not present\n");
5708 ret_val
= -E1000_ERR_CONFIG
;
5716 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5717 * @hw: pointer to the HW structure
5719 * In the case of a PHY power down to save power, or to turn off link during a
5720 * driver unload, or wake on lan is not enabled, remove the link.
5722 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
)
5724 /* If the management interface is not enabled, then power down */
5725 if (!(hw
->mac
.ops
.check_mng_mode(hw
) ||
5726 hw
->phy
.ops
.check_reset_block(hw
)))
5727 e1000_power_down_phy_copper(hw
);
5731 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5732 * @hw: pointer to the HW structure
5734 * Clears hardware counters specific to the silicon family and calls
5735 * clear_hw_cntrs_generic to clear all general purpose counters.
5737 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
5742 e1000e_clear_hw_cntrs_base(hw
);
5758 /* Clear PHY statistics registers */
5759 if ((hw
->phy
.type
== e1000_phy_82578
) ||
5760 (hw
->phy
.type
== e1000_phy_82579
) ||
5761 (hw
->phy
.type
== e1000_phy_i217
) ||
5762 (hw
->phy
.type
== e1000_phy_82577
)) {
5763 ret_val
= hw
->phy
.ops
.acquire(hw
);
5766 ret_val
= hw
->phy
.ops
.set_page(hw
,
5767 HV_STATS_PAGE
<< IGP_PAGE_SHIFT
);
5770 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_UPPER
, &phy_data
);
5771 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_LOWER
, &phy_data
);
5772 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_UPPER
, &phy_data
);
5773 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_LOWER
, &phy_data
);
5774 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_UPPER
, &phy_data
);
5775 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_LOWER
, &phy_data
);
5776 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_UPPER
, &phy_data
);
5777 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_LOWER
, &phy_data
);
5778 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_UPPER
, &phy_data
);
5779 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_LOWER
, &phy_data
);
5780 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_UPPER
, &phy_data
);
5781 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_LOWER
, &phy_data
);
5782 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_UPPER
, &phy_data
);
5783 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_LOWER
, &phy_data
);
5785 hw
->phy
.ops
.release(hw
);
5789 static const struct e1000_mac_operations ich8_mac_ops
= {
5790 /* check_mng_mode dependent on mac type */
5791 .check_for_link
= e1000_check_for_copper_link_ich8lan
,
5792 /* cleanup_led dependent on mac type */
5793 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
5794 .get_bus_info
= e1000_get_bus_info_ich8lan
,
5795 .set_lan_id
= e1000_set_lan_id_single_port
,
5796 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
5797 /* led_on dependent on mac type */
5798 /* led_off dependent on mac type */
5799 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
5800 .reset_hw
= e1000_reset_hw_ich8lan
,
5801 .init_hw
= e1000_init_hw_ich8lan
,
5802 .setup_link
= e1000_setup_link_ich8lan
,
5803 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
5804 /* id_led_init dependent on mac type */
5805 .config_collision_dist
= e1000e_config_collision_dist_generic
,
5806 .rar_set
= e1000e_rar_set_generic
,
5807 .rar_get_count
= e1000e_rar_get_count_generic
,
5810 static const struct e1000_phy_operations ich8_phy_ops
= {
5811 .acquire
= e1000_acquire_swflag_ich8lan
,
5812 .check_reset_block
= e1000_check_reset_block_ich8lan
,
5814 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
5815 .get_cable_length
= e1000e_get_cable_length_igp_2
,
5816 .read_reg
= e1000e_read_phy_reg_igp
,
5817 .release
= e1000_release_swflag_ich8lan
,
5818 .reset
= e1000_phy_hw_reset_ich8lan
,
5819 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
5820 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
5821 .write_reg
= e1000e_write_phy_reg_igp
,
5824 static const struct e1000_nvm_operations ich8_nvm_ops
= {
5825 .acquire
= e1000_acquire_nvm_ich8lan
,
5826 .read
= e1000_read_nvm_ich8lan
,
5827 .release
= e1000_release_nvm_ich8lan
,
5828 .reload
= e1000e_reload_nvm_generic
,
5829 .update
= e1000_update_nvm_checksum_ich8lan
,
5830 .valid_led_default
= e1000_valid_led_default_ich8lan
,
5831 .validate
= e1000_validate_nvm_checksum_ich8lan
,
5832 .write
= e1000_write_nvm_ich8lan
,
5835 static const struct e1000_nvm_operations spt_nvm_ops
= {
5836 .acquire
= e1000_acquire_nvm_ich8lan
,
5837 .release
= e1000_release_nvm_ich8lan
,
5838 .read
= e1000_read_nvm_spt
,
5839 .update
= e1000_update_nvm_checksum_spt
,
5840 .reload
= e1000e_reload_nvm_generic
,
5841 .valid_led_default
= e1000_valid_led_default_ich8lan
,
5842 .validate
= e1000_validate_nvm_checksum_ich8lan
,
5843 .write
= e1000_write_nvm_ich8lan
,
5846 const struct e1000_info e1000_ich8_info
= {
5847 .mac
= e1000_ich8lan
,
5848 .flags
= FLAG_HAS_WOL
5850 | FLAG_HAS_CTRLEXT_ON_LOAD
5855 .max_hw_frame_size
= VLAN_ETH_FRAME_LEN
+ ETH_FCS_LEN
,
5856 .get_variants
= e1000_get_variants_ich8lan
,
5857 .mac_ops
= &ich8_mac_ops
,
5858 .phy_ops
= &ich8_phy_ops
,
5859 .nvm_ops
= &ich8_nvm_ops
,
5862 const struct e1000_info e1000_ich9_info
= {
5863 .mac
= e1000_ich9lan
,
5864 .flags
= FLAG_HAS_JUMBO_FRAMES
5867 | FLAG_HAS_CTRLEXT_ON_LOAD
5872 .max_hw_frame_size
= DEFAULT_JUMBO
,
5873 .get_variants
= e1000_get_variants_ich8lan
,
5874 .mac_ops
= &ich8_mac_ops
,
5875 .phy_ops
= &ich8_phy_ops
,
5876 .nvm_ops
= &ich8_nvm_ops
,
5879 const struct e1000_info e1000_ich10_info
= {
5880 .mac
= e1000_ich10lan
,
5881 .flags
= FLAG_HAS_JUMBO_FRAMES
5884 | FLAG_HAS_CTRLEXT_ON_LOAD
5889 .max_hw_frame_size
= DEFAULT_JUMBO
,
5890 .get_variants
= e1000_get_variants_ich8lan
,
5891 .mac_ops
= &ich8_mac_ops
,
5892 .phy_ops
= &ich8_phy_ops
,
5893 .nvm_ops
= &ich8_nvm_ops
,
5896 const struct e1000_info e1000_pch_info
= {
5897 .mac
= e1000_pchlan
,
5898 .flags
= FLAG_IS_ICH
5900 | FLAG_HAS_CTRLEXT_ON_LOAD
5903 | FLAG_HAS_JUMBO_FRAMES
5904 | FLAG_DISABLE_FC_PAUSE_TIME
/* errata */
5906 .flags2
= FLAG2_HAS_PHY_STATS
,
5908 .max_hw_frame_size
= 4096,
5909 .get_variants
= e1000_get_variants_ich8lan
,
5910 .mac_ops
= &ich8_mac_ops
,
5911 .phy_ops
= &ich8_phy_ops
,
5912 .nvm_ops
= &ich8_nvm_ops
,
5915 const struct e1000_info e1000_pch2_info
= {
5916 .mac
= e1000_pch2lan
,
5917 .flags
= FLAG_IS_ICH
5919 | FLAG_HAS_HW_TIMESTAMP
5920 | FLAG_HAS_CTRLEXT_ON_LOAD
5923 | FLAG_HAS_JUMBO_FRAMES
5925 .flags2
= FLAG2_HAS_PHY_STATS
5927 | FLAG2_CHECK_SYSTIM_OVERFLOW
,
5929 .max_hw_frame_size
= 9022,
5930 .get_variants
= e1000_get_variants_ich8lan
,
5931 .mac_ops
= &ich8_mac_ops
,
5932 .phy_ops
= &ich8_phy_ops
,
5933 .nvm_ops
= &ich8_nvm_ops
,
5936 const struct e1000_info e1000_pch_lpt_info
= {
5937 .mac
= e1000_pch_lpt
,
5938 .flags
= FLAG_IS_ICH
5940 | FLAG_HAS_HW_TIMESTAMP
5941 | FLAG_HAS_CTRLEXT_ON_LOAD
5944 | FLAG_HAS_JUMBO_FRAMES
5946 .flags2
= FLAG2_HAS_PHY_STATS
5948 | FLAG2_CHECK_SYSTIM_OVERFLOW
,
5950 .max_hw_frame_size
= 9022,
5951 .get_variants
= e1000_get_variants_ich8lan
,
5952 .mac_ops
= &ich8_mac_ops
,
5953 .phy_ops
= &ich8_phy_ops
,
5954 .nvm_ops
= &ich8_nvm_ops
,
5957 const struct e1000_info e1000_pch_spt_info
= {
5958 .mac
= e1000_pch_spt
,
5959 .flags
= FLAG_IS_ICH
5961 | FLAG_HAS_HW_TIMESTAMP
5962 | FLAG_HAS_CTRLEXT_ON_LOAD
5965 | FLAG_HAS_JUMBO_FRAMES
5967 .flags2
= FLAG2_HAS_PHY_STATS
5970 .max_hw_frame_size
= 9022,
5971 .get_variants
= e1000_get_variants_ich8lan
,
5972 .mac_ops
= &ich8_mac_ops
,
5973 .phy_ops
= &ich8_phy_ops
,
5974 .nvm_ops
= &spt_nvm_ops
,
5977 const struct e1000_info e1000_pch_cnp_info
= {
5978 .mac
= e1000_pch_cnp
,
5979 .flags
= FLAG_IS_ICH
5981 | FLAG_HAS_HW_TIMESTAMP
5982 | FLAG_HAS_CTRLEXT_ON_LOAD
5985 | FLAG_HAS_JUMBO_FRAMES
5987 .flags2
= FLAG2_HAS_PHY_STATS
5990 .max_hw_frame_size
= 9022,
5991 .get_variants
= e1000_get_variants_ich8lan
,
5992 .mac_ops
= &ich8_mac_ops
,
5993 .phy_ops
= &ich8_phy_ops
,
5994 .nvm_ops
= &spt_nvm_ops
,