1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 /* 82562G 10/100 Network Connection
23 * 82562G-2 10/100 Network Connection
24 * 82562GT 10/100 Network Connection
25 * 82562GT-2 10/100 Network Connection
26 * 82562V 10/100 Network Connection
27 * 82562V-2 10/100 Network Connection
28 * 82566DC-2 Gigabit Network Connection
29 * 82566DC Gigabit Network Connection
30 * 82566DM-2 Gigabit Network Connection
31 * 82566DM Gigabit Network Connection
32 * 82566MC Gigabit Network Connection
33 * 82566MM Gigabit Network Connection
34 * 82567LM Gigabit Network Connection
35 * 82567LF Gigabit Network Connection
36 * 82567V Gigabit Network Connection
37 * 82567LM-2 Gigabit Network Connection
38 * 82567LF-2 Gigabit Network Connection
39 * 82567V-2 Gigabit Network Connection
40 * 82567LF-3 Gigabit Network Connection
41 * 82567LM-3 Gigabit Network Connection
42 * 82567LM-4 Gigabit Network Connection
43 * 82577LM Gigabit Network Connection
44 * 82577LC Gigabit Network Connection
45 * 82578DM Gigabit Network Connection
46 * 82578DC Gigabit Network Connection
47 * 82579LM Gigabit Network Connection
48 * 82579V Gigabit Network Connection
49 * Ethernet Connection I217-LM
50 * Ethernet Connection I217-V
51 * Ethernet Connection I218-V
52 * Ethernet Connection I218-LM
53 * Ethernet Connection (2) I218-LM
54 * Ethernet Connection (2) I218-V
55 * Ethernet Connection (3) I218-LM
56 * Ethernet Connection (3) I218-V
61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
62 /* Offset 04h HSFSTS */
63 union ich8_hws_flash_status
{
65 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
66 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
67 u16 dael
:1; /* bit 2 Direct Access error Log */
68 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
69 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
70 u16 reserved1
:2; /* bit 13:6 Reserved */
71 u16 reserved2
:6; /* bit 13:6 Reserved */
72 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
73 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
79 /* Offset 06h FLCTL */
80 union ich8_hws_flash_ctrl
{
82 u16 flcgo
:1; /* 0 Flash Cycle Go */
83 u16 flcycle
:2; /* 2:1 Flash Cycle */
84 u16 reserved
:5; /* 7:3 Reserved */
85 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
86 u16 flockdn
:6; /* 15:10 Reserved */
91 /* ICH Flash Region Access Permissions */
92 union ich8_hws_flash_regacc
{
94 u32 grra
:8; /* 0:7 GbE region Read Access */
95 u32 grwa
:8; /* 8:15 GbE region Write Access */
96 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
97 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
102 /* ICH Flash Protected Region */
103 union ich8_flash_protected_range
{
105 u32 base
:13; /* 0:12 Protected Range Base */
106 u32 reserved1
:2; /* 13:14 Reserved */
107 u32 rpe
:1; /* 15 Read Protection Enable */
108 u32 limit
:13; /* 16:28 Protected Range Limit */
109 u32 reserved2
:2; /* 29:30 Reserved */
110 u32 wpe
:1; /* 31 Write Protection Enable */
115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
117 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
118 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
119 u32 offset
, u8 byte
);
120 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
122 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
124 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
126 static s32
e1000_read_flash_data32_ich8lan(struct e1000_hw
*hw
, u32 offset
,
128 static s32
e1000_read_flash_dword_ich8lan(struct e1000_hw
*hw
,
129 u32 offset
, u32
*data
);
130 static s32
e1000_write_flash_data32_ich8lan(struct e1000_hw
*hw
,
131 u32 offset
, u32 data
);
132 static s32
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw
*hw
,
133 u32 offset
, u32 dword
);
134 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
135 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
136 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
137 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
138 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
139 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
140 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
141 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
142 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
143 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
);
144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
);
145 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
);
146 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
);
147 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
);
148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
);
149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
);
150 static int e1000_rar_set_pch2lan(struct e1000_hw
*hw
, u8
*addr
, u32 index
);
151 static int e1000_rar_set_pch_lpt(struct e1000_hw
*hw
, u8
*addr
, u32 index
);
152 static u32
e1000_rar_get_count_pch_lpt(struct e1000_hw
*hw
);
153 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
);
154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
);
155 static s32
e1000_disable_ulp_lpt_lp(struct e1000_hw
*hw
, bool force
);
156 static s32
e1000_setup_copper_link_pch_lpt(struct e1000_hw
*hw
);
157 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
);
159 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
161 return readw(hw
->flash_address
+ reg
);
164 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
166 return readl(hw
->flash_address
+ reg
);
169 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
171 writew(val
, hw
->flash_address
+ reg
);
174 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
176 writel(val
, hw
->flash_address
+ reg
);
179 #define er16flash(reg) __er16flash(hw, (reg))
180 #define er32flash(reg) __er32flash(hw, (reg))
181 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
182 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
185 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
186 * @hw: pointer to the HW structure
188 * Test access to the PHY registers by reading the PHY ID registers. If
189 * the PHY ID is already known (e.g. resume path) compare it with known ID,
190 * otherwise assume the read PHY ID is correct if it is valid.
192 * Assumes the sw/fw/hw semaphore is already acquired.
194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw
*hw
)
202 for (retry_count
= 0; retry_count
< 2; retry_count
++) {
203 ret_val
= e1e_rphy_locked(hw
, MII_PHYSID1
, &phy_reg
);
204 if (ret_val
|| (phy_reg
== 0xFFFF))
206 phy_id
= (u32
)(phy_reg
<< 16);
208 ret_val
= e1e_rphy_locked(hw
, MII_PHYSID2
, &phy_reg
);
209 if (ret_val
|| (phy_reg
== 0xFFFF)) {
213 phy_id
|= (u32
)(phy_reg
& PHY_REVISION_MASK
);
218 if (hw
->phy
.id
== phy_id
)
222 hw
->phy
.revision
= (u32
)(phy_reg
& ~PHY_REVISION_MASK
);
226 /* In case the PHY needs to be in mdio slow mode,
227 * set slow mode and try to get the PHY id again.
229 if (hw
->mac
.type
< e1000_pch_lpt
) {
230 hw
->phy
.ops
.release(hw
);
231 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
233 ret_val
= e1000e_get_phy_id(hw
);
234 hw
->phy
.ops
.acquire(hw
);
240 if (hw
->mac
.type
>= e1000_pch_lpt
) {
241 /* Only unforce SMBus if ME is not active */
242 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
243 /* Unforce SMBus mode in PHY */
244 e1e_rphy_locked(hw
, CV_SMB_CTRL
, &phy_reg
);
245 phy_reg
&= ~CV_SMB_CTRL_FORCE_SMBUS
;
246 e1e_wphy_locked(hw
, CV_SMB_CTRL
, phy_reg
);
248 /* Unforce SMBus mode in MAC */
249 mac_reg
= er32(CTRL_EXT
);
250 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
251 ew32(CTRL_EXT
, mac_reg
);
259 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
260 * @hw: pointer to the HW structure
262 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
263 * used to reset the PHY to a quiescent state when necessary.
265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw
*hw
)
269 /* Set Phy Config Counter to 50msec */
270 mac_reg
= er32(FEXTNVM3
);
271 mac_reg
&= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK
;
272 mac_reg
|= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
;
273 ew32(FEXTNVM3
, mac_reg
);
275 /* Toggle LANPHYPC Value bit */
276 mac_reg
= er32(CTRL
);
277 mac_reg
|= E1000_CTRL_LANPHYPC_OVERRIDE
;
278 mac_reg
&= ~E1000_CTRL_LANPHYPC_VALUE
;
281 usleep_range(10, 20);
282 mac_reg
&= ~E1000_CTRL_LANPHYPC_OVERRIDE
;
286 if (hw
->mac
.type
< e1000_pch_lpt
) {
292 usleep_range(5000, 10000);
293 } while (!(er32(CTRL_EXT
) & E1000_CTRL_EXT_LPCD
) && count
--);
300 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
301 * @hw: pointer to the HW structure
303 * Workarounds/flow necessary for PHY initialization during driver load
306 static s32
e1000_init_phy_workarounds_pchlan(struct e1000_hw
*hw
)
308 struct e1000_adapter
*adapter
= hw
->adapter
;
309 u32 mac_reg
, fwsm
= er32(FWSM
);
312 /* Gate automatic PHY configuration by hardware on managed and
313 * non-managed 82579 and newer adapters.
315 e1000_gate_hw_phy_config_ich8lan(hw
, true);
317 /* It is not possible to be certain of the current state of ULP
318 * so forcibly disable it.
320 hw
->dev_spec
.ich8lan
.ulp_state
= e1000_ulp_state_unknown
;
321 e1000_disable_ulp_lpt_lp(hw
, true);
323 ret_val
= hw
->phy
.ops
.acquire(hw
);
325 e_dbg("Failed to initialize PHY flow\n");
329 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
330 * inaccessible and resetting the PHY is not blocked, toggle the
331 * LANPHYPC Value bit to force the interconnect to PCIe mode.
333 switch (hw
->mac
.type
) {
337 if (e1000_phy_is_accessible_pchlan(hw
))
340 /* Before toggling LANPHYPC, see if PHY is accessible by
341 * forcing MAC to SMBus mode first.
343 mac_reg
= er32(CTRL_EXT
);
344 mac_reg
|= E1000_CTRL_EXT_FORCE_SMBUS
;
345 ew32(CTRL_EXT
, mac_reg
);
347 /* Wait 50 milliseconds for MAC to finish any retries
348 * that it might be trying to perform from previous
349 * attempts to acknowledge any phy read requests.
355 if (e1000_phy_is_accessible_pchlan(hw
))
360 if ((hw
->mac
.type
== e1000_pchlan
) &&
361 (fwsm
& E1000_ICH_FWSM_FW_VALID
))
364 if (hw
->phy
.ops
.check_reset_block(hw
)) {
365 e_dbg("Required LANPHYPC toggle blocked by ME\n");
366 ret_val
= -E1000_ERR_PHY
;
370 /* Toggle LANPHYPC Value bit */
371 e1000_toggle_lanphypc_pch_lpt(hw
);
372 if (hw
->mac
.type
>= e1000_pch_lpt
) {
373 if (e1000_phy_is_accessible_pchlan(hw
))
376 /* Toggling LANPHYPC brings the PHY out of SMBus mode
377 * so ensure that the MAC is also out of SMBus mode
379 mac_reg
= er32(CTRL_EXT
);
380 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
381 ew32(CTRL_EXT
, mac_reg
);
383 if (e1000_phy_is_accessible_pchlan(hw
))
386 ret_val
= -E1000_ERR_PHY
;
393 hw
->phy
.ops
.release(hw
);
396 /* Check to see if able to reset PHY. Print error if not */
397 if (hw
->phy
.ops
.check_reset_block(hw
)) {
398 e_err("Reset blocked by ME\n");
402 /* Reset the PHY before any access to it. Doing so, ensures
403 * that the PHY is in a known good state before we read/write
404 * PHY registers. The generic reset is sufficient here,
405 * because we haven't determined the PHY type yet.
407 ret_val
= e1000e_phy_hw_reset_generic(hw
);
411 /* On a successful reset, possibly need to wait for the PHY
412 * to quiesce to an accessible state before returning control
413 * to the calling function. If the PHY does not quiesce, then
414 * return E1000E_BLK_PHY_RESET, as this is the condition that
417 ret_val
= hw
->phy
.ops
.check_reset_block(hw
);
419 e_err("ME blocked access to PHY after reset\n");
423 /* Ungate automatic PHY configuration on non-managed 82579 */
424 if ((hw
->mac
.type
== e1000_pch2lan
) &&
425 !(fwsm
& E1000_ICH_FWSM_FW_VALID
)) {
426 usleep_range(10000, 20000);
427 e1000_gate_hw_phy_config_ich8lan(hw
, false);
434 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
435 * @hw: pointer to the HW structure
437 * Initialize family-specific PHY parameters and function pointers.
439 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
441 struct e1000_phy_info
*phy
= &hw
->phy
;
445 phy
->reset_delay_us
= 100;
447 phy
->ops
.set_page
= e1000_set_page_igp
;
448 phy
->ops
.read_reg
= e1000_read_phy_reg_hv
;
449 phy
->ops
.read_reg_locked
= e1000_read_phy_reg_hv_locked
;
450 phy
->ops
.read_reg_page
= e1000_read_phy_reg_page_hv
;
451 phy
->ops
.set_d0_lplu_state
= e1000_set_lplu_state_pchlan
;
452 phy
->ops
.set_d3_lplu_state
= e1000_set_lplu_state_pchlan
;
453 phy
->ops
.write_reg
= e1000_write_phy_reg_hv
;
454 phy
->ops
.write_reg_locked
= e1000_write_phy_reg_hv_locked
;
455 phy
->ops
.write_reg_page
= e1000_write_phy_reg_page_hv
;
456 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
457 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
458 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
460 phy
->id
= e1000_phy_unknown
;
462 ret_val
= e1000_init_phy_workarounds_pchlan(hw
);
466 if (phy
->id
== e1000_phy_unknown
)
467 switch (hw
->mac
.type
) {
469 ret_val
= e1000e_get_phy_id(hw
);
472 if ((phy
->id
!= 0) && (phy
->id
!= PHY_REVISION_MASK
))
479 /* In case the PHY needs to be in mdio slow mode,
480 * set slow mode and try to get the PHY id again.
482 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
485 ret_val
= e1000e_get_phy_id(hw
);
490 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
493 case e1000_phy_82577
:
494 case e1000_phy_82579
:
496 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
497 phy
->ops
.force_speed_duplex
=
498 e1000_phy_force_speed_duplex_82577
;
499 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
500 phy
->ops
.get_info
= e1000_get_phy_info_82577
;
501 phy
->ops
.commit
= e1000e_phy_sw_reset
;
503 case e1000_phy_82578
:
504 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
505 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
506 phy
->ops
.get_cable_length
= e1000e_get_cable_length_m88
;
507 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
510 ret_val
= -E1000_ERR_PHY
;
518 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
519 * @hw: pointer to the HW structure
521 * Initialize family-specific PHY parameters and function pointers.
523 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
525 struct e1000_phy_info
*phy
= &hw
->phy
;
530 phy
->reset_delay_us
= 100;
532 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
533 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
535 /* We may need to do this twice - once for IGP and if that fails,
536 * we'll set BM func pointers and try again
538 ret_val
= e1000e_determine_phy_address(hw
);
540 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
541 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
542 ret_val
= e1000e_determine_phy_address(hw
);
544 e_dbg("Cannot determine PHY addr. Erroring out\n");
550 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
552 usleep_range(1000, 2000);
553 ret_val
= e1000e_get_phy_id(hw
);
560 case IGP03E1000_E_PHY_ID
:
561 phy
->type
= e1000_phy_igp_3
;
562 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
563 phy
->ops
.read_reg_locked
= e1000e_read_phy_reg_igp_locked
;
564 phy
->ops
.write_reg_locked
= e1000e_write_phy_reg_igp_locked
;
565 phy
->ops
.get_info
= e1000e_get_phy_info_igp
;
566 phy
->ops
.check_polarity
= e1000_check_polarity_igp
;
567 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
;
570 case IFE_PLUS_E_PHY_ID
:
572 phy
->type
= e1000_phy_ife
;
573 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
574 phy
->ops
.get_info
= e1000_get_phy_info_ife
;
575 phy
->ops
.check_polarity
= e1000_check_polarity_ife
;
576 phy
->ops
.force_speed_duplex
= e1000_phy_force_speed_duplex_ife
;
578 case BME1000_E_PHY_ID
:
579 phy
->type
= e1000_phy_bm
;
580 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
581 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
582 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
583 phy
->ops
.commit
= e1000e_phy_sw_reset
;
584 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
585 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
586 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
589 return -E1000_ERR_PHY
;
596 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
597 * @hw: pointer to the HW structure
599 * Initialize family-specific NVM parameters and function
602 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
604 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
605 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
606 u32 gfpreg
, sector_base_addr
, sector_end_addr
;
610 nvm
->type
= e1000_nvm_flash_sw
;
612 if (hw
->mac
.type
>= e1000_pch_spt
) {
613 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
614 * STRAP register. This is because in SPT the GbE Flash region
615 * is no longer accessed through the flash registers. Instead,
616 * the mechanism has changed, and the Flash region access
617 * registers are now implemented in GbE memory space.
619 nvm
->flash_base_addr
= 0;
620 nvm_size
= (((er32(STRAP
) >> 1) & 0x1F) + 1)
621 * NVM_SIZE_MULTIPLIER
;
622 nvm
->flash_bank_size
= nvm_size
/ 2;
623 /* Adjust to word count */
624 nvm
->flash_bank_size
/= sizeof(u16
);
625 /* Set the base address for flash register access */
626 hw
->flash_address
= hw
->hw_addr
+ E1000_FLASH_BASE_ADDR
;
628 /* Can't read flash registers if register set isn't mapped. */
629 if (!hw
->flash_address
) {
630 e_dbg("ERROR: Flash registers not mapped\n");
631 return -E1000_ERR_CONFIG
;
634 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
636 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
637 * Add 1 to sector_end_addr since this sector is included in
640 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
641 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
643 /* flash_base_addr is byte-aligned */
644 nvm
->flash_base_addr
= sector_base_addr
645 << FLASH_SECTOR_ADDR_SHIFT
;
647 /* find total size of the NVM, then cut in half since the total
648 * size represents two separate NVM banks.
650 nvm
->flash_bank_size
= ((sector_end_addr
- sector_base_addr
)
651 << FLASH_SECTOR_ADDR_SHIFT
);
652 nvm
->flash_bank_size
/= 2;
653 /* Adjust to word count */
654 nvm
->flash_bank_size
/= sizeof(u16
);
657 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
659 /* Clear shadow ram */
660 for (i
= 0; i
< nvm
->word_size
; i
++) {
661 dev_spec
->shadow_ram
[i
].modified
= false;
662 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
669 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
670 * @hw: pointer to the HW structure
672 * Initialize family-specific MAC parameters and function
675 static s32
e1000_init_mac_params_ich8lan(struct e1000_hw
*hw
)
677 struct e1000_mac_info
*mac
= &hw
->mac
;
679 /* Set media type function pointer */
680 hw
->phy
.media_type
= e1000_media_type_copper
;
682 /* Set mta register count */
683 mac
->mta_reg_count
= 32;
684 /* Set rar entry count */
685 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
686 if (mac
->type
== e1000_ich8lan
)
687 mac
->rar_entry_count
--;
689 mac
->has_fwsm
= true;
690 /* ARC subsystem not supported */
691 mac
->arc_subsystem_valid
= false;
692 /* Adaptive IFS supported */
693 mac
->adaptive_ifs
= true;
695 /* LED and other operations */
700 /* check management mode */
701 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_ich8lan
;
703 mac
->ops
.id_led_init
= e1000e_id_led_init_generic
;
705 mac
->ops
.blink_led
= e1000e_blink_led_generic
;
707 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
709 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
710 /* turn on/off LED */
711 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
712 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
715 mac
->rar_entry_count
= E1000_PCH2_RAR_ENTRIES
;
716 mac
->ops
.rar_set
= e1000_rar_set_pch2lan
;
722 /* check management mode */
723 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_pchlan
;
725 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
727 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
729 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
730 /* turn on/off LED */
731 mac
->ops
.led_on
= e1000_led_on_pchlan
;
732 mac
->ops
.led_off
= e1000_led_off_pchlan
;
738 if (mac
->type
>= e1000_pch_lpt
) {
739 mac
->rar_entry_count
= E1000_PCH_LPT_RAR_ENTRIES
;
740 mac
->ops
.rar_set
= e1000_rar_set_pch_lpt
;
741 mac
->ops
.setup_physical_interface
=
742 e1000_setup_copper_link_pch_lpt
;
743 mac
->ops
.rar_get_count
= e1000_rar_get_count_pch_lpt
;
746 /* Enable PCS Lock-loss workaround for ICH8 */
747 if (mac
->type
== e1000_ich8lan
)
748 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, true);
754 * __e1000_access_emi_reg_locked - Read/write EMI register
755 * @hw: pointer to the HW structure
756 * @addr: EMI address to program
757 * @data: pointer to value to read/write from/to the EMI address
758 * @read: boolean flag to indicate read or write
760 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
762 static s32
__e1000_access_emi_reg_locked(struct e1000_hw
*hw
, u16 address
,
763 u16
*data
, bool read
)
767 ret_val
= e1e_wphy_locked(hw
, I82579_EMI_ADDR
, address
);
772 ret_val
= e1e_rphy_locked(hw
, I82579_EMI_DATA
, data
);
774 ret_val
= e1e_wphy_locked(hw
, I82579_EMI_DATA
, *data
);
780 * e1000_read_emi_reg_locked - Read Extended Management Interface register
781 * @hw: pointer to the HW structure
782 * @addr: EMI address to program
783 * @data: value to be read from the EMI address
785 * Assumes the SW/FW/HW Semaphore is already acquired.
787 s32
e1000_read_emi_reg_locked(struct e1000_hw
*hw
, u16 addr
, u16
*data
)
789 return __e1000_access_emi_reg_locked(hw
, addr
, data
, true);
793 * e1000_write_emi_reg_locked - Write Extended Management Interface register
794 * @hw: pointer to the HW structure
795 * @addr: EMI address to program
796 * @data: value to be written to the EMI address
798 * Assumes the SW/FW/HW Semaphore is already acquired.
800 s32
e1000_write_emi_reg_locked(struct e1000_hw
*hw
, u16 addr
, u16 data
)
802 return __e1000_access_emi_reg_locked(hw
, addr
, &data
, false);
806 * e1000_set_eee_pchlan - Enable/disable EEE support
807 * @hw: pointer to the HW structure
809 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
810 * the link and the EEE capabilities of the link partner. The LPI Control
811 * register bits will remain set only if/when link is up.
813 * EEE LPI must not be asserted earlier than one second after link is up.
814 * On 82579, EEE LPI should not be enabled until such time otherwise there
815 * can be link issues with some switches. Other devices can have EEE LPI
816 * enabled immediately upon link up since they have a timer in hardware which
817 * prevents LPI from being asserted too early.
819 s32
e1000_set_eee_pchlan(struct e1000_hw
*hw
)
821 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
823 u16 lpa
, pcs_status
, adv
, adv_addr
, lpi_ctrl
, data
;
825 switch (hw
->phy
.type
) {
826 case e1000_phy_82579
:
827 lpa
= I82579_EEE_LP_ABILITY
;
828 pcs_status
= I82579_EEE_PCS_STATUS
;
829 adv_addr
= I82579_EEE_ADVERTISEMENT
;
832 lpa
= I217_EEE_LP_ABILITY
;
833 pcs_status
= I217_EEE_PCS_STATUS
;
834 adv_addr
= I217_EEE_ADVERTISEMENT
;
840 ret_val
= hw
->phy
.ops
.acquire(hw
);
844 ret_val
= e1e_rphy_locked(hw
, I82579_LPI_CTRL
, &lpi_ctrl
);
848 /* Clear bits that enable EEE in various speeds */
849 lpi_ctrl
&= ~I82579_LPI_CTRL_ENABLE_MASK
;
851 /* Enable EEE if not disabled by user */
852 if (!dev_spec
->eee_disable
) {
853 /* Save off link partner's EEE ability */
854 ret_val
= e1000_read_emi_reg_locked(hw
, lpa
,
855 &dev_spec
->eee_lp_ability
);
859 /* Read EEE advertisement */
860 ret_val
= e1000_read_emi_reg_locked(hw
, adv_addr
, &adv
);
864 /* Enable EEE only for speeds in which the link partner is
865 * EEE capable and for which we advertise EEE.
867 if (adv
& dev_spec
->eee_lp_ability
& I82579_EEE_1000_SUPPORTED
)
868 lpi_ctrl
|= I82579_LPI_CTRL_1000_ENABLE
;
870 if (adv
& dev_spec
->eee_lp_ability
& I82579_EEE_100_SUPPORTED
) {
871 e1e_rphy_locked(hw
, MII_LPA
, &data
);
872 if (data
& LPA_100FULL
)
873 lpi_ctrl
|= I82579_LPI_CTRL_100_ENABLE
;
875 /* EEE is not supported in 100Half, so ignore
876 * partner's EEE in 100 ability if full-duplex
879 dev_spec
->eee_lp_ability
&=
880 ~I82579_EEE_100_SUPPORTED
;
884 if (hw
->phy
.type
== e1000_phy_82579
) {
885 ret_val
= e1000_read_emi_reg_locked(hw
, I82579_LPI_PLL_SHUT
,
890 data
&= ~I82579_LPI_100_PLL_SHUT
;
891 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_LPI_PLL_SHUT
,
895 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
896 ret_val
= e1000_read_emi_reg_locked(hw
, pcs_status
, &data
);
900 ret_val
= e1e_wphy_locked(hw
, I82579_LPI_CTRL
, lpi_ctrl
);
902 hw
->phy
.ops
.release(hw
);
908 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
909 * @hw: pointer to the HW structure
910 * @link: link up bool flag
912 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
913 * preventing further DMA write requests. Workaround the issue by disabling
914 * the de-assertion of the clock request when in 1Gpbs mode.
915 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
916 * speeds in order to avoid Tx hangs.
918 static s32
e1000_k1_workaround_lpt_lp(struct e1000_hw
*hw
, bool link
)
920 u32 fextnvm6
= er32(FEXTNVM6
);
921 u32 status
= er32(STATUS
);
925 if (link
&& (status
& E1000_STATUS_SPEED_1000
)) {
926 ret_val
= hw
->phy
.ops
.acquire(hw
);
931 e1000e_read_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
937 e1000e_write_kmrn_reg_locked(hw
,
938 E1000_KMRNCTRLSTA_K1_CONFIG
,
940 ~E1000_KMRNCTRLSTA_K1_ENABLE
);
944 usleep_range(10, 20);
946 ew32(FEXTNVM6
, fextnvm6
| E1000_FEXTNVM6_REQ_PLL_CLK
);
949 e1000e_write_kmrn_reg_locked(hw
,
950 E1000_KMRNCTRLSTA_K1_CONFIG
,
953 hw
->phy
.ops
.release(hw
);
955 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
956 fextnvm6
&= ~E1000_FEXTNVM6_REQ_PLL_CLK
;
958 if ((hw
->phy
.revision
> 5) || !link
||
959 ((status
& E1000_STATUS_SPEED_100
) &&
960 (status
& E1000_STATUS_FD
)))
961 goto update_fextnvm6
;
963 ret_val
= e1e_rphy(hw
, I217_INBAND_CTRL
, ®
);
967 /* Clear link status transmit timeout */
968 reg
&= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK
;
970 if (status
& E1000_STATUS_SPEED_100
) {
971 /* Set inband Tx timeout to 5x10us for 100Half */
972 reg
|= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT
;
974 /* Do not extend the K1 entry latency for 100Half */
975 fextnvm6
&= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION
;
977 /* Set inband Tx timeout to 50x10us for 10Full/Half */
979 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT
;
981 /* Extend the K1 entry latency for 10 Mbps */
982 fextnvm6
|= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION
;
985 ret_val
= e1e_wphy(hw
, I217_INBAND_CTRL
, reg
);
990 ew32(FEXTNVM6
, fextnvm6
);
997 * e1000_platform_pm_pch_lpt - Set platform power management values
998 * @hw: pointer to the HW structure
999 * @link: bool indicating link status
1001 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1002 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1003 * when link is up (which must not exceed the maximum latency supported
1004 * by the platform), otherwise specify there is no LTR requirement.
1005 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1006 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1007 * Capability register set, on this device LTR is set by writing the
1008 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1009 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1010 * message to the PMC.
1012 static s32
e1000_platform_pm_pch_lpt(struct e1000_hw
*hw
, bool link
)
1014 u32 reg
= link
<< (E1000_LTRV_REQ_SHIFT
+ E1000_LTRV_NOSNOOP_SHIFT
) |
1015 link
<< E1000_LTRV_REQ_SHIFT
| E1000_LTRV_SEND
;
1016 u16 lat_enc
= 0; /* latency encoded */
1019 u16 speed
, duplex
, scale
= 0;
1020 u16 max_snoop
, max_nosnoop
;
1021 u16 max_ltr_enc
; /* max LTR latency encoded */
1025 if (!hw
->adapter
->max_frame_size
) {
1026 e_dbg("max_frame_size not set.\n");
1027 return -E1000_ERR_CONFIG
;
1030 hw
->mac
.ops
.get_link_up_info(hw
, &speed
, &duplex
);
1032 e_dbg("Speed not set.\n");
1033 return -E1000_ERR_CONFIG
;
1036 /* Rx Packet Buffer Allocation size (KB) */
1037 rxa
= er32(PBA
) & E1000_PBA_RXA_MASK
;
1039 /* Determine the maximum latency tolerated by the device.
1041 * Per the PCIe spec, the tolerated latencies are encoded as
1042 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1043 * a 10-bit value (0-1023) to provide a range from 1 ns to
1044 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1045 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1048 value
= (rxa
> hw
->adapter
->max_frame_size
) ?
1049 (rxa
- hw
->adapter
->max_frame_size
) * (16000 / speed
) :
1052 while (value
> PCI_LTR_VALUE_MASK
) {
1054 value
= DIV_ROUND_UP(value
, BIT(5));
1056 if (scale
> E1000_LTRV_SCALE_MAX
) {
1057 e_dbg("Invalid LTR latency scale %d\n", scale
);
1058 return -E1000_ERR_CONFIG
;
1060 lat_enc
= (u16
)((scale
<< PCI_LTR_SCALE_SHIFT
) | value
);
1062 /* Determine the maximum latency tolerated by the platform */
1063 pci_read_config_word(hw
->adapter
->pdev
, E1000_PCI_LTR_CAP_LPT
,
1065 pci_read_config_word(hw
->adapter
->pdev
,
1066 E1000_PCI_LTR_CAP_LPT
+ 2, &max_nosnoop
);
1067 max_ltr_enc
= max_t(u16
, max_snoop
, max_nosnoop
);
1069 if (lat_enc
> max_ltr_enc
)
1070 lat_enc
= max_ltr_enc
;
1073 /* Set Snoop and No-Snoop latencies the same */
1074 reg
|= lat_enc
| (lat_enc
<< E1000_LTRV_NOSNOOP_SHIFT
);
1081 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1082 * @hw: pointer to the HW structure
1083 * @to_sx: boolean indicating a system power state transition to Sx
1085 * When link is down, configure ULP mode to significantly reduce the power
1086 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1087 * ME firmware to start the ULP configuration. If not on an ME enabled
1088 * system, configure the ULP mode by software.
1090 s32
e1000_enable_ulp_lpt_lp(struct e1000_hw
*hw
, bool to_sx
)
1097 if ((hw
->mac
.type
< e1000_pch_lpt
) ||
1098 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPT_I217_LM
) ||
1099 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPT_I217_V
) ||
1100 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_LM2
) ||
1101 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_V2
) ||
1102 (hw
->dev_spec
.ich8lan
.ulp_state
== e1000_ulp_state_on
))
1105 if (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
) {
1106 /* Request ME configure ULP mode in the PHY */
1107 mac_reg
= er32(H2ME
);
1108 mac_reg
|= E1000_H2ME_ULP
| E1000_H2ME_ENFORCE_SETTINGS
;
1109 ew32(H2ME
, mac_reg
);
1117 /* Poll up to 5 seconds for Cable Disconnected indication */
1118 while (!(er32(FEXT
) & E1000_FEXT_PHY_CABLE_DISCONNECTED
)) {
1119 /* Bail if link is re-acquired */
1120 if (er32(STATUS
) & E1000_STATUS_LU
)
1121 return -E1000_ERR_PHY
;
1128 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1130 E1000_FEXT_PHY_CABLE_DISCONNECTED
) ? "" : "not", i
* 50);
1133 ret_val
= hw
->phy
.ops
.acquire(hw
);
1137 /* Force SMBus mode in PHY */
1138 ret_val
= e1000_read_phy_reg_hv_locked(hw
, CV_SMB_CTRL
, &phy_reg
);
1141 phy_reg
|= CV_SMB_CTRL_FORCE_SMBUS
;
1142 e1000_write_phy_reg_hv_locked(hw
, CV_SMB_CTRL
, phy_reg
);
1144 /* Force SMBus mode in MAC */
1145 mac_reg
= er32(CTRL_EXT
);
1146 mac_reg
|= E1000_CTRL_EXT_FORCE_SMBUS
;
1147 ew32(CTRL_EXT
, mac_reg
);
1149 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1150 * LPLU and disable Gig speed when entering ULP
1152 if ((hw
->phy
.type
== e1000_phy_i217
) && (hw
->phy
.revision
== 6)) {
1153 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_OEM_BITS
,
1159 phy_reg
|= HV_OEM_BITS_LPLU
| HV_OEM_BITS_GBE_DIS
;
1161 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_OEM_BITS
,
1168 /* Set Inband ULP Exit, Reset to SMBus mode and
1169 * Disable SMBus Release on PERST# in PHY
1171 ret_val
= e1000_read_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, &phy_reg
);
1174 phy_reg
|= (I218_ULP_CONFIG1_RESET_TO_SMBUS
|
1175 I218_ULP_CONFIG1_DISABLE_SMB_PERST
);
1177 if (er32(WUFC
) & E1000_WUFC_LNKC
)
1178 phy_reg
|= I218_ULP_CONFIG1_WOL_HOST
;
1180 phy_reg
&= ~I218_ULP_CONFIG1_WOL_HOST
;
1182 phy_reg
|= I218_ULP_CONFIG1_STICKY_ULP
;
1183 phy_reg
&= ~I218_ULP_CONFIG1_INBAND_EXIT
;
1185 phy_reg
|= I218_ULP_CONFIG1_INBAND_EXIT
;
1186 phy_reg
&= ~I218_ULP_CONFIG1_STICKY_ULP
;
1187 phy_reg
&= ~I218_ULP_CONFIG1_WOL_HOST
;
1189 e1000_write_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, phy_reg
);
1191 /* Set Disable SMBus Release on PERST# in MAC */
1192 mac_reg
= er32(FEXTNVM7
);
1193 mac_reg
|= E1000_FEXTNVM7_DISABLE_SMB_PERST
;
1194 ew32(FEXTNVM7
, mac_reg
);
1196 /* Commit ULP changes in PHY by starting auto ULP configuration */
1197 phy_reg
|= I218_ULP_CONFIG1_START
;
1198 e1000_write_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, phy_reg
);
1200 if ((hw
->phy
.type
== e1000_phy_i217
) && (hw
->phy
.revision
== 6) &&
1201 to_sx
&& (er32(STATUS
) & E1000_STATUS_LU
)) {
1202 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_OEM_BITS
,
1209 hw
->phy
.ops
.release(hw
);
1212 e_dbg("Error in ULP enable flow: %d\n", ret_val
);
1214 hw
->dev_spec
.ich8lan
.ulp_state
= e1000_ulp_state_on
;
1220 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1221 * @hw: pointer to the HW structure
1222 * @force: boolean indicating whether or not to force disabling ULP
1224 * Un-configure ULP mode when link is up, the system is transitioned from
1225 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1226 * system, poll for an indication from ME that ULP has been un-configured.
1227 * If not on an ME enabled system, un-configure the ULP mode by software.
1229 * During nominal operation, this function is called when link is acquired
1230 * to disable ULP mode (force=false); otherwise, for example when unloading
1231 * the driver or during Sx->S0 transitions, this is called with force=true
1232 * to forcibly disable ULP.
1234 static s32
e1000_disable_ulp_lpt_lp(struct e1000_hw
*hw
, bool force
)
1241 if ((hw
->mac
.type
< e1000_pch_lpt
) ||
1242 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPT_I217_LM
) ||
1243 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPT_I217_V
) ||
1244 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_LM2
) ||
1245 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_V2
) ||
1246 (hw
->dev_spec
.ich8lan
.ulp_state
== e1000_ulp_state_off
))
1249 if (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
) {
1251 /* Request ME un-configure ULP mode in the PHY */
1252 mac_reg
= er32(H2ME
);
1253 mac_reg
&= ~E1000_H2ME_ULP
;
1254 mac_reg
|= E1000_H2ME_ENFORCE_SETTINGS
;
1255 ew32(H2ME
, mac_reg
);
1258 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1259 while (er32(FWSM
) & E1000_FWSM_ULP_CFG_DONE
) {
1261 ret_val
= -E1000_ERR_PHY
;
1265 usleep_range(10000, 20000);
1267 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i
* 10);
1270 mac_reg
= er32(H2ME
);
1271 mac_reg
&= ~E1000_H2ME_ENFORCE_SETTINGS
;
1272 ew32(H2ME
, mac_reg
);
1274 /* Clear H2ME.ULP after ME ULP configuration */
1275 mac_reg
= er32(H2ME
);
1276 mac_reg
&= ~E1000_H2ME_ULP
;
1277 ew32(H2ME
, mac_reg
);
1283 ret_val
= hw
->phy
.ops
.acquire(hw
);
1288 /* Toggle LANPHYPC Value bit */
1289 e1000_toggle_lanphypc_pch_lpt(hw
);
1291 /* Unforce SMBus mode in PHY */
1292 ret_val
= e1000_read_phy_reg_hv_locked(hw
, CV_SMB_CTRL
, &phy_reg
);
1294 /* The MAC might be in PCIe mode, so temporarily force to
1295 * SMBus mode in order to access the PHY.
1297 mac_reg
= er32(CTRL_EXT
);
1298 mac_reg
|= E1000_CTRL_EXT_FORCE_SMBUS
;
1299 ew32(CTRL_EXT
, mac_reg
);
1303 ret_val
= e1000_read_phy_reg_hv_locked(hw
, CV_SMB_CTRL
,
1308 phy_reg
&= ~CV_SMB_CTRL_FORCE_SMBUS
;
1309 e1000_write_phy_reg_hv_locked(hw
, CV_SMB_CTRL
, phy_reg
);
1311 /* Unforce SMBus mode in MAC */
1312 mac_reg
= er32(CTRL_EXT
);
1313 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
1314 ew32(CTRL_EXT
, mac_reg
);
1316 /* When ULP mode was previously entered, K1 was disabled by the
1317 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1319 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_PM_CTRL
, &phy_reg
);
1322 phy_reg
|= HV_PM_CTRL_K1_ENABLE
;
1323 e1000_write_phy_reg_hv_locked(hw
, HV_PM_CTRL
, phy_reg
);
1325 /* Clear ULP enabled configuration */
1326 ret_val
= e1000_read_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, &phy_reg
);
1329 phy_reg
&= ~(I218_ULP_CONFIG1_IND
|
1330 I218_ULP_CONFIG1_STICKY_ULP
|
1331 I218_ULP_CONFIG1_RESET_TO_SMBUS
|
1332 I218_ULP_CONFIG1_WOL_HOST
|
1333 I218_ULP_CONFIG1_INBAND_EXIT
|
1334 I218_ULP_CONFIG1_EN_ULP_LANPHYPC
|
1335 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST
|
1336 I218_ULP_CONFIG1_DISABLE_SMB_PERST
);
1337 e1000_write_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, phy_reg
);
1339 /* Commit ULP changes by starting auto ULP configuration */
1340 phy_reg
|= I218_ULP_CONFIG1_START
;
1341 e1000_write_phy_reg_hv_locked(hw
, I218_ULP_CONFIG1
, phy_reg
);
1343 /* Clear Disable SMBus Release on PERST# in MAC */
1344 mac_reg
= er32(FEXTNVM7
);
1345 mac_reg
&= ~E1000_FEXTNVM7_DISABLE_SMB_PERST
;
1346 ew32(FEXTNVM7
, mac_reg
);
1349 hw
->phy
.ops
.release(hw
);
1351 e1000_phy_hw_reset(hw
);
1356 e_dbg("Error in ULP disable flow: %d\n", ret_val
);
1358 hw
->dev_spec
.ich8lan
.ulp_state
= e1000_ulp_state_off
;
1364 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1365 * @hw: pointer to the HW structure
1367 * Checks to see of the link status of the hardware has changed. If a
1368 * change in link status has been detected, then we read the PHY registers
1369 * to get the current speed/duplex if link exists.
1371 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw
*hw
)
1373 struct e1000_mac_info
*mac
= &hw
->mac
;
1374 s32 ret_val
, tipg_reg
= 0;
1375 u16 emi_addr
, emi_val
= 0;
1379 /* We only want to go out to the PHY registers to see if Auto-Neg
1380 * has completed and/or if our link status has changed. The
1381 * get_link_status flag is set upon receiving a Link Status
1382 * Change or Rx Sequence Error interrupt.
1384 if (!mac
->get_link_status
)
1387 /* First we want to see if the MII Status Register reports
1388 * link. If so, then we want to get the current speed/duplex
1391 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1395 if (hw
->mac
.type
== e1000_pchlan
) {
1396 ret_val
= e1000_k1_gig_workaround_hv(hw
, link
);
1401 /* When connected at 10Mbps half-duplex, some parts are excessively
1402 * aggressive resulting in many collisions. To avoid this, increase
1403 * the IPG and reduce Rx latency in the PHY.
1405 if ((hw
->mac
.type
>= e1000_pch2lan
) && link
) {
1408 e1000e_get_speed_and_duplex_copper(hw
, &speed
, &duplex
);
1409 tipg_reg
= er32(TIPG
);
1410 tipg_reg
&= ~E1000_TIPG_IPGT_MASK
;
1412 if (duplex
== HALF_DUPLEX
&& speed
== SPEED_10
) {
1414 /* Reduce Rx latency in analog PHY */
1416 } else if (hw
->mac
.type
>= e1000_pch_spt
&&
1417 duplex
== FULL_DUPLEX
&& speed
!= SPEED_1000
) {
1422 /* Roll back the default values */
1427 ew32(TIPG
, tipg_reg
);
1429 ret_val
= hw
->phy
.ops
.acquire(hw
);
1433 if (hw
->mac
.type
== e1000_pch2lan
)
1434 emi_addr
= I82579_RX_CONFIG
;
1436 emi_addr
= I217_RX_CONFIG
;
1437 ret_val
= e1000_write_emi_reg_locked(hw
, emi_addr
, emi_val
);
1439 if (hw
->mac
.type
>= e1000_pch_lpt
) {
1442 e1e_rphy_locked(hw
, I217_PLL_CLOCK_GATE_REG
, &phy_reg
);
1443 phy_reg
&= ~I217_PLL_CLOCK_GATE_MASK
;
1444 if (speed
== SPEED_100
|| speed
== SPEED_10
)
1448 e1e_wphy_locked(hw
, I217_PLL_CLOCK_GATE_REG
, phy_reg
);
1450 hw
->phy
.ops
.release(hw
);
1455 if (hw
->mac
.type
>= e1000_pch_spt
) {
1459 if (speed
== SPEED_1000
) {
1460 ret_val
= hw
->phy
.ops
.acquire(hw
);
1464 ret_val
= e1e_rphy_locked(hw
,
1468 hw
->phy
.ops
.release(hw
);
1472 ptr_gap
= (data
& (0x3FF << 2)) >> 2;
1473 if (ptr_gap
< 0x18) {
1474 data
&= ~(0x3FF << 2);
1475 data
|= (0x18 << 2);
1481 hw
->phy
.ops
.release(hw
);
1485 ret_val
= hw
->phy
.ops
.acquire(hw
);
1489 ret_val
= e1e_wphy_locked(hw
,
1492 hw
->phy
.ops
.release(hw
);
1500 /* I217 Packet Loss issue:
1501 * ensure that FEXTNVM4 Beacon Duration is set correctly
1503 * Set the Beacon Duration for I217 to 8 usec
1505 if (hw
->mac
.type
>= e1000_pch_lpt
) {
1508 mac_reg
= er32(FEXTNVM4
);
1509 mac_reg
&= ~E1000_FEXTNVM4_BEACON_DURATION_MASK
;
1510 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_8USEC
;
1511 ew32(FEXTNVM4
, mac_reg
);
1514 /* Work-around I218 hang issue */
1515 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPTLP_I218_LM
) ||
1516 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPTLP_I218_V
) ||
1517 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_LM3
) ||
1518 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_I218_V3
)) {
1519 ret_val
= e1000_k1_workaround_lpt_lp(hw
, link
);
1523 if (hw
->mac
.type
>= e1000_pch_lpt
) {
1524 /* Set platform power management values for
1525 * Latency Tolerance Reporting (LTR)
1527 ret_val
= e1000_platform_pm_pch_lpt(hw
, link
);
1532 /* Clear link partner's EEE ability */
1533 hw
->dev_spec
.ich8lan
.eee_lp_ability
= 0;
1535 if (hw
->mac
.type
>= e1000_pch_lpt
) {
1536 u32 fextnvm6
= er32(FEXTNVM6
);
1538 if (hw
->mac
.type
== e1000_pch_spt
) {
1539 /* FEXTNVM6 K1-off workaround - for SPT only */
1540 u32 pcieanacfg
= er32(PCIEANACFG
);
1542 if (pcieanacfg
& E1000_FEXTNVM6_K1_OFF_ENABLE
)
1543 fextnvm6
|= E1000_FEXTNVM6_K1_OFF_ENABLE
;
1545 fextnvm6
&= ~E1000_FEXTNVM6_K1_OFF_ENABLE
;
1548 ew32(FEXTNVM6
, fextnvm6
);
1552 return 0; /* No link detected */
1554 mac
->get_link_status
= false;
1556 switch (hw
->mac
.type
) {
1558 ret_val
= e1000_k1_workaround_lv(hw
);
1563 if (hw
->phy
.type
== e1000_phy_82578
) {
1564 ret_val
= e1000_link_stall_workaround_hv(hw
);
1569 /* Workaround for PCHx parts in half-duplex:
1570 * Set the number of preambles removed from the packet
1571 * when it is passed from the PHY to the MAC to prevent
1572 * the MAC from misinterpreting the packet type.
1574 e1e_rphy(hw
, HV_KMRN_FIFO_CTRLSTA
, &phy_reg
);
1575 phy_reg
&= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK
;
1577 if ((er32(STATUS
) & E1000_STATUS_FD
) != E1000_STATUS_FD
)
1578 phy_reg
|= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT
);
1580 e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, phy_reg
);
1586 /* Check if there was DownShift, must be checked
1587 * immediately after link-up
1589 e1000e_check_downshift(hw
);
1591 /* Enable/Disable EEE after link up */
1592 if (hw
->phy
.type
> e1000_phy_82579
) {
1593 ret_val
= e1000_set_eee_pchlan(hw
);
1598 /* If we are forcing speed/duplex, then we simply return since
1599 * we have already determined whether we have link or not.
1602 return -E1000_ERR_CONFIG
;
1604 /* Auto-Neg is enabled. Auto Speed Detection takes care
1605 * of MAC speed/duplex configuration. So we only need to
1606 * configure Collision Distance in the MAC.
1608 mac
->ops
.config_collision_dist(hw
);
1610 /* Configure Flow Control now that Auto-Neg has completed.
1611 * First, we need to restore the desired flow control
1612 * settings because we may have had to re-autoneg with a
1613 * different link partner.
1615 ret_val
= e1000e_config_fc_after_link_up(hw
);
1617 e_dbg("Error configuring flow control\n");
1622 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
1624 struct e1000_hw
*hw
= &adapter
->hw
;
1627 rc
= e1000_init_mac_params_ich8lan(hw
);
1631 rc
= e1000_init_nvm_params_ich8lan(hw
);
1635 switch (hw
->mac
.type
) {
1638 case e1000_ich10lan
:
1639 rc
= e1000_init_phy_params_ich8lan(hw
);
1646 rc
= e1000_init_phy_params_pchlan(hw
);
1654 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1655 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1657 if ((adapter
->hw
.phy
.type
== e1000_phy_ife
) ||
1658 ((adapter
->hw
.mac
.type
>= e1000_pch2lan
) &&
1659 (!(er32(CTRL_EXT
) & E1000_CTRL_EXT_LSECCK
)))) {
1660 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
1661 adapter
->max_hw_frame_size
= VLAN_ETH_FRAME_LEN
+ ETH_FCS_LEN
;
1663 hw
->mac
.ops
.blink_led
= NULL
;
1666 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
1667 (adapter
->hw
.phy
.type
!= e1000_phy_ife
))
1668 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
1670 /* Enable workaround for 82579 w/ ME enabled */
1671 if ((adapter
->hw
.mac
.type
== e1000_pch2lan
) &&
1672 (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
1673 adapter
->flags2
|= FLAG2_PCIM2PCI_ARBITER_WA
;
1678 static DEFINE_MUTEX(nvm_mutex
);
1681 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1682 * @hw: pointer to the HW structure
1684 * Acquires the mutex for performing NVM operations.
1686 static s32
e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused
*hw
)
1688 mutex_lock(&nvm_mutex
);
1694 * e1000_release_nvm_ich8lan - Release NVM mutex
1695 * @hw: pointer to the HW structure
1697 * Releases the mutex used while performing NVM operations.
1699 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused
*hw
)
1701 mutex_unlock(&nvm_mutex
);
1705 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1706 * @hw: pointer to the HW structure
1708 * Acquires the software control flag for performing PHY and select
1711 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
1713 u32 extcnf_ctrl
, timeout
= PHY_CFG_TIMEOUT
;
1716 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE
,
1717 &hw
->adapter
->state
)) {
1718 e_dbg("contention for Phy access\n");
1719 return -E1000_ERR_PHY
;
1723 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1724 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
))
1732 e_dbg("SW has already locked the resource.\n");
1733 ret_val
= -E1000_ERR_CONFIG
;
1737 timeout
= SW_FLAG_TIMEOUT
;
1739 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
1740 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1743 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1744 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
1752 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1753 er32(FWSM
), extcnf_ctrl
);
1754 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
1755 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1756 ret_val
= -E1000_ERR_CONFIG
;
1762 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
1768 * e1000_release_swflag_ich8lan - Release software control flag
1769 * @hw: pointer to the HW structure
1771 * Releases the software control flag for performing PHY and select
1774 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
1778 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1780 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
) {
1781 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
1782 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1784 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1787 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
1791 * e1000_check_mng_mode_ich8lan - Checks management mode
1792 * @hw: pointer to the HW structure
1794 * This checks if the adapter has any manageability enabled.
1795 * This is a function pointer entry point only called by read/write
1796 * routines for the PHY and NVM parts.
1798 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
1803 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
1804 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1805 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
1809 * e1000_check_mng_mode_pchlan - Checks management mode
1810 * @hw: pointer to the HW structure
1812 * This checks if the adapter has iAMT enabled.
1813 * This is a function pointer entry point only called by read/write
1814 * routines for the PHY and NVM parts.
1816 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
)
1821 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
1822 (fwsm
& (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
1826 * e1000_rar_set_pch2lan - Set receive address register
1827 * @hw: pointer to the HW structure
1828 * @addr: pointer to the receive address
1829 * @index: receive address array register
1831 * Sets the receive address array register at index to the address passed
1832 * in by addr. For 82579, RAR[0] is the base address register that is to
1833 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1834 * Use SHRA[0-3] in place of those reserved for ME.
1836 static int e1000_rar_set_pch2lan(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
1838 u32 rar_low
, rar_high
;
1840 /* HW expects these in little endian so we reverse the byte order
1841 * from network order (big endian) to little endian
1843 rar_low
= ((u32
)addr
[0] |
1844 ((u32
)addr
[1] << 8) |
1845 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
1847 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1849 /* If MAC address zero, no need to set the AV bit */
1850 if (rar_low
|| rar_high
)
1851 rar_high
|= E1000_RAH_AV
;
1854 ew32(RAL(index
), rar_low
);
1856 ew32(RAH(index
), rar_high
);
1861 /* RAR[1-6] are owned by manageability. Skip those and program the
1862 * next address into the SHRA register array.
1864 if (index
< (u32
)(hw
->mac
.rar_entry_count
)) {
1867 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1871 ew32(SHRAL(index
- 1), rar_low
);
1873 ew32(SHRAH(index
- 1), rar_high
);
1876 e1000_release_swflag_ich8lan(hw
);
1878 /* verify the register updates */
1879 if ((er32(SHRAL(index
- 1)) == rar_low
) &&
1880 (er32(SHRAH(index
- 1)) == rar_high
))
1883 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1884 (index
- 1), er32(FWSM
));
1888 e_dbg("Failed to write receive address at index %d\n", index
);
1889 return -E1000_ERR_CONFIG
;
1893 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1894 * @hw: pointer to the HW structure
1896 * Get the number of available receive registers that the Host can
1897 * program. SHRA[0-10] are the shared receive address registers
1898 * that are shared between the Host and manageability engine (ME).
1899 * ME can reserve any number of addresses and the host needs to be
1900 * able to tell how many available registers it has access to.
1902 static u32
e1000_rar_get_count_pch_lpt(struct e1000_hw
*hw
)
1907 wlock_mac
= er32(FWSM
) & E1000_FWSM_WLOCK_MAC_MASK
;
1908 wlock_mac
>>= E1000_FWSM_WLOCK_MAC_SHIFT
;
1910 switch (wlock_mac
) {
1912 /* All SHRA[0..10] and RAR[0] available */
1913 num_entries
= hw
->mac
.rar_entry_count
;
1916 /* Only RAR[0] available */
1920 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1921 num_entries
= wlock_mac
+ 1;
1929 * e1000_rar_set_pch_lpt - Set receive address registers
1930 * @hw: pointer to the HW structure
1931 * @addr: pointer to the receive address
1932 * @index: receive address array register
1934 * Sets the receive address register array at index to the address passed
1935 * in by addr. For LPT, RAR[0] is the base address register that is to
1936 * contain the MAC address. SHRA[0-10] are the shared receive address
1937 * registers that are shared between the Host and manageability engine (ME).
1939 static int e1000_rar_set_pch_lpt(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
1941 u32 rar_low
, rar_high
;
1944 /* HW expects these in little endian so we reverse the byte order
1945 * from network order (big endian) to little endian
1947 rar_low
= ((u32
)addr
[0] | ((u32
)addr
[1] << 8) |
1948 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
1950 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1952 /* If MAC address zero, no need to set the AV bit */
1953 if (rar_low
|| rar_high
)
1954 rar_high
|= E1000_RAH_AV
;
1957 ew32(RAL(index
), rar_low
);
1959 ew32(RAH(index
), rar_high
);
1964 /* The manageability engine (ME) can lock certain SHRAR registers that
1965 * it is using - those registers are unavailable for use.
1967 if (index
< hw
->mac
.rar_entry_count
) {
1968 wlock_mac
= er32(FWSM
) & E1000_FWSM_WLOCK_MAC_MASK
;
1969 wlock_mac
>>= E1000_FWSM_WLOCK_MAC_SHIFT
;
1971 /* Check if all SHRAR registers are locked */
1975 if ((wlock_mac
== 0) || (index
<= wlock_mac
)) {
1978 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1983 ew32(SHRAL_PCH_LPT(index
- 1), rar_low
);
1985 ew32(SHRAH_PCH_LPT(index
- 1), rar_high
);
1988 e1000_release_swflag_ich8lan(hw
);
1990 /* verify the register updates */
1991 if ((er32(SHRAL_PCH_LPT(index
- 1)) == rar_low
) &&
1992 (er32(SHRAH_PCH_LPT(index
- 1)) == rar_high
))
1998 e_dbg("Failed to write receive address at index %d\n", index
);
1999 return -E1000_ERR_CONFIG
;
2003 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2004 * @hw: pointer to the HW structure
2006 * Checks if firmware is blocking the reset of the PHY.
2007 * This is a function pointer entry point only called by
2010 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
2012 bool blocked
= false;
2015 while ((blocked
= !(er32(FWSM
) & E1000_ICH_FWSM_RSPCIPHY
)) &&
2017 usleep_range(10000, 20000);
2018 return blocked
? E1000_BLK_PHY_RESET
: 0;
2022 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2023 * @hw: pointer to the HW structure
2025 * Assumes semaphore already acquired.
2028 static s32
e1000_write_smbus_addr(struct e1000_hw
*hw
)
2031 u32 strap
= er32(STRAP
);
2032 u32 freq
= (strap
& E1000_STRAP_SMT_FREQ_MASK
) >>
2033 E1000_STRAP_SMT_FREQ_SHIFT
;
2036 strap
&= E1000_STRAP_SMBUS_ADDRESS_MASK
;
2038 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, &phy_data
);
2042 phy_data
&= ~HV_SMB_ADDR_MASK
;
2043 phy_data
|= (strap
>> E1000_STRAP_SMBUS_ADDRESS_SHIFT
);
2044 phy_data
|= HV_SMB_ADDR_PEC_EN
| HV_SMB_ADDR_VALID
;
2046 if (hw
->phy
.type
== e1000_phy_i217
) {
2047 /* Restore SMBus frequency */
2049 phy_data
&= ~HV_SMB_ADDR_FREQ_MASK
;
2050 phy_data
|= (freq
& BIT(0)) <<
2051 HV_SMB_ADDR_FREQ_LOW_SHIFT
;
2052 phy_data
|= (freq
& BIT(1)) <<
2053 (HV_SMB_ADDR_FREQ_HIGH_SHIFT
- 1);
2055 e_dbg("Unsupported SMB frequency in PHY\n");
2059 return e1000_write_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, phy_data
);
2063 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2064 * @hw: pointer to the HW structure
2066 * SW should configure the LCD from the NVM extended configuration region
2067 * as a workaround for certain parts.
2069 static s32
e1000_sw_lcd_config_ich8lan(struct e1000_hw
*hw
)
2071 struct e1000_phy_info
*phy
= &hw
->phy
;
2072 u32 i
, data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
2074 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
2076 /* Initialize the PHY from the NVM on ICH platforms. This
2077 * is needed due to an issue where the NVM configuration is
2078 * not properly autoloaded after power transitions.
2079 * Therefore, after each PHY reset, we will load the
2080 * configuration data out of the NVM manually.
2082 switch (hw
->mac
.type
) {
2084 if (phy
->type
!= e1000_phy_igp_3
)
2087 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_AMT
) ||
2088 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_C
)) {
2089 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
2098 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
2104 ret_val
= hw
->phy
.ops
.acquire(hw
);
2108 data
= er32(FEXTNVM
);
2109 if (!(data
& sw_cfg_mask
))
2112 /* Make sure HW does not configure LCD from PHY
2113 * extended configuration before SW configuration
2115 data
= er32(EXTCNF_CTRL
);
2116 if ((hw
->mac
.type
< e1000_pch2lan
) &&
2117 (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
))
2120 cnf_size
= er32(EXTCNF_SIZE
);
2121 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
2122 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
2126 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
2127 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
2129 if (((hw
->mac
.type
== e1000_pchlan
) &&
2130 !(data
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)) ||
2131 (hw
->mac
.type
> e1000_pchlan
)) {
2132 /* HW configures the SMBus address and LEDs when the
2133 * OEM and LCD Write Enable bits are set in the NVM.
2134 * When both NVM bits are cleared, SW will configure
2137 ret_val
= e1000_write_smbus_addr(hw
);
2141 data
= er32(LEDCTL
);
2142 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_LED_CONFIG
,
2148 /* Configure LCD from extended configuration region. */
2150 /* cnf_base_addr is in DWORD */
2151 word_addr
= (u16
)(cnf_base_addr
<< 1);
2153 for (i
= 0; i
< cnf_size
; i
++) {
2154 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2), 1, ®_data
);
2158 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2 + 1),
2163 /* Save off the PHY page for future writes. */
2164 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
2165 phy_page
= reg_data
;
2169 reg_addr
&= PHY_REG_MASK
;
2170 reg_addr
|= phy_page
;
2172 ret_val
= e1e_wphy_locked(hw
, (u32
)reg_addr
, reg_data
);
2178 hw
->phy
.ops
.release(hw
);
2183 * e1000_k1_gig_workaround_hv - K1 Si workaround
2184 * @hw: pointer to the HW structure
2185 * @link: link up bool flag
2187 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2188 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2189 * If link is down, the function will restore the default K1 setting located
2192 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
)
2196 bool k1_enable
= hw
->dev_spec
.ich8lan
.nvm_k1_enabled
;
2198 if (hw
->mac
.type
!= e1000_pchlan
)
2201 /* Wrap the whole flow with the sw flag */
2202 ret_val
= hw
->phy
.ops
.acquire(hw
);
2206 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2208 if (hw
->phy
.type
== e1000_phy_82578
) {
2209 ret_val
= e1e_rphy_locked(hw
, BM_CS_STATUS
,
2214 status_reg
&= (BM_CS_STATUS_LINK_UP
|
2215 BM_CS_STATUS_RESOLVED
|
2216 BM_CS_STATUS_SPEED_MASK
);
2218 if (status_reg
== (BM_CS_STATUS_LINK_UP
|
2219 BM_CS_STATUS_RESOLVED
|
2220 BM_CS_STATUS_SPEED_1000
))
2224 if (hw
->phy
.type
== e1000_phy_82577
) {
2225 ret_val
= e1e_rphy_locked(hw
, HV_M_STATUS
, &status_reg
);
2229 status_reg
&= (HV_M_STATUS_LINK_UP
|
2230 HV_M_STATUS_AUTONEG_COMPLETE
|
2231 HV_M_STATUS_SPEED_MASK
);
2233 if (status_reg
== (HV_M_STATUS_LINK_UP
|
2234 HV_M_STATUS_AUTONEG_COMPLETE
|
2235 HV_M_STATUS_SPEED_1000
))
2239 /* Link stall fix for link up */
2240 ret_val
= e1e_wphy_locked(hw
, PHY_REG(770, 19), 0x0100);
2245 /* Link stall fix for link down */
2246 ret_val
= e1e_wphy_locked(hw
, PHY_REG(770, 19), 0x4100);
2251 ret_val
= e1000_configure_k1_ich8lan(hw
, k1_enable
);
2254 hw
->phy
.ops
.release(hw
);
2260 * e1000_configure_k1_ich8lan - Configure K1 power state
2261 * @hw: pointer to the HW structure
2262 * @enable: K1 state to configure
2264 * Configure the K1 power state based on the provided parameter.
2265 * Assumes semaphore already acquired.
2267 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2269 s32
e1000_configure_k1_ich8lan(struct e1000_hw
*hw
, bool k1_enable
)
2277 ret_val
= e1000e_read_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
2283 kmrn_reg
|= E1000_KMRNCTRLSTA_K1_ENABLE
;
2285 kmrn_reg
&= ~E1000_KMRNCTRLSTA_K1_ENABLE
;
2287 ret_val
= e1000e_write_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
2292 usleep_range(20, 40);
2293 ctrl_ext
= er32(CTRL_EXT
);
2294 ctrl_reg
= er32(CTRL
);
2296 reg
= ctrl_reg
& ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
2297 reg
|= E1000_CTRL_FRCSPD
;
2300 ew32(CTRL_EXT
, ctrl_ext
| E1000_CTRL_EXT_SPD_BYPS
);
2302 usleep_range(20, 40);
2303 ew32(CTRL
, ctrl_reg
);
2304 ew32(CTRL_EXT
, ctrl_ext
);
2306 usleep_range(20, 40);
2312 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2313 * @hw: pointer to the HW structure
2314 * @d0_state: boolean if entering d0 or d3 device state
2316 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2317 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2318 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2320 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
)
2326 if (hw
->mac
.type
< e1000_pchlan
)
2329 ret_val
= hw
->phy
.ops
.acquire(hw
);
2333 if (hw
->mac
.type
== e1000_pchlan
) {
2334 mac_reg
= er32(EXTCNF_CTRL
);
2335 if (mac_reg
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)
2339 mac_reg
= er32(FEXTNVM
);
2340 if (!(mac_reg
& E1000_FEXTNVM_SW_CONFIG_ICH8M
))
2343 mac_reg
= er32(PHY_CTRL
);
2345 ret_val
= e1e_rphy_locked(hw
, HV_OEM_BITS
, &oem_reg
);
2349 oem_reg
&= ~(HV_OEM_BITS_GBE_DIS
| HV_OEM_BITS_LPLU
);
2352 if (mac_reg
& E1000_PHY_CTRL_GBE_DISABLE
)
2353 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
2355 if (mac_reg
& E1000_PHY_CTRL_D0A_LPLU
)
2356 oem_reg
|= HV_OEM_BITS_LPLU
;
2358 if (mac_reg
& (E1000_PHY_CTRL_GBE_DISABLE
|
2359 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
))
2360 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
2362 if (mac_reg
& (E1000_PHY_CTRL_D0A_LPLU
|
2363 E1000_PHY_CTRL_NOND0A_LPLU
))
2364 oem_reg
|= HV_OEM_BITS_LPLU
;
2367 /* Set Restart auto-neg to activate the bits */
2368 if ((d0_state
|| (hw
->mac
.type
!= e1000_pchlan
)) &&
2369 !hw
->phy
.ops
.check_reset_block(hw
))
2370 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
2372 ret_val
= e1e_wphy_locked(hw
, HV_OEM_BITS
, oem_reg
);
2375 hw
->phy
.ops
.release(hw
);
2381 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2382 * @hw: pointer to the HW structure
2384 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
)
2389 ret_val
= e1e_rphy(hw
, HV_KMRN_MODE_CTRL
, &data
);
2393 data
|= HV_KMRN_MDIO_SLOW
;
2395 ret_val
= e1e_wphy(hw
, HV_KMRN_MODE_CTRL
, data
);
2401 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2402 * done after every PHY reset.
2404 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
2409 if (hw
->mac
.type
!= e1000_pchlan
)
2412 /* Set MDIO slow mode before any other MDIO access */
2413 if (hw
->phy
.type
== e1000_phy_82577
) {
2414 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
2419 if (((hw
->phy
.type
== e1000_phy_82577
) &&
2420 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
2421 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
2422 /* Disable generation of early preamble */
2423 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
2427 /* Preamble tuning for SSC */
2428 ret_val
= e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, 0xA204);
2433 if (hw
->phy
.type
== e1000_phy_82578
) {
2434 /* Return registers to default by doing a soft reset then
2435 * writing 0x3140 to the control register.
2437 if (hw
->phy
.revision
< 2) {
2438 e1000e_phy_sw_reset(hw
);
2439 ret_val
= e1e_wphy(hw
, MII_BMCR
, 0x3140);
2446 ret_val
= hw
->phy
.ops
.acquire(hw
);
2451 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
2452 hw
->phy
.ops
.release(hw
);
2456 /* Configure the K1 Si workaround during phy reset assuming there is
2457 * link so that it disables K1 if link is in 1Gbps.
2459 ret_val
= e1000_k1_gig_workaround_hv(hw
, true);
2463 /* Workaround for link disconnects on a busy hub in half duplex */
2464 ret_val
= hw
->phy
.ops
.acquire(hw
);
2467 ret_val
= e1e_rphy_locked(hw
, BM_PORT_GEN_CFG
, &phy_data
);
2470 ret_val
= e1e_wphy_locked(hw
, BM_PORT_GEN_CFG
, phy_data
& 0x00FF);
2474 /* set MSE higher to enable link to stay up when noise is high */
2475 ret_val
= e1000_write_emi_reg_locked(hw
, I82577_MSE_THRESHOLD
, 0x0034);
2477 hw
->phy
.ops
.release(hw
);
2483 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2484 * @hw: pointer to the HW structure
2486 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw
*hw
)
2492 ret_val
= hw
->phy
.ops
.acquire(hw
);
2495 ret_val
= e1000_enable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
2499 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2500 for (i
= 0; i
< (hw
->mac
.rar_entry_count
); i
++) {
2501 mac_reg
= er32(RAL(i
));
2502 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_L(i
),
2503 (u16
)(mac_reg
& 0xFFFF));
2504 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_M(i
),
2505 (u16
)((mac_reg
>> 16) & 0xFFFF));
2507 mac_reg
= er32(RAH(i
));
2508 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_H(i
),
2509 (u16
)(mac_reg
& 0xFFFF));
2510 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_CTRL(i
),
2511 (u16
)((mac_reg
& E1000_RAH_AV
)
2515 e1000_disable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
2518 hw
->phy
.ops
.release(hw
);
2522 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2524 * @hw: pointer to the HW structure
2525 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2527 s32
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
*hw
, bool enable
)
2534 if (hw
->mac
.type
< e1000_pch2lan
)
2537 /* disable Rx path while enabling/disabling workaround */
2538 e1e_rphy(hw
, PHY_REG(769, 20), &phy_reg
);
2539 ret_val
= e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
| BIT(14));
2544 /* Write Rx addresses (rar_entry_count for RAL/H, and
2545 * SHRAL/H) and initial CRC values to the MAC
2547 for (i
= 0; i
< hw
->mac
.rar_entry_count
; i
++) {
2548 u8 mac_addr
[ETH_ALEN
] = { 0 };
2549 u32 addr_high
, addr_low
;
2551 addr_high
= er32(RAH(i
));
2552 if (!(addr_high
& E1000_RAH_AV
))
2554 addr_low
= er32(RAL(i
));
2555 mac_addr
[0] = (addr_low
& 0xFF);
2556 mac_addr
[1] = ((addr_low
>> 8) & 0xFF);
2557 mac_addr
[2] = ((addr_low
>> 16) & 0xFF);
2558 mac_addr
[3] = ((addr_low
>> 24) & 0xFF);
2559 mac_addr
[4] = (addr_high
& 0xFF);
2560 mac_addr
[5] = ((addr_high
>> 8) & 0xFF);
2562 ew32(PCH_RAICC(i
), ~ether_crc_le(ETH_ALEN
, mac_addr
));
2565 /* Write Rx addresses to the PHY */
2566 e1000_copy_rx_addrs_to_phy_ich8lan(hw
);
2568 /* Enable jumbo frame workaround in the MAC */
2569 mac_reg
= er32(FFLT_DBG
);
2570 mac_reg
&= ~BIT(14);
2571 mac_reg
|= (7 << 15);
2572 ew32(FFLT_DBG
, mac_reg
);
2574 mac_reg
= er32(RCTL
);
2575 mac_reg
|= E1000_RCTL_SECRC
;
2576 ew32(RCTL
, mac_reg
);
2578 ret_val
= e1000e_read_kmrn_reg(hw
,
2579 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2583 ret_val
= e1000e_write_kmrn_reg(hw
,
2584 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2588 ret_val
= e1000e_read_kmrn_reg(hw
,
2589 E1000_KMRNCTRLSTA_HD_CTRL
,
2593 data
&= ~(0xF << 8);
2595 ret_val
= e1000e_write_kmrn_reg(hw
,
2596 E1000_KMRNCTRLSTA_HD_CTRL
,
2601 /* Enable jumbo frame workaround in the PHY */
2602 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
2603 data
&= ~(0x7F << 5);
2604 data
|= (0x37 << 5);
2605 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
2608 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
2610 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
2613 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
2614 data
&= ~(0x3FF << 2);
2615 data
|= (E1000_TX_PTR_GAP
<< 2);
2616 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
2619 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0xF100);
2622 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
2623 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
| BIT(10));
2627 /* Write MAC register values back to h/w defaults */
2628 mac_reg
= er32(FFLT_DBG
);
2629 mac_reg
&= ~(0xF << 14);
2630 ew32(FFLT_DBG
, mac_reg
);
2632 mac_reg
= er32(RCTL
);
2633 mac_reg
&= ~E1000_RCTL_SECRC
;
2634 ew32(RCTL
, mac_reg
);
2636 ret_val
= e1000e_read_kmrn_reg(hw
,
2637 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2641 ret_val
= e1000e_write_kmrn_reg(hw
,
2642 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2646 ret_val
= e1000e_read_kmrn_reg(hw
,
2647 E1000_KMRNCTRLSTA_HD_CTRL
,
2651 data
&= ~(0xF << 8);
2653 ret_val
= e1000e_write_kmrn_reg(hw
,
2654 E1000_KMRNCTRLSTA_HD_CTRL
,
2659 /* Write PHY register values back to h/w defaults */
2660 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
2661 data
&= ~(0x7F << 5);
2662 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
2665 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
2667 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
2670 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
2671 data
&= ~(0x3FF << 2);
2673 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
2676 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0x7E00);
2679 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
2680 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
& ~BIT(10));
2685 /* re-enable Rx path after enabling/disabling workaround */
2686 return e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
& ~BIT(14));
2690 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2691 * done after every PHY reset.
2693 static s32
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
2697 if (hw
->mac
.type
!= e1000_pch2lan
)
2700 /* Set MDIO slow mode before any other MDIO access */
2701 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
2705 ret_val
= hw
->phy
.ops
.acquire(hw
);
2708 /* set MSE higher to enable link to stay up when noise is high */
2709 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_MSE_THRESHOLD
, 0x0034);
2712 /* drop link after 5 times MSE threshold was reached */
2713 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_MSE_LINK_DOWN
, 0x0005);
2715 hw
->phy
.ops
.release(hw
);
2721 * e1000_k1_gig_workaround_lv - K1 Si workaround
2722 * @hw: pointer to the HW structure
2724 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2725 * Disable K1 in 1000Mbps and 100Mbps
2727 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
)
2732 if (hw
->mac
.type
!= e1000_pch2lan
)
2735 /* Set K1 beacon duration based on 10Mbs speed */
2736 ret_val
= e1e_rphy(hw
, HV_M_STATUS
, &status_reg
);
2740 if ((status_reg
& (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
))
2741 == (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
)) {
2743 (HV_M_STATUS_SPEED_1000
| HV_M_STATUS_SPEED_100
)) {
2746 /* LV 1G/100 Packet drop issue wa */
2747 ret_val
= e1e_rphy(hw
, HV_PM_CTRL
, &pm_phy_reg
);
2750 pm_phy_reg
&= ~HV_PM_CTRL_K1_ENABLE
;
2751 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, pm_phy_reg
);
2757 mac_reg
= er32(FEXTNVM4
);
2758 mac_reg
&= ~E1000_FEXTNVM4_BEACON_DURATION_MASK
;
2759 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_16USEC
;
2760 ew32(FEXTNVM4
, mac_reg
);
2768 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2769 * @hw: pointer to the HW structure
2770 * @gate: boolean set to true to gate, false to ungate
2772 * Gate/ungate the automatic PHY configuration via hardware; perform
2773 * the configuration via software instead.
2775 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
)
2779 if (hw
->mac
.type
< e1000_pch2lan
)
2782 extcnf_ctrl
= er32(EXTCNF_CTRL
);
2785 extcnf_ctrl
|= E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
2787 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
2789 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
2793 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2794 * @hw: pointer to the HW structure
2796 * Check the appropriate indication the MAC has finished configuring the
2797 * PHY after a software reset.
2799 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
)
2801 u32 data
, loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
2803 /* Wait for basic configuration completes before proceeding */
2805 data
= er32(STATUS
);
2806 data
&= E1000_STATUS_LAN_INIT_DONE
;
2807 usleep_range(100, 200);
2808 } while ((!data
) && --loop
);
2810 /* If basic configuration is incomplete before the above loop
2811 * count reaches 0, loading the configuration from NVM will
2812 * leave the PHY in a bad state possibly resulting in no link.
2815 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2817 /* Clear the Init Done bit for the next init event */
2818 data
= er32(STATUS
);
2819 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
2824 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2825 * @hw: pointer to the HW structure
2827 static s32
e1000_post_phy_reset_ich8lan(struct e1000_hw
*hw
)
2832 if (hw
->phy
.ops
.check_reset_block(hw
))
2835 /* Allow time for h/w to get to quiescent state after reset */
2836 usleep_range(10000, 20000);
2838 /* Perform any necessary post-reset workarounds */
2839 switch (hw
->mac
.type
) {
2841 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
2846 ret_val
= e1000_lv_phy_workarounds_ich8lan(hw
);
2854 /* Clear the host wakeup bit after lcd reset */
2855 if (hw
->mac
.type
>= e1000_pchlan
) {
2856 e1e_rphy(hw
, BM_PORT_GEN_CFG
, ®
);
2857 reg
&= ~BM_WUC_HOST_WU_BIT
;
2858 e1e_wphy(hw
, BM_PORT_GEN_CFG
, reg
);
2861 /* Configure the LCD with the extended configuration region in NVM */
2862 ret_val
= e1000_sw_lcd_config_ich8lan(hw
);
2866 /* Configure the LCD with the OEM bits in NVM */
2867 ret_val
= e1000_oem_bits_config_ich8lan(hw
, true);
2869 if (hw
->mac
.type
== e1000_pch2lan
) {
2870 /* Ungate automatic PHY configuration on non-managed 82579 */
2871 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
2872 usleep_range(10000, 20000);
2873 e1000_gate_hw_phy_config_ich8lan(hw
, false);
2876 /* Set EEE LPI Update Timer to 200usec */
2877 ret_val
= hw
->phy
.ops
.acquire(hw
);
2880 ret_val
= e1000_write_emi_reg_locked(hw
,
2881 I82579_LPI_UPDATE_TIMER
,
2883 hw
->phy
.ops
.release(hw
);
2890 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2891 * @hw: pointer to the HW structure
2894 * This is a function pointer entry point called by drivers
2895 * or other shared routines.
2897 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
2901 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2902 if ((hw
->mac
.type
== e1000_pch2lan
) &&
2903 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
2904 e1000_gate_hw_phy_config_ich8lan(hw
, true);
2906 ret_val
= e1000e_phy_hw_reset_generic(hw
);
2910 return e1000_post_phy_reset_ich8lan(hw
);
2914 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2915 * @hw: pointer to the HW structure
2916 * @active: true to enable LPLU, false to disable
2918 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2919 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2920 * the phy speed. This function will manually set the LPLU bit and restart
2921 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2922 * since it configures the same bit.
2924 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
)
2929 ret_val
= e1e_rphy(hw
, HV_OEM_BITS
, &oem_reg
);
2934 oem_reg
|= HV_OEM_BITS_LPLU
;
2936 oem_reg
&= ~HV_OEM_BITS_LPLU
;
2938 if (!hw
->phy
.ops
.check_reset_block(hw
))
2939 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
2941 return e1e_wphy(hw
, HV_OEM_BITS
, oem_reg
);
2945 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2946 * @hw: pointer to the HW structure
2947 * @active: true to enable LPLU, false to disable
2949 * Sets the LPLU D0 state according to the active flag. When
2950 * activating LPLU this function also disables smart speed
2951 * and vice versa. LPLU will not be activated unless the
2952 * device autonegotiation advertisement meets standards of
2953 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2954 * This is a function pointer entry point only called by
2955 * PHY setup routines.
2957 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
2959 struct e1000_phy_info
*phy
= &hw
->phy
;
2964 if (phy
->type
== e1000_phy_ife
)
2967 phy_ctrl
= er32(PHY_CTRL
);
2970 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
2971 ew32(PHY_CTRL
, phy_ctrl
);
2973 if (phy
->type
!= e1000_phy_igp_3
)
2976 /* Call gig speed drop workaround on LPLU before accessing
2979 if (hw
->mac
.type
== e1000_ich8lan
)
2980 e1000e_gig_downshift_workaround_ich8lan(hw
);
2982 /* When LPLU is enabled, we should disable SmartSpeed */
2983 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
2986 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2987 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
2991 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
2992 ew32(PHY_CTRL
, phy_ctrl
);
2994 if (phy
->type
!= e1000_phy_igp_3
)
2997 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2998 * during Dx states where the power conservation is most
2999 * important. During driver activity we should enable
3000 * SmartSpeed, so performance is maintained.
3002 if (phy
->smart_speed
== e1000_smart_speed_on
) {
3003 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3008 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
3009 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3013 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
3014 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3019 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
3020 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3031 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3032 * @hw: pointer to the HW structure
3033 * @active: true to enable LPLU, false to disable
3035 * Sets the LPLU D3 state according to the active flag. When
3036 * activating LPLU this function also disables smart speed
3037 * and vice versa. LPLU will not be activated unless the
3038 * device autonegotiation advertisement meets standards of
3039 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3040 * This is a function pointer entry point only called by
3041 * PHY setup routines.
3043 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
3045 struct e1000_phy_info
*phy
= &hw
->phy
;
3050 phy_ctrl
= er32(PHY_CTRL
);
3053 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
3054 ew32(PHY_CTRL
, phy_ctrl
);
3056 if (phy
->type
!= e1000_phy_igp_3
)
3059 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3060 * during Dx states where the power conservation is most
3061 * important. During driver activity we should enable
3062 * SmartSpeed, so performance is maintained.
3064 if (phy
->smart_speed
== e1000_smart_speed_on
) {
3065 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3070 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
3071 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3075 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
3076 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3081 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
3082 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
3087 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
3088 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
3089 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
3090 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
3091 ew32(PHY_CTRL
, phy_ctrl
);
3093 if (phy
->type
!= e1000_phy_igp_3
)
3096 /* Call gig speed drop workaround on LPLU before accessing
3099 if (hw
->mac
.type
== e1000_ich8lan
)
3100 e1000e_gig_downshift_workaround_ich8lan(hw
);
3102 /* When LPLU is enabled, we should disable SmartSpeed */
3103 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
3107 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
3108 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
3115 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3116 * @hw: pointer to the HW structure
3117 * @bank: pointer to the variable that returns the active bank
3119 * Reads signature byte from the NVM using the flash access registers.
3120 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3122 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
3125 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3126 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
3127 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
3132 switch (hw
->mac
.type
) {
3135 bank1_offset
= nvm
->flash_bank_size
;
3136 act_offset
= E1000_ICH_NVM_SIG_WORD
;
3138 /* set bank to 0 in case flash read fails */
3142 ret_val
= e1000_read_flash_dword_ich8lan(hw
, act_offset
,
3146 sig_byte
= (u8
)((nvm_dword
& 0xFF00) >> 8);
3147 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
3148 E1000_ICH_NVM_SIG_VALUE
) {
3154 ret_val
= e1000_read_flash_dword_ich8lan(hw
, act_offset
+
3159 sig_byte
= (u8
)((nvm_dword
& 0xFF00) >> 8);
3160 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
3161 E1000_ICH_NVM_SIG_VALUE
) {
3166 e_dbg("ERROR: No valid NVM bank present\n");
3167 return -E1000_ERR_NVM
;
3171 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
3172 E1000_EECD_SEC1VAL_VALID_MASK
) {
3173 if (eecd
& E1000_EECD_SEC1VAL
)
3180 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3183 /* set bank to 0 in case flash read fails */
3187 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
3191 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
3192 E1000_ICH_NVM_SIG_VALUE
) {
3198 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
3203 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
3204 E1000_ICH_NVM_SIG_VALUE
) {
3209 e_dbg("ERROR: No valid NVM bank present\n");
3210 return -E1000_ERR_NVM
;
3215 * e1000_read_nvm_spt - NVM access for SPT
3216 * @hw: pointer to the HW structure
3217 * @offset: The offset (in bytes) of the word(s) to read.
3218 * @words: Size of data to read in words.
3219 * @data: pointer to the word(s) to read at offset.
3221 * Reads a word(s) from the NVM
3223 static s32
e1000_read_nvm_spt(struct e1000_hw
*hw
, u16 offset
, u16 words
,
3226 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3227 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3235 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
3237 e_dbg("nvm parameter(s) out of bounds\n");
3238 ret_val
= -E1000_ERR_NVM
;
3242 nvm
->ops
.acquire(hw
);
3244 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
3246 e_dbg("Could not detect valid bank, assuming bank 0\n");
3250 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
3251 act_offset
+= offset
;
3255 for (i
= 0; i
< words
; i
+= 2) {
3256 if (words
- i
== 1) {
3257 if (dev_spec
->shadow_ram
[offset
+ i
].modified
) {
3259 dev_spec
->shadow_ram
[offset
+ i
].value
;
3261 offset_to_read
= act_offset
+ i
-
3262 ((act_offset
+ i
) % 2);
3264 e1000_read_flash_dword_ich8lan(hw
,
3269 if ((act_offset
+ i
) % 2 == 0)
3270 data
[i
] = (u16
)(dword
& 0xFFFF);
3272 data
[i
] = (u16
)((dword
>> 16) & 0xFFFF);
3275 offset_to_read
= act_offset
+ i
;
3276 if (!(dev_spec
->shadow_ram
[offset
+ i
].modified
) ||
3277 !(dev_spec
->shadow_ram
[offset
+ i
+ 1].modified
)) {
3279 e1000_read_flash_dword_ich8lan(hw
,
3285 if (dev_spec
->shadow_ram
[offset
+ i
].modified
)
3287 dev_spec
->shadow_ram
[offset
+ i
].value
;
3289 data
[i
] = (u16
)(dword
& 0xFFFF);
3290 if (dev_spec
->shadow_ram
[offset
+ i
].modified
)
3292 dev_spec
->shadow_ram
[offset
+ i
+ 1].value
;
3294 data
[i
+ 1] = (u16
)(dword
>> 16 & 0xFFFF);
3298 nvm
->ops
.release(hw
);
3302 e_dbg("NVM read error: %d\n", ret_val
);
3308 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3309 * @hw: pointer to the HW structure
3310 * @offset: The offset (in bytes) of the word(s) to read.
3311 * @words: Size of data to read in words
3312 * @data: Pointer to the word(s) to read at offset.
3314 * Reads a word(s) from the NVM using the flash access registers.
3316 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
3319 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3320 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3326 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
3328 e_dbg("nvm parameter(s) out of bounds\n");
3329 ret_val
= -E1000_ERR_NVM
;
3333 nvm
->ops
.acquire(hw
);
3335 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
3337 e_dbg("Could not detect valid bank, assuming bank 0\n");
3341 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
3342 act_offset
+= offset
;
3345 for (i
= 0; i
< words
; i
++) {
3346 if (dev_spec
->shadow_ram
[offset
+ i
].modified
) {
3347 data
[i
] = dev_spec
->shadow_ram
[offset
+ i
].value
;
3349 ret_val
= e1000_read_flash_word_ich8lan(hw
,
3358 nvm
->ops
.release(hw
);
3362 e_dbg("NVM read error: %d\n", ret_val
);
3368 * e1000_flash_cycle_init_ich8lan - Initialize flash
3369 * @hw: pointer to the HW structure
3371 * This function does initial flash setup so that a new read/write/erase cycle
3374 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
3376 union ich8_hws_flash_status hsfsts
;
3377 s32 ret_val
= -E1000_ERR_NVM
;
3379 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3381 /* Check if the flash descriptor is valid */
3382 if (!hsfsts
.hsf_status
.fldesvalid
) {
3383 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3384 return -E1000_ERR_NVM
;
3387 /* Clear FCERR and DAEL in hw status by writing 1 */
3388 hsfsts
.hsf_status
.flcerr
= 1;
3389 hsfsts
.hsf_status
.dael
= 1;
3390 if (hw
->mac
.type
>= e1000_pch_spt
)
3391 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
& 0xFFFF);
3393 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
3395 /* Either we should have a hardware SPI cycle in progress
3396 * bit to check against, in order to start a new cycle or
3397 * FDONE bit should be changed in the hardware so that it
3398 * is 1 after hardware reset, which can then be used as an
3399 * indication whether a cycle is in progress or has been
3403 if (!hsfsts
.hsf_status
.flcinprog
) {
3404 /* There is no cycle running at present,
3405 * so we can start a cycle.
3406 * Begin by setting Flash Cycle Done.
3408 hsfsts
.hsf_status
.flcdone
= 1;
3409 if (hw
->mac
.type
>= e1000_pch_spt
)
3410 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
& 0xFFFF);
3412 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
3417 /* Otherwise poll for sometime so the current
3418 * cycle has a chance to end before giving up.
3420 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
3421 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3422 if (!hsfsts
.hsf_status
.flcinprog
) {
3429 /* Successful in waiting for previous cycle to timeout,
3430 * now set the Flash Cycle Done.
3432 hsfsts
.hsf_status
.flcdone
= 1;
3433 if (hw
->mac
.type
>= e1000_pch_spt
)
3434 ew32flash(ICH_FLASH_HSFSTS
,
3435 hsfsts
.regval
& 0xFFFF);
3437 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
3439 e_dbg("Flash controller busy, cannot get access\n");
3447 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3448 * @hw: pointer to the HW structure
3449 * @timeout: maximum time to wait for completion
3451 * This function starts a flash cycle and waits for its completion.
3453 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
3455 union ich8_hws_flash_ctrl hsflctl
;
3456 union ich8_hws_flash_status hsfsts
;
3459 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3460 if (hw
->mac
.type
>= e1000_pch_spt
)
3461 hsflctl
.regval
= er32flash(ICH_FLASH_HSFSTS
) >> 16;
3463 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
3464 hsflctl
.hsf_ctrl
.flcgo
= 1;
3466 if (hw
->mac
.type
>= e1000_pch_spt
)
3467 ew32flash(ICH_FLASH_HSFSTS
, hsflctl
.regval
<< 16);
3469 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
3471 /* wait till FDONE bit is set to 1 */
3473 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3474 if (hsfsts
.hsf_status
.flcdone
)
3477 } while (i
++ < timeout
);
3479 if (hsfsts
.hsf_status
.flcdone
&& !hsfsts
.hsf_status
.flcerr
)
3482 return -E1000_ERR_NVM
;
3486 * e1000_read_flash_dword_ich8lan - Read dword from flash
3487 * @hw: pointer to the HW structure
3488 * @offset: offset to data location
3489 * @data: pointer to the location for storing the data
3491 * Reads the flash dword at offset into data. Offset is converted
3492 * to bytes before read.
3494 static s32
e1000_read_flash_dword_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3497 /* Must convert word offset into bytes. */
3499 return e1000_read_flash_data32_ich8lan(hw
, offset
, data
);
3503 * e1000_read_flash_word_ich8lan - Read word from flash
3504 * @hw: pointer to the HW structure
3505 * @offset: offset to data location
3506 * @data: pointer to the location for storing the data
3508 * Reads the flash word at offset into data. Offset is converted
3509 * to bytes before read.
3511 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3514 /* Must convert offset into bytes. */
3517 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
3521 * e1000_read_flash_byte_ich8lan - Read byte from flash
3522 * @hw: pointer to the HW structure
3523 * @offset: The offset of the byte to read.
3524 * @data: Pointer to a byte to store the value read.
3526 * Reads a single byte from the NVM using the flash access registers.
3528 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3534 /* In SPT, only 32 bits access is supported,
3535 * so this function should not be called.
3537 if (hw
->mac
.type
>= e1000_pch_spt
)
3538 return -E1000_ERR_NVM
;
3540 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
3551 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3552 * @hw: pointer to the HW structure
3553 * @offset: The offset (in bytes) of the byte or word to read.
3554 * @size: Size of data to read, 1=byte 2=word
3555 * @data: Pointer to the word to store the value read.
3557 * Reads a byte or word from the NVM using the flash access registers.
3559 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3562 union ich8_hws_flash_status hsfsts
;
3563 union ich8_hws_flash_ctrl hsflctl
;
3564 u32 flash_linear_addr
;
3566 s32 ret_val
= -E1000_ERR_NVM
;
3569 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
3570 return -E1000_ERR_NVM
;
3572 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
3573 hw
->nvm
.flash_base_addr
);
3578 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
3582 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
3583 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3584 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
3585 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
3586 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
3588 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
3591 e1000_flash_cycle_ich8lan(hw
,
3592 ICH_FLASH_READ_COMMAND_TIMEOUT
);
3594 /* Check if FCERR is set to 1, if set to 1, clear it
3595 * and try the whole sequence a few more times, else
3596 * read in (shift in) the Flash Data0, the order is
3597 * least significant byte first msb to lsb
3600 flash_data
= er32flash(ICH_FLASH_FDATA0
);
3602 *data
= (u8
)(flash_data
& 0x000000FF);
3604 *data
= (u16
)(flash_data
& 0x0000FFFF);
3607 /* If we've gotten here, then things are probably
3608 * completely hosed, but if the error condition is
3609 * detected, it won't hurt to give it another try...
3610 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3612 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3613 if (hsfsts
.hsf_status
.flcerr
) {
3614 /* Repeat for some time before giving up. */
3616 } else if (!hsfsts
.hsf_status
.flcdone
) {
3617 e_dbg("Timeout error - flash cycle did not complete.\n");
3621 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
3627 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3628 * @hw: pointer to the HW structure
3629 * @offset: The offset (in bytes) of the dword to read.
3630 * @data: Pointer to the dword to store the value read.
3632 * Reads a byte or word from the NVM using the flash access registers.
3635 static s32
e1000_read_flash_data32_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3638 union ich8_hws_flash_status hsfsts
;
3639 union ich8_hws_flash_ctrl hsflctl
;
3640 u32 flash_linear_addr
;
3641 s32 ret_val
= -E1000_ERR_NVM
;
3644 if (offset
> ICH_FLASH_LINEAR_ADDR_MASK
|| hw
->mac
.type
< e1000_pch_spt
)
3645 return -E1000_ERR_NVM
;
3646 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
3647 hw
->nvm
.flash_base_addr
);
3652 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
3655 /* In SPT, This register is in Lan memory space, not flash.
3656 * Therefore, only 32 bit access is supported
3658 hsflctl
.regval
= er32flash(ICH_FLASH_HSFSTS
) >> 16;
3660 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3661 hsflctl
.hsf_ctrl
.fldbcount
= sizeof(u32
) - 1;
3662 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
3663 /* In SPT, This register is in Lan memory space, not flash.
3664 * Therefore, only 32 bit access is supported
3666 ew32flash(ICH_FLASH_HSFSTS
, (u32
)hsflctl
.regval
<< 16);
3667 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
3670 e1000_flash_cycle_ich8lan(hw
,
3671 ICH_FLASH_READ_COMMAND_TIMEOUT
);
3673 /* Check if FCERR is set to 1, if set to 1, clear it
3674 * and try the whole sequence a few more times, else
3675 * read in (shift in) the Flash Data0, the order is
3676 * least significant byte first msb to lsb
3679 *data
= er32flash(ICH_FLASH_FDATA0
);
3682 /* If we've gotten here, then things are probably
3683 * completely hosed, but if the error condition is
3684 * detected, it won't hurt to give it another try...
3685 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3687 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3688 if (hsfsts
.hsf_status
.flcerr
) {
3689 /* Repeat for some time before giving up. */
3691 } else if (!hsfsts
.hsf_status
.flcdone
) {
3692 e_dbg("Timeout error - flash cycle did not complete.\n");
3696 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
3702 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3703 * @hw: pointer to the HW structure
3704 * @offset: The offset (in bytes) of the word(s) to write.
3705 * @words: Size of data to write in words
3706 * @data: Pointer to the word(s) to write at offset.
3708 * Writes a byte or word to the NVM using the flash access registers.
3710 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
3713 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3714 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3717 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
3719 e_dbg("nvm parameter(s) out of bounds\n");
3720 return -E1000_ERR_NVM
;
3723 nvm
->ops
.acquire(hw
);
3725 for (i
= 0; i
< words
; i
++) {
3726 dev_spec
->shadow_ram
[offset
+ i
].modified
= true;
3727 dev_spec
->shadow_ram
[offset
+ i
].value
= data
[i
];
3730 nvm
->ops
.release(hw
);
3736 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3737 * @hw: pointer to the HW structure
3739 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3740 * which writes the checksum to the shadow ram. The changes in the shadow
3741 * ram are then committed to the EEPROM by processing each bank at a time
3742 * checking for the modified bit and writing only the pending changes.
3743 * After a successful commit, the shadow ram is cleared and is ready for
3746 static s32
e1000_update_nvm_checksum_spt(struct e1000_hw
*hw
)
3748 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3749 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3750 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
3754 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
3758 if (nvm
->type
!= e1000_nvm_flash_sw
)
3761 nvm
->ops
.acquire(hw
);
3763 /* We're writing to the opposite bank so if we're on bank 1,
3764 * write to bank 0 etc. We also need to erase the segment that
3765 * is going to be written
3767 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
3769 e_dbg("Could not detect valid bank, assuming bank 0\n");
3774 new_bank_offset
= nvm
->flash_bank_size
;
3775 old_bank_offset
= 0;
3776 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
3780 old_bank_offset
= nvm
->flash_bank_size
;
3781 new_bank_offset
= 0;
3782 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
3786 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
+= 2) {
3787 /* Determine whether to write the value stored
3788 * in the other NVM bank or a modified value stored
3791 ret_val
= e1000_read_flash_dword_ich8lan(hw
,
3792 i
+ old_bank_offset
,
3795 if (dev_spec
->shadow_ram
[i
].modified
) {
3796 dword
&= 0xffff0000;
3797 dword
|= (dev_spec
->shadow_ram
[i
].value
& 0xffff);
3799 if (dev_spec
->shadow_ram
[i
+ 1].modified
) {
3800 dword
&= 0x0000ffff;
3801 dword
|= ((dev_spec
->shadow_ram
[i
+ 1].value
& 0xffff)
3807 /* If the word is 0x13, then make sure the signature bits
3808 * (15:14) are 11b until the commit has completed.
3809 * This will allow us to write 10b which indicates the
3810 * signature is valid. We want to do this after the write
3811 * has completed so that we don't mark the segment valid
3812 * while the write is still in progress
3814 if (i
== E1000_ICH_NVM_SIG_WORD
- 1)
3815 dword
|= E1000_ICH_NVM_SIG_MASK
<< 16;
3817 /* Convert offset to bytes. */
3818 act_offset
= (i
+ new_bank_offset
) << 1;
3820 usleep_range(100, 200);
3822 /* Write the data to the new bank. Offset in words */
3823 act_offset
= i
+ new_bank_offset
;
3824 ret_val
= e1000_retry_write_flash_dword_ich8lan(hw
, act_offset
,
3830 /* Don't bother writing the segment valid bits if sector
3831 * programming failed.
3834 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3835 e_dbg("Flash commit failed.\n");
3839 /* Finally validate the new segment by setting bit 15:14
3840 * to 10b in word 0x13 , this can be done without an
3841 * erase as well since these bits are 11 to start with
3842 * and we need to change bit 14 to 0b
3844 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
3846 /*offset in words but we read dword */
3848 ret_val
= e1000_read_flash_dword_ich8lan(hw
, act_offset
, &dword
);
3853 dword
&= 0xBFFFFFFF;
3854 ret_val
= e1000_retry_write_flash_dword_ich8lan(hw
, act_offset
, dword
);
3859 /* And invalidate the previously valid segment by setting
3860 * its signature word (0x13) high_byte to 0b. This can be
3861 * done without an erase because flash erase sets all bits
3862 * to 1's. We can write 1's to 0's without an erase
3864 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
3866 /* offset in words but we read dword */
3867 act_offset
= old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
- 1;
3868 ret_val
= e1000_read_flash_dword_ich8lan(hw
, act_offset
, &dword
);
3873 dword
&= 0x00FFFFFF;
3874 ret_val
= e1000_retry_write_flash_dword_ich8lan(hw
, act_offset
, dword
);
3879 /* Great! Everything worked, we can now clear the cached entries. */
3880 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
3881 dev_spec
->shadow_ram
[i
].modified
= false;
3882 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
3886 nvm
->ops
.release(hw
);
3888 /* Reload the EEPROM, or else modifications will not appear
3889 * until after the next adapter reset.
3892 nvm
->ops
.reload(hw
);
3893 usleep_range(10000, 20000);
3898 e_dbg("NVM update error: %d\n", ret_val
);
3904 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3905 * @hw: pointer to the HW structure
3907 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3908 * which writes the checksum to the shadow ram. The changes in the shadow
3909 * ram are then committed to the EEPROM by processing each bank at a time
3910 * checking for the modified bit and writing only the pending changes.
3911 * After a successful commit, the shadow ram is cleared and is ready for
3914 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
3916 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3917 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3918 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
3922 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
3926 if (nvm
->type
!= e1000_nvm_flash_sw
)
3929 nvm
->ops
.acquire(hw
);
3931 /* We're writing to the opposite bank so if we're on bank 1,
3932 * write to bank 0 etc. We also need to erase the segment that
3933 * is going to be written
3935 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
3937 e_dbg("Could not detect valid bank, assuming bank 0\n");
3942 new_bank_offset
= nvm
->flash_bank_size
;
3943 old_bank_offset
= 0;
3944 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
3948 old_bank_offset
= nvm
->flash_bank_size
;
3949 new_bank_offset
= 0;
3950 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
3954 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
3955 if (dev_spec
->shadow_ram
[i
].modified
) {
3956 data
= dev_spec
->shadow_ram
[i
].value
;
3958 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
3965 /* If the word is 0x13, then make sure the signature bits
3966 * (15:14) are 11b until the commit has completed.
3967 * This will allow us to write 10b which indicates the
3968 * signature is valid. We want to do this after the write
3969 * has completed so that we don't mark the segment valid
3970 * while the write is still in progress
3972 if (i
== E1000_ICH_NVM_SIG_WORD
)
3973 data
|= E1000_ICH_NVM_SIG_MASK
;
3975 /* Convert offset to bytes. */
3976 act_offset
= (i
+ new_bank_offset
) << 1;
3978 usleep_range(100, 200);
3979 /* Write the bytes to the new bank. */
3980 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
3986 usleep_range(100, 200);
3987 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
3994 /* Don't bother writing the segment valid bits if sector
3995 * programming failed.
3998 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3999 e_dbg("Flash commit failed.\n");
4003 /* Finally validate the new segment by setting bit 15:14
4004 * to 10b in word 0x13 , this can be done without an
4005 * erase as well since these bits are 11 to start with
4006 * and we need to change bit 14 to 0b
4008 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
4009 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
4014 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
4020 /* And invalidate the previously valid segment by setting
4021 * its signature word (0x13) high_byte to 0b. This can be
4022 * done without an erase because flash erase sets all bits
4023 * to 1's. We can write 1's to 0's without an erase
4025 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
4026 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
4030 /* Great! Everything worked, we can now clear the cached entries. */
4031 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
4032 dev_spec
->shadow_ram
[i
].modified
= false;
4033 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
4037 nvm
->ops
.release(hw
);
4039 /* Reload the EEPROM, or else modifications will not appear
4040 * until after the next adapter reset.
4043 nvm
->ops
.reload(hw
);
4044 usleep_range(10000, 20000);
4049 e_dbg("NVM update error: %d\n", ret_val
);
4055 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4056 * @hw: pointer to the HW structure
4058 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4059 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4060 * calculated, in which case we need to calculate the checksum and set bit 6.
4062 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
4067 u16 valid_csum_mask
;
4069 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4070 * the checksum needs to be fixed. This bit is an indication that
4071 * the NVM was prepared by OEM software and did not calculate
4072 * the checksum...a likely scenario.
4074 switch (hw
->mac
.type
) {
4079 valid_csum_mask
= NVM_COMPAT_VALID_CSUM
;
4082 word
= NVM_FUTURE_INIT_WORD1
;
4083 valid_csum_mask
= NVM_FUTURE_INIT_WORD1_VALID_CSUM
;
4087 ret_val
= e1000_read_nvm(hw
, word
, 1, &data
);
4091 if (!(data
& valid_csum_mask
)) {
4092 data
|= valid_csum_mask
;
4093 ret_val
= e1000_write_nvm(hw
, word
, 1, &data
);
4096 ret_val
= e1000e_update_nvm_checksum(hw
);
4101 return e1000e_validate_nvm_checksum_generic(hw
);
4105 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4106 * @hw: pointer to the HW structure
4108 * To prevent malicious write/erase of the NVM, set it to be read-only
4109 * so that the hardware ignores all write/erase cycles of the NVM via
4110 * the flash control registers. The shadow-ram copy of the NVM will
4111 * still be updated, however any updates to this copy will not stick
4112 * across driver reloads.
4114 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
4116 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
4117 union ich8_flash_protected_range pr0
;
4118 union ich8_hws_flash_status hsfsts
;
4121 nvm
->ops
.acquire(hw
);
4123 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
4125 /* Write-protect GbE Sector of NVM */
4126 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
4127 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
4128 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
4129 pr0
.range
.wpe
= true;
4130 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
4132 /* Lock down a subset of GbE Flash Control Registers, e.g.
4133 * PR0 to prevent the write-protection from being lifted.
4134 * Once FLOCKDN is set, the registers protected by it cannot
4135 * be written until FLOCKDN is cleared by a hardware reset.
4137 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4138 hsfsts
.hsf_status
.flockdn
= true;
4139 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
4141 nvm
->ops
.release(hw
);
4145 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4146 * @hw: pointer to the HW structure
4147 * @offset: The offset (in bytes) of the byte/word to read.
4148 * @size: Size of data to read, 1=byte 2=word
4149 * @data: The byte(s) to write to the NVM.
4151 * Writes one/two bytes to the NVM using the flash access registers.
4153 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
4156 union ich8_hws_flash_status hsfsts
;
4157 union ich8_hws_flash_ctrl hsflctl
;
4158 u32 flash_linear_addr
;
4163 if (hw
->mac
.type
>= e1000_pch_spt
) {
4164 if (size
!= 4 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
4165 return -E1000_ERR_NVM
;
4167 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
4168 return -E1000_ERR_NVM
;
4171 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
4172 hw
->nvm
.flash_base_addr
);
4177 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
4180 /* In SPT, This register is in Lan memory space, not
4181 * flash. Therefore, only 32 bit access is supported
4183 if (hw
->mac
.type
>= e1000_pch_spt
)
4184 hsflctl
.regval
= er32flash(ICH_FLASH_HSFSTS
) >> 16;
4186 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
4188 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4189 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
4190 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
4191 /* In SPT, This register is in Lan memory space,
4192 * not flash. Therefore, only 32 bit access is
4195 if (hw
->mac
.type
>= e1000_pch_spt
)
4196 ew32flash(ICH_FLASH_HSFSTS
, hsflctl
.regval
<< 16);
4198 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
4200 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
4203 flash_data
= (u32
)data
& 0x00FF;
4205 flash_data
= (u32
)data
;
4207 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
4209 /* check if FCERR is set to 1 , if set to 1, clear it
4210 * and try the whole sequence a few more times else done
4213 e1000_flash_cycle_ich8lan(hw
,
4214 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
4218 /* If we're here, then things are most likely
4219 * completely hosed, but if the error condition
4220 * is detected, it won't hurt to give it another
4221 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4223 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4224 if (hsfsts
.hsf_status
.flcerr
)
4225 /* Repeat for some time before giving up. */
4227 if (!hsfsts
.hsf_status
.flcdone
) {
4228 e_dbg("Timeout error - flash cycle did not complete.\n");
4231 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
4237 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4238 * @hw: pointer to the HW structure
4239 * @offset: The offset (in bytes) of the dwords to read.
4240 * @data: The 4 bytes to write to the NVM.
4242 * Writes one/two/four bytes to the NVM using the flash access registers.
4244 static s32
e1000_write_flash_data32_ich8lan(struct e1000_hw
*hw
, u32 offset
,
4247 union ich8_hws_flash_status hsfsts
;
4248 union ich8_hws_flash_ctrl hsflctl
;
4249 u32 flash_linear_addr
;
4253 if (hw
->mac
.type
>= e1000_pch_spt
) {
4254 if (offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
4255 return -E1000_ERR_NVM
;
4257 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
4258 hw
->nvm
.flash_base_addr
);
4262 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
4266 /* In SPT, This register is in Lan memory space, not
4267 * flash. Therefore, only 32 bit access is supported
4269 if (hw
->mac
.type
>= e1000_pch_spt
)
4270 hsflctl
.regval
= er32flash(ICH_FLASH_HSFSTS
)
4273 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
4275 hsflctl
.hsf_ctrl
.fldbcount
= sizeof(u32
) - 1;
4276 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
4278 /* In SPT, This register is in Lan memory space,
4279 * not flash. Therefore, only 32 bit access is
4282 if (hw
->mac
.type
>= e1000_pch_spt
)
4283 ew32flash(ICH_FLASH_HSFSTS
, hsflctl
.regval
<< 16);
4285 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
4287 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
4289 ew32flash(ICH_FLASH_FDATA0
, data
);
4291 /* check if FCERR is set to 1 , if set to 1, clear it
4292 * and try the whole sequence a few more times else done
4295 e1000_flash_cycle_ich8lan(hw
,
4296 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
4301 /* If we're here, then things are most likely
4302 * completely hosed, but if the error condition
4303 * is detected, it won't hurt to give it another
4304 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4306 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4308 if (hsfsts
.hsf_status
.flcerr
)
4309 /* Repeat for some time before giving up. */
4311 if (!hsfsts
.hsf_status
.flcdone
) {
4312 e_dbg("Timeout error - flash cycle did not complete.\n");
4315 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
4321 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4322 * @hw: pointer to the HW structure
4323 * @offset: The index of the byte to read.
4324 * @data: The byte to write to the NVM.
4326 * Writes a single byte to the NVM using the flash access registers.
4328 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
4331 u16 word
= (u16
)data
;
4333 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
4337 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4338 * @hw: pointer to the HW structure
4339 * @offset: The offset of the word to write.
4340 * @dword: The dword to write to the NVM.
4342 * Writes a single dword to the NVM using the flash access registers.
4343 * Goes through a retry algorithm before giving up.
4345 static s32
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw
*hw
,
4346 u32 offset
, u32 dword
)
4349 u16 program_retries
;
4351 /* Must convert word offset into bytes. */
4353 ret_val
= e1000_write_flash_data32_ich8lan(hw
, offset
, dword
);
4357 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
4358 e_dbg("Retrying Byte %8.8X at offset %u\n", dword
, offset
);
4359 usleep_range(100, 200);
4360 ret_val
= e1000_write_flash_data32_ich8lan(hw
, offset
, dword
);
4364 if (program_retries
== 100)
4365 return -E1000_ERR_NVM
;
4371 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4372 * @hw: pointer to the HW structure
4373 * @offset: The offset of the byte to write.
4374 * @byte: The byte to write to the NVM.
4376 * Writes a single byte to the NVM using the flash access registers.
4377 * Goes through a retry algorithm before giving up.
4379 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
4380 u32 offset
, u8 byte
)
4383 u16 program_retries
;
4385 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
4389 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
4390 e_dbg("Retrying Byte %2.2X at offset %u\n", byte
, offset
);
4391 usleep_range(100, 200);
4392 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
4396 if (program_retries
== 100)
4397 return -E1000_ERR_NVM
;
4403 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4404 * @hw: pointer to the HW structure
4405 * @bank: 0 for first bank, 1 for second bank, etc.
4407 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4408 * bank N is 4096 * N + flash_reg_addr.
4410 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
4412 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
4413 union ich8_hws_flash_status hsfsts
;
4414 union ich8_hws_flash_ctrl hsflctl
;
4415 u32 flash_linear_addr
;
4416 /* bank size is in 16bit words - adjust to bytes */
4417 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
4420 s32 j
, iteration
, sector_size
;
4422 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4424 /* Determine HW Sector size: Read BERASE bits of hw flash status
4426 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4427 * consecutive sectors. The start index for the nth Hw sector
4428 * can be calculated as = bank * 4096 + n * 256
4429 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4430 * The start index for the nth Hw sector can be calculated
4432 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4433 * (ich9 only, otherwise error condition)
4434 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4436 switch (hsfsts
.hsf_status
.berasesz
) {
4438 /* Hw sector size 256 */
4439 sector_size
= ICH_FLASH_SEG_SIZE_256
;
4440 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
4443 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
4447 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
4451 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
4455 return -E1000_ERR_NVM
;
4458 /* Start with the base address, then add the sector offset. */
4459 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
4460 flash_linear_addr
+= (bank
) ? flash_bank_size
: 0;
4462 for (j
= 0; j
< iteration
; j
++) {
4464 u32 timeout
= ICH_FLASH_ERASE_COMMAND_TIMEOUT
;
4467 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
4471 /* Write a value 11 (block Erase) in Flash
4472 * Cycle field in hw flash control
4474 if (hw
->mac
.type
>= e1000_pch_spt
)
4476 er32flash(ICH_FLASH_HSFSTS
) >> 16;
4478 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
4480 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
4481 if (hw
->mac
.type
>= e1000_pch_spt
)
4482 ew32flash(ICH_FLASH_HSFSTS
,
4483 hsflctl
.regval
<< 16);
4485 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
4487 /* Write the last 24 bits of an index within the
4488 * block into Flash Linear address field in Flash
4491 flash_linear_addr
+= (j
* sector_size
);
4492 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
4494 ret_val
= e1000_flash_cycle_ich8lan(hw
, timeout
);
4498 /* Check if FCERR is set to 1. If 1,
4499 * clear it and try the whole sequence
4500 * a few more times else Done
4502 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
4503 if (hsfsts
.hsf_status
.flcerr
)
4504 /* repeat for some time before giving up */
4506 else if (!hsfsts
.hsf_status
.flcdone
)
4508 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
4515 * e1000_valid_led_default_ich8lan - Set the default LED settings
4516 * @hw: pointer to the HW structure
4517 * @data: Pointer to the LED settings
4519 * Reads the LED default settings from the NVM to data. If the NVM LED
4520 * settings is all 0's or F's, set the LED default to a valid LED default
4523 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
4527 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
4529 e_dbg("NVM Read Error\n");
4533 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
)
4534 *data
= ID_LED_DEFAULT_ICH8LAN
;
4540 * e1000_id_led_init_pchlan - store LED configurations
4541 * @hw: pointer to the HW structure
4543 * PCH does not control LEDs via the LEDCTL register, rather it uses
4544 * the PHY LED configuration register.
4546 * PCH also does not have an "always on" or "always off" mode which
4547 * complicates the ID feature. Instead of using the "on" mode to indicate
4548 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4549 * use "link_up" mode. The LEDs will still ID on request if there is no
4550 * link based on logic in e1000_led_[on|off]_pchlan().
4552 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
4554 struct e1000_mac_info
*mac
= &hw
->mac
;
4556 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
4557 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
4558 u16 data
, i
, temp
, shift
;
4560 /* Get default ID LED modes */
4561 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
4565 mac
->ledctl_default
= er32(LEDCTL
);
4566 mac
->ledctl_mode1
= mac
->ledctl_default
;
4567 mac
->ledctl_mode2
= mac
->ledctl_default
;
4569 for (i
= 0; i
< 4; i
++) {
4570 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
4573 case ID_LED_ON1_DEF2
:
4574 case ID_LED_ON1_ON2
:
4575 case ID_LED_ON1_OFF2
:
4576 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
4577 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
4579 case ID_LED_OFF1_DEF2
:
4580 case ID_LED_OFF1_ON2
:
4581 case ID_LED_OFF1_OFF2
:
4582 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
4583 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
4590 case ID_LED_DEF1_ON2
:
4591 case ID_LED_ON1_ON2
:
4592 case ID_LED_OFF1_ON2
:
4593 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
4594 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
4596 case ID_LED_DEF1_OFF2
:
4597 case ID_LED_ON1_OFF2
:
4598 case ID_LED_OFF1_OFF2
:
4599 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
4600 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
4612 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4613 * @hw: pointer to the HW structure
4615 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4616 * register, so the the bus width is hard coded.
4618 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
4620 struct e1000_bus_info
*bus
= &hw
->bus
;
4623 ret_val
= e1000e_get_bus_info_pcie(hw
);
4625 /* ICH devices are "PCI Express"-ish. They have
4626 * a configuration space, but do not contain
4627 * PCI Express Capability registers, so bus width
4628 * must be hardcoded.
4630 if (bus
->width
== e1000_bus_width_unknown
)
4631 bus
->width
= e1000_bus_width_pcie_x1
;
4637 * e1000_reset_hw_ich8lan - Reset the hardware
4638 * @hw: pointer to the HW structure
4640 * Does a full reset of the hardware which includes a reset of the PHY and
4643 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
4645 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
4650 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4651 * on the last TLP read/write transaction when MAC is reset.
4653 ret_val
= e1000e_disable_pcie_master(hw
);
4655 e_dbg("PCI-E Master disable polling has failed.\n");
4657 e_dbg("Masking off all interrupts\n");
4658 ew32(IMC
, 0xffffffff);
4660 /* Disable the Transmit and Receive units. Then delay to allow
4661 * any pending transactions to complete before we hit the MAC
4662 * with the global reset.
4665 ew32(TCTL
, E1000_TCTL_PSP
);
4668 usleep_range(10000, 20000);
4670 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4671 if (hw
->mac
.type
== e1000_ich8lan
) {
4672 /* Set Tx and Rx buffer allocation to 8k apiece. */
4673 ew32(PBA
, E1000_PBA_8K
);
4674 /* Set Packet Buffer Size to 16k. */
4675 ew32(PBS
, E1000_PBS_16K
);
4678 if (hw
->mac
.type
== e1000_pchlan
) {
4679 /* Save the NVM K1 bit setting */
4680 ret_val
= e1000_read_nvm(hw
, E1000_NVM_K1_CONFIG
, 1, &kum_cfg
);
4684 if (kum_cfg
& E1000_NVM_K1_ENABLE
)
4685 dev_spec
->nvm_k1_enabled
= true;
4687 dev_spec
->nvm_k1_enabled
= false;
4692 if (!hw
->phy
.ops
.check_reset_block(hw
)) {
4693 /* Full-chip reset requires MAC and PHY reset at the same
4694 * time to make sure the interface between MAC and the
4695 * external PHY is reset.
4697 ctrl
|= E1000_CTRL_PHY_RST
;
4699 /* Gate automatic PHY configuration by hardware on
4702 if ((hw
->mac
.type
== e1000_pch2lan
) &&
4703 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
4704 e1000_gate_hw_phy_config_ich8lan(hw
, true);
4706 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
4707 e_dbg("Issuing a global reset to ich8lan\n");
4708 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
4709 /* cannot issue a flush here because it hangs the hardware */
4712 /* Set Phy Config Counter to 50msec */
4713 if (hw
->mac
.type
== e1000_pch2lan
) {
4714 reg
= er32(FEXTNVM3
);
4715 reg
&= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK
;
4716 reg
|= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
;
4717 ew32(FEXTNVM3
, reg
);
4721 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
4723 if (ctrl
& E1000_CTRL_PHY_RST
) {
4724 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
4728 ret_val
= e1000_post_phy_reset_ich8lan(hw
);
4733 /* For PCH, this write will make sure that any noise
4734 * will be detected as a CRC error and be dropped rather than show up
4735 * as a bad packet to the DMA engine.
4737 if (hw
->mac
.type
== e1000_pchlan
)
4738 ew32(CRC_OFFSET
, 0x65656565);
4740 ew32(IMC
, 0xffffffff);
4743 reg
= er32(KABGTXD
);
4744 reg
|= E1000_KABGTXD_BGSQLBIAS
;
4751 * e1000_init_hw_ich8lan - Initialize the hardware
4752 * @hw: pointer to the HW structure
4754 * Prepares the hardware for transmit and receive by doing the following:
4755 * - initialize hardware bits
4756 * - initialize LED identification
4757 * - setup receive address registers
4758 * - setup flow control
4759 * - setup transmit descriptors
4760 * - clear statistics
4762 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
4764 struct e1000_mac_info
*mac
= &hw
->mac
;
4765 u32 ctrl_ext
, txdctl
, snoop
;
4769 e1000_initialize_hw_bits_ich8lan(hw
);
4771 /* Initialize identification LED */
4772 ret_val
= mac
->ops
.id_led_init(hw
);
4773 /* An error is not fatal and we should not stop init due to this */
4775 e_dbg("Error initializing identification LED\n");
4777 /* Setup the receive address. */
4778 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
4780 /* Zero out the Multicast HASH table */
4781 e_dbg("Zeroing the MTA\n");
4782 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
4783 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
4785 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4786 * the ME. Disable wakeup by clearing the host wakeup bit.
4787 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4789 if (hw
->phy
.type
== e1000_phy_82578
) {
4790 e1e_rphy(hw
, BM_PORT_GEN_CFG
, &i
);
4791 i
&= ~BM_WUC_HOST_WU_BIT
;
4792 e1e_wphy(hw
, BM_PORT_GEN_CFG
, i
);
4793 ret_val
= e1000_phy_hw_reset_ich8lan(hw
);
4798 /* Setup link and flow control */
4799 ret_val
= mac
->ops
.setup_link(hw
);
4801 /* Set the transmit descriptor write-back policy for both queues */
4802 txdctl
= er32(TXDCTL(0));
4803 txdctl
= ((txdctl
& ~E1000_TXDCTL_WTHRESH
) |
4804 E1000_TXDCTL_FULL_TX_DESC_WB
);
4805 txdctl
= ((txdctl
& ~E1000_TXDCTL_PTHRESH
) |
4806 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
);
4807 ew32(TXDCTL(0), txdctl
);
4808 txdctl
= er32(TXDCTL(1));
4809 txdctl
= ((txdctl
& ~E1000_TXDCTL_WTHRESH
) |
4810 E1000_TXDCTL_FULL_TX_DESC_WB
);
4811 txdctl
= ((txdctl
& ~E1000_TXDCTL_PTHRESH
) |
4812 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
);
4813 ew32(TXDCTL(1), txdctl
);
4815 /* ICH8 has opposite polarity of no_snoop bits.
4816 * By default, we should use snoop behavior.
4818 if (mac
->type
== e1000_ich8lan
)
4819 snoop
= PCIE_ICH8_SNOOP_ALL
;
4821 snoop
= (u32
)~(PCIE_NO_SNOOP_ALL
);
4822 e1000e_set_pcie_no_snoop(hw
, snoop
);
4824 ctrl_ext
= er32(CTRL_EXT
);
4825 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
4826 ew32(CTRL_EXT
, ctrl_ext
);
4828 /* Clear all of the statistics registers (clear on read). It is
4829 * important that we do this after we have tried to establish link
4830 * because the symbol error count will increment wildly if there
4833 e1000_clear_hw_cntrs_ich8lan(hw
);
4839 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4840 * @hw: pointer to the HW structure
4842 * Sets/Clears required hardware bits necessary for correctly setting up the
4843 * hardware for transmit and receive.
4845 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
4849 /* Extended Device Control */
4850 reg
= er32(CTRL_EXT
);
4852 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4853 if (hw
->mac
.type
>= e1000_pchlan
)
4854 reg
|= E1000_CTRL_EXT_PHYPDEN
;
4855 ew32(CTRL_EXT
, reg
);
4857 /* Transmit Descriptor Control 0 */
4858 reg
= er32(TXDCTL(0));
4860 ew32(TXDCTL(0), reg
);
4862 /* Transmit Descriptor Control 1 */
4863 reg
= er32(TXDCTL(1));
4865 ew32(TXDCTL(1), reg
);
4867 /* Transmit Arbitration Control 0 */
4868 reg
= er32(TARC(0));
4869 if (hw
->mac
.type
== e1000_ich8lan
)
4870 reg
|= BIT(28) | BIT(29);
4871 reg
|= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4874 /* Transmit Arbitration Control 1 */
4875 reg
= er32(TARC(1));
4876 if (er32(TCTL
) & E1000_TCTL_MULR
)
4880 reg
|= BIT(24) | BIT(26) | BIT(30);
4884 if (hw
->mac
.type
== e1000_ich8lan
) {
4890 /* work-around descriptor data corruption issue during nfs v2 udp
4891 * traffic, just disable the nfs filtering capability
4894 reg
|= (E1000_RFCTL_NFSW_DIS
| E1000_RFCTL_NFSR_DIS
);
4896 /* Disable IPv6 extension header parsing because some malformed
4897 * IPv6 headers can hang the Rx.
4899 if (hw
->mac
.type
== e1000_ich8lan
)
4900 reg
|= (E1000_RFCTL_IPV6_EX_DIS
| E1000_RFCTL_NEW_IPV6_EXT_DIS
);
4903 /* Enable ECC on Lynxpoint */
4904 if (hw
->mac
.type
>= e1000_pch_lpt
) {
4905 reg
= er32(PBECCSTS
);
4906 reg
|= E1000_PBECCSTS_ECC_ENABLE
;
4907 ew32(PBECCSTS
, reg
);
4910 reg
|= E1000_CTRL_MEHE
;
4916 * e1000_setup_link_ich8lan - Setup flow control and link settings
4917 * @hw: pointer to the HW structure
4919 * Determines which flow control settings to use, then configures flow
4920 * control. Calls the appropriate media-specific link configuration
4921 * function. Assuming the adapter has a valid link partner, a valid link
4922 * should be established. Assumes the hardware has previously been reset
4923 * and the transmitter and receiver are not enabled.
4925 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
4929 if (hw
->phy
.ops
.check_reset_block(hw
))
4932 /* ICH parts do not have a word in the NVM to determine
4933 * the default flow control setting, so we explicitly
4936 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
4937 /* Workaround h/w hang when Tx flow control enabled */
4938 if (hw
->mac
.type
== e1000_pchlan
)
4939 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
4941 hw
->fc
.requested_mode
= e1000_fc_full
;
4944 /* Save off the requested flow control mode for use later. Depending
4945 * on the link partner's capabilities, we may or may not use this mode.
4947 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
4949 e_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.current_mode
);
4951 /* Continue to configure the copper link. */
4952 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
4956 ew32(FCTTV
, hw
->fc
.pause_time
);
4957 if ((hw
->phy
.type
== e1000_phy_82578
) ||
4958 (hw
->phy
.type
== e1000_phy_82579
) ||
4959 (hw
->phy
.type
== e1000_phy_i217
) ||
4960 (hw
->phy
.type
== e1000_phy_82577
)) {
4961 ew32(FCRTV_PCH
, hw
->fc
.refresh_time
);
4963 ret_val
= e1e_wphy(hw
, PHY_REG(BM_PORT_CTRL_PAGE
, 27),
4969 return e1000e_set_fc_watermarks(hw
);
4973 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4974 * @hw: pointer to the HW structure
4976 * Configures the kumeran interface to the PHY to wait the appropriate time
4977 * when polling the PHY, then call the generic setup_copper_link to finish
4978 * configuring the copper link.
4980 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
4987 ctrl
|= E1000_CTRL_SLU
;
4988 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
4991 /* Set the mac to wait the maximum time between each iteration
4992 * and increase the max iterations when polling the phy;
4993 * this fixes erroneous timeouts at 10Mbps.
4995 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_TIMEOUTS
, 0xFFFF);
4998 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
5003 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
5008 switch (hw
->phy
.type
) {
5009 case e1000_phy_igp_3
:
5010 ret_val
= e1000e_copper_link_setup_igp(hw
);
5015 case e1000_phy_82578
:
5016 ret_val
= e1000e_copper_link_setup_m88(hw
);
5020 case e1000_phy_82577
:
5021 case e1000_phy_82579
:
5022 ret_val
= e1000_copper_link_setup_82577(hw
);
5027 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
5031 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
5033 switch (hw
->phy
.mdix
) {
5035 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
5038 reg_data
|= IFE_PMC_FORCE_MDIX
;
5042 reg_data
|= IFE_PMC_AUTO_MDIX
;
5045 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
5053 return e1000e_setup_copper_link(hw
);
5057 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5058 * @hw: pointer to the HW structure
5060 * Calls the PHY specific link setup function and then calls the
5061 * generic setup_copper_link to finish configuring the link for
5062 * Lynxpoint PCH devices
5064 static s32
e1000_setup_copper_link_pch_lpt(struct e1000_hw
*hw
)
5070 ctrl
|= E1000_CTRL_SLU
;
5071 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
5074 ret_val
= e1000_copper_link_setup_82577(hw
);
5078 return e1000e_setup_copper_link(hw
);
5082 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5083 * @hw: pointer to the HW structure
5084 * @speed: pointer to store current link speed
5085 * @duplex: pointer to store the current link duplex
5087 * Calls the generic get_speed_and_duplex to retrieve the current link
5088 * information and then calls the Kumeran lock loss workaround for links at
5091 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
5096 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
5100 if ((hw
->mac
.type
== e1000_ich8lan
) &&
5101 (hw
->phy
.type
== e1000_phy_igp_3
) && (*speed
== SPEED_1000
)) {
5102 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
5109 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5110 * @hw: pointer to the HW structure
5112 * Work-around for 82566 Kumeran PCS lock loss:
5113 * On link status change (i.e. PCI reset, speed change) and link is up and
5115 * 0) if workaround is optionally disabled do nothing
5116 * 1) wait 1ms for Kumeran link to come up
5117 * 2) check Kumeran Diagnostic register PCS lock loss bit
5118 * 3) if not set the link is locked (all is good), otherwise...
5120 * 5) repeat up to 10 times
5121 * Note: this is only called for IGP3 copper when speed is 1gb.
5123 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
5125 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
5131 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
5134 /* Make sure link is up before proceeding. If not just return.
5135 * Attempting this while link is negotiating fouled up link
5138 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
5142 for (i
= 0; i
< 10; i
++) {
5143 /* read once to clear */
5144 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
5147 /* and again to get new status */
5148 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
5152 /* check for PCS lock */
5153 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
5156 /* Issue PHY reset */
5157 e1000_phy_hw_reset(hw
);
5160 /* Disable GigE link negotiation */
5161 phy_ctrl
= er32(PHY_CTRL
);
5162 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
5163 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
5164 ew32(PHY_CTRL
, phy_ctrl
);
5166 /* Call gig speed drop workaround on Gig disable before accessing
5169 e1000e_gig_downshift_workaround_ich8lan(hw
);
5171 /* unable to acquire PCS lock */
5172 return -E1000_ERR_PHY
;
5176 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5177 * @hw: pointer to the HW structure
5178 * @state: boolean value used to set the current Kumeran workaround state
5180 * If ICH8, set the current Kumeran workaround state (enabled - true
5181 * /disabled - false).
5183 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
5186 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
5188 if (hw
->mac
.type
!= e1000_ich8lan
) {
5189 e_dbg("Workaround applies to ICH8 only.\n");
5193 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
5197 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5198 * @hw: pointer to the HW structure
5200 * Workaround for 82566 power-down on D3 entry:
5201 * 1) disable gigabit link
5202 * 2) write VR power-down enable
5204 * Continue if successful, else issue LCD reset and repeat
5206 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
5212 if (hw
->phy
.type
!= e1000_phy_igp_3
)
5215 /* Try the workaround twice (if needed) */
5218 reg
= er32(PHY_CTRL
);
5219 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
5220 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
5221 ew32(PHY_CTRL
, reg
);
5223 /* Call gig speed drop workaround on Gig disable before
5224 * accessing any PHY registers
5226 if (hw
->mac
.type
== e1000_ich8lan
)
5227 e1000e_gig_downshift_workaround_ich8lan(hw
);
5229 /* Write VR power-down enable */
5230 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
5231 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
5232 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
5234 /* Read it back and test */
5235 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
5236 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
5237 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
5240 /* Issue PHY reset and repeat at most one more time */
5242 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
5248 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5249 * @hw: pointer to the HW structure
5251 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5252 * LPLU, Gig disable, MDIC PHY reset):
5253 * 1) Set Kumeran Near-end loopback
5254 * 2) Clear Kumeran Near-end loopback
5255 * Should only be called for ICH8[m] devices with any 1G Phy.
5257 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
5262 if ((hw
->mac
.type
!= e1000_ich8lan
) || (hw
->phy
.type
== e1000_phy_ife
))
5265 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
5269 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
5270 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
5274 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
5275 e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
, reg_data
);
5279 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5280 * @hw: pointer to the HW structure
5282 * During S0 to Sx transition, it is possible the link remains at gig
5283 * instead of negotiating to a lower speed. Before going to Sx, set
5284 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5285 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5286 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5287 * needs to be written.
5288 * Parts that support (and are linked to a partner which support) EEE in
5289 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5290 * than 10Mbps w/o EEE.
5292 void e1000_suspend_workarounds_ich8lan(struct e1000_hw
*hw
)
5294 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
5298 phy_ctrl
= er32(PHY_CTRL
);
5299 phy_ctrl
|= E1000_PHY_CTRL_GBE_DISABLE
;
5301 if (hw
->phy
.type
== e1000_phy_i217
) {
5302 u16 phy_reg
, device_id
= hw
->adapter
->pdev
->device
;
5304 if ((device_id
== E1000_DEV_ID_PCH_LPTLP_I218_LM
) ||
5305 (device_id
== E1000_DEV_ID_PCH_LPTLP_I218_V
) ||
5306 (device_id
== E1000_DEV_ID_PCH_I218_LM3
) ||
5307 (device_id
== E1000_DEV_ID_PCH_I218_V3
) ||
5308 (hw
->mac
.type
>= e1000_pch_spt
)) {
5309 u32 fextnvm6
= er32(FEXTNVM6
);
5311 ew32(FEXTNVM6
, fextnvm6
& ~E1000_FEXTNVM6_REQ_PLL_CLK
);
5314 ret_val
= hw
->phy
.ops
.acquire(hw
);
5318 if (!dev_spec
->eee_disable
) {
5322 e1000_read_emi_reg_locked(hw
,
5323 I217_EEE_ADVERTISEMENT
,
5328 /* Disable LPLU if both link partners support 100BaseT
5329 * EEE and 100Full is advertised on both ends of the
5330 * link, and enable Auto Enable LPI since there will
5331 * be no driver to enable LPI while in Sx.
5333 if ((eee_advert
& I82579_EEE_100_SUPPORTED
) &&
5334 (dev_spec
->eee_lp_ability
&
5335 I82579_EEE_100_SUPPORTED
) &&
5336 (hw
->phy
.autoneg_advertised
& ADVERTISE_100_FULL
)) {
5337 phy_ctrl
&= ~(E1000_PHY_CTRL_D0A_LPLU
|
5338 E1000_PHY_CTRL_NOND0A_LPLU
);
5340 /* Set Auto Enable LPI after link up */
5342 I217_LPI_GPIO_CTRL
, &phy_reg
);
5343 phy_reg
|= I217_LPI_GPIO_CTRL_AUTO_EN_LPI
;
5345 I217_LPI_GPIO_CTRL
, phy_reg
);
5349 /* For i217 Intel Rapid Start Technology support,
5350 * when the system is going into Sx and no manageability engine
5351 * is present, the driver must configure proxy to reset only on
5352 * power good. LPI (Low Power Idle) state must also reset only
5353 * on power good, as well as the MTA (Multicast table array).
5354 * The SMBus release must also be disabled on LCD reset.
5356 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
5357 /* Enable proxy to reset only on power good. */
5358 e1e_rphy_locked(hw
, I217_PROXY_CTRL
, &phy_reg
);
5359 phy_reg
|= I217_PROXY_CTRL_AUTO_DISABLE
;
5360 e1e_wphy_locked(hw
, I217_PROXY_CTRL
, phy_reg
);
5362 /* Set bit enable LPI (EEE) to reset only on
5365 e1e_rphy_locked(hw
, I217_SxCTRL
, &phy_reg
);
5366 phy_reg
|= I217_SxCTRL_ENABLE_LPI_RESET
;
5367 e1e_wphy_locked(hw
, I217_SxCTRL
, phy_reg
);
5369 /* Disable the SMB release on LCD reset. */
5370 e1e_rphy_locked(hw
, I217_MEMPWR
, &phy_reg
);
5371 phy_reg
&= ~I217_MEMPWR_DISABLE_SMB_RELEASE
;
5372 e1e_wphy_locked(hw
, I217_MEMPWR
, phy_reg
);
5375 /* Enable MTA to reset for Intel Rapid Start Technology
5378 e1e_rphy_locked(hw
, I217_CGFREG
, &phy_reg
);
5379 phy_reg
|= I217_CGFREG_ENABLE_MTA_RESET
;
5380 e1e_wphy_locked(hw
, I217_CGFREG
, phy_reg
);
5383 hw
->phy
.ops
.release(hw
);
5386 ew32(PHY_CTRL
, phy_ctrl
);
5388 if (hw
->mac
.type
== e1000_ich8lan
)
5389 e1000e_gig_downshift_workaround_ich8lan(hw
);
5391 if (hw
->mac
.type
>= e1000_pchlan
) {
5392 e1000_oem_bits_config_ich8lan(hw
, false);
5394 /* Reset PHY to activate OEM bits on 82577/8 */
5395 if (hw
->mac
.type
== e1000_pchlan
)
5396 e1000e_phy_hw_reset_generic(hw
);
5398 ret_val
= hw
->phy
.ops
.acquire(hw
);
5401 e1000_write_smbus_addr(hw
);
5402 hw
->phy
.ops
.release(hw
);
5407 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5408 * @hw: pointer to the HW structure
5410 * During Sx to S0 transitions on non-managed devices or managed devices
5411 * on which PHY resets are not blocked, if the PHY registers cannot be
5412 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5414 * On i217, setup Intel Rapid Start Technology.
5416 void e1000_resume_workarounds_pchlan(struct e1000_hw
*hw
)
5420 if (hw
->mac
.type
< e1000_pch2lan
)
5423 ret_val
= e1000_init_phy_workarounds_pchlan(hw
);
5425 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val
);
5429 /* For i217 Intel Rapid Start Technology support when the system
5430 * is transitioning from Sx and no manageability engine is present
5431 * configure SMBus to restore on reset, disable proxy, and enable
5432 * the reset on MTA (Multicast table array).
5434 if (hw
->phy
.type
== e1000_phy_i217
) {
5437 ret_val
= hw
->phy
.ops
.acquire(hw
);
5439 e_dbg("Failed to setup iRST\n");
5443 /* Clear Auto Enable LPI after link up */
5444 e1e_rphy_locked(hw
, I217_LPI_GPIO_CTRL
, &phy_reg
);
5445 phy_reg
&= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI
;
5446 e1e_wphy_locked(hw
, I217_LPI_GPIO_CTRL
, phy_reg
);
5448 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
5449 /* Restore clear on SMB if no manageability engine
5452 ret_val
= e1e_rphy_locked(hw
, I217_MEMPWR
, &phy_reg
);
5455 phy_reg
|= I217_MEMPWR_DISABLE_SMB_RELEASE
;
5456 e1e_wphy_locked(hw
, I217_MEMPWR
, phy_reg
);
5459 e1e_wphy_locked(hw
, I217_PROXY_CTRL
, 0);
5461 /* Enable reset on MTA */
5462 ret_val
= e1e_rphy_locked(hw
, I217_CGFREG
, &phy_reg
);
5465 phy_reg
&= ~I217_CGFREG_ENABLE_MTA_RESET
;
5466 e1e_wphy_locked(hw
, I217_CGFREG
, phy_reg
);
5469 e_dbg("Error %d in resume workarounds\n", ret_val
);
5470 hw
->phy
.ops
.release(hw
);
5475 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5476 * @hw: pointer to the HW structure
5478 * Return the LED back to the default configuration.
5480 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
5482 if (hw
->phy
.type
== e1000_phy_ife
)
5483 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
5485 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
5490 * e1000_led_on_ich8lan - Turn LEDs on
5491 * @hw: pointer to the HW structure
5495 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
5497 if (hw
->phy
.type
== e1000_phy_ife
)
5498 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
5499 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
5501 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
5506 * e1000_led_off_ich8lan - Turn LEDs off
5507 * @hw: pointer to the HW structure
5509 * Turn off the LEDs.
5511 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
5513 if (hw
->phy
.type
== e1000_phy_ife
)
5514 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
5515 (IFE_PSCL_PROBE_MODE
|
5516 IFE_PSCL_PROBE_LEDS_OFF
));
5518 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
5523 * e1000_setup_led_pchlan - Configures SW controllable LED
5524 * @hw: pointer to the HW structure
5526 * This prepares the SW controllable LED for use.
5528 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
5530 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_mode1
);
5534 * e1000_cleanup_led_pchlan - Restore the default LED operation
5535 * @hw: pointer to the HW structure
5537 * Return the LED back to the default configuration.
5539 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
5541 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_default
);
5545 * e1000_led_on_pchlan - Turn LEDs on
5546 * @hw: pointer to the HW structure
5550 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
5552 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
5555 /* If no link, then turn LED on by setting the invert bit
5556 * for each LED that's mode is "link_up" in ledctl_mode2.
5558 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
5559 for (i
= 0; i
< 3; i
++) {
5560 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
5561 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
5562 E1000_LEDCTL_MODE_LINK_UP
)
5564 if (led
& E1000_PHY_LED0_IVRT
)
5565 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
5567 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
5571 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
5575 * e1000_led_off_pchlan - Turn LEDs off
5576 * @hw: pointer to the HW structure
5578 * Turn off the LEDs.
5580 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
5582 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
5585 /* If no link, then turn LED off by clearing the invert bit
5586 * for each LED that's mode is "link_up" in ledctl_mode1.
5588 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
5589 for (i
= 0; i
< 3; i
++) {
5590 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
5591 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
5592 E1000_LEDCTL_MODE_LINK_UP
)
5594 if (led
& E1000_PHY_LED0_IVRT
)
5595 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
5597 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
5601 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
5605 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5606 * @hw: pointer to the HW structure
5608 * Read appropriate register for the config done bit for completion status
5609 * and configure the PHY through s/w for EEPROM-less parts.
5611 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5612 * config done bit, so only an error is logged and continues. If we were
5613 * to return with error, EEPROM-less silicon would not be able to be reset
5616 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
5622 e1000e_get_cfg_done_generic(hw
);
5624 /* Wait for indication from h/w that it has completed basic config */
5625 if (hw
->mac
.type
>= e1000_ich10lan
) {
5626 e1000_lan_init_done_ich8lan(hw
);
5628 ret_val
= e1000e_get_auto_rd_done(hw
);
5630 /* When auto config read does not complete, do not
5631 * return with an error. This can happen in situations
5632 * where there is no eeprom and prevents getting link.
5634 e_dbg("Auto Read Done did not complete\n");
5639 /* Clear PHY Reset Asserted bit */
5640 status
= er32(STATUS
);
5641 if (status
& E1000_STATUS_PHYRA
)
5642 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
5644 e_dbg("PHY Reset Asserted not set - needs delay\n");
5646 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5647 if (hw
->mac
.type
<= e1000_ich9lan
) {
5648 if (!(er32(EECD
) & E1000_EECD_PRES
) &&
5649 (hw
->phy
.type
== e1000_phy_igp_3
)) {
5650 e1000e_phy_init_script_igp3(hw
);
5653 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
5654 /* Maybe we should do a basic PHY config */
5655 e_dbg("EEPROM not present\n");
5656 ret_val
= -E1000_ERR_CONFIG
;
5664 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5665 * @hw: pointer to the HW structure
5667 * In the case of a PHY power down to save power, or to turn off link during a
5668 * driver unload, or wake on lan is not enabled, remove the link.
5670 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
)
5672 /* If the management interface is not enabled, then power down */
5673 if (!(hw
->mac
.ops
.check_mng_mode(hw
) ||
5674 hw
->phy
.ops
.check_reset_block(hw
)))
5675 e1000_power_down_phy_copper(hw
);
5679 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5680 * @hw: pointer to the HW structure
5682 * Clears hardware counters specific to the silicon family and calls
5683 * clear_hw_cntrs_generic to clear all general purpose counters.
5685 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
5690 e1000e_clear_hw_cntrs_base(hw
);
5706 /* Clear PHY statistics registers */
5707 if ((hw
->phy
.type
== e1000_phy_82578
) ||
5708 (hw
->phy
.type
== e1000_phy_82579
) ||
5709 (hw
->phy
.type
== e1000_phy_i217
) ||
5710 (hw
->phy
.type
== e1000_phy_82577
)) {
5711 ret_val
= hw
->phy
.ops
.acquire(hw
);
5714 ret_val
= hw
->phy
.ops
.set_page(hw
,
5715 HV_STATS_PAGE
<< IGP_PAGE_SHIFT
);
5718 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_UPPER
, &phy_data
);
5719 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_LOWER
, &phy_data
);
5720 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_UPPER
, &phy_data
);
5721 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_LOWER
, &phy_data
);
5722 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_UPPER
, &phy_data
);
5723 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_LOWER
, &phy_data
);
5724 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_UPPER
, &phy_data
);
5725 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_LOWER
, &phy_data
);
5726 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_UPPER
, &phy_data
);
5727 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_LOWER
, &phy_data
);
5728 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_UPPER
, &phy_data
);
5729 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_LOWER
, &phy_data
);
5730 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_UPPER
, &phy_data
);
5731 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_LOWER
, &phy_data
);
5733 hw
->phy
.ops
.release(hw
);
5737 static const struct e1000_mac_operations ich8_mac_ops
= {
5738 /* check_mng_mode dependent on mac type */
5739 .check_for_link
= e1000_check_for_copper_link_ich8lan
,
5740 /* cleanup_led dependent on mac type */
5741 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
5742 .get_bus_info
= e1000_get_bus_info_ich8lan
,
5743 .set_lan_id
= e1000_set_lan_id_single_port
,
5744 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
5745 /* led_on dependent on mac type */
5746 /* led_off dependent on mac type */
5747 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
5748 .reset_hw
= e1000_reset_hw_ich8lan
,
5749 .init_hw
= e1000_init_hw_ich8lan
,
5750 .setup_link
= e1000_setup_link_ich8lan
,
5751 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
5752 /* id_led_init dependent on mac type */
5753 .config_collision_dist
= e1000e_config_collision_dist_generic
,
5754 .rar_set
= e1000e_rar_set_generic
,
5755 .rar_get_count
= e1000e_rar_get_count_generic
,
5758 static const struct e1000_phy_operations ich8_phy_ops
= {
5759 .acquire
= e1000_acquire_swflag_ich8lan
,
5760 .check_reset_block
= e1000_check_reset_block_ich8lan
,
5762 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
5763 .get_cable_length
= e1000e_get_cable_length_igp_2
,
5764 .read_reg
= e1000e_read_phy_reg_igp
,
5765 .release
= e1000_release_swflag_ich8lan
,
5766 .reset
= e1000_phy_hw_reset_ich8lan
,
5767 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
5768 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
5769 .write_reg
= e1000e_write_phy_reg_igp
,
5772 static const struct e1000_nvm_operations ich8_nvm_ops
= {
5773 .acquire
= e1000_acquire_nvm_ich8lan
,
5774 .read
= e1000_read_nvm_ich8lan
,
5775 .release
= e1000_release_nvm_ich8lan
,
5776 .reload
= e1000e_reload_nvm_generic
,
5777 .update
= e1000_update_nvm_checksum_ich8lan
,
5778 .valid_led_default
= e1000_valid_led_default_ich8lan
,
5779 .validate
= e1000_validate_nvm_checksum_ich8lan
,
5780 .write
= e1000_write_nvm_ich8lan
,
5783 static const struct e1000_nvm_operations spt_nvm_ops
= {
5784 .acquire
= e1000_acquire_nvm_ich8lan
,
5785 .release
= e1000_release_nvm_ich8lan
,
5786 .read
= e1000_read_nvm_spt
,
5787 .update
= e1000_update_nvm_checksum_spt
,
5788 .reload
= e1000e_reload_nvm_generic
,
5789 .valid_led_default
= e1000_valid_led_default_ich8lan
,
5790 .validate
= e1000_validate_nvm_checksum_ich8lan
,
5791 .write
= e1000_write_nvm_ich8lan
,
5794 const struct e1000_info e1000_ich8_info
= {
5795 .mac
= e1000_ich8lan
,
5796 .flags
= FLAG_HAS_WOL
5798 | FLAG_HAS_CTRLEXT_ON_LOAD
5803 .max_hw_frame_size
= VLAN_ETH_FRAME_LEN
+ ETH_FCS_LEN
,
5804 .get_variants
= e1000_get_variants_ich8lan
,
5805 .mac_ops
= &ich8_mac_ops
,
5806 .phy_ops
= &ich8_phy_ops
,
5807 .nvm_ops
= &ich8_nvm_ops
,
5810 const struct e1000_info e1000_ich9_info
= {
5811 .mac
= e1000_ich9lan
,
5812 .flags
= FLAG_HAS_JUMBO_FRAMES
5815 | FLAG_HAS_CTRLEXT_ON_LOAD
5820 .max_hw_frame_size
= DEFAULT_JUMBO
,
5821 .get_variants
= e1000_get_variants_ich8lan
,
5822 .mac_ops
= &ich8_mac_ops
,
5823 .phy_ops
= &ich8_phy_ops
,
5824 .nvm_ops
= &ich8_nvm_ops
,
5827 const struct e1000_info e1000_ich10_info
= {
5828 .mac
= e1000_ich10lan
,
5829 .flags
= FLAG_HAS_JUMBO_FRAMES
5832 | FLAG_HAS_CTRLEXT_ON_LOAD
5837 .max_hw_frame_size
= DEFAULT_JUMBO
,
5838 .get_variants
= e1000_get_variants_ich8lan
,
5839 .mac_ops
= &ich8_mac_ops
,
5840 .phy_ops
= &ich8_phy_ops
,
5841 .nvm_ops
= &ich8_nvm_ops
,
5844 const struct e1000_info e1000_pch_info
= {
5845 .mac
= e1000_pchlan
,
5846 .flags
= FLAG_IS_ICH
5848 | FLAG_HAS_CTRLEXT_ON_LOAD
5851 | FLAG_HAS_JUMBO_FRAMES
5852 | FLAG_DISABLE_FC_PAUSE_TIME
/* errata */
5854 .flags2
= FLAG2_HAS_PHY_STATS
,
5856 .max_hw_frame_size
= 4096,
5857 .get_variants
= e1000_get_variants_ich8lan
,
5858 .mac_ops
= &ich8_mac_ops
,
5859 .phy_ops
= &ich8_phy_ops
,
5860 .nvm_ops
= &ich8_nvm_ops
,
5863 const struct e1000_info e1000_pch2_info
= {
5864 .mac
= e1000_pch2lan
,
5865 .flags
= FLAG_IS_ICH
5867 | FLAG_HAS_HW_TIMESTAMP
5868 | FLAG_HAS_CTRLEXT_ON_LOAD
5871 | FLAG_HAS_JUMBO_FRAMES
5873 .flags2
= FLAG2_HAS_PHY_STATS
5875 | FLAG2_CHECK_SYSTIM_OVERFLOW
,
5877 .max_hw_frame_size
= 9022,
5878 .get_variants
= e1000_get_variants_ich8lan
,
5879 .mac_ops
= &ich8_mac_ops
,
5880 .phy_ops
= &ich8_phy_ops
,
5881 .nvm_ops
= &ich8_nvm_ops
,
5884 const struct e1000_info e1000_pch_lpt_info
= {
5885 .mac
= e1000_pch_lpt
,
5886 .flags
= FLAG_IS_ICH
5888 | FLAG_HAS_HW_TIMESTAMP
5889 | FLAG_HAS_CTRLEXT_ON_LOAD
5892 | FLAG_HAS_JUMBO_FRAMES
5894 .flags2
= FLAG2_HAS_PHY_STATS
5896 | FLAG2_CHECK_SYSTIM_OVERFLOW
,
5898 .max_hw_frame_size
= 9022,
5899 .get_variants
= e1000_get_variants_ich8lan
,
5900 .mac_ops
= &ich8_mac_ops
,
5901 .phy_ops
= &ich8_phy_ops
,
5902 .nvm_ops
= &ich8_nvm_ops
,
5905 const struct e1000_info e1000_pch_spt_info
= {
5906 .mac
= e1000_pch_spt
,
5907 .flags
= FLAG_IS_ICH
5909 | FLAG_HAS_HW_TIMESTAMP
5910 | FLAG_HAS_CTRLEXT_ON_LOAD
5913 | FLAG_HAS_JUMBO_FRAMES
5915 .flags2
= FLAG2_HAS_PHY_STATS
5918 .max_hw_frame_size
= 9022,
5919 .get_variants
= e1000_get_variants_ich8lan
,
5920 .mac_ops
= &ich8_mac_ops
,
5921 .phy_ops
= &ich8_phy_ops
,
5922 .nvm_ops
= &spt_nvm_ops
,
5925 const struct e1000_info e1000_pch_cnp_info
= {
5926 .mac
= e1000_pch_cnp
,
5927 .flags
= FLAG_IS_ICH
5929 | FLAG_HAS_HW_TIMESTAMP
5930 | FLAG_HAS_CTRLEXT_ON_LOAD
5933 | FLAG_HAS_JUMBO_FRAMES
5935 .flags2
= FLAG2_HAS_PHY_STATS
5938 .max_hw_frame_size
= 9022,
5939 .get_variants
= e1000_get_variants_ich8lan
,
5940 .mac_ops
= &ich8_mac_ops
,
5941 .phy_ops
= &ich8_phy_ops
,
5942 .nvm_ops
= &spt_nvm_ops
,