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intel-ethernet: clean up W=1 warnings in kdoc
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
18 * 82567V Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
39 */
40
41 #include "e1000.h"
42
43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44 /* Offset 04h HSFSTS */
45 union ich8_hws_flash_status {
46 struct ich8_hsfsts {
47 u16 flcdone:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr:1; /* bit 1 Flash Cycle Error */
49 u16 dael:1; /* bit 2 Direct Access error Log */
50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1:2; /* bit 13:6 Reserved */
53 u16 reserved2:6; /* bit 13:6 Reserved */
54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
56 } hsf_status;
57 u16 regval;
58 };
59
60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61 /* Offset 06h FLCTL */
62 union ich8_hws_flash_ctrl {
63 struct ich8_hsflctl {
64 u16 flcgo:1; /* 0 Flash Cycle Go */
65 u16 flcycle:2; /* 2:1 Flash Cycle */
66 u16 reserved:5; /* 7:3 Reserved */
67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn:6; /* 15:10 Reserved */
69 } hsf_ctrl;
70 u16 regval;
71 };
72
73 /* ICH Flash Region Access Permissions */
74 union ich8_hws_flash_regacc {
75 struct ich8_flracc {
76 u32 grra:8; /* 0:7 GbE region Read Access */
77 u32 grwa:8; /* 8:15 GbE region Write Access */
78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
80 } hsf_flregacc;
81 u16 regval;
82 };
83
84 /* ICH Flash Protected Region */
85 union ich8_flash_protected_range {
86 struct ich8_pr {
87 u32 base:13; /* 0:12 Protected Range Base */
88 u32 reserved1:2; /* 13:14 Reserved */
89 u32 rpe:1; /* 15 Read Protection Enable */
90 u32 limit:13; /* 16:28 Protected Range Limit */
91 u32 reserved2:2; /* 29:30 Reserved */
92 u32 wpe:1; /* 31 Write Protection Enable */
93 } range;
94 u32 regval;
95 };
96
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 u32 offset, u8 byte);
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103 u8 *data);
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105 u16 *data);
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107 u8 size, u16 *data);
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109 u32 *data);
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 u32 offset, u32 *data);
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 u32 offset, u32 data);
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 u32 offset, u32 dword);
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140
141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142 {
143 return readw(hw->flash_address + reg);
144 }
145
146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147 {
148 return readl(hw->flash_address + reg);
149 }
150
151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152 {
153 writew(val, hw->flash_address + reg);
154 }
155
156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157 {
158 writel(val, hw->flash_address + reg);
159 }
160
161 #define er16flash(reg) __er16flash(hw, (reg))
162 #define er32flash(reg) __er32flash(hw, (reg))
163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
165
166 /**
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
169 *
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
173 *
174 * Assumes the sw/fw/hw semaphore is already acquired.
175 **/
176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177 {
178 u16 phy_reg = 0;
179 u32 phy_id = 0;
180 s32 ret_val = 0;
181 u16 retry_count;
182 u32 mac_reg = 0;
183
184 for (retry_count = 0; retry_count < 2; retry_count++) {
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
187 continue;
188 phy_id = (u32)(phy_reg << 16);
189
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
192 phy_id = 0;
193 continue;
194 }
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 break;
197 }
198
199 if (hw->phy.id) {
200 if (hw->phy.id == phy_id)
201 goto out;
202 } else if (phy_id) {
203 hw->phy.id = phy_id;
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205 goto out;
206 }
207
208 /* In case the PHY needs to be in mdio slow mode,
209 * set slow mode and try to get the PHY id again.
210 */
211 if (hw->mac.type < e1000_pch_lpt) {
212 hw->phy.ops.release(hw);
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
216 hw->phy.ops.acquire(hw);
217 }
218
219 if (ret_val)
220 return false;
221 out:
222 if (hw->mac.type >= e1000_pch_lpt) {
223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 /* Unforce SMBus mode in PHY */
226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
229
230 /* Unforce SMBus mode in MAC */
231 mac_reg = er32(CTRL_EXT);
232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233 ew32(CTRL_EXT, mac_reg);
234 }
235 }
236
237 return true;
238 }
239
240 /**
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242 * @hw: pointer to the HW structure
243 *
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245 * used to reset the PHY to a quiescent state when necessary.
246 **/
247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248 {
249 u32 mac_reg;
250
251 /* Set Phy Config Counter to 50msec */
252 mac_reg = er32(FEXTNVM3);
253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255 ew32(FEXTNVM3, mac_reg);
256
257 /* Toggle LANPHYPC Value bit */
258 mac_reg = er32(CTRL);
259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
261 ew32(CTRL, mac_reg);
262 e1e_flush();
263 usleep_range(10, 20);
264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
265 ew32(CTRL, mac_reg);
266 e1e_flush();
267
268 if (hw->mac.type < e1000_pch_lpt) {
269 msleep(50);
270 } else {
271 u16 count = 20;
272
273 do {
274 usleep_range(5000, 6000);
275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276
277 msleep(30);
278 }
279 }
280
281 /**
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
284 *
285 * Workarounds/flow necessary for PHY initialization during driver load
286 * and resume paths.
287 **/
288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
289 {
290 struct e1000_adapter *adapter = hw->adapter;
291 u32 mac_reg, fwsm = er32(FWSM);
292 s32 ret_val;
293
294 /* Gate automatic PHY configuration by hardware on managed and
295 * non-managed 82579 and newer adapters.
296 */
297 e1000_gate_hw_phy_config_ich8lan(hw, true);
298
299 /* It is not possible to be certain of the current state of ULP
300 * so forcibly disable it.
301 */
302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
304 if (ret_val)
305 e_warn("Failed to disable ULP\n");
306
307 ret_val = hw->phy.ops.acquire(hw);
308 if (ret_val) {
309 e_dbg("Failed to initialize PHY flow\n");
310 goto out;
311 }
312
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
316 */
317 switch (hw->mac.type) {
318 case e1000_pch_lpt:
319 case e1000_pch_spt:
320 case e1000_pch_cnp:
321 case e1000_pch_tgp:
322 case e1000_pch_adp:
323 if (e1000_phy_is_accessible_pchlan(hw))
324 break;
325
326 /* Before toggling LANPHYPC, see if PHY is accessible by
327 * forcing MAC to SMBus mode first.
328 */
329 mac_reg = er32(CTRL_EXT);
330 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
331 ew32(CTRL_EXT, mac_reg);
332
333 /* Wait 50 milliseconds for MAC to finish any retries
334 * that it might be trying to perform from previous
335 * attempts to acknowledge any phy read requests.
336 */
337 msleep(50);
338
339 fallthrough;
340 case e1000_pch2lan:
341 if (e1000_phy_is_accessible_pchlan(hw))
342 break;
343
344 fallthrough;
345 case e1000_pchlan:
346 if ((hw->mac.type == e1000_pchlan) &&
347 (fwsm & E1000_ICH_FWSM_FW_VALID))
348 break;
349
350 if (hw->phy.ops.check_reset_block(hw)) {
351 e_dbg("Required LANPHYPC toggle blocked by ME\n");
352 ret_val = -E1000_ERR_PHY;
353 break;
354 }
355
356 /* Toggle LANPHYPC Value bit */
357 e1000_toggle_lanphypc_pch_lpt(hw);
358 if (hw->mac.type >= e1000_pch_lpt) {
359 if (e1000_phy_is_accessible_pchlan(hw))
360 break;
361
362 /* Toggling LANPHYPC brings the PHY out of SMBus mode
363 * so ensure that the MAC is also out of SMBus mode
364 */
365 mac_reg = er32(CTRL_EXT);
366 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
367 ew32(CTRL_EXT, mac_reg);
368
369 if (e1000_phy_is_accessible_pchlan(hw))
370 break;
371
372 ret_val = -E1000_ERR_PHY;
373 }
374 break;
375 default:
376 break;
377 }
378
379 hw->phy.ops.release(hw);
380 if (!ret_val) {
381
382 /* Check to see if able to reset PHY. Print error if not */
383 if (hw->phy.ops.check_reset_block(hw)) {
384 e_err("Reset blocked by ME\n");
385 goto out;
386 }
387
388 /* Reset the PHY before any access to it. Doing so, ensures
389 * that the PHY is in a known good state before we read/write
390 * PHY registers. The generic reset is sufficient here,
391 * because we haven't determined the PHY type yet.
392 */
393 ret_val = e1000e_phy_hw_reset_generic(hw);
394 if (ret_val)
395 goto out;
396
397 /* On a successful reset, possibly need to wait for the PHY
398 * to quiesce to an accessible state before returning control
399 * to the calling function. If the PHY does not quiesce, then
400 * return E1000E_BLK_PHY_RESET, as this is the condition that
401 * the PHY is in.
402 */
403 ret_val = hw->phy.ops.check_reset_block(hw);
404 if (ret_val)
405 e_err("ME blocked access to PHY after reset\n");
406 }
407
408 out:
409 /* Ungate automatic PHY configuration on non-managed 82579 */
410 if ((hw->mac.type == e1000_pch2lan) &&
411 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
412 usleep_range(10000, 11000);
413 e1000_gate_hw_phy_config_ich8lan(hw, false);
414 }
415
416 return ret_val;
417 }
418
419 /**
420 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
421 * @hw: pointer to the HW structure
422 *
423 * Initialize family-specific PHY parameters and function pointers.
424 **/
425 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
426 {
427 struct e1000_phy_info *phy = &hw->phy;
428 s32 ret_val;
429
430 phy->addr = 1;
431 phy->reset_delay_us = 100;
432
433 phy->ops.set_page = e1000_set_page_igp;
434 phy->ops.read_reg = e1000_read_phy_reg_hv;
435 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
436 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
437 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
438 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
439 phy->ops.write_reg = e1000_write_phy_reg_hv;
440 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
441 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
442 phy->ops.power_up = e1000_power_up_phy_copper;
443 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
444 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
445
446 phy->id = e1000_phy_unknown;
447
448 ret_val = e1000_init_phy_workarounds_pchlan(hw);
449 if (ret_val)
450 return ret_val;
451
452 if (phy->id == e1000_phy_unknown)
453 switch (hw->mac.type) {
454 default:
455 ret_val = e1000e_get_phy_id(hw);
456 if (ret_val)
457 return ret_val;
458 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
459 break;
460 fallthrough;
461 case e1000_pch2lan:
462 case e1000_pch_lpt:
463 case e1000_pch_spt:
464 case e1000_pch_cnp:
465 case e1000_pch_tgp:
466 case e1000_pch_adp:
467 /* In case the PHY needs to be in mdio slow mode,
468 * set slow mode and try to get the PHY id again.
469 */
470 ret_val = e1000_set_mdio_slow_mode_hv(hw);
471 if (ret_val)
472 return ret_val;
473 ret_val = e1000e_get_phy_id(hw);
474 if (ret_val)
475 return ret_val;
476 break;
477 }
478 phy->type = e1000e_get_phy_type_from_id(phy->id);
479
480 switch (phy->type) {
481 case e1000_phy_82577:
482 case e1000_phy_82579:
483 case e1000_phy_i217:
484 phy->ops.check_polarity = e1000_check_polarity_82577;
485 phy->ops.force_speed_duplex =
486 e1000_phy_force_speed_duplex_82577;
487 phy->ops.get_cable_length = e1000_get_cable_length_82577;
488 phy->ops.get_info = e1000_get_phy_info_82577;
489 phy->ops.commit = e1000e_phy_sw_reset;
490 break;
491 case e1000_phy_82578:
492 phy->ops.check_polarity = e1000_check_polarity_m88;
493 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
494 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
495 phy->ops.get_info = e1000e_get_phy_info_m88;
496 break;
497 default:
498 ret_val = -E1000_ERR_PHY;
499 break;
500 }
501
502 return ret_val;
503 }
504
505 /**
506 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
507 * @hw: pointer to the HW structure
508 *
509 * Initialize family-specific PHY parameters and function pointers.
510 **/
511 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
512 {
513 struct e1000_phy_info *phy = &hw->phy;
514 s32 ret_val;
515 u16 i = 0;
516
517 phy->addr = 1;
518 phy->reset_delay_us = 100;
519
520 phy->ops.power_up = e1000_power_up_phy_copper;
521 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
522
523 /* We may need to do this twice - once for IGP and if that fails,
524 * we'll set BM func pointers and try again
525 */
526 ret_val = e1000e_determine_phy_address(hw);
527 if (ret_val) {
528 phy->ops.write_reg = e1000e_write_phy_reg_bm;
529 phy->ops.read_reg = e1000e_read_phy_reg_bm;
530 ret_val = e1000e_determine_phy_address(hw);
531 if (ret_val) {
532 e_dbg("Cannot determine PHY addr. Erroring out\n");
533 return ret_val;
534 }
535 }
536
537 phy->id = 0;
538 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
539 (i++ < 100)) {
540 usleep_range(1000, 1100);
541 ret_val = e1000e_get_phy_id(hw);
542 if (ret_val)
543 return ret_val;
544 }
545
546 /* Verify phy id */
547 switch (phy->id) {
548 case IGP03E1000_E_PHY_ID:
549 phy->type = e1000_phy_igp_3;
550 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
551 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
552 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
553 phy->ops.get_info = e1000e_get_phy_info_igp;
554 phy->ops.check_polarity = e1000_check_polarity_igp;
555 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
556 break;
557 case IFE_E_PHY_ID:
558 case IFE_PLUS_E_PHY_ID:
559 case IFE_C_E_PHY_ID:
560 phy->type = e1000_phy_ife;
561 phy->autoneg_mask = E1000_ALL_NOT_GIG;
562 phy->ops.get_info = e1000_get_phy_info_ife;
563 phy->ops.check_polarity = e1000_check_polarity_ife;
564 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
565 break;
566 case BME1000_E_PHY_ID:
567 phy->type = e1000_phy_bm;
568 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
569 phy->ops.read_reg = e1000e_read_phy_reg_bm;
570 phy->ops.write_reg = e1000e_write_phy_reg_bm;
571 phy->ops.commit = e1000e_phy_sw_reset;
572 phy->ops.get_info = e1000e_get_phy_info_m88;
573 phy->ops.check_polarity = e1000_check_polarity_m88;
574 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
575 break;
576 default:
577 return -E1000_ERR_PHY;
578 }
579
580 return 0;
581 }
582
583 /**
584 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
585 * @hw: pointer to the HW structure
586 *
587 * Initialize family-specific NVM parameters and function
588 * pointers.
589 **/
590 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
591 {
592 struct e1000_nvm_info *nvm = &hw->nvm;
593 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
594 u32 gfpreg, sector_base_addr, sector_end_addr;
595 u16 i;
596 u32 nvm_size;
597
598 nvm->type = e1000_nvm_flash_sw;
599
600 if (hw->mac.type >= e1000_pch_spt) {
601 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
602 * STRAP register. This is because in SPT the GbE Flash region
603 * is no longer accessed through the flash registers. Instead,
604 * the mechanism has changed, and the Flash region access
605 * registers are now implemented in GbE memory space.
606 */
607 nvm->flash_base_addr = 0;
608 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
609 * NVM_SIZE_MULTIPLIER;
610 nvm->flash_bank_size = nvm_size / 2;
611 /* Adjust to word count */
612 nvm->flash_bank_size /= sizeof(u16);
613 /* Set the base address for flash register access */
614 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
615 } else {
616 /* Can't read flash registers if register set isn't mapped. */
617 if (!hw->flash_address) {
618 e_dbg("ERROR: Flash registers not mapped\n");
619 return -E1000_ERR_CONFIG;
620 }
621
622 gfpreg = er32flash(ICH_FLASH_GFPREG);
623
624 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
625 * Add 1 to sector_end_addr since this sector is included in
626 * the overall size.
627 */
628 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
629 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
630
631 /* flash_base_addr is byte-aligned */
632 nvm->flash_base_addr = sector_base_addr
633 << FLASH_SECTOR_ADDR_SHIFT;
634
635 /* find total size of the NVM, then cut in half since the total
636 * size represents two separate NVM banks.
637 */
638 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
639 << FLASH_SECTOR_ADDR_SHIFT);
640 nvm->flash_bank_size /= 2;
641 /* Adjust to word count */
642 nvm->flash_bank_size /= sizeof(u16);
643 }
644
645 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
646
647 /* Clear shadow ram */
648 for (i = 0; i < nvm->word_size; i++) {
649 dev_spec->shadow_ram[i].modified = false;
650 dev_spec->shadow_ram[i].value = 0xFFFF;
651 }
652
653 return 0;
654 }
655
656 /**
657 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
658 * @hw: pointer to the HW structure
659 *
660 * Initialize family-specific MAC parameters and function
661 * pointers.
662 **/
663 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
664 {
665 struct e1000_mac_info *mac = &hw->mac;
666
667 /* Set media type function pointer */
668 hw->phy.media_type = e1000_media_type_copper;
669
670 /* Set mta register count */
671 mac->mta_reg_count = 32;
672 /* Set rar entry count */
673 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
674 if (mac->type == e1000_ich8lan)
675 mac->rar_entry_count--;
676 /* FWSM register */
677 mac->has_fwsm = true;
678 /* ARC subsystem not supported */
679 mac->arc_subsystem_valid = false;
680 /* Adaptive IFS supported */
681 mac->adaptive_ifs = true;
682
683 /* LED and other operations */
684 switch (mac->type) {
685 case e1000_ich8lan:
686 case e1000_ich9lan:
687 case e1000_ich10lan:
688 /* check management mode */
689 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
690 /* ID LED init */
691 mac->ops.id_led_init = e1000e_id_led_init_generic;
692 /* blink LED */
693 mac->ops.blink_led = e1000e_blink_led_generic;
694 /* setup LED */
695 mac->ops.setup_led = e1000e_setup_led_generic;
696 /* cleanup LED */
697 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
698 /* turn on/off LED */
699 mac->ops.led_on = e1000_led_on_ich8lan;
700 mac->ops.led_off = e1000_led_off_ich8lan;
701 break;
702 case e1000_pch2lan:
703 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
704 mac->ops.rar_set = e1000_rar_set_pch2lan;
705 fallthrough;
706 case e1000_pch_lpt:
707 case e1000_pch_spt:
708 case e1000_pch_cnp:
709 case e1000_pch_tgp:
710 case e1000_pch_adp:
711 case e1000_pchlan:
712 /* check management mode */
713 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
714 /* ID LED init */
715 mac->ops.id_led_init = e1000_id_led_init_pchlan;
716 /* setup LED */
717 mac->ops.setup_led = e1000_setup_led_pchlan;
718 /* cleanup LED */
719 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
720 /* turn on/off LED */
721 mac->ops.led_on = e1000_led_on_pchlan;
722 mac->ops.led_off = e1000_led_off_pchlan;
723 break;
724 default:
725 break;
726 }
727
728 if (mac->type >= e1000_pch_lpt) {
729 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
730 mac->ops.rar_set = e1000_rar_set_pch_lpt;
731 mac->ops.setup_physical_interface =
732 e1000_setup_copper_link_pch_lpt;
733 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
734 }
735
736 /* Enable PCS Lock-loss workaround for ICH8 */
737 if (mac->type == e1000_ich8lan)
738 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
739
740 return 0;
741 }
742
743 /**
744 * __e1000_access_emi_reg_locked - Read/write EMI register
745 * @hw: pointer to the HW structure
746 * @address: EMI address to program
747 * @data: pointer to value to read/write from/to the EMI address
748 * @read: boolean flag to indicate read or write
749 *
750 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
751 **/
752 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
753 u16 *data, bool read)
754 {
755 s32 ret_val;
756
757 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
758 if (ret_val)
759 return ret_val;
760
761 if (read)
762 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
763 else
764 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
765
766 return ret_val;
767 }
768
769 /**
770 * e1000_read_emi_reg_locked - Read Extended Management Interface register
771 * @hw: pointer to the HW structure
772 * @addr: EMI address to program
773 * @data: value to be read from the EMI address
774 *
775 * Assumes the SW/FW/HW Semaphore is already acquired.
776 **/
777 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
778 {
779 return __e1000_access_emi_reg_locked(hw, addr, data, true);
780 }
781
782 /**
783 * e1000_write_emi_reg_locked - Write Extended Management Interface register
784 * @hw: pointer to the HW structure
785 * @addr: EMI address to program
786 * @data: value to be written to the EMI address
787 *
788 * Assumes the SW/FW/HW Semaphore is already acquired.
789 **/
790 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
791 {
792 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
793 }
794
795 /**
796 * e1000_set_eee_pchlan - Enable/disable EEE support
797 * @hw: pointer to the HW structure
798 *
799 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
800 * the link and the EEE capabilities of the link partner. The LPI Control
801 * register bits will remain set only if/when link is up.
802 *
803 * EEE LPI must not be asserted earlier than one second after link is up.
804 * On 82579, EEE LPI should not be enabled until such time otherwise there
805 * can be link issues with some switches. Other devices can have EEE LPI
806 * enabled immediately upon link up since they have a timer in hardware which
807 * prevents LPI from being asserted too early.
808 **/
809 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
810 {
811 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
812 s32 ret_val;
813 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
814
815 switch (hw->phy.type) {
816 case e1000_phy_82579:
817 lpa = I82579_EEE_LP_ABILITY;
818 pcs_status = I82579_EEE_PCS_STATUS;
819 adv_addr = I82579_EEE_ADVERTISEMENT;
820 break;
821 case e1000_phy_i217:
822 lpa = I217_EEE_LP_ABILITY;
823 pcs_status = I217_EEE_PCS_STATUS;
824 adv_addr = I217_EEE_ADVERTISEMENT;
825 break;
826 default:
827 return 0;
828 }
829
830 ret_val = hw->phy.ops.acquire(hw);
831 if (ret_val)
832 return ret_val;
833
834 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
835 if (ret_val)
836 goto release;
837
838 /* Clear bits that enable EEE in various speeds */
839 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
840
841 /* Enable EEE if not disabled by user */
842 if (!dev_spec->eee_disable) {
843 /* Save off link partner's EEE ability */
844 ret_val = e1000_read_emi_reg_locked(hw, lpa,
845 &dev_spec->eee_lp_ability);
846 if (ret_val)
847 goto release;
848
849 /* Read EEE advertisement */
850 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
851 if (ret_val)
852 goto release;
853
854 /* Enable EEE only for speeds in which the link partner is
855 * EEE capable and for which we advertise EEE.
856 */
857 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
858 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
859
860 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
861 e1e_rphy_locked(hw, MII_LPA, &data);
862 if (data & LPA_100FULL)
863 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
864 else
865 /* EEE is not supported in 100Half, so ignore
866 * partner's EEE in 100 ability if full-duplex
867 * is not advertised.
868 */
869 dev_spec->eee_lp_ability &=
870 ~I82579_EEE_100_SUPPORTED;
871 }
872 }
873
874 if (hw->phy.type == e1000_phy_82579) {
875 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
876 &data);
877 if (ret_val)
878 goto release;
879
880 data &= ~I82579_LPI_100_PLL_SHUT;
881 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
882 data);
883 }
884
885 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
886 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
887 if (ret_val)
888 goto release;
889
890 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
891 release:
892 hw->phy.ops.release(hw);
893
894 return ret_val;
895 }
896
897 /**
898 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
899 * @hw: pointer to the HW structure
900 * @link: link up bool flag
901 *
902 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
903 * preventing further DMA write requests. Workaround the issue by disabling
904 * the de-assertion of the clock request when in 1Gpbs mode.
905 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
906 * speeds in order to avoid Tx hangs.
907 **/
908 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
909 {
910 u32 fextnvm6 = er32(FEXTNVM6);
911 u32 status = er32(STATUS);
912 s32 ret_val = 0;
913 u16 reg;
914
915 if (link && (status & E1000_STATUS_SPEED_1000)) {
916 ret_val = hw->phy.ops.acquire(hw);
917 if (ret_val)
918 return ret_val;
919
920 ret_val =
921 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
922 &reg);
923 if (ret_val)
924 goto release;
925
926 ret_val =
927 e1000e_write_kmrn_reg_locked(hw,
928 E1000_KMRNCTRLSTA_K1_CONFIG,
929 reg &
930 ~E1000_KMRNCTRLSTA_K1_ENABLE);
931 if (ret_val)
932 goto release;
933
934 usleep_range(10, 20);
935
936 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
937
938 ret_val =
939 e1000e_write_kmrn_reg_locked(hw,
940 E1000_KMRNCTRLSTA_K1_CONFIG,
941 reg);
942 release:
943 hw->phy.ops.release(hw);
944 } else {
945 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
946 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
947
948 if ((hw->phy.revision > 5) || !link ||
949 ((status & E1000_STATUS_SPEED_100) &&
950 (status & E1000_STATUS_FD)))
951 goto update_fextnvm6;
952
953 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
954 if (ret_val)
955 return ret_val;
956
957 /* Clear link status transmit timeout */
958 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
959
960 if (status & E1000_STATUS_SPEED_100) {
961 /* Set inband Tx timeout to 5x10us for 100Half */
962 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
963
964 /* Do not extend the K1 entry latency for 100Half */
965 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
966 } else {
967 /* Set inband Tx timeout to 50x10us for 10Full/Half */
968 reg |= 50 <<
969 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
970
971 /* Extend the K1 entry latency for 10 Mbps */
972 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
973 }
974
975 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
976 if (ret_val)
977 return ret_val;
978
979 update_fextnvm6:
980 ew32(FEXTNVM6, fextnvm6);
981 }
982
983 return ret_val;
984 }
985
986 /**
987 * e1000_platform_pm_pch_lpt - Set platform power management values
988 * @hw: pointer to the HW structure
989 * @link: bool indicating link status
990 *
991 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
992 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
993 * when link is up (which must not exceed the maximum latency supported
994 * by the platform), otherwise specify there is no LTR requirement.
995 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
996 * latencies in the LTR Extended Capability Structure in the PCIe Extended
997 * Capability register set, on this device LTR is set by writing the
998 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
999 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1000 * message to the PMC.
1001 **/
1002 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1003 {
1004 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1005 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1006 u16 lat_enc = 0; /* latency encoded */
1007
1008 if (link) {
1009 u16 speed, duplex, scale = 0;
1010 u16 max_snoop, max_nosnoop;
1011 u16 max_ltr_enc; /* max LTR latency encoded */
1012 u64 value;
1013 u32 rxa;
1014
1015 if (!hw->adapter->max_frame_size) {
1016 e_dbg("max_frame_size not set.\n");
1017 return -E1000_ERR_CONFIG;
1018 }
1019
1020 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1021 if (!speed) {
1022 e_dbg("Speed not set.\n");
1023 return -E1000_ERR_CONFIG;
1024 }
1025
1026 /* Rx Packet Buffer Allocation size (KB) */
1027 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1028
1029 /* Determine the maximum latency tolerated by the device.
1030 *
1031 * Per the PCIe spec, the tolerated latencies are encoded as
1032 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1033 * a 10-bit value (0-1023) to provide a range from 1 ns to
1034 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1035 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1036 */
1037 rxa *= 512;
1038 value = (rxa > hw->adapter->max_frame_size) ?
1039 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1040 0;
1041
1042 while (value > PCI_LTR_VALUE_MASK) {
1043 scale++;
1044 value = DIV_ROUND_UP(value, BIT(5));
1045 }
1046 if (scale > E1000_LTRV_SCALE_MAX) {
1047 e_dbg("Invalid LTR latency scale %d\n", scale);
1048 return -E1000_ERR_CONFIG;
1049 }
1050 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1051
1052 /* Determine the maximum latency tolerated by the platform */
1053 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1054 &max_snoop);
1055 pci_read_config_word(hw->adapter->pdev,
1056 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1057 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1058
1059 if (lat_enc > max_ltr_enc)
1060 lat_enc = max_ltr_enc;
1061 }
1062
1063 /* Set Snoop and No-Snoop latencies the same */
1064 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1065 ew32(LTRV, reg);
1066
1067 return 0;
1068 }
1069
1070 /**
1071 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1072 * @hw: pointer to the HW structure
1073 * @to_sx: boolean indicating a system power state transition to Sx
1074 *
1075 * When link is down, configure ULP mode to significantly reduce the power
1076 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1077 * ME firmware to start the ULP configuration. If not on an ME enabled
1078 * system, configure the ULP mode by software.
1079 */
1080 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1081 {
1082 u32 mac_reg;
1083 s32 ret_val = 0;
1084 u16 phy_reg;
1085 u16 oem_reg = 0;
1086
1087 if ((hw->mac.type < e1000_pch_lpt) ||
1088 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1089 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1090 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1091 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1092 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1093 return 0;
1094
1095 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1096 /* Request ME configure ULP mode in the PHY */
1097 mac_reg = er32(H2ME);
1098 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1099 ew32(H2ME, mac_reg);
1100
1101 goto out;
1102 }
1103
1104 if (!to_sx) {
1105 int i = 0;
1106
1107 /* Poll up to 5 seconds for Cable Disconnected indication */
1108 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1109 /* Bail if link is re-acquired */
1110 if (er32(STATUS) & E1000_STATUS_LU)
1111 return -E1000_ERR_PHY;
1112
1113 if (i++ == 100)
1114 break;
1115
1116 msleep(50);
1117 }
1118 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1119 (er32(FEXT) &
1120 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1121 }
1122
1123 ret_val = hw->phy.ops.acquire(hw);
1124 if (ret_val)
1125 goto out;
1126
1127 /* Force SMBus mode in PHY */
1128 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1129 if (ret_val)
1130 goto release;
1131 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1132 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1133
1134 /* Force SMBus mode in MAC */
1135 mac_reg = er32(CTRL_EXT);
1136 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1137 ew32(CTRL_EXT, mac_reg);
1138
1139 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1140 * LPLU and disable Gig speed when entering ULP
1141 */
1142 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1143 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1144 &oem_reg);
1145 if (ret_val)
1146 goto release;
1147
1148 phy_reg = oem_reg;
1149 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1150
1151 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1152 phy_reg);
1153
1154 if (ret_val)
1155 goto release;
1156 }
1157
1158 /* Set Inband ULP Exit, Reset to SMBus mode and
1159 * Disable SMBus Release on PERST# in PHY
1160 */
1161 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1162 if (ret_val)
1163 goto release;
1164 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1165 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1166 if (to_sx) {
1167 if (er32(WUFC) & E1000_WUFC_LNKC)
1168 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1169 else
1170 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1171
1172 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1173 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1174 } else {
1175 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1176 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1177 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1178 }
1179 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1180
1181 /* Set Disable SMBus Release on PERST# in MAC */
1182 mac_reg = er32(FEXTNVM7);
1183 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1184 ew32(FEXTNVM7, mac_reg);
1185
1186 /* Commit ULP changes in PHY by starting auto ULP configuration */
1187 phy_reg |= I218_ULP_CONFIG1_START;
1188 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1189
1190 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1191 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1192 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1193 oem_reg);
1194 if (ret_val)
1195 goto release;
1196 }
1197
1198 release:
1199 hw->phy.ops.release(hw);
1200 out:
1201 if (ret_val)
1202 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1203 else
1204 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1205
1206 return ret_val;
1207 }
1208
1209 /**
1210 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1211 * @hw: pointer to the HW structure
1212 * @force: boolean indicating whether or not to force disabling ULP
1213 *
1214 * Un-configure ULP mode when link is up, the system is transitioned from
1215 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1216 * system, poll for an indication from ME that ULP has been un-configured.
1217 * If not on an ME enabled system, un-configure the ULP mode by software.
1218 *
1219 * During nominal operation, this function is called when link is acquired
1220 * to disable ULP mode (force=false); otherwise, for example when unloading
1221 * the driver or during Sx->S0 transitions, this is called with force=true
1222 * to forcibly disable ULP.
1223 */
1224 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1225 {
1226 s32 ret_val = 0;
1227 u32 mac_reg;
1228 u16 phy_reg;
1229 int i = 0;
1230
1231 if ((hw->mac.type < e1000_pch_lpt) ||
1232 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1233 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1234 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1235 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1236 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1237 return 0;
1238
1239 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1240 if (force) {
1241 /* Request ME un-configure ULP mode in the PHY */
1242 mac_reg = er32(H2ME);
1243 mac_reg &= ~E1000_H2ME_ULP;
1244 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1245 ew32(H2ME, mac_reg);
1246 }
1247
1248 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1249 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1250 if (i++ == 30) {
1251 ret_val = -E1000_ERR_PHY;
1252 goto out;
1253 }
1254
1255 usleep_range(10000, 11000);
1256 }
1257 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1258
1259 if (force) {
1260 mac_reg = er32(H2ME);
1261 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1262 ew32(H2ME, mac_reg);
1263 } else {
1264 /* Clear H2ME.ULP after ME ULP configuration */
1265 mac_reg = er32(H2ME);
1266 mac_reg &= ~E1000_H2ME_ULP;
1267 ew32(H2ME, mac_reg);
1268 }
1269
1270 goto out;
1271 }
1272
1273 ret_val = hw->phy.ops.acquire(hw);
1274 if (ret_val)
1275 goto out;
1276
1277 if (force)
1278 /* Toggle LANPHYPC Value bit */
1279 e1000_toggle_lanphypc_pch_lpt(hw);
1280
1281 /* Unforce SMBus mode in PHY */
1282 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1283 if (ret_val) {
1284 /* The MAC might be in PCIe mode, so temporarily force to
1285 * SMBus mode in order to access the PHY.
1286 */
1287 mac_reg = er32(CTRL_EXT);
1288 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1289 ew32(CTRL_EXT, mac_reg);
1290
1291 msleep(50);
1292
1293 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1294 &phy_reg);
1295 if (ret_val)
1296 goto release;
1297 }
1298 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1299 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1300
1301 /* Unforce SMBus mode in MAC */
1302 mac_reg = er32(CTRL_EXT);
1303 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1304 ew32(CTRL_EXT, mac_reg);
1305
1306 /* When ULP mode was previously entered, K1 was disabled by the
1307 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1308 */
1309 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1310 if (ret_val)
1311 goto release;
1312 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1313 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1314
1315 /* Clear ULP enabled configuration */
1316 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1317 if (ret_val)
1318 goto release;
1319 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1320 I218_ULP_CONFIG1_STICKY_ULP |
1321 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1322 I218_ULP_CONFIG1_WOL_HOST |
1323 I218_ULP_CONFIG1_INBAND_EXIT |
1324 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1325 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1326 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1327 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1328
1329 /* Commit ULP changes by starting auto ULP configuration */
1330 phy_reg |= I218_ULP_CONFIG1_START;
1331 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1332
1333 /* Clear Disable SMBus Release on PERST# in MAC */
1334 mac_reg = er32(FEXTNVM7);
1335 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1336 ew32(FEXTNVM7, mac_reg);
1337
1338 release:
1339 hw->phy.ops.release(hw);
1340 if (force) {
1341 e1000_phy_hw_reset(hw);
1342 msleep(50);
1343 }
1344 out:
1345 if (ret_val)
1346 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1347 else
1348 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1349
1350 return ret_val;
1351 }
1352
1353 /**
1354 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1355 * @hw: pointer to the HW structure
1356 *
1357 * Checks to see of the link status of the hardware has changed. If a
1358 * change in link status has been detected, then we read the PHY registers
1359 * to get the current speed/duplex if link exists.
1360 **/
1361 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1362 {
1363 struct e1000_mac_info *mac = &hw->mac;
1364 s32 ret_val, tipg_reg = 0;
1365 u16 emi_addr, emi_val = 0;
1366 bool link;
1367 u16 phy_reg;
1368
1369 /* We only want to go out to the PHY registers to see if Auto-Neg
1370 * has completed and/or if our link status has changed. The
1371 * get_link_status flag is set upon receiving a Link Status
1372 * Change or Rx Sequence Error interrupt.
1373 */
1374 if (!mac->get_link_status)
1375 return 0;
1376 mac->get_link_status = false;
1377
1378 /* First we want to see if the MII Status Register reports
1379 * link. If so, then we want to get the current speed/duplex
1380 * of the PHY.
1381 */
1382 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1383 if (ret_val)
1384 goto out;
1385
1386 if (hw->mac.type == e1000_pchlan) {
1387 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1388 if (ret_val)
1389 goto out;
1390 }
1391
1392 /* When connected at 10Mbps half-duplex, some parts are excessively
1393 * aggressive resulting in many collisions. To avoid this, increase
1394 * the IPG and reduce Rx latency in the PHY.
1395 */
1396 if ((hw->mac.type >= e1000_pch2lan) && link) {
1397 u16 speed, duplex;
1398
1399 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1400 tipg_reg = er32(TIPG);
1401 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1402
1403 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1404 tipg_reg |= 0xFF;
1405 /* Reduce Rx latency in analog PHY */
1406 emi_val = 0;
1407 } else if (hw->mac.type >= e1000_pch_spt &&
1408 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1409 tipg_reg |= 0xC;
1410 emi_val = 1;
1411 } else {
1412
1413 /* Roll back the default values */
1414 tipg_reg |= 0x08;
1415 emi_val = 1;
1416 }
1417
1418 ew32(TIPG, tipg_reg);
1419
1420 ret_val = hw->phy.ops.acquire(hw);
1421 if (ret_val)
1422 goto out;
1423
1424 if (hw->mac.type == e1000_pch2lan)
1425 emi_addr = I82579_RX_CONFIG;
1426 else
1427 emi_addr = I217_RX_CONFIG;
1428 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1429
1430 if (hw->mac.type >= e1000_pch_lpt) {
1431 u16 phy_reg;
1432
1433 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1434 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1435 if (speed == SPEED_100 || speed == SPEED_10)
1436 phy_reg |= 0x3E8;
1437 else
1438 phy_reg |= 0xFA;
1439 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1440
1441 if (speed == SPEED_1000) {
1442 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1443 &phy_reg);
1444
1445 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1446
1447 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1448 phy_reg);
1449 }
1450 }
1451 hw->phy.ops.release(hw);
1452
1453 if (ret_val)
1454 goto out;
1455
1456 if (hw->mac.type >= e1000_pch_spt) {
1457 u16 data;
1458 u16 ptr_gap;
1459
1460 if (speed == SPEED_1000) {
1461 ret_val = hw->phy.ops.acquire(hw);
1462 if (ret_val)
1463 goto out;
1464
1465 ret_val = e1e_rphy_locked(hw,
1466 PHY_REG(776, 20),
1467 &data);
1468 if (ret_val) {
1469 hw->phy.ops.release(hw);
1470 goto out;
1471 }
1472
1473 ptr_gap = (data & (0x3FF << 2)) >> 2;
1474 if (ptr_gap < 0x18) {
1475 data &= ~(0x3FF << 2);
1476 data |= (0x18 << 2);
1477 ret_val =
1478 e1e_wphy_locked(hw,
1479 PHY_REG(776, 20),
1480 data);
1481 }
1482 hw->phy.ops.release(hw);
1483 if (ret_val)
1484 goto out;
1485 } else {
1486 ret_val = hw->phy.ops.acquire(hw);
1487 if (ret_val)
1488 goto out;
1489
1490 ret_val = e1e_wphy_locked(hw,
1491 PHY_REG(776, 20),
1492 0xC023);
1493 hw->phy.ops.release(hw);
1494 if (ret_val)
1495 goto out;
1496
1497 }
1498 }
1499 }
1500
1501 /* I217 Packet Loss issue:
1502 * ensure that FEXTNVM4 Beacon Duration is set correctly
1503 * on power up.
1504 * Set the Beacon Duration for I217 to 8 usec
1505 */
1506 if (hw->mac.type >= e1000_pch_lpt) {
1507 u32 mac_reg;
1508
1509 mac_reg = er32(FEXTNVM4);
1510 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1511 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1512 ew32(FEXTNVM4, mac_reg);
1513 }
1514
1515 /* Work-around I218 hang issue */
1516 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1517 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1518 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1519 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1520 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1521 if (ret_val)
1522 goto out;
1523 }
1524 if (hw->mac.type >= e1000_pch_lpt) {
1525 /* Set platform power management values for
1526 * Latency Tolerance Reporting (LTR)
1527 */
1528 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1529 if (ret_val)
1530 goto out;
1531 }
1532
1533 /* Clear link partner's EEE ability */
1534 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1535
1536 if (hw->mac.type >= e1000_pch_lpt) {
1537 u32 fextnvm6 = er32(FEXTNVM6);
1538
1539 if (hw->mac.type == e1000_pch_spt) {
1540 /* FEXTNVM6 K1-off workaround - for SPT only */
1541 u32 pcieanacfg = er32(PCIEANACFG);
1542
1543 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1544 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1545 else
1546 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1547 }
1548
1549 ew32(FEXTNVM6, fextnvm6);
1550 }
1551
1552 if (!link)
1553 goto out;
1554
1555 switch (hw->mac.type) {
1556 case e1000_pch2lan:
1557 ret_val = e1000_k1_workaround_lv(hw);
1558 if (ret_val)
1559 return ret_val;
1560 fallthrough;
1561 case e1000_pchlan:
1562 if (hw->phy.type == e1000_phy_82578) {
1563 ret_val = e1000_link_stall_workaround_hv(hw);
1564 if (ret_val)
1565 return ret_val;
1566 }
1567
1568 /* Workaround for PCHx parts in half-duplex:
1569 * Set the number of preambles removed from the packet
1570 * when it is passed from the PHY to the MAC to prevent
1571 * the MAC from misinterpreting the packet type.
1572 */
1573 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1574 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1575
1576 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1577 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1578
1579 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1580 break;
1581 default:
1582 break;
1583 }
1584
1585 /* Check if there was DownShift, must be checked
1586 * immediately after link-up
1587 */
1588 e1000e_check_downshift(hw);
1589
1590 /* Enable/Disable EEE after link up */
1591 if (hw->phy.type > e1000_phy_82579) {
1592 ret_val = e1000_set_eee_pchlan(hw);
1593 if (ret_val)
1594 return ret_val;
1595 }
1596
1597 /* If we are forcing speed/duplex, then we simply return since
1598 * we have already determined whether we have link or not.
1599 */
1600 if (!mac->autoneg)
1601 return -E1000_ERR_CONFIG;
1602
1603 /* Auto-Neg is enabled. Auto Speed Detection takes care
1604 * of MAC speed/duplex configuration. So we only need to
1605 * configure Collision Distance in the MAC.
1606 */
1607 mac->ops.config_collision_dist(hw);
1608
1609 /* Configure Flow Control now that Auto-Neg has completed.
1610 * First, we need to restore the desired flow control
1611 * settings because we may have had to re-autoneg with a
1612 * different link partner.
1613 */
1614 ret_val = e1000e_config_fc_after_link_up(hw);
1615 if (ret_val)
1616 e_dbg("Error configuring flow control\n");
1617
1618 return ret_val;
1619
1620 out:
1621 mac->get_link_status = true;
1622 return ret_val;
1623 }
1624
1625 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1626 {
1627 struct e1000_hw *hw = &adapter->hw;
1628 s32 rc;
1629
1630 rc = e1000_init_mac_params_ich8lan(hw);
1631 if (rc)
1632 return rc;
1633
1634 rc = e1000_init_nvm_params_ich8lan(hw);
1635 if (rc)
1636 return rc;
1637
1638 switch (hw->mac.type) {
1639 case e1000_ich8lan:
1640 case e1000_ich9lan:
1641 case e1000_ich10lan:
1642 rc = e1000_init_phy_params_ich8lan(hw);
1643 break;
1644 case e1000_pchlan:
1645 case e1000_pch2lan:
1646 case e1000_pch_lpt:
1647 case e1000_pch_spt:
1648 case e1000_pch_cnp:
1649 case e1000_pch_tgp:
1650 case e1000_pch_adp:
1651 rc = e1000_init_phy_params_pchlan(hw);
1652 break;
1653 default:
1654 break;
1655 }
1656 if (rc)
1657 return rc;
1658
1659 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1660 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1661 */
1662 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1663 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1664 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1665 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1666 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1667
1668 hw->mac.ops.blink_led = NULL;
1669 }
1670
1671 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1672 (adapter->hw.phy.type != e1000_phy_ife))
1673 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1674
1675 /* Enable workaround for 82579 w/ ME enabled */
1676 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1677 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1678 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1679
1680 return 0;
1681 }
1682
1683 static DEFINE_MUTEX(nvm_mutex);
1684
1685 /**
1686 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1687 * @hw: pointer to the HW structure
1688 *
1689 * Acquires the mutex for performing NVM operations.
1690 **/
1691 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1692 {
1693 mutex_lock(&nvm_mutex);
1694
1695 return 0;
1696 }
1697
1698 /**
1699 * e1000_release_nvm_ich8lan - Release NVM mutex
1700 * @hw: pointer to the HW structure
1701 *
1702 * Releases the mutex used while performing NVM operations.
1703 **/
1704 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1705 {
1706 mutex_unlock(&nvm_mutex);
1707 }
1708
1709 /**
1710 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1711 * @hw: pointer to the HW structure
1712 *
1713 * Acquires the software control flag for performing PHY and select
1714 * MAC CSR accesses.
1715 **/
1716 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1717 {
1718 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1719 s32 ret_val = 0;
1720
1721 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1722 &hw->adapter->state)) {
1723 e_dbg("contention for Phy access\n");
1724 return -E1000_ERR_PHY;
1725 }
1726
1727 while (timeout) {
1728 extcnf_ctrl = er32(EXTCNF_CTRL);
1729 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1730 break;
1731
1732 mdelay(1);
1733 timeout--;
1734 }
1735
1736 if (!timeout) {
1737 e_dbg("SW has already locked the resource.\n");
1738 ret_val = -E1000_ERR_CONFIG;
1739 goto out;
1740 }
1741
1742 timeout = SW_FLAG_TIMEOUT;
1743
1744 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1745 ew32(EXTCNF_CTRL, extcnf_ctrl);
1746
1747 while (timeout) {
1748 extcnf_ctrl = er32(EXTCNF_CTRL);
1749 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1750 break;
1751
1752 mdelay(1);
1753 timeout--;
1754 }
1755
1756 if (!timeout) {
1757 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1758 er32(FWSM), extcnf_ctrl);
1759 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1760 ew32(EXTCNF_CTRL, extcnf_ctrl);
1761 ret_val = -E1000_ERR_CONFIG;
1762 goto out;
1763 }
1764
1765 out:
1766 if (ret_val)
1767 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1768
1769 return ret_val;
1770 }
1771
1772 /**
1773 * e1000_release_swflag_ich8lan - Release software control flag
1774 * @hw: pointer to the HW structure
1775 *
1776 * Releases the software control flag for performing PHY and select
1777 * MAC CSR accesses.
1778 **/
1779 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1780 {
1781 u32 extcnf_ctrl;
1782
1783 extcnf_ctrl = er32(EXTCNF_CTRL);
1784
1785 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1786 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1787 ew32(EXTCNF_CTRL, extcnf_ctrl);
1788 } else {
1789 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1790 }
1791
1792 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1793 }
1794
1795 /**
1796 * e1000_check_mng_mode_ich8lan - Checks management mode
1797 * @hw: pointer to the HW structure
1798 *
1799 * This checks if the adapter has any manageability enabled.
1800 * This is a function pointer entry point only called by read/write
1801 * routines for the PHY and NVM parts.
1802 **/
1803 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1804 {
1805 u32 fwsm;
1806
1807 fwsm = er32(FWSM);
1808 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1809 ((fwsm & E1000_FWSM_MODE_MASK) ==
1810 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1811 }
1812
1813 /**
1814 * e1000_check_mng_mode_pchlan - Checks management mode
1815 * @hw: pointer to the HW structure
1816 *
1817 * This checks if the adapter has iAMT enabled.
1818 * This is a function pointer entry point only called by read/write
1819 * routines for the PHY and NVM parts.
1820 **/
1821 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1822 {
1823 u32 fwsm;
1824
1825 fwsm = er32(FWSM);
1826 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1827 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1828 }
1829
1830 /**
1831 * e1000_rar_set_pch2lan - Set receive address register
1832 * @hw: pointer to the HW structure
1833 * @addr: pointer to the receive address
1834 * @index: receive address array register
1835 *
1836 * Sets the receive address array register at index to the address passed
1837 * in by addr. For 82579, RAR[0] is the base address register that is to
1838 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1839 * Use SHRA[0-3] in place of those reserved for ME.
1840 **/
1841 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1842 {
1843 u32 rar_low, rar_high;
1844
1845 /* HW expects these in little endian so we reverse the byte order
1846 * from network order (big endian) to little endian
1847 */
1848 rar_low = ((u32)addr[0] |
1849 ((u32)addr[1] << 8) |
1850 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1851
1852 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1853
1854 /* If MAC address zero, no need to set the AV bit */
1855 if (rar_low || rar_high)
1856 rar_high |= E1000_RAH_AV;
1857
1858 if (index == 0) {
1859 ew32(RAL(index), rar_low);
1860 e1e_flush();
1861 ew32(RAH(index), rar_high);
1862 e1e_flush();
1863 return 0;
1864 }
1865
1866 /* RAR[1-6] are owned by manageability. Skip those and program the
1867 * next address into the SHRA register array.
1868 */
1869 if (index < (u32)(hw->mac.rar_entry_count)) {
1870 s32 ret_val;
1871
1872 ret_val = e1000_acquire_swflag_ich8lan(hw);
1873 if (ret_val)
1874 goto out;
1875
1876 ew32(SHRAL(index - 1), rar_low);
1877 e1e_flush();
1878 ew32(SHRAH(index - 1), rar_high);
1879 e1e_flush();
1880
1881 e1000_release_swflag_ich8lan(hw);
1882
1883 /* verify the register updates */
1884 if ((er32(SHRAL(index - 1)) == rar_low) &&
1885 (er32(SHRAH(index - 1)) == rar_high))
1886 return 0;
1887
1888 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1889 (index - 1), er32(FWSM));
1890 }
1891
1892 out:
1893 e_dbg("Failed to write receive address at index %d\n", index);
1894 return -E1000_ERR_CONFIG;
1895 }
1896
1897 /**
1898 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1899 * @hw: pointer to the HW structure
1900 *
1901 * Get the number of available receive registers that the Host can
1902 * program. SHRA[0-10] are the shared receive address registers
1903 * that are shared between the Host and manageability engine (ME).
1904 * ME can reserve any number of addresses and the host needs to be
1905 * able to tell how many available registers it has access to.
1906 **/
1907 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1908 {
1909 u32 wlock_mac;
1910 u32 num_entries;
1911
1912 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1913 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1914
1915 switch (wlock_mac) {
1916 case 0:
1917 /* All SHRA[0..10] and RAR[0] available */
1918 num_entries = hw->mac.rar_entry_count;
1919 break;
1920 case 1:
1921 /* Only RAR[0] available */
1922 num_entries = 1;
1923 break;
1924 default:
1925 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1926 num_entries = wlock_mac + 1;
1927 break;
1928 }
1929
1930 return num_entries;
1931 }
1932
1933 /**
1934 * e1000_rar_set_pch_lpt - Set receive address registers
1935 * @hw: pointer to the HW structure
1936 * @addr: pointer to the receive address
1937 * @index: receive address array register
1938 *
1939 * Sets the receive address register array at index to the address passed
1940 * in by addr. For LPT, RAR[0] is the base address register that is to
1941 * contain the MAC address. SHRA[0-10] are the shared receive address
1942 * registers that are shared between the Host and manageability engine (ME).
1943 **/
1944 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1945 {
1946 u32 rar_low, rar_high;
1947 u32 wlock_mac;
1948
1949 /* HW expects these in little endian so we reverse the byte order
1950 * from network order (big endian) to little endian
1951 */
1952 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1953 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1954
1955 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1956
1957 /* If MAC address zero, no need to set the AV bit */
1958 if (rar_low || rar_high)
1959 rar_high |= E1000_RAH_AV;
1960
1961 if (index == 0) {
1962 ew32(RAL(index), rar_low);
1963 e1e_flush();
1964 ew32(RAH(index), rar_high);
1965 e1e_flush();
1966 return 0;
1967 }
1968
1969 /* The manageability engine (ME) can lock certain SHRAR registers that
1970 * it is using - those registers are unavailable for use.
1971 */
1972 if (index < hw->mac.rar_entry_count) {
1973 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1974 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1975
1976 /* Check if all SHRAR registers are locked */
1977 if (wlock_mac == 1)
1978 goto out;
1979
1980 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1981 s32 ret_val;
1982
1983 ret_val = e1000_acquire_swflag_ich8lan(hw);
1984
1985 if (ret_val)
1986 goto out;
1987
1988 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1989 e1e_flush();
1990 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1991 e1e_flush();
1992
1993 e1000_release_swflag_ich8lan(hw);
1994
1995 /* verify the register updates */
1996 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1997 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1998 return 0;
1999 }
2000 }
2001
2002 out:
2003 e_dbg("Failed to write receive address at index %d\n", index);
2004 return -E1000_ERR_CONFIG;
2005 }
2006
2007 /**
2008 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2009 * @hw: pointer to the HW structure
2010 *
2011 * Checks if firmware is blocking the reset of the PHY.
2012 * This is a function pointer entry point only called by
2013 * reset routines.
2014 **/
2015 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2016 {
2017 bool blocked = false;
2018 int i = 0;
2019
2020 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2021 (i++ < 30))
2022 usleep_range(10000, 11000);
2023 return blocked ? E1000_BLK_PHY_RESET : 0;
2024 }
2025
2026 /**
2027 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2028 * @hw: pointer to the HW structure
2029 *
2030 * Assumes semaphore already acquired.
2031 *
2032 **/
2033 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2034 {
2035 u16 phy_data;
2036 u32 strap = er32(STRAP);
2037 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2038 E1000_STRAP_SMT_FREQ_SHIFT;
2039 s32 ret_val;
2040
2041 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2042
2043 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2044 if (ret_val)
2045 return ret_val;
2046
2047 phy_data &= ~HV_SMB_ADDR_MASK;
2048 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2049 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2050
2051 if (hw->phy.type == e1000_phy_i217) {
2052 /* Restore SMBus frequency */
2053 if (freq--) {
2054 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2055 phy_data |= (freq & BIT(0)) <<
2056 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2057 phy_data |= (freq & BIT(1)) <<
2058 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2059 } else {
2060 e_dbg("Unsupported SMB frequency in PHY\n");
2061 }
2062 }
2063
2064 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2065 }
2066
2067 /**
2068 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2069 * @hw: pointer to the HW structure
2070 *
2071 * SW should configure the LCD from the NVM extended configuration region
2072 * as a workaround for certain parts.
2073 **/
2074 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2075 {
2076 struct e1000_phy_info *phy = &hw->phy;
2077 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2078 s32 ret_val = 0;
2079 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2080
2081 /* Initialize the PHY from the NVM on ICH platforms. This
2082 * is needed due to an issue where the NVM configuration is
2083 * not properly autoloaded after power transitions.
2084 * Therefore, after each PHY reset, we will load the
2085 * configuration data out of the NVM manually.
2086 */
2087 switch (hw->mac.type) {
2088 case e1000_ich8lan:
2089 if (phy->type != e1000_phy_igp_3)
2090 return ret_val;
2091
2092 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2093 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2094 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2095 break;
2096 }
2097 fallthrough;
2098 case e1000_pchlan:
2099 case e1000_pch2lan:
2100 case e1000_pch_lpt:
2101 case e1000_pch_spt:
2102 case e1000_pch_cnp:
2103 case e1000_pch_tgp:
2104 case e1000_pch_adp:
2105 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2106 break;
2107 default:
2108 return ret_val;
2109 }
2110
2111 ret_val = hw->phy.ops.acquire(hw);
2112 if (ret_val)
2113 return ret_val;
2114
2115 data = er32(FEXTNVM);
2116 if (!(data & sw_cfg_mask))
2117 goto release;
2118
2119 /* Make sure HW does not configure LCD from PHY
2120 * extended configuration before SW configuration
2121 */
2122 data = er32(EXTCNF_CTRL);
2123 if ((hw->mac.type < e1000_pch2lan) &&
2124 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2125 goto release;
2126
2127 cnf_size = er32(EXTCNF_SIZE);
2128 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2129 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2130 if (!cnf_size)
2131 goto release;
2132
2133 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2134 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2135
2136 if (((hw->mac.type == e1000_pchlan) &&
2137 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2138 (hw->mac.type > e1000_pchlan)) {
2139 /* HW configures the SMBus address and LEDs when the
2140 * OEM and LCD Write Enable bits are set in the NVM.
2141 * When both NVM bits are cleared, SW will configure
2142 * them instead.
2143 */
2144 ret_val = e1000_write_smbus_addr(hw);
2145 if (ret_val)
2146 goto release;
2147
2148 data = er32(LEDCTL);
2149 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2150 (u16)data);
2151 if (ret_val)
2152 goto release;
2153 }
2154
2155 /* Configure LCD from extended configuration region. */
2156
2157 /* cnf_base_addr is in DWORD */
2158 word_addr = (u16)(cnf_base_addr << 1);
2159
2160 for (i = 0; i < cnf_size; i++) {
2161 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2162 if (ret_val)
2163 goto release;
2164
2165 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2166 1, &reg_addr);
2167 if (ret_val)
2168 goto release;
2169
2170 /* Save off the PHY page for future writes. */
2171 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2172 phy_page = reg_data;
2173 continue;
2174 }
2175
2176 reg_addr &= PHY_REG_MASK;
2177 reg_addr |= phy_page;
2178
2179 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2180 if (ret_val)
2181 goto release;
2182 }
2183
2184 release:
2185 hw->phy.ops.release(hw);
2186 return ret_val;
2187 }
2188
2189 /**
2190 * e1000_k1_gig_workaround_hv - K1 Si workaround
2191 * @hw: pointer to the HW structure
2192 * @link: link up bool flag
2193 *
2194 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2195 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2196 * If link is down, the function will restore the default K1 setting located
2197 * in the NVM.
2198 **/
2199 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2200 {
2201 s32 ret_val = 0;
2202 u16 status_reg = 0;
2203 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2204
2205 if (hw->mac.type != e1000_pchlan)
2206 return 0;
2207
2208 /* Wrap the whole flow with the sw flag */
2209 ret_val = hw->phy.ops.acquire(hw);
2210 if (ret_val)
2211 return ret_val;
2212
2213 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2214 if (link) {
2215 if (hw->phy.type == e1000_phy_82578) {
2216 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2217 &status_reg);
2218 if (ret_val)
2219 goto release;
2220
2221 status_reg &= (BM_CS_STATUS_LINK_UP |
2222 BM_CS_STATUS_RESOLVED |
2223 BM_CS_STATUS_SPEED_MASK);
2224
2225 if (status_reg == (BM_CS_STATUS_LINK_UP |
2226 BM_CS_STATUS_RESOLVED |
2227 BM_CS_STATUS_SPEED_1000))
2228 k1_enable = false;
2229 }
2230
2231 if (hw->phy.type == e1000_phy_82577) {
2232 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2233 if (ret_val)
2234 goto release;
2235
2236 status_reg &= (HV_M_STATUS_LINK_UP |
2237 HV_M_STATUS_AUTONEG_COMPLETE |
2238 HV_M_STATUS_SPEED_MASK);
2239
2240 if (status_reg == (HV_M_STATUS_LINK_UP |
2241 HV_M_STATUS_AUTONEG_COMPLETE |
2242 HV_M_STATUS_SPEED_1000))
2243 k1_enable = false;
2244 }
2245
2246 /* Link stall fix for link up */
2247 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2248 if (ret_val)
2249 goto release;
2250
2251 } else {
2252 /* Link stall fix for link down */
2253 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2254 if (ret_val)
2255 goto release;
2256 }
2257
2258 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2259
2260 release:
2261 hw->phy.ops.release(hw);
2262
2263 return ret_val;
2264 }
2265
2266 /**
2267 * e1000_configure_k1_ich8lan - Configure K1 power state
2268 * @hw: pointer to the HW structure
2269 * @k1_enable: K1 state to configure
2270 *
2271 * Configure the K1 power state based on the provided parameter.
2272 * Assumes semaphore already acquired.
2273 *
2274 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2275 **/
2276 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2277 {
2278 s32 ret_val;
2279 u32 ctrl_reg = 0;
2280 u32 ctrl_ext = 0;
2281 u32 reg = 0;
2282 u16 kmrn_reg = 0;
2283
2284 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2285 &kmrn_reg);
2286 if (ret_val)
2287 return ret_val;
2288
2289 if (k1_enable)
2290 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2291 else
2292 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2293
2294 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2295 kmrn_reg);
2296 if (ret_val)
2297 return ret_val;
2298
2299 usleep_range(20, 40);
2300 ctrl_ext = er32(CTRL_EXT);
2301 ctrl_reg = er32(CTRL);
2302
2303 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2304 reg |= E1000_CTRL_FRCSPD;
2305 ew32(CTRL, reg);
2306
2307 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2308 e1e_flush();
2309 usleep_range(20, 40);
2310 ew32(CTRL, ctrl_reg);
2311 ew32(CTRL_EXT, ctrl_ext);
2312 e1e_flush();
2313 usleep_range(20, 40);
2314
2315 return 0;
2316 }
2317
2318 /**
2319 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2320 * @hw: pointer to the HW structure
2321 * @d0_state: boolean if entering d0 or d3 device state
2322 *
2323 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2324 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2325 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2326 **/
2327 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2328 {
2329 s32 ret_val = 0;
2330 u32 mac_reg;
2331 u16 oem_reg;
2332
2333 if (hw->mac.type < e1000_pchlan)
2334 return ret_val;
2335
2336 ret_val = hw->phy.ops.acquire(hw);
2337 if (ret_val)
2338 return ret_val;
2339
2340 if (hw->mac.type == e1000_pchlan) {
2341 mac_reg = er32(EXTCNF_CTRL);
2342 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2343 goto release;
2344 }
2345
2346 mac_reg = er32(FEXTNVM);
2347 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2348 goto release;
2349
2350 mac_reg = er32(PHY_CTRL);
2351
2352 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2353 if (ret_val)
2354 goto release;
2355
2356 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2357
2358 if (d0_state) {
2359 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2360 oem_reg |= HV_OEM_BITS_GBE_DIS;
2361
2362 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2363 oem_reg |= HV_OEM_BITS_LPLU;
2364 } else {
2365 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2366 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2367 oem_reg |= HV_OEM_BITS_GBE_DIS;
2368
2369 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2370 E1000_PHY_CTRL_NOND0A_LPLU))
2371 oem_reg |= HV_OEM_BITS_LPLU;
2372 }
2373
2374 /* Set Restart auto-neg to activate the bits */
2375 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2376 !hw->phy.ops.check_reset_block(hw))
2377 oem_reg |= HV_OEM_BITS_RESTART_AN;
2378
2379 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2380
2381 release:
2382 hw->phy.ops.release(hw);
2383
2384 return ret_val;
2385 }
2386
2387 /**
2388 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2389 * @hw: pointer to the HW structure
2390 **/
2391 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2392 {
2393 s32 ret_val;
2394 u16 data;
2395
2396 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2397 if (ret_val)
2398 return ret_val;
2399
2400 data |= HV_KMRN_MDIO_SLOW;
2401
2402 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2403
2404 return ret_val;
2405 }
2406
2407 /**
2408 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2409 * @hw: pointer to the HW structure
2410 *
2411 * A series of PHY workarounds to be done after every PHY reset.
2412 **/
2413 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2414 {
2415 s32 ret_val = 0;
2416 u16 phy_data;
2417
2418 if (hw->mac.type != e1000_pchlan)
2419 return 0;
2420
2421 /* Set MDIO slow mode before any other MDIO access */
2422 if (hw->phy.type == e1000_phy_82577) {
2423 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2424 if (ret_val)
2425 return ret_val;
2426 }
2427
2428 if (((hw->phy.type == e1000_phy_82577) &&
2429 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2430 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2431 /* Disable generation of early preamble */
2432 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2433 if (ret_val)
2434 return ret_val;
2435
2436 /* Preamble tuning for SSC */
2437 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2438 if (ret_val)
2439 return ret_val;
2440 }
2441
2442 if (hw->phy.type == e1000_phy_82578) {
2443 /* Return registers to default by doing a soft reset then
2444 * writing 0x3140 to the control register.
2445 */
2446 if (hw->phy.revision < 2) {
2447 e1000e_phy_sw_reset(hw);
2448 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2449 if (ret_val)
2450 return ret_val;
2451 }
2452 }
2453
2454 /* Select page 0 */
2455 ret_val = hw->phy.ops.acquire(hw);
2456 if (ret_val)
2457 return ret_val;
2458
2459 hw->phy.addr = 1;
2460 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2461 hw->phy.ops.release(hw);
2462 if (ret_val)
2463 return ret_val;
2464
2465 /* Configure the K1 Si workaround during phy reset assuming there is
2466 * link so that it disables K1 if link is in 1Gbps.
2467 */
2468 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2469 if (ret_val)
2470 return ret_val;
2471
2472 /* Workaround for link disconnects on a busy hub in half duplex */
2473 ret_val = hw->phy.ops.acquire(hw);
2474 if (ret_val)
2475 return ret_val;
2476 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2477 if (ret_val)
2478 goto release;
2479 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2480 if (ret_val)
2481 goto release;
2482
2483 /* set MSE higher to enable link to stay up when noise is high */
2484 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2485 release:
2486 hw->phy.ops.release(hw);
2487
2488 return ret_val;
2489 }
2490
2491 /**
2492 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2493 * @hw: pointer to the HW structure
2494 **/
2495 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2496 {
2497 u32 mac_reg;
2498 u16 i, phy_reg = 0;
2499 s32 ret_val;
2500
2501 ret_val = hw->phy.ops.acquire(hw);
2502 if (ret_val)
2503 return;
2504 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2505 if (ret_val)
2506 goto release;
2507
2508 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2509 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2510 mac_reg = er32(RAL(i));
2511 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2512 (u16)(mac_reg & 0xFFFF));
2513 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2514 (u16)((mac_reg >> 16) & 0xFFFF));
2515
2516 mac_reg = er32(RAH(i));
2517 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2518 (u16)(mac_reg & 0xFFFF));
2519 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2520 (u16)((mac_reg & E1000_RAH_AV)
2521 >> 16));
2522 }
2523
2524 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2525
2526 release:
2527 hw->phy.ops.release(hw);
2528 }
2529
2530 /**
2531 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2532 * with 82579 PHY
2533 * @hw: pointer to the HW structure
2534 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2535 **/
2536 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2537 {
2538 s32 ret_val = 0;
2539 u16 phy_reg, data;
2540 u32 mac_reg;
2541 u16 i;
2542
2543 if (hw->mac.type < e1000_pch2lan)
2544 return 0;
2545
2546 /* disable Rx path while enabling/disabling workaround */
2547 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2548 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2549 if (ret_val)
2550 return ret_val;
2551
2552 if (enable) {
2553 /* Write Rx addresses (rar_entry_count for RAL/H, and
2554 * SHRAL/H) and initial CRC values to the MAC
2555 */
2556 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2557 u8 mac_addr[ETH_ALEN] = { 0 };
2558 u32 addr_high, addr_low;
2559
2560 addr_high = er32(RAH(i));
2561 if (!(addr_high & E1000_RAH_AV))
2562 continue;
2563 addr_low = er32(RAL(i));
2564 mac_addr[0] = (addr_low & 0xFF);
2565 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2566 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2567 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2568 mac_addr[4] = (addr_high & 0xFF);
2569 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2570
2571 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2572 }
2573
2574 /* Write Rx addresses to the PHY */
2575 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2576
2577 /* Enable jumbo frame workaround in the MAC */
2578 mac_reg = er32(FFLT_DBG);
2579 mac_reg &= ~BIT(14);
2580 mac_reg |= (7 << 15);
2581 ew32(FFLT_DBG, mac_reg);
2582
2583 mac_reg = er32(RCTL);
2584 mac_reg |= E1000_RCTL_SECRC;
2585 ew32(RCTL, mac_reg);
2586
2587 ret_val = e1000e_read_kmrn_reg(hw,
2588 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2589 &data);
2590 if (ret_val)
2591 return ret_val;
2592 ret_val = e1000e_write_kmrn_reg(hw,
2593 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2594 data | BIT(0));
2595 if (ret_val)
2596 return ret_val;
2597 ret_val = e1000e_read_kmrn_reg(hw,
2598 E1000_KMRNCTRLSTA_HD_CTRL,
2599 &data);
2600 if (ret_val)
2601 return ret_val;
2602 data &= ~(0xF << 8);
2603 data |= (0xB << 8);
2604 ret_val = e1000e_write_kmrn_reg(hw,
2605 E1000_KMRNCTRLSTA_HD_CTRL,
2606 data);
2607 if (ret_val)
2608 return ret_val;
2609
2610 /* Enable jumbo frame workaround in the PHY */
2611 e1e_rphy(hw, PHY_REG(769, 23), &data);
2612 data &= ~(0x7F << 5);
2613 data |= (0x37 << 5);
2614 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2615 if (ret_val)
2616 return ret_val;
2617 e1e_rphy(hw, PHY_REG(769, 16), &data);
2618 data &= ~BIT(13);
2619 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2620 if (ret_val)
2621 return ret_val;
2622 e1e_rphy(hw, PHY_REG(776, 20), &data);
2623 data &= ~(0x3FF << 2);
2624 data |= (E1000_TX_PTR_GAP << 2);
2625 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2626 if (ret_val)
2627 return ret_val;
2628 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2629 if (ret_val)
2630 return ret_val;
2631 e1e_rphy(hw, HV_PM_CTRL, &data);
2632 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2633 if (ret_val)
2634 return ret_val;
2635 } else {
2636 /* Write MAC register values back to h/w defaults */
2637 mac_reg = er32(FFLT_DBG);
2638 mac_reg &= ~(0xF << 14);
2639 ew32(FFLT_DBG, mac_reg);
2640
2641 mac_reg = er32(RCTL);
2642 mac_reg &= ~E1000_RCTL_SECRC;
2643 ew32(RCTL, mac_reg);
2644
2645 ret_val = e1000e_read_kmrn_reg(hw,
2646 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2647 &data);
2648 if (ret_val)
2649 return ret_val;
2650 ret_val = e1000e_write_kmrn_reg(hw,
2651 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2652 data & ~BIT(0));
2653 if (ret_val)
2654 return ret_val;
2655 ret_val = e1000e_read_kmrn_reg(hw,
2656 E1000_KMRNCTRLSTA_HD_CTRL,
2657 &data);
2658 if (ret_val)
2659 return ret_val;
2660 data &= ~(0xF << 8);
2661 data |= (0xB << 8);
2662 ret_val = e1000e_write_kmrn_reg(hw,
2663 E1000_KMRNCTRLSTA_HD_CTRL,
2664 data);
2665 if (ret_val)
2666 return ret_val;
2667
2668 /* Write PHY register values back to h/w defaults */
2669 e1e_rphy(hw, PHY_REG(769, 23), &data);
2670 data &= ~(0x7F << 5);
2671 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2672 if (ret_val)
2673 return ret_val;
2674 e1e_rphy(hw, PHY_REG(769, 16), &data);
2675 data |= BIT(13);
2676 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2677 if (ret_val)
2678 return ret_val;
2679 e1e_rphy(hw, PHY_REG(776, 20), &data);
2680 data &= ~(0x3FF << 2);
2681 data |= (0x8 << 2);
2682 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2683 if (ret_val)
2684 return ret_val;
2685 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2686 if (ret_val)
2687 return ret_val;
2688 e1e_rphy(hw, HV_PM_CTRL, &data);
2689 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2690 if (ret_val)
2691 return ret_val;
2692 }
2693
2694 /* re-enable Rx path after enabling/disabling workaround */
2695 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2696 }
2697
2698 /**
2699 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2700 * @hw: pointer to the HW structure
2701 *
2702 * A series of PHY workarounds to be done after every PHY reset.
2703 **/
2704 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2705 {
2706 s32 ret_val = 0;
2707
2708 if (hw->mac.type != e1000_pch2lan)
2709 return 0;
2710
2711 /* Set MDIO slow mode before any other MDIO access */
2712 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2713 if (ret_val)
2714 return ret_val;
2715
2716 ret_val = hw->phy.ops.acquire(hw);
2717 if (ret_val)
2718 return ret_val;
2719 /* set MSE higher to enable link to stay up when noise is high */
2720 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2721 if (ret_val)
2722 goto release;
2723 /* drop link after 5 times MSE threshold was reached */
2724 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2725 release:
2726 hw->phy.ops.release(hw);
2727
2728 return ret_val;
2729 }
2730
2731 /**
2732 * e1000_k1_gig_workaround_lv - K1 Si workaround
2733 * @hw: pointer to the HW structure
2734 *
2735 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2736 * Disable K1 in 1000Mbps and 100Mbps
2737 **/
2738 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2739 {
2740 s32 ret_val = 0;
2741 u16 status_reg = 0;
2742
2743 if (hw->mac.type != e1000_pch2lan)
2744 return 0;
2745
2746 /* Set K1 beacon duration based on 10Mbs speed */
2747 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2748 if (ret_val)
2749 return ret_val;
2750
2751 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2752 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2753 if (status_reg &
2754 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2755 u16 pm_phy_reg;
2756
2757 /* LV 1G/100 Packet drop issue wa */
2758 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2759 if (ret_val)
2760 return ret_val;
2761 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2762 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2763 if (ret_val)
2764 return ret_val;
2765 } else {
2766 u32 mac_reg;
2767
2768 mac_reg = er32(FEXTNVM4);
2769 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2770 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2771 ew32(FEXTNVM4, mac_reg);
2772 }
2773 }
2774
2775 return ret_val;
2776 }
2777
2778 /**
2779 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2780 * @hw: pointer to the HW structure
2781 * @gate: boolean set to true to gate, false to ungate
2782 *
2783 * Gate/ungate the automatic PHY configuration via hardware; perform
2784 * the configuration via software instead.
2785 **/
2786 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2787 {
2788 u32 extcnf_ctrl;
2789
2790 if (hw->mac.type < e1000_pch2lan)
2791 return;
2792
2793 extcnf_ctrl = er32(EXTCNF_CTRL);
2794
2795 if (gate)
2796 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2797 else
2798 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2799
2800 ew32(EXTCNF_CTRL, extcnf_ctrl);
2801 }
2802
2803 /**
2804 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2805 * @hw: pointer to the HW structure
2806 *
2807 * Check the appropriate indication the MAC has finished configuring the
2808 * PHY after a software reset.
2809 **/
2810 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2811 {
2812 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2813
2814 /* Wait for basic configuration completes before proceeding */
2815 do {
2816 data = er32(STATUS);
2817 data &= E1000_STATUS_LAN_INIT_DONE;
2818 usleep_range(100, 200);
2819 } while ((!data) && --loop);
2820
2821 /* If basic configuration is incomplete before the above loop
2822 * count reaches 0, loading the configuration from NVM will
2823 * leave the PHY in a bad state possibly resulting in no link.
2824 */
2825 if (loop == 0)
2826 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2827
2828 /* Clear the Init Done bit for the next init event */
2829 data = er32(STATUS);
2830 data &= ~E1000_STATUS_LAN_INIT_DONE;
2831 ew32(STATUS, data);
2832 }
2833
2834 /**
2835 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2836 * @hw: pointer to the HW structure
2837 **/
2838 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2839 {
2840 s32 ret_val = 0;
2841 u16 reg;
2842
2843 if (hw->phy.ops.check_reset_block(hw))
2844 return 0;
2845
2846 /* Allow time for h/w to get to quiescent state after reset */
2847 usleep_range(10000, 11000);
2848
2849 /* Perform any necessary post-reset workarounds */
2850 switch (hw->mac.type) {
2851 case e1000_pchlan:
2852 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2853 if (ret_val)
2854 return ret_val;
2855 break;
2856 case e1000_pch2lan:
2857 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2858 if (ret_val)
2859 return ret_val;
2860 break;
2861 default:
2862 break;
2863 }
2864
2865 /* Clear the host wakeup bit after lcd reset */
2866 if (hw->mac.type >= e1000_pchlan) {
2867 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2868 reg &= ~BM_WUC_HOST_WU_BIT;
2869 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2870 }
2871
2872 /* Configure the LCD with the extended configuration region in NVM */
2873 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2874 if (ret_val)
2875 return ret_val;
2876
2877 /* Configure the LCD with the OEM bits in NVM */
2878 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2879
2880 if (hw->mac.type == e1000_pch2lan) {
2881 /* Ungate automatic PHY configuration on non-managed 82579 */
2882 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2883 usleep_range(10000, 11000);
2884 e1000_gate_hw_phy_config_ich8lan(hw, false);
2885 }
2886
2887 /* Set EEE LPI Update Timer to 200usec */
2888 ret_val = hw->phy.ops.acquire(hw);
2889 if (ret_val)
2890 return ret_val;
2891 ret_val = e1000_write_emi_reg_locked(hw,
2892 I82579_LPI_UPDATE_TIMER,
2893 0x1387);
2894 hw->phy.ops.release(hw);
2895 }
2896
2897 return ret_val;
2898 }
2899
2900 /**
2901 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2902 * @hw: pointer to the HW structure
2903 *
2904 * Resets the PHY
2905 * This is a function pointer entry point called by drivers
2906 * or other shared routines.
2907 **/
2908 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2909 {
2910 s32 ret_val = 0;
2911
2912 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2913 if ((hw->mac.type == e1000_pch2lan) &&
2914 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2915 e1000_gate_hw_phy_config_ich8lan(hw, true);
2916
2917 ret_val = e1000e_phy_hw_reset_generic(hw);
2918 if (ret_val)
2919 return ret_val;
2920
2921 return e1000_post_phy_reset_ich8lan(hw);
2922 }
2923
2924 /**
2925 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2926 * @hw: pointer to the HW structure
2927 * @active: true to enable LPLU, false to disable
2928 *
2929 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2930 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2931 * the phy speed. This function will manually set the LPLU bit and restart
2932 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2933 * since it configures the same bit.
2934 **/
2935 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2936 {
2937 s32 ret_val;
2938 u16 oem_reg;
2939
2940 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2941 if (ret_val)
2942 return ret_val;
2943
2944 if (active)
2945 oem_reg |= HV_OEM_BITS_LPLU;
2946 else
2947 oem_reg &= ~HV_OEM_BITS_LPLU;
2948
2949 if (!hw->phy.ops.check_reset_block(hw))
2950 oem_reg |= HV_OEM_BITS_RESTART_AN;
2951
2952 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2953 }
2954
2955 /**
2956 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2957 * @hw: pointer to the HW structure
2958 * @active: true to enable LPLU, false to disable
2959 *
2960 * Sets the LPLU D0 state according to the active flag. When
2961 * activating LPLU this function also disables smart speed
2962 * and vice versa. LPLU will not be activated unless the
2963 * device autonegotiation advertisement meets standards of
2964 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2965 * This is a function pointer entry point only called by
2966 * PHY setup routines.
2967 **/
2968 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2969 {
2970 struct e1000_phy_info *phy = &hw->phy;
2971 u32 phy_ctrl;
2972 s32 ret_val = 0;
2973 u16 data;
2974
2975 if (phy->type == e1000_phy_ife)
2976 return 0;
2977
2978 phy_ctrl = er32(PHY_CTRL);
2979
2980 if (active) {
2981 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2982 ew32(PHY_CTRL, phy_ctrl);
2983
2984 if (phy->type != e1000_phy_igp_3)
2985 return 0;
2986
2987 /* Call gig speed drop workaround on LPLU before accessing
2988 * any PHY registers
2989 */
2990 if (hw->mac.type == e1000_ich8lan)
2991 e1000e_gig_downshift_workaround_ich8lan(hw);
2992
2993 /* When LPLU is enabled, we should disable SmartSpeed */
2994 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2995 if (ret_val)
2996 return ret_val;
2997 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2998 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2999 if (ret_val)
3000 return ret_val;
3001 } else {
3002 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3003 ew32(PHY_CTRL, phy_ctrl);
3004
3005 if (phy->type != e1000_phy_igp_3)
3006 return 0;
3007
3008 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3009 * during Dx states where the power conservation is most
3010 * important. During driver activity we should enable
3011 * SmartSpeed, so performance is maintained.
3012 */
3013 if (phy->smart_speed == e1000_smart_speed_on) {
3014 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3015 &data);
3016 if (ret_val)
3017 return ret_val;
3018
3019 data |= IGP01E1000_PSCFR_SMART_SPEED;
3020 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3021 data);
3022 if (ret_val)
3023 return ret_val;
3024 } else if (phy->smart_speed == e1000_smart_speed_off) {
3025 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3026 &data);
3027 if (ret_val)
3028 return ret_val;
3029
3030 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3031 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3032 data);
3033 if (ret_val)
3034 return ret_val;
3035 }
3036 }
3037
3038 return 0;
3039 }
3040
3041 /**
3042 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3043 * @hw: pointer to the HW structure
3044 * @active: true to enable LPLU, false to disable
3045 *
3046 * Sets the LPLU D3 state according to the active flag. When
3047 * activating LPLU this function also disables smart speed
3048 * and vice versa. LPLU will not be activated unless the
3049 * device autonegotiation advertisement meets standards of
3050 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3051 * This is a function pointer entry point only called by
3052 * PHY setup routines.
3053 **/
3054 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3055 {
3056 struct e1000_phy_info *phy = &hw->phy;
3057 u32 phy_ctrl;
3058 s32 ret_val = 0;
3059 u16 data;
3060
3061 phy_ctrl = er32(PHY_CTRL);
3062
3063 if (!active) {
3064 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3065 ew32(PHY_CTRL, phy_ctrl);
3066
3067 if (phy->type != e1000_phy_igp_3)
3068 return 0;
3069
3070 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3071 * during Dx states where the power conservation is most
3072 * important. During driver activity we should enable
3073 * SmartSpeed, so performance is maintained.
3074 */
3075 if (phy->smart_speed == e1000_smart_speed_on) {
3076 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3077 &data);
3078 if (ret_val)
3079 return ret_val;
3080
3081 data |= IGP01E1000_PSCFR_SMART_SPEED;
3082 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3083 data);
3084 if (ret_val)
3085 return ret_val;
3086 } else if (phy->smart_speed == e1000_smart_speed_off) {
3087 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3088 &data);
3089 if (ret_val)
3090 return ret_val;
3091
3092 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3093 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3094 data);
3095 if (ret_val)
3096 return ret_val;
3097 }
3098 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3099 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3100 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3101 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3102 ew32(PHY_CTRL, phy_ctrl);
3103
3104 if (phy->type != e1000_phy_igp_3)
3105 return 0;
3106
3107 /* Call gig speed drop workaround on LPLU before accessing
3108 * any PHY registers
3109 */
3110 if (hw->mac.type == e1000_ich8lan)
3111 e1000e_gig_downshift_workaround_ich8lan(hw);
3112
3113 /* When LPLU is enabled, we should disable SmartSpeed */
3114 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3115 if (ret_val)
3116 return ret_val;
3117
3118 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3119 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3120 }
3121
3122 return ret_val;
3123 }
3124
3125 /**
3126 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3127 * @hw: pointer to the HW structure
3128 * @bank: pointer to the variable that returns the active bank
3129 *
3130 * Reads signature byte from the NVM using the flash access registers.
3131 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3132 **/
3133 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3134 {
3135 u32 eecd;
3136 struct e1000_nvm_info *nvm = &hw->nvm;
3137 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3138 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3139 u32 nvm_dword = 0;
3140 u8 sig_byte = 0;
3141 s32 ret_val;
3142
3143 switch (hw->mac.type) {
3144 case e1000_pch_spt:
3145 case e1000_pch_cnp:
3146 case e1000_pch_tgp:
3147 case e1000_pch_adp:
3148 bank1_offset = nvm->flash_bank_size;
3149 act_offset = E1000_ICH_NVM_SIG_WORD;
3150
3151 /* set bank to 0 in case flash read fails */
3152 *bank = 0;
3153
3154 /* Check bank 0 */
3155 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3156 &nvm_dword);
3157 if (ret_val)
3158 return ret_val;
3159 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3160 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3161 E1000_ICH_NVM_SIG_VALUE) {
3162 *bank = 0;
3163 return 0;
3164 }
3165
3166 /* Check bank 1 */
3167 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3168 bank1_offset,
3169 &nvm_dword);
3170 if (ret_val)
3171 return ret_val;
3172 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3173 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3174 E1000_ICH_NVM_SIG_VALUE) {
3175 *bank = 1;
3176 return 0;
3177 }
3178
3179 e_dbg("ERROR: No valid NVM bank present\n");
3180 return -E1000_ERR_NVM;
3181 case e1000_ich8lan:
3182 case e1000_ich9lan:
3183 eecd = er32(EECD);
3184 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3185 E1000_EECD_SEC1VAL_VALID_MASK) {
3186 if (eecd & E1000_EECD_SEC1VAL)
3187 *bank = 1;
3188 else
3189 *bank = 0;
3190
3191 return 0;
3192 }
3193 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3194 fallthrough;
3195 default:
3196 /* set bank to 0 in case flash read fails */
3197 *bank = 0;
3198
3199 /* Check bank 0 */
3200 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3201 &sig_byte);
3202 if (ret_val)
3203 return ret_val;
3204 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3205 E1000_ICH_NVM_SIG_VALUE) {
3206 *bank = 0;
3207 return 0;
3208 }
3209
3210 /* Check bank 1 */
3211 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3212 bank1_offset,
3213 &sig_byte);
3214 if (ret_val)
3215 return ret_val;
3216 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3217 E1000_ICH_NVM_SIG_VALUE) {
3218 *bank = 1;
3219 return 0;
3220 }
3221
3222 e_dbg("ERROR: No valid NVM bank present\n");
3223 return -E1000_ERR_NVM;
3224 }
3225 }
3226
3227 /**
3228 * e1000_read_nvm_spt - NVM access for SPT
3229 * @hw: pointer to the HW structure
3230 * @offset: The offset (in bytes) of the word(s) to read.
3231 * @words: Size of data to read in words.
3232 * @data: pointer to the word(s) to read at offset.
3233 *
3234 * Reads a word(s) from the NVM
3235 **/
3236 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3237 u16 *data)
3238 {
3239 struct e1000_nvm_info *nvm = &hw->nvm;
3240 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3241 u32 act_offset;
3242 s32 ret_val = 0;
3243 u32 bank = 0;
3244 u32 dword = 0;
3245 u16 offset_to_read;
3246 u16 i;
3247
3248 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3249 (words == 0)) {
3250 e_dbg("nvm parameter(s) out of bounds\n");
3251 ret_val = -E1000_ERR_NVM;
3252 goto out;
3253 }
3254
3255 nvm->ops.acquire(hw);
3256
3257 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3258 if (ret_val) {
3259 e_dbg("Could not detect valid bank, assuming bank 0\n");
3260 bank = 0;
3261 }
3262
3263 act_offset = (bank) ? nvm->flash_bank_size : 0;
3264 act_offset += offset;
3265
3266 ret_val = 0;
3267
3268 for (i = 0; i < words; i += 2) {
3269 if (words - i == 1) {
3270 if (dev_spec->shadow_ram[offset + i].modified) {
3271 data[i] =
3272 dev_spec->shadow_ram[offset + i].value;
3273 } else {
3274 offset_to_read = act_offset + i -
3275 ((act_offset + i) % 2);
3276 ret_val =
3277 e1000_read_flash_dword_ich8lan(hw,
3278 offset_to_read,
3279 &dword);
3280 if (ret_val)
3281 break;
3282 if ((act_offset + i) % 2 == 0)
3283 data[i] = (u16)(dword & 0xFFFF);
3284 else
3285 data[i] = (u16)((dword >> 16) & 0xFFFF);
3286 }
3287 } else {
3288 offset_to_read = act_offset + i;
3289 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3290 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3291 ret_val =
3292 e1000_read_flash_dword_ich8lan(hw,
3293 offset_to_read,
3294 &dword);
3295 if (ret_val)
3296 break;
3297 }
3298 if (dev_spec->shadow_ram[offset + i].modified)
3299 data[i] =
3300 dev_spec->shadow_ram[offset + i].value;
3301 else
3302 data[i] = (u16)(dword & 0xFFFF);
3303 if (dev_spec->shadow_ram[offset + i].modified)
3304 data[i + 1] =
3305 dev_spec->shadow_ram[offset + i + 1].value;
3306 else
3307 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3308 }
3309 }
3310
3311 nvm->ops.release(hw);
3312
3313 out:
3314 if (ret_val)
3315 e_dbg("NVM read error: %d\n", ret_val);
3316
3317 return ret_val;
3318 }
3319
3320 /**
3321 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3322 * @hw: pointer to the HW structure
3323 * @offset: The offset (in bytes) of the word(s) to read.
3324 * @words: Size of data to read in words
3325 * @data: Pointer to the word(s) to read at offset.
3326 *
3327 * Reads a word(s) from the NVM using the flash access registers.
3328 **/
3329 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3330 u16 *data)
3331 {
3332 struct e1000_nvm_info *nvm = &hw->nvm;
3333 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3334 u32 act_offset;
3335 s32 ret_val = 0;
3336 u32 bank = 0;
3337 u16 i, word;
3338
3339 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3340 (words == 0)) {
3341 e_dbg("nvm parameter(s) out of bounds\n");
3342 ret_val = -E1000_ERR_NVM;
3343 goto out;
3344 }
3345
3346 nvm->ops.acquire(hw);
3347
3348 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3349 if (ret_val) {
3350 e_dbg("Could not detect valid bank, assuming bank 0\n");
3351 bank = 0;
3352 }
3353
3354 act_offset = (bank) ? nvm->flash_bank_size : 0;
3355 act_offset += offset;
3356
3357 ret_val = 0;
3358 for (i = 0; i < words; i++) {
3359 if (dev_spec->shadow_ram[offset + i].modified) {
3360 data[i] = dev_spec->shadow_ram[offset + i].value;
3361 } else {
3362 ret_val = e1000_read_flash_word_ich8lan(hw,
3363 act_offset + i,
3364 &word);
3365 if (ret_val)
3366 break;
3367 data[i] = word;
3368 }
3369 }
3370
3371 nvm->ops.release(hw);
3372
3373 out:
3374 if (ret_val)
3375 e_dbg("NVM read error: %d\n", ret_val);
3376
3377 return ret_val;
3378 }
3379
3380 /**
3381 * e1000_flash_cycle_init_ich8lan - Initialize flash
3382 * @hw: pointer to the HW structure
3383 *
3384 * This function does initial flash setup so that a new read/write/erase cycle
3385 * can be started.
3386 **/
3387 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3388 {
3389 union ich8_hws_flash_status hsfsts;
3390 s32 ret_val = -E1000_ERR_NVM;
3391
3392 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3393
3394 /* Check if the flash descriptor is valid */
3395 if (!hsfsts.hsf_status.fldesvalid) {
3396 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3397 return -E1000_ERR_NVM;
3398 }
3399
3400 /* Clear FCERR and DAEL in hw status by writing 1 */
3401 hsfsts.hsf_status.flcerr = 1;
3402 hsfsts.hsf_status.dael = 1;
3403 if (hw->mac.type >= e1000_pch_spt)
3404 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3405 else
3406 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3407
3408 /* Either we should have a hardware SPI cycle in progress
3409 * bit to check against, in order to start a new cycle or
3410 * FDONE bit should be changed in the hardware so that it
3411 * is 1 after hardware reset, which can then be used as an
3412 * indication whether a cycle is in progress or has been
3413 * completed.
3414 */
3415
3416 if (!hsfsts.hsf_status.flcinprog) {
3417 /* There is no cycle running at present,
3418 * so we can start a cycle.
3419 * Begin by setting Flash Cycle Done.
3420 */
3421 hsfsts.hsf_status.flcdone = 1;
3422 if (hw->mac.type >= e1000_pch_spt)
3423 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3424 else
3425 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3426 ret_val = 0;
3427 } else {
3428 s32 i;
3429
3430 /* Otherwise poll for sometime so the current
3431 * cycle has a chance to end before giving up.
3432 */
3433 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3434 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3435 if (!hsfsts.hsf_status.flcinprog) {
3436 ret_val = 0;
3437 break;
3438 }
3439 udelay(1);
3440 }
3441 if (!ret_val) {
3442 /* Successful in waiting for previous cycle to timeout,
3443 * now set the Flash Cycle Done.
3444 */
3445 hsfsts.hsf_status.flcdone = 1;
3446 if (hw->mac.type >= e1000_pch_spt)
3447 ew32flash(ICH_FLASH_HSFSTS,
3448 hsfsts.regval & 0xFFFF);
3449 else
3450 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3451 } else {
3452 e_dbg("Flash controller busy, cannot get access\n");
3453 }
3454 }
3455
3456 return ret_val;
3457 }
3458
3459 /**
3460 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3461 * @hw: pointer to the HW structure
3462 * @timeout: maximum time to wait for completion
3463 *
3464 * This function starts a flash cycle and waits for its completion.
3465 **/
3466 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3467 {
3468 union ich8_hws_flash_ctrl hsflctl;
3469 union ich8_hws_flash_status hsfsts;
3470 u32 i = 0;
3471
3472 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3473 if (hw->mac.type >= e1000_pch_spt)
3474 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3475 else
3476 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3477 hsflctl.hsf_ctrl.flcgo = 1;
3478
3479 if (hw->mac.type >= e1000_pch_spt)
3480 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3481 else
3482 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3483
3484 /* wait till FDONE bit is set to 1 */
3485 do {
3486 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3487 if (hsfsts.hsf_status.flcdone)
3488 break;
3489 udelay(1);
3490 } while (i++ < timeout);
3491
3492 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3493 return 0;
3494
3495 return -E1000_ERR_NVM;
3496 }
3497
3498 /**
3499 * e1000_read_flash_dword_ich8lan - Read dword from flash
3500 * @hw: pointer to the HW structure
3501 * @offset: offset to data location
3502 * @data: pointer to the location for storing the data
3503 *
3504 * Reads the flash dword at offset into data. Offset is converted
3505 * to bytes before read.
3506 **/
3507 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3508 u32 *data)
3509 {
3510 /* Must convert word offset into bytes. */
3511 offset <<= 1;
3512 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3513 }
3514
3515 /**
3516 * e1000_read_flash_word_ich8lan - Read word from flash
3517 * @hw: pointer to the HW structure
3518 * @offset: offset to data location
3519 * @data: pointer to the location for storing the data
3520 *
3521 * Reads the flash word at offset into data. Offset is converted
3522 * to bytes before read.
3523 **/
3524 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3525 u16 *data)
3526 {
3527 /* Must convert offset into bytes. */
3528 offset <<= 1;
3529
3530 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3531 }
3532
3533 /**
3534 * e1000_read_flash_byte_ich8lan - Read byte from flash
3535 * @hw: pointer to the HW structure
3536 * @offset: The offset of the byte to read.
3537 * @data: Pointer to a byte to store the value read.
3538 *
3539 * Reads a single byte from the NVM using the flash access registers.
3540 **/
3541 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3542 u8 *data)
3543 {
3544 s32 ret_val;
3545 u16 word = 0;
3546
3547 /* In SPT, only 32 bits access is supported,
3548 * so this function should not be called.
3549 */
3550 if (hw->mac.type >= e1000_pch_spt)
3551 return -E1000_ERR_NVM;
3552 else
3553 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3554
3555 if (ret_val)
3556 return ret_val;
3557
3558 *data = (u8)word;
3559
3560 return 0;
3561 }
3562
3563 /**
3564 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3565 * @hw: pointer to the HW structure
3566 * @offset: The offset (in bytes) of the byte or word to read.
3567 * @size: Size of data to read, 1=byte 2=word
3568 * @data: Pointer to the word to store the value read.
3569 *
3570 * Reads a byte or word from the NVM using the flash access registers.
3571 **/
3572 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3573 u8 size, u16 *data)
3574 {
3575 union ich8_hws_flash_status hsfsts;
3576 union ich8_hws_flash_ctrl hsflctl;
3577 u32 flash_linear_addr;
3578 u32 flash_data = 0;
3579 s32 ret_val = -E1000_ERR_NVM;
3580 u8 count = 0;
3581
3582 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3583 return -E1000_ERR_NVM;
3584
3585 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3586 hw->nvm.flash_base_addr);
3587
3588 do {
3589 udelay(1);
3590 /* Steps */
3591 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3592 if (ret_val)
3593 break;
3594
3595 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3596 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3597 hsflctl.hsf_ctrl.fldbcount = size - 1;
3598 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3599 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3600
3601 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3602
3603 ret_val =
3604 e1000_flash_cycle_ich8lan(hw,
3605 ICH_FLASH_READ_COMMAND_TIMEOUT);
3606
3607 /* Check if FCERR is set to 1, if set to 1, clear it
3608 * and try the whole sequence a few more times, else
3609 * read in (shift in) the Flash Data0, the order is
3610 * least significant byte first msb to lsb
3611 */
3612 if (!ret_val) {
3613 flash_data = er32flash(ICH_FLASH_FDATA0);
3614 if (size == 1)
3615 *data = (u8)(flash_data & 0x000000FF);
3616 else if (size == 2)
3617 *data = (u16)(flash_data & 0x0000FFFF);
3618 break;
3619 } else {
3620 /* If we've gotten here, then things are probably
3621 * completely hosed, but if the error condition is
3622 * detected, it won't hurt to give it another try...
3623 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3624 */
3625 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3626 if (hsfsts.hsf_status.flcerr) {
3627 /* Repeat for some time before giving up. */
3628 continue;
3629 } else if (!hsfsts.hsf_status.flcdone) {
3630 e_dbg("Timeout error - flash cycle did not complete.\n");
3631 break;
3632 }
3633 }
3634 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3635
3636 return ret_val;
3637 }
3638
3639 /**
3640 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3641 * @hw: pointer to the HW structure
3642 * @offset: The offset (in bytes) of the dword to read.
3643 * @data: Pointer to the dword to store the value read.
3644 *
3645 * Reads a byte or word from the NVM using the flash access registers.
3646 **/
3647
3648 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3649 u32 *data)
3650 {
3651 union ich8_hws_flash_status hsfsts;
3652 union ich8_hws_flash_ctrl hsflctl;
3653 u32 flash_linear_addr;
3654 s32 ret_val = -E1000_ERR_NVM;
3655 u8 count = 0;
3656
3657 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3658 return -E1000_ERR_NVM;
3659 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3660 hw->nvm.flash_base_addr);
3661
3662 do {
3663 udelay(1);
3664 /* Steps */
3665 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3666 if (ret_val)
3667 break;
3668 /* In SPT, This register is in Lan memory space, not flash.
3669 * Therefore, only 32 bit access is supported
3670 */
3671 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3672
3673 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3674 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3675 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3676 /* In SPT, This register is in Lan memory space, not flash.
3677 * Therefore, only 32 bit access is supported
3678 */
3679 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3680 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3681
3682 ret_val =
3683 e1000_flash_cycle_ich8lan(hw,
3684 ICH_FLASH_READ_COMMAND_TIMEOUT);
3685
3686 /* Check if FCERR is set to 1, if set to 1, clear it
3687 * and try the whole sequence a few more times, else
3688 * read in (shift in) the Flash Data0, the order is
3689 * least significant byte first msb to lsb
3690 */
3691 if (!ret_val) {
3692 *data = er32flash(ICH_FLASH_FDATA0);
3693 break;
3694 } else {
3695 /* If we've gotten here, then things are probably
3696 * completely hosed, but if the error condition is
3697 * detected, it won't hurt to give it another try...
3698 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3699 */
3700 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3701 if (hsfsts.hsf_status.flcerr) {
3702 /* Repeat for some time before giving up. */
3703 continue;
3704 } else if (!hsfsts.hsf_status.flcdone) {
3705 e_dbg("Timeout error - flash cycle did not complete.\n");
3706 break;
3707 }
3708 }
3709 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3710
3711 return ret_val;
3712 }
3713
3714 /**
3715 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3716 * @hw: pointer to the HW structure
3717 * @offset: The offset (in bytes) of the word(s) to write.
3718 * @words: Size of data to write in words
3719 * @data: Pointer to the word(s) to write at offset.
3720 *
3721 * Writes a byte or word to the NVM using the flash access registers.
3722 **/
3723 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3724 u16 *data)
3725 {
3726 struct e1000_nvm_info *nvm = &hw->nvm;
3727 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3728 u16 i;
3729
3730 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3731 (words == 0)) {
3732 e_dbg("nvm parameter(s) out of bounds\n");
3733 return -E1000_ERR_NVM;
3734 }
3735
3736 nvm->ops.acquire(hw);
3737
3738 for (i = 0; i < words; i++) {
3739 dev_spec->shadow_ram[offset + i].modified = true;
3740 dev_spec->shadow_ram[offset + i].value = data[i];
3741 }
3742
3743 nvm->ops.release(hw);
3744
3745 return 0;
3746 }
3747
3748 /**
3749 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3750 * @hw: pointer to the HW structure
3751 *
3752 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3753 * which writes the checksum to the shadow ram. The changes in the shadow
3754 * ram are then committed to the EEPROM by processing each bank at a time
3755 * checking for the modified bit and writing only the pending changes.
3756 * After a successful commit, the shadow ram is cleared and is ready for
3757 * future writes.
3758 **/
3759 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3760 {
3761 struct e1000_nvm_info *nvm = &hw->nvm;
3762 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3763 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3764 s32 ret_val;
3765 u32 dword = 0;
3766
3767 ret_val = e1000e_update_nvm_checksum_generic(hw);
3768 if (ret_val)
3769 goto out;
3770
3771 if (nvm->type != e1000_nvm_flash_sw)
3772 goto out;
3773
3774 nvm->ops.acquire(hw);
3775
3776 /* We're writing to the opposite bank so if we're on bank 1,
3777 * write to bank 0 etc. We also need to erase the segment that
3778 * is going to be written
3779 */
3780 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3781 if (ret_val) {
3782 e_dbg("Could not detect valid bank, assuming bank 0\n");
3783 bank = 0;
3784 }
3785
3786 if (bank == 0) {
3787 new_bank_offset = nvm->flash_bank_size;
3788 old_bank_offset = 0;
3789 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3790 if (ret_val)
3791 goto release;
3792 } else {
3793 old_bank_offset = nvm->flash_bank_size;
3794 new_bank_offset = 0;
3795 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3796 if (ret_val)
3797 goto release;
3798 }
3799 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3800 /* Determine whether to write the value stored
3801 * in the other NVM bank or a modified value stored
3802 * in the shadow RAM
3803 */
3804 ret_val = e1000_read_flash_dword_ich8lan(hw,
3805 i + old_bank_offset,
3806 &dword);
3807
3808 if (dev_spec->shadow_ram[i].modified) {
3809 dword &= 0xffff0000;
3810 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3811 }
3812 if (dev_spec->shadow_ram[i + 1].modified) {
3813 dword &= 0x0000ffff;
3814 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3815 << 16);
3816 }
3817 if (ret_val)
3818 break;
3819
3820 /* If the word is 0x13, then make sure the signature bits
3821 * (15:14) are 11b until the commit has completed.
3822 * This will allow us to write 10b which indicates the
3823 * signature is valid. We want to do this after the write
3824 * has completed so that we don't mark the segment valid
3825 * while the write is still in progress
3826 */
3827 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3828 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3829
3830 /* Convert offset to bytes. */
3831 act_offset = (i + new_bank_offset) << 1;
3832
3833 usleep_range(100, 200);
3834
3835 /* Write the data to the new bank. Offset in words */
3836 act_offset = i + new_bank_offset;
3837 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3838 dword);
3839 if (ret_val)
3840 break;
3841 }
3842
3843 /* Don't bother writing the segment valid bits if sector
3844 * programming failed.
3845 */
3846 if (ret_val) {
3847 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3848 e_dbg("Flash commit failed.\n");
3849 goto release;
3850 }
3851
3852 /* Finally validate the new segment by setting bit 15:14
3853 * to 10b in word 0x13 , this can be done without an
3854 * erase as well since these bits are 11 to start with
3855 * and we need to change bit 14 to 0b
3856 */
3857 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3858
3859 /*offset in words but we read dword */
3860 --act_offset;
3861 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3862
3863 if (ret_val)
3864 goto release;
3865
3866 dword &= 0xBFFFFFFF;
3867 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3868
3869 if (ret_val)
3870 goto release;
3871
3872 /* And invalidate the previously valid segment by setting
3873 * its signature word (0x13) high_byte to 0b. This can be
3874 * done without an erase because flash erase sets all bits
3875 * to 1's. We can write 1's to 0's without an erase
3876 */
3877 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3878
3879 /* offset in words but we read dword */
3880 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3881 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3882
3883 if (ret_val)
3884 goto release;
3885
3886 dword &= 0x00FFFFFF;
3887 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3888
3889 if (ret_val)
3890 goto release;
3891
3892 /* Great! Everything worked, we can now clear the cached entries. */
3893 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3894 dev_spec->shadow_ram[i].modified = false;
3895 dev_spec->shadow_ram[i].value = 0xFFFF;
3896 }
3897
3898 release:
3899 nvm->ops.release(hw);
3900
3901 /* Reload the EEPROM, or else modifications will not appear
3902 * until after the next adapter reset.
3903 */
3904 if (!ret_val) {
3905 nvm->ops.reload(hw);
3906 usleep_range(10000, 11000);
3907 }
3908
3909 out:
3910 if (ret_val)
3911 e_dbg("NVM update error: %d\n", ret_val);
3912
3913 return ret_val;
3914 }
3915
3916 /**
3917 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3918 * @hw: pointer to the HW structure
3919 *
3920 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3921 * which writes the checksum to the shadow ram. The changes in the shadow
3922 * ram are then committed to the EEPROM by processing each bank at a time
3923 * checking for the modified bit and writing only the pending changes.
3924 * After a successful commit, the shadow ram is cleared and is ready for
3925 * future writes.
3926 **/
3927 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3928 {
3929 struct e1000_nvm_info *nvm = &hw->nvm;
3930 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3931 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3932 s32 ret_val;
3933 u16 data = 0;
3934
3935 ret_val = e1000e_update_nvm_checksum_generic(hw);
3936 if (ret_val)
3937 goto out;
3938
3939 if (nvm->type != e1000_nvm_flash_sw)
3940 goto out;
3941
3942 nvm->ops.acquire(hw);
3943
3944 /* We're writing to the opposite bank so if we're on bank 1,
3945 * write to bank 0 etc. We also need to erase the segment that
3946 * is going to be written
3947 */
3948 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3949 if (ret_val) {
3950 e_dbg("Could not detect valid bank, assuming bank 0\n");
3951 bank = 0;
3952 }
3953
3954 if (bank == 0) {
3955 new_bank_offset = nvm->flash_bank_size;
3956 old_bank_offset = 0;
3957 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3958 if (ret_val)
3959 goto release;
3960 } else {
3961 old_bank_offset = nvm->flash_bank_size;
3962 new_bank_offset = 0;
3963 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3964 if (ret_val)
3965 goto release;
3966 }
3967 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3968 if (dev_spec->shadow_ram[i].modified) {
3969 data = dev_spec->shadow_ram[i].value;
3970 } else {
3971 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3972 old_bank_offset,
3973 &data);
3974 if (ret_val)
3975 break;
3976 }
3977
3978 /* If the word is 0x13, then make sure the signature bits
3979 * (15:14) are 11b until the commit has completed.
3980 * This will allow us to write 10b which indicates the
3981 * signature is valid. We want to do this after the write
3982 * has completed so that we don't mark the segment valid
3983 * while the write is still in progress
3984 */
3985 if (i == E1000_ICH_NVM_SIG_WORD)
3986 data |= E1000_ICH_NVM_SIG_MASK;
3987
3988 /* Convert offset to bytes. */
3989 act_offset = (i + new_bank_offset) << 1;
3990
3991 usleep_range(100, 200);
3992 /* Write the bytes to the new bank. */
3993 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3994 act_offset,
3995 (u8)data);
3996 if (ret_val)
3997 break;
3998
3999 usleep_range(100, 200);
4000 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4001 act_offset + 1,
4002 (u8)(data >> 8));
4003 if (ret_val)
4004 break;
4005 }
4006
4007 /* Don't bother writing the segment valid bits if sector
4008 * programming failed.
4009 */
4010 if (ret_val) {
4011 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4012 e_dbg("Flash commit failed.\n");
4013 goto release;
4014 }
4015
4016 /* Finally validate the new segment by setting bit 15:14
4017 * to 10b in word 0x13 , this can be done without an
4018 * erase as well since these bits are 11 to start with
4019 * and we need to change bit 14 to 0b
4020 */
4021 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4022 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4023 if (ret_val)
4024 goto release;
4025
4026 data &= 0xBFFF;
4027 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4028 act_offset * 2 + 1,
4029 (u8)(data >> 8));
4030 if (ret_val)
4031 goto release;
4032
4033 /* And invalidate the previously valid segment by setting
4034 * its signature word (0x13) high_byte to 0b. This can be
4035 * done without an erase because flash erase sets all bits
4036 * to 1's. We can write 1's to 0's without an erase
4037 */
4038 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4039 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4040 if (ret_val)
4041 goto release;
4042
4043 /* Great! Everything worked, we can now clear the cached entries. */
4044 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4045 dev_spec->shadow_ram[i].modified = false;
4046 dev_spec->shadow_ram[i].value = 0xFFFF;
4047 }
4048
4049 release:
4050 nvm->ops.release(hw);
4051
4052 /* Reload the EEPROM, or else modifications will not appear
4053 * until after the next adapter reset.
4054 */
4055 if (!ret_val) {
4056 nvm->ops.reload(hw);
4057 usleep_range(10000, 11000);
4058 }
4059
4060 out:
4061 if (ret_val)
4062 e_dbg("NVM update error: %d\n", ret_val);
4063
4064 return ret_val;
4065 }
4066
4067 /**
4068 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4069 * @hw: pointer to the HW structure
4070 *
4071 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4072 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4073 * calculated, in which case we need to calculate the checksum and set bit 6.
4074 **/
4075 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4076 {
4077 s32 ret_val;
4078 u16 data;
4079 u16 word;
4080 u16 valid_csum_mask;
4081
4082 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4083 * the checksum needs to be fixed. This bit is an indication that
4084 * the NVM was prepared by OEM software and did not calculate
4085 * the checksum...a likely scenario.
4086 */
4087 switch (hw->mac.type) {
4088 case e1000_pch_lpt:
4089 case e1000_pch_spt:
4090 case e1000_pch_cnp:
4091 case e1000_pch_tgp:
4092 case e1000_pch_adp:
4093 word = NVM_COMPAT;
4094 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4095 break;
4096 default:
4097 word = NVM_FUTURE_INIT_WORD1;
4098 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4099 break;
4100 }
4101
4102 ret_val = e1000_read_nvm(hw, word, 1, &data);
4103 if (ret_val)
4104 return ret_val;
4105
4106 if (!(data & valid_csum_mask)) {
4107 data |= valid_csum_mask;
4108 ret_val = e1000_write_nvm(hw, word, 1, &data);
4109 if (ret_val)
4110 return ret_val;
4111 ret_val = e1000e_update_nvm_checksum(hw);
4112 if (ret_val)
4113 return ret_val;
4114 }
4115
4116 return e1000e_validate_nvm_checksum_generic(hw);
4117 }
4118
4119 /**
4120 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4121 * @hw: pointer to the HW structure
4122 *
4123 * To prevent malicious write/erase of the NVM, set it to be read-only
4124 * so that the hardware ignores all write/erase cycles of the NVM via
4125 * the flash control registers. The shadow-ram copy of the NVM will
4126 * still be updated, however any updates to this copy will not stick
4127 * across driver reloads.
4128 **/
4129 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4130 {
4131 struct e1000_nvm_info *nvm = &hw->nvm;
4132 union ich8_flash_protected_range pr0;
4133 union ich8_hws_flash_status hsfsts;
4134 u32 gfpreg;
4135
4136 nvm->ops.acquire(hw);
4137
4138 gfpreg = er32flash(ICH_FLASH_GFPREG);
4139
4140 /* Write-protect GbE Sector of NVM */
4141 pr0.regval = er32flash(ICH_FLASH_PR0);
4142 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4143 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4144 pr0.range.wpe = true;
4145 ew32flash(ICH_FLASH_PR0, pr0.regval);
4146
4147 /* Lock down a subset of GbE Flash Control Registers, e.g.
4148 * PR0 to prevent the write-protection from being lifted.
4149 * Once FLOCKDN is set, the registers protected by it cannot
4150 * be written until FLOCKDN is cleared by a hardware reset.
4151 */
4152 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4153 hsfsts.hsf_status.flockdn = true;
4154 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4155
4156 nvm->ops.release(hw);
4157 }
4158
4159 /**
4160 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4161 * @hw: pointer to the HW structure
4162 * @offset: The offset (in bytes) of the byte/word to read.
4163 * @size: Size of data to read, 1=byte 2=word
4164 * @data: The byte(s) to write to the NVM.
4165 *
4166 * Writes one/two bytes to the NVM using the flash access registers.
4167 **/
4168 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4169 u8 size, u16 data)
4170 {
4171 union ich8_hws_flash_status hsfsts;
4172 union ich8_hws_flash_ctrl hsflctl;
4173 u32 flash_linear_addr;
4174 u32 flash_data = 0;
4175 s32 ret_val;
4176 u8 count = 0;
4177
4178 if (hw->mac.type >= e1000_pch_spt) {
4179 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4180 return -E1000_ERR_NVM;
4181 } else {
4182 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4183 return -E1000_ERR_NVM;
4184 }
4185
4186 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4187 hw->nvm.flash_base_addr);
4188
4189 do {
4190 udelay(1);
4191 /* Steps */
4192 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4193 if (ret_val)
4194 break;
4195 /* In SPT, This register is in Lan memory space, not
4196 * flash. Therefore, only 32 bit access is supported
4197 */
4198 if (hw->mac.type >= e1000_pch_spt)
4199 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4200 else
4201 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4202
4203 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4204 hsflctl.hsf_ctrl.fldbcount = size - 1;
4205 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4206 /* In SPT, This register is in Lan memory space,
4207 * not flash. Therefore, only 32 bit access is
4208 * supported
4209 */
4210 if (hw->mac.type >= e1000_pch_spt)
4211 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4212 else
4213 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4214
4215 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4216
4217 if (size == 1)
4218 flash_data = (u32)data & 0x00FF;
4219 else
4220 flash_data = (u32)data;
4221
4222 ew32flash(ICH_FLASH_FDATA0, flash_data);
4223
4224 /* check if FCERR is set to 1 , if set to 1, clear it
4225 * and try the whole sequence a few more times else done
4226 */
4227 ret_val =
4228 e1000_flash_cycle_ich8lan(hw,
4229 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4230 if (!ret_val)
4231 break;
4232
4233 /* If we're here, then things are most likely
4234 * completely hosed, but if the error condition
4235 * is detected, it won't hurt to give it another
4236 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4237 */
4238 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4239 if (hsfsts.hsf_status.flcerr)
4240 /* Repeat for some time before giving up. */
4241 continue;
4242 if (!hsfsts.hsf_status.flcdone) {
4243 e_dbg("Timeout error - flash cycle did not complete.\n");
4244 break;
4245 }
4246 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4247
4248 return ret_val;
4249 }
4250
4251 /**
4252 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4253 * @hw: pointer to the HW structure
4254 * @offset: The offset (in bytes) of the dwords to read.
4255 * @data: The 4 bytes to write to the NVM.
4256 *
4257 * Writes one/two/four bytes to the NVM using the flash access registers.
4258 **/
4259 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4260 u32 data)
4261 {
4262 union ich8_hws_flash_status hsfsts;
4263 union ich8_hws_flash_ctrl hsflctl;
4264 u32 flash_linear_addr;
4265 s32 ret_val;
4266 u8 count = 0;
4267
4268 if (hw->mac.type >= e1000_pch_spt) {
4269 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4270 return -E1000_ERR_NVM;
4271 }
4272 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4273 hw->nvm.flash_base_addr);
4274 do {
4275 udelay(1);
4276 /* Steps */
4277 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4278 if (ret_val)
4279 break;
4280
4281 /* In SPT, This register is in Lan memory space, not
4282 * flash. Therefore, only 32 bit access is supported
4283 */
4284 if (hw->mac.type >= e1000_pch_spt)
4285 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4286 >> 16;
4287 else
4288 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4289
4290 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4291 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4292
4293 /* In SPT, This register is in Lan memory space,
4294 * not flash. Therefore, only 32 bit access is
4295 * supported
4296 */
4297 if (hw->mac.type >= e1000_pch_spt)
4298 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4299 else
4300 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4301
4302 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4303
4304 ew32flash(ICH_FLASH_FDATA0, data);
4305
4306 /* check if FCERR is set to 1 , if set to 1, clear it
4307 * and try the whole sequence a few more times else done
4308 */
4309 ret_val =
4310 e1000_flash_cycle_ich8lan(hw,
4311 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4312
4313 if (!ret_val)
4314 break;
4315
4316 /* If we're here, then things are most likely
4317 * completely hosed, but if the error condition
4318 * is detected, it won't hurt to give it another
4319 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4320 */
4321 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4322
4323 if (hsfsts.hsf_status.flcerr)
4324 /* Repeat for some time before giving up. */
4325 continue;
4326 if (!hsfsts.hsf_status.flcdone) {
4327 e_dbg("Timeout error - flash cycle did not complete.\n");
4328 break;
4329 }
4330 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4331
4332 return ret_val;
4333 }
4334
4335 /**
4336 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4337 * @hw: pointer to the HW structure
4338 * @offset: The index of the byte to read.
4339 * @data: The byte to write to the NVM.
4340 *
4341 * Writes a single byte to the NVM using the flash access registers.
4342 **/
4343 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4344 u8 data)
4345 {
4346 u16 word = (u16)data;
4347
4348 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4349 }
4350
4351 /**
4352 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4353 * @hw: pointer to the HW structure
4354 * @offset: The offset of the word to write.
4355 * @dword: The dword to write to the NVM.
4356 *
4357 * Writes a single dword to the NVM using the flash access registers.
4358 * Goes through a retry algorithm before giving up.
4359 **/
4360 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4361 u32 offset, u32 dword)
4362 {
4363 s32 ret_val;
4364 u16 program_retries;
4365
4366 /* Must convert word offset into bytes. */
4367 offset <<= 1;
4368 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4369
4370 if (!ret_val)
4371 return ret_val;
4372 for (program_retries = 0; program_retries < 100; program_retries++) {
4373 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4374 usleep_range(100, 200);
4375 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4376 if (!ret_val)
4377 break;
4378 }
4379 if (program_retries == 100)
4380 return -E1000_ERR_NVM;
4381
4382 return 0;
4383 }
4384
4385 /**
4386 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4387 * @hw: pointer to the HW structure
4388 * @offset: The offset of the byte to write.
4389 * @byte: The byte to write to the NVM.
4390 *
4391 * Writes a single byte to the NVM using the flash access registers.
4392 * Goes through a retry algorithm before giving up.
4393 **/
4394 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4395 u32 offset, u8 byte)
4396 {
4397 s32 ret_val;
4398 u16 program_retries;
4399
4400 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4401 if (!ret_val)
4402 return ret_val;
4403
4404 for (program_retries = 0; program_retries < 100; program_retries++) {
4405 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4406 usleep_range(100, 200);
4407 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4408 if (!ret_val)
4409 break;
4410 }
4411 if (program_retries == 100)
4412 return -E1000_ERR_NVM;
4413
4414 return 0;
4415 }
4416
4417 /**
4418 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4419 * @hw: pointer to the HW structure
4420 * @bank: 0 for first bank, 1 for second bank, etc.
4421 *
4422 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4423 * bank N is 4096 * N + flash_reg_addr.
4424 **/
4425 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4426 {
4427 struct e1000_nvm_info *nvm = &hw->nvm;
4428 union ich8_hws_flash_status hsfsts;
4429 union ich8_hws_flash_ctrl hsflctl;
4430 u32 flash_linear_addr;
4431 /* bank size is in 16bit words - adjust to bytes */
4432 u32 flash_bank_size = nvm->flash_bank_size * 2;
4433 s32 ret_val;
4434 s32 count = 0;
4435 s32 j, iteration, sector_size;
4436
4437 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4438
4439 /* Determine HW Sector size: Read BERASE bits of hw flash status
4440 * register
4441 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4442 * consecutive sectors. The start index for the nth Hw sector
4443 * can be calculated as = bank * 4096 + n * 256
4444 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4445 * The start index for the nth Hw sector can be calculated
4446 * as = bank * 4096
4447 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4448 * (ich9 only, otherwise error condition)
4449 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4450 */
4451 switch (hsfsts.hsf_status.berasesz) {
4452 case 0:
4453 /* Hw sector size 256 */
4454 sector_size = ICH_FLASH_SEG_SIZE_256;
4455 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4456 break;
4457 case 1:
4458 sector_size = ICH_FLASH_SEG_SIZE_4K;
4459 iteration = 1;
4460 break;
4461 case 2:
4462 sector_size = ICH_FLASH_SEG_SIZE_8K;
4463 iteration = 1;
4464 break;
4465 case 3:
4466 sector_size = ICH_FLASH_SEG_SIZE_64K;
4467 iteration = 1;
4468 break;
4469 default:
4470 return -E1000_ERR_NVM;
4471 }
4472
4473 /* Start with the base address, then add the sector offset. */
4474 flash_linear_addr = hw->nvm.flash_base_addr;
4475 flash_linear_addr += (bank) ? flash_bank_size : 0;
4476
4477 for (j = 0; j < iteration; j++) {
4478 do {
4479 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4480
4481 /* Steps */
4482 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4483 if (ret_val)
4484 return ret_val;
4485
4486 /* Write a value 11 (block Erase) in Flash
4487 * Cycle field in hw flash control
4488 */
4489 if (hw->mac.type >= e1000_pch_spt)
4490 hsflctl.regval =
4491 er32flash(ICH_FLASH_HSFSTS) >> 16;
4492 else
4493 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4494
4495 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4496 if (hw->mac.type >= e1000_pch_spt)
4497 ew32flash(ICH_FLASH_HSFSTS,
4498 hsflctl.regval << 16);
4499 else
4500 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4501
4502 /* Write the last 24 bits of an index within the
4503 * block into Flash Linear address field in Flash
4504 * Address.
4505 */
4506 flash_linear_addr += (j * sector_size);
4507 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4508
4509 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4510 if (!ret_val)
4511 break;
4512
4513 /* Check if FCERR is set to 1. If 1,
4514 * clear it and try the whole sequence
4515 * a few more times else Done
4516 */
4517 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4518 if (hsfsts.hsf_status.flcerr)
4519 /* repeat for some time before giving up */
4520 continue;
4521 else if (!hsfsts.hsf_status.flcdone)
4522 return ret_val;
4523 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4524 }
4525
4526 return 0;
4527 }
4528
4529 /**
4530 * e1000_valid_led_default_ich8lan - Set the default LED settings
4531 * @hw: pointer to the HW structure
4532 * @data: Pointer to the LED settings
4533 *
4534 * Reads the LED default settings from the NVM to data. If the NVM LED
4535 * settings is all 0's or F's, set the LED default to a valid LED default
4536 * setting.
4537 **/
4538 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4539 {
4540 s32 ret_val;
4541
4542 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4543 if (ret_val) {
4544 e_dbg("NVM Read Error\n");
4545 return ret_val;
4546 }
4547
4548 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4549 *data = ID_LED_DEFAULT_ICH8LAN;
4550
4551 return 0;
4552 }
4553
4554 /**
4555 * e1000_id_led_init_pchlan - store LED configurations
4556 * @hw: pointer to the HW structure
4557 *
4558 * PCH does not control LEDs via the LEDCTL register, rather it uses
4559 * the PHY LED configuration register.
4560 *
4561 * PCH also does not have an "always on" or "always off" mode which
4562 * complicates the ID feature. Instead of using the "on" mode to indicate
4563 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4564 * use "link_up" mode. The LEDs will still ID on request if there is no
4565 * link based on logic in e1000_led_[on|off]_pchlan().
4566 **/
4567 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4568 {
4569 struct e1000_mac_info *mac = &hw->mac;
4570 s32 ret_val;
4571 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4572 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4573 u16 data, i, temp, shift;
4574
4575 /* Get default ID LED modes */
4576 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4577 if (ret_val)
4578 return ret_val;
4579
4580 mac->ledctl_default = er32(LEDCTL);
4581 mac->ledctl_mode1 = mac->ledctl_default;
4582 mac->ledctl_mode2 = mac->ledctl_default;
4583
4584 for (i = 0; i < 4; i++) {
4585 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4586 shift = (i * 5);
4587 switch (temp) {
4588 case ID_LED_ON1_DEF2:
4589 case ID_LED_ON1_ON2:
4590 case ID_LED_ON1_OFF2:
4591 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4592 mac->ledctl_mode1 |= (ledctl_on << shift);
4593 break;
4594 case ID_LED_OFF1_DEF2:
4595 case ID_LED_OFF1_ON2:
4596 case ID_LED_OFF1_OFF2:
4597 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4598 mac->ledctl_mode1 |= (ledctl_off << shift);
4599 break;
4600 default:
4601 /* Do nothing */
4602 break;
4603 }
4604 switch (temp) {
4605 case ID_LED_DEF1_ON2:
4606 case ID_LED_ON1_ON2:
4607 case ID_LED_OFF1_ON2:
4608 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4609 mac->ledctl_mode2 |= (ledctl_on << shift);
4610 break;
4611 case ID_LED_DEF1_OFF2:
4612 case ID_LED_ON1_OFF2:
4613 case ID_LED_OFF1_OFF2:
4614 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4615 mac->ledctl_mode2 |= (ledctl_off << shift);
4616 break;
4617 default:
4618 /* Do nothing */
4619 break;
4620 }
4621 }
4622
4623 return 0;
4624 }
4625
4626 /**
4627 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4628 * @hw: pointer to the HW structure
4629 *
4630 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4631 * register, so the the bus width is hard coded.
4632 **/
4633 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4634 {
4635 struct e1000_bus_info *bus = &hw->bus;
4636 s32 ret_val;
4637
4638 ret_val = e1000e_get_bus_info_pcie(hw);
4639
4640 /* ICH devices are "PCI Express"-ish. They have
4641 * a configuration space, but do not contain
4642 * PCI Express Capability registers, so bus width
4643 * must be hardcoded.
4644 */
4645 if (bus->width == e1000_bus_width_unknown)
4646 bus->width = e1000_bus_width_pcie_x1;
4647
4648 return ret_val;
4649 }
4650
4651 /**
4652 * e1000_reset_hw_ich8lan - Reset the hardware
4653 * @hw: pointer to the HW structure
4654 *
4655 * Does a full reset of the hardware which includes a reset of the PHY and
4656 * MAC.
4657 **/
4658 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4659 {
4660 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4661 u16 kum_cfg;
4662 u32 ctrl, reg;
4663 s32 ret_val;
4664
4665 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4666 * on the last TLP read/write transaction when MAC is reset.
4667 */
4668 ret_val = e1000e_disable_pcie_master(hw);
4669 if (ret_val)
4670 e_dbg("PCI-E Master disable polling has failed.\n");
4671
4672 e_dbg("Masking off all interrupts\n");
4673 ew32(IMC, 0xffffffff);
4674
4675 /* Disable the Transmit and Receive units. Then delay to allow
4676 * any pending transactions to complete before we hit the MAC
4677 * with the global reset.
4678 */
4679 ew32(RCTL, 0);
4680 ew32(TCTL, E1000_TCTL_PSP);
4681 e1e_flush();
4682
4683 usleep_range(10000, 11000);
4684
4685 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4686 if (hw->mac.type == e1000_ich8lan) {
4687 /* Set Tx and Rx buffer allocation to 8k apiece. */
4688 ew32(PBA, E1000_PBA_8K);
4689 /* Set Packet Buffer Size to 16k. */
4690 ew32(PBS, E1000_PBS_16K);
4691 }
4692
4693 if (hw->mac.type == e1000_pchlan) {
4694 /* Save the NVM K1 bit setting */
4695 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4696 if (ret_val)
4697 return ret_val;
4698
4699 if (kum_cfg & E1000_NVM_K1_ENABLE)
4700 dev_spec->nvm_k1_enabled = true;
4701 else
4702 dev_spec->nvm_k1_enabled = false;
4703 }
4704
4705 ctrl = er32(CTRL);
4706
4707 if (!hw->phy.ops.check_reset_block(hw)) {
4708 /* Full-chip reset requires MAC and PHY reset at the same
4709 * time to make sure the interface between MAC and the
4710 * external PHY is reset.
4711 */
4712 ctrl |= E1000_CTRL_PHY_RST;
4713
4714 /* Gate automatic PHY configuration by hardware on
4715 * non-managed 82579
4716 */
4717 if ((hw->mac.type == e1000_pch2lan) &&
4718 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4719 e1000_gate_hw_phy_config_ich8lan(hw, true);
4720 }
4721 ret_val = e1000_acquire_swflag_ich8lan(hw);
4722 e_dbg("Issuing a global reset to ich8lan\n");
4723 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4724 /* cannot issue a flush here because it hangs the hardware */
4725 msleep(20);
4726
4727 /* Set Phy Config Counter to 50msec */
4728 if (hw->mac.type == e1000_pch2lan) {
4729 reg = er32(FEXTNVM3);
4730 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4731 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4732 ew32(FEXTNVM3, reg);
4733 }
4734
4735 if (!ret_val)
4736 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4737
4738 if (ctrl & E1000_CTRL_PHY_RST) {
4739 ret_val = hw->phy.ops.get_cfg_done(hw);
4740 if (ret_val)
4741 return ret_val;
4742
4743 ret_val = e1000_post_phy_reset_ich8lan(hw);
4744 if (ret_val)
4745 return ret_val;
4746 }
4747
4748 /* For PCH, this write will make sure that any noise
4749 * will be detected as a CRC error and be dropped rather than show up
4750 * as a bad packet to the DMA engine.
4751 */
4752 if (hw->mac.type == e1000_pchlan)
4753 ew32(CRC_OFFSET, 0x65656565);
4754
4755 ew32(IMC, 0xffffffff);
4756 er32(ICR);
4757
4758 reg = er32(KABGTXD);
4759 reg |= E1000_KABGTXD_BGSQLBIAS;
4760 ew32(KABGTXD, reg);
4761
4762 return 0;
4763 }
4764
4765 /**
4766 * e1000_init_hw_ich8lan - Initialize the hardware
4767 * @hw: pointer to the HW structure
4768 *
4769 * Prepares the hardware for transmit and receive by doing the following:
4770 * - initialize hardware bits
4771 * - initialize LED identification
4772 * - setup receive address registers
4773 * - setup flow control
4774 * - setup transmit descriptors
4775 * - clear statistics
4776 **/
4777 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4778 {
4779 struct e1000_mac_info *mac = &hw->mac;
4780 u32 ctrl_ext, txdctl, snoop;
4781 s32 ret_val;
4782 u16 i;
4783
4784 e1000_initialize_hw_bits_ich8lan(hw);
4785
4786 /* Initialize identification LED */
4787 ret_val = mac->ops.id_led_init(hw);
4788 /* An error is not fatal and we should not stop init due to this */
4789 if (ret_val)
4790 e_dbg("Error initializing identification LED\n");
4791
4792 /* Setup the receive address. */
4793 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4794
4795 /* Zero out the Multicast HASH table */
4796 e_dbg("Zeroing the MTA\n");
4797 for (i = 0; i < mac->mta_reg_count; i++)
4798 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4799
4800 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4801 * the ME. Disable wakeup by clearing the host wakeup bit.
4802 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4803 */
4804 if (hw->phy.type == e1000_phy_82578) {
4805 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4806 i &= ~BM_WUC_HOST_WU_BIT;
4807 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4808 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4809 if (ret_val)
4810 return ret_val;
4811 }
4812
4813 /* Setup link and flow control */
4814 ret_val = mac->ops.setup_link(hw);
4815
4816 /* Set the transmit descriptor write-back policy for both queues */
4817 txdctl = er32(TXDCTL(0));
4818 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4819 E1000_TXDCTL_FULL_TX_DESC_WB);
4820 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4821 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4822 ew32(TXDCTL(0), txdctl);
4823 txdctl = er32(TXDCTL(1));
4824 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4825 E1000_TXDCTL_FULL_TX_DESC_WB);
4826 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4827 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4828 ew32(TXDCTL(1), txdctl);
4829
4830 /* ICH8 has opposite polarity of no_snoop bits.
4831 * By default, we should use snoop behavior.
4832 */
4833 if (mac->type == e1000_ich8lan)
4834 snoop = PCIE_ICH8_SNOOP_ALL;
4835 else
4836 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4837 e1000e_set_pcie_no_snoop(hw, snoop);
4838
4839 ctrl_ext = er32(CTRL_EXT);
4840 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4841 ew32(CTRL_EXT, ctrl_ext);
4842
4843 /* Clear all of the statistics registers (clear on read). It is
4844 * important that we do this after we have tried to establish link
4845 * because the symbol error count will increment wildly if there
4846 * is no link.
4847 */
4848 e1000_clear_hw_cntrs_ich8lan(hw);
4849
4850 return ret_val;
4851 }
4852
4853 /**
4854 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4855 * @hw: pointer to the HW structure
4856 *
4857 * Sets/Clears required hardware bits necessary for correctly setting up the
4858 * hardware for transmit and receive.
4859 **/
4860 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4861 {
4862 u32 reg;
4863
4864 /* Extended Device Control */
4865 reg = er32(CTRL_EXT);
4866 reg |= BIT(22);
4867 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4868 if (hw->mac.type >= e1000_pchlan)
4869 reg |= E1000_CTRL_EXT_PHYPDEN;
4870 ew32(CTRL_EXT, reg);
4871
4872 /* Transmit Descriptor Control 0 */
4873 reg = er32(TXDCTL(0));
4874 reg |= BIT(22);
4875 ew32(TXDCTL(0), reg);
4876
4877 /* Transmit Descriptor Control 1 */
4878 reg = er32(TXDCTL(1));
4879 reg |= BIT(22);
4880 ew32(TXDCTL(1), reg);
4881
4882 /* Transmit Arbitration Control 0 */
4883 reg = er32(TARC(0));
4884 if (hw->mac.type == e1000_ich8lan)
4885 reg |= BIT(28) | BIT(29);
4886 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4887 ew32(TARC(0), reg);
4888
4889 /* Transmit Arbitration Control 1 */
4890 reg = er32(TARC(1));
4891 if (er32(TCTL) & E1000_TCTL_MULR)
4892 reg &= ~BIT(28);
4893 else
4894 reg |= BIT(28);
4895 reg |= BIT(24) | BIT(26) | BIT(30);
4896 ew32(TARC(1), reg);
4897
4898 /* Device Status */
4899 if (hw->mac.type == e1000_ich8lan) {
4900 reg = er32(STATUS);
4901 reg &= ~BIT(31);
4902 ew32(STATUS, reg);
4903 }
4904
4905 /* work-around descriptor data corruption issue during nfs v2 udp
4906 * traffic, just disable the nfs filtering capability
4907 */
4908 reg = er32(RFCTL);
4909 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4910
4911 /* Disable IPv6 extension header parsing because some malformed
4912 * IPv6 headers can hang the Rx.
4913 */
4914 if (hw->mac.type == e1000_ich8lan)
4915 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4916 ew32(RFCTL, reg);
4917
4918 /* Enable ECC on Lynxpoint */
4919 if (hw->mac.type >= e1000_pch_lpt) {
4920 reg = er32(PBECCSTS);
4921 reg |= E1000_PBECCSTS_ECC_ENABLE;
4922 ew32(PBECCSTS, reg);
4923
4924 reg = er32(CTRL);
4925 reg |= E1000_CTRL_MEHE;
4926 ew32(CTRL, reg);
4927 }
4928 }
4929
4930 /**
4931 * e1000_setup_link_ich8lan - Setup flow control and link settings
4932 * @hw: pointer to the HW structure
4933 *
4934 * Determines which flow control settings to use, then configures flow
4935 * control. Calls the appropriate media-specific link configuration
4936 * function. Assuming the adapter has a valid link partner, a valid link
4937 * should be established. Assumes the hardware has previously been reset
4938 * and the transmitter and receiver are not enabled.
4939 **/
4940 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4941 {
4942 s32 ret_val;
4943
4944 if (hw->phy.ops.check_reset_block(hw))
4945 return 0;
4946
4947 /* ICH parts do not have a word in the NVM to determine
4948 * the default flow control setting, so we explicitly
4949 * set it to full.
4950 */
4951 if (hw->fc.requested_mode == e1000_fc_default) {
4952 /* Workaround h/w hang when Tx flow control enabled */
4953 if (hw->mac.type == e1000_pchlan)
4954 hw->fc.requested_mode = e1000_fc_rx_pause;
4955 else
4956 hw->fc.requested_mode = e1000_fc_full;
4957 }
4958
4959 /* Save off the requested flow control mode for use later. Depending
4960 * on the link partner's capabilities, we may or may not use this mode.
4961 */
4962 hw->fc.current_mode = hw->fc.requested_mode;
4963
4964 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4965
4966 /* Continue to configure the copper link. */
4967 ret_val = hw->mac.ops.setup_physical_interface(hw);
4968 if (ret_val)
4969 return ret_val;
4970
4971 ew32(FCTTV, hw->fc.pause_time);
4972 if ((hw->phy.type == e1000_phy_82578) ||
4973 (hw->phy.type == e1000_phy_82579) ||
4974 (hw->phy.type == e1000_phy_i217) ||
4975 (hw->phy.type == e1000_phy_82577)) {
4976 ew32(FCRTV_PCH, hw->fc.refresh_time);
4977
4978 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4979 hw->fc.pause_time);
4980 if (ret_val)
4981 return ret_val;
4982 }
4983
4984 return e1000e_set_fc_watermarks(hw);
4985 }
4986
4987 /**
4988 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4989 * @hw: pointer to the HW structure
4990 *
4991 * Configures the kumeran interface to the PHY to wait the appropriate time
4992 * when polling the PHY, then call the generic setup_copper_link to finish
4993 * configuring the copper link.
4994 **/
4995 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4996 {
4997 u32 ctrl;
4998 s32 ret_val;
4999 u16 reg_data;
5000
5001 ctrl = er32(CTRL);
5002 ctrl |= E1000_CTRL_SLU;
5003 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5004 ew32(CTRL, ctrl);
5005
5006 /* Set the mac to wait the maximum time between each iteration
5007 * and increase the max iterations when polling the phy;
5008 * this fixes erroneous timeouts at 10Mbps.
5009 */
5010 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5011 if (ret_val)
5012 return ret_val;
5013 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5014 &reg_data);
5015 if (ret_val)
5016 return ret_val;
5017 reg_data |= 0x3F;
5018 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5019 reg_data);
5020 if (ret_val)
5021 return ret_val;
5022
5023 switch (hw->phy.type) {
5024 case e1000_phy_igp_3:
5025 ret_val = e1000e_copper_link_setup_igp(hw);
5026 if (ret_val)
5027 return ret_val;
5028 break;
5029 case e1000_phy_bm:
5030 case e1000_phy_82578:
5031 ret_val = e1000e_copper_link_setup_m88(hw);
5032 if (ret_val)
5033 return ret_val;
5034 break;
5035 case e1000_phy_82577:
5036 case e1000_phy_82579:
5037 ret_val = e1000_copper_link_setup_82577(hw);
5038 if (ret_val)
5039 return ret_val;
5040 break;
5041 case e1000_phy_ife:
5042 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5043 if (ret_val)
5044 return ret_val;
5045
5046 reg_data &= ~IFE_PMC_AUTO_MDIX;
5047
5048 switch (hw->phy.mdix) {
5049 case 1:
5050 reg_data &= ~IFE_PMC_FORCE_MDIX;
5051 break;
5052 case 2:
5053 reg_data |= IFE_PMC_FORCE_MDIX;
5054 break;
5055 case 0:
5056 default:
5057 reg_data |= IFE_PMC_AUTO_MDIX;
5058 break;
5059 }
5060 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5061 if (ret_val)
5062 return ret_val;
5063 break;
5064 default:
5065 break;
5066 }
5067
5068 return e1000e_setup_copper_link(hw);
5069 }
5070
5071 /**
5072 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5073 * @hw: pointer to the HW structure
5074 *
5075 * Calls the PHY specific link setup function and then calls the
5076 * generic setup_copper_link to finish configuring the link for
5077 * Lynxpoint PCH devices
5078 **/
5079 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5080 {
5081 u32 ctrl;
5082 s32 ret_val;
5083
5084 ctrl = er32(CTRL);
5085 ctrl |= E1000_CTRL_SLU;
5086 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5087 ew32(CTRL, ctrl);
5088
5089 ret_val = e1000_copper_link_setup_82577(hw);
5090 if (ret_val)
5091 return ret_val;
5092
5093 return e1000e_setup_copper_link(hw);
5094 }
5095
5096 /**
5097 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5098 * @hw: pointer to the HW structure
5099 * @speed: pointer to store current link speed
5100 * @duplex: pointer to store the current link duplex
5101 *
5102 * Calls the generic get_speed_and_duplex to retrieve the current link
5103 * information and then calls the Kumeran lock loss workaround for links at
5104 * gigabit speeds.
5105 **/
5106 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5107 u16 *duplex)
5108 {
5109 s32 ret_val;
5110
5111 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5112 if (ret_val)
5113 return ret_val;
5114
5115 if ((hw->mac.type == e1000_ich8lan) &&
5116 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5117 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5118 }
5119
5120 return ret_val;
5121 }
5122
5123 /**
5124 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5125 * @hw: pointer to the HW structure
5126 *
5127 * Work-around for 82566 Kumeran PCS lock loss:
5128 * On link status change (i.e. PCI reset, speed change) and link is up and
5129 * speed is gigabit-
5130 * 0) if workaround is optionally disabled do nothing
5131 * 1) wait 1ms for Kumeran link to come up
5132 * 2) check Kumeran Diagnostic register PCS lock loss bit
5133 * 3) if not set the link is locked (all is good), otherwise...
5134 * 4) reset the PHY
5135 * 5) repeat up to 10 times
5136 * Note: this is only called for IGP3 copper when speed is 1gb.
5137 **/
5138 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5139 {
5140 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5141 u32 phy_ctrl;
5142 s32 ret_val;
5143 u16 i, data;
5144 bool link;
5145
5146 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5147 return 0;
5148
5149 /* Make sure link is up before proceeding. If not just return.
5150 * Attempting this while link is negotiating fouled up link
5151 * stability
5152 */
5153 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5154 if (!link)
5155 return 0;
5156
5157 for (i = 0; i < 10; i++) {
5158 /* read once to clear */
5159 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5160 if (ret_val)
5161 return ret_val;
5162 /* and again to get new status */
5163 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5164 if (ret_val)
5165 return ret_val;
5166
5167 /* check for PCS lock */
5168 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5169 return 0;
5170
5171 /* Issue PHY reset */
5172 e1000_phy_hw_reset(hw);
5173 mdelay(5);
5174 }
5175 /* Disable GigE link negotiation */
5176 phy_ctrl = er32(PHY_CTRL);
5177 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5178 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5179 ew32(PHY_CTRL, phy_ctrl);
5180
5181 /* Call gig speed drop workaround on Gig disable before accessing
5182 * any PHY registers
5183 */
5184 e1000e_gig_downshift_workaround_ich8lan(hw);
5185
5186 /* unable to acquire PCS lock */
5187 return -E1000_ERR_PHY;
5188 }
5189
5190 /**
5191 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5192 * @hw: pointer to the HW structure
5193 * @state: boolean value used to set the current Kumeran workaround state
5194 *
5195 * If ICH8, set the current Kumeran workaround state (enabled - true
5196 * /disabled - false).
5197 **/
5198 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5199 bool state)
5200 {
5201 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5202
5203 if (hw->mac.type != e1000_ich8lan) {
5204 e_dbg("Workaround applies to ICH8 only.\n");
5205 return;
5206 }
5207
5208 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5209 }
5210
5211 /**
5212 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5213 * @hw: pointer to the HW structure
5214 *
5215 * Workaround for 82566 power-down on D3 entry:
5216 * 1) disable gigabit link
5217 * 2) write VR power-down enable
5218 * 3) read it back
5219 * Continue if successful, else issue LCD reset and repeat
5220 **/
5221 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5222 {
5223 u32 reg;
5224 u16 data;
5225 u8 retry = 0;
5226
5227 if (hw->phy.type != e1000_phy_igp_3)
5228 return;
5229
5230 /* Try the workaround twice (if needed) */
5231 do {
5232 /* Disable link */
5233 reg = er32(PHY_CTRL);
5234 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5235 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5236 ew32(PHY_CTRL, reg);
5237
5238 /* Call gig speed drop workaround on Gig disable before
5239 * accessing any PHY registers
5240 */
5241 if (hw->mac.type == e1000_ich8lan)
5242 e1000e_gig_downshift_workaround_ich8lan(hw);
5243
5244 /* Write VR power-down enable */
5245 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5246 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5247 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5248
5249 /* Read it back and test */
5250 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5251 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5252 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5253 break;
5254
5255 /* Issue PHY reset and repeat at most one more time */
5256 reg = er32(CTRL);
5257 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5258 retry++;
5259 } while (retry);
5260 }
5261
5262 /**
5263 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5264 * @hw: pointer to the HW structure
5265 *
5266 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5267 * LPLU, Gig disable, MDIC PHY reset):
5268 * 1) Set Kumeran Near-end loopback
5269 * 2) Clear Kumeran Near-end loopback
5270 * Should only be called for ICH8[m] devices with any 1G Phy.
5271 **/
5272 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5273 {
5274 s32 ret_val;
5275 u16 reg_data;
5276
5277 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5278 return;
5279
5280 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5281 &reg_data);
5282 if (ret_val)
5283 return;
5284 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5285 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5286 reg_data);
5287 if (ret_val)
5288 return;
5289 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5290 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5291 }
5292
5293 /**
5294 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5295 * @hw: pointer to the HW structure
5296 *
5297 * During S0 to Sx transition, it is possible the link remains at gig
5298 * instead of negotiating to a lower speed. Before going to Sx, set
5299 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5300 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5301 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5302 * needs to be written.
5303 * Parts that support (and are linked to a partner which support) EEE in
5304 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5305 * than 10Mbps w/o EEE.
5306 **/
5307 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5308 {
5309 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5310 u32 phy_ctrl;
5311 s32 ret_val;
5312
5313 phy_ctrl = er32(PHY_CTRL);
5314 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5315
5316 if (hw->phy.type == e1000_phy_i217) {
5317 u16 phy_reg, device_id = hw->adapter->pdev->device;
5318
5319 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5320 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5321 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5322 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5323 (hw->mac.type >= e1000_pch_spt)) {
5324 u32 fextnvm6 = er32(FEXTNVM6);
5325
5326 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5327 }
5328
5329 ret_val = hw->phy.ops.acquire(hw);
5330 if (ret_val)
5331 goto out;
5332
5333 if (!dev_spec->eee_disable) {
5334 u16 eee_advert;
5335
5336 ret_val =
5337 e1000_read_emi_reg_locked(hw,
5338 I217_EEE_ADVERTISEMENT,
5339 &eee_advert);
5340 if (ret_val)
5341 goto release;
5342
5343 /* Disable LPLU if both link partners support 100BaseT
5344 * EEE and 100Full is advertised on both ends of the
5345 * link, and enable Auto Enable LPI since there will
5346 * be no driver to enable LPI while in Sx.
5347 */
5348 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5349 (dev_spec->eee_lp_ability &
5350 I82579_EEE_100_SUPPORTED) &&
5351 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5352 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5353 E1000_PHY_CTRL_NOND0A_LPLU);
5354
5355 /* Set Auto Enable LPI after link up */
5356 e1e_rphy_locked(hw,
5357 I217_LPI_GPIO_CTRL, &phy_reg);
5358 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5359 e1e_wphy_locked(hw,
5360 I217_LPI_GPIO_CTRL, phy_reg);
5361 }
5362 }
5363
5364 /* For i217 Intel Rapid Start Technology support,
5365 * when the system is going into Sx and no manageability engine
5366 * is present, the driver must configure proxy to reset only on
5367 * power good. LPI (Low Power Idle) state must also reset only
5368 * on power good, as well as the MTA (Multicast table array).
5369 * The SMBus release must also be disabled on LCD reset.
5370 */
5371 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5372 /* Enable proxy to reset only on power good. */
5373 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5374 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5375 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5376
5377 /* Set bit enable LPI (EEE) to reset only on
5378 * power good.
5379 */
5380 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5381 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5382 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5383
5384 /* Disable the SMB release on LCD reset. */
5385 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5386 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5387 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5388 }
5389
5390 /* Enable MTA to reset for Intel Rapid Start Technology
5391 * Support
5392 */
5393 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5394 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5395 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5396
5397 release:
5398 hw->phy.ops.release(hw);
5399 }
5400 out:
5401 ew32(PHY_CTRL, phy_ctrl);
5402
5403 if (hw->mac.type == e1000_ich8lan)
5404 e1000e_gig_downshift_workaround_ich8lan(hw);
5405
5406 if (hw->mac.type >= e1000_pchlan) {
5407 e1000_oem_bits_config_ich8lan(hw, false);
5408
5409 /* Reset PHY to activate OEM bits on 82577/8 */
5410 if (hw->mac.type == e1000_pchlan)
5411 e1000e_phy_hw_reset_generic(hw);
5412
5413 ret_val = hw->phy.ops.acquire(hw);
5414 if (ret_val)
5415 return;
5416 e1000_write_smbus_addr(hw);
5417 hw->phy.ops.release(hw);
5418 }
5419 }
5420
5421 /**
5422 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5423 * @hw: pointer to the HW structure
5424 *
5425 * During Sx to S0 transitions on non-managed devices or managed devices
5426 * on which PHY resets are not blocked, if the PHY registers cannot be
5427 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5428 * the PHY.
5429 * On i217, setup Intel Rapid Start Technology.
5430 **/
5431 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5432 {
5433 s32 ret_val;
5434
5435 if (hw->mac.type < e1000_pch2lan)
5436 return;
5437
5438 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5439 if (ret_val) {
5440 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5441 return;
5442 }
5443
5444 /* For i217 Intel Rapid Start Technology support when the system
5445 * is transitioning from Sx and no manageability engine is present
5446 * configure SMBus to restore on reset, disable proxy, and enable
5447 * the reset on MTA (Multicast table array).
5448 */
5449 if (hw->phy.type == e1000_phy_i217) {
5450 u16 phy_reg;
5451
5452 ret_val = hw->phy.ops.acquire(hw);
5453 if (ret_val) {
5454 e_dbg("Failed to setup iRST\n");
5455 return;
5456 }
5457
5458 /* Clear Auto Enable LPI after link up */
5459 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5460 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5461 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5462
5463 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5464 /* Restore clear on SMB if no manageability engine
5465 * is present
5466 */
5467 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5468 if (ret_val)
5469 goto release;
5470 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5471 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5472
5473 /* Disable Proxy */
5474 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5475 }
5476 /* Enable reset on MTA */
5477 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5478 if (ret_val)
5479 goto release;
5480 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5481 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5482 release:
5483 if (ret_val)
5484 e_dbg("Error %d in resume workarounds\n", ret_val);
5485 hw->phy.ops.release(hw);
5486 }
5487 }
5488
5489 /**
5490 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5491 * @hw: pointer to the HW structure
5492 *
5493 * Return the LED back to the default configuration.
5494 **/
5495 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5496 {
5497 if (hw->phy.type == e1000_phy_ife)
5498 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5499
5500 ew32(LEDCTL, hw->mac.ledctl_default);
5501 return 0;
5502 }
5503
5504 /**
5505 * e1000_led_on_ich8lan - Turn LEDs on
5506 * @hw: pointer to the HW structure
5507 *
5508 * Turn on the LEDs.
5509 **/
5510 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5511 {
5512 if (hw->phy.type == e1000_phy_ife)
5513 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5514 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5515
5516 ew32(LEDCTL, hw->mac.ledctl_mode2);
5517 return 0;
5518 }
5519
5520 /**
5521 * e1000_led_off_ich8lan - Turn LEDs off
5522 * @hw: pointer to the HW structure
5523 *
5524 * Turn off the LEDs.
5525 **/
5526 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5527 {
5528 if (hw->phy.type == e1000_phy_ife)
5529 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5530 (IFE_PSCL_PROBE_MODE |
5531 IFE_PSCL_PROBE_LEDS_OFF));
5532
5533 ew32(LEDCTL, hw->mac.ledctl_mode1);
5534 return 0;
5535 }
5536
5537 /**
5538 * e1000_setup_led_pchlan - Configures SW controllable LED
5539 * @hw: pointer to the HW structure
5540 *
5541 * This prepares the SW controllable LED for use.
5542 **/
5543 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5544 {
5545 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5546 }
5547
5548 /**
5549 * e1000_cleanup_led_pchlan - Restore the default LED operation
5550 * @hw: pointer to the HW structure
5551 *
5552 * Return the LED back to the default configuration.
5553 **/
5554 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5555 {
5556 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5557 }
5558
5559 /**
5560 * e1000_led_on_pchlan - Turn LEDs on
5561 * @hw: pointer to the HW structure
5562 *
5563 * Turn on the LEDs.
5564 **/
5565 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5566 {
5567 u16 data = (u16)hw->mac.ledctl_mode2;
5568 u32 i, led;
5569
5570 /* If no link, then turn LED on by setting the invert bit
5571 * for each LED that's mode is "link_up" in ledctl_mode2.
5572 */
5573 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5574 for (i = 0; i < 3; i++) {
5575 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5576 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5577 E1000_LEDCTL_MODE_LINK_UP)
5578 continue;
5579 if (led & E1000_PHY_LED0_IVRT)
5580 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5581 else
5582 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5583 }
5584 }
5585
5586 return e1e_wphy(hw, HV_LED_CONFIG, data);
5587 }
5588
5589 /**
5590 * e1000_led_off_pchlan - Turn LEDs off
5591 * @hw: pointer to the HW structure
5592 *
5593 * Turn off the LEDs.
5594 **/
5595 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5596 {
5597 u16 data = (u16)hw->mac.ledctl_mode1;
5598 u32 i, led;
5599
5600 /* If no link, then turn LED off by clearing the invert bit
5601 * for each LED that's mode is "link_up" in ledctl_mode1.
5602 */
5603 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5604 for (i = 0; i < 3; i++) {
5605 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5606 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5607 E1000_LEDCTL_MODE_LINK_UP)
5608 continue;
5609 if (led & E1000_PHY_LED0_IVRT)
5610 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5611 else
5612 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5613 }
5614 }
5615
5616 return e1e_wphy(hw, HV_LED_CONFIG, data);
5617 }
5618
5619 /**
5620 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5621 * @hw: pointer to the HW structure
5622 *
5623 * Read appropriate register for the config done bit for completion status
5624 * and configure the PHY through s/w for EEPROM-less parts.
5625 *
5626 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5627 * config done bit, so only an error is logged and continues. If we were
5628 * to return with error, EEPROM-less silicon would not be able to be reset
5629 * or change link.
5630 **/
5631 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5632 {
5633 s32 ret_val = 0;
5634 u32 bank = 0;
5635 u32 status;
5636
5637 e1000e_get_cfg_done_generic(hw);
5638
5639 /* Wait for indication from h/w that it has completed basic config */
5640 if (hw->mac.type >= e1000_ich10lan) {
5641 e1000_lan_init_done_ich8lan(hw);
5642 } else {
5643 ret_val = e1000e_get_auto_rd_done(hw);
5644 if (ret_val) {
5645 /* When auto config read does not complete, do not
5646 * return with an error. This can happen in situations
5647 * where there is no eeprom and prevents getting link.
5648 */
5649 e_dbg("Auto Read Done did not complete\n");
5650 ret_val = 0;
5651 }
5652 }
5653
5654 /* Clear PHY Reset Asserted bit */
5655 status = er32(STATUS);
5656 if (status & E1000_STATUS_PHYRA)
5657 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5658 else
5659 e_dbg("PHY Reset Asserted not set - needs delay\n");
5660
5661 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5662 if (hw->mac.type <= e1000_ich9lan) {
5663 if (!(er32(EECD) & E1000_EECD_PRES) &&
5664 (hw->phy.type == e1000_phy_igp_3)) {
5665 e1000e_phy_init_script_igp3(hw);
5666 }
5667 } else {
5668 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5669 /* Maybe we should do a basic PHY config */
5670 e_dbg("EEPROM not present\n");
5671 ret_val = -E1000_ERR_CONFIG;
5672 }
5673 }
5674
5675 return ret_val;
5676 }
5677
5678 /**
5679 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5680 * @hw: pointer to the HW structure
5681 *
5682 * In the case of a PHY power down to save power, or to turn off link during a
5683 * driver unload, or wake on lan is not enabled, remove the link.
5684 **/
5685 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5686 {
5687 /* If the management interface is not enabled, then power down */
5688 if (!(hw->mac.ops.check_mng_mode(hw) ||
5689 hw->phy.ops.check_reset_block(hw)))
5690 e1000_power_down_phy_copper(hw);
5691 }
5692
5693 /**
5694 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5695 * @hw: pointer to the HW structure
5696 *
5697 * Clears hardware counters specific to the silicon family and calls
5698 * clear_hw_cntrs_generic to clear all general purpose counters.
5699 **/
5700 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5701 {
5702 u16 phy_data;
5703 s32 ret_val;
5704
5705 e1000e_clear_hw_cntrs_base(hw);
5706
5707 er32(ALGNERRC);
5708 er32(RXERRC);
5709 er32(TNCRS);
5710 er32(CEXTERR);
5711 er32(TSCTC);
5712 er32(TSCTFC);
5713
5714 er32(MGTPRC);
5715 er32(MGTPDC);
5716 er32(MGTPTC);
5717
5718 er32(IAC);
5719 er32(ICRXOC);
5720
5721 /* Clear PHY statistics registers */
5722 if ((hw->phy.type == e1000_phy_82578) ||
5723 (hw->phy.type == e1000_phy_82579) ||
5724 (hw->phy.type == e1000_phy_i217) ||
5725 (hw->phy.type == e1000_phy_82577)) {
5726 ret_val = hw->phy.ops.acquire(hw);
5727 if (ret_val)
5728 return;
5729 ret_val = hw->phy.ops.set_page(hw,
5730 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5731 if (ret_val)
5732 goto release;
5733 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5734 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5735 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5736 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5737 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5738 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5739 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5740 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5741 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5742 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5743 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5744 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5745 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5746 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5747 release:
5748 hw->phy.ops.release(hw);
5749 }
5750 }
5751
5752 static const struct e1000_mac_operations ich8_mac_ops = {
5753 /* check_mng_mode dependent on mac type */
5754 .check_for_link = e1000_check_for_copper_link_ich8lan,
5755 /* cleanup_led dependent on mac type */
5756 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5757 .get_bus_info = e1000_get_bus_info_ich8lan,
5758 .set_lan_id = e1000_set_lan_id_single_port,
5759 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5760 /* led_on dependent on mac type */
5761 /* led_off dependent on mac type */
5762 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5763 .reset_hw = e1000_reset_hw_ich8lan,
5764 .init_hw = e1000_init_hw_ich8lan,
5765 .setup_link = e1000_setup_link_ich8lan,
5766 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5767 /* id_led_init dependent on mac type */
5768 .config_collision_dist = e1000e_config_collision_dist_generic,
5769 .rar_set = e1000e_rar_set_generic,
5770 .rar_get_count = e1000e_rar_get_count_generic,
5771 };
5772
5773 static const struct e1000_phy_operations ich8_phy_ops = {
5774 .acquire = e1000_acquire_swflag_ich8lan,
5775 .check_reset_block = e1000_check_reset_block_ich8lan,
5776 .commit = NULL,
5777 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5778 .get_cable_length = e1000e_get_cable_length_igp_2,
5779 .read_reg = e1000e_read_phy_reg_igp,
5780 .release = e1000_release_swflag_ich8lan,
5781 .reset = e1000_phy_hw_reset_ich8lan,
5782 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5783 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5784 .write_reg = e1000e_write_phy_reg_igp,
5785 };
5786
5787 static const struct e1000_nvm_operations ich8_nvm_ops = {
5788 .acquire = e1000_acquire_nvm_ich8lan,
5789 .read = e1000_read_nvm_ich8lan,
5790 .release = e1000_release_nvm_ich8lan,
5791 .reload = e1000e_reload_nvm_generic,
5792 .update = e1000_update_nvm_checksum_ich8lan,
5793 .valid_led_default = e1000_valid_led_default_ich8lan,
5794 .validate = e1000_validate_nvm_checksum_ich8lan,
5795 .write = e1000_write_nvm_ich8lan,
5796 };
5797
5798 static const struct e1000_nvm_operations spt_nvm_ops = {
5799 .acquire = e1000_acquire_nvm_ich8lan,
5800 .release = e1000_release_nvm_ich8lan,
5801 .read = e1000_read_nvm_spt,
5802 .update = e1000_update_nvm_checksum_spt,
5803 .reload = e1000e_reload_nvm_generic,
5804 .valid_led_default = e1000_valid_led_default_ich8lan,
5805 .validate = e1000_validate_nvm_checksum_ich8lan,
5806 .write = e1000_write_nvm_ich8lan,
5807 };
5808
5809 const struct e1000_info e1000_ich8_info = {
5810 .mac = e1000_ich8lan,
5811 .flags = FLAG_HAS_WOL
5812 | FLAG_IS_ICH
5813 | FLAG_HAS_CTRLEXT_ON_LOAD
5814 | FLAG_HAS_AMT
5815 | FLAG_HAS_FLASH
5816 | FLAG_APME_IN_WUC,
5817 .pba = 8,
5818 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5819 .get_variants = e1000_get_variants_ich8lan,
5820 .mac_ops = &ich8_mac_ops,
5821 .phy_ops = &ich8_phy_ops,
5822 .nvm_ops = &ich8_nvm_ops,
5823 };
5824
5825 const struct e1000_info e1000_ich9_info = {
5826 .mac = e1000_ich9lan,
5827 .flags = FLAG_HAS_JUMBO_FRAMES
5828 | FLAG_IS_ICH
5829 | FLAG_HAS_WOL
5830 | FLAG_HAS_CTRLEXT_ON_LOAD
5831 | FLAG_HAS_AMT
5832 | FLAG_HAS_FLASH
5833 | FLAG_APME_IN_WUC,
5834 .pba = 18,
5835 .max_hw_frame_size = DEFAULT_JUMBO,
5836 .get_variants = e1000_get_variants_ich8lan,
5837 .mac_ops = &ich8_mac_ops,
5838 .phy_ops = &ich8_phy_ops,
5839 .nvm_ops = &ich8_nvm_ops,
5840 };
5841
5842 const struct e1000_info e1000_ich10_info = {
5843 .mac = e1000_ich10lan,
5844 .flags = FLAG_HAS_JUMBO_FRAMES
5845 | FLAG_IS_ICH
5846 | FLAG_HAS_WOL
5847 | FLAG_HAS_CTRLEXT_ON_LOAD
5848 | FLAG_HAS_AMT
5849 | FLAG_HAS_FLASH
5850 | FLAG_APME_IN_WUC,
5851 .pba = 18,
5852 .max_hw_frame_size = DEFAULT_JUMBO,
5853 .get_variants = e1000_get_variants_ich8lan,
5854 .mac_ops = &ich8_mac_ops,
5855 .phy_ops = &ich8_phy_ops,
5856 .nvm_ops = &ich8_nvm_ops,
5857 };
5858
5859 const struct e1000_info e1000_pch_info = {
5860 .mac = e1000_pchlan,
5861 .flags = FLAG_IS_ICH
5862 | FLAG_HAS_WOL
5863 | FLAG_HAS_CTRLEXT_ON_LOAD
5864 | FLAG_HAS_AMT
5865 | FLAG_HAS_FLASH
5866 | FLAG_HAS_JUMBO_FRAMES
5867 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5868 | FLAG_APME_IN_WUC,
5869 .flags2 = FLAG2_HAS_PHY_STATS,
5870 .pba = 26,
5871 .max_hw_frame_size = 4096,
5872 .get_variants = e1000_get_variants_ich8lan,
5873 .mac_ops = &ich8_mac_ops,
5874 .phy_ops = &ich8_phy_ops,
5875 .nvm_ops = &ich8_nvm_ops,
5876 };
5877
5878 const struct e1000_info e1000_pch2_info = {
5879 .mac = e1000_pch2lan,
5880 .flags = FLAG_IS_ICH
5881 | FLAG_HAS_WOL
5882 | FLAG_HAS_HW_TIMESTAMP
5883 | FLAG_HAS_CTRLEXT_ON_LOAD
5884 | FLAG_HAS_AMT
5885 | FLAG_HAS_FLASH
5886 | FLAG_HAS_JUMBO_FRAMES
5887 | FLAG_APME_IN_WUC,
5888 .flags2 = FLAG2_HAS_PHY_STATS
5889 | FLAG2_HAS_EEE
5890 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5891 .pba = 26,
5892 .max_hw_frame_size = 9022,
5893 .get_variants = e1000_get_variants_ich8lan,
5894 .mac_ops = &ich8_mac_ops,
5895 .phy_ops = &ich8_phy_ops,
5896 .nvm_ops = &ich8_nvm_ops,
5897 };
5898
5899 const struct e1000_info e1000_pch_lpt_info = {
5900 .mac = e1000_pch_lpt,
5901 .flags = FLAG_IS_ICH
5902 | FLAG_HAS_WOL
5903 | FLAG_HAS_HW_TIMESTAMP
5904 | FLAG_HAS_CTRLEXT_ON_LOAD
5905 | FLAG_HAS_AMT
5906 | FLAG_HAS_FLASH
5907 | FLAG_HAS_JUMBO_FRAMES
5908 | FLAG_APME_IN_WUC,
5909 .flags2 = FLAG2_HAS_PHY_STATS
5910 | FLAG2_HAS_EEE
5911 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5912 .pba = 26,
5913 .max_hw_frame_size = 9022,
5914 .get_variants = e1000_get_variants_ich8lan,
5915 .mac_ops = &ich8_mac_ops,
5916 .phy_ops = &ich8_phy_ops,
5917 .nvm_ops = &ich8_nvm_ops,
5918 };
5919
5920 const struct e1000_info e1000_pch_spt_info = {
5921 .mac = e1000_pch_spt,
5922 .flags = FLAG_IS_ICH
5923 | FLAG_HAS_WOL
5924 | FLAG_HAS_HW_TIMESTAMP
5925 | FLAG_HAS_CTRLEXT_ON_LOAD
5926 | FLAG_HAS_AMT
5927 | FLAG_HAS_FLASH
5928 | FLAG_HAS_JUMBO_FRAMES
5929 | FLAG_APME_IN_WUC,
5930 .flags2 = FLAG2_HAS_PHY_STATS
5931 | FLAG2_HAS_EEE,
5932 .pba = 26,
5933 .max_hw_frame_size = 9022,
5934 .get_variants = e1000_get_variants_ich8lan,
5935 .mac_ops = &ich8_mac_ops,
5936 .phy_ops = &ich8_phy_ops,
5937 .nvm_ops = &spt_nvm_ops,
5938 };
5939
5940 const struct e1000_info e1000_pch_cnp_info = {
5941 .mac = e1000_pch_cnp,
5942 .flags = FLAG_IS_ICH
5943 | FLAG_HAS_WOL
5944 | FLAG_HAS_HW_TIMESTAMP
5945 | FLAG_HAS_CTRLEXT_ON_LOAD
5946 | FLAG_HAS_AMT
5947 | FLAG_HAS_FLASH
5948 | FLAG_HAS_JUMBO_FRAMES
5949 | FLAG_APME_IN_WUC,
5950 .flags2 = FLAG2_HAS_PHY_STATS
5951 | FLAG2_HAS_EEE,
5952 .pba = 26,
5953 .max_hw_frame_size = 9022,
5954 .get_variants = e1000_get_variants_ich8lan,
5955 .mac_ops = &ich8_mac_ops,
5956 .phy_ops = &ich8_phy_ops,
5957 .nvm_ops = &spt_nvm_ops,
5958 };
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