1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 * e1000e_get_bus_info_pcie - Get PCIe bus information
33 * @hw: pointer to the HW structure
35 * Determines and stores the system bus information for a particular
36 * network interface. The following bus information is determined and stored:
37 * bus speed, bus width, type (PCIe), and PCIe function.
39 s32
e1000e_get_bus_info_pcie(struct e1000_hw
*hw
)
41 struct e1000_mac_info
*mac
= &hw
->mac
;
42 struct e1000_bus_info
*bus
= &hw
->bus
;
43 struct e1000_adapter
*adapter
= hw
->adapter
;
44 u16 pcie_link_status
, cap_offset
;
46 cap_offset
= adapter
->pdev
->pcie_cap
;
48 bus
->width
= e1000_bus_width_unknown
;
50 pci_read_config_word(adapter
->pdev
,
51 cap_offset
+ PCIE_LINK_STATUS
,
53 bus
->width
= (enum e1000_bus_width
)((pcie_link_status
&
54 PCIE_LINK_WIDTH_MASK
) >>
55 PCIE_LINK_WIDTH_SHIFT
);
58 mac
->ops
.set_lan_id(hw
);
64 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
66 * @hw: pointer to the HW structure
68 * Determines the LAN function id by reading memory-mapped registers
69 * and swaps the port value if requested.
71 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw
*hw
)
73 struct e1000_bus_info
*bus
= &hw
->bus
;
77 * The status register reports the correct function number
78 * for the device regardless of function swap state.
81 bus
->func
= (reg
& E1000_STATUS_FUNC_MASK
) >> E1000_STATUS_FUNC_SHIFT
;
85 * e1000_set_lan_id_single_port - Set LAN id for a single port device
86 * @hw: pointer to the HW structure
88 * Sets the LAN function id to zero for a single port device.
90 void e1000_set_lan_id_single_port(struct e1000_hw
*hw
)
92 struct e1000_bus_info
*bus
= &hw
->bus
;
98 * e1000_clear_vfta_generic - Clear VLAN filter table
99 * @hw: pointer to the HW structure
101 * Clears the register array which contains the VLAN filter table by
102 * setting all the values to 0.
104 void e1000_clear_vfta_generic(struct e1000_hw
*hw
)
108 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
109 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
, 0);
115 * e1000_write_vfta_generic - Write value to VLAN filter table
116 * @hw: pointer to the HW structure
117 * @offset: register offset in VLAN filter table
118 * @value: register value written to VLAN filter table
120 * Writes value at the given offset in the register array which stores
121 * the VLAN filter table.
123 void e1000_write_vfta_generic(struct e1000_hw
*hw
, u32 offset
, u32 value
)
125 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
, value
);
130 * e1000e_init_rx_addrs - Initialize receive address's
131 * @hw: pointer to the HW structure
132 * @rar_count: receive address registers
134 * Setup the receive address registers by setting the base receive address
135 * register to the devices MAC address and clearing all the other receive
136 * address registers to 0.
138 void e1000e_init_rx_addrs(struct e1000_hw
*hw
, u16 rar_count
)
141 u8 mac_addr
[ETH_ALEN
] = { 0 };
143 /* Setup the receive address */
144 e_dbg("Programming MAC Address into RAR[0]\n");
146 e1000e_rar_set(hw
, hw
->mac
.addr
, 0);
148 /* Zero out the other (rar_entry_count - 1) receive addresses */
149 e_dbg("Clearing RAR[1-%u]\n", rar_count
- 1);
150 for (i
= 1; i
< rar_count
; i
++)
151 e1000e_rar_set(hw
, mac_addr
, i
);
155 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
156 * @hw: pointer to the HW structure
158 * Checks the nvm for an alternate MAC address. An alternate MAC address
159 * can be setup by pre-boot software and must be treated like a permanent
160 * address and must override the actual permanent MAC address. If an
161 * alternate MAC address is found it is programmed into RAR0, replacing
162 * the permanent address that was installed into RAR0 by the Si on reset.
163 * This function will return SUCCESS unless it encounters an error while
164 * reading the EEPROM.
166 s32
e1000_check_alt_mac_addr_generic(struct e1000_hw
*hw
)
170 u16 offset
, nvm_alt_mac_addr_offset
, nvm_data
;
171 u8 alt_mac_addr
[ETH_ALEN
];
173 ret_val
= e1000_read_nvm(hw
, NVM_COMPAT
, 1, &nvm_data
);
177 /* not supported on 82573 */
178 if (hw
->mac
.type
== e1000_82573
)
181 ret_val
= e1000_read_nvm(hw
, NVM_ALT_MAC_ADDR_PTR
, 1,
182 &nvm_alt_mac_addr_offset
);
184 e_dbg("NVM Read Error\n");
188 if ((nvm_alt_mac_addr_offset
== 0xFFFF) ||
189 (nvm_alt_mac_addr_offset
== 0x0000))
190 /* There is no Alternate MAC Address */
193 if (hw
->bus
.func
== E1000_FUNC_1
)
194 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN1
;
195 for (i
= 0; i
< ETH_ALEN
; i
+= 2) {
196 offset
= nvm_alt_mac_addr_offset
+ (i
>> 1);
197 ret_val
= e1000_read_nvm(hw
, offset
, 1, &nvm_data
);
199 e_dbg("NVM Read Error\n");
203 alt_mac_addr
[i
] = (u8
)(nvm_data
& 0xFF);
204 alt_mac_addr
[i
+ 1] = (u8
)(nvm_data
>> 8);
207 /* if multicast bit is set, the alternate address will not be used */
208 if (is_multicast_ether_addr(alt_mac_addr
)) {
209 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
214 * We have a valid alternate MAC address, and we want to treat it the
215 * same as the normal permanent MAC address stored by the HW into the
216 * RAR. Do this by mapping this address into RAR0.
218 e1000e_rar_set(hw
, alt_mac_addr
, 0);
224 * e1000e_rar_set - Set receive address register
225 * @hw: pointer to the HW structure
226 * @addr: pointer to the receive address
227 * @index: receive address array register
229 * Sets the receive address array register at index to the address passed
232 void e1000e_rar_set(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
234 u32 rar_low
, rar_high
;
237 * HW expects these in little endian so we reverse the byte order
238 * from network order (big endian) to little endian
240 rar_low
= ((u32
)addr
[0] | ((u32
)addr
[1] << 8) |
241 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
243 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
245 /* If MAC address zero, no need to set the AV bit */
246 if (rar_low
|| rar_high
)
247 rar_high
|= E1000_RAH_AV
;
250 * Some bridges will combine consecutive 32-bit writes into
251 * a single burst write, which will malfunction on some parts.
252 * The flushes avoid this.
254 ew32(RAL(index
), rar_low
);
256 ew32(RAH(index
), rar_high
);
261 * e1000_hash_mc_addr - Generate a multicast hash value
262 * @hw: pointer to the HW structure
263 * @mc_addr: pointer to a multicast address
265 * Generates a multicast address hash value which is used to determine
266 * the multicast filter table array address and new table value. See
267 * e1000_mta_set_generic()
269 static u32
e1000_hash_mc_addr(struct e1000_hw
*hw
, u8
*mc_addr
)
271 u32 hash_value
, hash_mask
;
274 /* Register count multiplied by bits per register */
275 hash_mask
= (hw
->mac
.mta_reg_count
* 32) - 1;
278 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
279 * where 0xFF would still fall within the hash mask.
281 while (hash_mask
>> bit_shift
!= 0xFF)
285 * The portion of the address that is used for the hash table
286 * is determined by the mc_filter_type setting.
287 * The algorithm is such that there is a total of 8 bits of shifting.
288 * The bit_shift for a mc_filter_type of 0 represents the number of
289 * left-shifts where the MSB of mc_addr[5] would still fall within
290 * the hash_mask. Case 0 does this exactly. Since there are a total
291 * of 8 bits of shifting, then mc_addr[4] will shift right the
292 * remaining number of bits. Thus 8 - bit_shift. The rest of the
293 * cases are a variation of this algorithm...essentially raising the
294 * number of bits to shift mc_addr[5] left, while still keeping the
295 * 8-bit shifting total.
297 * For example, given the following Destination MAC Address and an
298 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
299 * we can see that the bit_shift for case 0 is 4. These are the hash
300 * values resulting from each mc_filter_type...
301 * [0] [1] [2] [3] [4] [5]
305 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
306 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
307 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
308 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
310 switch (hw
->mac
.mc_filter_type
) {
325 hash_value
= hash_mask
& (((mc_addr
[4] >> (8 - bit_shift
)) |
326 (((u16
)mc_addr
[5]) << bit_shift
)));
332 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
333 * @hw: pointer to the HW structure
334 * @mc_addr_list: array of multicast addresses to program
335 * @mc_addr_count: number of multicast addresses to program
337 * Updates entire Multicast Table Array.
338 * The caller must have a packed mc_addr_list of multicast addresses.
340 void e1000e_update_mc_addr_list_generic(struct e1000_hw
*hw
,
341 u8
*mc_addr_list
, u32 mc_addr_count
)
343 u32 hash_value
, hash_bit
, hash_reg
;
346 /* clear mta_shadow */
347 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
349 /* update mta_shadow from mc_addr_list */
350 for (i
= 0; (u32
)i
< mc_addr_count
; i
++) {
351 hash_value
= e1000_hash_mc_addr(hw
, mc_addr_list
);
353 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
354 hash_bit
= hash_value
& 0x1F;
356 hw
->mac
.mta_shadow
[hash_reg
] |= (1 << hash_bit
);
357 mc_addr_list
+= (ETH_ALEN
);
360 /* replace the entire MTA table */
361 for (i
= hw
->mac
.mta_reg_count
- 1; i
>= 0; i
--)
362 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, hw
->mac
.mta_shadow
[i
]);
367 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
368 * @hw: pointer to the HW structure
370 * Clears the base hardware counters by reading the counter registers.
372 void e1000e_clear_hw_cntrs_base(struct e1000_hw
*hw
)
414 * e1000e_check_for_copper_link - Check for link (Copper)
415 * @hw: pointer to the HW structure
417 * Checks to see of the link status of the hardware has changed. If a
418 * change in link status has been detected, then we read the PHY registers
419 * to get the current speed/duplex if link exists.
421 s32
e1000e_check_for_copper_link(struct e1000_hw
*hw
)
423 struct e1000_mac_info
*mac
= &hw
->mac
;
428 * We only want to go out to the PHY registers to see if Auto-Neg
429 * has completed and/or if our link status has changed. The
430 * get_link_status flag is set upon receiving a Link Status
431 * Change or Rx Sequence Error interrupt.
433 if (!mac
->get_link_status
)
437 * First we want to see if the MII Status Register reports
438 * link. If so, then we want to get the current speed/duplex
441 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
446 return 0; /* No link detected */
448 mac
->get_link_status
= false;
451 * Check if there was DownShift, must be checked
452 * immediately after link-up
454 e1000e_check_downshift(hw
);
457 * If we are forcing speed/duplex, then we simply return since
458 * we have already determined whether we have link or not.
461 return -E1000_ERR_CONFIG
;
464 * Auto-Neg is enabled. Auto Speed Detection takes care
465 * of MAC speed/duplex configuration. So we only need to
466 * configure Collision Distance in the MAC.
468 e1000e_config_collision_dist(hw
);
471 * Configure Flow Control now that Auto-Neg has completed.
472 * First, we need to restore the desired flow control
473 * settings because we may have had to re-autoneg with a
474 * different link partner.
476 ret_val
= e1000e_config_fc_after_link_up(hw
);
478 e_dbg("Error configuring flow control\n");
484 * e1000e_check_for_fiber_link - Check for link (Fiber)
485 * @hw: pointer to the HW structure
487 * Checks for link up on the hardware. If link is not up and we have
488 * a signal, then we need to force link up.
490 s32
e1000e_check_for_fiber_link(struct e1000_hw
*hw
)
492 struct e1000_mac_info
*mac
= &hw
->mac
;
499 status
= er32(STATUS
);
503 * If we don't have link (auto-negotiation failed or link partner
504 * cannot auto-negotiate), the cable is plugged in (we have signal),
505 * and our link partner is not trying to auto-negotiate with us (we
506 * are receiving idles or data), we need to force link up. We also
507 * need to give auto-negotiation time to complete, in case the cable
508 * was just plugged in. The autoneg_failed flag does this.
510 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
511 if ((ctrl
& E1000_CTRL_SWDPIN1
) && !(status
& E1000_STATUS_LU
) &&
512 !(rxcw
& E1000_RXCW_C
)) {
513 if (!mac
->autoneg_failed
) {
514 mac
->autoneg_failed
= true;
517 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
519 /* Disable auto-negotiation in the TXCW register */
520 ew32(TXCW
, (mac
->txcw
& ~E1000_TXCW_ANE
));
522 /* Force link-up and also force full-duplex. */
524 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
527 /* Configure Flow Control after forcing link up. */
528 ret_val
= e1000e_config_fc_after_link_up(hw
);
530 e_dbg("Error configuring flow control\n");
533 } else if ((ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
535 * If we are forcing link and we are receiving /C/ ordered
536 * sets, re-enable auto-negotiation in the TXCW register
537 * and disable forced link in the Device Control register
538 * in an attempt to auto-negotiate with our link partner.
540 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
541 ew32(TXCW
, mac
->txcw
);
542 ew32(CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
544 mac
->serdes_has_link
= true;
551 * e1000e_check_for_serdes_link - Check for link (Serdes)
552 * @hw: pointer to the HW structure
554 * Checks for link up on the hardware. If link is not up and we have
555 * a signal, then we need to force link up.
557 s32
e1000e_check_for_serdes_link(struct e1000_hw
*hw
)
559 struct e1000_mac_info
*mac
= &hw
->mac
;
566 status
= er32(STATUS
);
570 * If we don't have link (auto-negotiation failed or link partner
571 * cannot auto-negotiate), and our link partner is not trying to
572 * auto-negotiate with us (we are receiving idles or data),
573 * we need to force link up. We also need to give auto-negotiation
576 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
577 if (!(status
& E1000_STATUS_LU
) && !(rxcw
& E1000_RXCW_C
)) {
578 if (!mac
->autoneg_failed
) {
579 mac
->autoneg_failed
= true;
582 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
584 /* Disable auto-negotiation in the TXCW register */
585 ew32(TXCW
, (mac
->txcw
& ~E1000_TXCW_ANE
));
587 /* Force link-up and also force full-duplex. */
589 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
592 /* Configure Flow Control after forcing link up. */
593 ret_val
= e1000e_config_fc_after_link_up(hw
);
595 e_dbg("Error configuring flow control\n");
598 } else if ((ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
600 * If we are forcing link and we are receiving /C/ ordered
601 * sets, re-enable auto-negotiation in the TXCW register
602 * and disable forced link in the Device Control register
603 * in an attempt to auto-negotiate with our link partner.
605 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
606 ew32(TXCW
, mac
->txcw
);
607 ew32(CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
609 mac
->serdes_has_link
= true;
610 } else if (!(E1000_TXCW_ANE
& er32(TXCW
))) {
612 * If we force link for non-auto-negotiation switch, check
613 * link status based on MAC synchronization for internal
616 /* SYNCH bit and IV bit are sticky. */
619 if (rxcw
& E1000_RXCW_SYNCH
) {
620 if (!(rxcw
& E1000_RXCW_IV
)) {
621 mac
->serdes_has_link
= true;
622 e_dbg("SERDES: Link up - forced.\n");
625 mac
->serdes_has_link
= false;
626 e_dbg("SERDES: Link down - force failed.\n");
630 if (E1000_TXCW_ANE
& er32(TXCW
)) {
631 status
= er32(STATUS
);
632 if (status
& E1000_STATUS_LU
) {
633 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
636 if (rxcw
& E1000_RXCW_SYNCH
) {
637 if (!(rxcw
& E1000_RXCW_IV
)) {
638 mac
->serdes_has_link
= true;
639 e_dbg("SERDES: Link up - autoneg completed successfully.\n");
641 mac
->serdes_has_link
= false;
642 e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n");
645 mac
->serdes_has_link
= false;
646 e_dbg("SERDES: Link down - no sync.\n");
649 mac
->serdes_has_link
= false;
650 e_dbg("SERDES: Link down - autoneg failed\n");
658 * e1000_set_default_fc_generic - Set flow control default values
659 * @hw: pointer to the HW structure
661 * Read the EEPROM for the default values for flow control and store the
664 static s32
e1000_set_default_fc_generic(struct e1000_hw
*hw
)
670 * Read and store word 0x0F of the EEPROM. This word contains bits
671 * that determine the hardware's default PAUSE (flow control) mode,
672 * a bit that determines whether the HW defaults to enabling or
673 * disabling auto-negotiation, and the direction of the
674 * SW defined pins. If there is no SW over-ride of the flow
675 * control setting, then the variable hw->fc will
676 * be initialized based on a value in the EEPROM.
678 ret_val
= e1000_read_nvm(hw
, NVM_INIT_CONTROL2_REG
, 1, &nvm_data
);
681 e_dbg("NVM Read Error\n");
685 if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == 0)
686 hw
->fc
.requested_mode
= e1000_fc_none
;
687 else if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == NVM_WORD0F_ASM_DIR
)
688 hw
->fc
.requested_mode
= e1000_fc_tx_pause
;
690 hw
->fc
.requested_mode
= e1000_fc_full
;
696 * e1000e_setup_link_generic - Setup flow control and link settings
697 * @hw: pointer to the HW structure
699 * Determines which flow control settings to use, then configures flow
700 * control. Calls the appropriate media-specific link configuration
701 * function. Assuming the adapter has a valid link partner, a valid link
702 * should be established. Assumes the hardware has previously been reset
703 * and the transmitter and receiver are not enabled.
705 s32
e1000e_setup_link_generic(struct e1000_hw
*hw
)
707 struct e1000_mac_info
*mac
= &hw
->mac
;
711 * In the case of the phy reset being blocked, we already have a link.
712 * We do not need to set it up again.
714 if (e1000_check_reset_block(hw
))
718 * If requested flow control is set to default, set flow control
719 * based on the EEPROM flow control settings.
721 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
722 ret_val
= e1000_set_default_fc_generic(hw
);
728 * Save off the requested flow control mode for use later. Depending
729 * on the link partner's capabilities, we may or may not use this mode.
731 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
733 e_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.current_mode
);
735 /* Call the necessary media_type subroutine to configure the link. */
736 ret_val
= mac
->ops
.setup_physical_interface(hw
);
741 * Initialize the flow control address, type, and PAUSE timer
742 * registers to their default values. This is done even if flow
743 * control is disabled, because it does not hurt anything to
744 * initialize these registers.
746 e_dbg("Initializing the Flow Control address, type and timer regs\n");
747 ew32(FCT
, FLOW_CONTROL_TYPE
);
748 ew32(FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
749 ew32(FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
751 ew32(FCTTV
, hw
->fc
.pause_time
);
753 return e1000e_set_fc_watermarks(hw
);
757 * e1000_commit_fc_settings_generic - Configure flow control
758 * @hw: pointer to the HW structure
760 * Write the flow control settings to the Transmit Config Word Register (TXCW)
761 * base on the flow control settings in e1000_mac_info.
763 static s32
e1000_commit_fc_settings_generic(struct e1000_hw
*hw
)
765 struct e1000_mac_info
*mac
= &hw
->mac
;
769 * Check for a software override of the flow control settings, and
770 * setup the device accordingly. If auto-negotiation is enabled, then
771 * software will have to set the "PAUSE" bits to the correct value in
772 * the Transmit Config Word Register (TXCW) and re-start auto-
773 * negotiation. However, if auto-negotiation is disabled, then
774 * software will have to manually configure the two flow control enable
775 * bits in the CTRL register.
777 * The possible values of the "fc" parameter are:
778 * 0: Flow control is completely disabled
779 * 1: Rx flow control is enabled (we can receive pause frames,
780 * but not send pause frames).
781 * 2: Tx flow control is enabled (we can send pause frames but we
782 * do not support receiving pause frames).
783 * 3: Both Rx and Tx flow control (symmetric) are enabled.
785 switch (hw
->fc
.current_mode
) {
787 /* Flow control completely disabled by a software over-ride. */
788 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
);
790 case e1000_fc_rx_pause
:
792 * Rx Flow control is enabled and Tx Flow control is disabled
793 * by a software over-ride. Since there really isn't a way to
794 * advertise that we are capable of Rx Pause ONLY, we will
795 * advertise that we support both symmetric and asymmetric Rx
796 * PAUSE. Later, we will disable the adapter's ability to send
799 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
801 case e1000_fc_tx_pause
:
803 * Tx Flow control is enabled, and Rx Flow control is disabled,
804 * by a software over-ride.
806 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_ASM_DIR
);
810 * Flow control (both Rx and Tx) is enabled by a software
813 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
816 e_dbg("Flow control param set incorrectly\n");
817 return -E1000_ERR_CONFIG
;
828 * e1000_poll_fiber_serdes_link_generic - Poll for link up
829 * @hw: pointer to the HW structure
831 * Polls for link up by reading the status register, if link fails to come
832 * up with auto-negotiation, then the link is forced if a signal is detected.
834 static s32
e1000_poll_fiber_serdes_link_generic(struct e1000_hw
*hw
)
836 struct e1000_mac_info
*mac
= &hw
->mac
;
841 * If we have a signal (the cable is plugged in, or assumed true for
842 * serdes media) then poll for a "Link-Up" indication in the Device
843 * Status Register. Time-out if a link isn't seen in 500 milliseconds
844 * seconds (Auto-negotiation should complete in less than 500
845 * milliseconds even if the other end is doing it in SW).
847 for (i
= 0; i
< FIBER_LINK_UP_LIMIT
; i
++) {
848 usleep_range(10000, 20000);
849 status
= er32(STATUS
);
850 if (status
& E1000_STATUS_LU
)
853 if (i
== FIBER_LINK_UP_LIMIT
) {
854 e_dbg("Never got a valid link from auto-neg!!!\n");
855 mac
->autoneg_failed
= true;
857 * AutoNeg failed to achieve a link, so we'll call
858 * mac->check_for_link. This routine will force the
859 * link up if we detect a signal. This will allow us to
860 * communicate with non-autonegotiating link partners.
862 ret_val
= mac
->ops
.check_for_link(hw
);
864 e_dbg("Error while checking for link\n");
867 mac
->autoneg_failed
= false;
869 mac
->autoneg_failed
= false;
870 e_dbg("Valid Link Found\n");
877 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
878 * @hw: pointer to the HW structure
880 * Configures collision distance and flow control for fiber and serdes
881 * links. Upon successful setup, poll for link.
883 s32
e1000e_setup_fiber_serdes_link(struct e1000_hw
*hw
)
890 /* Take the link out of reset */
891 ctrl
&= ~E1000_CTRL_LRST
;
893 e1000e_config_collision_dist(hw
);
895 ret_val
= e1000_commit_fc_settings_generic(hw
);
900 * Since auto-negotiation is enabled, take the link out of reset (the
901 * link will be in reset, because we previously reset the chip). This
902 * will restart auto-negotiation. If auto-negotiation is successful
903 * then the link-up status bit will be set and the flow control enable
904 * bits (RFCE and TFCE) will be set according to their negotiated value.
906 e_dbg("Auto-negotiation enabled\n");
910 usleep_range(1000, 2000);
913 * For these adapters, the SW definable pin 1 is set when the optics
914 * detect a signal. If we have a signal, then poll for a "Link-Up"
917 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
||
918 (er32(CTRL
) & E1000_CTRL_SWDPIN1
)) {
919 ret_val
= e1000_poll_fiber_serdes_link_generic(hw
);
921 e_dbg("No signal detected\n");
928 * e1000e_config_collision_dist - Configure collision distance
929 * @hw: pointer to the HW structure
931 * Configures the collision distance to the default value and is used
932 * during link setup. Currently no func pointer exists and all
933 * implementations are handled in the generic version of this function.
935 void e1000e_config_collision_dist(struct e1000_hw
*hw
)
941 tctl
&= ~E1000_TCTL_COLD
;
942 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
949 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
950 * @hw: pointer to the HW structure
952 * Sets the flow control high/low threshold (watermark) registers. If
953 * flow control XON frame transmission is enabled, then set XON frame
954 * transmission as well.
956 s32
e1000e_set_fc_watermarks(struct e1000_hw
*hw
)
958 u32 fcrtl
= 0, fcrth
= 0;
961 * Set the flow control receive threshold registers. Normally,
962 * these registers will be set to a default threshold that may be
963 * adjusted later by the driver's runtime code. However, if the
964 * ability to transmit pause frames is not enabled, then these
965 * registers will be set to 0.
967 if (hw
->fc
.current_mode
& e1000_fc_tx_pause
) {
969 * We need to set up the Receive Threshold high and low water
970 * marks as well as (optionally) enabling the transmission of
973 fcrtl
= hw
->fc
.low_water
;
974 fcrtl
|= E1000_FCRTL_XONE
;
975 fcrth
= hw
->fc
.high_water
;
984 * e1000e_force_mac_fc - Force the MAC's flow control settings
985 * @hw: pointer to the HW structure
987 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
988 * device control register to reflect the adapter settings. TFCE and RFCE
989 * need to be explicitly set by software when a copper PHY is used because
990 * autonegotiation is managed by the PHY rather than the MAC. Software must
991 * also configure these bits when link is forced on a fiber connection.
993 s32
e1000e_force_mac_fc(struct e1000_hw
*hw
)
1000 * Because we didn't get link via the internal auto-negotiation
1001 * mechanism (we either forced link or we got link via PHY
1002 * auto-neg), we have to manually enable/disable transmit an
1003 * receive flow control.
1005 * The "Case" statement below enables/disable flow control
1006 * according to the "hw->fc.current_mode" parameter.
1008 * The possible values of the "fc" parameter are:
1009 * 0: Flow control is completely disabled
1010 * 1: Rx flow control is enabled (we can receive pause
1011 * frames but not send pause frames).
1012 * 2: Tx flow control is enabled (we can send pause frames
1013 * frames but we do not receive pause frames).
1014 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1015 * other: No other values should be possible at this point.
1017 e_dbg("hw->fc.current_mode = %u\n", hw
->fc
.current_mode
);
1019 switch (hw
->fc
.current_mode
) {
1021 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
1023 case e1000_fc_rx_pause
:
1024 ctrl
&= (~E1000_CTRL_TFCE
);
1025 ctrl
|= E1000_CTRL_RFCE
;
1027 case e1000_fc_tx_pause
:
1028 ctrl
&= (~E1000_CTRL_RFCE
);
1029 ctrl
|= E1000_CTRL_TFCE
;
1032 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
1035 e_dbg("Flow control param set incorrectly\n");
1036 return -E1000_ERR_CONFIG
;
1045 * e1000e_config_fc_after_link_up - Configures flow control after link
1046 * @hw: pointer to the HW structure
1048 * Checks the status of auto-negotiation after link up to ensure that the
1049 * speed and duplex were not forced. If the link needed to be forced, then
1050 * flow control needs to be forced also. If auto-negotiation is enabled
1051 * and did not fail, then we configure flow control based on our link
1054 s32
e1000e_config_fc_after_link_up(struct e1000_hw
*hw
)
1056 struct e1000_mac_info
*mac
= &hw
->mac
;
1058 u16 mii_status_reg
, mii_nway_adv_reg
, mii_nway_lp_ability_reg
;
1062 * Check for the case where we have fiber media and auto-neg failed
1063 * so we had to force link. In this case, we need to force the
1064 * configuration of the MAC to match the "fc" parameter.
1066 if (mac
->autoneg_failed
) {
1067 if (hw
->phy
.media_type
== e1000_media_type_fiber
||
1068 hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
1069 ret_val
= e1000e_force_mac_fc(hw
);
1071 if (hw
->phy
.media_type
== e1000_media_type_copper
)
1072 ret_val
= e1000e_force_mac_fc(hw
);
1076 e_dbg("Error forcing flow control settings\n");
1081 * Check for the case where we have copper media and auto-neg is
1082 * enabled. In this case, we need to check and see if Auto-Neg
1083 * has completed, and if so, how the PHY and link partner has
1084 * flow control configured.
1086 if ((hw
->phy
.media_type
== e1000_media_type_copper
) && mac
->autoneg
) {
1088 * Read the MII Status Register and check to see if AutoNeg
1089 * has completed. We read this twice because this reg has
1090 * some "sticky" (latched) bits.
1092 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &mii_status_reg
);
1095 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &mii_status_reg
);
1099 if (!(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
)) {
1100 e_dbg("Copper PHY and Auto Neg has not completed.\n");
1105 * The AutoNeg process has completed, so we now need to
1106 * read both the Auto Negotiation Advertisement
1107 * Register (Address 4) and the Auto_Negotiation Base
1108 * Page Ability Register (Address 5) to determine how
1109 * flow control was negotiated.
1111 ret_val
= e1e_rphy(hw
, PHY_AUTONEG_ADV
, &mii_nway_adv_reg
);
1115 e1e_rphy(hw
, PHY_LP_ABILITY
, &mii_nway_lp_ability_reg
);
1120 * Two bits in the Auto Negotiation Advertisement Register
1121 * (Address 4) and two bits in the Auto Negotiation Base
1122 * Page Ability Register (Address 5) determine flow control
1123 * for both the PHY and the link partner. The following
1124 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1125 * 1999, describes these PAUSE resolution bits and how flow
1126 * control is determined based upon these settings.
1127 * NOTE: DC = Don't Care
1129 * LOCAL DEVICE | LINK PARTNER
1130 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1131 *-------|---------|-------|---------|--------------------
1132 * 0 | 0 | DC | DC | e1000_fc_none
1133 * 0 | 1 | 0 | DC | e1000_fc_none
1134 * 0 | 1 | 1 | 0 | e1000_fc_none
1135 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1136 * 1 | 0 | 0 | DC | e1000_fc_none
1137 * 1 | DC | 1 | DC | e1000_fc_full
1138 * 1 | 1 | 0 | 0 | e1000_fc_none
1139 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1141 * Are both PAUSE bits set to 1? If so, this implies
1142 * Symmetric Flow Control is enabled at both ends. The
1143 * ASM_DIR bits are irrelevant per the spec.
1145 * For Symmetric Flow Control:
1147 * LOCAL DEVICE | LINK PARTNER
1148 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1149 *-------|---------|-------|---------|--------------------
1150 * 1 | DC | 1 | DC | E1000_fc_full
1153 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
1154 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
1156 * Now we need to check if the user selected Rx ONLY
1157 * of pause frames. In this case, we had to advertise
1158 * FULL flow control because we could not advertise Rx
1159 * ONLY. Hence, we must now check to see if we need to
1160 * turn OFF the TRANSMISSION of PAUSE frames.
1162 if (hw
->fc
.requested_mode
== e1000_fc_full
) {
1163 hw
->fc
.current_mode
= e1000_fc_full
;
1164 e_dbg("Flow Control = FULL.\n");
1166 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1167 e_dbg("Flow Control = Rx PAUSE frames only.\n");
1171 * For receiving PAUSE frames ONLY.
1173 * LOCAL DEVICE | LINK PARTNER
1174 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1175 *-------|---------|-------|---------|--------------------
1176 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1178 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
1179 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
1180 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
1181 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
1182 hw
->fc
.current_mode
= e1000_fc_tx_pause
;
1183 e_dbg("Flow Control = Tx PAUSE frames only.\n");
1186 * For transmitting PAUSE frames ONLY.
1188 * LOCAL DEVICE | LINK PARTNER
1189 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1190 *-------|---------|-------|---------|--------------------
1191 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1193 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
1194 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
1195 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
1196 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
1197 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1198 e_dbg("Flow Control = Rx PAUSE frames only.\n");
1201 * Per the IEEE spec, at this point flow control
1202 * should be disabled.
1204 hw
->fc
.current_mode
= e1000_fc_none
;
1205 e_dbg("Flow Control = NONE.\n");
1209 * Now we need to do one last check... If we auto-
1210 * negotiated to HALF DUPLEX, flow control should not be
1211 * enabled per IEEE 802.3 spec.
1213 ret_val
= mac
->ops
.get_link_up_info(hw
, &speed
, &duplex
);
1215 e_dbg("Error getting link speed and duplex\n");
1219 if (duplex
== HALF_DUPLEX
)
1220 hw
->fc
.current_mode
= e1000_fc_none
;
1223 * Now we call a subroutine to actually force the MAC
1224 * controller to use the correct flow control settings.
1226 ret_val
= e1000e_force_mac_fc(hw
);
1228 e_dbg("Error forcing flow control settings\n");
1237 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1238 * @hw: pointer to the HW structure
1239 * @speed: stores the current speed
1240 * @duplex: stores the current duplex
1242 * Read the status register for the current speed/duplex and store the current
1243 * speed and duplex for copper connections.
1245 s32
e1000e_get_speed_and_duplex_copper(struct e1000_hw
*hw
, u16
*speed
,
1250 status
= er32(STATUS
);
1251 if (status
& E1000_STATUS_SPEED_1000
)
1252 *speed
= SPEED_1000
;
1253 else if (status
& E1000_STATUS_SPEED_100
)
1258 if (status
& E1000_STATUS_FD
)
1259 *duplex
= FULL_DUPLEX
;
1261 *duplex
= HALF_DUPLEX
;
1263 e_dbg("%u Mbps, %s Duplex\n",
1264 *speed
== SPEED_1000
? 1000 : *speed
== SPEED_100
? 100 : 10,
1265 *duplex
== FULL_DUPLEX
? "Full" : "Half");
1271 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1272 * @hw: pointer to the HW structure
1273 * @speed: stores the current speed
1274 * @duplex: stores the current duplex
1276 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1277 * for fiber/serdes links.
1279 s32
e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw
*hw
, u16
*speed
,
1282 *speed
= SPEED_1000
;
1283 *duplex
= FULL_DUPLEX
;
1289 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1290 * @hw: pointer to the HW structure
1292 * Acquire the HW semaphore to access the PHY or NVM
1294 s32
e1000e_get_hw_semaphore(struct e1000_hw
*hw
)
1297 s32 timeout
= hw
->nvm
.word_size
+ 1;
1300 /* Get the SW semaphore */
1301 while (i
< timeout
) {
1303 if (!(swsm
& E1000_SWSM_SMBI
))
1311 e_dbg("Driver can't access device - SMBI bit is set.\n");
1312 return -E1000_ERR_NVM
;
1315 /* Get the FW semaphore. */
1316 for (i
= 0; i
< timeout
; i
++) {
1318 ew32(SWSM
, swsm
| E1000_SWSM_SWESMBI
);
1320 /* Semaphore acquired if bit latched */
1321 if (er32(SWSM
) & E1000_SWSM_SWESMBI
)
1328 /* Release semaphores */
1329 e1000e_put_hw_semaphore(hw
);
1330 e_dbg("Driver can't access the NVM\n");
1331 return -E1000_ERR_NVM
;
1338 * e1000e_put_hw_semaphore - Release hardware semaphore
1339 * @hw: pointer to the HW structure
1341 * Release hardware semaphore used to access the PHY or NVM
1343 void e1000e_put_hw_semaphore(struct e1000_hw
*hw
)
1348 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
1353 * e1000e_get_auto_rd_done - Check for auto read completion
1354 * @hw: pointer to the HW structure
1356 * Check EEPROM for Auto Read done bit.
1358 s32
e1000e_get_auto_rd_done(struct e1000_hw
*hw
)
1362 while (i
< AUTO_READ_DONE_TIMEOUT
) {
1363 if (er32(EECD
) & E1000_EECD_AUTO_RD
)
1365 usleep_range(1000, 2000);
1369 if (i
== AUTO_READ_DONE_TIMEOUT
) {
1370 e_dbg("Auto read by HW from NVM has not completed.\n");
1371 return -E1000_ERR_RESET
;
1378 * e1000e_valid_led_default - Verify a valid default LED config
1379 * @hw: pointer to the HW structure
1380 * @data: pointer to the NVM (EEPROM)
1382 * Read the EEPROM for the current default LED configuration. If the
1383 * LED configuration is not valid, set to a valid LED configuration.
1385 s32
e1000e_valid_led_default(struct e1000_hw
*hw
, u16
*data
)
1389 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1391 e_dbg("NVM Read Error\n");
1395 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
)
1396 *data
= ID_LED_DEFAULT
;
1402 * e1000e_id_led_init_generic -
1403 * @hw: pointer to the HW structure
1406 s32
e1000e_id_led_init_generic(struct e1000_hw
*hw
)
1408 struct e1000_mac_info
*mac
= &hw
->mac
;
1410 const u32 ledctl_mask
= 0x000000FF;
1411 const u32 ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
1412 const u32 ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
1414 const u16 led_mask
= 0x0F;
1416 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
1420 mac
->ledctl_default
= er32(LEDCTL
);
1421 mac
->ledctl_mode1
= mac
->ledctl_default
;
1422 mac
->ledctl_mode2
= mac
->ledctl_default
;
1424 for (i
= 0; i
< 4; i
++) {
1425 temp
= (data
>> (i
<< 2)) & led_mask
;
1427 case ID_LED_ON1_DEF2
:
1428 case ID_LED_ON1_ON2
:
1429 case ID_LED_ON1_OFF2
:
1430 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1431 mac
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
1433 case ID_LED_OFF1_DEF2
:
1434 case ID_LED_OFF1_ON2
:
1435 case ID_LED_OFF1_OFF2
:
1436 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1437 mac
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
1444 case ID_LED_DEF1_ON2
:
1445 case ID_LED_ON1_ON2
:
1446 case ID_LED_OFF1_ON2
:
1447 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1448 mac
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
1450 case ID_LED_DEF1_OFF2
:
1451 case ID_LED_ON1_OFF2
:
1452 case ID_LED_OFF1_OFF2
:
1453 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1454 mac
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
1466 * e1000e_setup_led_generic - Configures SW controllable LED
1467 * @hw: pointer to the HW structure
1469 * This prepares the SW controllable LED for use and saves the current state
1470 * of the LED so it can be later restored.
1472 s32
e1000e_setup_led_generic(struct e1000_hw
*hw
)
1476 if (hw
->mac
.ops
.setup_led
!= e1000e_setup_led_generic
)
1477 return -E1000_ERR_CONFIG
;
1479 if (hw
->phy
.media_type
== e1000_media_type_fiber
) {
1480 ledctl
= er32(LEDCTL
);
1481 hw
->mac
.ledctl_default
= ledctl
;
1483 ledctl
&= ~(E1000_LEDCTL_LED0_IVRT
| E1000_LEDCTL_LED0_BLINK
|
1484 E1000_LEDCTL_LED0_MODE_MASK
);
1485 ledctl
|= (E1000_LEDCTL_MODE_LED_OFF
<<
1486 E1000_LEDCTL_LED0_MODE_SHIFT
);
1487 ew32(LEDCTL
, ledctl
);
1488 } else if (hw
->phy
.media_type
== e1000_media_type_copper
) {
1489 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
1496 * e1000e_cleanup_led_generic - Set LED config to default operation
1497 * @hw: pointer to the HW structure
1499 * Remove the current LED configuration and set the LED configuration
1500 * to the default value, saved from the EEPROM.
1502 s32
e1000e_cleanup_led_generic(struct e1000_hw
*hw
)
1504 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
1509 * e1000e_blink_led_generic - Blink LED
1510 * @hw: pointer to the HW structure
1512 * Blink the LEDs which are set to be on.
1514 s32
e1000e_blink_led_generic(struct e1000_hw
*hw
)
1516 u32 ledctl_blink
= 0;
1519 if (hw
->phy
.media_type
== e1000_media_type_fiber
) {
1520 /* always blink LED0 for PCI-E fiber */
1521 ledctl_blink
= E1000_LEDCTL_LED0_BLINK
|
1522 (E1000_LEDCTL_MODE_LED_ON
<< E1000_LEDCTL_LED0_MODE_SHIFT
);
1525 * set the blink bit for each LED that's "on" (0x0E)
1528 ledctl_blink
= hw
->mac
.ledctl_mode2
;
1529 for (i
= 0; i
< 4; i
++)
1530 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1531 E1000_LEDCTL_MODE_LED_ON
)
1532 ledctl_blink
|= (E1000_LEDCTL_LED0_BLINK
<<
1536 ew32(LEDCTL
, ledctl_blink
);
1542 * e1000e_led_on_generic - Turn LED on
1543 * @hw: pointer to the HW structure
1547 s32
e1000e_led_on_generic(struct e1000_hw
*hw
)
1551 switch (hw
->phy
.media_type
) {
1552 case e1000_media_type_fiber
:
1554 ctrl
&= ~E1000_CTRL_SWDPIN0
;
1555 ctrl
|= E1000_CTRL_SWDPIO0
;
1558 case e1000_media_type_copper
:
1559 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
1569 * e1000e_led_off_generic - Turn LED off
1570 * @hw: pointer to the HW structure
1574 s32
e1000e_led_off_generic(struct e1000_hw
*hw
)
1578 switch (hw
->phy
.media_type
) {
1579 case e1000_media_type_fiber
:
1581 ctrl
|= E1000_CTRL_SWDPIN0
;
1582 ctrl
|= E1000_CTRL_SWDPIO0
;
1585 case e1000_media_type_copper
:
1586 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
1596 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1597 * @hw: pointer to the HW structure
1598 * @no_snoop: bitmap of snoop events
1600 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1602 void e1000e_set_pcie_no_snoop(struct e1000_hw
*hw
, u32 no_snoop
)
1608 gcr
&= ~(PCIE_NO_SNOOP_ALL
);
1615 * e1000e_disable_pcie_master - Disables PCI-express master access
1616 * @hw: pointer to the HW structure
1618 * Returns 0 if successful, else returns -10
1619 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1620 * the master requests to be disabled.
1622 * Disables PCI-Express master access and verifies there are no pending
1625 s32
e1000e_disable_pcie_master(struct e1000_hw
*hw
)
1628 s32 timeout
= MASTER_DISABLE_TIMEOUT
;
1631 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
1635 if (!(er32(STATUS
) & E1000_STATUS_GIO_MASTER_ENABLE
))
1642 e_dbg("Master requests are pending.\n");
1643 return -E1000_ERR_MASTER_REQUESTS_PENDING
;
1650 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1651 * @hw: pointer to the HW structure
1653 * Reset the Adaptive Interframe Spacing throttle to default values.
1655 void e1000e_reset_adaptive(struct e1000_hw
*hw
)
1657 struct e1000_mac_info
*mac
= &hw
->mac
;
1659 if (!mac
->adaptive_ifs
) {
1660 e_dbg("Not in Adaptive IFS mode!\n");
1664 mac
->current_ifs_val
= 0;
1665 mac
->ifs_min_val
= IFS_MIN
;
1666 mac
->ifs_max_val
= IFS_MAX
;
1667 mac
->ifs_step_size
= IFS_STEP
;
1668 mac
->ifs_ratio
= IFS_RATIO
;
1670 mac
->in_ifs_mode
= false;
1675 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1676 * @hw: pointer to the HW structure
1678 * Update the Adaptive Interframe Spacing Throttle value based on the
1679 * time between transmitted packets and time between collisions.
1681 void e1000e_update_adaptive(struct e1000_hw
*hw
)
1683 struct e1000_mac_info
*mac
= &hw
->mac
;
1685 if (!mac
->adaptive_ifs
) {
1686 e_dbg("Not in Adaptive IFS mode!\n");
1690 if ((mac
->collision_delta
* mac
->ifs_ratio
) > mac
->tx_packet_delta
) {
1691 if (mac
->tx_packet_delta
> MIN_NUM_XMITS
) {
1692 mac
->in_ifs_mode
= true;
1693 if (mac
->current_ifs_val
< mac
->ifs_max_val
) {
1694 if (!mac
->current_ifs_val
)
1695 mac
->current_ifs_val
= mac
->ifs_min_val
;
1697 mac
->current_ifs_val
+=
1699 ew32(AIT
, mac
->current_ifs_val
);
1703 if (mac
->in_ifs_mode
&&
1704 (mac
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
1705 mac
->current_ifs_val
= 0;
1706 mac
->in_ifs_mode
= false;