1 /* Intel(R) Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2016 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 * fm10k_reset_hw_pf - PF hardware reset
26 * @hw: pointer to hardware structure
28 * This function should return the hardware to a state similar to the
29 * one it is in after being powered on.
31 static s32
fm10k_reset_hw_pf(struct fm10k_hw
*hw
)
37 /* Disable interrupts */
38 fm10k_write_reg(hw
, FM10K_EIMR
, FM10K_EIMR_DISABLE(ALL
));
40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
41 fm10k_write_reg(hw
, FM10K_ITR2(0), 0);
42 fm10k_write_reg(hw
, FM10K_INT_CTRL
, 0);
44 /* We assume here Tx and Rx queue 0 are owned by the PF */
46 /* Shut off VF access to their queues forcing them to queue 0 */
47 for (i
= 0; i
< FM10K_TQMAP_TABLE_SIZE
; i
++) {
48 fm10k_write_reg(hw
, FM10K_TQMAP(i
), 0);
49 fm10k_write_reg(hw
, FM10K_RQMAP(i
), 0);
52 /* shut down all rings */
53 err
= fm10k_disable_queues_generic(hw
, FM10K_MAX_QUEUES
);
54 if (err
== FM10K_ERR_REQUESTS_PENDING
) {
55 hw
->mac
.reset_while_pending
++;
61 /* Verify that DMA is no longer active */
62 reg
= fm10k_read_reg(hw
, FM10K_DMA_CTRL
);
63 if (reg
& (FM10K_DMA_CTRL_TX_ACTIVE
| FM10K_DMA_CTRL_RX_ACTIVE
))
64 return FM10K_ERR_DMA_PENDING
;
67 /* Inititate data path reset */
68 reg
= FM10K_DMA_CTRL_DATAPATH_RESET
;
69 fm10k_write_reg(hw
, FM10K_DMA_CTRL
, reg
);
71 /* Flush write and allow 100us for reset to complete */
72 fm10k_write_flush(hw
);
73 udelay(FM10K_RESET_TIMEOUT
);
75 /* Verify we made it out of reset */
76 reg
= fm10k_read_reg(hw
, FM10K_IP
);
77 if (!(reg
& FM10K_IP_NOTINRESET
))
78 return FM10K_ERR_RESET_FAILED
;
84 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
85 * @hw: pointer to hardware structure
87 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
89 static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw
*hw
)
91 u16 sriov_ctrl
= fm10k_read_pci_cfg_word(hw
, FM10K_PCIE_SRIOV_CTRL
);
93 return !!(sriov_ctrl
& FM10K_PCIE_SRIOV_CTRL_VFARI
);
97 * fm10k_init_hw_pf - PF hardware initialization
98 * @hw: pointer to hardware structure
101 static s32
fm10k_init_hw_pf(struct fm10k_hw
*hw
)
103 u32 dma_ctrl
, txqctl
;
106 /* Establish default VSI as valid */
107 fm10k_write_reg(hw
, FM10K_DGLORTDEC(fm10k_dglort_default
), 0);
108 fm10k_write_reg(hw
, FM10K_DGLORTMAP(fm10k_dglort_default
),
109 FM10K_DGLORTMAP_ANY
);
111 /* Invalidate all other GLORT entries */
112 for (i
= 1; i
< FM10K_DGLORT_COUNT
; i
++)
113 fm10k_write_reg(hw
, FM10K_DGLORTMAP(i
), FM10K_DGLORTMAP_NONE
);
115 /* reset ITR2(0) to point to itself */
116 fm10k_write_reg(hw
, FM10K_ITR2(0), 0);
118 /* reset VF ITR2(0) to point to 0 avoid PF registers */
119 fm10k_write_reg(hw
, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF
), 0);
121 /* loop through all PF ITR2 registers pointing them to the previous */
122 for (i
= 1; i
< FM10K_ITR_REG_COUNT_PF
; i
++)
123 fm10k_write_reg(hw
, FM10K_ITR2(i
), i
- 1);
125 /* Enable interrupt moderator if not already enabled */
126 fm10k_write_reg(hw
, FM10K_INT_CTRL
, FM10K_INT_CTRL_ENABLEMODERATOR
);
128 /* compute the default txqctl configuration */
129 txqctl
= FM10K_TXQCTL_PF
| FM10K_TXQCTL_UNLIMITED_BW
|
130 (hw
->mac
.default_vid
<< FM10K_TXQCTL_VID_SHIFT
);
132 for (i
= 0; i
< FM10K_MAX_QUEUES
; i
++) {
133 /* configure rings for 256 Queue / 32 Descriptor cache mode */
134 fm10k_write_reg(hw
, FM10K_TQDLOC(i
),
135 (i
* FM10K_TQDLOC_BASE_32_DESC
) |
136 FM10K_TQDLOC_SIZE_32_DESC
);
137 fm10k_write_reg(hw
, FM10K_TXQCTL(i
), txqctl
);
139 /* configure rings to provide TPH processing hints */
140 fm10k_write_reg(hw
, FM10K_TPH_TXCTRL(i
),
141 FM10K_TPH_TXCTRL_DESC_TPHEN
|
142 FM10K_TPH_TXCTRL_DESC_RROEN
|
143 FM10K_TPH_TXCTRL_DESC_WROEN
|
144 FM10K_TPH_TXCTRL_DATA_RROEN
);
145 fm10k_write_reg(hw
, FM10K_TPH_RXCTRL(i
),
146 FM10K_TPH_RXCTRL_DESC_TPHEN
|
147 FM10K_TPH_RXCTRL_DESC_RROEN
|
148 FM10K_TPH_RXCTRL_DATA_WROEN
|
149 FM10K_TPH_RXCTRL_HDR_WROEN
);
152 /* set max hold interval to align with 1.024 usec in all modes and
155 switch (hw
->bus
.speed
) {
156 case fm10k_bus_speed_2500
:
157 dma_ctrl
= FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1
;
158 hw
->mac
.itr_scale
= FM10K_TDLEN_ITR_SCALE_GEN1
;
160 case fm10k_bus_speed_5000
:
161 dma_ctrl
= FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2
;
162 hw
->mac
.itr_scale
= FM10K_TDLEN_ITR_SCALE_GEN2
;
164 case fm10k_bus_speed_8000
:
165 dma_ctrl
= FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3
;
166 hw
->mac
.itr_scale
= FM10K_TDLEN_ITR_SCALE_GEN3
;
170 /* just in case, assume Gen3 ITR scale */
171 hw
->mac
.itr_scale
= FM10K_TDLEN_ITR_SCALE_GEN3
;
175 /* Configure TSO flags */
176 fm10k_write_reg(hw
, FM10K_DTXTCPFLGL
, FM10K_TSO_FLAGS_LOW
);
177 fm10k_write_reg(hw
, FM10K_DTXTCPFLGH
, FM10K_TSO_FLAGS_HI
);
180 * Set Rx Descriptor size to 32
181 * Set Minimum MSS to 64
182 * Set Maximum number of Rx queues to 256 / 32 Descriptor
184 dma_ctrl
|= FM10K_DMA_CTRL_TX_ENABLE
| FM10K_DMA_CTRL_RX_ENABLE
|
185 FM10K_DMA_CTRL_RX_DESC_SIZE
| FM10K_DMA_CTRL_MINMSS_64
|
186 FM10K_DMA_CTRL_32_DESC
;
188 fm10k_write_reg(hw
, FM10K_DMA_CTRL
, dma_ctrl
);
190 /* record maximum queue count, we limit ourselves to 128 */
191 hw
->mac
.max_queues
= FM10K_MAX_QUEUES_PF
;
193 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
194 hw
->iov
.total_vfs
= fm10k_is_ari_hierarchy_pf(hw
) ? 64 : 7;
200 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
201 * @hw: pointer to hardware structure
202 * @vid: VLAN ID to add to table
203 * @vsi: Index indicating VF ID or PF ID in table
204 * @set: Indicates if this is a set or clear operation
206 * This function adds or removes the corresponding VLAN ID from the VLAN
207 * filter table for the corresponding function. In addition to the
208 * standard set/clear that supports one bit a multi-bit write is
209 * supported to set 64 bits at a time.
211 static s32
fm10k_update_vlan_pf(struct fm10k_hw
*hw
, u32 vid
, u8 vsi
, bool set
)
213 u32 vlan_table
, reg
, mask
, bit
, len
;
215 /* verify the VSI index is valid */
216 if (vsi
> FM10K_VLAN_TABLE_VSI_MAX
)
217 return FM10K_ERR_PARAM
;
219 /* VLAN multi-bit write:
220 * The multi-bit write has several parts to it.
222 * 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
223 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
224 * | RSVD0 | Length |C|RSVD0| VLAN ID |
225 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
227 * VLAN ID: Vlan Starting value
228 * RSVD0: Reserved section, must be 0
229 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
230 * Length: Number of times to repeat the bit being set
233 vid
= (vid
<< 17) >> 17;
235 /* verify the reserved 0 fields are 0 */
236 if (len
>= FM10K_VLAN_TABLE_VID_MAX
|| vid
>= FM10K_VLAN_TABLE_VID_MAX
)
237 return FM10K_ERR_PARAM
;
239 /* Loop through the table updating all required VLANs */
240 for (reg
= FM10K_VLAN_TABLE(vsi
, vid
/ 32), bit
= vid
% 32;
241 len
< FM10K_VLAN_TABLE_VID_MAX
;
242 len
-= 32 - bit
, reg
++, bit
= 0) {
243 /* record the initial state of the register */
244 vlan_table
= fm10k_read_reg(hw
, reg
);
246 /* truncate mask if we are at the start or end of the run */
247 mask
= (~(u32
)0 >> ((len
< 31) ? 31 - len
: 0)) << bit
;
249 /* make necessary modifications to the register */
250 mask
&= set
? ~vlan_table
: vlan_table
;
252 fm10k_write_reg(hw
, reg
, vlan_table
^ mask
);
259 * fm10k_read_mac_addr_pf - Read device MAC address
260 * @hw: pointer to the HW structure
262 * Reads the device MAC address from the SM_AREA and stores the value.
264 static s32
fm10k_read_mac_addr_pf(struct fm10k_hw
*hw
)
266 u8 perm_addr
[ETH_ALEN
];
269 serial_num
= fm10k_read_reg(hw
, FM10K_SM_AREA(1));
271 /* last byte should be all 1's */
272 if ((~serial_num
) << 24)
273 return FM10K_ERR_INVALID_MAC_ADDR
;
275 perm_addr
[0] = (u8
)(serial_num
>> 24);
276 perm_addr
[1] = (u8
)(serial_num
>> 16);
277 perm_addr
[2] = (u8
)(serial_num
>> 8);
279 serial_num
= fm10k_read_reg(hw
, FM10K_SM_AREA(0));
281 /* first byte should be all 1's */
282 if ((~serial_num
) >> 24)
283 return FM10K_ERR_INVALID_MAC_ADDR
;
285 perm_addr
[3] = (u8
)(serial_num
>> 16);
286 perm_addr
[4] = (u8
)(serial_num
>> 8);
287 perm_addr
[5] = (u8
)(serial_num
);
289 ether_addr_copy(hw
->mac
.perm_addr
, perm_addr
);
290 ether_addr_copy(hw
->mac
.addr
, perm_addr
);
296 * fm10k_glort_valid_pf - Validate that the provided glort is valid
297 * @hw: pointer to the HW structure
298 * @glort: base glort to be validated
300 * This function will return an error if the provided glort is invalid
302 bool fm10k_glort_valid_pf(struct fm10k_hw
*hw
, u16 glort
)
304 glort
&= hw
->mac
.dglort_map
>> FM10K_DGLORTMAP_MASK_SHIFT
;
306 return glort
== (hw
->mac
.dglort_map
& FM10K_DGLORTMAP_NONE
);
310 * fm10k_update_xc_addr_pf - Update device addresses
311 * @hw: pointer to the HW structure
312 * @glort: base resource tag for this request
313 * @mac: MAC address to add/remove from table
314 * @vid: VLAN ID to add/remove from table
315 * @add: Indicates if this is an add or remove operation
316 * @flags: flags field to indicate add and secure
318 * This function generates a message to the Switch API requesting
319 * that the given logical port add/remove the given L2 MAC/VLAN address.
321 static s32
fm10k_update_xc_addr_pf(struct fm10k_hw
*hw
, u16 glort
,
322 const u8
*mac
, u16 vid
, bool add
, u8 flags
)
324 struct fm10k_mbx_info
*mbx
= &hw
->mbx
;
325 struct fm10k_mac_update mac_update
;
328 /* clear set bit from VLAN ID */
329 vid
&= ~FM10K_VLAN_CLEAR
;
331 /* if glort or VLAN are not valid return error */
332 if (!fm10k_glort_valid_pf(hw
, glort
) || vid
>= FM10K_VLAN_TABLE_VID_MAX
)
333 return FM10K_ERR_PARAM
;
336 mac_update
.mac_lower
= cpu_to_le32(((u32
)mac
[2] << 24) |
337 ((u32
)mac
[3] << 16) |
340 mac_update
.mac_upper
= cpu_to_le16(((u16
)mac
[0] << 8) |
342 mac_update
.vlan
= cpu_to_le16(vid
);
343 mac_update
.glort
= cpu_to_le16(glort
);
344 mac_update
.action
= add
? 0 : 1;
345 mac_update
.flags
= flags
;
347 /* populate mac_update fields */
348 fm10k_tlv_msg_init(msg
, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE
);
349 fm10k_tlv_attr_put_le_struct(msg
, FM10K_PF_ATTR_ID_MAC_UPDATE
,
350 &mac_update
, sizeof(mac_update
));
352 /* load onto outgoing mailbox */
353 return mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
357 * fm10k_update_uc_addr_pf - Update device unicast addresses
358 * @hw: pointer to the HW structure
359 * @glort: base resource tag for this request
360 * @mac: MAC address to add/remove from table
361 * @vid: VLAN ID to add/remove from table
362 * @add: Indicates if this is an add or remove operation
363 * @flags: flags field to indicate add and secure
365 * This function is used to add or remove unicast addresses for
368 static s32
fm10k_update_uc_addr_pf(struct fm10k_hw
*hw
, u16 glort
,
369 const u8
*mac
, u16 vid
, bool add
, u8 flags
)
371 /* verify MAC address is valid */
372 if (!is_valid_ether_addr(mac
))
373 return FM10K_ERR_PARAM
;
375 return fm10k_update_xc_addr_pf(hw
, glort
, mac
, vid
, add
, flags
);
379 * fm10k_update_mc_addr_pf - Update device multicast addresses
380 * @hw: pointer to the HW structure
381 * @glort: base resource tag for this request
382 * @mac: MAC address to add/remove from table
383 * @vid: VLAN ID to add/remove from table
384 * @add: Indicates if this is an add or remove operation
386 * This function is used to add or remove multicast MAC addresses for
389 static s32
fm10k_update_mc_addr_pf(struct fm10k_hw
*hw
, u16 glort
,
390 const u8
*mac
, u16 vid
, bool add
)
392 /* verify multicast address is valid */
393 if (!is_multicast_ether_addr(mac
))
394 return FM10K_ERR_PARAM
;
396 return fm10k_update_xc_addr_pf(hw
, glort
, mac
, vid
, add
, 0);
400 * fm10k_update_xcast_mode_pf - Request update of multicast mode
401 * @hw: pointer to hardware structure
402 * @glort: base resource tag for this request
403 * @mode: integer value indicating mode being requested
405 * This function will attempt to request a higher mode for the port
406 * so that it can enable either multicast, multicast promiscuous, or
407 * promiscuous mode of operation.
409 static s32
fm10k_update_xcast_mode_pf(struct fm10k_hw
*hw
, u16 glort
, u8 mode
)
411 struct fm10k_mbx_info
*mbx
= &hw
->mbx
;
412 u32 msg
[3], xcast_mode
;
414 if (mode
> FM10K_XCAST_MODE_NONE
)
415 return FM10K_ERR_PARAM
;
417 /* if glort is not valid return error */
418 if (!fm10k_glort_valid_pf(hw
, glort
))
419 return FM10K_ERR_PARAM
;
421 /* write xcast mode as a single u32 value,
422 * lower 16 bits: glort
423 * upper 16 bits: mode
425 xcast_mode
= ((u32
)mode
<< 16) | glort
;
427 /* generate message requesting to change xcast mode */
428 fm10k_tlv_msg_init(msg
, FM10K_PF_MSG_ID_XCAST_MODES
);
429 fm10k_tlv_attr_put_u32(msg
, FM10K_PF_ATTR_ID_XCAST_MODE
, xcast_mode
);
431 /* load onto outgoing mailbox */
432 return mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
436 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
437 * @hw: pointer to hardware structure
439 * This function walks through the MSI-X vector table to determine the
440 * number of active interrupts and based on that information updates the
441 * interrupt moderator linked list.
443 static void fm10k_update_int_moderator_pf(struct fm10k_hw
*hw
)
447 /* Disable interrupt moderator */
448 fm10k_write_reg(hw
, FM10K_INT_CTRL
, 0);
450 /* loop through PF from last to first looking enabled vectors */
451 for (i
= FM10K_ITR_REG_COUNT_PF
- 1; i
; i
--) {
452 if (!fm10k_read_reg(hw
, FM10K_MSIX_VECTOR_MASK(i
)))
456 /* always reset VFITR2[0] to point to last enabled PF vector */
457 fm10k_write_reg(hw
, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF
), i
);
459 /* reset ITR2[0] to point to last enabled PF vector */
460 if (!hw
->iov
.num_vfs
)
461 fm10k_write_reg(hw
, FM10K_ITR2(0), i
);
463 /* Enable interrupt moderator */
464 fm10k_write_reg(hw
, FM10K_INT_CTRL
, FM10K_INT_CTRL_ENABLEMODERATOR
);
468 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
469 * @hw: pointer to the HW structure
470 * @glort: base resource tag for this request
471 * @count: number of logical ports being updated
472 * @enable: boolean value indicating enable or disable
474 * This function is used to add/remove a logical port from the switch.
476 static s32
fm10k_update_lport_state_pf(struct fm10k_hw
*hw
, u16 glort
,
477 u16 count
, bool enable
)
479 struct fm10k_mbx_info
*mbx
= &hw
->mbx
;
480 u32 msg
[3], lport_msg
;
482 /* do nothing if we are being asked to create or destroy 0 ports */
486 /* if glort is not valid return error */
487 if (!fm10k_glort_valid_pf(hw
, glort
))
488 return FM10K_ERR_PARAM
;
490 /* reset multicast mode if deleting lport */
492 fm10k_update_xcast_mode_pf(hw
, glort
, FM10K_XCAST_MODE_NONE
);
494 /* construct the lport message from the 2 pieces of data we have */
495 lport_msg
= ((u32
)count
<< 16) | glort
;
497 /* generate lport create/delete message */
498 fm10k_tlv_msg_init(msg
, enable
? FM10K_PF_MSG_ID_LPORT_CREATE
:
499 FM10K_PF_MSG_ID_LPORT_DELETE
);
500 fm10k_tlv_attr_put_u32(msg
, FM10K_PF_ATTR_ID_PORT
, lport_msg
);
502 /* load onto outgoing mailbox */
503 return mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
507 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
508 * @hw: pointer to hardware structure
509 * @dglort: pointer to dglort configuration structure
511 * Reads the configuration structure contained in dglort_cfg and uses
512 * that information to then populate a DGLORTMAP/DEC entry and the queues
513 * to which it has been assigned.
515 static s32
fm10k_configure_dglort_map_pf(struct fm10k_hw
*hw
,
516 struct fm10k_dglort_cfg
*dglort
)
518 u16 glort
, queue_count
, vsi_count
, pc_count
;
519 u16 vsi
, queue
, pc
, q_idx
;
520 u32 txqctl
, dglortdec
, dglortmap
;
522 /* verify the dglort pointer */
524 return FM10K_ERR_PARAM
;
526 /* verify the dglort values */
527 if ((dglort
->idx
> 7) || (dglort
->rss_l
> 7) || (dglort
->pc_l
> 3) ||
528 (dglort
->vsi_l
> 6) || (dglort
->vsi_b
> 64) ||
529 (dglort
->queue_l
> 8) || (dglort
->queue_b
>= 256))
530 return FM10K_ERR_PARAM
;
532 /* determine count of VSIs and queues */
533 queue_count
= BIT(dglort
->rss_l
+ dglort
->pc_l
);
534 vsi_count
= BIT(dglort
->vsi_l
+ dglort
->queue_l
);
535 glort
= dglort
->glort
;
536 q_idx
= dglort
->queue_b
;
538 /* configure SGLORT for queues */
539 for (vsi
= 0; vsi
< vsi_count
; vsi
++, glort
++) {
540 for (queue
= 0; queue
< queue_count
; queue
++, q_idx
++) {
541 if (q_idx
>= FM10K_MAX_QUEUES
)
544 fm10k_write_reg(hw
, FM10K_TX_SGLORT(q_idx
), glort
);
545 fm10k_write_reg(hw
, FM10K_RX_SGLORT(q_idx
), glort
);
549 /* determine count of PCs and queues */
550 queue_count
= BIT(dglort
->queue_l
+ dglort
->rss_l
+ dglort
->vsi_l
);
551 pc_count
= BIT(dglort
->pc_l
);
553 /* configure PC for Tx queues */
554 for (pc
= 0; pc
< pc_count
; pc
++) {
555 q_idx
= pc
+ dglort
->queue_b
;
556 for (queue
= 0; queue
< queue_count
; queue
++) {
557 if (q_idx
>= FM10K_MAX_QUEUES
)
560 txqctl
= fm10k_read_reg(hw
, FM10K_TXQCTL(q_idx
));
561 txqctl
&= ~FM10K_TXQCTL_PC_MASK
;
562 txqctl
|= pc
<< FM10K_TXQCTL_PC_SHIFT
;
563 fm10k_write_reg(hw
, FM10K_TXQCTL(q_idx
), txqctl
);
569 /* configure DGLORTDEC */
570 dglortdec
= ((u32
)(dglort
->rss_l
) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT
) |
571 ((u32
)(dglort
->queue_b
) << FM10K_DGLORTDEC_QBASE_SHIFT
) |
572 ((u32
)(dglort
->pc_l
) << FM10K_DGLORTDEC_PCLENGTH_SHIFT
) |
573 ((u32
)(dglort
->vsi_b
) << FM10K_DGLORTDEC_VSIBASE_SHIFT
) |
574 ((u32
)(dglort
->vsi_l
) << FM10K_DGLORTDEC_VSILENGTH_SHIFT
) |
575 ((u32
)(dglort
->queue_l
));
576 if (dglort
->inner_rss
)
577 dglortdec
|= FM10K_DGLORTDEC_INNERRSS_ENABLE
;
579 /* configure DGLORTMAP */
580 dglortmap
= (dglort
->idx
== fm10k_dglort_default
) ?
581 FM10K_DGLORTMAP_ANY
: FM10K_DGLORTMAP_ZERO
;
582 dglortmap
<<= dglort
->vsi_l
+ dglort
->queue_l
+ dglort
->shared_l
;
583 dglortmap
|= dglort
->glort
;
585 /* write values to hardware */
586 fm10k_write_reg(hw
, FM10K_DGLORTDEC(dglort
->idx
), dglortdec
);
587 fm10k_write_reg(hw
, FM10K_DGLORTMAP(dglort
->idx
), dglortmap
);
592 u16
fm10k_queues_per_pool(struct fm10k_hw
*hw
)
594 u16 num_pools
= hw
->iov
.num_pools
;
596 return (num_pools
> 32) ? 2 : (num_pools
> 16) ? 4 : (num_pools
> 8) ?
597 8 : FM10K_MAX_QUEUES_POOL
;
600 u16
fm10k_vf_queue_index(struct fm10k_hw
*hw
, u16 vf_idx
)
602 u16 num_vfs
= hw
->iov
.num_vfs
;
603 u16 vf_q_idx
= FM10K_MAX_QUEUES
;
605 vf_q_idx
-= fm10k_queues_per_pool(hw
) * (num_vfs
- vf_idx
);
610 static u16
fm10k_vectors_per_pool(struct fm10k_hw
*hw
)
612 u16 num_pools
= hw
->iov
.num_pools
;
614 return (num_pools
> 32) ? 8 : (num_pools
> 16) ? 16 :
615 FM10K_MAX_VECTORS_POOL
;
618 static u16
fm10k_vf_vector_index(struct fm10k_hw
*hw
, u16 vf_idx
)
620 u16 vf_v_idx
= FM10K_MAX_VECTORS_PF
;
622 vf_v_idx
+= fm10k_vectors_per_pool(hw
) * vf_idx
;
628 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
629 * @hw: pointer to the HW structure
630 * @num_vfs: number of VFs to be allocated
631 * @num_pools: number of virtualization pools to be allocated
633 * Allocates queues and traffic classes to virtualization entities to prepare
634 * the PF for SR-IOV and VMDq
636 static s32
fm10k_iov_assign_resources_pf(struct fm10k_hw
*hw
, u16 num_vfs
,
639 u16 qmap_stride
, qpp
, vpp
, vf_q_idx
, vf_q_idx0
, qmap_idx
;
640 u32 vid
= hw
->mac
.default_vid
<< FM10K_TXQCTL_VID_SHIFT
;
643 /* hardware only supports up to 64 pools */
645 return FM10K_ERR_PARAM
;
647 /* the number of VFs cannot exceed the number of pools */
648 if ((num_vfs
> num_pools
) || (num_vfs
> hw
->iov
.total_vfs
))
649 return FM10K_ERR_PARAM
;
651 /* record number of virtualization entities */
652 hw
->iov
.num_vfs
= num_vfs
;
653 hw
->iov
.num_pools
= num_pools
;
655 /* determine qmap offsets and counts */
656 qmap_stride
= (num_vfs
> 8) ? 32 : 256;
657 qpp
= fm10k_queues_per_pool(hw
);
658 vpp
= fm10k_vectors_per_pool(hw
);
660 /* calculate starting index for queues */
661 vf_q_idx
= fm10k_vf_queue_index(hw
, 0);
664 /* establish TCs with -1 credits and no quanta to prevent transmit */
665 for (i
= 0; i
< num_vfs
; i
++) {
666 fm10k_write_reg(hw
, FM10K_TC_MAXCREDIT(i
), 0);
667 fm10k_write_reg(hw
, FM10K_TC_RATE(i
), 0);
668 fm10k_write_reg(hw
, FM10K_TC_CREDIT(i
),
669 FM10K_TC_CREDIT_CREDIT_MASK
);
672 /* zero out all mbmem registers */
673 for (i
= FM10K_VFMBMEM_LEN
* num_vfs
; i
--;)
674 fm10k_write_reg(hw
, FM10K_MBMEM(i
), 0);
676 /* clear event notification of VF FLR */
677 fm10k_write_reg(hw
, FM10K_PFVFLREC(0), ~0);
678 fm10k_write_reg(hw
, FM10K_PFVFLREC(1), ~0);
680 /* loop through unallocated rings assigning them back to PF */
681 for (i
= FM10K_MAX_QUEUES_PF
; i
< vf_q_idx
; i
++) {
682 fm10k_write_reg(hw
, FM10K_TXDCTL(i
), 0);
683 fm10k_write_reg(hw
, FM10K_TXQCTL(i
), FM10K_TXQCTL_PF
|
684 FM10K_TXQCTL_UNLIMITED_BW
| vid
);
685 fm10k_write_reg(hw
, FM10K_RXQCTL(i
), FM10K_RXQCTL_PF
);
688 /* PF should have already updated VFITR2[0] */
690 /* update all ITR registers to flow to VFITR2[0] */
691 for (i
= FM10K_ITR_REG_COUNT_PF
+ 1; i
< FM10K_ITR_REG_COUNT
; i
++) {
692 if (!(i
& (vpp
- 1)))
693 fm10k_write_reg(hw
, FM10K_ITR2(i
), i
- vpp
);
695 fm10k_write_reg(hw
, FM10K_ITR2(i
), i
- 1);
698 /* update PF ITR2[0] to reference the last vector */
699 fm10k_write_reg(hw
, FM10K_ITR2(0),
700 fm10k_vf_vector_index(hw
, num_vfs
- 1));
702 /* loop through rings populating rings and TCs */
703 for (i
= 0; i
< num_vfs
; i
++) {
704 /* record index for VF queue 0 for use in end of loop */
705 vf_q_idx0
= vf_q_idx
;
707 for (j
= 0; j
< qpp
; j
++, qmap_idx
++, vf_q_idx
++) {
708 /* assign VF and locked TC to queues */
709 fm10k_write_reg(hw
, FM10K_TXDCTL(vf_q_idx
), 0);
710 fm10k_write_reg(hw
, FM10K_TXQCTL(vf_q_idx
),
711 (i
<< FM10K_TXQCTL_TC_SHIFT
) | i
|
712 FM10K_TXQCTL_VF
| vid
);
713 fm10k_write_reg(hw
, FM10K_RXDCTL(vf_q_idx
),
714 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY
|
715 FM10K_RXDCTL_DROP_ON_EMPTY
);
716 fm10k_write_reg(hw
, FM10K_RXQCTL(vf_q_idx
),
717 (i
<< FM10K_RXQCTL_VF_SHIFT
) |
720 /* map queue pair to VF */
721 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), vf_q_idx
);
722 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
), vf_q_idx
);
725 /* repeat the first ring for all of the remaining VF rings */
726 for (; j
< qmap_stride
; j
++, qmap_idx
++) {
727 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), vf_q_idx0
);
728 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
), vf_q_idx0
);
732 /* loop through remaining indexes assigning all to queue 0 */
733 while (qmap_idx
< FM10K_TQMAP_TABLE_SIZE
) {
734 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), 0);
735 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
), 0);
743 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
744 * @hw: pointer to the HW structure
745 * @vf_idx: index of VF receiving GLORT
746 * @rate: Rate indicated in Mb/s
748 * Configured the TC for a given VF to allow only up to a given number
749 * of Mb/s of outgoing Tx throughput.
751 static s32
fm10k_iov_configure_tc_pf(struct fm10k_hw
*hw
, u16 vf_idx
, int rate
)
753 /* configure defaults */
754 u32 interval
= FM10K_TC_RATE_INTERVAL_4US_GEN3
;
755 u32 tc_rate
= FM10K_TC_RATE_QUANTA_MASK
;
757 /* verify vf is in range */
758 if (vf_idx
>= hw
->iov
.num_vfs
)
759 return FM10K_ERR_PARAM
;
761 /* set interval to align with 4.096 usec in all modes */
762 switch (hw
->bus
.speed
) {
763 case fm10k_bus_speed_2500
:
764 interval
= FM10K_TC_RATE_INTERVAL_4US_GEN1
;
766 case fm10k_bus_speed_5000
:
767 interval
= FM10K_TC_RATE_INTERVAL_4US_GEN2
;
774 if (rate
> FM10K_VF_TC_MAX
|| rate
< FM10K_VF_TC_MIN
)
775 return FM10K_ERR_PARAM
;
777 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
778 * The rate is provided in Mbits per second
779 * To tralslate from rate to quanta we need to multiply the
780 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
781 * dealing with floating point we can round the values up
782 * to the nearest whole number ratio which gives us 128 / 125.
784 tc_rate
= (rate
* 128) / 125;
786 /* try to keep the rate limiting accurate by increasing
787 * the number of credits and interval for rates less than 4Gb/s
795 /* update rate limiter with new values */
796 fm10k_write_reg(hw
, FM10K_TC_RATE(vf_idx
), tc_rate
| interval
);
797 fm10k_write_reg(hw
, FM10K_TC_MAXCREDIT(vf_idx
), FM10K_TC_MAXCREDIT_64K
);
798 fm10k_write_reg(hw
, FM10K_TC_CREDIT(vf_idx
), FM10K_TC_MAXCREDIT_64K
);
804 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
805 * @hw: pointer to the HW structure
806 * @vf_idx: index of VF receiving GLORT
808 * Update the interrupt moderator linked list to include any MSI-X
809 * interrupts which the VF has enabled in the MSI-X vector table.
811 static s32
fm10k_iov_assign_int_moderator_pf(struct fm10k_hw
*hw
, u16 vf_idx
)
813 u16 vf_v_idx
, vf_v_limit
, i
;
815 /* verify vf is in range */
816 if (vf_idx
>= hw
->iov
.num_vfs
)
817 return FM10K_ERR_PARAM
;
819 /* determine vector offset and count */
820 vf_v_idx
= fm10k_vf_vector_index(hw
, vf_idx
);
821 vf_v_limit
= vf_v_idx
+ fm10k_vectors_per_pool(hw
);
823 /* search for first vector that is not masked */
824 for (i
= vf_v_limit
- 1; i
> vf_v_idx
; i
--) {
825 if (!fm10k_read_reg(hw
, FM10K_MSIX_VECTOR_MASK(i
)))
829 /* reset linked list so it now includes our active vectors */
830 if (vf_idx
== (hw
->iov
.num_vfs
- 1))
831 fm10k_write_reg(hw
, FM10K_ITR2(0), i
);
833 fm10k_write_reg(hw
, FM10K_ITR2(vf_v_limit
), i
);
839 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
840 * @hw: pointer to the HW structure
841 * @vf_info: pointer to VF information structure
843 * Assign a MAC address and default VLAN to a VF and notify it of the update
845 static s32
fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw
*hw
,
846 struct fm10k_vf_info
*vf_info
)
848 u16 qmap_stride
, queues_per_pool
, vf_q_idx
, timeout
, qmap_idx
, i
;
849 u32 msg
[4], txdctl
, txqctl
, tdbal
= 0, tdbah
= 0;
853 /* verify vf is in range */
854 if (!vf_info
|| vf_info
->vf_idx
>= hw
->iov
.num_vfs
)
855 return FM10K_ERR_PARAM
;
857 /* determine qmap offsets and counts */
858 qmap_stride
= (hw
->iov
.num_vfs
> 8) ? 32 : 256;
859 queues_per_pool
= fm10k_queues_per_pool(hw
);
861 /* calculate starting index for queues */
862 vf_idx
= vf_info
->vf_idx
;
863 vf_q_idx
= fm10k_vf_queue_index(hw
, vf_idx
);
864 qmap_idx
= qmap_stride
* vf_idx
;
866 /* Determine correct default VLAN ID. The FM10K_VLAN_OVERRIDE bit is
867 * used here to indicate to the VF that it will not have privilege to
868 * write VLAN_TABLE. All policy is enforced on the PF but this allows
869 * the VF to correctly report errors to userspace rqeuests.
872 vf_vid
= vf_info
->pf_vid
| FM10K_VLAN_OVERRIDE
;
874 vf_vid
= vf_info
->sw_vid
;
876 /* generate MAC_ADDR request */
877 fm10k_tlv_msg_init(msg
, FM10K_VF_MSG_ID_MAC_VLAN
);
878 fm10k_tlv_attr_put_mac_vlan(msg
, FM10K_MAC_VLAN_MSG_DEFAULT_MAC
,
879 vf_info
->mac
, vf_vid
);
881 /* Configure Queue control register with new VLAN ID. The TXQCTL
882 * register is RO from the VF, so the PF must do this even in the
883 * case of notifying the VF of a new VID via the mailbox.
885 txqctl
= ((u32
)vf_vid
<< FM10K_TXQCTL_VID_SHIFT
) &
886 FM10K_TXQCTL_VID_MASK
;
887 txqctl
|= (vf_idx
<< FM10K_TXQCTL_TC_SHIFT
) |
888 FM10K_TXQCTL_VF
| vf_idx
;
890 for (i
= 0; i
< queues_per_pool
; i
++)
891 fm10k_write_reg(hw
, FM10K_TXQCTL(vf_q_idx
+ i
), txqctl
);
893 /* try loading a message onto outgoing mailbox first */
894 if (vf_info
->mbx
.ops
.enqueue_tx
) {
895 err
= vf_info
->mbx
.ops
.enqueue_tx(hw
, &vf_info
->mbx
, msg
);
896 if (err
!= FM10K_MBX_ERR_NO_MBX
)
901 /* If we aren't connected to a mailbox, this is most likely because
902 * the VF driver is not running. It should thus be safe to re-map
903 * queues and use the registers to pass the MAC address so that the VF
904 * driver gets correct information during its initialization.
907 /* MAP Tx queue back to 0 temporarily, and disable it */
908 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), 0);
909 fm10k_write_reg(hw
, FM10K_TXDCTL(vf_q_idx
), 0);
911 /* verify ring has disabled before modifying base address registers */
912 txdctl
= fm10k_read_reg(hw
, FM10K_TXDCTL(vf_q_idx
));
913 for (timeout
= 0; txdctl
& FM10K_TXDCTL_ENABLE
; timeout
++) {
914 /* limit ourselves to a 1ms timeout */
916 err
= FM10K_ERR_DMA_PENDING
;
920 usleep_range(100, 200);
921 txdctl
= fm10k_read_reg(hw
, FM10K_TXDCTL(vf_q_idx
));
924 /* Update base address registers to contain MAC address */
925 if (is_valid_ether_addr(vf_info
->mac
)) {
926 tdbal
= (((u32
)vf_info
->mac
[3]) << 24) |
927 (((u32
)vf_info
->mac
[4]) << 16) |
928 (((u32
)vf_info
->mac
[5]) << 8);
930 tdbah
= (((u32
)0xFF) << 24) |
931 (((u32
)vf_info
->mac
[0]) << 16) |
932 (((u32
)vf_info
->mac
[1]) << 8) |
933 ((u32
)vf_info
->mac
[2]);
936 /* Record the base address into queue 0 */
937 fm10k_write_reg(hw
, FM10K_TDBAL(vf_q_idx
), tdbal
);
938 fm10k_write_reg(hw
, FM10K_TDBAH(vf_q_idx
), tdbah
);
940 /* Provide the VF the ITR scale, using software-defined fields in TDLEN
941 * to pass the information during VF initialization. See definition of
942 * FM10K_TDLEN_ITR_SCALE_SHIFT for more details.
944 fm10k_write_reg(hw
, FM10K_TDLEN(vf_q_idx
), hw
->mac
.itr_scale
<<
945 FM10K_TDLEN_ITR_SCALE_SHIFT
);
948 /* restore the queue back to VF ownership */
949 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), vf_q_idx
);
954 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
955 * @hw: pointer to the HW structure
956 * @vf_info: pointer to VF information structure
958 * Reassign the interrupts and queues to a VF following an FLR
960 static s32
fm10k_iov_reset_resources_pf(struct fm10k_hw
*hw
,
961 struct fm10k_vf_info
*vf_info
)
963 u16 qmap_stride
, queues_per_pool
, vf_q_idx
, qmap_idx
;
964 u32 tdbal
= 0, tdbah
= 0, txqctl
, rxqctl
;
965 u16 vf_v_idx
, vf_v_limit
, vf_vid
;
966 u8 vf_idx
= vf_info
->vf_idx
;
969 /* verify vf is in range */
970 if (vf_idx
>= hw
->iov
.num_vfs
)
971 return FM10K_ERR_PARAM
;
973 /* clear event notification of VF FLR */
974 fm10k_write_reg(hw
, FM10K_PFVFLREC(vf_idx
/ 32), BIT(vf_idx
% 32));
976 /* force timeout and then disconnect the mailbox */
977 vf_info
->mbx
.timeout
= 0;
978 if (vf_info
->mbx
.ops
.disconnect
)
979 vf_info
->mbx
.ops
.disconnect(hw
, &vf_info
->mbx
);
981 /* determine vector offset and count */
982 vf_v_idx
= fm10k_vf_vector_index(hw
, vf_idx
);
983 vf_v_limit
= vf_v_idx
+ fm10k_vectors_per_pool(hw
);
985 /* determine qmap offsets and counts */
986 qmap_stride
= (hw
->iov
.num_vfs
> 8) ? 32 : 256;
987 queues_per_pool
= fm10k_queues_per_pool(hw
);
988 qmap_idx
= qmap_stride
* vf_idx
;
990 /* make all the queues inaccessible to the VF */
991 for (i
= qmap_idx
; i
< (qmap_idx
+ qmap_stride
); i
++) {
992 fm10k_write_reg(hw
, FM10K_TQMAP(i
), 0);
993 fm10k_write_reg(hw
, FM10K_RQMAP(i
), 0);
996 /* calculate starting index for queues */
997 vf_q_idx
= fm10k_vf_queue_index(hw
, vf_idx
);
999 /* determine correct default VLAN ID */
1000 if (vf_info
->pf_vid
)
1001 vf_vid
= vf_info
->pf_vid
;
1003 vf_vid
= vf_info
->sw_vid
;
1005 /* configure Queue control register */
1006 txqctl
= ((u32
)vf_vid
<< FM10K_TXQCTL_VID_SHIFT
) |
1007 (vf_idx
<< FM10K_TXQCTL_TC_SHIFT
) |
1008 FM10K_TXQCTL_VF
| vf_idx
;
1009 rxqctl
= (vf_idx
<< FM10K_RXQCTL_VF_SHIFT
) | FM10K_RXQCTL_VF
;
1011 /* stop further DMA and reset queue ownership back to VF */
1012 for (i
= vf_q_idx
; i
< (queues_per_pool
+ vf_q_idx
); i
++) {
1013 fm10k_write_reg(hw
, FM10K_TXDCTL(i
), 0);
1014 fm10k_write_reg(hw
, FM10K_TXQCTL(i
), txqctl
);
1015 fm10k_write_reg(hw
, FM10K_RXDCTL(i
),
1016 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY
|
1017 FM10K_RXDCTL_DROP_ON_EMPTY
);
1018 fm10k_write_reg(hw
, FM10K_RXQCTL(i
), rxqctl
);
1021 /* reset TC with -1 credits and no quanta to prevent transmit */
1022 fm10k_write_reg(hw
, FM10K_TC_MAXCREDIT(vf_idx
), 0);
1023 fm10k_write_reg(hw
, FM10K_TC_RATE(vf_idx
), 0);
1024 fm10k_write_reg(hw
, FM10K_TC_CREDIT(vf_idx
),
1025 FM10K_TC_CREDIT_CREDIT_MASK
);
1027 /* update our first entry in the table based on previous VF */
1029 hw
->mac
.ops
.update_int_moderator(hw
);
1031 hw
->iov
.ops
.assign_int_moderator(hw
, vf_idx
- 1);
1033 /* reset linked list so it now includes our active vectors */
1034 if (vf_idx
== (hw
->iov
.num_vfs
- 1))
1035 fm10k_write_reg(hw
, FM10K_ITR2(0), vf_v_idx
);
1037 fm10k_write_reg(hw
, FM10K_ITR2(vf_v_limit
), vf_v_idx
);
1039 /* link remaining vectors so that next points to previous */
1040 for (vf_v_idx
++; vf_v_idx
< vf_v_limit
; vf_v_idx
++)
1041 fm10k_write_reg(hw
, FM10K_ITR2(vf_v_idx
), vf_v_idx
- 1);
1043 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1044 for (i
= FM10K_VFMBMEM_LEN
; i
--;)
1045 fm10k_write_reg(hw
, FM10K_MBMEM_VF(vf_idx
, i
), 0);
1046 for (i
= FM10K_VLAN_TABLE_SIZE
; i
--;)
1047 fm10k_write_reg(hw
, FM10K_VLAN_TABLE(vf_info
->vsi
, i
), 0);
1048 for (i
= FM10K_RETA_SIZE
; i
--;)
1049 fm10k_write_reg(hw
, FM10K_RETA(vf_info
->vsi
, i
), 0);
1050 for (i
= FM10K_RSSRK_SIZE
; i
--;)
1051 fm10k_write_reg(hw
, FM10K_RSSRK(vf_info
->vsi
, i
), 0);
1052 fm10k_write_reg(hw
, FM10K_MRQC(vf_info
->vsi
), 0);
1054 /* Update base address registers to contain MAC address */
1055 if (is_valid_ether_addr(vf_info
->mac
)) {
1056 tdbal
= (((u32
)vf_info
->mac
[3]) << 24) |
1057 (((u32
)vf_info
->mac
[4]) << 16) |
1058 (((u32
)vf_info
->mac
[5]) << 8);
1059 tdbah
= (((u32
)0xFF) << 24) |
1060 (((u32
)vf_info
->mac
[0]) << 16) |
1061 (((u32
)vf_info
->mac
[1]) << 8) |
1062 ((u32
)vf_info
->mac
[2]);
1065 /* map queue pairs back to VF from last to first */
1066 for (i
= queues_per_pool
; i
--;) {
1067 fm10k_write_reg(hw
, FM10K_TDBAL(vf_q_idx
+ i
), tdbal
);
1068 fm10k_write_reg(hw
, FM10K_TDBAH(vf_q_idx
+ i
), tdbah
);
1069 /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an
1070 * explanation of how TDLEN is used.
1072 fm10k_write_reg(hw
, FM10K_TDLEN(vf_q_idx
+ i
),
1073 hw
->mac
.itr_scale
<<
1074 FM10K_TDLEN_ITR_SCALE_SHIFT
);
1075 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
+ i
), vf_q_idx
+ i
);
1076 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
+ i
), vf_q_idx
+ i
);
1079 /* repeat the first ring for all the remaining VF rings */
1080 for (i
= queues_per_pool
; i
< qmap_stride
; i
++) {
1081 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
+ i
), vf_q_idx
);
1082 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
+ i
), vf_q_idx
);
1089 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1090 * @hw: pointer to hardware structure
1091 * @vf_info: pointer to VF information structure
1092 * @lport_idx: Logical port offset from the hardware glort
1093 * @flags: Set of capability flags to extend port beyond basic functionality
1095 * This function allows enabling a VF port by assigning it a GLORT and
1096 * setting the flags so that it can enable an Rx mode.
1098 static s32
fm10k_iov_set_lport_pf(struct fm10k_hw
*hw
,
1099 struct fm10k_vf_info
*vf_info
,
1100 u16 lport_idx
, u8 flags
)
1102 u16 glort
= (hw
->mac
.dglort_map
+ lport_idx
) & FM10K_DGLORTMAP_NONE
;
1104 /* if glort is not valid return error */
1105 if (!fm10k_glort_valid_pf(hw
, glort
))
1106 return FM10K_ERR_PARAM
;
1108 vf_info
->vf_flags
= flags
| FM10K_VF_FLAG_NONE_CAPABLE
;
1109 vf_info
->glort
= glort
;
1115 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1116 * @hw: pointer to hardware structure
1117 * @vf_info: pointer to VF information structure
1119 * This function disables a VF port by stripping it of a GLORT and
1120 * setting the flags so that it cannot enable any Rx mode.
1122 static void fm10k_iov_reset_lport_pf(struct fm10k_hw
*hw
,
1123 struct fm10k_vf_info
*vf_info
)
1127 /* need to disable the port if it is already enabled */
1128 if (FM10K_VF_FLAG_ENABLED(vf_info
)) {
1129 /* notify switch that this port has been disabled */
1130 fm10k_update_lport_state_pf(hw
, vf_info
->glort
, 1, false);
1132 /* generate port state response to notify VF it is not ready */
1133 fm10k_tlv_msg_init(msg
, FM10K_VF_MSG_ID_LPORT_STATE
);
1134 vf_info
->mbx
.ops
.enqueue_tx(hw
, &vf_info
->mbx
, msg
);
1137 /* clear flags and glort if it exists */
1138 vf_info
->vf_flags
= 0;
1143 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1144 * @hw: pointer to hardware structure
1145 * @q: stats for all queues of a VF
1146 * @vf_idx: index of VF
1148 * This function collects queue stats for VFs.
1150 static void fm10k_iov_update_stats_pf(struct fm10k_hw
*hw
,
1151 struct fm10k_hw_stats_q
*q
,
1156 /* get stats for all of the queues */
1157 qpp
= fm10k_queues_per_pool(hw
);
1158 idx
= fm10k_vf_queue_index(hw
, vf_idx
);
1159 fm10k_update_hw_stats_q(hw
, q
, idx
, qpp
);
1163 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1164 * @hw: Pointer to hardware structure
1165 * @results: Pointer array to message, results[0] is pointer to message
1166 * @mbx: Pointer to mailbox information structure
1168 * This function is a default handler for MSI-X requests from the VF. The
1169 * assumption is that in this case it is acceptable to just directly
1170 * hand off the message from the VF to the underlying shared code.
1172 s32
fm10k_iov_msg_msix_pf(struct fm10k_hw
*hw
, u32
**results
,
1173 struct fm10k_mbx_info
*mbx
)
1175 struct fm10k_vf_info
*vf_info
= (struct fm10k_vf_info
*)mbx
;
1176 u8 vf_idx
= vf_info
->vf_idx
;
1178 return hw
->iov
.ops
.assign_int_moderator(hw
, vf_idx
);
1182 * fm10k_iov_select_vid - Select correct default VLAN ID
1183 * @hw: Pointer to hardware structure
1184 * @vid: VLAN ID to correct
1186 * Will report an error if the VLAN ID is out of range. For VID = 0, it will
1187 * return either the pf_vid or sw_vid depending on which one is set.
1189 static s32
fm10k_iov_select_vid(struct fm10k_vf_info
*vf_info
, u16 vid
)
1192 return vf_info
->pf_vid
? vf_info
->pf_vid
: vf_info
->sw_vid
;
1193 else if (vf_info
->pf_vid
&& vid
!= vf_info
->pf_vid
)
1194 return FM10K_ERR_PARAM
;
1200 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1201 * @hw: Pointer to hardware structure
1202 * @results: Pointer array to message, results[0] is pointer to message
1203 * @mbx: Pointer to mailbox information structure
1205 * This function is a default handler for MAC/VLAN requests from the VF.
1206 * The assumption is that in this case it is acceptable to just directly
1207 * hand off the message from the VF to the underlying shared code.
1209 s32
fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw
*hw
, u32
**results
,
1210 struct fm10k_mbx_info
*mbx
)
1212 struct fm10k_vf_info
*vf_info
= (struct fm10k_vf_info
*)mbx
;
1220 /* we shouldn't be updating rules on a disabled interface */
1221 if (!FM10K_VF_FLAG_ENABLED(vf_info
))
1222 err
= FM10K_ERR_PARAM
;
1224 if (!err
&& !!results
[FM10K_MAC_VLAN_MSG_VLAN
]) {
1225 result
= results
[FM10K_MAC_VLAN_MSG_VLAN
];
1227 /* record VLAN id requested */
1228 err
= fm10k_tlv_attr_get_u32(result
, &vid
);
1232 set
= !(vid
& FM10K_VLAN_CLEAR
);
1233 vid
&= ~FM10K_VLAN_CLEAR
;
1235 /* if the length field has been set, this is a multi-bit
1236 * update request. For multi-bit requests, simply disallow
1237 * them when the pf_vid has been set. In this case, the PF
1238 * should have already cleared the VLAN_TABLE, and if we
1239 * allowed them, it could allow a rogue VF to receive traffic
1240 * on a VLAN it was not assigned. In the single-bit case, we
1241 * need to modify requests for VLAN 0 to use the default PF or
1242 * SW vid when assigned.
1246 /* prevent multi-bit requests when PF has
1247 * administratively set the VLAN for this VF
1249 if (vf_info
->pf_vid
)
1250 return FM10K_ERR_PARAM
;
1252 err
= fm10k_iov_select_vid(vf_info
, (u16
)vid
);
1259 /* update VSI info for VF in regards to VLAN table */
1260 err
= hw
->mac
.ops
.update_vlan(hw
, vid
, vf_info
->vsi
, set
);
1263 if (!err
&& !!results
[FM10K_MAC_VLAN_MSG_MAC
]) {
1264 result
= results
[FM10K_MAC_VLAN_MSG_MAC
];
1266 /* record unicast MAC address requested */
1267 err
= fm10k_tlv_attr_get_mac_vlan(result
, mac
, &vlan
);
1271 /* block attempts to set MAC for a locked device */
1272 if (is_valid_ether_addr(vf_info
->mac
) &&
1273 !ether_addr_equal(mac
, vf_info
->mac
))
1274 return FM10K_ERR_PARAM
;
1276 set
= !(vlan
& FM10K_VLAN_CLEAR
);
1277 vlan
&= ~FM10K_VLAN_CLEAR
;
1279 err
= fm10k_iov_select_vid(vf_info
, vlan
);
1285 /* notify switch of request for new unicast address */
1286 err
= hw
->mac
.ops
.update_uc_addr(hw
, vf_info
->glort
,
1290 if (!err
&& !!results
[FM10K_MAC_VLAN_MSG_MULTICAST
]) {
1291 result
= results
[FM10K_MAC_VLAN_MSG_MULTICAST
];
1293 /* record multicast MAC address requested */
1294 err
= fm10k_tlv_attr_get_mac_vlan(result
, mac
, &vlan
);
1298 /* verify that the VF is allowed to request multicast */
1299 if (!(vf_info
->vf_flags
& FM10K_VF_FLAG_MULTI_ENABLED
))
1300 return FM10K_ERR_PARAM
;
1302 set
= !(vlan
& FM10K_VLAN_CLEAR
);
1303 vlan
&= ~FM10K_VLAN_CLEAR
;
1305 err
= fm10k_iov_select_vid(vf_info
, vlan
);
1311 /* notify switch of request for new multicast address */
1312 err
= hw
->mac
.ops
.update_mc_addr(hw
, vf_info
->glort
,
1320 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1321 * @vf_info: VF info structure containing capability flags
1322 * @mode: Requested xcast mode
1324 * This function outputs the mode that most closely matches the requested
1325 * mode. If not modes match it will request we disable the port
1327 static u8
fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info
*vf_info
,
1330 u8 vf_flags
= vf_info
->vf_flags
;
1332 /* match up mode to capabilities as best as possible */
1334 case FM10K_XCAST_MODE_PROMISC
:
1335 if (vf_flags
& FM10K_VF_FLAG_PROMISC_CAPABLE
)
1336 return FM10K_XCAST_MODE_PROMISC
;
1338 case FM10K_XCAST_MODE_ALLMULTI
:
1339 if (vf_flags
& FM10K_VF_FLAG_ALLMULTI_CAPABLE
)
1340 return FM10K_XCAST_MODE_ALLMULTI
;
1342 case FM10K_XCAST_MODE_MULTI
:
1343 if (vf_flags
& FM10K_VF_FLAG_MULTI_CAPABLE
)
1344 return FM10K_XCAST_MODE_MULTI
;
1346 case FM10K_XCAST_MODE_NONE
:
1347 if (vf_flags
& FM10K_VF_FLAG_NONE_CAPABLE
)
1348 return FM10K_XCAST_MODE_NONE
;
1354 /* disable interface as it should not be able to request any */
1355 return FM10K_XCAST_MODE_DISABLE
;
1359 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1360 * @hw: Pointer to hardware structure
1361 * @results: Pointer array to message, results[0] is pointer to message
1362 * @mbx: Pointer to mailbox information structure
1364 * This function is a default handler for port state requests. The port
1365 * state requests for now are basic and consist of enabling or disabling
1368 s32
fm10k_iov_msg_lport_state_pf(struct fm10k_hw
*hw
, u32
**results
,
1369 struct fm10k_mbx_info
*mbx
)
1371 struct fm10k_vf_info
*vf_info
= (struct fm10k_vf_info
*)mbx
;
1377 /* verify VF is allowed to enable even minimal mode */
1378 if (!(vf_info
->vf_flags
& FM10K_VF_FLAG_NONE_CAPABLE
))
1379 return FM10K_ERR_PARAM
;
1381 if (!!results
[FM10K_LPORT_STATE_MSG_XCAST_MODE
]) {
1382 result
= results
[FM10K_LPORT_STATE_MSG_XCAST_MODE
];
1384 /* XCAST mode update requested */
1385 err
= fm10k_tlv_attr_get_u8(result
, &mode
);
1387 return FM10K_ERR_PARAM
;
1389 /* prep for possible demotion depending on capabilities */
1390 mode
= fm10k_iov_supported_xcast_mode_pf(vf_info
, mode
);
1392 /* if mode is not currently enabled, enable it */
1393 if (!(FM10K_VF_FLAG_ENABLED(vf_info
) & BIT(mode
)))
1394 fm10k_update_xcast_mode_pf(hw
, vf_info
->glort
, mode
);
1396 /* swap mode back to a bit flag */
1397 mode
= FM10K_VF_FLAG_SET_MODE(mode
);
1398 } else if (!results
[FM10K_LPORT_STATE_MSG_DISABLE
]) {
1399 /* need to disable the port if it is already enabled */
1400 if (FM10K_VF_FLAG_ENABLED(vf_info
))
1401 err
= fm10k_update_lport_state_pf(hw
, vf_info
->glort
,
1404 /* we need to clear VF_FLAG_ENABLED flags in order to ensure
1405 * that we actually re-enable the LPORT state below. Note that
1406 * this has no impact if the VF is already disabled, as the
1407 * flags are already cleared.
1410 vf_info
->vf_flags
= FM10K_VF_FLAG_CAPABLE(vf_info
);
1412 /* when enabling the port we should reset the rate limiters */
1413 hw
->iov
.ops
.configure_tc(hw
, vf_info
->vf_idx
, vf_info
->rate
);
1415 /* set mode for minimal functionality */
1416 mode
= FM10K_VF_FLAG_SET_MODE_NONE
;
1418 /* generate port state response to notify VF it is ready */
1419 fm10k_tlv_msg_init(msg
, FM10K_VF_MSG_ID_LPORT_STATE
);
1420 fm10k_tlv_attr_put_bool(msg
, FM10K_LPORT_STATE_MSG_READY
);
1421 mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
1424 /* if enable state toggled note the update */
1425 if (!err
&& (!FM10K_VF_FLAG_ENABLED(vf_info
) != !mode
))
1426 err
= fm10k_update_lport_state_pf(hw
, vf_info
->glort
, 1,
1429 /* if state change succeeded, then update our stored state */
1430 mode
|= FM10K_VF_FLAG_CAPABLE(vf_info
);
1432 vf_info
->vf_flags
= mode
;
1438 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1439 * @hw: pointer to hardware structure
1440 * @stats: pointer to the stats structure to update
1442 * This function collects and aggregates global and per queue hardware
1445 static void fm10k_update_hw_stats_pf(struct fm10k_hw
*hw
,
1446 struct fm10k_hw_stats
*stats
)
1448 u32 timeout
, ur
, ca
, um
, xec
, vlan_drop
, loopback_drop
, nodesc_drop
;
1451 /* Use Tx queue 0 as a canary to detect a reset */
1452 id
= fm10k_read_reg(hw
, FM10K_TXQCTL(0));
1454 /* Read Global Statistics */
1456 timeout
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_TIMEOUT
,
1458 ur
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_UR
, &stats
->ur
);
1459 ca
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_CA
, &stats
->ca
);
1460 um
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_UM
, &stats
->um
);
1461 xec
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_XEC
, &stats
->xec
);
1462 vlan_drop
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_VLAN_DROP
,
1465 fm10k_read_hw_stats_32b(hw
,
1466 FM10K_STATS_LOOPBACK_DROP
,
1467 &stats
->loopback_drop
);
1468 nodesc_drop
= fm10k_read_hw_stats_32b(hw
,
1469 FM10K_STATS_NODESC_DROP
,
1470 &stats
->nodesc_drop
);
1472 /* if value has not changed then we have consistent data */
1474 id
= fm10k_read_reg(hw
, FM10K_TXQCTL(0));
1475 } while ((id
^ id_prev
) & FM10K_TXQCTL_ID_MASK
);
1477 /* drop non-ID bits and set VALID ID bit */
1478 id
&= FM10K_TXQCTL_ID_MASK
;
1479 id
|= FM10K_STAT_VALID
;
1481 /* Update Global Statistics */
1482 if (stats
->stats_idx
== id
) {
1483 stats
->timeout
.count
+= timeout
;
1484 stats
->ur
.count
+= ur
;
1485 stats
->ca
.count
+= ca
;
1486 stats
->um
.count
+= um
;
1487 stats
->xec
.count
+= xec
;
1488 stats
->vlan_drop
.count
+= vlan_drop
;
1489 stats
->loopback_drop
.count
+= loopback_drop
;
1490 stats
->nodesc_drop
.count
+= nodesc_drop
;
1493 /* Update bases and record current PF id */
1494 fm10k_update_hw_base_32b(&stats
->timeout
, timeout
);
1495 fm10k_update_hw_base_32b(&stats
->ur
, ur
);
1496 fm10k_update_hw_base_32b(&stats
->ca
, ca
);
1497 fm10k_update_hw_base_32b(&stats
->um
, um
);
1498 fm10k_update_hw_base_32b(&stats
->xec
, xec
);
1499 fm10k_update_hw_base_32b(&stats
->vlan_drop
, vlan_drop
);
1500 fm10k_update_hw_base_32b(&stats
->loopback_drop
, loopback_drop
);
1501 fm10k_update_hw_base_32b(&stats
->nodesc_drop
, nodesc_drop
);
1502 stats
->stats_idx
= id
;
1504 /* Update Queue Statistics */
1505 fm10k_update_hw_stats_q(hw
, stats
->q
, 0, hw
->mac
.max_queues
);
1509 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1510 * @hw: pointer to hardware structure
1511 * @stats: pointer to the stats structure to update
1513 * This function resets the base for global and per queue hardware
1516 static void fm10k_rebind_hw_stats_pf(struct fm10k_hw
*hw
,
1517 struct fm10k_hw_stats
*stats
)
1519 /* Unbind Global Statistics */
1520 fm10k_unbind_hw_stats_32b(&stats
->timeout
);
1521 fm10k_unbind_hw_stats_32b(&stats
->ur
);
1522 fm10k_unbind_hw_stats_32b(&stats
->ca
);
1523 fm10k_unbind_hw_stats_32b(&stats
->um
);
1524 fm10k_unbind_hw_stats_32b(&stats
->xec
);
1525 fm10k_unbind_hw_stats_32b(&stats
->vlan_drop
);
1526 fm10k_unbind_hw_stats_32b(&stats
->loopback_drop
);
1527 fm10k_unbind_hw_stats_32b(&stats
->nodesc_drop
);
1529 /* Unbind Queue Statistics */
1530 fm10k_unbind_hw_stats_q(stats
->q
, 0, hw
->mac
.max_queues
);
1532 /* Reinitialize bases for all stats */
1533 fm10k_update_hw_stats_pf(hw
, stats
);
1537 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1538 * @hw: pointer to hardware structure
1539 * @dma_mask: 64 bit DMA mask required for platform
1541 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1542 * to limit the access to memory beyond what is physically in the system.
1544 static void fm10k_set_dma_mask_pf(struct fm10k_hw
*hw
, u64 dma_mask
)
1546 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1547 u32 phyaddr
= (u32
)(dma_mask
>> 32);
1549 fm10k_write_reg(hw
, FM10K_PHYADDR
, phyaddr
);
1553 * fm10k_get_fault_pf - Record a fault in one of the interface units
1554 * @hw: pointer to hardware structure
1555 * @type: pointer to fault type register offset
1556 * @fault: pointer to memory location to record the fault
1558 * Record the fault register contents to the fault data structure and
1559 * clear the entry from the register.
1561 * Returns ERR_PARAM if invalid register is specified or no error is present.
1563 static s32
fm10k_get_fault_pf(struct fm10k_hw
*hw
, int type
,
1564 struct fm10k_fault
*fault
)
1568 /* verify the fault register is in range and is aligned */
1570 case FM10K_PCA_FAULT
:
1571 case FM10K_THI_FAULT
:
1572 case FM10K_FUM_FAULT
:
1575 return FM10K_ERR_PARAM
;
1578 /* only service faults that are valid */
1579 func
= fm10k_read_reg(hw
, type
+ FM10K_FAULT_FUNC
);
1580 if (!(func
& FM10K_FAULT_FUNC_VALID
))
1581 return FM10K_ERR_PARAM
;
1583 /* read remaining fields */
1584 fault
->address
= fm10k_read_reg(hw
, type
+ FM10K_FAULT_ADDR_HI
);
1585 fault
->address
<<= 32;
1586 fault
->address
= fm10k_read_reg(hw
, type
+ FM10K_FAULT_ADDR_LO
);
1587 fault
->specinfo
= fm10k_read_reg(hw
, type
+ FM10K_FAULT_SPECINFO
);
1589 /* clear valid bit to allow for next error */
1590 fm10k_write_reg(hw
, type
+ FM10K_FAULT_FUNC
, FM10K_FAULT_FUNC_VALID
);
1592 /* Record which function triggered the error */
1593 if (func
& FM10K_FAULT_FUNC_PF
)
1596 fault
->func
= 1 + ((func
& FM10K_FAULT_FUNC_VF_MASK
) >>
1597 FM10K_FAULT_FUNC_VF_SHIFT
);
1599 /* record fault type */
1600 fault
->type
= func
& FM10K_FAULT_FUNC_TYPE_MASK
;
1606 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1607 * @hw: pointer to hardware structure
1610 static s32
fm10k_request_lport_map_pf(struct fm10k_hw
*hw
)
1612 struct fm10k_mbx_info
*mbx
= &hw
->mbx
;
1615 /* issue request asking for LPORT map */
1616 fm10k_tlv_msg_init(msg
, FM10K_PF_MSG_ID_LPORT_MAP
);
1618 /* load onto outgoing mailbox */
1619 return mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
1623 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1624 * @hw: pointer to hardware structure
1625 * @switch_ready: pointer to boolean value that will record switch state
1627 * This function will check the DMA_CTRL2 register and mailbox in order
1628 * to determine if the switch is ready for the PF to begin requesting
1629 * addresses and mapping traffic to the local interface.
1631 static s32
fm10k_get_host_state_pf(struct fm10k_hw
*hw
, bool *switch_ready
)
1635 /* verify the switch is ready for interaction */
1636 dma_ctrl2
= fm10k_read_reg(hw
, FM10K_DMA_CTRL2
);
1637 if (!(dma_ctrl2
& FM10K_DMA_CTRL2_SWITCH_READY
))
1640 /* retrieve generic host state info */
1641 return fm10k_get_host_state_generic(hw
, switch_ready
);
1644 /* This structure defines the attibutes to be parsed below */
1645 const struct fm10k_tlv_attr fm10k_lport_map_msg_attr
[] = {
1646 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR
,
1647 sizeof(struct fm10k_swapi_error
)),
1648 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP
),
1653 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1654 * @hw: Pointer to hardware structure
1655 * @results: pointer array containing parsed data
1656 * @mbx: Pointer to mailbox information structure
1658 * This handler configures the lport mapping based on the reply from the
1661 s32
fm10k_msg_lport_map_pf(struct fm10k_hw
*hw
, u32
**results
,
1662 struct fm10k_mbx_info
*mbx
)
1668 err
= fm10k_tlv_attr_get_u32(results
[FM10K_PF_ATTR_ID_LPORT_MAP
],
1673 /* extract values out of the header */
1674 glort
= FM10K_MSG_HDR_FIELD_GET(dglort_map
, LPORT_MAP_GLORT
);
1675 mask
= FM10K_MSG_HDR_FIELD_GET(dglort_map
, LPORT_MAP_MASK
);
1677 /* verify mask is set and none of the masked bits in glort are set */
1678 if (!mask
|| (glort
& ~mask
))
1679 return FM10K_ERR_PARAM
;
1681 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1682 if (((~(mask
- 1) & mask
) + mask
) & FM10K_DGLORTMAP_NONE
)
1683 return FM10K_ERR_PARAM
;
1685 /* record the glort, mask, and port count */
1686 hw
->mac
.dglort_map
= dglort_map
;
1691 const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr
[] = {
1692 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID
),
1697 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1698 * @hw: Pointer to hardware structure
1699 * @results: pointer array containing parsed data
1700 * @mbx: Pointer to mailbox information structure
1702 * This handler configures the default VLAN for the PF
1704 static s32
fm10k_msg_update_pvid_pf(struct fm10k_hw
*hw
, u32
**results
,
1705 struct fm10k_mbx_info
*mbx
)
1711 err
= fm10k_tlv_attr_get_u32(results
[FM10K_PF_ATTR_ID_UPDATE_PVID
],
1716 /* extract values from the pvid update */
1717 glort
= FM10K_MSG_HDR_FIELD_GET(pvid_update
, UPDATE_PVID_GLORT
);
1718 pvid
= FM10K_MSG_HDR_FIELD_GET(pvid_update
, UPDATE_PVID_PVID
);
1720 /* if glort is not valid return error */
1721 if (!fm10k_glort_valid_pf(hw
, glort
))
1722 return FM10K_ERR_PARAM
;
1724 /* verify VLAN ID is valid */
1725 if (pvid
>= FM10K_VLAN_TABLE_VID_MAX
)
1726 return FM10K_ERR_PARAM
;
1728 /* record the port VLAN ID value */
1729 hw
->mac
.default_vid
= pvid
;
1735 * fm10k_record_global_table_data - Move global table data to swapi table info
1736 * @from: pointer to source table data structure
1737 * @to: pointer to destination table info structure
1739 * This function is will copy table_data to the table_info contained in
1742 static void fm10k_record_global_table_data(struct fm10k_global_table_data
*from
,
1743 struct fm10k_swapi_table_info
*to
)
1745 /* convert from le32 struct to CPU byte ordered values */
1746 to
->used
= le32_to_cpu(from
->used
);
1747 to
->avail
= le32_to_cpu(from
->avail
);
1750 const struct fm10k_tlv_attr fm10k_err_msg_attr
[] = {
1751 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR
,
1752 sizeof(struct fm10k_swapi_error
)),
1757 * fm10k_msg_err_pf - Message handler for error reply
1758 * @hw: Pointer to hardware structure
1759 * @results: pointer array containing parsed data
1760 * @mbx: Pointer to mailbox information structure
1762 * This handler will capture the data for any error replies to previous
1763 * messages that the PF has sent.
1765 s32
fm10k_msg_err_pf(struct fm10k_hw
*hw
, u32
**results
,
1766 struct fm10k_mbx_info
*mbx
)
1768 struct fm10k_swapi_error err_msg
;
1771 /* extract structure from message */
1772 err
= fm10k_tlv_attr_get_le_struct(results
[FM10K_PF_ATTR_ID_ERR
],
1773 &err_msg
, sizeof(err_msg
));
1777 /* record table status */
1778 fm10k_record_global_table_data(&err_msg
.mac
, &hw
->swapi
.mac
);
1779 fm10k_record_global_table_data(&err_msg
.nexthop
, &hw
->swapi
.nexthop
);
1780 fm10k_record_global_table_data(&err_msg
.ffu
, &hw
->swapi
.ffu
);
1782 /* record SW API status value */
1783 hw
->swapi
.status
= le32_to_cpu(err_msg
.status
);
1788 static const struct fm10k_msg_data fm10k_msg_data_pf
[] = {
1789 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES
, fm10k_msg_err_pf
),
1790 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE
, fm10k_msg_err_pf
),
1791 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf
),
1792 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE
, fm10k_msg_err_pf
),
1793 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE
, fm10k_msg_err_pf
),
1794 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf
),
1795 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error
),
1798 static const struct fm10k_mac_ops mac_ops_pf
= {
1799 .get_bus_info
= fm10k_get_bus_info_generic
,
1800 .reset_hw
= fm10k_reset_hw_pf
,
1801 .init_hw
= fm10k_init_hw_pf
,
1802 .start_hw
= fm10k_start_hw_generic
,
1803 .stop_hw
= fm10k_stop_hw_generic
,
1804 .update_vlan
= fm10k_update_vlan_pf
,
1805 .read_mac_addr
= fm10k_read_mac_addr_pf
,
1806 .update_uc_addr
= fm10k_update_uc_addr_pf
,
1807 .update_mc_addr
= fm10k_update_mc_addr_pf
,
1808 .update_xcast_mode
= fm10k_update_xcast_mode_pf
,
1809 .update_int_moderator
= fm10k_update_int_moderator_pf
,
1810 .update_lport_state
= fm10k_update_lport_state_pf
,
1811 .update_hw_stats
= fm10k_update_hw_stats_pf
,
1812 .rebind_hw_stats
= fm10k_rebind_hw_stats_pf
,
1813 .configure_dglort_map
= fm10k_configure_dglort_map_pf
,
1814 .set_dma_mask
= fm10k_set_dma_mask_pf
,
1815 .get_fault
= fm10k_get_fault_pf
,
1816 .get_host_state
= fm10k_get_host_state_pf
,
1817 .request_lport_map
= fm10k_request_lport_map_pf
,
1820 static const struct fm10k_iov_ops iov_ops_pf
= {
1821 .assign_resources
= fm10k_iov_assign_resources_pf
,
1822 .configure_tc
= fm10k_iov_configure_tc_pf
,
1823 .assign_int_moderator
= fm10k_iov_assign_int_moderator_pf
,
1824 .assign_default_mac_vlan
= fm10k_iov_assign_default_mac_vlan_pf
,
1825 .reset_resources
= fm10k_iov_reset_resources_pf
,
1826 .set_lport
= fm10k_iov_set_lport_pf
,
1827 .reset_lport
= fm10k_iov_reset_lport_pf
,
1828 .update_stats
= fm10k_iov_update_stats_pf
,
1831 static s32
fm10k_get_invariants_pf(struct fm10k_hw
*hw
)
1833 fm10k_get_invariants_generic(hw
);
1835 return fm10k_sm_mbx_init(hw
, &hw
->mbx
, fm10k_msg_data_pf
);
1838 const struct fm10k_info fm10k_pf_info
= {
1839 .mac
= fm10k_mac_pf
,
1840 .get_invariants
= fm10k_get_invariants_pf
,
1841 .mac_ops
= &mac_ops_pf
,
1842 .iov_ops
= &iov_ops_pf
,