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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / intel / i40e / i40e.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2017 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_H_
28 #define _I40E_H_
29
30 #include <net/tcp.h>
31 #include <net/udp.h>
32 #include <linux/types.h>
33 #include <linux/errno.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/aer.h>
37 #include <linux/netdevice.h>
38 #include <linux/ioport.h>
39 #include <linux/iommu.h>
40 #include <linux/slab.h>
41 #include <linux/list.h>
42 #include <linux/hashtable.h>
43 #include <linux/string.h>
44 #include <linux/in.h>
45 #include <linux/ip.h>
46 #include <linux/sctp.h>
47 #include <linux/pkt_sched.h>
48 #include <linux/ipv6.h>
49 #include <net/checksum.h>
50 #include <net/ip6_checksum.h>
51 #include <linux/ethtool.h>
52 #include <linux/if_vlan.h>
53 #include <linux/if_bridge.h>
54 #include <linux/clocksource.h>
55 #include <linux/net_tstamp.h>
56 #include <linux/ptp_clock_kernel.h>
57 #include "i40e_type.h"
58 #include "i40e_prototype.h"
59 #include "i40e_client.h"
60 #include <linux/avf/virtchnl.h>
61 #include "i40e_virtchnl_pf.h"
62 #include "i40e_txrx.h"
63 #include "i40e_dcb.h"
64
65 /* Useful i40e defaults */
66 #define I40E_MAX_VEB 16
67
68 #define I40E_MAX_NUM_DESCRIPTORS 4096
69 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
70 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
71 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
72 #define I40E_MIN_NUM_DESCRIPTORS 64
73 #define I40E_MIN_MSIX 2
74 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
75 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
76 /* max 16 qps */
77 #define i40e_default_queues_per_vmdq(pf) \
78 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
79 #define I40E_DEFAULT_QUEUES_PER_VF 4
80 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
81 #define i40e_pf_get_max_q_per_tc(pf) \
82 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
83 #define I40E_FDIR_RING 0
84 #define I40E_FDIR_RING_COUNT 32
85 #define I40E_MAX_AQ_BUF_SIZE 4096
86 #define I40E_AQ_LEN 256
87 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
88 #define I40E_MAX_USER_PRIORITY 8
89 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
90 #define I40E_DEFAULT_MSG_ENABLE 4
91 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
92 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
93
94 #define I40E_NVM_VERSION_LO_SHIFT 0
95 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
96 #define I40E_NVM_VERSION_HI_SHIFT 12
97 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
98 #define I40E_OEM_VER_BUILD_MASK 0xffff
99 #define I40E_OEM_VER_PATCH_MASK 0xff
100 #define I40E_OEM_VER_BUILD_SHIFT 8
101 #define I40E_OEM_VER_SHIFT 24
102 #define I40E_PHY_DEBUG_ALL \
103 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
104 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
105
106 #define I40E_OEM_EETRACK_ID 0xffffffff
107 #define I40E_OEM_GEN_SHIFT 24
108 #define I40E_OEM_SNAP_MASK 0x00ff0000
109 #define I40E_OEM_SNAP_SHIFT 16
110 #define I40E_OEM_RELEASE_MASK 0x0000ffff
111
112 /* The values in here are decimal coded as hex as is the case in the NVM map*/
113 #define I40E_CURRENT_NVM_VERSION_HI 0x2
114 #define I40E_CURRENT_NVM_VERSION_LO 0x40
115
116 #define I40E_RX_DESC(R, i) \
117 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
118 #define I40E_TX_DESC(R, i) \
119 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
120 #define I40E_TX_CTXTDESC(R, i) \
121 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
122 #define I40E_TX_FDIRDESC(R, i) \
123 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
124
125 /* default to trying for four seconds */
126 #define I40E_TRY_LINK_TIMEOUT (4 * HZ)
127
128 /* driver state flags */
129 enum i40e_state_t {
130 __I40E_TESTING,
131 __I40E_CONFIG_BUSY,
132 __I40E_CONFIG_DONE,
133 __I40E_DOWN,
134 __I40E_SERVICE_SCHED,
135 __I40E_ADMINQ_EVENT_PENDING,
136 __I40E_MDD_EVENT_PENDING,
137 __I40E_VFLR_EVENT_PENDING,
138 __I40E_RESET_RECOVERY_PENDING,
139 __I40E_RESET_INTR_RECEIVED,
140 __I40E_REINIT_REQUESTED,
141 __I40E_PF_RESET_REQUESTED,
142 __I40E_CORE_RESET_REQUESTED,
143 __I40E_GLOBAL_RESET_REQUESTED,
144 __I40E_EMP_RESET_REQUESTED,
145 __I40E_EMP_RESET_INTR_RECEIVED,
146 __I40E_SUSPENDED,
147 __I40E_PTP_TX_IN_PROGRESS,
148 __I40E_BAD_EEPROM,
149 __I40E_DOWN_REQUESTED,
150 __I40E_FD_FLUSH_REQUESTED,
151 __I40E_RESET_FAILED,
152 __I40E_PORT_SUSPENDED,
153 __I40E_VF_DISABLE,
154 /* This must be last as it determines the size of the BITMAP */
155 __I40E_STATE_SIZE__,
156 };
157
158 /* VSI state flags */
159 enum i40e_vsi_state_t {
160 __I40E_VSI_DOWN,
161 __I40E_VSI_NEEDS_RESTART,
162 __I40E_VSI_SYNCING_FILTERS,
163 __I40E_VSI_OVERFLOW_PROMISC,
164 __I40E_VSI_REINIT_REQUESTED,
165 __I40E_VSI_DOWN_REQUESTED,
166 /* This must be last as it determines the size of the BITMAP */
167 __I40E_VSI_STATE_SIZE__,
168 };
169
170 enum i40e_interrupt_policy {
171 I40E_INTERRUPT_BEST_CASE,
172 I40E_INTERRUPT_MEDIUM,
173 I40E_INTERRUPT_LOWEST
174 };
175
176 struct i40e_lump_tracking {
177 u16 num_entries;
178 u16 search_hint;
179 u16 list[0];
180 #define I40E_PILE_VALID_BIT 0x8000
181 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
182 };
183
184 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
185 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
186 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
187 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
188 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
189
190 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
191 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
192 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
193
194 enum i40e_fd_stat_idx {
195 I40E_FD_STAT_ATR,
196 I40E_FD_STAT_SB,
197 I40E_FD_STAT_ATR_TUNNEL,
198 I40E_FD_STAT_PF_COUNT
199 };
200 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
201 #define I40E_FD_ATR_STAT_IDX(pf_id) \
202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
203 #define I40E_FD_SB_STAT_IDX(pf_id) \
204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
205 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
206 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
207
208 /* The following structure contains the data parsed from the user-defined
209 * field of the ethtool_rx_flow_spec structure.
210 */
211 struct i40e_rx_flow_userdef {
212 bool flex_filter;
213 u16 flex_word;
214 u16 flex_offset;
215 };
216
217 struct i40e_fdir_filter {
218 struct hlist_node fdir_node;
219 /* filter ipnut set */
220 u8 flow_type;
221 u8 ip4_proto;
222 /* TX packet view of src and dst */
223 __be32 dst_ip;
224 __be32 src_ip;
225 __be16 src_port;
226 __be16 dst_port;
227 __be32 sctp_v_tag;
228
229 /* Flexible data to match within the packet payload */
230 __be16 flex_word;
231 u16 flex_offset;
232 bool flex_filter;
233
234 /* filter control */
235 u16 q_index;
236 u8 flex_off;
237 u8 pctype;
238 u16 dest_vsi;
239 u8 dest_ctl;
240 u8 fd_status;
241 u16 cnt_index;
242 u32 fd_id;
243 };
244
245 #define I40E_ETH_P_LLDP 0x88cc
246
247 #define I40E_DCB_PRIO_TYPE_STRICT 0
248 #define I40E_DCB_PRIO_TYPE_ETS 1
249 #define I40E_DCB_STRICT_PRIO_CREDITS 127
250 /* DCB per TC information data structure */
251 struct i40e_tc_info {
252 u16 qoffset; /* Queue offset from base queue */
253 u16 qcount; /* Total Queues */
254 u8 netdev_tc; /* Netdev TC index if netdev associated */
255 };
256
257 /* TC configuration data structure */
258 struct i40e_tc_configuration {
259 u8 numtc; /* Total number of enabled TCs */
260 u8 enabled_tc; /* TC map */
261 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
262 };
263
264 struct i40e_udp_port_config {
265 /* AdminQ command interface expects port number in Host byte order */
266 u16 port;
267 u8 type;
268 };
269
270 /* macros related to FLX_PIT */
271 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
272 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
273 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
274 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
275 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
276 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
277 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
278 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
279 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
280 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
281 I40E_FLEX_SET_FSIZE(fsize) | \
282 I40E_FLEX_SET_SRC_WORD(src))
283
284 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
285 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
286 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
287 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
288 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
289 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
290 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
291 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
292 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
293
294 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
295
296 /* macros related to GLQF_ORT */
297 #define I40E_ORT_SET_IDX(idx) (((idx) << \
298 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
299 I40E_GLQF_ORT_PIT_INDX_MASK)
300
301 #define I40E_ORT_SET_COUNT(count) (((count) << \
302 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
303 I40E_GLQF_ORT_FIELD_CNT_MASK)
304
305 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
306 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
307 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
308
309 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
310 I40E_ORT_SET_COUNT(count) | \
311 I40E_ORT_SET_PAYLOAD(payload))
312
313 #define I40E_L3_GLQF_ORT_IDX 34
314 #define I40E_L4_GLQF_ORT_IDX 35
315
316 /* Flex PIT register index */
317 #define I40E_FLEX_PIT_IDX_START_L2 0
318 #define I40E_FLEX_PIT_IDX_START_L3 3
319 #define I40E_FLEX_PIT_IDX_START_L4 6
320
321 #define I40E_FLEX_PIT_TABLE_SIZE 3
322
323 #define I40E_FLEX_DEST_UNUSED 63
324
325 #define I40E_FLEX_INDEX_ENTRIES 8
326
327 /* Flex MASK to disable all flexible entries */
328 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
329 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
330 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
331 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
332
333 struct i40e_flex_pit {
334 struct list_head list;
335 u16 src_offset;
336 u8 pit_index;
337 };
338
339 /* struct that defines the Ethernet device */
340 struct i40e_pf {
341 struct pci_dev *pdev;
342 struct i40e_hw hw;
343 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
344 struct msix_entry *msix_entries;
345 bool fc_autoneg_status;
346
347 u16 eeprom_version;
348 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
349 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
350 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
351 u16 num_req_vfs; /* num VFs requested for this VF */
352 u16 num_vf_qps; /* num queue pairs per VF */
353 u16 num_lan_qps; /* num lan queues this PF has set up */
354 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
355 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
356 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
357 int iwarp_base_vector;
358 int queues_left; /* queues left unclaimed */
359 u16 alloc_rss_size; /* allocated RSS queues */
360 u16 rss_size_max; /* HW defined max RSS queues */
361 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
362 u16 num_alloc_vsi; /* num VSIs this driver supports */
363 u8 atr_sample_rate;
364 bool wol_en;
365
366 struct hlist_head fdir_filter_list;
367 u16 fdir_pf_active_filters;
368 unsigned long fd_flush_timestamp;
369 u32 fd_flush_cnt;
370 u32 fd_add_err;
371 u32 fd_atr_cnt;
372
373 /* Book-keeping of side-band filter count per flow-type.
374 * This is used to detect and handle input set changes for
375 * respective flow-type.
376 */
377 u16 fd_tcp4_filter_cnt;
378 u16 fd_udp4_filter_cnt;
379 u16 fd_sctp4_filter_cnt;
380 u16 fd_ip4_filter_cnt;
381
382 /* Flexible filter table values that need to be programmed into
383 * hardware, which expects L3 and L4 to be programmed separately. We
384 * need to ensure that the values are in ascended order and don't have
385 * duplicates, so we track each L3 and L4 values in separate lists.
386 */
387 struct list_head l3_flex_pit_list;
388 struct list_head l4_flex_pit_list;
389
390 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
391 u16 pending_udp_bitmap;
392
393 enum i40e_interrupt_policy int_policy;
394 u16 rx_itr_default;
395 u16 tx_itr_default;
396 u32 msg_enable;
397 char int_name[I40E_INT_NAME_STR_LEN];
398 u16 adminq_work_limit; /* num of admin receive queue desc to process */
399 unsigned long service_timer_period;
400 unsigned long service_timer_previous;
401 struct timer_list service_timer;
402 struct work_struct service_task;
403
404 u64 hw_features;
405 #define I40E_HW_RSS_AQ_CAPABLE BIT_ULL(0)
406 #define I40E_HW_128_QP_RSS_CAPABLE BIT_ULL(1)
407 #define I40E_HW_ATR_EVICT_CAPABLE BIT_ULL(2)
408 #define I40E_HW_WB_ON_ITR_CAPABLE BIT_ULL(3)
409 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(4)
410 #define I40E_HW_NO_PCI_LINK_CHECK BIT_ULL(5)
411 #define I40E_HW_100M_SGMII_CAPABLE BIT_ULL(6)
412 #define I40E_HW_NO_DCB_SUPPORT BIT_ULL(7)
413 #define I40E_HW_USE_SET_LLDP_MIB BIT_ULL(8)
414 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT_ULL(9)
415 #define I40E_HW_PTP_L4_CAPABLE BIT_ULL(10)
416 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT_ULL(11)
417 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT_ULL(12)
418 #define I40E_HW_HAVE_CRT_RETIMER BIT_ULL(13)
419 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT_ULL(14)
420 #define I40E_HW_PHY_CONTROLS_LEDS BIT_ULL(15)
421 #define I40E_HW_STOP_FW_LLDP BIT_ULL(16)
422 #define I40E_HW_PORT_ID_VALID BIT_ULL(17)
423 #define I40E_HW_RESTART_AUTONEG BIT_ULL(18)
424
425 u64 flags;
426 #define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
427 #define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
428 #define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
429 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT_ULL(4)
430 #define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
431 #define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
432 #define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
433 #define I40E_FLAG_FILTER_SYNC BIT_ULL(15)
434 #define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT_ULL(16)
435 #define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19)
436 #define I40E_FLAG_DCB_ENABLED BIT_ULL(20)
437 #define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21)
438 #define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22)
439 #define I40E_FLAG_FD_SB_AUTO_DISABLED BIT_ULL(23)
440 #define I40E_FLAG_FD_ATR_AUTO_DISABLED BIT_ULL(24)
441 #define I40E_FLAG_PTP BIT_ULL(25)
442 #define I40E_FLAG_MFP_ENABLED BIT_ULL(26)
443 #define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27)
444 #define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
445 #define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37)
446 #define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39)
447 #define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
448 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT_ULL(51)
449 #define I40E_FLAG_CLIENT_RESET BIT_ULL(54)
450 #define I40E_FLAG_TEMP_LINK_POLLING BIT_ULL(55)
451 #define I40E_FLAG_CLIENT_L2_CHANGE BIT_ULL(56)
452 #define I40E_FLAG_LEGACY_RX BIT_ULL(58)
453
454 struct i40e_client_instance *cinst;
455 bool stat_offsets_loaded;
456 struct i40e_hw_port_stats stats;
457 struct i40e_hw_port_stats stats_offsets;
458 u32 tx_timeout_count;
459 u32 tx_timeout_recovery_level;
460 unsigned long tx_timeout_last_recovery;
461 u32 tx_sluggish_count;
462 u32 hw_csum_rx_error;
463 u32 led_status;
464 u16 corer_count; /* Core reset count */
465 u16 globr_count; /* Global reset count */
466 u16 empr_count; /* EMP reset count */
467 u16 pfr_count; /* PF reset count */
468 u16 sw_int_count; /* SW interrupt count */
469
470 struct mutex switch_mutex;
471 u16 lan_vsi; /* our default LAN VSI */
472 u16 lan_veb; /* initial relay, if exists */
473 #define I40E_NO_VEB 0xffff
474 #define I40E_NO_VSI 0xffff
475 u16 next_vsi; /* Next unallocated VSI - 0-based! */
476 struct i40e_vsi **vsi;
477 struct i40e_veb *veb[I40E_MAX_VEB];
478
479 struct i40e_lump_tracking *qp_pile;
480 struct i40e_lump_tracking *irq_pile;
481
482 /* switch config info */
483 u16 pf_seid;
484 u16 main_vsi_seid;
485 u16 mac_seid;
486 struct kobject *switch_kobj;
487 #ifdef CONFIG_DEBUG_FS
488 struct dentry *i40e_dbg_pf;
489 #endif /* CONFIG_DEBUG_FS */
490 bool cur_promisc;
491
492 u16 instance; /* A unique number per i40e_pf instance in the system */
493
494 /* sr-iov config info */
495 struct i40e_vf *vf;
496 int num_alloc_vfs; /* actual number of VFs allocated */
497 u32 vf_aq_requests;
498 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
499
500 /* DCBx/DCBNL capability for PF that indicates
501 * whether DCBx is managed by firmware or host
502 * based agent (LLDPAD). Also, indicates what
503 * flavor of DCBx protocol (IEEE/CEE) is supported
504 * by the device. For now we're supporting IEEE
505 * mode only.
506 */
507 u16 dcbx_cap;
508
509 struct i40e_filter_control_settings filter_settings;
510
511 struct ptp_clock *ptp_clock;
512 struct ptp_clock_info ptp_caps;
513 struct sk_buff *ptp_tx_skb;
514 unsigned long ptp_tx_start;
515 struct hwtstamp_config tstamp_config;
516 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
517 u64 ptp_base_adj;
518 u32 tx_hwtstamp_timeouts;
519 u32 tx_hwtstamp_skipped;
520 u32 rx_hwtstamp_cleared;
521 u32 latch_event_flags;
522 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
523 unsigned long latch_events[4];
524 bool ptp_tx;
525 bool ptp_rx;
526 u16 rss_table_size; /* HW RSS table size */
527 u32 max_bw;
528 u32 min_bw;
529
530 u32 ioremap_len;
531 u32 fd_inv;
532 u16 phy_led_val;
533 };
534
535 /**
536 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
537 * @macaddr: the MAC Address as the base key
538 *
539 * Simply copies the address and returns it as a u64 for hashing
540 **/
541 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
542 {
543 u64 key = 0;
544
545 ether_addr_copy((u8 *)&key, macaddr);
546 return key;
547 }
548
549 enum i40e_filter_state {
550 I40E_FILTER_INVALID = 0, /* Invalid state */
551 I40E_FILTER_NEW, /* New, not sent to FW yet */
552 I40E_FILTER_ACTIVE, /* Added to switch by FW */
553 I40E_FILTER_FAILED, /* Rejected by FW */
554 I40E_FILTER_REMOVE, /* To be removed */
555 /* There is no 'removed' state; the filter struct is freed */
556 };
557 struct i40e_mac_filter {
558 struct hlist_node hlist;
559 u8 macaddr[ETH_ALEN];
560 #define I40E_VLAN_ANY -1
561 s16 vlan;
562 enum i40e_filter_state state;
563 };
564
565 /* Wrapper structure to keep track of filters while we are preparing to send
566 * firmware commands. We cannot send firmware commands while holding a
567 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
568 * a separate structure, which will track the state change and update the real
569 * filter while under lock. We can't simply hold the filters in a separate
570 * list, as this opens a window for a race condition when adding new MAC
571 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
572 */
573 struct i40e_new_mac_filter {
574 struct hlist_node hlist;
575 struct i40e_mac_filter *f;
576
577 /* Track future changes to state separately */
578 enum i40e_filter_state state;
579 };
580
581 struct i40e_veb {
582 struct i40e_pf *pf;
583 u16 idx;
584 u16 veb_idx; /* index of VEB parent */
585 u16 seid;
586 u16 uplink_seid;
587 u16 stats_idx; /* index of VEB parent */
588 u8 enabled_tc;
589 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
590 u16 flags;
591 u16 bw_limit;
592 u8 bw_max_quanta;
593 bool is_abs_credits;
594 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
595 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
596 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
597 struct kobject *kobj;
598 bool stat_offsets_loaded;
599 struct i40e_eth_stats stats;
600 struct i40e_eth_stats stats_offsets;
601 struct i40e_veb_tc_stats tc_stats;
602 struct i40e_veb_tc_stats tc_stats_offsets;
603 };
604
605 /* struct that defines a VSI, associated with a dev */
606 struct i40e_vsi {
607 struct net_device *netdev;
608 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
609 bool netdev_registered;
610 bool stat_offsets_loaded;
611
612 u32 current_netdev_flags;
613 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
614 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
615 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
616 unsigned long flags;
617
618 /* Per VSI lock to protect elements/hash (MAC filter) */
619 spinlock_t mac_filter_hash_lock;
620 /* Fixed size hash table with 2^8 buckets for MAC filters */
621 DECLARE_HASHTABLE(mac_filter_hash, 8);
622 bool has_vlan_filter;
623
624 /* VSI stats */
625 struct rtnl_link_stats64 net_stats;
626 struct rtnl_link_stats64 net_stats_offsets;
627 struct i40e_eth_stats eth_stats;
628 struct i40e_eth_stats eth_stats_offsets;
629 u32 tx_restart;
630 u32 tx_busy;
631 u64 tx_linearize;
632 u64 tx_force_wb;
633 u32 rx_buf_failed;
634 u32 rx_page_failed;
635
636 /* These are containers of ring pointers, allocated at run-time */
637 struct i40e_ring **rx_rings;
638 struct i40e_ring **tx_rings;
639 struct i40e_ring **xdp_rings; /* XDP Tx rings */
640
641 u32 active_filters;
642 u32 promisc_threshold;
643
644 u16 work_limit;
645 u16 int_rate_limit; /* value in usecs */
646
647 u16 rss_table_size; /* HW RSS table size */
648 u16 rss_size; /* Allocated RSS queues */
649 u8 *rss_hkey_user; /* User configured hash keys */
650 u8 *rss_lut_user; /* User configured lookup table entries */
651
652
653 u16 max_frame;
654 u16 rx_buf_len;
655
656 struct bpf_prog *xdp_prog;
657
658 /* List of q_vectors allocated to this VSI */
659 struct i40e_q_vector **q_vectors;
660 int num_q_vectors;
661 int base_vector;
662 bool irqs_ready;
663
664 u16 seid; /* HW index of this VSI (absolute index) */
665 u16 id; /* VSI number */
666 u16 uplink_seid;
667
668 u16 base_queue; /* vsi's first queue in hw array */
669 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
670 u16 req_queue_pairs; /* User requested queue pairs */
671 u16 num_queue_pairs; /* Used tx and rx pairs */
672 u16 num_desc;
673 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
674 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
675
676 struct i40e_tc_configuration tc_config;
677 struct i40e_aqc_vsi_properties_data info;
678
679 /* VSI BW limit (absolute across all TCs) */
680 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
681 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
682
683 /* Relative TC credits across VSIs */
684 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
685 /* TC BW limit credits within VSI */
686 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
687 /* TC BW limit max quanta within VSI */
688 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
689
690 struct i40e_pf *back; /* Backreference to associated PF */
691 u16 idx; /* index in pf->vsi[] */
692 u16 veb_idx; /* index of VEB parent */
693 struct kobject *kobj; /* sysfs object */
694 bool current_isup; /* Sync 'link up' logging */
695 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
696
697 void *priv; /* client driver data reference. */
698
699 /* VSI specific handlers */
700 irqreturn_t (*irq_handler)(int irq, void *data);
701 } ____cacheline_internodealigned_in_smp;
702
703 struct i40e_netdev_priv {
704 struct i40e_vsi *vsi;
705 };
706
707 /* struct that defines an interrupt vector */
708 struct i40e_q_vector {
709 struct i40e_vsi *vsi;
710
711 u16 v_idx; /* index in the vsi->q_vector array. */
712 u16 reg_idx; /* register index of the interrupt */
713
714 struct napi_struct napi;
715
716 struct i40e_ring_container rx;
717 struct i40e_ring_container tx;
718
719 u8 num_ringpairs; /* total number of ring pairs in vector */
720
721 cpumask_t affinity_mask;
722 struct irq_affinity_notify affinity_notify;
723
724 struct rcu_head rcu; /* to avoid race with update stats on free */
725 char name[I40E_INT_NAME_STR_LEN];
726 bool arm_wb_state;
727 #define ITR_COUNTDOWN_START 100
728 u8 itr_countdown; /* when 0 should adjust ITR */
729 } ____cacheline_internodealigned_in_smp;
730
731 /* lan device */
732 struct i40e_device {
733 struct list_head list;
734 struct i40e_pf *pf;
735 };
736
737 /**
738 * i40e_nvm_version_str - format the NVM version strings
739 * @hw: ptr to the hardware info
740 **/
741 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
742 {
743 static char buf[32];
744 u32 full_ver;
745
746 full_ver = hw->nvm.oem_ver;
747
748 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
749 u8 gen, snap;
750 u16 release;
751
752 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
753 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
754 I40E_OEM_SNAP_SHIFT);
755 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
756
757 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
758 } else {
759 u8 ver, patch;
760 u16 build;
761
762 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
763 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
764 I40E_OEM_VER_BUILD_MASK);
765 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
766
767 snprintf(buf, sizeof(buf),
768 "%x.%02x 0x%x %d.%d.%d",
769 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
770 I40E_NVM_VERSION_HI_SHIFT,
771 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
772 I40E_NVM_VERSION_LO_SHIFT,
773 hw->nvm.eetrack, ver, build, patch);
774 }
775
776 return buf;
777 }
778
779 /**
780 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
781 * @netdev: the corresponding netdev
782 *
783 * Return the PF struct for the given netdev
784 **/
785 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
786 {
787 struct i40e_netdev_priv *np = netdev_priv(netdev);
788 struct i40e_vsi *vsi = np->vsi;
789
790 return vsi->back;
791 }
792
793 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
794 irqreturn_t (*irq_handler)(int, void *))
795 {
796 vsi->irq_handler = irq_handler;
797 }
798
799 /**
800 * i40e_get_fd_cnt_all - get the total FD filter space available
801 * @pf: pointer to the PF struct
802 **/
803 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
804 {
805 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
806 }
807
808 /**
809 * i40e_read_fd_input_set - reads value of flow director input set register
810 * @pf: pointer to the PF struct
811 * @addr: register addr
812 *
813 * This function reads value of flow director input set register
814 * specified by 'addr' (which is specific to flow-type)
815 **/
816 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
817 {
818 u64 val;
819
820 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
821 val <<= 32;
822 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
823
824 return val;
825 }
826
827 /**
828 * i40e_write_fd_input_set - writes value into flow director input set register
829 * @pf: pointer to the PF struct
830 * @addr: register addr
831 * @val: value to be written
832 *
833 * This function writes specified value to the register specified by 'addr'.
834 * This register is input set register based on flow-type.
835 **/
836 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
837 u16 addr, u64 val)
838 {
839 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
840 (u32)(val >> 32));
841 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
842 (u32)(val & 0xFFFFFFFFULL));
843 }
844
845 /* needed by i40e_ethtool.c */
846 int i40e_up(struct i40e_vsi *vsi);
847 void i40e_down(struct i40e_vsi *vsi);
848 extern const char i40e_driver_name[];
849 extern const char i40e_driver_version_str[];
850 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
851 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
852 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
853 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
854 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
855 u16 rss_table_size, u16 rss_size);
856 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
857 /**
858 * i40e_find_vsi_by_type - Find and return Flow Director VSI
859 * @pf: PF to search for VSI
860 * @type: Value indicating type of VSI we are looking for
861 **/
862 static inline struct i40e_vsi *
863 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
864 {
865 int i;
866
867 for (i = 0; i < pf->num_alloc_vsi; i++) {
868 struct i40e_vsi *vsi = pf->vsi[i];
869
870 if (vsi && vsi->type == type)
871 return vsi;
872 }
873
874 return NULL;
875 }
876 void i40e_update_stats(struct i40e_vsi *vsi);
877 void i40e_update_eth_stats(struct i40e_vsi *vsi);
878 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
879 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
880 bool printconfig);
881
882 int i40e_add_del_fdir(struct i40e_vsi *vsi,
883 struct i40e_fdir_filter *input, bool add);
884 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
885 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
886 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
887 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
888 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
889 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
890 void i40e_set_ethtool_ops(struct net_device *netdev);
891 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
892 const u8 *macaddr, s16 vlan);
893 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
894 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
895 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
896 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
897 u16 uplink, u32 param1);
898 int i40e_vsi_release(struct i40e_vsi *vsi);
899 void i40e_service_event_schedule(struct i40e_pf *pf);
900 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
901 u8 *msg, u16 len);
902
903 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
904 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
905 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
906 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
907 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
908 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
909 u16 downlink_seid, u8 enabled_tc);
910 void i40e_veb_release(struct i40e_veb *veb);
911
912 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
913 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
914 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
915 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
916 void i40e_pf_reset_stats(struct i40e_pf *pf);
917 #ifdef CONFIG_DEBUG_FS
918 void i40e_dbg_pf_init(struct i40e_pf *pf);
919 void i40e_dbg_pf_exit(struct i40e_pf *pf);
920 void i40e_dbg_init(void);
921 void i40e_dbg_exit(void);
922 #else
923 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
924 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
925 static inline void i40e_dbg_init(void) {}
926 static inline void i40e_dbg_exit(void) {}
927 #endif /* CONFIG_DEBUG_FS*/
928 /* needed by client drivers */
929 int i40e_lan_add_device(struct i40e_pf *pf);
930 int i40e_lan_del_device(struct i40e_pf *pf);
931 void i40e_client_subtask(struct i40e_pf *pf);
932 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
933 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
934 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
935 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
936 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
937 /**
938 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
939 * @vsi: pointer to a vsi
940 * @vector: enable a particular Hw Interrupt vector, without base_vector
941 **/
942 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
943 {
944 struct i40e_pf *pf = vsi->back;
945 struct i40e_hw *hw = &pf->hw;
946 u32 val;
947
948 /* definitely clear the PBA here, as this function is meant to
949 * clean out all previous interrupts AND enable the interrupt
950 */
951 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
952 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
953 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
954 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
955 /* skip the flush */
956 }
957
958 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
959 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba);
960 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
961 int i40e_open(struct net_device *netdev);
962 int i40e_close(struct net_device *netdev);
963 int i40e_vsi_open(struct i40e_vsi *vsi);
964 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
965 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
966 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
967 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
968 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
969 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
970 const u8 *macaddr);
971 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
972 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
973 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
974 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
975 #ifdef CONFIG_I40E_DCB
976 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
977 struct i40e_dcbx_config *old_cfg,
978 struct i40e_dcbx_config *new_cfg);
979 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
980 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
981 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
982 struct i40e_dcbx_config *old_cfg,
983 struct i40e_dcbx_config *new_cfg);
984 #endif /* CONFIG_I40E_DCB */
985 void i40e_ptp_rx_hang(struct i40e_pf *pf);
986 void i40e_ptp_tx_hang(struct i40e_pf *pf);
987 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
988 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
989 void i40e_ptp_set_increment(struct i40e_pf *pf);
990 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
991 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
992 void i40e_ptp_init(struct i40e_pf *pf);
993 void i40e_ptp_stop(struct i40e_pf *pf);
994 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
995 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
996 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
997 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
998 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
999
1000 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1001 {
1002 return !!vsi->xdp_prog;
1003 }
1004 #endif /* _I40E_H_ */
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