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Merge tag 'pm-fixes-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / intel / i40e / i40e.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2017 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_H_
28 #define _I40E_H_
29
30 #include <net/tcp.h>
31 #include <net/udp.h>
32 #include <linux/types.h>
33 #include <linux/errno.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/aer.h>
37 #include <linux/netdevice.h>
38 #include <linux/ioport.h>
39 #include <linux/iommu.h>
40 #include <linux/slab.h>
41 #include <linux/list.h>
42 #include <linux/hashtable.h>
43 #include <linux/string.h>
44 #include <linux/in.h>
45 #include <linux/ip.h>
46 #include <linux/sctp.h>
47 #include <linux/pkt_sched.h>
48 #include <linux/ipv6.h>
49 #include <net/checksum.h>
50 #include <net/ip6_checksum.h>
51 #include <linux/ethtool.h>
52 #include <linux/if_vlan.h>
53 #include <linux/if_bridge.h>
54 #include <linux/clocksource.h>
55 #include <linux/net_tstamp.h>
56 #include <linux/ptp_clock_kernel.h>
57 #include <net/pkt_cls.h>
58 #include <net/tc_act/tc_gact.h>
59 #include <net/tc_act/tc_mirred.h>
60 #include "i40e_type.h"
61 #include "i40e_prototype.h"
62 #include "i40e_client.h"
63 #include <linux/avf/virtchnl.h>
64 #include "i40e_virtchnl_pf.h"
65 #include "i40e_txrx.h"
66 #include "i40e_dcb.h"
67
68 /* Useful i40e defaults */
69 #define I40E_MAX_VEB 16
70
71 #define I40E_MAX_NUM_DESCRIPTORS 4096
72 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
73 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
74 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
75 #define I40E_MIN_NUM_DESCRIPTORS 64
76 #define I40E_MIN_MSIX 2
77 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
78 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
79 /* max 16 qps */
80 #define i40e_default_queues_per_vmdq(pf) \
81 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
82 #define I40E_DEFAULT_QUEUES_PER_VF 4
83 #define I40E_MAX_VF_QUEUES 16
84 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
85 #define i40e_pf_get_max_q_per_tc(pf) \
86 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
87 #define I40E_FDIR_RING 0
88 #define I40E_FDIR_RING_COUNT 32
89 #define I40E_MAX_AQ_BUF_SIZE 4096
90 #define I40E_AQ_LEN 256
91 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
92 #define I40E_MAX_USER_PRIORITY 8
93 #define I40E_MAX_QUEUES_PER_CH 64
94 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
95 #define I40E_DEFAULT_MSG_ENABLE 4
96 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
97 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
98
99 #define I40E_NVM_VERSION_LO_SHIFT 0
100 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
101 #define I40E_NVM_VERSION_HI_SHIFT 12
102 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
103 #define I40E_OEM_VER_BUILD_MASK 0xffff
104 #define I40E_OEM_VER_PATCH_MASK 0xff
105 #define I40E_OEM_VER_BUILD_SHIFT 8
106 #define I40E_OEM_VER_SHIFT 24
107 #define I40E_PHY_DEBUG_ALL \
108 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
109 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
110
111 #define I40E_OEM_EETRACK_ID 0xffffffff
112 #define I40E_OEM_GEN_SHIFT 24
113 #define I40E_OEM_SNAP_MASK 0x00ff0000
114 #define I40E_OEM_SNAP_SHIFT 16
115 #define I40E_OEM_RELEASE_MASK 0x0000ffff
116
117 /* The values in here are decimal coded as hex as is the case in the NVM map*/
118 #define I40E_CURRENT_NVM_VERSION_HI 0x2
119 #define I40E_CURRENT_NVM_VERSION_LO 0x40
120
121 #define I40E_RX_DESC(R, i) \
122 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
123 #define I40E_TX_DESC(R, i) \
124 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
125 #define I40E_TX_CTXTDESC(R, i) \
126 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
127 #define I40E_TX_FDIRDESC(R, i) \
128 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
129
130 /* default to trying for four seconds */
131 #define I40E_TRY_LINK_TIMEOUT (4 * HZ)
132
133 /* BW rate limiting */
134 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
135 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
136 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
137
138 /* driver state flags */
139 enum i40e_state_t {
140 __I40E_TESTING,
141 __I40E_CONFIG_BUSY,
142 __I40E_CONFIG_DONE,
143 __I40E_DOWN,
144 __I40E_SERVICE_SCHED,
145 __I40E_ADMINQ_EVENT_PENDING,
146 __I40E_MDD_EVENT_PENDING,
147 __I40E_VFLR_EVENT_PENDING,
148 __I40E_RESET_RECOVERY_PENDING,
149 __I40E_MISC_IRQ_REQUESTED,
150 __I40E_RESET_INTR_RECEIVED,
151 __I40E_REINIT_REQUESTED,
152 __I40E_PF_RESET_REQUESTED,
153 __I40E_CORE_RESET_REQUESTED,
154 __I40E_GLOBAL_RESET_REQUESTED,
155 __I40E_EMP_RESET_REQUESTED,
156 __I40E_EMP_RESET_INTR_RECEIVED,
157 __I40E_SUSPENDED,
158 __I40E_PTP_TX_IN_PROGRESS,
159 __I40E_BAD_EEPROM,
160 __I40E_DOWN_REQUESTED,
161 __I40E_FD_FLUSH_REQUESTED,
162 __I40E_RESET_FAILED,
163 __I40E_PORT_SUSPENDED,
164 __I40E_VF_DISABLE,
165 /* This must be last as it determines the size of the BITMAP */
166 __I40E_STATE_SIZE__,
167 };
168
169 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
170
171 /* VSI state flags */
172 enum i40e_vsi_state_t {
173 __I40E_VSI_DOWN,
174 __I40E_VSI_NEEDS_RESTART,
175 __I40E_VSI_SYNCING_FILTERS,
176 __I40E_VSI_OVERFLOW_PROMISC,
177 __I40E_VSI_REINIT_REQUESTED,
178 __I40E_VSI_DOWN_REQUESTED,
179 /* This must be last as it determines the size of the BITMAP */
180 __I40E_VSI_STATE_SIZE__,
181 };
182
183 enum i40e_interrupt_policy {
184 I40E_INTERRUPT_BEST_CASE,
185 I40E_INTERRUPT_MEDIUM,
186 I40E_INTERRUPT_LOWEST
187 };
188
189 struct i40e_lump_tracking {
190 u16 num_entries;
191 u16 search_hint;
192 u16 list[0];
193 #define I40E_PILE_VALID_BIT 0x8000
194 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
195 };
196
197 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
198 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
199 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
200 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
201 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
202
203 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
204 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
205 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
206
207 enum i40e_fd_stat_idx {
208 I40E_FD_STAT_ATR,
209 I40E_FD_STAT_SB,
210 I40E_FD_STAT_ATR_TUNNEL,
211 I40E_FD_STAT_PF_COUNT
212 };
213 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
214 #define I40E_FD_ATR_STAT_IDX(pf_id) \
215 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
216 #define I40E_FD_SB_STAT_IDX(pf_id) \
217 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
218 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
219 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
220
221 /* The following structure contains the data parsed from the user-defined
222 * field of the ethtool_rx_flow_spec structure.
223 */
224 struct i40e_rx_flow_userdef {
225 bool flex_filter;
226 u16 flex_word;
227 u16 flex_offset;
228 };
229
230 struct i40e_fdir_filter {
231 struct hlist_node fdir_node;
232 /* filter ipnut set */
233 u8 flow_type;
234 u8 ip4_proto;
235 /* TX packet view of src and dst */
236 __be32 dst_ip;
237 __be32 src_ip;
238 __be16 src_port;
239 __be16 dst_port;
240 __be32 sctp_v_tag;
241
242 /* Flexible data to match within the packet payload */
243 __be16 flex_word;
244 u16 flex_offset;
245 bool flex_filter;
246
247 /* filter control */
248 u16 q_index;
249 u8 flex_off;
250 u8 pctype;
251 u16 dest_vsi;
252 u8 dest_ctl;
253 u8 fd_status;
254 u16 cnt_index;
255 u32 fd_id;
256 };
257
258 #define I40E_CLOUD_FIELD_OMAC 0x01
259 #define I40E_CLOUD_FIELD_IMAC 0x02
260 #define I40E_CLOUD_FIELD_IVLAN 0x04
261 #define I40E_CLOUD_FIELD_TEN_ID 0x08
262 #define I40E_CLOUD_FIELD_IIP 0x10
263
264 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
265 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
266 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
267 I40E_CLOUD_FIELD_IVLAN)
268 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
269 I40E_CLOUD_FIELD_TEN_ID)
270 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
271 I40E_CLOUD_FIELD_IMAC | \
272 I40E_CLOUD_FIELD_TEN_ID)
273 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
274 I40E_CLOUD_FIELD_IVLAN | \
275 I40E_CLOUD_FIELD_TEN_ID)
276 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
277
278 struct i40e_cloud_filter {
279 struct hlist_node cloud_node;
280 unsigned long cookie;
281 /* cloud filter input set follows */
282 u8 dst_mac[ETH_ALEN];
283 u8 src_mac[ETH_ALEN];
284 __be16 vlan_id;
285 u16 seid; /* filter control */
286 __be16 dst_port;
287 __be16 src_port;
288 u32 tenant_id;
289 union {
290 struct {
291 struct in_addr dst_ip;
292 struct in_addr src_ip;
293 } v4;
294 struct {
295 struct in6_addr dst_ip6;
296 struct in6_addr src_ip6;
297 } v6;
298 } ip;
299 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32
300 #define src_ipv6 ip.v6.src_ip6.s6_addr32
301 #define dst_ipv4 ip.v4.dst_ip.s_addr
302 #define src_ipv4 ip.v4.src_ip.s_addr
303 u16 n_proto; /* Ethernet Protocol */
304 u8 ip_proto; /* IPPROTO value */
305 u8 flags;
306 #define I40E_CLOUD_TNL_TYPE_NONE 0xff
307 u8 tunnel_type;
308 };
309
310 #define I40E_ETH_P_LLDP 0x88cc
311
312 #define I40E_DCB_PRIO_TYPE_STRICT 0
313 #define I40E_DCB_PRIO_TYPE_ETS 1
314 #define I40E_DCB_STRICT_PRIO_CREDITS 127
315 /* DCB per TC information data structure */
316 struct i40e_tc_info {
317 u16 qoffset; /* Queue offset from base queue */
318 u16 qcount; /* Total Queues */
319 u8 netdev_tc; /* Netdev TC index if netdev associated */
320 };
321
322 /* TC configuration data structure */
323 struct i40e_tc_configuration {
324 u8 numtc; /* Total number of enabled TCs */
325 u8 enabled_tc; /* TC map */
326 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
327 };
328
329 struct i40e_udp_port_config {
330 /* AdminQ command interface expects port number in Host byte order */
331 u16 port;
332 u8 type;
333 };
334
335 /* macros related to FLX_PIT */
336 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
337 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
338 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
339 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
340 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
341 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
342 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
343 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
344 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
345 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
346 I40E_FLEX_SET_FSIZE(fsize) | \
347 I40E_FLEX_SET_SRC_WORD(src))
348
349 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
350 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
351 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
352 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
353 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
354 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
355 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
356 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
357 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
358
359 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
360
361 /* macros related to GLQF_ORT */
362 #define I40E_ORT_SET_IDX(idx) (((idx) << \
363 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
364 I40E_GLQF_ORT_PIT_INDX_MASK)
365
366 #define I40E_ORT_SET_COUNT(count) (((count) << \
367 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
368 I40E_GLQF_ORT_FIELD_CNT_MASK)
369
370 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
371 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
372 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
373
374 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
375 I40E_ORT_SET_COUNT(count) | \
376 I40E_ORT_SET_PAYLOAD(payload))
377
378 #define I40E_L3_GLQF_ORT_IDX 34
379 #define I40E_L4_GLQF_ORT_IDX 35
380
381 /* Flex PIT register index */
382 #define I40E_FLEX_PIT_IDX_START_L2 0
383 #define I40E_FLEX_PIT_IDX_START_L3 3
384 #define I40E_FLEX_PIT_IDX_START_L4 6
385
386 #define I40E_FLEX_PIT_TABLE_SIZE 3
387
388 #define I40E_FLEX_DEST_UNUSED 63
389
390 #define I40E_FLEX_INDEX_ENTRIES 8
391
392 /* Flex MASK to disable all flexible entries */
393 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
394 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
395 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
396 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
397
398 struct i40e_flex_pit {
399 struct list_head list;
400 u16 src_offset;
401 u8 pit_index;
402 };
403
404 struct i40e_channel {
405 struct list_head list;
406 bool initialized;
407 u8 type;
408 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
409 u16 stat_counter_idx;
410 u16 base_queue;
411 u16 num_queue_pairs; /* Requested by user */
412 u16 seid;
413
414 u8 enabled_tc;
415 struct i40e_aqc_vsi_properties_data info;
416
417 u64 max_tx_rate;
418
419 /* track this channel belongs to which VSI */
420 struct i40e_vsi *parent_vsi;
421 };
422
423 /* struct that defines the Ethernet device */
424 struct i40e_pf {
425 struct pci_dev *pdev;
426 struct i40e_hw hw;
427 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
428 struct msix_entry *msix_entries;
429 bool fc_autoneg_status;
430
431 u16 eeprom_version;
432 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
433 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
434 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
435 u16 num_req_vfs; /* num VFs requested for this PF */
436 u16 num_vf_qps; /* num queue pairs per VF */
437 u16 num_lan_qps; /* num lan queues this PF has set up */
438 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
439 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
440 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
441 int iwarp_base_vector;
442 int queues_left; /* queues left unclaimed */
443 u16 alloc_rss_size; /* allocated RSS queues */
444 u16 rss_size_max; /* HW defined max RSS queues */
445 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
446 u16 num_alloc_vsi; /* num VSIs this driver supports */
447 u8 atr_sample_rate;
448 bool wol_en;
449
450 struct hlist_head fdir_filter_list;
451 u16 fdir_pf_active_filters;
452 unsigned long fd_flush_timestamp;
453 u32 fd_flush_cnt;
454 u32 fd_add_err;
455 u32 fd_atr_cnt;
456
457 /* Book-keeping of side-band filter count per flow-type.
458 * This is used to detect and handle input set changes for
459 * respective flow-type.
460 */
461 u16 fd_tcp4_filter_cnt;
462 u16 fd_udp4_filter_cnt;
463 u16 fd_sctp4_filter_cnt;
464 u16 fd_ip4_filter_cnt;
465
466 /* Flexible filter table values that need to be programmed into
467 * hardware, which expects L3 and L4 to be programmed separately. We
468 * need to ensure that the values are in ascended order and don't have
469 * duplicates, so we track each L3 and L4 values in separate lists.
470 */
471 struct list_head l3_flex_pit_list;
472 struct list_head l4_flex_pit_list;
473
474 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
475 u16 pending_udp_bitmap;
476
477 struct hlist_head cloud_filter_list;
478 u16 num_cloud_filters;
479
480 enum i40e_interrupt_policy int_policy;
481 u16 rx_itr_default;
482 u16 tx_itr_default;
483 u32 msg_enable;
484 char int_name[I40E_INT_NAME_STR_LEN];
485 u16 adminq_work_limit; /* num of admin receive queue desc to process */
486 unsigned long service_timer_period;
487 unsigned long service_timer_previous;
488 struct timer_list service_timer;
489 struct work_struct service_task;
490
491 u32 hw_features;
492 #define I40E_HW_RSS_AQ_CAPABLE BIT(0)
493 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
494 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
495 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
496 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
497 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
498 #define I40E_HW_100M_SGMII_CAPABLE BIT(6)
499 #define I40E_HW_NO_DCB_SUPPORT BIT(7)
500 #define I40E_HW_USE_SET_LLDP_MIB BIT(8)
501 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
502 #define I40E_HW_PTP_L4_CAPABLE BIT(10)
503 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
504 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12)
505 #define I40E_HW_HAVE_CRT_RETIMER BIT(13)
506 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
507 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
508 #define I40E_HW_STOP_FW_LLDP BIT(16)
509 #define I40E_HW_PORT_ID_VALID BIT(17)
510 #define I40E_HW_RESTART_AUTONEG BIT(18)
511
512 u32 flags;
513 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
514 #define I40E_FLAG_MSI_ENABLED BIT(1)
515 #define I40E_FLAG_MSIX_ENABLED BIT(2)
516 #define I40E_FLAG_RSS_ENABLED BIT(3)
517 #define I40E_FLAG_VMDQ_ENABLED BIT(4)
518 #define I40E_FLAG_FILTER_SYNC BIT(5)
519 #define I40E_FLAG_SRIOV_ENABLED BIT(6)
520 #define I40E_FLAG_DCB_CAPABLE BIT(7)
521 #define I40E_FLAG_DCB_ENABLED BIT(8)
522 #define I40E_FLAG_FD_SB_ENABLED BIT(9)
523 #define I40E_FLAG_FD_ATR_ENABLED BIT(10)
524 #define I40E_FLAG_FD_SB_AUTO_DISABLED BIT(11)
525 #define I40E_FLAG_FD_ATR_AUTO_DISABLED BIT(12)
526 #define I40E_FLAG_MFP_ENABLED BIT(13)
527 #define I40E_FLAG_UDP_FILTER_SYNC BIT(14)
528 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(15)
529 #define I40E_FLAG_VEB_MODE_ENABLED BIT(16)
530 #define I40E_FLAG_VEB_STATS_ENABLED BIT(17)
531 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(18)
532 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(19)
533 #define I40E_FLAG_TEMP_LINK_POLLING BIT(20)
534 #define I40E_FLAG_LEGACY_RX BIT(21)
535 #define I40E_FLAG_PTP BIT(22)
536 #define I40E_FLAG_IWARP_ENABLED BIT(23)
537 #define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT(24)
538 #define I40E_FLAG_CLIENT_L2_CHANGE BIT(25)
539 #define I40E_FLAG_CLIENT_RESET BIT(26)
540 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(27)
541 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(28)
542 #define I40E_FLAG_TC_MQPRIO BIT(29)
543 #define I40E_FLAG_FD_SB_INACTIVE BIT(30)
544 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(31)
545
546 struct i40e_client_instance *cinst;
547 bool stat_offsets_loaded;
548 struct i40e_hw_port_stats stats;
549 struct i40e_hw_port_stats stats_offsets;
550 u32 tx_timeout_count;
551 u32 tx_timeout_recovery_level;
552 unsigned long tx_timeout_last_recovery;
553 u32 tx_sluggish_count;
554 u32 hw_csum_rx_error;
555 u32 led_status;
556 u16 corer_count; /* Core reset count */
557 u16 globr_count; /* Global reset count */
558 u16 empr_count; /* EMP reset count */
559 u16 pfr_count; /* PF reset count */
560 u16 sw_int_count; /* SW interrupt count */
561
562 struct mutex switch_mutex;
563 u16 lan_vsi; /* our default LAN VSI */
564 u16 lan_veb; /* initial relay, if exists */
565 #define I40E_NO_VEB 0xffff
566 #define I40E_NO_VSI 0xffff
567 u16 next_vsi; /* Next unallocated VSI - 0-based! */
568 struct i40e_vsi **vsi;
569 struct i40e_veb *veb[I40E_MAX_VEB];
570
571 struct i40e_lump_tracking *qp_pile;
572 struct i40e_lump_tracking *irq_pile;
573
574 /* switch config info */
575 u16 pf_seid;
576 u16 main_vsi_seid;
577 u16 mac_seid;
578 struct kobject *switch_kobj;
579 #ifdef CONFIG_DEBUG_FS
580 struct dentry *i40e_dbg_pf;
581 #endif /* CONFIG_DEBUG_FS */
582 bool cur_promisc;
583
584 u16 instance; /* A unique number per i40e_pf instance in the system */
585
586 /* sr-iov config info */
587 struct i40e_vf *vf;
588 int num_alloc_vfs; /* actual number of VFs allocated */
589 u32 vf_aq_requests;
590 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
591
592 /* DCBx/DCBNL capability for PF that indicates
593 * whether DCBx is managed by firmware or host
594 * based agent (LLDPAD). Also, indicates what
595 * flavor of DCBx protocol (IEEE/CEE) is supported
596 * by the device. For now we're supporting IEEE
597 * mode only.
598 */
599 u16 dcbx_cap;
600
601 struct i40e_filter_control_settings filter_settings;
602
603 struct ptp_clock *ptp_clock;
604 struct ptp_clock_info ptp_caps;
605 struct sk_buff *ptp_tx_skb;
606 unsigned long ptp_tx_start;
607 struct hwtstamp_config tstamp_config;
608 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
609 u64 ptp_base_adj;
610 u32 tx_hwtstamp_timeouts;
611 u32 tx_hwtstamp_skipped;
612 u32 rx_hwtstamp_cleared;
613 u32 latch_event_flags;
614 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
615 unsigned long latch_events[4];
616 bool ptp_tx;
617 bool ptp_rx;
618 u16 rss_table_size; /* HW RSS table size */
619 u32 max_bw;
620 u32 min_bw;
621
622 u32 ioremap_len;
623 u32 fd_inv;
624 u16 phy_led_val;
625
626 u16 override_q_count;
627 u16 last_sw_conf_flags;
628 u16 last_sw_conf_valid_flags;
629 };
630
631 /**
632 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
633 * @macaddr: the MAC Address as the base key
634 *
635 * Simply copies the address and returns it as a u64 for hashing
636 **/
637 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
638 {
639 u64 key = 0;
640
641 ether_addr_copy((u8 *)&key, macaddr);
642 return key;
643 }
644
645 enum i40e_filter_state {
646 I40E_FILTER_INVALID = 0, /* Invalid state */
647 I40E_FILTER_NEW, /* New, not sent to FW yet */
648 I40E_FILTER_ACTIVE, /* Added to switch by FW */
649 I40E_FILTER_FAILED, /* Rejected by FW */
650 I40E_FILTER_REMOVE, /* To be removed */
651 /* There is no 'removed' state; the filter struct is freed */
652 };
653 struct i40e_mac_filter {
654 struct hlist_node hlist;
655 u8 macaddr[ETH_ALEN];
656 #define I40E_VLAN_ANY -1
657 s16 vlan;
658 enum i40e_filter_state state;
659 };
660
661 /* Wrapper structure to keep track of filters while we are preparing to send
662 * firmware commands. We cannot send firmware commands while holding a
663 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
664 * a separate structure, which will track the state change and update the real
665 * filter while under lock. We can't simply hold the filters in a separate
666 * list, as this opens a window for a race condition when adding new MAC
667 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
668 */
669 struct i40e_new_mac_filter {
670 struct hlist_node hlist;
671 struct i40e_mac_filter *f;
672
673 /* Track future changes to state separately */
674 enum i40e_filter_state state;
675 };
676
677 struct i40e_veb {
678 struct i40e_pf *pf;
679 u16 idx;
680 u16 veb_idx; /* index of VEB parent */
681 u16 seid;
682 u16 uplink_seid;
683 u16 stats_idx; /* index of VEB parent */
684 u8 enabled_tc;
685 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
686 u16 flags;
687 u16 bw_limit;
688 u8 bw_max_quanta;
689 bool is_abs_credits;
690 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
691 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
692 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
693 struct kobject *kobj;
694 bool stat_offsets_loaded;
695 struct i40e_eth_stats stats;
696 struct i40e_eth_stats stats_offsets;
697 struct i40e_veb_tc_stats tc_stats;
698 struct i40e_veb_tc_stats tc_stats_offsets;
699 };
700
701 /* struct that defines a VSI, associated with a dev */
702 struct i40e_vsi {
703 struct net_device *netdev;
704 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
705 bool netdev_registered;
706 bool stat_offsets_loaded;
707
708 u32 current_netdev_flags;
709 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
710 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
711 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
712 unsigned long flags;
713
714 /* Per VSI lock to protect elements/hash (MAC filter) */
715 spinlock_t mac_filter_hash_lock;
716 /* Fixed size hash table with 2^8 buckets for MAC filters */
717 DECLARE_HASHTABLE(mac_filter_hash, 8);
718 bool has_vlan_filter;
719
720 /* VSI stats */
721 struct rtnl_link_stats64 net_stats;
722 struct rtnl_link_stats64 net_stats_offsets;
723 struct i40e_eth_stats eth_stats;
724 struct i40e_eth_stats eth_stats_offsets;
725 u32 tx_restart;
726 u32 tx_busy;
727 u64 tx_linearize;
728 u64 tx_force_wb;
729 u32 rx_buf_failed;
730 u32 rx_page_failed;
731
732 /* These are containers of ring pointers, allocated at run-time */
733 struct i40e_ring **rx_rings;
734 struct i40e_ring **tx_rings;
735 struct i40e_ring **xdp_rings; /* XDP Tx rings */
736
737 u32 active_filters;
738 u32 promisc_threshold;
739
740 u16 work_limit;
741 u16 int_rate_limit; /* value in usecs */
742
743 u16 rss_table_size; /* HW RSS table size */
744 u16 rss_size; /* Allocated RSS queues */
745 u8 *rss_hkey_user; /* User configured hash keys */
746 u8 *rss_lut_user; /* User configured lookup table entries */
747
748
749 u16 max_frame;
750 u16 rx_buf_len;
751
752 struct bpf_prog *xdp_prog;
753
754 /* List of q_vectors allocated to this VSI */
755 struct i40e_q_vector **q_vectors;
756 int num_q_vectors;
757 int base_vector;
758 bool irqs_ready;
759
760 u16 seid; /* HW index of this VSI (absolute index) */
761 u16 id; /* VSI number */
762 u16 uplink_seid;
763
764 u16 base_queue; /* vsi's first queue in hw array */
765 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
766 u16 req_queue_pairs; /* User requested queue pairs */
767 u16 num_queue_pairs; /* Used tx and rx pairs */
768 u16 num_desc;
769 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
770 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
771
772 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
773 struct i40e_tc_configuration tc_config;
774 struct i40e_aqc_vsi_properties_data info;
775
776 /* VSI BW limit (absolute across all TCs) */
777 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
778 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
779
780 /* Relative TC credits across VSIs */
781 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
782 /* TC BW limit credits within VSI */
783 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
784 /* TC BW limit max quanta within VSI */
785 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
786
787 struct i40e_pf *back; /* Backreference to associated PF */
788 u16 idx; /* index in pf->vsi[] */
789 u16 veb_idx; /* index of VEB parent */
790 struct kobject *kobj; /* sysfs object */
791 bool current_isup; /* Sync 'link up' logging */
792 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
793
794 /* channel specific fields */
795 u16 cnt_q_avail; /* num of queues available for channel usage */
796 u16 orig_rss_size;
797 u16 current_rss_size;
798 bool reconfig_rss;
799
800 u16 next_base_queue; /* next queue to be used for channel setup */
801
802 struct list_head ch_list;
803 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
804
805 void *priv; /* client driver data reference. */
806
807 /* VSI specific handlers */
808 irqreturn_t (*irq_handler)(int irq, void *data);
809 } ____cacheline_internodealigned_in_smp;
810
811 struct i40e_netdev_priv {
812 struct i40e_vsi *vsi;
813 };
814
815 /* struct that defines an interrupt vector */
816 struct i40e_q_vector {
817 struct i40e_vsi *vsi;
818
819 u16 v_idx; /* index in the vsi->q_vector array. */
820 u16 reg_idx; /* register index of the interrupt */
821
822 struct napi_struct napi;
823
824 struct i40e_ring_container rx;
825 struct i40e_ring_container tx;
826
827 u8 num_ringpairs; /* total number of ring pairs in vector */
828
829 cpumask_t affinity_mask;
830 struct irq_affinity_notify affinity_notify;
831
832 struct rcu_head rcu; /* to avoid race with update stats on free */
833 char name[I40E_INT_NAME_STR_LEN];
834 bool arm_wb_state;
835 #define ITR_COUNTDOWN_START 100
836 u8 itr_countdown; /* when 0 should adjust ITR */
837 } ____cacheline_internodealigned_in_smp;
838
839 /* lan device */
840 struct i40e_device {
841 struct list_head list;
842 struct i40e_pf *pf;
843 };
844
845 /**
846 * i40e_nvm_version_str - format the NVM version strings
847 * @hw: ptr to the hardware info
848 **/
849 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
850 {
851 static char buf[32];
852 u32 full_ver;
853
854 full_ver = hw->nvm.oem_ver;
855
856 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
857 u8 gen, snap;
858 u16 release;
859
860 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
861 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
862 I40E_OEM_SNAP_SHIFT);
863 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
864
865 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
866 } else {
867 u8 ver, patch;
868 u16 build;
869
870 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
871 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
872 I40E_OEM_VER_BUILD_MASK);
873 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
874
875 snprintf(buf, sizeof(buf),
876 "%x.%02x 0x%x %d.%d.%d",
877 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
878 I40E_NVM_VERSION_HI_SHIFT,
879 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
880 I40E_NVM_VERSION_LO_SHIFT,
881 hw->nvm.eetrack, ver, build, patch);
882 }
883
884 return buf;
885 }
886
887 /**
888 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
889 * @netdev: the corresponding netdev
890 *
891 * Return the PF struct for the given netdev
892 **/
893 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
894 {
895 struct i40e_netdev_priv *np = netdev_priv(netdev);
896 struct i40e_vsi *vsi = np->vsi;
897
898 return vsi->back;
899 }
900
901 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
902 irqreturn_t (*irq_handler)(int, void *))
903 {
904 vsi->irq_handler = irq_handler;
905 }
906
907 /**
908 * i40e_get_fd_cnt_all - get the total FD filter space available
909 * @pf: pointer to the PF struct
910 **/
911 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
912 {
913 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
914 }
915
916 /**
917 * i40e_read_fd_input_set - reads value of flow director input set register
918 * @pf: pointer to the PF struct
919 * @addr: register addr
920 *
921 * This function reads value of flow director input set register
922 * specified by 'addr' (which is specific to flow-type)
923 **/
924 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
925 {
926 u64 val;
927
928 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
929 val <<= 32;
930 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
931
932 return val;
933 }
934
935 /**
936 * i40e_write_fd_input_set - writes value into flow director input set register
937 * @pf: pointer to the PF struct
938 * @addr: register addr
939 * @val: value to be written
940 *
941 * This function writes specified value to the register specified by 'addr'.
942 * This register is input set register based on flow-type.
943 **/
944 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
945 u16 addr, u64 val)
946 {
947 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
948 (u32)(val >> 32));
949 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
950 (u32)(val & 0xFFFFFFFFULL));
951 }
952
953 /* needed by i40e_ethtool.c */
954 int i40e_up(struct i40e_vsi *vsi);
955 void i40e_down(struct i40e_vsi *vsi);
956 extern const char i40e_driver_name[];
957 extern const char i40e_driver_version_str[];
958 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
959 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
960 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
961 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
962 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
963 u16 rss_table_size, u16 rss_size);
964 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
965 /**
966 * i40e_find_vsi_by_type - Find and return Flow Director VSI
967 * @pf: PF to search for VSI
968 * @type: Value indicating type of VSI we are looking for
969 **/
970 static inline struct i40e_vsi *
971 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
972 {
973 int i;
974
975 for (i = 0; i < pf->num_alloc_vsi; i++) {
976 struct i40e_vsi *vsi = pf->vsi[i];
977
978 if (vsi && vsi->type == type)
979 return vsi;
980 }
981
982 return NULL;
983 }
984 void i40e_update_stats(struct i40e_vsi *vsi);
985 void i40e_update_eth_stats(struct i40e_vsi *vsi);
986 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
987 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
988 bool printconfig);
989
990 int i40e_add_del_fdir(struct i40e_vsi *vsi,
991 struct i40e_fdir_filter *input, bool add);
992 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
993 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
994 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
995 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
996 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
997 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
998 void i40e_set_ethtool_ops(struct net_device *netdev);
999 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1000 const u8 *macaddr, s16 vlan);
1001 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1002 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1003 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1004 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1005 u16 uplink, u32 param1);
1006 int i40e_vsi_release(struct i40e_vsi *vsi);
1007 void i40e_service_event_schedule(struct i40e_pf *pf);
1008 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1009 u8 *msg, u16 len);
1010
1011 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1012 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1013 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1014 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1015 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1016 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1017 u16 downlink_seid, u8 enabled_tc);
1018 void i40e_veb_release(struct i40e_veb *veb);
1019
1020 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1021 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1022 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1023 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1024 void i40e_pf_reset_stats(struct i40e_pf *pf);
1025 #ifdef CONFIG_DEBUG_FS
1026 void i40e_dbg_pf_init(struct i40e_pf *pf);
1027 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1028 void i40e_dbg_init(void);
1029 void i40e_dbg_exit(void);
1030 #else
1031 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1032 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1033 static inline void i40e_dbg_init(void) {}
1034 static inline void i40e_dbg_exit(void) {}
1035 #endif /* CONFIG_DEBUG_FS*/
1036 /* needed by client drivers */
1037 int i40e_lan_add_device(struct i40e_pf *pf);
1038 int i40e_lan_del_device(struct i40e_pf *pf);
1039 void i40e_client_subtask(struct i40e_pf *pf);
1040 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1041 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1042 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1043 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1044 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1045 /**
1046 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1047 * @vsi: pointer to a vsi
1048 * @vector: enable a particular Hw Interrupt vector, without base_vector
1049 **/
1050 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1051 {
1052 struct i40e_pf *pf = vsi->back;
1053 struct i40e_hw *hw = &pf->hw;
1054 u32 val;
1055
1056 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1057 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1058 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1059 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1060 /* skip the flush */
1061 }
1062
1063 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1064 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1065 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1066 int i40e_open(struct net_device *netdev);
1067 int i40e_close(struct net_device *netdev);
1068 int i40e_vsi_open(struct i40e_vsi *vsi);
1069 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1070 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1071 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1072 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1073 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1074 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1075 const u8 *macaddr);
1076 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1077 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1078 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1079 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1080 #ifdef CONFIG_I40E_DCB
1081 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1082 struct i40e_dcbx_config *old_cfg,
1083 struct i40e_dcbx_config *new_cfg);
1084 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1085 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1086 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1087 struct i40e_dcbx_config *old_cfg,
1088 struct i40e_dcbx_config *new_cfg);
1089 #endif /* CONFIG_I40E_DCB */
1090 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1091 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1092 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1093 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1094 void i40e_ptp_set_increment(struct i40e_pf *pf);
1095 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1096 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1097 void i40e_ptp_init(struct i40e_pf *pf);
1098 void i40e_ptp_stop(struct i40e_pf *pf);
1099 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1100 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1101 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1102 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1103 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1104
1105 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1106 {
1107 return !!vsi->xdp_prog;
1108 }
1109
1110 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1111 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1112 #endif /* _I40E_H_ */
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