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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_adminq.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_status.h"
28 #include "i40e_type.h"
29 #include "i40e_register.h"
30 #include "i40e_adminq.h"
31 #include "i40e_prototype.h"
32
33 static void i40e_resume_aq(struct i40e_hw *hw);
34
35 /**
36 * i40e_is_nvm_update_op - return true if this is an NVM update operation
37 * @desc: API request descriptor
38 **/
39 static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
40 {
41 return (desc->opcode == cpu_to_le16(i40e_aqc_opc_nvm_erase)) ||
42 (desc->opcode == cpu_to_le16(i40e_aqc_opc_nvm_update));
43 }
44
45 /**
46 * i40e_adminq_init_regs - Initialize AdminQ registers
47 * @hw: pointer to the hardware structure
48 *
49 * This assumes the alloc_asq and alloc_arq functions have already been called
50 **/
51 static void i40e_adminq_init_regs(struct i40e_hw *hw)
52 {
53 /* set head and tail registers in our local struct */
54 if (i40e_is_vf(hw)) {
55 hw->aq.asq.tail = I40E_VF_ATQT1;
56 hw->aq.asq.head = I40E_VF_ATQH1;
57 hw->aq.asq.len = I40E_VF_ATQLEN1;
58 hw->aq.asq.bal = I40E_VF_ATQBAL1;
59 hw->aq.asq.bah = I40E_VF_ATQBAH1;
60 hw->aq.arq.tail = I40E_VF_ARQT1;
61 hw->aq.arq.head = I40E_VF_ARQH1;
62 hw->aq.arq.len = I40E_VF_ARQLEN1;
63 hw->aq.arq.bal = I40E_VF_ARQBAL1;
64 hw->aq.arq.bah = I40E_VF_ARQBAH1;
65 } else {
66 hw->aq.asq.tail = I40E_PF_ATQT;
67 hw->aq.asq.head = I40E_PF_ATQH;
68 hw->aq.asq.len = I40E_PF_ATQLEN;
69 hw->aq.asq.bal = I40E_PF_ATQBAL;
70 hw->aq.asq.bah = I40E_PF_ATQBAH;
71 hw->aq.arq.tail = I40E_PF_ARQT;
72 hw->aq.arq.head = I40E_PF_ARQH;
73 hw->aq.arq.len = I40E_PF_ARQLEN;
74 hw->aq.arq.bal = I40E_PF_ARQBAL;
75 hw->aq.arq.bah = I40E_PF_ARQBAH;
76 }
77 }
78
79 /**
80 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
81 * @hw: pointer to the hardware structure
82 **/
83 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
84 {
85 i40e_status ret_code;
86
87 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
88 i40e_mem_atq_ring,
89 (hw->aq.num_asq_entries *
90 sizeof(struct i40e_aq_desc)),
91 I40E_ADMINQ_DESC_ALIGNMENT);
92 if (ret_code)
93 return ret_code;
94
95 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
96 (hw->aq.num_asq_entries *
97 sizeof(struct i40e_asq_cmd_details)));
98 if (ret_code) {
99 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
100 return ret_code;
101 }
102
103 return ret_code;
104 }
105
106 /**
107 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
108 * @hw: pointer to the hardware structure
109 **/
110 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
111 {
112 i40e_status ret_code;
113
114 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
115 i40e_mem_arq_ring,
116 (hw->aq.num_arq_entries *
117 sizeof(struct i40e_aq_desc)),
118 I40E_ADMINQ_DESC_ALIGNMENT);
119
120 return ret_code;
121 }
122
123 /**
124 * i40e_free_adminq_asq - Free Admin Queue send rings
125 * @hw: pointer to the hardware structure
126 *
127 * This assumes the posted send buffers have already been cleaned
128 * and de-allocated
129 **/
130 static void i40e_free_adminq_asq(struct i40e_hw *hw)
131 {
132 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
133 }
134
135 /**
136 * i40e_free_adminq_arq - Free Admin Queue receive rings
137 * @hw: pointer to the hardware structure
138 *
139 * This assumes the posted receive buffers have already been cleaned
140 * and de-allocated
141 **/
142 static void i40e_free_adminq_arq(struct i40e_hw *hw)
143 {
144 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
145 }
146
147 /**
148 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
149 * @hw: pointer to the hardware structure
150 **/
151 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
152 {
153 i40e_status ret_code;
154 struct i40e_aq_desc *desc;
155 struct i40e_dma_mem *bi;
156 int i;
157
158 /* We'll be allocating the buffer info memory first, then we can
159 * allocate the mapped buffers for the event processing
160 */
161
162 /* buffer_info structures do not need alignment */
163 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
164 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
165 if (ret_code)
166 goto alloc_arq_bufs;
167 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
168
169 /* allocate the mapped buffers */
170 for (i = 0; i < hw->aq.num_arq_entries; i++) {
171 bi = &hw->aq.arq.r.arq_bi[i];
172 ret_code = i40e_allocate_dma_mem(hw, bi,
173 i40e_mem_arq_buf,
174 hw->aq.arq_buf_size,
175 I40E_ADMINQ_DESC_ALIGNMENT);
176 if (ret_code)
177 goto unwind_alloc_arq_bufs;
178
179 /* now configure the descriptors for use */
180 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
181
182 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
183 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
184 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
185 desc->opcode = 0;
186 /* This is in accordance with Admin queue design, there is no
187 * register for buffer size configuration
188 */
189 desc->datalen = cpu_to_le16((u16)bi->size);
190 desc->retval = 0;
191 desc->cookie_high = 0;
192 desc->cookie_low = 0;
193 desc->params.external.addr_high =
194 cpu_to_le32(upper_32_bits(bi->pa));
195 desc->params.external.addr_low =
196 cpu_to_le32(lower_32_bits(bi->pa));
197 desc->params.external.param0 = 0;
198 desc->params.external.param1 = 0;
199 }
200
201 alloc_arq_bufs:
202 return ret_code;
203
204 unwind_alloc_arq_bufs:
205 /* don't try to free the one that failed... */
206 i--;
207 for (; i >= 0; i--)
208 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
209 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
210
211 return ret_code;
212 }
213
214 /**
215 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
216 * @hw: pointer to the hardware structure
217 **/
218 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
219 {
220 i40e_status ret_code;
221 struct i40e_dma_mem *bi;
222 int i;
223
224 /* No mapped memory needed yet, just the buffer info structures */
225 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
226 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
227 if (ret_code)
228 goto alloc_asq_bufs;
229 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
230
231 /* allocate the mapped buffers */
232 for (i = 0; i < hw->aq.num_asq_entries; i++) {
233 bi = &hw->aq.asq.r.asq_bi[i];
234 ret_code = i40e_allocate_dma_mem(hw, bi,
235 i40e_mem_asq_buf,
236 hw->aq.asq_buf_size,
237 I40E_ADMINQ_DESC_ALIGNMENT);
238 if (ret_code)
239 goto unwind_alloc_asq_bufs;
240 }
241 alloc_asq_bufs:
242 return ret_code;
243
244 unwind_alloc_asq_bufs:
245 /* don't try to free the one that failed... */
246 i--;
247 for (; i >= 0; i--)
248 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
249 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
250
251 return ret_code;
252 }
253
254 /**
255 * i40e_free_arq_bufs - Free receive queue buffer info elements
256 * @hw: pointer to the hardware structure
257 **/
258 static void i40e_free_arq_bufs(struct i40e_hw *hw)
259 {
260 int i;
261
262 /* free descriptors */
263 for (i = 0; i < hw->aq.num_arq_entries; i++)
264 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
265
266 /* free the descriptor memory */
267 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
268
269 /* free the dma header */
270 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
271 }
272
273 /**
274 * i40e_free_asq_bufs - Free send queue buffer info elements
275 * @hw: pointer to the hardware structure
276 **/
277 static void i40e_free_asq_bufs(struct i40e_hw *hw)
278 {
279 int i;
280
281 /* only unmap if the address is non-NULL */
282 for (i = 0; i < hw->aq.num_asq_entries; i++)
283 if (hw->aq.asq.r.asq_bi[i].pa)
284 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
285
286 /* free the buffer info list */
287 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
288
289 /* free the descriptor memory */
290 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
291
292 /* free the dma header */
293 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
294 }
295
296 /**
297 * i40e_config_asq_regs - configure ASQ registers
298 * @hw: pointer to the hardware structure
299 *
300 * Configure base address and length registers for the transmit queue
301 **/
302 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
303 {
304 i40e_status ret_code = 0;
305 u32 reg = 0;
306
307 /* Clear Head and Tail */
308 wr32(hw, hw->aq.asq.head, 0);
309 wr32(hw, hw->aq.asq.tail, 0);
310
311 /* set starting point */
312 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
313 I40E_PF_ATQLEN_ATQENABLE_MASK));
314 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
315 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
316
317 /* Check one register to verify that config was applied */
318 reg = rd32(hw, hw->aq.asq.bal);
319 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
320 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
321
322 return ret_code;
323 }
324
325 /**
326 * i40e_config_arq_regs - ARQ register configuration
327 * @hw: pointer to the hardware structure
328 *
329 * Configure base address and length registers for the receive (event queue)
330 **/
331 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
332 {
333 i40e_status ret_code = 0;
334 u32 reg = 0;
335
336 /* Clear Head and Tail */
337 wr32(hw, hw->aq.arq.head, 0);
338 wr32(hw, hw->aq.arq.tail, 0);
339
340 /* set starting point */
341 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
342 I40E_PF_ARQLEN_ARQENABLE_MASK));
343 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
344 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
345
346 /* Update tail in the HW to post pre-allocated buffers */
347 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
348
349 /* Check one register to verify that config was applied */
350 reg = rd32(hw, hw->aq.arq.bal);
351 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
352 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
353
354 return ret_code;
355 }
356
357 /**
358 * i40e_init_asq - main initialization routine for ASQ
359 * @hw: pointer to the hardware structure
360 *
361 * This is the main initialization routine for the Admin Send Queue
362 * Prior to calling this function, drivers *MUST* set the following fields
363 * in the hw->aq structure:
364 * - hw->aq.num_asq_entries
365 * - hw->aq.arq_buf_size
366 *
367 * Do *NOT* hold the lock when calling this as the memory allocation routines
368 * called are not going to be atomic context safe
369 **/
370 static i40e_status i40e_init_asq(struct i40e_hw *hw)
371 {
372 i40e_status ret_code = 0;
373
374 if (hw->aq.asq.count > 0) {
375 /* queue already initialized */
376 ret_code = I40E_ERR_NOT_READY;
377 goto init_adminq_exit;
378 }
379
380 /* verify input for valid configuration */
381 if ((hw->aq.num_asq_entries == 0) ||
382 (hw->aq.asq_buf_size == 0)) {
383 ret_code = I40E_ERR_CONFIG;
384 goto init_adminq_exit;
385 }
386
387 hw->aq.asq.next_to_use = 0;
388 hw->aq.asq.next_to_clean = 0;
389
390 /* allocate the ring memory */
391 ret_code = i40e_alloc_adminq_asq_ring(hw);
392 if (ret_code)
393 goto init_adminq_exit;
394
395 /* allocate buffers in the rings */
396 ret_code = i40e_alloc_asq_bufs(hw);
397 if (ret_code)
398 goto init_adminq_free_rings;
399
400 /* initialize base registers */
401 ret_code = i40e_config_asq_regs(hw);
402 if (ret_code)
403 goto init_adminq_free_rings;
404
405 /* success! */
406 hw->aq.asq.count = hw->aq.num_asq_entries;
407 goto init_adminq_exit;
408
409 init_adminq_free_rings:
410 i40e_free_adminq_asq(hw);
411
412 init_adminq_exit:
413 return ret_code;
414 }
415
416 /**
417 * i40e_init_arq - initialize ARQ
418 * @hw: pointer to the hardware structure
419 *
420 * The main initialization routine for the Admin Receive (Event) Queue.
421 * Prior to calling this function, drivers *MUST* set the following fields
422 * in the hw->aq structure:
423 * - hw->aq.num_asq_entries
424 * - hw->aq.arq_buf_size
425 *
426 * Do *NOT* hold the lock when calling this as the memory allocation routines
427 * called are not going to be atomic context safe
428 **/
429 static i40e_status i40e_init_arq(struct i40e_hw *hw)
430 {
431 i40e_status ret_code = 0;
432
433 if (hw->aq.arq.count > 0) {
434 /* queue already initialized */
435 ret_code = I40E_ERR_NOT_READY;
436 goto init_adminq_exit;
437 }
438
439 /* verify input for valid configuration */
440 if ((hw->aq.num_arq_entries == 0) ||
441 (hw->aq.arq_buf_size == 0)) {
442 ret_code = I40E_ERR_CONFIG;
443 goto init_adminq_exit;
444 }
445
446 hw->aq.arq.next_to_use = 0;
447 hw->aq.arq.next_to_clean = 0;
448
449 /* allocate the ring memory */
450 ret_code = i40e_alloc_adminq_arq_ring(hw);
451 if (ret_code)
452 goto init_adminq_exit;
453
454 /* allocate buffers in the rings */
455 ret_code = i40e_alloc_arq_bufs(hw);
456 if (ret_code)
457 goto init_adminq_free_rings;
458
459 /* initialize base registers */
460 ret_code = i40e_config_arq_regs(hw);
461 if (ret_code)
462 goto init_adminq_free_rings;
463
464 /* success! */
465 hw->aq.arq.count = hw->aq.num_arq_entries;
466 goto init_adminq_exit;
467
468 init_adminq_free_rings:
469 i40e_free_adminq_arq(hw);
470
471 init_adminq_exit:
472 return ret_code;
473 }
474
475 /**
476 * i40e_shutdown_asq - shutdown the ASQ
477 * @hw: pointer to the hardware structure
478 *
479 * The main shutdown routine for the Admin Send Queue
480 **/
481 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
482 {
483 i40e_status ret_code = 0;
484
485 mutex_lock(&hw->aq.asq_mutex);
486
487 if (hw->aq.asq.count == 0) {
488 ret_code = I40E_ERR_NOT_READY;
489 goto shutdown_asq_out;
490 }
491
492 /* Stop firmware AdminQ processing */
493 wr32(hw, hw->aq.asq.head, 0);
494 wr32(hw, hw->aq.asq.tail, 0);
495 wr32(hw, hw->aq.asq.len, 0);
496 wr32(hw, hw->aq.asq.bal, 0);
497 wr32(hw, hw->aq.asq.bah, 0);
498
499 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
500
501 /* free ring buffers */
502 i40e_free_asq_bufs(hw);
503
504 shutdown_asq_out:
505 mutex_unlock(&hw->aq.asq_mutex);
506 return ret_code;
507 }
508
509 /**
510 * i40e_shutdown_arq - shutdown ARQ
511 * @hw: pointer to the hardware structure
512 *
513 * The main shutdown routine for the Admin Receive Queue
514 **/
515 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
516 {
517 i40e_status ret_code = 0;
518
519 mutex_lock(&hw->aq.arq_mutex);
520
521 if (hw->aq.arq.count == 0) {
522 ret_code = I40E_ERR_NOT_READY;
523 goto shutdown_arq_out;
524 }
525
526 /* Stop firmware AdminQ processing */
527 wr32(hw, hw->aq.arq.head, 0);
528 wr32(hw, hw->aq.arq.tail, 0);
529 wr32(hw, hw->aq.arq.len, 0);
530 wr32(hw, hw->aq.arq.bal, 0);
531 wr32(hw, hw->aq.arq.bah, 0);
532
533 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
534
535 /* free ring buffers */
536 i40e_free_arq_bufs(hw);
537
538 shutdown_arq_out:
539 mutex_unlock(&hw->aq.arq_mutex);
540 return ret_code;
541 }
542
543 /**
544 * i40e_init_adminq - main initialization routine for Admin Queue
545 * @hw: pointer to the hardware structure
546 *
547 * Prior to calling this function, drivers *MUST* set the following fields
548 * in the hw->aq structure:
549 * - hw->aq.num_asq_entries
550 * - hw->aq.num_arq_entries
551 * - hw->aq.arq_buf_size
552 * - hw->aq.asq_buf_size
553 **/
554 i40e_status i40e_init_adminq(struct i40e_hw *hw)
555 {
556 u16 cfg_ptr, oem_hi, oem_lo;
557 u16 eetrack_lo, eetrack_hi;
558 i40e_status ret_code;
559 int retry = 0;
560
561 /* verify input for valid configuration */
562 if ((hw->aq.num_arq_entries == 0) ||
563 (hw->aq.num_asq_entries == 0) ||
564 (hw->aq.arq_buf_size == 0) ||
565 (hw->aq.asq_buf_size == 0)) {
566 ret_code = I40E_ERR_CONFIG;
567 goto init_adminq_exit;
568 }
569
570 /* initialize locks */
571 mutex_init(&hw->aq.asq_mutex);
572 mutex_init(&hw->aq.arq_mutex);
573
574 /* Set up register offsets */
575 i40e_adminq_init_regs(hw);
576
577 /* setup ASQ command write back timeout */
578 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
579
580 /* allocate the ASQ */
581 ret_code = i40e_init_asq(hw);
582 if (ret_code)
583 goto init_adminq_destroy_locks;
584
585 /* allocate the ARQ */
586 ret_code = i40e_init_arq(hw);
587 if (ret_code)
588 goto init_adminq_free_asq;
589
590 /* There are some cases where the firmware may not be quite ready
591 * for AdminQ operations, so we retry the AdminQ setup a few times
592 * if we see timeouts in this first AQ call.
593 */
594 do {
595 ret_code = i40e_aq_get_firmware_version(hw,
596 &hw->aq.fw_maj_ver,
597 &hw->aq.fw_min_ver,
598 &hw->aq.fw_build,
599 &hw->aq.api_maj_ver,
600 &hw->aq.api_min_ver,
601 NULL);
602 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
603 break;
604 retry++;
605 msleep(100);
606 i40e_resume_aq(hw);
607 } while (retry < 10);
608 if (ret_code != I40E_SUCCESS)
609 goto init_adminq_free_arq;
610
611 /* get the NVM version info */
612 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,
613 &hw->nvm.version);
614 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
615 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
616 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
617 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr);
618 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF),
619 &oem_hi);
620 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)),
621 &oem_lo);
622 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
623
624 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
625 ret_code = I40E_ERR_FIRMWARE_API_VERSION;
626 goto init_adminq_free_arq;
627 }
628
629 /* pre-emptive resource lock release */
630 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
631 hw->aq.nvm_release_on_done = false;
632 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
633
634 ret_code = i40e_aq_set_hmc_resource_profile(hw,
635 I40E_HMC_PROFILE_DEFAULT,
636 0,
637 NULL);
638 ret_code = 0;
639
640 /* success! */
641 goto init_adminq_exit;
642
643 init_adminq_free_arq:
644 i40e_shutdown_arq(hw);
645 init_adminq_free_asq:
646 i40e_shutdown_asq(hw);
647 init_adminq_destroy_locks:
648
649 init_adminq_exit:
650 return ret_code;
651 }
652
653 /**
654 * i40e_shutdown_adminq - shutdown routine for the Admin Queue
655 * @hw: pointer to the hardware structure
656 **/
657 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw)
658 {
659 i40e_status ret_code = 0;
660
661 if (i40e_check_asq_alive(hw))
662 i40e_aq_queue_shutdown(hw, true);
663
664 i40e_shutdown_asq(hw);
665 i40e_shutdown_arq(hw);
666
667 /* destroy the locks */
668
669 if (hw->nvm_buff.va)
670 i40e_free_virt_mem(hw, &hw->nvm_buff);
671
672 return ret_code;
673 }
674
675 /**
676 * i40e_clean_asq - cleans Admin send queue
677 * @hw: pointer to the hardware structure
678 *
679 * returns the number of free desc
680 **/
681 static u16 i40e_clean_asq(struct i40e_hw *hw)
682 {
683 struct i40e_adminq_ring *asq = &(hw->aq.asq);
684 struct i40e_asq_cmd_details *details;
685 u16 ntc = asq->next_to_clean;
686 struct i40e_aq_desc desc_cb;
687 struct i40e_aq_desc *desc;
688
689 desc = I40E_ADMINQ_DESC(*asq, ntc);
690 details = I40E_ADMINQ_DETAILS(*asq, ntc);
691 while (rd32(hw, hw->aq.asq.head) != ntc) {
692 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
693 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
694
695 if (details->callback) {
696 I40E_ADMINQ_CALLBACK cb_func =
697 (I40E_ADMINQ_CALLBACK)details->callback;
698 desc_cb = *desc;
699 cb_func(hw, &desc_cb);
700 }
701 memset(desc, 0, sizeof(*desc));
702 memset(details, 0, sizeof(*details));
703 ntc++;
704 if (ntc == asq->count)
705 ntc = 0;
706 desc = I40E_ADMINQ_DESC(*asq, ntc);
707 details = I40E_ADMINQ_DETAILS(*asq, ntc);
708 }
709
710 asq->next_to_clean = ntc;
711
712 return I40E_DESC_UNUSED(asq);
713 }
714
715 /**
716 * i40e_asq_done - check if FW has processed the Admin Send Queue
717 * @hw: pointer to the hw struct
718 *
719 * Returns true if the firmware has processed all descriptors on the
720 * admin send queue. Returns false if there are still requests pending.
721 **/
722 static bool i40e_asq_done(struct i40e_hw *hw)
723 {
724 /* AQ designers suggest use of head for better
725 * timing reliability than DD bit
726 */
727 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
728
729 }
730
731 /**
732 * i40e_asq_send_command - send command to Admin Queue
733 * @hw: pointer to the hw struct
734 * @desc: prefilled descriptor describing the command (non DMA mem)
735 * @buff: buffer to use for indirect commands
736 * @buff_size: size of buffer for indirect commands
737 * @cmd_details: pointer to command details structure
738 *
739 * This is the main send command driver routine for the Admin Queue send
740 * queue. It runs the queue, cleans the queue, etc
741 **/
742 i40e_status i40e_asq_send_command(struct i40e_hw *hw,
743 struct i40e_aq_desc *desc,
744 void *buff, /* can be NULL */
745 u16 buff_size,
746 struct i40e_asq_cmd_details *cmd_details)
747 {
748 i40e_status status = 0;
749 struct i40e_dma_mem *dma_buff = NULL;
750 struct i40e_asq_cmd_details *details;
751 struct i40e_aq_desc *desc_on_ring;
752 bool cmd_completed = false;
753 u16 retval = 0;
754 u32 val = 0;
755
756 mutex_lock(&hw->aq.asq_mutex);
757
758 if (hw->aq.asq.count == 0) {
759 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
760 "AQTX: Admin queue not initialized.\n");
761 status = I40E_ERR_QUEUE_EMPTY;
762 goto asq_send_command_error;
763 }
764
765 hw->aq.asq_last_status = I40E_AQ_RC_OK;
766
767 val = rd32(hw, hw->aq.asq.head);
768 if (val >= hw->aq.num_asq_entries) {
769 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
770 "AQTX: head overrun at %d\n", val);
771 status = I40E_ERR_QUEUE_EMPTY;
772 goto asq_send_command_error;
773 }
774
775 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
776 if (cmd_details) {
777 *details = *cmd_details;
778
779 /* If the cmd_details are defined copy the cookie. The
780 * cpu_to_le32 is not needed here because the data is ignored
781 * by the FW, only used by the driver
782 */
783 if (details->cookie) {
784 desc->cookie_high =
785 cpu_to_le32(upper_32_bits(details->cookie));
786 desc->cookie_low =
787 cpu_to_le32(lower_32_bits(details->cookie));
788 }
789 } else {
790 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
791 }
792
793 /* clear requested flags and then set additional flags if defined */
794 desc->flags &= ~cpu_to_le16(details->flags_dis);
795 desc->flags |= cpu_to_le16(details->flags_ena);
796
797 if (buff_size > hw->aq.asq_buf_size) {
798 i40e_debug(hw,
799 I40E_DEBUG_AQ_MESSAGE,
800 "AQTX: Invalid buffer size: %d.\n",
801 buff_size);
802 status = I40E_ERR_INVALID_SIZE;
803 goto asq_send_command_error;
804 }
805
806 if (details->postpone && !details->async) {
807 i40e_debug(hw,
808 I40E_DEBUG_AQ_MESSAGE,
809 "AQTX: Async flag not set along with postpone flag");
810 status = I40E_ERR_PARAM;
811 goto asq_send_command_error;
812 }
813
814 /* call clean and check queue available function to reclaim the
815 * descriptors that were processed by FW, the function returns the
816 * number of desc available
817 */
818 /* the clean function called here could be called in a separate thread
819 * in case of asynchronous completions
820 */
821 if (i40e_clean_asq(hw) == 0) {
822 i40e_debug(hw,
823 I40E_DEBUG_AQ_MESSAGE,
824 "AQTX: Error queue is full.\n");
825 status = I40E_ERR_ADMIN_QUEUE_FULL;
826 goto asq_send_command_error;
827 }
828
829 /* initialize the temp desc pointer with the right desc */
830 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
831
832 /* if the desc is available copy the temp desc to the right place */
833 *desc_on_ring = *desc;
834
835 /* if buff is not NULL assume indirect command */
836 if (buff != NULL) {
837 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
838 /* copy the user buff into the respective DMA buff */
839 memcpy(dma_buff->va, buff, buff_size);
840 desc_on_ring->datalen = cpu_to_le16(buff_size);
841
842 /* Update the address values in the desc with the pa value
843 * for respective buffer
844 */
845 desc_on_ring->params.external.addr_high =
846 cpu_to_le32(upper_32_bits(dma_buff->pa));
847 desc_on_ring->params.external.addr_low =
848 cpu_to_le32(lower_32_bits(dma_buff->pa));
849 }
850
851 /* bump the tail */
852 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
853 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
854 buff, buff_size);
855 (hw->aq.asq.next_to_use)++;
856 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
857 hw->aq.asq.next_to_use = 0;
858 if (!details->postpone)
859 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
860
861 /* if cmd_details are not defined or async flag is not set,
862 * we need to wait for desc write back
863 */
864 if (!details->async && !details->postpone) {
865 u32 total_delay = 0;
866
867 do {
868 /* AQ designers suggest use of head for better
869 * timing reliability than DD bit
870 */
871 if (i40e_asq_done(hw))
872 break;
873 usleep_range(1000, 2000);
874 total_delay++;
875 } while (total_delay < hw->aq.asq_cmd_timeout);
876 }
877
878 /* if ready, copy the desc back to temp */
879 if (i40e_asq_done(hw)) {
880 *desc = *desc_on_ring;
881 if (buff != NULL)
882 memcpy(buff, dma_buff->va, buff_size);
883 retval = le16_to_cpu(desc->retval);
884 if (retval != 0) {
885 i40e_debug(hw,
886 I40E_DEBUG_AQ_MESSAGE,
887 "AQTX: Command completed with error 0x%X.\n",
888 retval);
889
890 /* strip off FW internal code */
891 retval &= 0xff;
892 }
893 cmd_completed = true;
894 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
895 status = 0;
896 else
897 status = I40E_ERR_ADMIN_QUEUE_ERROR;
898 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
899 }
900
901 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
902 "AQTX: desc and buffer writeback:\n");
903 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
904
905 /* save writeback aq if requested */
906 if (details->wb_desc)
907 *details->wb_desc = *desc_on_ring;
908
909 /* update the error if time out occurred */
910 if ((!cmd_completed) &&
911 (!details->async && !details->postpone)) {
912 i40e_debug(hw,
913 I40E_DEBUG_AQ_MESSAGE,
914 "AQTX: Writeback timeout.\n");
915 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
916 }
917
918 asq_send_command_error:
919 mutex_unlock(&hw->aq.asq_mutex);
920 return status;
921 }
922
923 /**
924 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
925 * @desc: pointer to the temp descriptor (non DMA mem)
926 * @opcode: the opcode can be used to decide which flags to turn off or on
927 *
928 * Fill the desc with default values
929 **/
930 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
931 u16 opcode)
932 {
933 /* zero out the desc */
934 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
935 desc->opcode = cpu_to_le16(opcode);
936 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
937 }
938
939 /**
940 * i40e_clean_arq_element
941 * @hw: pointer to the hw struct
942 * @e: event info from the receive descriptor, includes any buffers
943 * @pending: number of events that could be left to process
944 *
945 * This function cleans one Admin Receive Queue element and returns
946 * the contents through e. It can also return how many events are
947 * left to process through 'pending'
948 **/
949 i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
950 struct i40e_arq_event_info *e,
951 u16 *pending)
952 {
953 i40e_status ret_code = 0;
954 u16 ntc = hw->aq.arq.next_to_clean;
955 struct i40e_aq_desc *desc;
956 struct i40e_dma_mem *bi;
957 u16 desc_idx;
958 u16 datalen;
959 u16 flags;
960 u16 ntu;
961
962 /* take the lock before we start messing with the ring */
963 mutex_lock(&hw->aq.arq_mutex);
964
965 if (hw->aq.arq.count == 0) {
966 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
967 "AQRX: Admin queue not initialized.\n");
968 ret_code = I40E_ERR_QUEUE_EMPTY;
969 goto clean_arq_element_err;
970 }
971
972 /* set next_to_use to head */
973 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
974 if (ntu == ntc) {
975 /* nothing to do - shouldn't need to update ring's values */
976 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
977 goto clean_arq_element_out;
978 }
979
980 /* now clean the next descriptor */
981 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
982 desc_idx = ntc;
983
984 flags = le16_to_cpu(desc->flags);
985 if (flags & I40E_AQ_FLAG_ERR) {
986 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
987 hw->aq.arq_last_status =
988 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
989 i40e_debug(hw,
990 I40E_DEBUG_AQ_MESSAGE,
991 "AQRX: Event received with error 0x%X.\n",
992 hw->aq.arq_last_status);
993 }
994
995 e->desc = *desc;
996 datalen = le16_to_cpu(desc->datalen);
997 e->msg_len = min(datalen, e->buf_len);
998 if (e->msg_buf != NULL && (e->msg_len != 0))
999 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
1000 e->msg_len);
1001
1002 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
1003 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
1004 hw->aq.arq_buf_size);
1005
1006 /* Restore the original datalen and buffer address in the desc,
1007 * FW updates datalen to indicate the event message
1008 * size
1009 */
1010 bi = &hw->aq.arq.r.arq_bi[ntc];
1011 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
1012
1013 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
1014 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
1015 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
1016 desc->datalen = cpu_to_le16((u16)bi->size);
1017 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
1018 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
1019
1020 /* set tail = the last cleaned desc index. */
1021 wr32(hw, hw->aq.arq.tail, ntc);
1022 /* ntc is updated to tail + 1 */
1023 ntc++;
1024 if (ntc == hw->aq.num_arq_entries)
1025 ntc = 0;
1026 hw->aq.arq.next_to_clean = ntc;
1027 hw->aq.arq.next_to_use = ntu;
1028
1029 clean_arq_element_out:
1030 /* Set pending if needed, unlock and return */
1031 if (pending != NULL)
1032 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1033
1034 clean_arq_element_err:
1035 mutex_unlock(&hw->aq.arq_mutex);
1036
1037 if (i40e_is_nvm_update_op(&e->desc)) {
1038 if (hw->aq.nvm_release_on_done) {
1039 i40e_release_nvm(hw);
1040 hw->aq.nvm_release_on_done = false;
1041 }
1042
1043 switch (hw->nvmupd_state) {
1044 case I40E_NVMUPD_STATE_INIT_WAIT:
1045 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1046 break;
1047
1048 case I40E_NVMUPD_STATE_WRITE_WAIT:
1049 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1050 break;
1051
1052 default:
1053 break;
1054 }
1055 }
1056
1057 return ret_code;
1058 }
1059
1060 static void i40e_resume_aq(struct i40e_hw *hw)
1061 {
1062 /* Registers are reset after PF reset */
1063 hw->aq.asq.next_to_use = 0;
1064 hw->aq.asq.next_to_clean = 0;
1065
1066 i40e_config_asq_regs(hw);
1067
1068 hw->aq.arq.next_to_use = 0;
1069 hw->aq.arq.next_to_clean = 0;
1070
1071 i40e_config_arq_regs(hw);
1072 }
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