1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
4 #ifndef _I40E_ADMINQ_CMD_H_
5 #define _I40E_ADMINQ_CMD_H_
7 /* This header file defines the i40e Admin Queue commands and is shared between
8 * i40e Firmware and Software.
10 * This file needs to comply with the Linux Kernel coding style.
13 #define I40E_FW_API_VERSION_MAJOR 0x0001
14 #define I40E_FW_API_VERSION_MINOR_X722 0x0009
15 #define I40E_FW_API_VERSION_MINOR_X710 0x0009
17 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
18 I40E_FW_API_VERSION_MINOR_X710 : \
19 I40E_FW_API_VERSION_MINOR_X722)
21 /* API version 1.7 implements additional link and PHY-specific APIs */
22 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
23 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */
24 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
25 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
26 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
52 /* Flags sub-structure
53 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
54 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
57 /* command flags and offsets*/
58 #define I40E_AQ_FLAG_DD_SHIFT 0
59 #define I40E_AQ_FLAG_CMP_SHIFT 1
60 #define I40E_AQ_FLAG_ERR_SHIFT 2
61 #define I40E_AQ_FLAG_VFE_SHIFT 3
62 #define I40E_AQ_FLAG_LB_SHIFT 9
63 #define I40E_AQ_FLAG_RD_SHIFT 10
64 #define I40E_AQ_FLAG_VFC_SHIFT 11
65 #define I40E_AQ_FLAG_BUF_SHIFT 12
66 #define I40E_AQ_FLAG_SI_SHIFT 13
67 #define I40E_AQ_FLAG_EI_SHIFT 14
68 #define I40E_AQ_FLAG_FE_SHIFT 15
70 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
71 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
72 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
73 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
74 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
75 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
76 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
77 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
78 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
79 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
80 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
83 enum i40e_admin_queue_err
{
84 I40E_AQ_RC_OK
= 0, /* success */
85 I40E_AQ_RC_EPERM
= 1, /* Operation not permitted */
86 I40E_AQ_RC_ENOENT
= 2, /* No such element */
87 I40E_AQ_RC_ESRCH
= 3, /* Bad opcode */
88 I40E_AQ_RC_EINTR
= 4, /* operation interrupted */
89 I40E_AQ_RC_EIO
= 5, /* I/O error */
90 I40E_AQ_RC_ENXIO
= 6, /* No such resource */
91 I40E_AQ_RC_E2BIG
= 7, /* Arg too long */
92 I40E_AQ_RC_EAGAIN
= 8, /* Try again */
93 I40E_AQ_RC_ENOMEM
= 9, /* Out of memory */
94 I40E_AQ_RC_EACCES
= 10, /* Permission denied */
95 I40E_AQ_RC_EFAULT
= 11, /* Bad address */
96 I40E_AQ_RC_EBUSY
= 12, /* Device or resource busy */
97 I40E_AQ_RC_EEXIST
= 13, /* object already exists */
98 I40E_AQ_RC_EINVAL
= 14, /* Invalid argument */
99 I40E_AQ_RC_ENOTTY
= 15, /* Not a typewriter */
100 I40E_AQ_RC_ENOSPC
= 16, /* No space left or alloc failure */
101 I40E_AQ_RC_ENOSYS
= 17, /* Function not implemented */
102 I40E_AQ_RC_ERANGE
= 18, /* Parameter out of range */
103 I40E_AQ_RC_EFLUSHED
= 19, /* Cmd flushed due to prev cmd error */
104 I40E_AQ_RC_BAD_ADDR
= 20, /* Descriptor contains a bad pointer */
105 I40E_AQ_RC_EMODE
= 21, /* Op not allowed in current dev mode */
106 I40E_AQ_RC_EFBIG
= 22, /* File too large */
109 /* Admin Queue command opcodes */
110 enum i40e_admin_queue_opc
{
112 i40e_aqc_opc_get_version
= 0x0001,
113 i40e_aqc_opc_driver_version
= 0x0002,
114 i40e_aqc_opc_queue_shutdown
= 0x0003,
115 i40e_aqc_opc_set_pf_context
= 0x0004,
117 /* resource ownership */
118 i40e_aqc_opc_request_resource
= 0x0008,
119 i40e_aqc_opc_release_resource
= 0x0009,
121 i40e_aqc_opc_list_func_capabilities
= 0x000A,
122 i40e_aqc_opc_list_dev_capabilities
= 0x000B,
125 i40e_aqc_opc_set_proxy_config
= 0x0104,
126 i40e_aqc_opc_set_ns_proxy_table_entry
= 0x0105,
129 i40e_aqc_opc_mac_address_read
= 0x0107,
130 i40e_aqc_opc_mac_address_write
= 0x0108,
133 i40e_aqc_opc_clear_pxe_mode
= 0x0110,
136 i40e_aqc_opc_set_wol_filter
= 0x0120,
137 i40e_aqc_opc_get_wake_reason
= 0x0121,
139 /* internal switch commands */
140 i40e_aqc_opc_get_switch_config
= 0x0200,
141 i40e_aqc_opc_add_statistics
= 0x0201,
142 i40e_aqc_opc_remove_statistics
= 0x0202,
143 i40e_aqc_opc_set_port_parameters
= 0x0203,
144 i40e_aqc_opc_get_switch_resource_alloc
= 0x0204,
145 i40e_aqc_opc_set_switch_config
= 0x0205,
146 i40e_aqc_opc_rx_ctl_reg_read
= 0x0206,
147 i40e_aqc_opc_rx_ctl_reg_write
= 0x0207,
149 i40e_aqc_opc_add_vsi
= 0x0210,
150 i40e_aqc_opc_update_vsi_parameters
= 0x0211,
151 i40e_aqc_opc_get_vsi_parameters
= 0x0212,
153 i40e_aqc_opc_add_pv
= 0x0220,
154 i40e_aqc_opc_update_pv_parameters
= 0x0221,
155 i40e_aqc_opc_get_pv_parameters
= 0x0222,
157 i40e_aqc_opc_add_veb
= 0x0230,
158 i40e_aqc_opc_update_veb_parameters
= 0x0231,
159 i40e_aqc_opc_get_veb_parameters
= 0x0232,
161 i40e_aqc_opc_delete_element
= 0x0243,
163 i40e_aqc_opc_add_macvlan
= 0x0250,
164 i40e_aqc_opc_remove_macvlan
= 0x0251,
165 i40e_aqc_opc_add_vlan
= 0x0252,
166 i40e_aqc_opc_remove_vlan
= 0x0253,
167 i40e_aqc_opc_set_vsi_promiscuous_modes
= 0x0254,
168 i40e_aqc_opc_add_tag
= 0x0255,
169 i40e_aqc_opc_remove_tag
= 0x0256,
170 i40e_aqc_opc_add_multicast_etag
= 0x0257,
171 i40e_aqc_opc_remove_multicast_etag
= 0x0258,
172 i40e_aqc_opc_update_tag
= 0x0259,
173 i40e_aqc_opc_add_control_packet_filter
= 0x025A,
174 i40e_aqc_opc_remove_control_packet_filter
= 0x025B,
175 i40e_aqc_opc_add_cloud_filters
= 0x025C,
176 i40e_aqc_opc_remove_cloud_filters
= 0x025D,
177 i40e_aqc_opc_clear_wol_switch_filters
= 0x025E,
179 i40e_aqc_opc_add_mirror_rule
= 0x0260,
180 i40e_aqc_opc_delete_mirror_rule
= 0x0261,
182 /* Dynamic Device Personalization */
183 i40e_aqc_opc_write_personalization_profile
= 0x0270,
184 i40e_aqc_opc_get_personalization_profile_list
= 0x0271,
187 i40e_aqc_opc_dcb_ignore_pfc
= 0x0301,
188 i40e_aqc_opc_dcb_updated
= 0x0302,
189 i40e_aqc_opc_set_dcb_parameters
= 0x0303,
192 i40e_aqc_opc_configure_vsi_bw_limit
= 0x0400,
193 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
= 0x0406,
194 i40e_aqc_opc_configure_vsi_tc_bw
= 0x0407,
195 i40e_aqc_opc_query_vsi_bw_config
= 0x0408,
196 i40e_aqc_opc_query_vsi_ets_sla_config
= 0x040A,
197 i40e_aqc_opc_configure_switching_comp_bw_limit
= 0x0410,
199 i40e_aqc_opc_enable_switching_comp_ets
= 0x0413,
200 i40e_aqc_opc_modify_switching_comp_ets
= 0x0414,
201 i40e_aqc_opc_disable_switching_comp_ets
= 0x0415,
202 i40e_aqc_opc_configure_switching_comp_ets_bw_limit
= 0x0416,
203 i40e_aqc_opc_configure_switching_comp_bw_config
= 0x0417,
204 i40e_aqc_opc_query_switching_comp_ets_config
= 0x0418,
205 i40e_aqc_opc_query_port_ets_config
= 0x0419,
206 i40e_aqc_opc_query_switching_comp_bw_config
= 0x041A,
207 i40e_aqc_opc_suspend_port_tx
= 0x041B,
208 i40e_aqc_opc_resume_port_tx
= 0x041C,
209 i40e_aqc_opc_configure_partition_bw
= 0x041D,
211 i40e_aqc_opc_query_hmc_resource_profile
= 0x0500,
212 i40e_aqc_opc_set_hmc_resource_profile
= 0x0501,
215 i40e_aqc_opc_get_phy_abilities
= 0x0600,
216 i40e_aqc_opc_set_phy_config
= 0x0601,
217 i40e_aqc_opc_set_mac_config
= 0x0603,
218 i40e_aqc_opc_set_link_restart_an
= 0x0605,
219 i40e_aqc_opc_get_link_status
= 0x0607,
220 i40e_aqc_opc_set_phy_int_mask
= 0x0613,
221 i40e_aqc_opc_get_local_advt_reg
= 0x0614,
222 i40e_aqc_opc_set_local_advt_reg
= 0x0615,
223 i40e_aqc_opc_get_partner_advt
= 0x0616,
224 i40e_aqc_opc_set_lb_modes
= 0x0618,
225 i40e_aqc_opc_get_phy_wol_caps
= 0x0621,
226 i40e_aqc_opc_set_phy_debug
= 0x0622,
227 i40e_aqc_opc_upload_ext_phy_fm
= 0x0625,
228 i40e_aqc_opc_run_phy_activity
= 0x0626,
229 i40e_aqc_opc_set_phy_register
= 0x0628,
230 i40e_aqc_opc_get_phy_register
= 0x0629,
233 i40e_aqc_opc_nvm_read
= 0x0701,
234 i40e_aqc_opc_nvm_erase
= 0x0702,
235 i40e_aqc_opc_nvm_update
= 0x0703,
236 i40e_aqc_opc_nvm_config_read
= 0x0704,
237 i40e_aqc_opc_nvm_config_write
= 0x0705,
238 i40e_aqc_opc_oem_post_update
= 0x0720,
239 i40e_aqc_opc_thermal_sensor
= 0x0721,
241 /* virtualization commands */
242 i40e_aqc_opc_send_msg_to_pf
= 0x0801,
243 i40e_aqc_opc_send_msg_to_vf
= 0x0802,
244 i40e_aqc_opc_send_msg_to_peer
= 0x0803,
246 /* alternate structure */
247 i40e_aqc_opc_alternate_write
= 0x0900,
248 i40e_aqc_opc_alternate_write_indirect
= 0x0901,
249 i40e_aqc_opc_alternate_read
= 0x0902,
250 i40e_aqc_opc_alternate_read_indirect
= 0x0903,
251 i40e_aqc_opc_alternate_write_done
= 0x0904,
252 i40e_aqc_opc_alternate_set_mode
= 0x0905,
253 i40e_aqc_opc_alternate_clear_port
= 0x0906,
256 i40e_aqc_opc_lldp_get_mib
= 0x0A00,
257 i40e_aqc_opc_lldp_update_mib
= 0x0A01,
258 i40e_aqc_opc_lldp_add_tlv
= 0x0A02,
259 i40e_aqc_opc_lldp_update_tlv
= 0x0A03,
260 i40e_aqc_opc_lldp_delete_tlv
= 0x0A04,
261 i40e_aqc_opc_lldp_stop
= 0x0A05,
262 i40e_aqc_opc_lldp_start
= 0x0A06,
263 i40e_aqc_opc_get_cee_dcb_cfg
= 0x0A07,
264 i40e_aqc_opc_lldp_set_local_mib
= 0x0A08,
265 i40e_aqc_opc_lldp_stop_start_spec_agent
= 0x0A09,
266 i40e_aqc_opc_lldp_restore
= 0x0A0A,
268 /* Tunnel commands */
269 i40e_aqc_opc_add_udp_tunnel
= 0x0B00,
270 i40e_aqc_opc_del_udp_tunnel
= 0x0B01,
271 i40e_aqc_opc_set_rss_key
= 0x0B02,
272 i40e_aqc_opc_set_rss_lut
= 0x0B03,
273 i40e_aqc_opc_get_rss_key
= 0x0B04,
274 i40e_aqc_opc_get_rss_lut
= 0x0B05,
277 i40e_aqc_opc_event_lan_overflow
= 0x1001,
280 i40e_aqc_opc_oem_parameter_change
= 0xFE00,
281 i40e_aqc_opc_oem_device_status_change
= 0xFE01,
282 i40e_aqc_opc_oem_ocsd_initialize
= 0xFE02,
283 i40e_aqc_opc_oem_ocbb_initialize
= 0xFE03,
286 i40e_aqc_opc_debug_read_reg
= 0xFF03,
287 i40e_aqc_opc_debug_write_reg
= 0xFF04,
288 i40e_aqc_opc_debug_modify_reg
= 0xFF07,
289 i40e_aqc_opc_debug_dump_internals
= 0xFF08,
292 /* command structures and indirect data structures */
294 /* Structure naming conventions:
295 * - no suffix for direct command descriptor structures
296 * - _data for indirect sent data
297 * - _resp for indirect return data (data which is both will use _data)
298 * - _completion for direct return data
299 * - _element_ for repeated elements (may also be _data or _resp)
301 * Command structures are expected to overlay the params.raw member of the basic
302 * descriptor, and as such cannot exceed 16 bytes in length.
305 /* This macro is used to generate a compilation error if a structure
306 * is not exactly the correct length. It gives a divide by zero error if the
307 * structure is not of the correct size, otherwise it creates an enum that is
310 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
311 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
313 /* This macro is used extensively to ensure that command structures are 16
314 * bytes in length as they have to map to the raw array of that size.
316 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
318 /* internal (0x00XX) commands */
320 /* Get version (direct 0x0001) */
321 struct i40e_aqc_get_version
{
330 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version
);
332 /* Send driver version (indirect 0x0002) */
333 struct i40e_aqc_driver_version
{
337 u8 driver_subbuild_ver
;
343 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version
);
345 /* Queue Shutdown (direct 0x0003) */
346 struct i40e_aqc_queue_shutdown
{
347 __le32 driver_unloading
;
348 #define I40E_AQ_DRIVER_UNLOADING 0x1
352 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown
);
354 /* Set PF context (0x0004, direct) */
355 struct i40e_aqc_set_pf_context
{
360 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context
);
362 /* Request resource ownership (direct 0x0008)
363 * Release resource ownership (direct 0x0009)
365 #define I40E_AQ_RESOURCE_NVM 1
366 #define I40E_AQ_RESOURCE_SDP 2
367 #define I40E_AQ_RESOURCE_ACCESS_READ 1
368 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
369 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
370 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
372 struct i40e_aqc_request_resource
{
376 __le32 resource_number
;
380 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource
);
382 /* Get function capabilities (indirect 0x000A)
383 * Get device capabilities (indirect 0x000B)
385 struct i40e_aqc_list_capabilites
{
387 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
395 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites
);
397 struct i40e_aqc_list_capabilities_element_resp
{
409 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
410 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
411 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
412 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
413 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
414 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
415 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
416 #define I40E_AQ_CAP_ID_SRIOV 0x0012
417 #define I40E_AQ_CAP_ID_VF 0x0013
418 #define I40E_AQ_CAP_ID_VMDQ 0x0014
419 #define I40E_AQ_CAP_ID_8021QBG 0x0015
420 #define I40E_AQ_CAP_ID_8021QBR 0x0016
421 #define I40E_AQ_CAP_ID_VSI 0x0017
422 #define I40E_AQ_CAP_ID_DCB 0x0018
423 #define I40E_AQ_CAP_ID_FCOE 0x0021
424 #define I40E_AQ_CAP_ID_ISCSI 0x0022
425 #define I40E_AQ_CAP_ID_RSS 0x0040
426 #define I40E_AQ_CAP_ID_RXQ 0x0041
427 #define I40E_AQ_CAP_ID_TXQ 0x0042
428 #define I40E_AQ_CAP_ID_MSIX 0x0043
429 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
430 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
431 #define I40E_AQ_CAP_ID_1588 0x0046
432 #define I40E_AQ_CAP_ID_IWARP 0x0051
433 #define I40E_AQ_CAP_ID_LED 0x0061
434 #define I40E_AQ_CAP_ID_SDP 0x0062
435 #define I40E_AQ_CAP_ID_MDIO 0x0063
436 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
437 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
438 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
439 #define I40E_AQ_CAP_ID_CEM 0x00F2
441 /* Set CPPM Configuration (direct 0x0103) */
442 struct i40e_aqc_cppm_configuration
{
443 __le16 command_flags
;
444 #define I40E_AQ_CPPM_EN_LTRC 0x0800
445 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
446 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
447 #define I40E_AQ_CPPM_EN_HPTC 0x4000
448 #define I40E_AQ_CPPM_EN_DMARC 0x8000
457 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration
);
459 /* Set ARP Proxy command / response (indirect 0x0104) */
460 struct i40e_aqc_arp_proxy_data
{
461 __le16 command_flags
;
462 #define I40E_AQ_ARP_INIT_IPV4 0x0800
463 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
464 #define I40E_AQ_ARP_ENA 0x2000
465 #define I40E_AQ_ARP_ADD_IPV4 0x4000
466 #define I40E_AQ_ARP_DEL_IPV4 0x8000
468 __le32 enabled_offloads
;
469 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
470 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
476 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data
);
478 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
479 struct i40e_aqc_ns_proxy_data
{
480 __le16 table_idx_mac_addr_0
;
481 __le16 table_idx_mac_addr_1
;
482 __le16 table_idx_ipv6_0
;
483 __le16 table_idx_ipv6_1
;
485 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
486 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
487 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
488 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
489 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
490 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
491 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
492 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
493 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
494 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
495 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
496 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
497 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
500 u8 local_mac_addr
[6];
501 u8 ipv6_addr_0
[16]; /* Warning! spec specifies BE byte order */
505 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data
);
507 /* Manage LAA Command (0x0106) - obsolete */
508 struct i40e_aqc_mng_laa
{
509 __le16 command_flags
;
510 #define I40E_AQ_LAA_FLAG_WR 0x8000
517 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa
);
519 /* Manage MAC Address Read Command (indirect 0x0107) */
520 struct i40e_aqc_mac_address_read
{
521 __le16 command_flags
;
522 #define I40E_AQC_LAN_ADDR_VALID 0x10
523 #define I40E_AQC_SAN_ADDR_VALID 0x20
524 #define I40E_AQC_PORT_ADDR_VALID 0x40
525 #define I40E_AQC_WOL_ADDR_VALID 0x80
526 #define I40E_AQC_MC_MAG_EN_VALID 0x100
527 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
533 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read
);
535 struct i40e_aqc_mac_address_read_data
{
542 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data
);
544 /* Manage MAC Address Write Command (0x0108) */
545 struct i40e_aqc_mac_address_write
{
546 __le16 command_flags
;
547 #define I40E_AQC_MC_MAG_EN 0x0100
548 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
549 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
550 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
551 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
552 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
553 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
560 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write
);
562 /* PXE commands (0x011x) */
564 /* Clear PXE Command and response (direct 0x0110) */
565 struct i40e_aqc_clear_pxe
{
570 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe
);
572 /* Set WoL Filter (0x0120) */
574 struct i40e_aqc_set_wol_filter
{
576 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
577 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
578 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
579 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
581 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
582 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
583 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
585 #define I40E_AQC_SET_WOL_FILTER 0x8000
586 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
587 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
588 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
590 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
591 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
597 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter
);
599 struct i40e_aqc_set_wol_filter_data
{
604 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data
);
606 /* Get Wake Reason (0x0121) */
608 struct i40e_aqc_get_wake_reason_completion
{
611 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
612 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
613 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
614 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
615 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
616 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
620 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion
);
622 /* Switch configuration commands (0x02xx) */
624 /* Used by many indirect commands that only pass an seid and a buffer in the
627 struct i40e_aqc_switch_seid
{
634 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid
);
636 /* Get Switch Configuration command (indirect 0x0200)
637 * uses i40e_aqc_switch_seid for the descriptor
639 struct i40e_aqc_get_switch_config_header_resp
{
645 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp
);
647 struct i40e_aqc_switch_config_element_resp
{
649 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
650 #define I40E_AQ_SW_ELEM_TYPE_PF 2
651 #define I40E_AQ_SW_ELEM_TYPE_VF 3
652 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
653 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
654 #define I40E_AQ_SW_ELEM_TYPE_PV 16
655 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
656 #define I40E_AQ_SW_ELEM_TYPE_PA 18
657 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
659 #define I40E_AQ_SW_ELEM_REV_1 1
662 __le16 downlink_seid
;
665 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
666 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
667 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
672 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp
);
674 /* Get Switch Configuration (indirect 0x0200)
675 * an array of elements are returned in the response buffer
676 * the first in the array is the header, remainder are elements
678 struct i40e_aqc_get_switch_config_resp
{
679 struct i40e_aqc_get_switch_config_header_resp header
;
680 struct i40e_aqc_switch_config_element_resp element
[1];
683 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp
);
685 /* Add Statistics (direct 0x0201)
686 * Remove Statistics (direct 0x0202)
688 struct i40e_aqc_add_remove_statistics
{
695 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics
);
697 /* Set Port Parameters command (direct 0x0203) */
698 struct i40e_aqc_set_port_parameters
{
699 __le16 command_flags
;
700 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
701 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
702 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
703 __le16 bad_frame_vsi
;
704 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
705 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
706 __le16 default_seid
; /* reserved for command */
710 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters
);
712 /* Get Switch Resource Allocation (indirect 0x0204) */
713 struct i40e_aqc_get_switch_resource_alloc
{
714 u8 num_entries
; /* reserved for command */
720 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc
);
722 /* expect an array of these structs in the response buffer */
723 struct i40e_aqc_switch_resource_alloc_element_resp
{
725 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
726 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
727 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
728 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
729 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
730 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
731 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
732 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
733 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
734 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
735 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
736 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
737 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
738 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
739 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
740 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
741 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
742 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
743 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
748 __le16 total_unalloced
;
752 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp
);
754 /* Set Switch Configuration (direct 0x0205) */
755 struct i40e_aqc_set_switch_config
{
757 /* flags used for both fields below */
758 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
759 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
761 /* The ethertype in switch_tag is dropped on ingress and used
762 * internally by the switch. Set this to zero for the default
763 * of 0x88a8 (802.1ad). Should be zero for firmware API
764 * versions lower than 1.7.
767 /* The ethertypes in first_tag and second_tag are used to
768 * match the outer and inner VLAN tags (respectively) when HW
769 * double VLAN tagging is enabled via the set port parameters
770 * AQ command. Otherwise these are both ignored. Set them to
771 * zero for their defaults of 0x8100 (802.1Q). Should be zero
772 * for firmware API versions lower than 1.7.
776 /* Next byte is split into following:
777 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
778 * Bit 6 : 0 : Destination Port, 1: source port
783 * 3: Both TCP and UDP
786 * 1: L4 port only mode
787 * 2: non-tunneled mode
790 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
792 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40
794 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00
795 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
796 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20
797 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30
799 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00
800 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01
801 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
802 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03
807 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config
);
809 /* Read Receive control registers (direct 0x0206)
810 * Write Receive control registers (direct 0x0207)
811 * used for accessing Rx control registers that can be
812 * slow and need special handling when under high Rx load
814 struct i40e_aqc_rx_ctl_reg_read_write
{
821 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write
);
823 /* Add VSI (indirect 0x0210)
824 * this indirect command uses struct i40e_aqc_vsi_properties_data
825 * as the indirect buffer (128 bytes)
827 * Update VSI (indirect 0x211)
828 * uses the same data structure as Add VSI
830 * Get VSI (indirect 0x0212)
831 * uses the same completion and data structure as Add VSI
833 struct i40e_aqc_add_get_update_vsi
{
836 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
837 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
838 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
843 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
844 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
845 #define I40E_AQ_VSI_TYPE_VF 0x0
846 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
847 #define I40E_AQ_VSI_TYPE_PF 0x2
848 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
849 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
854 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi
);
856 struct i40e_aqc_add_get_update_vsi_completion
{
865 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion
);
867 struct i40e_aqc_vsi_properties_data
{
868 /* first 96 byte are written by SW */
869 __le16 valid_sections
;
870 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
871 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
872 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
873 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
874 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
875 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
876 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
877 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
878 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
879 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
881 __le16 switch_id
; /* 12bit id combined with flags below */
882 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
883 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
884 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
885 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
886 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
888 /* security section */
890 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
891 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
892 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
895 __le16 pvid
; /* VLANS include priority bits */
898 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
899 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
900 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
901 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
902 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
903 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
904 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
905 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
906 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
907 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
908 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
909 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
910 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
911 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
912 u8 pvlan_reserved
[3];
913 /* ingress egress up sections */
914 __le32 ingress_table
; /* bitmap, 3 bits per up */
915 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
916 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
917 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
918 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
919 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
920 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
921 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
922 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
923 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
924 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
925 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
926 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
927 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
928 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
929 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
930 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
931 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
932 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
933 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
934 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
935 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
936 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
937 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
938 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
939 __le32 egress_table
; /* same defines as for ingress table */
940 /* cascaded PV section */
943 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
944 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
945 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
946 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
947 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
948 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
949 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
950 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
951 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
953 /* queue mapping section */
954 __le16 mapping_flags
;
955 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
956 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
957 __le16 queue_mapping
[16];
958 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
959 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
960 __le16 tc_mapping
[8];
961 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
962 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
963 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
964 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
965 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
966 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
967 /* queueing option section */
968 u8 queueing_opt_flags
;
969 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
970 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
971 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
972 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
973 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
974 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
975 u8 queueing_opt_reserved
[3];
976 /* scheduler section */
979 /* outer up section */
980 __le32 outer_up_table
; /* same structure and defines as ingress tbl */
982 /* last 32 bytes are written by FW */
984 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
985 __le16 stat_counter_idx
;
987 u8 resp_reserved
[12];
990 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data
);
992 /* Add Port Virtualizer (direct 0x0220)
993 * also used for update PV (direct 0x0221) but only flags are used
994 * (IS_CTRL_PORT only works on add PV)
996 struct i40e_aqc_add_update_pv
{
997 __le16 command_flags
;
998 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
999 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1000 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1001 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1003 __le16 connected_seid
;
1007 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv
);
1009 struct i40e_aqc_add_update_pv_completion
{
1010 /* reserved for update; for add also encodes error if rc == ENOSPC */
1012 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1013 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1014 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1015 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1019 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion
);
1021 /* Get PV Params (direct 0x0222)
1022 * uses i40e_aqc_switch_seid for the descriptor
1025 struct i40e_aqc_get_pv_params_completion
{
1027 __le16 default_stag
;
1028 __le16 pv_flags
; /* same flags as add_pv */
1029 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1030 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1031 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1033 __le16 default_port_seid
;
1036 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion
);
1038 /* Add VEB (direct 0x0230) */
1039 struct i40e_aqc_add_veb
{
1041 __le16 downlink_seid
;
1043 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1044 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1045 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1046 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1047 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1048 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1049 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1050 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1055 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb
);
1057 struct i40e_aqc_add_veb_completion
{
1060 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1062 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1063 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1064 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1065 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1066 __le16 statistic_index
;
1071 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion
);
1073 /* Get VEB Parameters (direct 0x0232)
1074 * uses i40e_aqc_switch_seid for the descriptor
1076 struct i40e_aqc_get_veb_parameters_completion
{
1079 __le16 veb_flags
; /* only the first/last flags from 0x0230 is valid */
1080 __le16 statistic_index
;
1086 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion
);
1088 /* Delete Element (direct 0x0243)
1089 * uses the generic i40e_aqc_switch_seid
1092 /* Add MAC-VLAN (indirect 0x0250) */
1094 /* used for the command for most vlan commands */
1095 struct i40e_aqc_macvlan
{
1096 __le16 num_addresses
;
1098 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1099 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1100 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1101 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1106 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan
);
1108 /* indirect data for command and response */
1109 struct i40e_aqc_add_macvlan_element_data
{
1113 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1114 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1115 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1116 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1117 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1118 __le16 queue_number
;
1119 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1120 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1121 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1122 /* response section */
1124 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1125 #define I40E_AQC_MM_HASH_MATCH 0x02
1126 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1130 struct i40e_aqc_add_remove_macvlan_completion
{
1131 __le16 perfect_mac_used
;
1132 __le16 perfect_mac_free
;
1133 __le16 unicast_hash_free
;
1134 __le16 multicast_hash_free
;
1139 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion
);
1141 /* Remove MAC-VLAN (indirect 0x0251)
1142 * uses i40e_aqc_macvlan for the descriptor
1143 * data points to an array of num_addresses of elements
1146 struct i40e_aqc_remove_macvlan_element_data
{
1150 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1151 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1152 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1153 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1157 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1158 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1159 u8 reply_reserved
[3];
1162 /* Add VLAN (indirect 0x0252)
1163 * Remove VLAN (indirect 0x0253)
1164 * use the generic i40e_aqc_macvlan for the command
1166 struct i40e_aqc_add_remove_vlan_element_data
{
1169 /* flags for add VLAN */
1170 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1171 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1172 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1173 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1174 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1175 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1176 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1177 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1178 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1179 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1180 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1181 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1182 /* flags for remove VLAN */
1183 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1186 /* flags for add VLAN */
1187 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1188 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1189 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1190 /* flags for remove VLAN */
1191 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1192 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1196 struct i40e_aqc_add_remove_vlan_completion
{
1204 /* Set VSI Promiscuous Modes (direct 0x0254) */
1205 struct i40e_aqc_set_vsi_promiscuous_modes
{
1206 __le16 promiscuous_flags
;
1208 /* flags used for both fields above */
1209 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1210 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1211 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1212 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1213 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1214 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1216 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1218 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1219 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1223 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes
);
1225 /* Add S/E-tag command (direct 0x0255)
1226 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1228 struct i40e_aqc_add_tag
{
1230 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1232 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1233 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1234 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1236 __le16 queue_number
;
1240 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag
);
1242 struct i40e_aqc_add_remove_tag_completion
{
1248 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion
);
1250 /* Remove S/E-tag command (direct 0x0256)
1251 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1253 struct i40e_aqc_remove_tag
{
1255 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1256 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1257 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1262 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag
);
1264 /* Add multicast E-Tag (direct 0x0257)
1265 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1266 * and no external data
1268 struct i40e_aqc_add_remove_mcast_etag
{
1271 u8 num_unicast_etags
;
1273 __le32 addr_high
; /* address of array of 2-byte s-tags */
1277 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag
);
1279 struct i40e_aqc_add_remove_mcast_etag_completion
{
1281 __le16 mcast_etags_used
;
1282 __le16 mcast_etags_free
;
1288 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion
);
1290 /* Update S/E-Tag (direct 0x0259) */
1291 struct i40e_aqc_update_tag
{
1293 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1294 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1295 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1301 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag
);
1303 struct i40e_aqc_update_tag_completion
{
1309 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion
);
1311 /* Add Control Packet filter (direct 0x025A)
1312 * Remove Control Packet filter (direct 0x025B)
1313 * uses the i40e_aqc_add_oveb_cloud,
1314 * and the generic direct completion structure
1316 struct i40e_aqc_add_remove_control_packet_filter
{
1320 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1321 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1322 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1323 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1324 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1326 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1327 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1328 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1333 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter
);
1335 struct i40e_aqc_add_remove_control_packet_filter_completion
{
1336 __le16 mac_etype_used
;
1338 __le16 mac_etype_free
;
1343 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion
);
1345 /* Add Cloud filters (indirect 0x025C)
1346 * Remove Cloud filters (indirect 0x025D)
1347 * uses the i40e_aqc_add_remove_cloud_filters,
1348 * and the generic indirect completion structure
1350 struct i40e_aqc_add_remove_cloud_filters
{
1354 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1355 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1356 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1358 #define I40E_AQC_ADD_CLOUD_CMD_BB 1
1364 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters
);
1366 struct i40e_aqc_cloud_filters_element_data
{
1383 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1384 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1385 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1386 /* 0x0000 reserved */
1387 /* 0x0001 reserved */
1388 /* 0x0002 reserved */
1389 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1390 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1391 /* 0x0005 reserved */
1392 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1393 /* 0x0007 reserved */
1394 /* 0x0008 reserved */
1395 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1396 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1397 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1398 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1399 /* 0x000D reserved */
1400 /* 0x000E reserved */
1401 /* 0x000F reserved */
1402 /* 0x0010 to 0x0017 is for custom filters */
1403 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1404 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1405 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1407 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1408 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1409 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1410 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1411 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1413 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1414 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1415 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1416 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1417 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1418 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1419 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1420 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1422 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1423 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1424 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1428 __le16 queue_number
;
1429 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1430 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1431 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1433 /* response section */
1434 u8 allocation_result
;
1435 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1436 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1437 u8 response_reserved
[7];
1440 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data
);
1442 /* i40e_aqc_cloud_filters_element_bb is used when
1443 * I40E_AQC_CLOUD_CMD_BB flag is set.
1445 struct i40e_aqc_cloud_filters_element_bb
{
1446 struct i40e_aqc_cloud_filters_element_data element
;
1447 u16 general_fields
[32];
1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1481 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb
);
1483 struct i40e_aqc_remove_cloud_filters_completion
{
1484 __le16 perfect_ovlan_used
;
1485 __le16 perfect_ovlan_free
;
1492 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion
);
1494 /* Replace filter Command 0x025F
1495 * uses the i40e_aqc_replace_cloud_filters,
1496 * and the generic indirect completion structure
1498 struct i40e_filter_data
{
1503 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data
);
1505 struct i40e_aqc_replace_cloud_filters_cmd
{
1507 #define I40E_AQC_REPLACE_L1_FILTER 0x0
1508 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1509 #define I40E_AQC_GET_CLOUD_FILTERS 0x2
1510 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1511 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1520 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd
);
1522 struct i40e_aqc_replace_cloud_filters_cmd_buf
{
1524 /* Filter type INPUT codes*/
1525 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1526 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7)
1528 /* Field Vector offsets */
1529 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1530 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1531 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1532 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1533 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1534 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1535 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1536 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1538 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1540 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1542 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1543 struct i40e_filter_data filters
[8];
1546 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf
);
1548 /* Add Mirror Rule (indirect or direct 0x0260)
1549 * Delete Mirror Rule (indirect or direct 0x0261)
1550 * note: some rule types (4,5) do not use an external buffer.
1551 * take care to set the flags correctly.
1553 struct i40e_aqc_add_delete_mirror_rule
{
1556 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1557 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1558 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1559 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1560 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1561 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1562 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1563 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1565 __le16 destination
; /* VSI for add, rule id for delete */
1566 __le32 addr_high
; /* address of array of 2-byte VSI or VLAN ids */
1570 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule
);
1572 struct i40e_aqc_add_delete_mirror_rule_completion
{
1574 __le16 rule_id
; /* only used on add */
1575 __le16 mirror_rules_used
;
1576 __le16 mirror_rules_free
;
1581 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion
);
1583 /* Dynamic Device Personalization */
1584 struct i40e_aqc_write_personalization_profile
{
1587 __le32 profile_track_id
;
1592 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile
);
1594 struct i40e_aqc_write_ddp_resp
{
1595 __le32 error_offset
;
1601 struct i40e_aqc_get_applied_profiles
{
1603 #define I40E_AQC_GET_DDP_GET_CONF 0x1
1604 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2
1611 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles
);
1615 /* PFC Ignore (direct 0x0301)
1616 * the command and response use the same descriptor structure
1618 struct i40e_aqc_pfc_ignore
{
1620 u8 command_flags
; /* unused on response */
1621 #define I40E_AQC_PFC_IGNORE_SET 0x80
1622 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1626 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore
);
1628 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1629 * with no parameters
1632 /* TX scheduler 0x04xx */
1634 /* Almost all the indirect commands use
1635 * this generic struct to pass the SEID in param0
1637 struct i40e_aqc_tx_sched_ind
{
1644 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind
);
1646 /* Several commands respond with a set of queue set handles */
1647 struct i40e_aqc_qs_handles_resp
{
1648 __le16 qs_handles
[8];
1651 /* Configure VSI BW limits (direct 0x0400) */
1652 struct i40e_aqc_configure_vsi_bw_limit
{
1657 u8 max_credit
; /* 0-3, limit = 2^max */
1661 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit
);
1663 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1664 * responds with i40e_aqc_qs_handles_resp
1666 struct i40e_aqc_configure_vsi_ets_sla_bw_data
{
1669 __le16 tc_bw_credits
[8]; /* FW writesback QS handles here */
1671 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1672 __le16 tc_bw_max
[2];
1676 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data
);
1678 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1679 * responds with i40e_aqc_qs_handles_resp
1681 struct i40e_aqc_configure_vsi_tc_bw_data
{
1684 u8 tc_bw_credits
[8];
1686 __le16 qs_handles
[8];
1689 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data
);
1691 /* Query vsi bw configuration (indirect 0x0408) */
1692 struct i40e_aqc_query_vsi_bw_config_resp
{
1694 u8 tc_suspended_bits
;
1696 __le16 qs_handles
[8];
1698 __le16 port_bw_limit
;
1700 u8 max_bw
; /* 0-3, limit = 2^max */
1704 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp
);
1706 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1707 struct i40e_aqc_query_vsi_ets_sla_config_resp
{
1710 u8 share_credits
[8];
1713 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1714 __le16 tc_bw_max
[2];
1717 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp
);
1719 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1720 struct i40e_aqc_configure_switching_comp_bw_limit
{
1725 u8 max_bw
; /* 0-3, limit = 2^max */
1729 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit
);
1731 /* Enable Physical Port ETS (indirect 0x0413)
1732 * Modify Physical Port ETS (indirect 0x0414)
1733 * Disable Physical Port ETS (indirect 0x0415)
1735 struct i40e_aqc_configure_switching_comp_ets_data
{
1739 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1740 u8 tc_strict_priority_flags
;
1742 u8 tc_bw_share_credits
[8];
1746 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data
);
1748 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1749 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data
{
1752 __le16 tc_bw_credit
[8];
1754 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1755 __le16 tc_bw_max
[2];
1759 I40E_CHECK_STRUCT_LEN(0x40,
1760 i40e_aqc_configure_switching_comp_ets_bw_limit_data
);
1762 /* Configure Switching Component Bandwidth Allocation per Tc
1765 struct i40e_aqc_configure_switching_comp_bw_config_data
{
1768 u8 absolute_credits
; /* bool */
1769 u8 tc_bw_share_credits
[8];
1773 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data
);
1775 /* Query Switching Component Configuration (indirect 0x0418) */
1776 struct i40e_aqc_query_switching_comp_ets_config_resp
{
1779 __le16 port_bw_limit
;
1781 u8 tc_bw_max
; /* 0-3, limit = 2^max */
1785 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp
);
1787 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1788 struct i40e_aqc_query_port_ets_config_resp
{
1792 u8 tc_strict_priority_bits
;
1794 u8 tc_bw_share_credits
[8];
1795 __le16 tc_bw_limits
[8];
1797 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1798 __le16 tc_bw_max
[2];
1802 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp
);
1804 /* Query Switching Component Bandwidth Allocation per Traffic Type
1807 struct i40e_aqc_query_switching_comp_bw_config_resp
{
1810 u8 absolute_credits_enable
; /* bool */
1811 u8 tc_bw_share_credits
[8];
1812 __le16 tc_bw_limits
[8];
1814 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1815 __le16 tc_bw_max
[2];
1818 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp
);
1820 /* Suspend/resume port TX traffic
1821 * (direct 0x041B and 0x041C) uses the generic SEID struct
1824 /* Configure partition BW
1827 struct i40e_aqc_configure_partition_bw_data
{
1828 __le16 pf_valid_bits
;
1829 u8 min_bw
[16]; /* guaranteed bandwidth */
1830 u8 max_bw
[16]; /* bandwidth limit */
1833 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data
);
1835 /* Get and set the active HMC resource profile and status.
1836 * (direct 0x0500) and (direct 0x0501)
1838 struct i40e_aq_get_set_hmc_resource_profile
{
1844 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile
);
1846 enum i40e_aq_hmc_profile
{
1847 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1848 I40E_HMC_PROFILE_DEFAULT
= 1,
1849 I40E_HMC_PROFILE_FAVOR_VF
= 2,
1850 I40E_HMC_PROFILE_EQUAL
= 3,
1853 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1855 /* set in param0 for get phy abilities to report qualified modules */
1856 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1857 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1859 enum i40e_aq_phy_type
{
1860 I40E_PHY_TYPE_SGMII
= 0x0,
1861 I40E_PHY_TYPE_1000BASE_KX
= 0x1,
1862 I40E_PHY_TYPE_10GBASE_KX4
= 0x2,
1863 I40E_PHY_TYPE_10GBASE_KR
= 0x3,
1864 I40E_PHY_TYPE_40GBASE_KR4
= 0x4,
1865 I40E_PHY_TYPE_XAUI
= 0x5,
1866 I40E_PHY_TYPE_XFI
= 0x6,
1867 I40E_PHY_TYPE_SFI
= 0x7,
1868 I40E_PHY_TYPE_XLAUI
= 0x8,
1869 I40E_PHY_TYPE_XLPPI
= 0x9,
1870 I40E_PHY_TYPE_40GBASE_CR4_CU
= 0xA,
1871 I40E_PHY_TYPE_10GBASE_CR1_CU
= 0xB,
1872 I40E_PHY_TYPE_10GBASE_AOC
= 0xC,
1873 I40E_PHY_TYPE_40GBASE_AOC
= 0xD,
1874 I40E_PHY_TYPE_UNRECOGNIZED
= 0xE,
1875 I40E_PHY_TYPE_UNSUPPORTED
= 0xF,
1876 I40E_PHY_TYPE_100BASE_TX
= 0x11,
1877 I40E_PHY_TYPE_1000BASE_T
= 0x12,
1878 I40E_PHY_TYPE_10GBASE_T
= 0x13,
1879 I40E_PHY_TYPE_10GBASE_SR
= 0x14,
1880 I40E_PHY_TYPE_10GBASE_LR
= 0x15,
1881 I40E_PHY_TYPE_10GBASE_SFPP_CU
= 0x16,
1882 I40E_PHY_TYPE_10GBASE_CR1
= 0x17,
1883 I40E_PHY_TYPE_40GBASE_CR4
= 0x18,
1884 I40E_PHY_TYPE_40GBASE_SR4
= 0x19,
1885 I40E_PHY_TYPE_40GBASE_LR4
= 0x1A,
1886 I40E_PHY_TYPE_1000BASE_SX
= 0x1B,
1887 I40E_PHY_TYPE_1000BASE_LX
= 0x1C,
1888 I40E_PHY_TYPE_1000BASE_T_OPTICAL
= 0x1D,
1889 I40E_PHY_TYPE_20GBASE_KR2
= 0x1E,
1890 I40E_PHY_TYPE_25GBASE_KR
= 0x1F,
1891 I40E_PHY_TYPE_25GBASE_CR
= 0x20,
1892 I40E_PHY_TYPE_25GBASE_SR
= 0x21,
1893 I40E_PHY_TYPE_25GBASE_LR
= 0x22,
1894 I40E_PHY_TYPE_25GBASE_AOC
= 0x23,
1895 I40E_PHY_TYPE_25GBASE_ACC
= 0x24,
1896 I40E_PHY_TYPE_2_5GBASE_T
= 0x30,
1897 I40E_PHY_TYPE_5GBASE_T
= 0x31,
1899 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP
= 0xFD,
1900 I40E_PHY_TYPE_EMPTY
= 0xFE,
1901 I40E_PHY_TYPE_DEFAULT
= 0xFF,
1904 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1905 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1906 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1907 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1908 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1909 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1910 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1911 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1912 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1913 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1914 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1915 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1916 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1917 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1918 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1919 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1920 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1921 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1922 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1923 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1924 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1925 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1926 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1927 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1928 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1929 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1930 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1931 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1932 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1933 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1934 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1935 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1936 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1937 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1938 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1939 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1940 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1941 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1943 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1944 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1945 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1946 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1947 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1948 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1949 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1950 #define I40E_LINK_SPEED_5GB_SHIFT 0x7
1952 enum i40e_aq_link_speed
{
1953 I40E_LINK_SPEED_UNKNOWN
= 0,
1954 I40E_LINK_SPEED_100MB
= BIT(I40E_LINK_SPEED_100MB_SHIFT
),
1955 I40E_LINK_SPEED_1GB
= BIT(I40E_LINK_SPEED_1000MB_SHIFT
),
1956 I40E_LINK_SPEED_2_5GB
= (1 << I40E_LINK_SPEED_2_5GB_SHIFT
),
1957 I40E_LINK_SPEED_5GB
= (1 << I40E_LINK_SPEED_5GB_SHIFT
),
1958 I40E_LINK_SPEED_10GB
= BIT(I40E_LINK_SPEED_10GB_SHIFT
),
1959 I40E_LINK_SPEED_40GB
= BIT(I40E_LINK_SPEED_40GB_SHIFT
),
1960 I40E_LINK_SPEED_20GB
= BIT(I40E_LINK_SPEED_20GB_SHIFT
),
1961 I40E_LINK_SPEED_25GB
= BIT(I40E_LINK_SPEED_25GB_SHIFT
),
1964 struct i40e_aqc_module_desc
{
1972 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc
);
1974 struct i40e_aq_get_phy_abilities_resp
{
1975 __le32 phy_type
; /* bitmap using the above enum for offsets */
1976 u8 link_speed
; /* bitmap using the above enum bit patterns */
1978 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1979 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1980 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1981 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1982 #define I40E_AQ_PHY_AN_ENABLED 0x10
1983 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1984 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1985 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1986 __le16 eee_capability
;
1987 #define I40E_AQ_EEE_100BASE_TX 0x0002
1988 #define I40E_AQ_EEE_1000BASE_T 0x0004
1989 #define I40E_AQ_EEE_10GBASE_T 0x0008
1990 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1991 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1992 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1995 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1997 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1998 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1999 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
2000 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
2001 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
2002 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
2003 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40
2004 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80
2005 u8 fec_cfg_curr_mod_ext_info
;
2006 #define I40E_AQ_ENABLE_FEC_KR 0x01
2007 #define I40E_AQ_ENABLE_FEC_RS 0x02
2008 #define I40E_AQ_REQUEST_FEC_KR 0x04
2009 #define I40E_AQ_REQUEST_FEC_RS 0x08
2010 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
2012 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
2013 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
2018 u8 qualified_module_count
;
2019 #define I40E_AQ_PHY_MAX_QMS 16
2020 struct i40e_aqc_module_desc qualified_module
[I40E_AQ_PHY_MAX_QMS
];
2023 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp
);
2025 /* Set PHY Config (direct 0x0601) */
2026 struct i40e_aq_set_phy_config
{ /* same bits as above in all */
2030 /* bits 0-2 use the values from get_phy_abilities_resp */
2031 #define I40E_AQ_PHY_ENABLE_LINK 0x08
2032 #define I40E_AQ_PHY_ENABLE_AN 0x10
2033 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
2034 __le16 eee_capability
;
2038 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
2039 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
2040 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
2041 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
2043 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
2044 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
2045 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
2046 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
2047 #define I40E_AQ_SET_FEC_AUTO BIT(4)
2048 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
2049 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
2053 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config
);
2055 /* Set MAC Config command data structure (direct 0x0603) */
2056 struct i40e_aq_set_mac_config
{
2057 __le16 max_frame_size
;
2059 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
2060 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
2061 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
2062 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
2063 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
2064 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
2065 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2066 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2067 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2068 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2069 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2070 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2071 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2072 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2073 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80
2074 u8 tx_timer_priority
; /* bitmap */
2075 __le16 tx_timer_value
;
2076 __le16 fc_refresh_threshold
;
2080 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config
);
2082 /* Restart Auto-Negotiation (direct 0x605) */
2083 struct i40e_aqc_set_link_restart_an
{
2085 #define I40E_AQ_PHY_RESTART_AN 0x02
2086 #define I40E_AQ_PHY_LINK_ENABLE 0x04
2090 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an
);
2092 /* Get Link Status cmd & response data structure (direct 0x0607) */
2093 struct i40e_aqc_get_link_status
{
2094 __le16 command_flags
; /* only field set on command */
2095 #define I40E_AQ_LSE_MASK 0x3
2096 #define I40E_AQ_LSE_NOP 0x0
2097 #define I40E_AQ_LSE_DISABLE 0x2
2098 #define I40E_AQ_LSE_ENABLE 0x3
2099 /* only response uses this flag */
2100 #define I40E_AQ_LSE_IS_ENABLED 0x1
2101 u8 phy_type
; /* i40e_aq_phy_type */
2102 u8 link_speed
; /* i40e_aq_link_speed */
2104 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
2105 #define I40E_AQ_LINK_UP_FUNCTION 0x01
2106 #define I40E_AQ_LINK_FAULT 0x02
2107 #define I40E_AQ_LINK_FAULT_TX 0x04
2108 #define I40E_AQ_LINK_FAULT_RX 0x08
2109 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
2110 #define I40E_AQ_LINK_UP_PORT 0x20
2111 #define I40E_AQ_MEDIA_AVAILABLE 0x40
2112 #define I40E_AQ_SIGNAL_DETECT 0x80
2114 #define I40E_AQ_AN_COMPLETED 0x01
2115 #define I40E_AQ_LP_AN_ABILITY 0x02
2116 #define I40E_AQ_PD_FAULT 0x04
2117 #define I40E_AQ_FEC_EN 0x08
2118 #define I40E_AQ_PHY_LOW_POWER 0x10
2119 #define I40E_AQ_LINK_PAUSE_TX 0x20
2120 #define I40E_AQ_LINK_PAUSE_RX 0x40
2121 #define I40E_AQ_QUALIFIED_MODULE 0x80
2123 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2124 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2125 #define I40E_AQ_LINK_TX_SHIFT 0x02
2126 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2127 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2128 #define I40E_AQ_LINK_TX_DRAINED 0x01
2129 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2130 #define I40E_AQ_LINK_FORCED_40G 0x10
2131 /* 25G Error Codes */
2132 #define I40E_AQ_25G_NO_ERR 0X00
2133 #define I40E_AQ_25G_NOT_PRESENT 0X01
2134 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2135 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2136 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2137 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2138 u8 loopback
; /* use defines from i40e_aqc_set_lb_mode */
2139 /* Since firmware API 1.7 loopback field keeps power class info as well */
2140 #define I40E_AQ_LOOPBACK_MASK 0x07
2141 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2142 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2143 __le16 max_frame_size
;
2145 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2146 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2147 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2148 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2152 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2153 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2154 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2155 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2156 #define I40E_AQ_PWR_CLASS_MASK 0x03
2166 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status
);
2168 /* Set event mask command (direct 0x613) */
2169 struct i40e_aqc_set_phy_int_mask
{
2172 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2173 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2174 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2175 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2176 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2177 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2178 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2179 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2180 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2184 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask
);
2186 /* Get Local AN advt register (direct 0x0614)
2187 * Set Local AN advt register (direct 0x0615)
2188 * Get Link Partner AN advt register (direct 0x0616)
2190 struct i40e_aqc_an_advt_reg
{
2191 __le32 local_an_reg0
;
2192 __le16 local_an_reg1
;
2196 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg
);
2198 /* Set Loopback mode (0x0618) */
2199 struct i40e_aqc_set_lb_mode
{
2201 #define I40E_AQ_LB_PHY_LOCAL 0x01
2202 #define I40E_AQ_LB_PHY_REMOTE 0x02
2203 #define I40E_AQ_LB_MAC_LOCAL 0x04
2207 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode
);
2209 /* Set PHY Debug command (0x0622) */
2210 struct i40e_aqc_set_phy_debug
{
2212 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2213 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2214 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2215 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2216 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2217 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2218 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2219 /* Disable link manageability on a single port */
2220 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2221 /* Disable link manageability on all ports */
2222 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2226 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug
);
2228 enum i40e_aq_phy_reg_type
{
2229 I40E_AQC_PHY_REG_INTERNAL
= 0x1,
2230 I40E_AQC_PHY_REG_EXERNAL_BASET
= 0x2,
2231 I40E_AQC_PHY_REG_EXERNAL_MODULE
= 0x3
2234 /* Run PHY Activity (0x0626) */
2235 struct i40e_aqc_run_phy_activity
{
2244 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity
);
2246 /* Set PHY Register command (0x0628) */
2247 /* Get PHY Register command (0x0629) */
2248 struct i40e_aqc_phy_register_access
{
2250 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2251 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2252 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2260 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access
);
2262 /* NVM Read command (indirect 0x0701)
2263 * NVM Erase commands (direct 0x0702)
2264 * NVM Update commands (indirect 0x0703)
2266 struct i40e_aqc_nvm_update
{
2268 #define I40E_AQ_NVM_LAST_CMD 0x01
2269 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
2270 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
2271 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2272 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2273 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2274 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2275 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2283 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update
);
2285 /* NVM Config Read (indirect 0x0704) */
2286 struct i40e_aqc_nvm_config_read
{
2288 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2289 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2290 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2291 __le16 element_count
;
2292 __le16 element_id
; /* Feature/field ID */
2293 __le16 element_id_msw
; /* MSWord of field ID */
2294 __le32 address_high
;
2298 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read
);
2300 /* NVM Config Write (indirect 0x0705) */
2301 struct i40e_aqc_nvm_config_write
{
2303 __le16 element_count
;
2305 __le32 address_high
;
2309 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write
);
2311 /* Used for 0x0704 as well as for 0x0705 commands */
2312 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2313 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2314 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2315 #define I40E_AQ_ANVM_FEATURE 0
2316 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT)
2317 struct i40e_aqc_nvm_config_data_feature
{
2319 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2320 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2321 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2322 __le16 feature_options
;
2323 __le16 feature_selection
;
2326 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature
);
2328 struct i40e_aqc_nvm_config_data_immediate_field
{
2331 __le16 field_options
;
2335 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field
);
2337 /* OEM Post Update (indirect 0x0720)
2338 * no command data struct used
2340 struct i40e_aqc_nvm_oem_post_update
{
2341 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2346 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update
);
2348 struct i40e_aqc_nvm_oem_post_update_buffer
{
2355 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer
);
2357 /* Thermal Sensor (indirect 0x0721)
2358 * read or set thermal sensor configs and values
2359 * takes a sensor and command specific data buffer, not detailed here
2361 struct i40e_aqc_thermal_sensor
{
2363 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2364 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2365 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2371 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor
);
2373 /* Send to PF command (indirect 0x0801) id is only used by PF
2374 * Send to VF command (indirect 0x0802) id is only used by PF
2375 * Send to Peer PF command (indirect 0x0803)
2377 struct i40e_aqc_pf_vf_message
{
2384 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message
);
2386 /* Alternate structure */
2388 /* Direct write (direct 0x0900)
2389 * Direct read (direct 0x0902)
2391 struct i40e_aqc_alternate_write
{
2398 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write
);
2400 /* Indirect write (indirect 0x0901)
2401 * Indirect read (indirect 0x0903)
2404 struct i40e_aqc_alternate_ind_write
{
2411 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write
);
2413 /* Done alternate write (direct 0x0904)
2416 struct i40e_aqc_alternate_write_done
{
2418 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2419 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2420 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2421 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2425 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done
);
2427 /* Set OEM mode (direct 0x0905) */
2428 struct i40e_aqc_alternate_set_mode
{
2430 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2431 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2435 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode
);
2437 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2439 /* async events 0x10xx */
2441 /* Lan Queue Overflow Event (direct, 0x1001) */
2442 struct i40e_aqc_lan_overflow
{
2443 __le32 prtdcb_rupto
;
2448 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow
);
2450 /* Get LLDP MIB (indirect 0x0A00) */
2451 struct i40e_aqc_lldp_get_mib
{
2454 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2455 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2456 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2457 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2458 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2459 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2460 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2461 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2462 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2463 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2464 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2472 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib
);
2474 /* Configure LLDP MIB Change Event (direct 0x0A01)
2475 * also used for the event (with type in the command field)
2477 struct i40e_aqc_lldp_update_mib
{
2479 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2480 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2486 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib
);
2488 /* Add LLDP TLV (indirect 0x0A02)
2489 * Delete LLDP TLV (indirect 0x0A04)
2491 struct i40e_aqc_lldp_add_tlv
{
2492 u8 type
; /* only nearest bridge and non-TPMR from 0x0A00 */
2500 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv
);
2502 /* Update LLDP TLV (indirect 0x0A03) */
2503 struct i40e_aqc_lldp_update_tlv
{
2504 u8 type
; /* only nearest bridge and non-TPMR from 0x0A00 */
2513 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv
);
2515 /* Stop LLDP (direct 0x0A05) */
2516 struct i40e_aqc_lldp_stop
{
2518 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2519 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2520 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
2524 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop
);
2526 /* Start LLDP (direct 0x0A06) */
2527 struct i40e_aqc_lldp_start
{
2529 #define I40E_AQ_LLDP_AGENT_START 0x1
2530 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
2534 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start
);
2536 /* Set DCB (direct 0x0303) */
2537 struct i40e_aqc_set_dcb_parameters
{
2539 #define I40E_AQ_DCB_SET_AGENT 0x1
2540 #define I40E_DCB_VALID 0x1
2545 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters
);
2547 /* Get CEE DCBX Oper Config (0x0A07)
2548 * uses the generic descriptor struct
2549 * returns below as indirect response
2552 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2553 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2554 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2555 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2556 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2557 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2559 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2560 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2561 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2562 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2563 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2564 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2565 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2566 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2567 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2568 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2569 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2570 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2572 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2573 * word boundary layout issues, which the Linux compilers silently deal
2574 * with by adding padding, making the actual struct larger than designed.
2575 * However, the FW compiler for the NIC is less lenient and complains
2576 * about the struct. Hence, the struct defined here has an extra byte in
2577 * fields reserved3 and reserved4 to directly acknowledge that padding,
2578 * and the new length is used in the length check macro.
2580 struct i40e_aqc_get_cee_dcb_cfg_v1_resp
{
2588 __le16 oper_app_prio
;
2593 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp
);
2595 struct i40e_aqc_get_cee_dcb_cfg_resp
{
2600 __le16 oper_app_prio
;
2601 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2602 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2603 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2604 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2605 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2606 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2607 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2609 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2610 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2611 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2612 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2613 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2614 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2618 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp
);
2620 /* Set Local LLDP MIB (indirect 0x0A08)
2621 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2623 struct i40e_aqc_lldp_set_local_mib
{
2624 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2625 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2626 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2627 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2628 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \
2629 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2630 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2635 __le32 address_high
;
2639 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib
);
2641 /* Stop/Start LLDP Agent (direct 0x0A09)
2642 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2644 struct i40e_aqc_lldp_stop_start_specific_agent
{
2645 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2646 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2647 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2652 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent
);
2654 /* Restore LLDP Agent factory settings (direct 0x0A0A) */
2655 struct i40e_aqc_lldp_restore
{
2657 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0
2658 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2662 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore
);
2664 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2665 struct i40e_aqc_add_udp_tunnel
{
2669 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2670 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2671 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2672 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2676 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel
);
2678 struct i40e_aqc_add_udp_tunnel_completion
{
2680 u8 filter_entry_index
;
2682 #define I40E_AQC_SINGLE_PF 0x0
2683 #define I40E_AQC_MULTIPLE_PFS 0x1
2688 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion
);
2690 /* remove UDP Tunnel command (0x0B01) */
2691 struct i40e_aqc_remove_udp_tunnel
{
2693 u8 index
; /* 0 to 15 */
2697 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel
);
2699 struct i40e_aqc_del_udp_tunnel_completion
{
2701 u8 index
; /* 0 to 15 */
2703 u8 total_filters_used
;
2707 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion
);
2709 struct i40e_aqc_get_set_rss_key
{
2710 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2711 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2712 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2713 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2720 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key
);
2722 struct i40e_aqc_get_set_rss_key_data
{
2723 u8 standard_rss_key
[0x28];
2724 u8 extended_hash_key
[0xc];
2727 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data
);
2729 struct i40e_aqc_get_set_rss_lut
{
2730 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2731 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2732 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2733 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2735 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2736 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2738 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2739 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2746 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut
);
2748 /* tunnel key structure 0x0B10 */
2750 struct i40e_aqc_tunnel_key_structure
{
2753 u8 key1_len
; /* 0 to 15 */
2754 u8 key2_len
; /* 0 to 15 */
2756 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2757 /* response flags */
2758 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2759 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2760 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2761 u8 network_key_index
;
2762 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2763 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2764 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2765 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2769 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure
);
2771 /* OEM mode commands (direct 0xFE0x) */
2772 struct i40e_aqc_oem_param_change
{
2774 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2775 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2776 #define I40E_AQ_OEM_PARAM_MAC 2
2777 __le32 param_value1
;
2778 __le16 param_value2
;
2782 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change
);
2784 struct i40e_aqc_oem_state_change
{
2786 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2787 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2791 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change
);
2793 /* Initialize OCSD (0xFE02, direct) */
2794 struct i40e_aqc_opc_oem_ocsd_initialize
{
2797 __le32 ocsd_memory_block_addr_high
;
2798 __le32 ocsd_memory_block_addr_low
;
2799 __le32 requested_update_interval
;
2802 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize
);
2804 /* Initialize OCBB (0xFE03, direct) */
2805 struct i40e_aqc_opc_oem_ocbb_initialize
{
2808 __le32 ocbb_memory_block_addr_high
;
2809 __le32 ocbb_memory_block_addr_low
;
2813 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize
);
2815 /* debug commands */
2817 /* get device id (0xFF00) uses the generic structure */
2819 /* set test more (0xFF01, internal) */
2821 struct i40e_acq_set_test_mode
{
2823 #define I40E_AQ_TEST_PARTIAL 0
2824 #define I40E_AQ_TEST_FULL 1
2825 #define I40E_AQ_TEST_NVM 2
2828 #define I40E_AQ_TEST_OPEN 0
2829 #define I40E_AQ_TEST_CLOSE 1
2830 #define I40E_AQ_TEST_INC 2
2832 __le32 address_high
;
2836 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode
);
2838 /* Debug Read Register command (0xFF03)
2839 * Debug Write Register command (0xFF04)
2841 struct i40e_aqc_debug_reg_read_write
{
2848 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write
);
2850 /* Scatter/gather Reg Read (indirect 0xFF05)
2851 * Scatter/gather Reg Write (indirect 0xFF06)
2854 /* i40e_aq_desc is used for the command */
2855 struct i40e_aqc_debug_reg_sg_element_data
{
2860 /* Debug Modify register (direct 0xFF07) */
2861 struct i40e_aqc_debug_modify_reg
{
2868 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg
);
2870 /* dump internal data (0xFF08, indirect) */
2872 #define I40E_AQ_CLUSTER_ID_AUX 0
2873 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2874 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2875 #define I40E_AQ_CLUSTER_ID_HMC 3
2876 #define I40E_AQ_CLUSTER_ID_MAC0 4
2877 #define I40E_AQ_CLUSTER_ID_MAC1 5
2878 #define I40E_AQ_CLUSTER_ID_MAC2 6
2879 #define I40E_AQ_CLUSTER_ID_MAC3 7
2880 #define I40E_AQ_CLUSTER_ID_DCB 8
2881 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2882 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2883 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2885 struct i40e_aqc_debug_dump_internals
{
2890 __le32 address_high
;
2894 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals
);
2896 struct i40e_aqc_debug_modify_internals
{
2898 u8 cluster_specific_params
[7];
2899 __le32 address_high
;
2903 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals
);
2905 #endif /* _I40E_ADMINQ_CMD_H_ */