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Merge branch 'work.uaccess-unaligned' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_adminq_cmd.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2017 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
29
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0005
38
39 struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61 };
62
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
80
81 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
92
93 /* error codes */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
118 };
119
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
122 /* aq commands */
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
127
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
131
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
134
135 /* Proxy commands */
136 i40e_aqc_opc_set_proxy_config = 0x0104,
137 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
138
139 /* LAA */
140 i40e_aqc_opc_mac_address_read = 0x0107,
141 i40e_aqc_opc_mac_address_write = 0x0108,
142
143 /* PXE */
144 i40e_aqc_opc_clear_pxe_mode = 0x0110,
145
146 /* WoL commands */
147 i40e_aqc_opc_set_wol_filter = 0x0120,
148 i40e_aqc_opc_get_wake_reason = 0x0121,
149
150 /* internal switch commands */
151 i40e_aqc_opc_get_switch_config = 0x0200,
152 i40e_aqc_opc_add_statistics = 0x0201,
153 i40e_aqc_opc_remove_statistics = 0x0202,
154 i40e_aqc_opc_set_port_parameters = 0x0203,
155 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
156 i40e_aqc_opc_set_switch_config = 0x0205,
157 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
158 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
159
160 i40e_aqc_opc_add_vsi = 0x0210,
161 i40e_aqc_opc_update_vsi_parameters = 0x0211,
162 i40e_aqc_opc_get_vsi_parameters = 0x0212,
163
164 i40e_aqc_opc_add_pv = 0x0220,
165 i40e_aqc_opc_update_pv_parameters = 0x0221,
166 i40e_aqc_opc_get_pv_parameters = 0x0222,
167
168 i40e_aqc_opc_add_veb = 0x0230,
169 i40e_aqc_opc_update_veb_parameters = 0x0231,
170 i40e_aqc_opc_get_veb_parameters = 0x0232,
171
172 i40e_aqc_opc_delete_element = 0x0243,
173
174 i40e_aqc_opc_add_macvlan = 0x0250,
175 i40e_aqc_opc_remove_macvlan = 0x0251,
176 i40e_aqc_opc_add_vlan = 0x0252,
177 i40e_aqc_opc_remove_vlan = 0x0253,
178 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
179 i40e_aqc_opc_add_tag = 0x0255,
180 i40e_aqc_opc_remove_tag = 0x0256,
181 i40e_aqc_opc_add_multicast_etag = 0x0257,
182 i40e_aqc_opc_remove_multicast_etag = 0x0258,
183 i40e_aqc_opc_update_tag = 0x0259,
184 i40e_aqc_opc_add_control_packet_filter = 0x025A,
185 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
186 i40e_aqc_opc_add_cloud_filters = 0x025C,
187 i40e_aqc_opc_remove_cloud_filters = 0x025D,
188 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
189
190 i40e_aqc_opc_add_mirror_rule = 0x0260,
191 i40e_aqc_opc_delete_mirror_rule = 0x0261,
192
193 /* Pipeline Personalization Profile */
194 i40e_aqc_opc_write_personalization_profile = 0x0270,
195 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
196
197 /* DCB commands */
198 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
199 i40e_aqc_opc_dcb_updated = 0x0302,
200
201 /* TX scheduler */
202 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
203 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
204 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
205 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
206 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
207 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
208
209 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
210 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
211 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
212 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
213 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
214 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
215 i40e_aqc_opc_query_port_ets_config = 0x0419,
216 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
217 i40e_aqc_opc_suspend_port_tx = 0x041B,
218 i40e_aqc_opc_resume_port_tx = 0x041C,
219 i40e_aqc_opc_configure_partition_bw = 0x041D,
220 /* hmc */
221 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
222 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
223
224 /* phy commands*/
225 i40e_aqc_opc_get_phy_abilities = 0x0600,
226 i40e_aqc_opc_set_phy_config = 0x0601,
227 i40e_aqc_opc_set_mac_config = 0x0603,
228 i40e_aqc_opc_set_link_restart_an = 0x0605,
229 i40e_aqc_opc_get_link_status = 0x0607,
230 i40e_aqc_opc_set_phy_int_mask = 0x0613,
231 i40e_aqc_opc_get_local_advt_reg = 0x0614,
232 i40e_aqc_opc_set_local_advt_reg = 0x0615,
233 i40e_aqc_opc_get_partner_advt = 0x0616,
234 i40e_aqc_opc_set_lb_modes = 0x0618,
235 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
236 i40e_aqc_opc_set_phy_debug = 0x0622,
237 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
238 i40e_aqc_opc_run_phy_activity = 0x0626,
239
240 /* NVM commands */
241 i40e_aqc_opc_nvm_read = 0x0701,
242 i40e_aqc_opc_nvm_erase = 0x0702,
243 i40e_aqc_opc_nvm_update = 0x0703,
244 i40e_aqc_opc_nvm_config_read = 0x0704,
245 i40e_aqc_opc_nvm_config_write = 0x0705,
246 i40e_aqc_opc_oem_post_update = 0x0720,
247 i40e_aqc_opc_thermal_sensor = 0x0721,
248
249 /* virtualization commands */
250 i40e_aqc_opc_send_msg_to_pf = 0x0801,
251 i40e_aqc_opc_send_msg_to_vf = 0x0802,
252 i40e_aqc_opc_send_msg_to_peer = 0x0803,
253
254 /* alternate structure */
255 i40e_aqc_opc_alternate_write = 0x0900,
256 i40e_aqc_opc_alternate_write_indirect = 0x0901,
257 i40e_aqc_opc_alternate_read = 0x0902,
258 i40e_aqc_opc_alternate_read_indirect = 0x0903,
259 i40e_aqc_opc_alternate_write_done = 0x0904,
260 i40e_aqc_opc_alternate_set_mode = 0x0905,
261 i40e_aqc_opc_alternate_clear_port = 0x0906,
262
263 /* LLDP commands */
264 i40e_aqc_opc_lldp_get_mib = 0x0A00,
265 i40e_aqc_opc_lldp_update_mib = 0x0A01,
266 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
267 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
268 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
269 i40e_aqc_opc_lldp_stop = 0x0A05,
270 i40e_aqc_opc_lldp_start = 0x0A06,
271 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
272 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
273 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
274
275 /* Tunnel commands */
276 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
277 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
278 i40e_aqc_opc_set_rss_key = 0x0B02,
279 i40e_aqc_opc_set_rss_lut = 0x0B03,
280 i40e_aqc_opc_get_rss_key = 0x0B04,
281 i40e_aqc_opc_get_rss_lut = 0x0B05,
282
283 /* Async Events */
284 i40e_aqc_opc_event_lan_overflow = 0x1001,
285
286 /* OEM commands */
287 i40e_aqc_opc_oem_parameter_change = 0xFE00,
288 i40e_aqc_opc_oem_device_status_change = 0xFE01,
289 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
290 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
291
292 /* debug commands */
293 i40e_aqc_opc_debug_read_reg = 0xFF03,
294 i40e_aqc_opc_debug_write_reg = 0xFF04,
295 i40e_aqc_opc_debug_modify_reg = 0xFF07,
296 i40e_aqc_opc_debug_dump_internals = 0xFF08,
297 };
298
299 /* command structures and indirect data structures */
300
301 /* Structure naming conventions:
302 * - no suffix for direct command descriptor structures
303 * - _data for indirect sent data
304 * - _resp for indirect return data (data which is both will use _data)
305 * - _completion for direct return data
306 * - _element_ for repeated elements (may also be _data or _resp)
307 *
308 * Command structures are expected to overlay the params.raw member of the basic
309 * descriptor, and as such cannot exceed 16 bytes in length.
310 */
311
312 /* This macro is used to generate a compilation error if a structure
313 * is not exactly the correct length. It gives a divide by zero error if the
314 * structure is not of the correct size, otherwise it creates an enum that is
315 * never used.
316 */
317 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
318 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
319
320 /* This macro is used extensively to ensure that command structures are 16
321 * bytes in length as they have to map to the raw array of that size.
322 */
323 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
324
325 /* internal (0x00XX) commands */
326
327 /* Get version (direct 0x0001) */
328 struct i40e_aqc_get_version {
329 __le32 rom_ver;
330 __le32 fw_build;
331 __le16 fw_major;
332 __le16 fw_minor;
333 __le16 api_major;
334 __le16 api_minor;
335 };
336
337 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
338
339 /* Send driver version (indirect 0x0002) */
340 struct i40e_aqc_driver_version {
341 u8 driver_major_ver;
342 u8 driver_minor_ver;
343 u8 driver_build_ver;
344 u8 driver_subbuild_ver;
345 u8 reserved[4];
346 __le32 address_high;
347 __le32 address_low;
348 };
349
350 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
351
352 /* Queue Shutdown (direct 0x0003) */
353 struct i40e_aqc_queue_shutdown {
354 __le32 driver_unloading;
355 #define I40E_AQ_DRIVER_UNLOADING 0x1
356 u8 reserved[12];
357 };
358
359 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
360
361 /* Set PF context (0x0004, direct) */
362 struct i40e_aqc_set_pf_context {
363 u8 pf_id;
364 u8 reserved[15];
365 };
366
367 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
368
369 /* Request resource ownership (direct 0x0008)
370 * Release resource ownership (direct 0x0009)
371 */
372 #define I40E_AQ_RESOURCE_NVM 1
373 #define I40E_AQ_RESOURCE_SDP 2
374 #define I40E_AQ_RESOURCE_ACCESS_READ 1
375 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
376 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
377 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
378
379 struct i40e_aqc_request_resource {
380 __le16 resource_id;
381 __le16 access_type;
382 __le32 timeout;
383 __le32 resource_number;
384 u8 reserved[4];
385 };
386
387 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
388
389 /* Get function capabilities (indirect 0x000A)
390 * Get device capabilities (indirect 0x000B)
391 */
392 struct i40e_aqc_list_capabilites {
393 u8 command_flags;
394 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
395 u8 pf_index;
396 u8 reserved[2];
397 __le32 count;
398 __le32 addr_high;
399 __le32 addr_low;
400 };
401
402 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
403
404 struct i40e_aqc_list_capabilities_element_resp {
405 __le16 id;
406 u8 major_rev;
407 u8 minor_rev;
408 __le32 number;
409 __le32 logical_id;
410 __le32 phys_id;
411 u8 reserved[16];
412 };
413
414 /* list of caps */
415
416 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
417 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
418 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
419 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
420 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
421 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
422 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
423 #define I40E_AQ_CAP_ID_SRIOV 0x0012
424 #define I40E_AQ_CAP_ID_VF 0x0013
425 #define I40E_AQ_CAP_ID_VMDQ 0x0014
426 #define I40E_AQ_CAP_ID_8021QBG 0x0015
427 #define I40E_AQ_CAP_ID_8021QBR 0x0016
428 #define I40E_AQ_CAP_ID_VSI 0x0017
429 #define I40E_AQ_CAP_ID_DCB 0x0018
430 #define I40E_AQ_CAP_ID_FCOE 0x0021
431 #define I40E_AQ_CAP_ID_ISCSI 0x0022
432 #define I40E_AQ_CAP_ID_RSS 0x0040
433 #define I40E_AQ_CAP_ID_RXQ 0x0041
434 #define I40E_AQ_CAP_ID_TXQ 0x0042
435 #define I40E_AQ_CAP_ID_MSIX 0x0043
436 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
437 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
438 #define I40E_AQ_CAP_ID_1588 0x0046
439 #define I40E_AQ_CAP_ID_IWARP 0x0051
440 #define I40E_AQ_CAP_ID_LED 0x0061
441 #define I40E_AQ_CAP_ID_SDP 0x0062
442 #define I40E_AQ_CAP_ID_MDIO 0x0063
443 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
444 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
445 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
446 #define I40E_AQ_CAP_ID_CEM 0x00F2
447
448 /* Set CPPM Configuration (direct 0x0103) */
449 struct i40e_aqc_cppm_configuration {
450 __le16 command_flags;
451 #define I40E_AQ_CPPM_EN_LTRC 0x0800
452 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
453 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
454 #define I40E_AQ_CPPM_EN_HPTC 0x4000
455 #define I40E_AQ_CPPM_EN_DMARC 0x8000
456 __le16 ttlx;
457 __le32 dmacr;
458 __le16 dmcth;
459 u8 hptc;
460 u8 reserved;
461 __le32 pfltrc;
462 };
463
464 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
465
466 /* Set ARP Proxy command / response (indirect 0x0104) */
467 struct i40e_aqc_arp_proxy_data {
468 __le16 command_flags;
469 #define I40E_AQ_ARP_INIT_IPV4 0x0800
470 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
471 #define I40E_AQ_ARP_ENA 0x2000
472 #define I40E_AQ_ARP_ADD_IPV4 0x4000
473 #define I40E_AQ_ARP_DEL_IPV4 0x8000
474 __le16 table_id;
475 __le32 enabled_offloads;
476 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
477 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
478 __le32 ip_addr;
479 u8 mac_addr[6];
480 u8 reserved[2];
481 };
482
483 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
484
485 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
486 struct i40e_aqc_ns_proxy_data {
487 __le16 table_idx_mac_addr_0;
488 __le16 table_idx_mac_addr_1;
489 __le16 table_idx_ipv6_0;
490 __le16 table_idx_ipv6_1;
491 __le16 control;
492 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
493 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
494 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
495 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
496 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
497 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
498 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
499 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
500 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
501 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
502 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
503 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
504 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
505 u8 mac_addr_0[6];
506 u8 mac_addr_1[6];
507 u8 local_mac_addr[6];
508 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
509 u8 ipv6_addr_1[16];
510 };
511
512 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
513
514 /* Manage LAA Command (0x0106) - obsolete */
515 struct i40e_aqc_mng_laa {
516 __le16 command_flags;
517 #define I40E_AQ_LAA_FLAG_WR 0x8000
518 u8 reserved[2];
519 __le32 sal;
520 __le16 sah;
521 u8 reserved2[6];
522 };
523
524 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
525
526 /* Manage MAC Address Read Command (indirect 0x0107) */
527 struct i40e_aqc_mac_address_read {
528 __le16 command_flags;
529 #define I40E_AQC_LAN_ADDR_VALID 0x10
530 #define I40E_AQC_SAN_ADDR_VALID 0x20
531 #define I40E_AQC_PORT_ADDR_VALID 0x40
532 #define I40E_AQC_WOL_ADDR_VALID 0x80
533 #define I40E_AQC_MC_MAG_EN_VALID 0x100
534 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
535 u8 reserved[6];
536 __le32 addr_high;
537 __le32 addr_low;
538 };
539
540 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
541
542 struct i40e_aqc_mac_address_read_data {
543 u8 pf_lan_mac[6];
544 u8 pf_san_mac[6];
545 u8 port_mac[6];
546 u8 pf_wol_mac[6];
547 };
548
549 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
550
551 /* Manage MAC Address Write Command (0x0108) */
552 struct i40e_aqc_mac_address_write {
553 __le16 command_flags;
554 #define I40E_AQC_MC_MAG_EN 0x0100
555 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
556 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
557 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
558 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
559 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
560 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
561
562 __le16 mac_sah;
563 __le32 mac_sal;
564 u8 reserved[8];
565 };
566
567 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
568
569 /* PXE commands (0x011x) */
570
571 /* Clear PXE Command and response (direct 0x0110) */
572 struct i40e_aqc_clear_pxe {
573 u8 rx_cnt;
574 u8 reserved[15];
575 };
576
577 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
578
579 /* Set WoL Filter (0x0120) */
580
581 struct i40e_aqc_set_wol_filter {
582 __le16 filter_index;
583 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
584 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
585 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
586 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
587
588 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
589 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
590 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
591 __le16 cmd_flags;
592 #define I40E_AQC_SET_WOL_FILTER 0x8000
593 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
594 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
595 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
596 __le16 valid_flags;
597 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
598 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
599 u8 reserved[2];
600 __le32 address_high;
601 __le32 address_low;
602 };
603
604 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
605
606 struct i40e_aqc_set_wol_filter_data {
607 u8 filter[128];
608 u8 mask[16];
609 };
610
611 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
612
613 /* Get Wake Reason (0x0121) */
614
615 struct i40e_aqc_get_wake_reason_completion {
616 u8 reserved_1[2];
617 __le16 wake_reason;
618 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
619 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
620 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
621 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
622 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
623 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
624 u8 reserved_2[12];
625 };
626
627 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
628
629 /* Switch configuration commands (0x02xx) */
630
631 /* Used by many indirect commands that only pass an seid and a buffer in the
632 * command
633 */
634 struct i40e_aqc_switch_seid {
635 __le16 seid;
636 u8 reserved[6];
637 __le32 addr_high;
638 __le32 addr_low;
639 };
640
641 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
642
643 /* Get Switch Configuration command (indirect 0x0200)
644 * uses i40e_aqc_switch_seid for the descriptor
645 */
646 struct i40e_aqc_get_switch_config_header_resp {
647 __le16 num_reported;
648 __le16 num_total;
649 u8 reserved[12];
650 };
651
652 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
653
654 struct i40e_aqc_switch_config_element_resp {
655 u8 element_type;
656 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
657 #define I40E_AQ_SW_ELEM_TYPE_PF 2
658 #define I40E_AQ_SW_ELEM_TYPE_VF 3
659 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
660 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
661 #define I40E_AQ_SW_ELEM_TYPE_PV 16
662 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
663 #define I40E_AQ_SW_ELEM_TYPE_PA 18
664 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
665 u8 revision;
666 #define I40E_AQ_SW_ELEM_REV_1 1
667 __le16 seid;
668 __le16 uplink_seid;
669 __le16 downlink_seid;
670 u8 reserved[3];
671 u8 connection_type;
672 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
673 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
674 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
675 __le16 scheduler_id;
676 __le16 element_info;
677 };
678
679 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
680
681 /* Get Switch Configuration (indirect 0x0200)
682 * an array of elements are returned in the response buffer
683 * the first in the array is the header, remainder are elements
684 */
685 struct i40e_aqc_get_switch_config_resp {
686 struct i40e_aqc_get_switch_config_header_resp header;
687 struct i40e_aqc_switch_config_element_resp element[1];
688 };
689
690 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
691
692 /* Add Statistics (direct 0x0201)
693 * Remove Statistics (direct 0x0202)
694 */
695 struct i40e_aqc_add_remove_statistics {
696 __le16 seid;
697 __le16 vlan;
698 __le16 stat_index;
699 u8 reserved[10];
700 };
701
702 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
703
704 /* Set Port Parameters command (direct 0x0203) */
705 struct i40e_aqc_set_port_parameters {
706 __le16 command_flags;
707 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
708 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
709 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
710 __le16 bad_frame_vsi;
711 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
712 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
713 __le16 default_seid; /* reserved for command */
714 u8 reserved[10];
715 };
716
717 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
718
719 /* Get Switch Resource Allocation (indirect 0x0204) */
720 struct i40e_aqc_get_switch_resource_alloc {
721 u8 num_entries; /* reserved for command */
722 u8 reserved[7];
723 __le32 addr_high;
724 __le32 addr_low;
725 };
726
727 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
728
729 /* expect an array of these structs in the response buffer */
730 struct i40e_aqc_switch_resource_alloc_element_resp {
731 u8 resource_type;
732 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
733 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
734 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
735 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
736 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
737 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
738 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
739 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
740 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
741 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
742 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
743 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
744 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
745 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
746 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
747 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
748 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
749 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
750 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
751 u8 reserved1;
752 __le16 guaranteed;
753 __le16 total;
754 __le16 used;
755 __le16 total_unalloced;
756 u8 reserved2[6];
757 };
758
759 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
760
761 /* Set Switch Configuration (direct 0x0205) */
762 struct i40e_aqc_set_switch_config {
763 __le16 flags;
764 /* flags used for both fields below */
765 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
766 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
767 __le16 valid_flags;
768 u8 reserved[12];
769 };
770
771 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
772
773 /* Read Receive control registers (direct 0x0206)
774 * Write Receive control registers (direct 0x0207)
775 * used for accessing Rx control registers that can be
776 * slow and need special handling when under high Rx load
777 */
778 struct i40e_aqc_rx_ctl_reg_read_write {
779 __le32 reserved1;
780 __le32 address;
781 __le32 reserved2;
782 __le32 value;
783 };
784
785 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
786
787 /* Add VSI (indirect 0x0210)
788 * this indirect command uses struct i40e_aqc_vsi_properties_data
789 * as the indirect buffer (128 bytes)
790 *
791 * Update VSI (indirect 0x211)
792 * uses the same data structure as Add VSI
793 *
794 * Get VSI (indirect 0x0212)
795 * uses the same completion and data structure as Add VSI
796 */
797 struct i40e_aqc_add_get_update_vsi {
798 __le16 uplink_seid;
799 u8 connection_type;
800 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
801 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
802 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
803 u8 reserved1;
804 u8 vf_id;
805 u8 reserved2;
806 __le16 vsi_flags;
807 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
808 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
809 #define I40E_AQ_VSI_TYPE_VF 0x0
810 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
811 #define I40E_AQ_VSI_TYPE_PF 0x2
812 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
813 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
814 __le32 addr_high;
815 __le32 addr_low;
816 };
817
818 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
819
820 struct i40e_aqc_add_get_update_vsi_completion {
821 __le16 seid;
822 __le16 vsi_number;
823 __le16 vsi_used;
824 __le16 vsi_free;
825 __le32 addr_high;
826 __le32 addr_low;
827 };
828
829 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
830
831 struct i40e_aqc_vsi_properties_data {
832 /* first 96 byte are written by SW */
833 __le16 valid_sections;
834 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
835 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
836 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
837 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
838 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
839 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
840 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
841 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
842 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
843 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
844 /* switch section */
845 __le16 switch_id; /* 12bit id combined with flags below */
846 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
847 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
848 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
849 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
850 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
851 u8 sw_reserved[2];
852 /* security section */
853 u8 sec_flags;
854 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
855 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
856 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
857 u8 sec_reserved;
858 /* VLAN section */
859 __le16 pvid; /* VLANS include priority bits */
860 __le16 fcoe_pvid;
861 u8 port_vlan_flags;
862 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
863 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
864 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
865 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
866 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
867 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
868 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
869 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
870 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
871 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
872 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
873 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
874 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
875 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
876 u8 pvlan_reserved[3];
877 /* ingress egress up sections */
878 __le32 ingress_table; /* bitmap, 3 bits per up */
879 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
880 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
881 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
882 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
883 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
884 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
885 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
886 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
887 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
888 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
889 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
890 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
891 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
892 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
893 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
894 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
895 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
896 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
897 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
898 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
899 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
900 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
901 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
902 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
903 __le32 egress_table; /* same defines as for ingress table */
904 /* cascaded PV section */
905 __le16 cas_pv_tag;
906 u8 cas_pv_flags;
907 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
908 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
909 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
910 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
911 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
912 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
913 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
914 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
915 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
916 u8 cas_pv_reserved;
917 /* queue mapping section */
918 __le16 mapping_flags;
919 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
920 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
921 __le16 queue_mapping[16];
922 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
923 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
924 __le16 tc_mapping[8];
925 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
926 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
927 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
928 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
929 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
930 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
931 /* queueing option section */
932 u8 queueing_opt_flags;
933 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
934 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
935 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
936 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
937 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
938 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
939 u8 queueing_opt_reserved[3];
940 /* scheduler section */
941 u8 up_enable_bits;
942 u8 sched_reserved;
943 /* outer up section */
944 __le32 outer_up_table; /* same structure and defines as ingress tbl */
945 u8 cmd_reserved[8];
946 /* last 32 bytes are written by FW */
947 __le16 qs_handle[8];
948 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
949 __le16 stat_counter_idx;
950 __le16 sched_id;
951 u8 resp_reserved[12];
952 };
953
954 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
955
956 /* Add Port Virtualizer (direct 0x0220)
957 * also used for update PV (direct 0x0221) but only flags are used
958 * (IS_CTRL_PORT only works on add PV)
959 */
960 struct i40e_aqc_add_update_pv {
961 __le16 command_flags;
962 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
963 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
964 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
965 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
966 __le16 uplink_seid;
967 __le16 connected_seid;
968 u8 reserved[10];
969 };
970
971 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
972
973 struct i40e_aqc_add_update_pv_completion {
974 /* reserved for update; for add also encodes error if rc == ENOSPC */
975 __le16 pv_seid;
976 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
977 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
978 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
979 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
980 u8 reserved[14];
981 };
982
983 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
984
985 /* Get PV Params (direct 0x0222)
986 * uses i40e_aqc_switch_seid for the descriptor
987 */
988
989 struct i40e_aqc_get_pv_params_completion {
990 __le16 seid;
991 __le16 default_stag;
992 __le16 pv_flags; /* same flags as add_pv */
993 #define I40E_AQC_GET_PV_PV_TYPE 0x1
994 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
995 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
996 u8 reserved[8];
997 __le16 default_port_seid;
998 };
999
1000 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1001
1002 /* Add VEB (direct 0x0230) */
1003 struct i40e_aqc_add_veb {
1004 __le16 uplink_seid;
1005 __le16 downlink_seid;
1006 __le16 veb_flags;
1007 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1008 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1009 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1010 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1011 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1012 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1013 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1014 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1015 u8 enable_tcs;
1016 u8 reserved[9];
1017 };
1018
1019 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1020
1021 struct i40e_aqc_add_veb_completion {
1022 u8 reserved[6];
1023 __le16 switch_seid;
1024 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1025 __le16 veb_seid;
1026 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1027 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1028 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1029 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1030 __le16 statistic_index;
1031 __le16 vebs_used;
1032 __le16 vebs_free;
1033 };
1034
1035 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1036
1037 /* Get VEB Parameters (direct 0x0232)
1038 * uses i40e_aqc_switch_seid for the descriptor
1039 */
1040 struct i40e_aqc_get_veb_parameters_completion {
1041 __le16 seid;
1042 __le16 switch_id;
1043 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1044 __le16 statistic_index;
1045 __le16 vebs_used;
1046 __le16 vebs_free;
1047 u8 reserved[4];
1048 };
1049
1050 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1051
1052 /* Delete Element (direct 0x0243)
1053 * uses the generic i40e_aqc_switch_seid
1054 */
1055
1056 /* Add MAC-VLAN (indirect 0x0250) */
1057
1058 /* used for the command for most vlan commands */
1059 struct i40e_aqc_macvlan {
1060 __le16 num_addresses;
1061 __le16 seid[3];
1062 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1063 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1064 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1065 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1066 __le32 addr_high;
1067 __le32 addr_low;
1068 };
1069
1070 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1071
1072 /* indirect data for command and response */
1073 struct i40e_aqc_add_macvlan_element_data {
1074 u8 mac_addr[6];
1075 __le16 vlan_tag;
1076 __le16 flags;
1077 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1078 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1079 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1080 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1081 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1082 __le16 queue_number;
1083 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1084 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1085 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1086 /* response section */
1087 u8 match_method;
1088 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1089 #define I40E_AQC_MM_HASH_MATCH 0x02
1090 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1091 u8 reserved1[3];
1092 };
1093
1094 struct i40e_aqc_add_remove_macvlan_completion {
1095 __le16 perfect_mac_used;
1096 __le16 perfect_mac_free;
1097 __le16 unicast_hash_free;
1098 __le16 multicast_hash_free;
1099 __le32 addr_high;
1100 __le32 addr_low;
1101 };
1102
1103 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1104
1105 /* Remove MAC-VLAN (indirect 0x0251)
1106 * uses i40e_aqc_macvlan for the descriptor
1107 * data points to an array of num_addresses of elements
1108 */
1109
1110 struct i40e_aqc_remove_macvlan_element_data {
1111 u8 mac_addr[6];
1112 __le16 vlan_tag;
1113 u8 flags;
1114 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1115 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1116 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1117 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1118 u8 reserved[3];
1119 /* reply section */
1120 u8 error_code;
1121 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1122 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1123 u8 reply_reserved[3];
1124 };
1125
1126 /* Add VLAN (indirect 0x0252)
1127 * Remove VLAN (indirect 0x0253)
1128 * use the generic i40e_aqc_macvlan for the command
1129 */
1130 struct i40e_aqc_add_remove_vlan_element_data {
1131 __le16 vlan_tag;
1132 u8 vlan_flags;
1133 /* flags for add VLAN */
1134 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1135 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1136 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1137 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1138 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1139 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1140 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1141 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1142 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1143 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1144 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1145 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1146 /* flags for remove VLAN */
1147 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1148 u8 reserved;
1149 u8 result;
1150 /* flags for add VLAN */
1151 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1152 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1153 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1154 /* flags for remove VLAN */
1155 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1156 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1157 u8 reserved1[3];
1158 };
1159
1160 struct i40e_aqc_add_remove_vlan_completion {
1161 u8 reserved[4];
1162 __le16 vlans_used;
1163 __le16 vlans_free;
1164 __le32 addr_high;
1165 __le32 addr_low;
1166 };
1167
1168 /* Set VSI Promiscuous Modes (direct 0x0254) */
1169 struct i40e_aqc_set_vsi_promiscuous_modes {
1170 __le16 promiscuous_flags;
1171 __le16 valid_flags;
1172 /* flags used for both fields above */
1173 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1174 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1175 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1176 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1177 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1178 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1179 __le16 seid;
1180 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1181 __le16 vlan_tag;
1182 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1183 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1184 u8 reserved[8];
1185 };
1186
1187 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1188
1189 /* Add S/E-tag command (direct 0x0255)
1190 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1191 */
1192 struct i40e_aqc_add_tag {
1193 __le16 flags;
1194 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1195 __le16 seid;
1196 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1197 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1198 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1199 __le16 tag;
1200 __le16 queue_number;
1201 u8 reserved[8];
1202 };
1203
1204 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1205
1206 struct i40e_aqc_add_remove_tag_completion {
1207 u8 reserved[12];
1208 __le16 tags_used;
1209 __le16 tags_free;
1210 };
1211
1212 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1213
1214 /* Remove S/E-tag command (direct 0x0256)
1215 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1216 */
1217 struct i40e_aqc_remove_tag {
1218 __le16 seid;
1219 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1220 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1221 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1222 __le16 tag;
1223 u8 reserved[12];
1224 };
1225
1226 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1227
1228 /* Add multicast E-Tag (direct 0x0257)
1229 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1230 * and no external data
1231 */
1232 struct i40e_aqc_add_remove_mcast_etag {
1233 __le16 pv_seid;
1234 __le16 etag;
1235 u8 num_unicast_etags;
1236 u8 reserved[3];
1237 __le32 addr_high; /* address of array of 2-byte s-tags */
1238 __le32 addr_low;
1239 };
1240
1241 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1242
1243 struct i40e_aqc_add_remove_mcast_etag_completion {
1244 u8 reserved[4];
1245 __le16 mcast_etags_used;
1246 __le16 mcast_etags_free;
1247 __le32 addr_high;
1248 __le32 addr_low;
1249
1250 };
1251
1252 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1253
1254 /* Update S/E-Tag (direct 0x0259) */
1255 struct i40e_aqc_update_tag {
1256 __le16 seid;
1257 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1258 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1259 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1260 __le16 old_tag;
1261 __le16 new_tag;
1262 u8 reserved[10];
1263 };
1264
1265 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1266
1267 struct i40e_aqc_update_tag_completion {
1268 u8 reserved[12];
1269 __le16 tags_used;
1270 __le16 tags_free;
1271 };
1272
1273 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1274
1275 /* Add Control Packet filter (direct 0x025A)
1276 * Remove Control Packet filter (direct 0x025B)
1277 * uses the i40e_aqc_add_oveb_cloud,
1278 * and the generic direct completion structure
1279 */
1280 struct i40e_aqc_add_remove_control_packet_filter {
1281 u8 mac[6];
1282 __le16 etype;
1283 __le16 flags;
1284 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1285 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1286 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1287 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1288 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1289 __le16 seid;
1290 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1291 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1292 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1293 __le16 queue;
1294 u8 reserved[2];
1295 };
1296
1297 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1298
1299 struct i40e_aqc_add_remove_control_packet_filter_completion {
1300 __le16 mac_etype_used;
1301 __le16 etype_used;
1302 __le16 mac_etype_free;
1303 __le16 etype_free;
1304 u8 reserved[8];
1305 };
1306
1307 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1308
1309 /* Add Cloud filters (indirect 0x025C)
1310 * Remove Cloud filters (indirect 0x025D)
1311 * uses the i40e_aqc_add_remove_cloud_filters,
1312 * and the generic indirect completion structure
1313 */
1314 struct i40e_aqc_add_remove_cloud_filters {
1315 u8 num_filters;
1316 u8 reserved;
1317 __le16 seid;
1318 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1319 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1320 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1321 u8 reserved2[4];
1322 __le32 addr_high;
1323 __le32 addr_low;
1324 };
1325
1326 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1327
1328 struct i40e_aqc_add_remove_cloud_filters_element_data {
1329 u8 outer_mac[6];
1330 u8 inner_mac[6];
1331 __le16 inner_vlan;
1332 union {
1333 struct {
1334 u8 reserved[12];
1335 u8 data[4];
1336 } v4;
1337 struct {
1338 u8 data[16];
1339 } v6;
1340 } ipaddr;
1341 __le16 flags;
1342 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1343 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1344 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1345 /* 0x0000 reserved */
1346 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1347 /* 0x0002 reserved */
1348 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1349 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1350 /* 0x0005 reserved */
1351 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1352 /* 0x0007 reserved */
1353 /* 0x0008 reserved */
1354 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1355 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1356 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1357 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1358
1359 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1360 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1361 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1362 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1363 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1364
1365 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1366 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1367 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1368 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1369 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1370 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1371 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1372 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1373
1374 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1375 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1376 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1377
1378 __le32 tenant_id;
1379 u8 reserved[4];
1380 __le16 queue_number;
1381 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1382 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1383 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1384 u8 reserved2[14];
1385 /* response section */
1386 u8 allocation_result;
1387 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1388 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1389 u8 response_reserved[7];
1390 };
1391
1392 struct i40e_aqc_remove_cloud_filters_completion {
1393 __le16 perfect_ovlan_used;
1394 __le16 perfect_ovlan_free;
1395 __le16 vlan_used;
1396 __le16 vlan_free;
1397 __le32 addr_high;
1398 __le32 addr_low;
1399 };
1400
1401 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1402
1403 /* Add Mirror Rule (indirect or direct 0x0260)
1404 * Delete Mirror Rule (indirect or direct 0x0261)
1405 * note: some rule types (4,5) do not use an external buffer.
1406 * take care to set the flags correctly.
1407 */
1408 struct i40e_aqc_add_delete_mirror_rule {
1409 __le16 seid;
1410 __le16 rule_type;
1411 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1412 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1413 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1414 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1415 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1416 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1417 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1418 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1419 __le16 num_entries;
1420 __le16 destination; /* VSI for add, rule id for delete */
1421 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1422 __le32 addr_low;
1423 };
1424
1425 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1426
1427 struct i40e_aqc_add_delete_mirror_rule_completion {
1428 u8 reserved[2];
1429 __le16 rule_id; /* only used on add */
1430 __le16 mirror_rules_used;
1431 __le16 mirror_rules_free;
1432 __le32 addr_high;
1433 __le32 addr_low;
1434 };
1435
1436 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1437
1438 /* Pipeline Personalization Profile */
1439 struct i40e_aqc_write_personalization_profile {
1440 u8 flags;
1441 u8 reserved[3];
1442 __le32 profile_track_id;
1443 __le32 addr_high;
1444 __le32 addr_low;
1445 };
1446
1447 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1448
1449 struct i40e_aqc_write_ppp_resp {
1450 __le32 error_offset;
1451 __le32 error_info;
1452 __le32 addr_high;
1453 __le32 addr_low;
1454 };
1455
1456 struct i40e_aqc_get_applied_profiles {
1457 u8 flags;
1458 #define I40E_AQC_GET_PPP_GET_CONF 0x1
1459 #define I40E_AQC_GET_PPP_GET_RDPU_CONF 0x2
1460 u8 rsv[3];
1461 __le32 reserved;
1462 __le32 addr_high;
1463 __le32 addr_low;
1464 };
1465
1466 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1467
1468 /* DCB 0x03xx*/
1469
1470 /* PFC Ignore (direct 0x0301)
1471 * the command and response use the same descriptor structure
1472 */
1473 struct i40e_aqc_pfc_ignore {
1474 u8 tc_bitmap;
1475 u8 command_flags; /* unused on response */
1476 #define I40E_AQC_PFC_IGNORE_SET 0x80
1477 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1478 u8 reserved[14];
1479 };
1480
1481 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1482
1483 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1484 * with no parameters
1485 */
1486
1487 /* TX scheduler 0x04xx */
1488
1489 /* Almost all the indirect commands use
1490 * this generic struct to pass the SEID in param0
1491 */
1492 struct i40e_aqc_tx_sched_ind {
1493 __le16 vsi_seid;
1494 u8 reserved[6];
1495 __le32 addr_high;
1496 __le32 addr_low;
1497 };
1498
1499 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1500
1501 /* Several commands respond with a set of queue set handles */
1502 struct i40e_aqc_qs_handles_resp {
1503 __le16 qs_handles[8];
1504 };
1505
1506 /* Configure VSI BW limits (direct 0x0400) */
1507 struct i40e_aqc_configure_vsi_bw_limit {
1508 __le16 vsi_seid;
1509 u8 reserved[2];
1510 __le16 credit;
1511 u8 reserved1[2];
1512 u8 max_credit; /* 0-3, limit = 2^max */
1513 u8 reserved2[7];
1514 };
1515
1516 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1517
1518 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1519 * responds with i40e_aqc_qs_handles_resp
1520 */
1521 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1522 u8 tc_valid_bits;
1523 u8 reserved[15];
1524 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1525
1526 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1527 __le16 tc_bw_max[2];
1528 u8 reserved1[28];
1529 };
1530
1531 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1532
1533 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1534 * responds with i40e_aqc_qs_handles_resp
1535 */
1536 struct i40e_aqc_configure_vsi_tc_bw_data {
1537 u8 tc_valid_bits;
1538 u8 reserved[3];
1539 u8 tc_bw_credits[8];
1540 u8 reserved1[4];
1541 __le16 qs_handles[8];
1542 };
1543
1544 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1545
1546 /* Query vsi bw configuration (indirect 0x0408) */
1547 struct i40e_aqc_query_vsi_bw_config_resp {
1548 u8 tc_valid_bits;
1549 u8 tc_suspended_bits;
1550 u8 reserved[14];
1551 __le16 qs_handles[8];
1552 u8 reserved1[4];
1553 __le16 port_bw_limit;
1554 u8 reserved2[2];
1555 u8 max_bw; /* 0-3, limit = 2^max */
1556 u8 reserved3[23];
1557 };
1558
1559 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1560
1561 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1562 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1563 u8 tc_valid_bits;
1564 u8 reserved[3];
1565 u8 share_credits[8];
1566 __le16 credits[8];
1567
1568 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1569 __le16 tc_bw_max[2];
1570 };
1571
1572 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1573
1574 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1575 struct i40e_aqc_configure_switching_comp_bw_limit {
1576 __le16 seid;
1577 u8 reserved[2];
1578 __le16 credit;
1579 u8 reserved1[2];
1580 u8 max_bw; /* 0-3, limit = 2^max */
1581 u8 reserved2[7];
1582 };
1583
1584 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1585
1586 /* Enable Physical Port ETS (indirect 0x0413)
1587 * Modify Physical Port ETS (indirect 0x0414)
1588 * Disable Physical Port ETS (indirect 0x0415)
1589 */
1590 struct i40e_aqc_configure_switching_comp_ets_data {
1591 u8 reserved[4];
1592 u8 tc_valid_bits;
1593 u8 seepage;
1594 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1595 u8 tc_strict_priority_flags;
1596 u8 reserved1[17];
1597 u8 tc_bw_share_credits[8];
1598 u8 reserved2[96];
1599 };
1600
1601 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1602
1603 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1604 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1605 u8 tc_valid_bits;
1606 u8 reserved[15];
1607 __le16 tc_bw_credit[8];
1608
1609 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1610 __le16 tc_bw_max[2];
1611 u8 reserved1[28];
1612 };
1613
1614 I40E_CHECK_STRUCT_LEN(0x40,
1615 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1616
1617 /* Configure Switching Component Bandwidth Allocation per Tc
1618 * (indirect 0x0417)
1619 */
1620 struct i40e_aqc_configure_switching_comp_bw_config_data {
1621 u8 tc_valid_bits;
1622 u8 reserved[2];
1623 u8 absolute_credits; /* bool */
1624 u8 tc_bw_share_credits[8];
1625 u8 reserved1[20];
1626 };
1627
1628 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1629
1630 /* Query Switching Component Configuration (indirect 0x0418) */
1631 struct i40e_aqc_query_switching_comp_ets_config_resp {
1632 u8 tc_valid_bits;
1633 u8 reserved[35];
1634 __le16 port_bw_limit;
1635 u8 reserved1[2];
1636 u8 tc_bw_max; /* 0-3, limit = 2^max */
1637 u8 reserved2[23];
1638 };
1639
1640 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1641
1642 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1643 struct i40e_aqc_query_port_ets_config_resp {
1644 u8 reserved[4];
1645 u8 tc_valid_bits;
1646 u8 reserved1;
1647 u8 tc_strict_priority_bits;
1648 u8 reserved2;
1649 u8 tc_bw_share_credits[8];
1650 __le16 tc_bw_limits[8];
1651
1652 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1653 __le16 tc_bw_max[2];
1654 u8 reserved3[32];
1655 };
1656
1657 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1658
1659 /* Query Switching Component Bandwidth Allocation per Traffic Type
1660 * (indirect 0x041A)
1661 */
1662 struct i40e_aqc_query_switching_comp_bw_config_resp {
1663 u8 tc_valid_bits;
1664 u8 reserved[2];
1665 u8 absolute_credits_enable; /* bool */
1666 u8 tc_bw_share_credits[8];
1667 __le16 tc_bw_limits[8];
1668
1669 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1670 __le16 tc_bw_max[2];
1671 };
1672
1673 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1674
1675 /* Suspend/resume port TX traffic
1676 * (direct 0x041B and 0x041C) uses the generic SEID struct
1677 */
1678
1679 /* Configure partition BW
1680 * (indirect 0x041D)
1681 */
1682 struct i40e_aqc_configure_partition_bw_data {
1683 __le16 pf_valid_bits;
1684 u8 min_bw[16]; /* guaranteed bandwidth */
1685 u8 max_bw[16]; /* bandwidth limit */
1686 };
1687
1688 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1689
1690 /* Get and set the active HMC resource profile and status.
1691 * (direct 0x0500) and (direct 0x0501)
1692 */
1693 struct i40e_aq_get_set_hmc_resource_profile {
1694 u8 pm_profile;
1695 u8 pe_vf_enabled;
1696 u8 reserved[14];
1697 };
1698
1699 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1700
1701 enum i40e_aq_hmc_profile {
1702 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1703 I40E_HMC_PROFILE_DEFAULT = 1,
1704 I40E_HMC_PROFILE_FAVOR_VF = 2,
1705 I40E_HMC_PROFILE_EQUAL = 3,
1706 };
1707
1708 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1709
1710 /* set in param0 for get phy abilities to report qualified modules */
1711 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1712 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1713
1714 enum i40e_aq_phy_type {
1715 I40E_PHY_TYPE_SGMII = 0x0,
1716 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1717 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1718 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1719 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1720 I40E_PHY_TYPE_XAUI = 0x5,
1721 I40E_PHY_TYPE_XFI = 0x6,
1722 I40E_PHY_TYPE_SFI = 0x7,
1723 I40E_PHY_TYPE_XLAUI = 0x8,
1724 I40E_PHY_TYPE_XLPPI = 0x9,
1725 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1726 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1727 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1728 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1729 I40E_PHY_TYPE_100BASE_TX = 0x11,
1730 I40E_PHY_TYPE_1000BASE_T = 0x12,
1731 I40E_PHY_TYPE_10GBASE_T = 0x13,
1732 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1733 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1734 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1735 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1736 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1737 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1738 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1739 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1740 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1741 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1742 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1743 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1744 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1745 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1746 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1747 I40E_PHY_TYPE_MAX
1748 };
1749
1750 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1751 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1752 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1753 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1754 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1755 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1756
1757 enum i40e_aq_link_speed {
1758 I40E_LINK_SPEED_UNKNOWN = 0,
1759 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1760 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1761 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1762 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1763 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1764 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1765 };
1766
1767 struct i40e_aqc_module_desc {
1768 u8 oui[3];
1769 u8 reserved1;
1770 u8 part_number[16];
1771 u8 revision[4];
1772 u8 reserved2[8];
1773 };
1774
1775 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1776
1777 struct i40e_aq_get_phy_abilities_resp {
1778 __le32 phy_type; /* bitmap using the above enum for offsets */
1779 u8 link_speed; /* bitmap using the above enum bit patterns */
1780 u8 abilities;
1781 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1782 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1783 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1784 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1785 #define I40E_AQ_PHY_AN_ENABLED 0x10
1786 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1787 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1788 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1789 __le16 eee_capability;
1790 #define I40E_AQ_EEE_100BASE_TX 0x0002
1791 #define I40E_AQ_EEE_1000BASE_T 0x0004
1792 #define I40E_AQ_EEE_10GBASE_T 0x0008
1793 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1794 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1795 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1796 __le32 eeer_val;
1797 u8 d3_lpan;
1798 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1799 u8 phy_type_ext;
1800 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1801 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1802 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1803 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1804 u8 fec_cfg_curr_mod_ext_info;
1805 #define I40E_AQ_ENABLE_FEC_KR 0x01
1806 #define I40E_AQ_ENABLE_FEC_RS 0x02
1807 #define I40E_AQ_REQUEST_FEC_KR 0x04
1808 #define I40E_AQ_REQUEST_FEC_RS 0x08
1809 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1810 #define I40E_AQ_FEC
1811 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1812 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1813
1814 u8 ext_comp_code;
1815 u8 phy_id[4];
1816 u8 module_type[3];
1817 u8 qualified_module_count;
1818 #define I40E_AQ_PHY_MAX_QMS 16
1819 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1820 };
1821
1822 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1823
1824 /* Set PHY Config (direct 0x0601) */
1825 struct i40e_aq_set_phy_config { /* same bits as above in all */
1826 __le32 phy_type;
1827 u8 link_speed;
1828 u8 abilities;
1829 /* bits 0-2 use the values from get_phy_abilities_resp */
1830 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1831 #define I40E_AQ_PHY_ENABLE_AN 0x10
1832 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1833 __le16 eee_capability;
1834 __le32 eeer;
1835 u8 low_power_ctrl;
1836 u8 phy_type_ext;
1837 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1838 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1839 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1840 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1841 u8 fec_config;
1842 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1843 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1844 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1845 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1846 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1847 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1848 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1849 u8 reserved;
1850 };
1851
1852 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1853
1854 /* Set MAC Config command data structure (direct 0x0603) */
1855 struct i40e_aq_set_mac_config {
1856 __le16 max_frame_size;
1857 u8 params;
1858 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1859 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1860 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1861 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1862 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1863 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1864 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1865 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1866 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1867 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1868 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1869 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1870 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1871 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1872 u8 tx_timer_priority; /* bitmap */
1873 __le16 tx_timer_value;
1874 __le16 fc_refresh_threshold;
1875 u8 reserved[8];
1876 };
1877
1878 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1879
1880 /* Restart Auto-Negotiation (direct 0x605) */
1881 struct i40e_aqc_set_link_restart_an {
1882 u8 command;
1883 #define I40E_AQ_PHY_RESTART_AN 0x02
1884 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1885 u8 reserved[15];
1886 };
1887
1888 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1889
1890 /* Get Link Status cmd & response data structure (direct 0x0607) */
1891 struct i40e_aqc_get_link_status {
1892 __le16 command_flags; /* only field set on command */
1893 #define I40E_AQ_LSE_MASK 0x3
1894 #define I40E_AQ_LSE_NOP 0x0
1895 #define I40E_AQ_LSE_DISABLE 0x2
1896 #define I40E_AQ_LSE_ENABLE 0x3
1897 /* only response uses this flag */
1898 #define I40E_AQ_LSE_IS_ENABLED 0x1
1899 u8 phy_type; /* i40e_aq_phy_type */
1900 u8 link_speed; /* i40e_aq_link_speed */
1901 u8 link_info;
1902 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1903 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1904 #define I40E_AQ_LINK_FAULT 0x02
1905 #define I40E_AQ_LINK_FAULT_TX 0x04
1906 #define I40E_AQ_LINK_FAULT_RX 0x08
1907 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1908 #define I40E_AQ_LINK_UP_PORT 0x20
1909 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1910 #define I40E_AQ_SIGNAL_DETECT 0x80
1911 u8 an_info;
1912 #define I40E_AQ_AN_COMPLETED 0x01
1913 #define I40E_AQ_LP_AN_ABILITY 0x02
1914 #define I40E_AQ_PD_FAULT 0x04
1915 #define I40E_AQ_FEC_EN 0x08
1916 #define I40E_AQ_PHY_LOW_POWER 0x10
1917 #define I40E_AQ_LINK_PAUSE_TX 0x20
1918 #define I40E_AQ_LINK_PAUSE_RX 0x40
1919 #define I40E_AQ_QUALIFIED_MODULE 0x80
1920 u8 ext_info;
1921 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1922 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1923 #define I40E_AQ_LINK_TX_SHIFT 0x02
1924 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1925 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1926 #define I40E_AQ_LINK_TX_DRAINED 0x01
1927 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1928 #define I40E_AQ_LINK_FORCED_40G 0x10
1929 /* 25G Error Codes */
1930 #define I40E_AQ_25G_NO_ERR 0X00
1931 #define I40E_AQ_25G_NOT_PRESENT 0X01
1932 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
1933 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1934 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1935 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1936 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1937 __le16 max_frame_size;
1938 u8 config;
1939 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1940 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1941 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1942 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1943 u8 power_desc;
1944 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1945 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1946 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1947 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1948 #define I40E_AQ_PWR_CLASS_MASK 0x03
1949 u8 reserved[4];
1950 };
1951
1952 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1953
1954 /* Set event mask command (direct 0x613) */
1955 struct i40e_aqc_set_phy_int_mask {
1956 u8 reserved[8];
1957 __le16 event_mask;
1958 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1959 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1960 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1961 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1962 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1963 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1964 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1965 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1966 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1967 u8 reserved1[6];
1968 };
1969
1970 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1971
1972 /* Get Local AN advt register (direct 0x0614)
1973 * Set Local AN advt register (direct 0x0615)
1974 * Get Link Partner AN advt register (direct 0x0616)
1975 */
1976 struct i40e_aqc_an_advt_reg {
1977 __le32 local_an_reg0;
1978 __le16 local_an_reg1;
1979 u8 reserved[10];
1980 };
1981
1982 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1983
1984 /* Set Loopback mode (0x0618) */
1985 struct i40e_aqc_set_lb_mode {
1986 __le16 lb_mode;
1987 #define I40E_AQ_LB_PHY_LOCAL 0x01
1988 #define I40E_AQ_LB_PHY_REMOTE 0x02
1989 #define I40E_AQ_LB_MAC_LOCAL 0x04
1990 u8 reserved[14];
1991 };
1992
1993 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1994
1995 /* Set PHY Debug command (0x0622) */
1996 struct i40e_aqc_set_phy_debug {
1997 u8 command_flags;
1998 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1999 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2000 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2001 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2002 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2003 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2004 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2005 /* Disable link manageability on a single port */
2006 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2007 /* Disable link manageability on all ports */
2008 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2009 u8 reserved[15];
2010 };
2011
2012 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2013
2014 enum i40e_aq_phy_reg_type {
2015 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2016 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2017 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2018 };
2019
2020 /* Run PHY Activity (0x0626) */
2021 struct i40e_aqc_run_phy_activity {
2022 __le16 activity_id;
2023 u8 flags;
2024 u8 reserved1;
2025 __le32 control;
2026 __le32 data;
2027 u8 reserved2[4];
2028 };
2029
2030 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2031
2032 /* NVM Read command (indirect 0x0701)
2033 * NVM Erase commands (direct 0x0702)
2034 * NVM Update commands (indirect 0x0703)
2035 */
2036 struct i40e_aqc_nvm_update {
2037 u8 command_flags;
2038 #define I40E_AQ_NVM_LAST_CMD 0x01
2039 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2040 u8 module_pointer;
2041 __le16 length;
2042 __le32 offset;
2043 __le32 addr_high;
2044 __le32 addr_low;
2045 };
2046
2047 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2048
2049 /* NVM Config Read (indirect 0x0704) */
2050 struct i40e_aqc_nvm_config_read {
2051 __le16 cmd_flags;
2052 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2053 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2054 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2055 __le16 element_count;
2056 __le16 element_id; /* Feature/field ID */
2057 __le16 element_id_msw; /* MSWord of field ID */
2058 __le32 address_high;
2059 __le32 address_low;
2060 };
2061
2062 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2063
2064 /* NVM Config Write (indirect 0x0705) */
2065 struct i40e_aqc_nvm_config_write {
2066 __le16 cmd_flags;
2067 __le16 element_count;
2068 u8 reserved[4];
2069 __le32 address_high;
2070 __le32 address_low;
2071 };
2072
2073 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2074
2075 /* Used for 0x0704 as well as for 0x0705 commands */
2076 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2077 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2078 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2079 #define I40E_AQ_ANVM_FEATURE 0
2080 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT)
2081 struct i40e_aqc_nvm_config_data_feature {
2082 __le16 feature_id;
2083 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2084 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2085 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2086 __le16 feature_options;
2087 __le16 feature_selection;
2088 };
2089
2090 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2091
2092 struct i40e_aqc_nvm_config_data_immediate_field {
2093 __le32 field_id;
2094 __le32 field_value;
2095 __le16 field_options;
2096 __le16 reserved;
2097 };
2098
2099 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2100
2101 /* OEM Post Update (indirect 0x0720)
2102 * no command data struct used
2103 */
2104 struct i40e_aqc_nvm_oem_post_update {
2105 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2106 u8 sel_data;
2107 u8 reserved[7];
2108 };
2109
2110 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2111
2112 struct i40e_aqc_nvm_oem_post_update_buffer {
2113 u8 str_len;
2114 u8 dev_addr;
2115 __le16 eeprom_addr;
2116 u8 data[36];
2117 };
2118
2119 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2120
2121 /* Thermal Sensor (indirect 0x0721)
2122 * read or set thermal sensor configs and values
2123 * takes a sensor and command specific data buffer, not detailed here
2124 */
2125 struct i40e_aqc_thermal_sensor {
2126 u8 sensor_action;
2127 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2128 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2129 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2130 u8 reserved[7];
2131 __le32 addr_high;
2132 __le32 addr_low;
2133 };
2134
2135 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2136
2137 /* Send to PF command (indirect 0x0801) id is only used by PF
2138 * Send to VF command (indirect 0x0802) id is only used by PF
2139 * Send to Peer PF command (indirect 0x0803)
2140 */
2141 struct i40e_aqc_pf_vf_message {
2142 __le32 id;
2143 u8 reserved[4];
2144 __le32 addr_high;
2145 __le32 addr_low;
2146 };
2147
2148 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2149
2150 /* Alternate structure */
2151
2152 /* Direct write (direct 0x0900)
2153 * Direct read (direct 0x0902)
2154 */
2155 struct i40e_aqc_alternate_write {
2156 __le32 address0;
2157 __le32 data0;
2158 __le32 address1;
2159 __le32 data1;
2160 };
2161
2162 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2163
2164 /* Indirect write (indirect 0x0901)
2165 * Indirect read (indirect 0x0903)
2166 */
2167
2168 struct i40e_aqc_alternate_ind_write {
2169 __le32 address;
2170 __le32 length;
2171 __le32 addr_high;
2172 __le32 addr_low;
2173 };
2174
2175 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2176
2177 /* Done alternate write (direct 0x0904)
2178 * uses i40e_aq_desc
2179 */
2180 struct i40e_aqc_alternate_write_done {
2181 __le16 cmd_flags;
2182 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2183 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2184 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2185 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2186 u8 reserved[14];
2187 };
2188
2189 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2190
2191 /* Set OEM mode (direct 0x0905) */
2192 struct i40e_aqc_alternate_set_mode {
2193 __le32 mode;
2194 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2195 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2196 u8 reserved[12];
2197 };
2198
2199 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2200
2201 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2202
2203 /* async events 0x10xx */
2204
2205 /* Lan Queue Overflow Event (direct, 0x1001) */
2206 struct i40e_aqc_lan_overflow {
2207 __le32 prtdcb_rupto;
2208 __le32 otx_ctl;
2209 u8 reserved[8];
2210 };
2211
2212 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2213
2214 /* Get LLDP MIB (indirect 0x0A00) */
2215 struct i40e_aqc_lldp_get_mib {
2216 u8 type;
2217 u8 reserved1;
2218 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2219 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2220 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2221 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2222 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2223 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2224 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2225 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2226 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2227 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2228 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2229 __le16 local_len;
2230 __le16 remote_len;
2231 u8 reserved2[2];
2232 __le32 addr_high;
2233 __le32 addr_low;
2234 };
2235
2236 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2237
2238 /* Configure LLDP MIB Change Event (direct 0x0A01)
2239 * also used for the event (with type in the command field)
2240 */
2241 struct i40e_aqc_lldp_update_mib {
2242 u8 command;
2243 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2244 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2245 u8 reserved[7];
2246 __le32 addr_high;
2247 __le32 addr_low;
2248 };
2249
2250 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2251
2252 /* Add LLDP TLV (indirect 0x0A02)
2253 * Delete LLDP TLV (indirect 0x0A04)
2254 */
2255 struct i40e_aqc_lldp_add_tlv {
2256 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2257 u8 reserved1[1];
2258 __le16 len;
2259 u8 reserved2[4];
2260 __le32 addr_high;
2261 __le32 addr_low;
2262 };
2263
2264 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2265
2266 /* Update LLDP TLV (indirect 0x0A03) */
2267 struct i40e_aqc_lldp_update_tlv {
2268 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2269 u8 reserved;
2270 __le16 old_len;
2271 __le16 new_offset;
2272 __le16 new_len;
2273 __le32 addr_high;
2274 __le32 addr_low;
2275 };
2276
2277 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2278
2279 /* Stop LLDP (direct 0x0A05) */
2280 struct i40e_aqc_lldp_stop {
2281 u8 command;
2282 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2283 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2284 u8 reserved[15];
2285 };
2286
2287 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2288
2289 /* Start LLDP (direct 0x0A06) */
2290
2291 struct i40e_aqc_lldp_start {
2292 u8 command;
2293 #define I40E_AQ_LLDP_AGENT_START 0x1
2294 u8 reserved[15];
2295 };
2296
2297 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2298
2299 /* Get CEE DCBX Oper Config (0x0A07)
2300 * uses the generic descriptor struct
2301 * returns below as indirect response
2302 */
2303
2304 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2305 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2306 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2307 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2308 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2309 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2310
2311 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2312 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2313 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2314 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2315 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2316 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2317 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2318 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2319 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2320 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2321 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2322 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2323
2324 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2325 * word boundary layout issues, which the Linux compilers silently deal
2326 * with by adding padding, making the actual struct larger than designed.
2327 * However, the FW compiler for the NIC is less lenient and complains
2328 * about the struct. Hence, the struct defined here has an extra byte in
2329 * fields reserved3 and reserved4 to directly acknowledge that padding,
2330 * and the new length is used in the length check macro.
2331 */
2332 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2333 u8 reserved1;
2334 u8 oper_num_tc;
2335 u8 oper_prio_tc[4];
2336 u8 reserved2;
2337 u8 oper_tc_bw[8];
2338 u8 oper_pfc_en;
2339 u8 reserved3[2];
2340 __le16 oper_app_prio;
2341 u8 reserved4[2];
2342 __le16 tlv_status;
2343 };
2344
2345 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2346
2347 struct i40e_aqc_get_cee_dcb_cfg_resp {
2348 u8 oper_num_tc;
2349 u8 oper_prio_tc[4];
2350 u8 oper_tc_bw[8];
2351 u8 oper_pfc_en;
2352 __le16 oper_app_prio;
2353 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2354 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2355 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2356 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2357 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2358 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2359 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2360 __le32 tlv_status;
2361 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2362 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2363 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2364 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2365 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2366 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2367 u8 reserved[12];
2368 };
2369
2370 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2371
2372 /* Set Local LLDP MIB (indirect 0x0A08)
2373 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2374 */
2375 struct i40e_aqc_lldp_set_local_mib {
2376 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2377 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2378 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2379 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2380 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \
2381 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2382 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2383 u8 type;
2384 u8 reserved0;
2385 __le16 length;
2386 u8 reserved1[4];
2387 __le32 address_high;
2388 __le32 address_low;
2389 };
2390
2391 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2392
2393 /* Stop/Start LLDP Agent (direct 0x0A09)
2394 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2395 */
2396 struct i40e_aqc_lldp_stop_start_specific_agent {
2397 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2398 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2399 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2400 u8 command;
2401 u8 reserved[15];
2402 };
2403
2404 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2405
2406 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2407 struct i40e_aqc_add_udp_tunnel {
2408 __le16 udp_port;
2409 u8 reserved0[3];
2410 u8 protocol_type;
2411 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2412 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2413 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2414 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2415 u8 reserved1[10];
2416 };
2417
2418 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2419
2420 struct i40e_aqc_add_udp_tunnel_completion {
2421 __le16 udp_port;
2422 u8 filter_entry_index;
2423 u8 multiple_pfs;
2424 #define I40E_AQC_SINGLE_PF 0x0
2425 #define I40E_AQC_MULTIPLE_PFS 0x1
2426 u8 total_filters;
2427 u8 reserved[11];
2428 };
2429
2430 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2431
2432 /* remove UDP Tunnel command (0x0B01) */
2433 struct i40e_aqc_remove_udp_tunnel {
2434 u8 reserved[2];
2435 u8 index; /* 0 to 15 */
2436 u8 reserved2[13];
2437 };
2438
2439 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2440
2441 struct i40e_aqc_del_udp_tunnel_completion {
2442 __le16 udp_port;
2443 u8 index; /* 0 to 15 */
2444 u8 multiple_pfs;
2445 u8 total_filters_used;
2446 u8 reserved1[11];
2447 };
2448
2449 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2450
2451 struct i40e_aqc_get_set_rss_key {
2452 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2453 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2454 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2455 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2456 __le16 vsi_id;
2457 u8 reserved[6];
2458 __le32 addr_high;
2459 __le32 addr_low;
2460 };
2461
2462 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2463
2464 struct i40e_aqc_get_set_rss_key_data {
2465 u8 standard_rss_key[0x28];
2466 u8 extended_hash_key[0xc];
2467 };
2468
2469 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2470
2471 struct i40e_aqc_get_set_rss_lut {
2472 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2473 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2474 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2475 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2476 __le16 vsi_id;
2477 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2478 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2479
2480 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2481 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2482 __le16 flags;
2483 u8 reserved[4];
2484 __le32 addr_high;
2485 __le32 addr_low;
2486 };
2487
2488 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2489
2490 /* tunnel key structure 0x0B10 */
2491
2492 struct i40e_aqc_tunnel_key_structure {
2493 u8 key1_off;
2494 u8 key2_off;
2495 u8 key1_len; /* 0 to 15 */
2496 u8 key2_len; /* 0 to 15 */
2497 u8 flags;
2498 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2499 /* response flags */
2500 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2501 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2502 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2503 u8 network_key_index;
2504 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2505 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2506 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2507 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2508 u8 reserved[10];
2509 };
2510
2511 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2512
2513 /* OEM mode commands (direct 0xFE0x) */
2514 struct i40e_aqc_oem_param_change {
2515 __le32 param_type;
2516 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2517 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2518 #define I40E_AQ_OEM_PARAM_MAC 2
2519 __le32 param_value1;
2520 __le16 param_value2;
2521 u8 reserved[6];
2522 };
2523
2524 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2525
2526 struct i40e_aqc_oem_state_change {
2527 __le32 state;
2528 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2529 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2530 u8 reserved[12];
2531 };
2532
2533 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2534
2535 /* Initialize OCSD (0xFE02, direct) */
2536 struct i40e_aqc_opc_oem_ocsd_initialize {
2537 u8 type_status;
2538 u8 reserved1[3];
2539 __le32 ocsd_memory_block_addr_high;
2540 __le32 ocsd_memory_block_addr_low;
2541 __le32 requested_update_interval;
2542 };
2543
2544 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2545
2546 /* Initialize OCBB (0xFE03, direct) */
2547 struct i40e_aqc_opc_oem_ocbb_initialize {
2548 u8 type_status;
2549 u8 reserved1[3];
2550 __le32 ocbb_memory_block_addr_high;
2551 __le32 ocbb_memory_block_addr_low;
2552 u8 reserved2[4];
2553 };
2554
2555 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2556
2557 /* debug commands */
2558
2559 /* get device id (0xFF00) uses the generic structure */
2560
2561 /* set test more (0xFF01, internal) */
2562
2563 struct i40e_acq_set_test_mode {
2564 u8 mode;
2565 #define I40E_AQ_TEST_PARTIAL 0
2566 #define I40E_AQ_TEST_FULL 1
2567 #define I40E_AQ_TEST_NVM 2
2568 u8 reserved[3];
2569 u8 command;
2570 #define I40E_AQ_TEST_OPEN 0
2571 #define I40E_AQ_TEST_CLOSE 1
2572 #define I40E_AQ_TEST_INC 2
2573 u8 reserved2[3];
2574 __le32 address_high;
2575 __le32 address_low;
2576 };
2577
2578 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2579
2580 /* Debug Read Register command (0xFF03)
2581 * Debug Write Register command (0xFF04)
2582 */
2583 struct i40e_aqc_debug_reg_read_write {
2584 __le32 reserved;
2585 __le32 address;
2586 __le32 value_high;
2587 __le32 value_low;
2588 };
2589
2590 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2591
2592 /* Scatter/gather Reg Read (indirect 0xFF05)
2593 * Scatter/gather Reg Write (indirect 0xFF06)
2594 */
2595
2596 /* i40e_aq_desc is used for the command */
2597 struct i40e_aqc_debug_reg_sg_element_data {
2598 __le32 address;
2599 __le32 value;
2600 };
2601
2602 /* Debug Modify register (direct 0xFF07) */
2603 struct i40e_aqc_debug_modify_reg {
2604 __le32 address;
2605 __le32 value;
2606 __le32 clear_mask;
2607 __le32 set_mask;
2608 };
2609
2610 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2611
2612 /* dump internal data (0xFF08, indirect) */
2613
2614 #define I40E_AQ_CLUSTER_ID_AUX 0
2615 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2616 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2617 #define I40E_AQ_CLUSTER_ID_HMC 3
2618 #define I40E_AQ_CLUSTER_ID_MAC0 4
2619 #define I40E_AQ_CLUSTER_ID_MAC1 5
2620 #define I40E_AQ_CLUSTER_ID_MAC2 6
2621 #define I40E_AQ_CLUSTER_ID_MAC3 7
2622 #define I40E_AQ_CLUSTER_ID_DCB 8
2623 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2624 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2625 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2626
2627 struct i40e_aqc_debug_dump_internals {
2628 u8 cluster_id;
2629 u8 table_id;
2630 __le16 data_size;
2631 __le32 idx;
2632 __le32 address_high;
2633 __le32 address_low;
2634 };
2635
2636 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2637
2638 struct i40e_aqc_debug_modify_internals {
2639 u8 cluster_id;
2640 u8 cluster_specific_params[7];
2641 __le32 address_high;
2642 __le32 address_low;
2643 };
2644
2645 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2646
2647 #endif /* _I40E_ADMINQ_CMD_H_ */
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