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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_adminq_cmd.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2017 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
29
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
38 #define I40E_FW_API_VERSION_MINOR_X710 0x0007
39
40 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
41 I40E_FW_API_VERSION_MINOR_X710 : \
42 I40E_FW_API_VERSION_MINOR_X722)
43
44 /* API version 1.7 implements additional link and PHY-specific APIs */
45 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
46
47 struct i40e_aq_desc {
48 __le16 flags;
49 __le16 opcode;
50 __le16 datalen;
51 __le16 retval;
52 __le32 cookie_high;
53 __le32 cookie_low;
54 union {
55 struct {
56 __le32 param0;
57 __le32 param1;
58 __le32 param2;
59 __le32 param3;
60 } internal;
61 struct {
62 __le32 param0;
63 __le32 param1;
64 __le32 addr_high;
65 __le32 addr_low;
66 } external;
67 u8 raw[16];
68 } params;
69 };
70
71 /* Flags sub-structure
72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
74 */
75
76 /* command flags and offsets*/
77 #define I40E_AQ_FLAG_DD_SHIFT 0
78 #define I40E_AQ_FLAG_CMP_SHIFT 1
79 #define I40E_AQ_FLAG_ERR_SHIFT 2
80 #define I40E_AQ_FLAG_VFE_SHIFT 3
81 #define I40E_AQ_FLAG_LB_SHIFT 9
82 #define I40E_AQ_FLAG_RD_SHIFT 10
83 #define I40E_AQ_FLAG_VFC_SHIFT 11
84 #define I40E_AQ_FLAG_BUF_SHIFT 12
85 #define I40E_AQ_FLAG_SI_SHIFT 13
86 #define I40E_AQ_FLAG_EI_SHIFT 14
87 #define I40E_AQ_FLAG_FE_SHIFT 15
88
89 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
90 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
91 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
92 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
93 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
94 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
95 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
96 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
97 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
98 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
99 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
100
101 /* error codes */
102 enum i40e_admin_queue_err {
103 I40E_AQ_RC_OK = 0, /* success */
104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
105 I40E_AQ_RC_ENOENT = 2, /* No such element */
106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
108 I40E_AQ_RC_EIO = 5, /* I/O error */
109 I40E_AQ_RC_ENXIO = 6, /* No such resource */
110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
111 I40E_AQ_RC_EAGAIN = 8, /* Try again */
112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
113 I40E_AQ_RC_EACCES = 10, /* Permission denied */
114 I40E_AQ_RC_EFAULT = 11, /* Bad address */
115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
116 I40E_AQ_RC_EEXIST = 13, /* object already exists */
117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
125 I40E_AQ_RC_EFBIG = 22, /* File too large */
126 };
127
128 /* Admin Queue command opcodes */
129 enum i40e_admin_queue_opc {
130 /* aq commands */
131 i40e_aqc_opc_get_version = 0x0001,
132 i40e_aqc_opc_driver_version = 0x0002,
133 i40e_aqc_opc_queue_shutdown = 0x0003,
134 i40e_aqc_opc_set_pf_context = 0x0004,
135
136 /* resource ownership */
137 i40e_aqc_opc_request_resource = 0x0008,
138 i40e_aqc_opc_release_resource = 0x0009,
139
140 i40e_aqc_opc_list_func_capabilities = 0x000A,
141 i40e_aqc_opc_list_dev_capabilities = 0x000B,
142
143 /* Proxy commands */
144 i40e_aqc_opc_set_proxy_config = 0x0104,
145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
146
147 /* LAA */
148 i40e_aqc_opc_mac_address_read = 0x0107,
149 i40e_aqc_opc_mac_address_write = 0x0108,
150
151 /* PXE */
152 i40e_aqc_opc_clear_pxe_mode = 0x0110,
153
154 /* WoL commands */
155 i40e_aqc_opc_set_wol_filter = 0x0120,
156 i40e_aqc_opc_get_wake_reason = 0x0121,
157
158 /* internal switch commands */
159 i40e_aqc_opc_get_switch_config = 0x0200,
160 i40e_aqc_opc_add_statistics = 0x0201,
161 i40e_aqc_opc_remove_statistics = 0x0202,
162 i40e_aqc_opc_set_port_parameters = 0x0203,
163 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
164 i40e_aqc_opc_set_switch_config = 0x0205,
165 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
166 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
167
168 i40e_aqc_opc_add_vsi = 0x0210,
169 i40e_aqc_opc_update_vsi_parameters = 0x0211,
170 i40e_aqc_opc_get_vsi_parameters = 0x0212,
171
172 i40e_aqc_opc_add_pv = 0x0220,
173 i40e_aqc_opc_update_pv_parameters = 0x0221,
174 i40e_aqc_opc_get_pv_parameters = 0x0222,
175
176 i40e_aqc_opc_add_veb = 0x0230,
177 i40e_aqc_opc_update_veb_parameters = 0x0231,
178 i40e_aqc_opc_get_veb_parameters = 0x0232,
179
180 i40e_aqc_opc_delete_element = 0x0243,
181
182 i40e_aqc_opc_add_macvlan = 0x0250,
183 i40e_aqc_opc_remove_macvlan = 0x0251,
184 i40e_aqc_opc_add_vlan = 0x0252,
185 i40e_aqc_opc_remove_vlan = 0x0253,
186 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
187 i40e_aqc_opc_add_tag = 0x0255,
188 i40e_aqc_opc_remove_tag = 0x0256,
189 i40e_aqc_opc_add_multicast_etag = 0x0257,
190 i40e_aqc_opc_remove_multicast_etag = 0x0258,
191 i40e_aqc_opc_update_tag = 0x0259,
192 i40e_aqc_opc_add_control_packet_filter = 0x025A,
193 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
194 i40e_aqc_opc_add_cloud_filters = 0x025C,
195 i40e_aqc_opc_remove_cloud_filters = 0x025D,
196 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
197
198 i40e_aqc_opc_add_mirror_rule = 0x0260,
199 i40e_aqc_opc_delete_mirror_rule = 0x0261,
200
201 /* Pipeline Personalization Profile */
202 i40e_aqc_opc_write_personalization_profile = 0x0270,
203 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
204
205 /* DCB commands */
206 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
207 i40e_aqc_opc_dcb_updated = 0x0302,
208
209 /* TX scheduler */
210 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
211 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
212 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
213 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
214 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
215 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
216
217 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
218 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
219 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
220 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
221 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
222 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
223 i40e_aqc_opc_query_port_ets_config = 0x0419,
224 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
225 i40e_aqc_opc_suspend_port_tx = 0x041B,
226 i40e_aqc_opc_resume_port_tx = 0x041C,
227 i40e_aqc_opc_configure_partition_bw = 0x041D,
228 /* hmc */
229 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
230 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
231
232 /* phy commands*/
233 i40e_aqc_opc_get_phy_abilities = 0x0600,
234 i40e_aqc_opc_set_phy_config = 0x0601,
235 i40e_aqc_opc_set_mac_config = 0x0603,
236 i40e_aqc_opc_set_link_restart_an = 0x0605,
237 i40e_aqc_opc_get_link_status = 0x0607,
238 i40e_aqc_opc_set_phy_int_mask = 0x0613,
239 i40e_aqc_opc_get_local_advt_reg = 0x0614,
240 i40e_aqc_opc_set_local_advt_reg = 0x0615,
241 i40e_aqc_opc_get_partner_advt = 0x0616,
242 i40e_aqc_opc_set_lb_modes = 0x0618,
243 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
244 i40e_aqc_opc_set_phy_debug = 0x0622,
245 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
246 i40e_aqc_opc_run_phy_activity = 0x0626,
247 i40e_aqc_opc_set_phy_register = 0x0628,
248 i40e_aqc_opc_get_phy_register = 0x0629,
249
250 /* NVM commands */
251 i40e_aqc_opc_nvm_read = 0x0701,
252 i40e_aqc_opc_nvm_erase = 0x0702,
253 i40e_aqc_opc_nvm_update = 0x0703,
254 i40e_aqc_opc_nvm_config_read = 0x0704,
255 i40e_aqc_opc_nvm_config_write = 0x0705,
256 i40e_aqc_opc_oem_post_update = 0x0720,
257 i40e_aqc_opc_thermal_sensor = 0x0721,
258
259 /* virtualization commands */
260 i40e_aqc_opc_send_msg_to_pf = 0x0801,
261 i40e_aqc_opc_send_msg_to_vf = 0x0802,
262 i40e_aqc_opc_send_msg_to_peer = 0x0803,
263
264 /* alternate structure */
265 i40e_aqc_opc_alternate_write = 0x0900,
266 i40e_aqc_opc_alternate_write_indirect = 0x0901,
267 i40e_aqc_opc_alternate_read = 0x0902,
268 i40e_aqc_opc_alternate_read_indirect = 0x0903,
269 i40e_aqc_opc_alternate_write_done = 0x0904,
270 i40e_aqc_opc_alternate_set_mode = 0x0905,
271 i40e_aqc_opc_alternate_clear_port = 0x0906,
272
273 /* LLDP commands */
274 i40e_aqc_opc_lldp_get_mib = 0x0A00,
275 i40e_aqc_opc_lldp_update_mib = 0x0A01,
276 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
277 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
278 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
279 i40e_aqc_opc_lldp_stop = 0x0A05,
280 i40e_aqc_opc_lldp_start = 0x0A06,
281 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
282 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
283 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
284
285 /* Tunnel commands */
286 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
287 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
288 i40e_aqc_opc_set_rss_key = 0x0B02,
289 i40e_aqc_opc_set_rss_lut = 0x0B03,
290 i40e_aqc_opc_get_rss_key = 0x0B04,
291 i40e_aqc_opc_get_rss_lut = 0x0B05,
292
293 /* Async Events */
294 i40e_aqc_opc_event_lan_overflow = 0x1001,
295
296 /* OEM commands */
297 i40e_aqc_opc_oem_parameter_change = 0xFE00,
298 i40e_aqc_opc_oem_device_status_change = 0xFE01,
299 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
300 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
301
302 /* debug commands */
303 i40e_aqc_opc_debug_read_reg = 0xFF03,
304 i40e_aqc_opc_debug_write_reg = 0xFF04,
305 i40e_aqc_opc_debug_modify_reg = 0xFF07,
306 i40e_aqc_opc_debug_dump_internals = 0xFF08,
307 };
308
309 /* command structures and indirect data structures */
310
311 /* Structure naming conventions:
312 * - no suffix for direct command descriptor structures
313 * - _data for indirect sent data
314 * - _resp for indirect return data (data which is both will use _data)
315 * - _completion for direct return data
316 * - _element_ for repeated elements (may also be _data or _resp)
317 *
318 * Command structures are expected to overlay the params.raw member of the basic
319 * descriptor, and as such cannot exceed 16 bytes in length.
320 */
321
322 /* This macro is used to generate a compilation error if a structure
323 * is not exactly the correct length. It gives a divide by zero error if the
324 * structure is not of the correct size, otherwise it creates an enum that is
325 * never used.
326 */
327 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
328 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
329
330 /* This macro is used extensively to ensure that command structures are 16
331 * bytes in length as they have to map to the raw array of that size.
332 */
333 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
334
335 /* internal (0x00XX) commands */
336
337 /* Get version (direct 0x0001) */
338 struct i40e_aqc_get_version {
339 __le32 rom_ver;
340 __le32 fw_build;
341 __le16 fw_major;
342 __le16 fw_minor;
343 __le16 api_major;
344 __le16 api_minor;
345 };
346
347 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
348
349 /* Send driver version (indirect 0x0002) */
350 struct i40e_aqc_driver_version {
351 u8 driver_major_ver;
352 u8 driver_minor_ver;
353 u8 driver_build_ver;
354 u8 driver_subbuild_ver;
355 u8 reserved[4];
356 __le32 address_high;
357 __le32 address_low;
358 };
359
360 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
361
362 /* Queue Shutdown (direct 0x0003) */
363 struct i40e_aqc_queue_shutdown {
364 __le32 driver_unloading;
365 #define I40E_AQ_DRIVER_UNLOADING 0x1
366 u8 reserved[12];
367 };
368
369 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
370
371 /* Set PF context (0x0004, direct) */
372 struct i40e_aqc_set_pf_context {
373 u8 pf_id;
374 u8 reserved[15];
375 };
376
377 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
378
379 /* Request resource ownership (direct 0x0008)
380 * Release resource ownership (direct 0x0009)
381 */
382 #define I40E_AQ_RESOURCE_NVM 1
383 #define I40E_AQ_RESOURCE_SDP 2
384 #define I40E_AQ_RESOURCE_ACCESS_READ 1
385 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
386 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
387 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
388
389 struct i40e_aqc_request_resource {
390 __le16 resource_id;
391 __le16 access_type;
392 __le32 timeout;
393 __le32 resource_number;
394 u8 reserved[4];
395 };
396
397 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
398
399 /* Get function capabilities (indirect 0x000A)
400 * Get device capabilities (indirect 0x000B)
401 */
402 struct i40e_aqc_list_capabilites {
403 u8 command_flags;
404 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
405 u8 pf_index;
406 u8 reserved[2];
407 __le32 count;
408 __le32 addr_high;
409 __le32 addr_low;
410 };
411
412 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
413
414 struct i40e_aqc_list_capabilities_element_resp {
415 __le16 id;
416 u8 major_rev;
417 u8 minor_rev;
418 __le32 number;
419 __le32 logical_id;
420 __le32 phys_id;
421 u8 reserved[16];
422 };
423
424 /* list of caps */
425
426 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
427 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
428 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
429 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
430 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
431 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
432 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
433 #define I40E_AQ_CAP_ID_SRIOV 0x0012
434 #define I40E_AQ_CAP_ID_VF 0x0013
435 #define I40E_AQ_CAP_ID_VMDQ 0x0014
436 #define I40E_AQ_CAP_ID_8021QBG 0x0015
437 #define I40E_AQ_CAP_ID_8021QBR 0x0016
438 #define I40E_AQ_CAP_ID_VSI 0x0017
439 #define I40E_AQ_CAP_ID_DCB 0x0018
440 #define I40E_AQ_CAP_ID_FCOE 0x0021
441 #define I40E_AQ_CAP_ID_ISCSI 0x0022
442 #define I40E_AQ_CAP_ID_RSS 0x0040
443 #define I40E_AQ_CAP_ID_RXQ 0x0041
444 #define I40E_AQ_CAP_ID_TXQ 0x0042
445 #define I40E_AQ_CAP_ID_MSIX 0x0043
446 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
447 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
448 #define I40E_AQ_CAP_ID_1588 0x0046
449 #define I40E_AQ_CAP_ID_IWARP 0x0051
450 #define I40E_AQ_CAP_ID_LED 0x0061
451 #define I40E_AQ_CAP_ID_SDP 0x0062
452 #define I40E_AQ_CAP_ID_MDIO 0x0063
453 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
454 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
455 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
456 #define I40E_AQ_CAP_ID_CEM 0x00F2
457
458 /* Set CPPM Configuration (direct 0x0103) */
459 struct i40e_aqc_cppm_configuration {
460 __le16 command_flags;
461 #define I40E_AQ_CPPM_EN_LTRC 0x0800
462 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
463 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
464 #define I40E_AQ_CPPM_EN_HPTC 0x4000
465 #define I40E_AQ_CPPM_EN_DMARC 0x8000
466 __le16 ttlx;
467 __le32 dmacr;
468 __le16 dmcth;
469 u8 hptc;
470 u8 reserved;
471 __le32 pfltrc;
472 };
473
474 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
475
476 /* Set ARP Proxy command / response (indirect 0x0104) */
477 struct i40e_aqc_arp_proxy_data {
478 __le16 command_flags;
479 #define I40E_AQ_ARP_INIT_IPV4 0x0800
480 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
481 #define I40E_AQ_ARP_ENA 0x2000
482 #define I40E_AQ_ARP_ADD_IPV4 0x4000
483 #define I40E_AQ_ARP_DEL_IPV4 0x8000
484 __le16 table_id;
485 __le32 enabled_offloads;
486 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
487 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
488 __le32 ip_addr;
489 u8 mac_addr[6];
490 u8 reserved[2];
491 };
492
493 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
494
495 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
496 struct i40e_aqc_ns_proxy_data {
497 __le16 table_idx_mac_addr_0;
498 __le16 table_idx_mac_addr_1;
499 __le16 table_idx_ipv6_0;
500 __le16 table_idx_ipv6_1;
501 __le16 control;
502 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
503 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
504 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
505 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
506 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
507 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
508 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
509 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
510 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
511 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
512 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
513 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
514 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
515 u8 mac_addr_0[6];
516 u8 mac_addr_1[6];
517 u8 local_mac_addr[6];
518 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
519 u8 ipv6_addr_1[16];
520 };
521
522 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
523
524 /* Manage LAA Command (0x0106) - obsolete */
525 struct i40e_aqc_mng_laa {
526 __le16 command_flags;
527 #define I40E_AQ_LAA_FLAG_WR 0x8000
528 u8 reserved[2];
529 __le32 sal;
530 __le16 sah;
531 u8 reserved2[6];
532 };
533
534 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
535
536 /* Manage MAC Address Read Command (indirect 0x0107) */
537 struct i40e_aqc_mac_address_read {
538 __le16 command_flags;
539 #define I40E_AQC_LAN_ADDR_VALID 0x10
540 #define I40E_AQC_SAN_ADDR_VALID 0x20
541 #define I40E_AQC_PORT_ADDR_VALID 0x40
542 #define I40E_AQC_WOL_ADDR_VALID 0x80
543 #define I40E_AQC_MC_MAG_EN_VALID 0x100
544 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
545 u8 reserved[6];
546 __le32 addr_high;
547 __le32 addr_low;
548 };
549
550 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
551
552 struct i40e_aqc_mac_address_read_data {
553 u8 pf_lan_mac[6];
554 u8 pf_san_mac[6];
555 u8 port_mac[6];
556 u8 pf_wol_mac[6];
557 };
558
559 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
560
561 /* Manage MAC Address Write Command (0x0108) */
562 struct i40e_aqc_mac_address_write {
563 __le16 command_flags;
564 #define I40E_AQC_MC_MAG_EN 0x0100
565 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
566 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
567 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
568 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
569 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
570 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
571
572 __le16 mac_sah;
573 __le32 mac_sal;
574 u8 reserved[8];
575 };
576
577 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
578
579 /* PXE commands (0x011x) */
580
581 /* Clear PXE Command and response (direct 0x0110) */
582 struct i40e_aqc_clear_pxe {
583 u8 rx_cnt;
584 u8 reserved[15];
585 };
586
587 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
588
589 /* Set WoL Filter (0x0120) */
590
591 struct i40e_aqc_set_wol_filter {
592 __le16 filter_index;
593 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
594 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
595 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
596 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
597
598 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
599 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
600 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
601 __le16 cmd_flags;
602 #define I40E_AQC_SET_WOL_FILTER 0x8000
603 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
604 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
605 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
606 __le16 valid_flags;
607 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
608 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
609 u8 reserved[2];
610 __le32 address_high;
611 __le32 address_low;
612 };
613
614 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
615
616 struct i40e_aqc_set_wol_filter_data {
617 u8 filter[128];
618 u8 mask[16];
619 };
620
621 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
622
623 /* Get Wake Reason (0x0121) */
624
625 struct i40e_aqc_get_wake_reason_completion {
626 u8 reserved_1[2];
627 __le16 wake_reason;
628 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
629 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
630 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
631 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
632 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
633 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
634 u8 reserved_2[12];
635 };
636
637 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
638
639 /* Switch configuration commands (0x02xx) */
640
641 /* Used by many indirect commands that only pass an seid and a buffer in the
642 * command
643 */
644 struct i40e_aqc_switch_seid {
645 __le16 seid;
646 u8 reserved[6];
647 __le32 addr_high;
648 __le32 addr_low;
649 };
650
651 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
652
653 /* Get Switch Configuration command (indirect 0x0200)
654 * uses i40e_aqc_switch_seid for the descriptor
655 */
656 struct i40e_aqc_get_switch_config_header_resp {
657 __le16 num_reported;
658 __le16 num_total;
659 u8 reserved[12];
660 };
661
662 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
663
664 struct i40e_aqc_switch_config_element_resp {
665 u8 element_type;
666 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
667 #define I40E_AQ_SW_ELEM_TYPE_PF 2
668 #define I40E_AQ_SW_ELEM_TYPE_VF 3
669 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
670 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
671 #define I40E_AQ_SW_ELEM_TYPE_PV 16
672 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
673 #define I40E_AQ_SW_ELEM_TYPE_PA 18
674 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
675 u8 revision;
676 #define I40E_AQ_SW_ELEM_REV_1 1
677 __le16 seid;
678 __le16 uplink_seid;
679 __le16 downlink_seid;
680 u8 reserved[3];
681 u8 connection_type;
682 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
683 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
684 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
685 __le16 scheduler_id;
686 __le16 element_info;
687 };
688
689 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
690
691 /* Get Switch Configuration (indirect 0x0200)
692 * an array of elements are returned in the response buffer
693 * the first in the array is the header, remainder are elements
694 */
695 struct i40e_aqc_get_switch_config_resp {
696 struct i40e_aqc_get_switch_config_header_resp header;
697 struct i40e_aqc_switch_config_element_resp element[1];
698 };
699
700 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
701
702 /* Add Statistics (direct 0x0201)
703 * Remove Statistics (direct 0x0202)
704 */
705 struct i40e_aqc_add_remove_statistics {
706 __le16 seid;
707 __le16 vlan;
708 __le16 stat_index;
709 u8 reserved[10];
710 };
711
712 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
713
714 /* Set Port Parameters command (direct 0x0203) */
715 struct i40e_aqc_set_port_parameters {
716 __le16 command_flags;
717 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
718 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
719 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
720 __le16 bad_frame_vsi;
721 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
722 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
723 __le16 default_seid; /* reserved for command */
724 u8 reserved[10];
725 };
726
727 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
728
729 /* Get Switch Resource Allocation (indirect 0x0204) */
730 struct i40e_aqc_get_switch_resource_alloc {
731 u8 num_entries; /* reserved for command */
732 u8 reserved[7];
733 __le32 addr_high;
734 __le32 addr_low;
735 };
736
737 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
738
739 /* expect an array of these structs in the response buffer */
740 struct i40e_aqc_switch_resource_alloc_element_resp {
741 u8 resource_type;
742 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
743 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
744 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
745 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
746 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
747 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
748 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
749 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
750 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
751 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
752 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
753 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
754 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
755 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
756 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
757 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
758 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
759 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
760 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
761 u8 reserved1;
762 __le16 guaranteed;
763 __le16 total;
764 __le16 used;
765 __le16 total_unalloced;
766 u8 reserved2[6];
767 };
768
769 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
770
771 /* Set Switch Configuration (direct 0x0205) */
772 struct i40e_aqc_set_switch_config {
773 __le16 flags;
774 /* flags used for both fields below */
775 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
776 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
777 __le16 valid_flags;
778 u8 reserved[12];
779 };
780
781 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
782
783 /* Read Receive control registers (direct 0x0206)
784 * Write Receive control registers (direct 0x0207)
785 * used for accessing Rx control registers that can be
786 * slow and need special handling when under high Rx load
787 */
788 struct i40e_aqc_rx_ctl_reg_read_write {
789 __le32 reserved1;
790 __le32 address;
791 __le32 reserved2;
792 __le32 value;
793 };
794
795 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
796
797 /* Add VSI (indirect 0x0210)
798 * this indirect command uses struct i40e_aqc_vsi_properties_data
799 * as the indirect buffer (128 bytes)
800 *
801 * Update VSI (indirect 0x211)
802 * uses the same data structure as Add VSI
803 *
804 * Get VSI (indirect 0x0212)
805 * uses the same completion and data structure as Add VSI
806 */
807 struct i40e_aqc_add_get_update_vsi {
808 __le16 uplink_seid;
809 u8 connection_type;
810 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
811 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
812 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
813 u8 reserved1;
814 u8 vf_id;
815 u8 reserved2;
816 __le16 vsi_flags;
817 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
818 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
819 #define I40E_AQ_VSI_TYPE_VF 0x0
820 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
821 #define I40E_AQ_VSI_TYPE_PF 0x2
822 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
823 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
824 __le32 addr_high;
825 __le32 addr_low;
826 };
827
828 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
829
830 struct i40e_aqc_add_get_update_vsi_completion {
831 __le16 seid;
832 __le16 vsi_number;
833 __le16 vsi_used;
834 __le16 vsi_free;
835 __le32 addr_high;
836 __le32 addr_low;
837 };
838
839 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
840
841 struct i40e_aqc_vsi_properties_data {
842 /* first 96 byte are written by SW */
843 __le16 valid_sections;
844 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
845 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
846 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
847 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
848 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
849 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
850 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
851 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
852 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
853 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
854 /* switch section */
855 __le16 switch_id; /* 12bit id combined with flags below */
856 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
857 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
858 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
859 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
860 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
861 u8 sw_reserved[2];
862 /* security section */
863 u8 sec_flags;
864 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
865 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
866 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
867 u8 sec_reserved;
868 /* VLAN section */
869 __le16 pvid; /* VLANS include priority bits */
870 __le16 fcoe_pvid;
871 u8 port_vlan_flags;
872 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
873 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
874 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
875 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
876 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
877 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
878 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
879 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
880 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
881 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
882 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
883 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
884 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
885 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
886 u8 pvlan_reserved[3];
887 /* ingress egress up sections */
888 __le32 ingress_table; /* bitmap, 3 bits per up */
889 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
890 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
891 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
892 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
893 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
894 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
895 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
896 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
897 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
898 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
899 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
900 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
901 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
902 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
903 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
904 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
905 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
906 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
907 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
908 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
909 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
910 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
911 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
912 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
913 __le32 egress_table; /* same defines as for ingress table */
914 /* cascaded PV section */
915 __le16 cas_pv_tag;
916 u8 cas_pv_flags;
917 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
918 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
919 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
920 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
921 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
922 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
923 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
924 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
925 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
926 u8 cas_pv_reserved;
927 /* queue mapping section */
928 __le16 mapping_flags;
929 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
930 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
931 __le16 queue_mapping[16];
932 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
933 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
934 __le16 tc_mapping[8];
935 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
936 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
937 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
938 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
939 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
940 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
941 /* queueing option section */
942 u8 queueing_opt_flags;
943 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
944 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
945 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
946 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
947 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
948 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
949 u8 queueing_opt_reserved[3];
950 /* scheduler section */
951 u8 up_enable_bits;
952 u8 sched_reserved;
953 /* outer up section */
954 __le32 outer_up_table; /* same structure and defines as ingress tbl */
955 u8 cmd_reserved[8];
956 /* last 32 bytes are written by FW */
957 __le16 qs_handle[8];
958 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
959 __le16 stat_counter_idx;
960 __le16 sched_id;
961 u8 resp_reserved[12];
962 };
963
964 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
965
966 /* Add Port Virtualizer (direct 0x0220)
967 * also used for update PV (direct 0x0221) but only flags are used
968 * (IS_CTRL_PORT only works on add PV)
969 */
970 struct i40e_aqc_add_update_pv {
971 __le16 command_flags;
972 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
973 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
974 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
975 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
976 __le16 uplink_seid;
977 __le16 connected_seid;
978 u8 reserved[10];
979 };
980
981 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
982
983 struct i40e_aqc_add_update_pv_completion {
984 /* reserved for update; for add also encodes error if rc == ENOSPC */
985 __le16 pv_seid;
986 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
987 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
988 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
989 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
990 u8 reserved[14];
991 };
992
993 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
994
995 /* Get PV Params (direct 0x0222)
996 * uses i40e_aqc_switch_seid for the descriptor
997 */
998
999 struct i40e_aqc_get_pv_params_completion {
1000 __le16 seid;
1001 __le16 default_stag;
1002 __le16 pv_flags; /* same flags as add_pv */
1003 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1004 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1005 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1006 u8 reserved[8];
1007 __le16 default_port_seid;
1008 };
1009
1010 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1011
1012 /* Add VEB (direct 0x0230) */
1013 struct i40e_aqc_add_veb {
1014 __le16 uplink_seid;
1015 __le16 downlink_seid;
1016 __le16 veb_flags;
1017 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1018 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1019 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1020 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1021 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1022 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1023 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1024 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1025 u8 enable_tcs;
1026 u8 reserved[9];
1027 };
1028
1029 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1030
1031 struct i40e_aqc_add_veb_completion {
1032 u8 reserved[6];
1033 __le16 switch_seid;
1034 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1035 __le16 veb_seid;
1036 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1037 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1038 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1039 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1040 __le16 statistic_index;
1041 __le16 vebs_used;
1042 __le16 vebs_free;
1043 };
1044
1045 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1046
1047 /* Get VEB Parameters (direct 0x0232)
1048 * uses i40e_aqc_switch_seid for the descriptor
1049 */
1050 struct i40e_aqc_get_veb_parameters_completion {
1051 __le16 seid;
1052 __le16 switch_id;
1053 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1054 __le16 statistic_index;
1055 __le16 vebs_used;
1056 __le16 vebs_free;
1057 u8 reserved[4];
1058 };
1059
1060 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1061
1062 /* Delete Element (direct 0x0243)
1063 * uses the generic i40e_aqc_switch_seid
1064 */
1065
1066 /* Add MAC-VLAN (indirect 0x0250) */
1067
1068 /* used for the command for most vlan commands */
1069 struct i40e_aqc_macvlan {
1070 __le16 num_addresses;
1071 __le16 seid[3];
1072 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1073 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1074 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1075 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1076 __le32 addr_high;
1077 __le32 addr_low;
1078 };
1079
1080 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1081
1082 /* indirect data for command and response */
1083 struct i40e_aqc_add_macvlan_element_data {
1084 u8 mac_addr[6];
1085 __le16 vlan_tag;
1086 __le16 flags;
1087 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1088 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1089 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1090 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1091 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1092 __le16 queue_number;
1093 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1094 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1095 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1096 /* response section */
1097 u8 match_method;
1098 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1099 #define I40E_AQC_MM_HASH_MATCH 0x02
1100 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1101 u8 reserved1[3];
1102 };
1103
1104 struct i40e_aqc_add_remove_macvlan_completion {
1105 __le16 perfect_mac_used;
1106 __le16 perfect_mac_free;
1107 __le16 unicast_hash_free;
1108 __le16 multicast_hash_free;
1109 __le32 addr_high;
1110 __le32 addr_low;
1111 };
1112
1113 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1114
1115 /* Remove MAC-VLAN (indirect 0x0251)
1116 * uses i40e_aqc_macvlan for the descriptor
1117 * data points to an array of num_addresses of elements
1118 */
1119
1120 struct i40e_aqc_remove_macvlan_element_data {
1121 u8 mac_addr[6];
1122 __le16 vlan_tag;
1123 u8 flags;
1124 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1125 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1126 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1127 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1128 u8 reserved[3];
1129 /* reply section */
1130 u8 error_code;
1131 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1132 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1133 u8 reply_reserved[3];
1134 };
1135
1136 /* Add VLAN (indirect 0x0252)
1137 * Remove VLAN (indirect 0x0253)
1138 * use the generic i40e_aqc_macvlan for the command
1139 */
1140 struct i40e_aqc_add_remove_vlan_element_data {
1141 __le16 vlan_tag;
1142 u8 vlan_flags;
1143 /* flags for add VLAN */
1144 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1145 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1146 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1147 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1148 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1149 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1150 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1151 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1152 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1153 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1154 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1155 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1156 /* flags for remove VLAN */
1157 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1158 u8 reserved;
1159 u8 result;
1160 /* flags for add VLAN */
1161 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1162 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1163 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1164 /* flags for remove VLAN */
1165 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1166 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1167 u8 reserved1[3];
1168 };
1169
1170 struct i40e_aqc_add_remove_vlan_completion {
1171 u8 reserved[4];
1172 __le16 vlans_used;
1173 __le16 vlans_free;
1174 __le32 addr_high;
1175 __le32 addr_low;
1176 };
1177
1178 /* Set VSI Promiscuous Modes (direct 0x0254) */
1179 struct i40e_aqc_set_vsi_promiscuous_modes {
1180 __le16 promiscuous_flags;
1181 __le16 valid_flags;
1182 /* flags used for both fields above */
1183 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1184 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1185 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1186 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1187 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1188 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1189 __le16 seid;
1190 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1191 __le16 vlan_tag;
1192 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1193 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1194 u8 reserved[8];
1195 };
1196
1197 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1198
1199 /* Add S/E-tag command (direct 0x0255)
1200 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1201 */
1202 struct i40e_aqc_add_tag {
1203 __le16 flags;
1204 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1205 __le16 seid;
1206 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1207 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1208 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1209 __le16 tag;
1210 __le16 queue_number;
1211 u8 reserved[8];
1212 };
1213
1214 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1215
1216 struct i40e_aqc_add_remove_tag_completion {
1217 u8 reserved[12];
1218 __le16 tags_used;
1219 __le16 tags_free;
1220 };
1221
1222 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1223
1224 /* Remove S/E-tag command (direct 0x0256)
1225 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1226 */
1227 struct i40e_aqc_remove_tag {
1228 __le16 seid;
1229 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1230 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1231 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1232 __le16 tag;
1233 u8 reserved[12];
1234 };
1235
1236 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1237
1238 /* Add multicast E-Tag (direct 0x0257)
1239 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1240 * and no external data
1241 */
1242 struct i40e_aqc_add_remove_mcast_etag {
1243 __le16 pv_seid;
1244 __le16 etag;
1245 u8 num_unicast_etags;
1246 u8 reserved[3];
1247 __le32 addr_high; /* address of array of 2-byte s-tags */
1248 __le32 addr_low;
1249 };
1250
1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1252
1253 struct i40e_aqc_add_remove_mcast_etag_completion {
1254 u8 reserved[4];
1255 __le16 mcast_etags_used;
1256 __le16 mcast_etags_free;
1257 __le32 addr_high;
1258 __le32 addr_low;
1259
1260 };
1261
1262 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1263
1264 /* Update S/E-Tag (direct 0x0259) */
1265 struct i40e_aqc_update_tag {
1266 __le16 seid;
1267 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1268 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1269 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1270 __le16 old_tag;
1271 __le16 new_tag;
1272 u8 reserved[10];
1273 };
1274
1275 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1276
1277 struct i40e_aqc_update_tag_completion {
1278 u8 reserved[12];
1279 __le16 tags_used;
1280 __le16 tags_free;
1281 };
1282
1283 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1284
1285 /* Add Control Packet filter (direct 0x025A)
1286 * Remove Control Packet filter (direct 0x025B)
1287 * uses the i40e_aqc_add_oveb_cloud,
1288 * and the generic direct completion structure
1289 */
1290 struct i40e_aqc_add_remove_control_packet_filter {
1291 u8 mac[6];
1292 __le16 etype;
1293 __le16 flags;
1294 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1295 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1296 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1297 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1298 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1299 __le16 seid;
1300 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1301 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1302 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1303 __le16 queue;
1304 u8 reserved[2];
1305 };
1306
1307 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1308
1309 struct i40e_aqc_add_remove_control_packet_filter_completion {
1310 __le16 mac_etype_used;
1311 __le16 etype_used;
1312 __le16 mac_etype_free;
1313 __le16 etype_free;
1314 u8 reserved[8];
1315 };
1316
1317 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1318
1319 /* Add Cloud filters (indirect 0x025C)
1320 * Remove Cloud filters (indirect 0x025D)
1321 * uses the i40e_aqc_add_remove_cloud_filters,
1322 * and the generic indirect completion structure
1323 */
1324 struct i40e_aqc_add_remove_cloud_filters {
1325 u8 num_filters;
1326 u8 reserved;
1327 __le16 seid;
1328 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1329 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1330 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1331 u8 reserved2[4];
1332 __le32 addr_high;
1333 __le32 addr_low;
1334 };
1335
1336 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1337
1338 struct i40e_aqc_add_remove_cloud_filters_element_data {
1339 u8 outer_mac[6];
1340 u8 inner_mac[6];
1341 __le16 inner_vlan;
1342 union {
1343 struct {
1344 u8 reserved[12];
1345 u8 data[4];
1346 } v4;
1347 struct {
1348 u8 data[16];
1349 } v6;
1350 } ipaddr;
1351 __le16 flags;
1352 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1353 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1354 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1355 /* 0x0000 reserved */
1356 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1357 /* 0x0002 reserved */
1358 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1359 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1360 /* 0x0005 reserved */
1361 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1362 /* 0x0007 reserved */
1363 /* 0x0008 reserved */
1364 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1365 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1366 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1367 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1368
1369 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1370 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1371 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1372 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1373 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1374
1375 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1376 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1377 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1378 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1379 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1380 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1381 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1382 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1383
1384 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1385 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1386 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1387
1388 __le32 tenant_id;
1389 u8 reserved[4];
1390 __le16 queue_number;
1391 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1392 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1393 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1394 u8 reserved2[14];
1395 /* response section */
1396 u8 allocation_result;
1397 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1398 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1399 u8 response_reserved[7];
1400 };
1401
1402 struct i40e_aqc_remove_cloud_filters_completion {
1403 __le16 perfect_ovlan_used;
1404 __le16 perfect_ovlan_free;
1405 __le16 vlan_used;
1406 __le16 vlan_free;
1407 __le32 addr_high;
1408 __le32 addr_low;
1409 };
1410
1411 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1412
1413 /* Add Mirror Rule (indirect or direct 0x0260)
1414 * Delete Mirror Rule (indirect or direct 0x0261)
1415 * note: some rule types (4,5) do not use an external buffer.
1416 * take care to set the flags correctly.
1417 */
1418 struct i40e_aqc_add_delete_mirror_rule {
1419 __le16 seid;
1420 __le16 rule_type;
1421 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1422 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1423 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1424 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1425 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1426 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1427 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1428 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1429 __le16 num_entries;
1430 __le16 destination; /* VSI for add, rule id for delete */
1431 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1432 __le32 addr_low;
1433 };
1434
1435 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1436
1437 struct i40e_aqc_add_delete_mirror_rule_completion {
1438 u8 reserved[2];
1439 __le16 rule_id; /* only used on add */
1440 __le16 mirror_rules_used;
1441 __le16 mirror_rules_free;
1442 __le32 addr_high;
1443 __le32 addr_low;
1444 };
1445
1446 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1447
1448 /* Pipeline Personalization Profile */
1449 struct i40e_aqc_write_personalization_profile {
1450 u8 flags;
1451 u8 reserved[3];
1452 __le32 profile_track_id;
1453 __le32 addr_high;
1454 __le32 addr_low;
1455 };
1456
1457 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1458
1459 struct i40e_aqc_write_ppp_resp {
1460 __le32 error_offset;
1461 __le32 error_info;
1462 __le32 addr_high;
1463 __le32 addr_low;
1464 };
1465
1466 struct i40e_aqc_get_applied_profiles {
1467 u8 flags;
1468 #define I40E_AQC_GET_PPP_GET_CONF 0x1
1469 #define I40E_AQC_GET_PPP_GET_RDPU_CONF 0x2
1470 u8 rsv[3];
1471 __le32 reserved;
1472 __le32 addr_high;
1473 __le32 addr_low;
1474 };
1475
1476 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1477
1478 /* DCB 0x03xx*/
1479
1480 /* PFC Ignore (direct 0x0301)
1481 * the command and response use the same descriptor structure
1482 */
1483 struct i40e_aqc_pfc_ignore {
1484 u8 tc_bitmap;
1485 u8 command_flags; /* unused on response */
1486 #define I40E_AQC_PFC_IGNORE_SET 0x80
1487 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1488 u8 reserved[14];
1489 };
1490
1491 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1492
1493 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1494 * with no parameters
1495 */
1496
1497 /* TX scheduler 0x04xx */
1498
1499 /* Almost all the indirect commands use
1500 * this generic struct to pass the SEID in param0
1501 */
1502 struct i40e_aqc_tx_sched_ind {
1503 __le16 vsi_seid;
1504 u8 reserved[6];
1505 __le32 addr_high;
1506 __le32 addr_low;
1507 };
1508
1509 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1510
1511 /* Several commands respond with a set of queue set handles */
1512 struct i40e_aqc_qs_handles_resp {
1513 __le16 qs_handles[8];
1514 };
1515
1516 /* Configure VSI BW limits (direct 0x0400) */
1517 struct i40e_aqc_configure_vsi_bw_limit {
1518 __le16 vsi_seid;
1519 u8 reserved[2];
1520 __le16 credit;
1521 u8 reserved1[2];
1522 u8 max_credit; /* 0-3, limit = 2^max */
1523 u8 reserved2[7];
1524 };
1525
1526 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1527
1528 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1529 * responds with i40e_aqc_qs_handles_resp
1530 */
1531 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1532 u8 tc_valid_bits;
1533 u8 reserved[15];
1534 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1535
1536 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1537 __le16 tc_bw_max[2];
1538 u8 reserved1[28];
1539 };
1540
1541 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1542
1543 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1544 * responds with i40e_aqc_qs_handles_resp
1545 */
1546 struct i40e_aqc_configure_vsi_tc_bw_data {
1547 u8 tc_valid_bits;
1548 u8 reserved[3];
1549 u8 tc_bw_credits[8];
1550 u8 reserved1[4];
1551 __le16 qs_handles[8];
1552 };
1553
1554 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1555
1556 /* Query vsi bw configuration (indirect 0x0408) */
1557 struct i40e_aqc_query_vsi_bw_config_resp {
1558 u8 tc_valid_bits;
1559 u8 tc_suspended_bits;
1560 u8 reserved[14];
1561 __le16 qs_handles[8];
1562 u8 reserved1[4];
1563 __le16 port_bw_limit;
1564 u8 reserved2[2];
1565 u8 max_bw; /* 0-3, limit = 2^max */
1566 u8 reserved3[23];
1567 };
1568
1569 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1570
1571 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1572 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1573 u8 tc_valid_bits;
1574 u8 reserved[3];
1575 u8 share_credits[8];
1576 __le16 credits[8];
1577
1578 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1579 __le16 tc_bw_max[2];
1580 };
1581
1582 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1583
1584 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1585 struct i40e_aqc_configure_switching_comp_bw_limit {
1586 __le16 seid;
1587 u8 reserved[2];
1588 __le16 credit;
1589 u8 reserved1[2];
1590 u8 max_bw; /* 0-3, limit = 2^max */
1591 u8 reserved2[7];
1592 };
1593
1594 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1595
1596 /* Enable Physical Port ETS (indirect 0x0413)
1597 * Modify Physical Port ETS (indirect 0x0414)
1598 * Disable Physical Port ETS (indirect 0x0415)
1599 */
1600 struct i40e_aqc_configure_switching_comp_ets_data {
1601 u8 reserved[4];
1602 u8 tc_valid_bits;
1603 u8 seepage;
1604 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1605 u8 tc_strict_priority_flags;
1606 u8 reserved1[17];
1607 u8 tc_bw_share_credits[8];
1608 u8 reserved2[96];
1609 };
1610
1611 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1612
1613 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1614 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1615 u8 tc_valid_bits;
1616 u8 reserved[15];
1617 __le16 tc_bw_credit[8];
1618
1619 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1620 __le16 tc_bw_max[2];
1621 u8 reserved1[28];
1622 };
1623
1624 I40E_CHECK_STRUCT_LEN(0x40,
1625 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1626
1627 /* Configure Switching Component Bandwidth Allocation per Tc
1628 * (indirect 0x0417)
1629 */
1630 struct i40e_aqc_configure_switching_comp_bw_config_data {
1631 u8 tc_valid_bits;
1632 u8 reserved[2];
1633 u8 absolute_credits; /* bool */
1634 u8 tc_bw_share_credits[8];
1635 u8 reserved1[20];
1636 };
1637
1638 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1639
1640 /* Query Switching Component Configuration (indirect 0x0418) */
1641 struct i40e_aqc_query_switching_comp_ets_config_resp {
1642 u8 tc_valid_bits;
1643 u8 reserved[35];
1644 __le16 port_bw_limit;
1645 u8 reserved1[2];
1646 u8 tc_bw_max; /* 0-3, limit = 2^max */
1647 u8 reserved2[23];
1648 };
1649
1650 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1651
1652 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1653 struct i40e_aqc_query_port_ets_config_resp {
1654 u8 reserved[4];
1655 u8 tc_valid_bits;
1656 u8 reserved1;
1657 u8 tc_strict_priority_bits;
1658 u8 reserved2;
1659 u8 tc_bw_share_credits[8];
1660 __le16 tc_bw_limits[8];
1661
1662 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1663 __le16 tc_bw_max[2];
1664 u8 reserved3[32];
1665 };
1666
1667 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1668
1669 /* Query Switching Component Bandwidth Allocation per Traffic Type
1670 * (indirect 0x041A)
1671 */
1672 struct i40e_aqc_query_switching_comp_bw_config_resp {
1673 u8 tc_valid_bits;
1674 u8 reserved[2];
1675 u8 absolute_credits_enable; /* bool */
1676 u8 tc_bw_share_credits[8];
1677 __le16 tc_bw_limits[8];
1678
1679 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1680 __le16 tc_bw_max[2];
1681 };
1682
1683 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1684
1685 /* Suspend/resume port TX traffic
1686 * (direct 0x041B and 0x041C) uses the generic SEID struct
1687 */
1688
1689 /* Configure partition BW
1690 * (indirect 0x041D)
1691 */
1692 struct i40e_aqc_configure_partition_bw_data {
1693 __le16 pf_valid_bits;
1694 u8 min_bw[16]; /* guaranteed bandwidth */
1695 u8 max_bw[16]; /* bandwidth limit */
1696 };
1697
1698 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1699
1700 /* Get and set the active HMC resource profile and status.
1701 * (direct 0x0500) and (direct 0x0501)
1702 */
1703 struct i40e_aq_get_set_hmc_resource_profile {
1704 u8 pm_profile;
1705 u8 pe_vf_enabled;
1706 u8 reserved[14];
1707 };
1708
1709 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1710
1711 enum i40e_aq_hmc_profile {
1712 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1713 I40E_HMC_PROFILE_DEFAULT = 1,
1714 I40E_HMC_PROFILE_FAVOR_VF = 2,
1715 I40E_HMC_PROFILE_EQUAL = 3,
1716 };
1717
1718 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1719
1720 /* set in param0 for get phy abilities to report qualified modules */
1721 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1722 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1723
1724 enum i40e_aq_phy_type {
1725 I40E_PHY_TYPE_SGMII = 0x0,
1726 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1727 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1728 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1729 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1730 I40E_PHY_TYPE_XAUI = 0x5,
1731 I40E_PHY_TYPE_XFI = 0x6,
1732 I40E_PHY_TYPE_SFI = 0x7,
1733 I40E_PHY_TYPE_XLAUI = 0x8,
1734 I40E_PHY_TYPE_XLPPI = 0x9,
1735 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1736 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1737 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1738 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1739 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1740 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1741 I40E_PHY_TYPE_100BASE_TX = 0x11,
1742 I40E_PHY_TYPE_1000BASE_T = 0x12,
1743 I40E_PHY_TYPE_10GBASE_T = 0x13,
1744 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1745 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1746 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1747 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1748 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1749 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1750 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1751 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1752 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1753 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1754 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1755 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1756 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1757 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1758 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1759 I40E_PHY_TYPE_EMPTY = 0xFE,
1760 I40E_PHY_TYPE_DEFAULT = 0xFF,
1761 I40E_PHY_TYPE_MAX
1762 };
1763
1764 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1765 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1766 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1767 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1768 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1769 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1770
1771 enum i40e_aq_link_speed {
1772 I40E_LINK_SPEED_UNKNOWN = 0,
1773 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1774 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1775 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1776 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1777 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1778 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1779 };
1780
1781 struct i40e_aqc_module_desc {
1782 u8 oui[3];
1783 u8 reserved1;
1784 u8 part_number[16];
1785 u8 revision[4];
1786 u8 reserved2[8];
1787 };
1788
1789 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1790
1791 struct i40e_aq_get_phy_abilities_resp {
1792 __le32 phy_type; /* bitmap using the above enum for offsets */
1793 u8 link_speed; /* bitmap using the above enum bit patterns */
1794 u8 abilities;
1795 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1796 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1797 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1798 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1799 #define I40E_AQ_PHY_AN_ENABLED 0x10
1800 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1801 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1802 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1803 __le16 eee_capability;
1804 #define I40E_AQ_EEE_100BASE_TX 0x0002
1805 #define I40E_AQ_EEE_1000BASE_T 0x0004
1806 #define I40E_AQ_EEE_10GBASE_T 0x0008
1807 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1808 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1809 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1810 __le32 eeer_val;
1811 u8 d3_lpan;
1812 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1813 u8 phy_type_ext;
1814 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1815 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1816 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1817 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1818 u8 fec_cfg_curr_mod_ext_info;
1819 #define I40E_AQ_ENABLE_FEC_KR 0x01
1820 #define I40E_AQ_ENABLE_FEC_RS 0x02
1821 #define I40E_AQ_REQUEST_FEC_KR 0x04
1822 #define I40E_AQ_REQUEST_FEC_RS 0x08
1823 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1824 #define I40E_AQ_FEC
1825 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1826 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1827
1828 u8 ext_comp_code;
1829 u8 phy_id[4];
1830 u8 module_type[3];
1831 u8 qualified_module_count;
1832 #define I40E_AQ_PHY_MAX_QMS 16
1833 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1834 };
1835
1836 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1837
1838 /* Set PHY Config (direct 0x0601) */
1839 struct i40e_aq_set_phy_config { /* same bits as above in all */
1840 __le32 phy_type;
1841 u8 link_speed;
1842 u8 abilities;
1843 /* bits 0-2 use the values from get_phy_abilities_resp */
1844 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1845 #define I40E_AQ_PHY_ENABLE_AN 0x10
1846 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1847 __le16 eee_capability;
1848 __le32 eeer;
1849 u8 low_power_ctrl;
1850 u8 phy_type_ext;
1851 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1852 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1853 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1854 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1855 u8 fec_config;
1856 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1857 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1858 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1859 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1860 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1861 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1862 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1863 u8 reserved;
1864 };
1865
1866 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1867
1868 /* Set MAC Config command data structure (direct 0x0603) */
1869 struct i40e_aq_set_mac_config {
1870 __le16 max_frame_size;
1871 u8 params;
1872 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1873 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1874 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1875 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1876 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1877 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1878 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1879 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1880 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1881 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1882 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1883 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1884 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1885 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1886 u8 tx_timer_priority; /* bitmap */
1887 __le16 tx_timer_value;
1888 __le16 fc_refresh_threshold;
1889 u8 reserved[8];
1890 };
1891
1892 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1893
1894 /* Restart Auto-Negotiation (direct 0x605) */
1895 struct i40e_aqc_set_link_restart_an {
1896 u8 command;
1897 #define I40E_AQ_PHY_RESTART_AN 0x02
1898 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1899 u8 reserved[15];
1900 };
1901
1902 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1903
1904 /* Get Link Status cmd & response data structure (direct 0x0607) */
1905 struct i40e_aqc_get_link_status {
1906 __le16 command_flags; /* only field set on command */
1907 #define I40E_AQ_LSE_MASK 0x3
1908 #define I40E_AQ_LSE_NOP 0x0
1909 #define I40E_AQ_LSE_DISABLE 0x2
1910 #define I40E_AQ_LSE_ENABLE 0x3
1911 /* only response uses this flag */
1912 #define I40E_AQ_LSE_IS_ENABLED 0x1
1913 u8 phy_type; /* i40e_aq_phy_type */
1914 u8 link_speed; /* i40e_aq_link_speed */
1915 u8 link_info;
1916 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1917 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1918 #define I40E_AQ_LINK_FAULT 0x02
1919 #define I40E_AQ_LINK_FAULT_TX 0x04
1920 #define I40E_AQ_LINK_FAULT_RX 0x08
1921 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1922 #define I40E_AQ_LINK_UP_PORT 0x20
1923 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1924 #define I40E_AQ_SIGNAL_DETECT 0x80
1925 u8 an_info;
1926 #define I40E_AQ_AN_COMPLETED 0x01
1927 #define I40E_AQ_LP_AN_ABILITY 0x02
1928 #define I40E_AQ_PD_FAULT 0x04
1929 #define I40E_AQ_FEC_EN 0x08
1930 #define I40E_AQ_PHY_LOW_POWER 0x10
1931 #define I40E_AQ_LINK_PAUSE_TX 0x20
1932 #define I40E_AQ_LINK_PAUSE_RX 0x40
1933 #define I40E_AQ_QUALIFIED_MODULE 0x80
1934 u8 ext_info;
1935 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1936 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1937 #define I40E_AQ_LINK_TX_SHIFT 0x02
1938 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1939 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1940 #define I40E_AQ_LINK_TX_DRAINED 0x01
1941 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1942 #define I40E_AQ_LINK_FORCED_40G 0x10
1943 /* 25G Error Codes */
1944 #define I40E_AQ_25G_NO_ERR 0X00
1945 #define I40E_AQ_25G_NOT_PRESENT 0X01
1946 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
1947 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1948 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1949 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1950 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1951 /* Since firmware API 1.7 loopback field keeps power class info as well */
1952 #define I40E_AQ_LOOPBACK_MASK 0x07
1953 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
1954 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
1955 __le16 max_frame_size;
1956 u8 config;
1957 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1958 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1959 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1960 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1961 union {
1962 struct {
1963 u8 power_desc;
1964 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1965 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1966 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1967 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1968 #define I40E_AQ_PWR_CLASS_MASK 0x03
1969 u8 reserved[4];
1970 };
1971 struct {
1972 u8 link_type[4];
1973 u8 link_type_ext;
1974 };
1975 };
1976 };
1977
1978 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1979
1980 /* Set event mask command (direct 0x613) */
1981 struct i40e_aqc_set_phy_int_mask {
1982 u8 reserved[8];
1983 __le16 event_mask;
1984 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1985 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1986 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1987 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1988 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1989 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1990 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1991 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1992 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1993 u8 reserved1[6];
1994 };
1995
1996 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1997
1998 /* Get Local AN advt register (direct 0x0614)
1999 * Set Local AN advt register (direct 0x0615)
2000 * Get Link Partner AN advt register (direct 0x0616)
2001 */
2002 struct i40e_aqc_an_advt_reg {
2003 __le32 local_an_reg0;
2004 __le16 local_an_reg1;
2005 u8 reserved[10];
2006 };
2007
2008 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2009
2010 /* Set Loopback mode (0x0618) */
2011 struct i40e_aqc_set_lb_mode {
2012 __le16 lb_mode;
2013 #define I40E_AQ_LB_PHY_LOCAL 0x01
2014 #define I40E_AQ_LB_PHY_REMOTE 0x02
2015 #define I40E_AQ_LB_MAC_LOCAL 0x04
2016 u8 reserved[14];
2017 };
2018
2019 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2020
2021 /* Set PHY Debug command (0x0622) */
2022 struct i40e_aqc_set_phy_debug {
2023 u8 command_flags;
2024 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2025 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2026 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2027 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2028 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2029 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2030 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2031 /* Disable link manageability on a single port */
2032 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2033 /* Disable link manageability on all ports */
2034 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2035 u8 reserved[15];
2036 };
2037
2038 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2039
2040 enum i40e_aq_phy_reg_type {
2041 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2042 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2043 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2044 };
2045
2046 /* Run PHY Activity (0x0626) */
2047 struct i40e_aqc_run_phy_activity {
2048 __le16 activity_id;
2049 u8 flags;
2050 u8 reserved1;
2051 __le32 control;
2052 __le32 data;
2053 u8 reserved2[4];
2054 };
2055
2056 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2057
2058 /* Set PHY Register command (0x0628) */
2059 /* Get PHY Register command (0x0629) */
2060 struct i40e_aqc_phy_register_access {
2061 u8 phy_interface;
2062 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2063 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2064 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2065 u8 dev_address;
2066 u8 reserved1[2];
2067 __le32 reg_address;
2068 __le32 reg_value;
2069 u8 reserved2[4];
2070 };
2071
2072 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2073
2074 /* NVM Read command (indirect 0x0701)
2075 * NVM Erase commands (direct 0x0702)
2076 * NVM Update commands (indirect 0x0703)
2077 */
2078 struct i40e_aqc_nvm_update {
2079 u8 command_flags;
2080 #define I40E_AQ_NVM_LAST_CMD 0x01
2081 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2082 u8 module_pointer;
2083 __le16 length;
2084 __le32 offset;
2085 __le32 addr_high;
2086 __le32 addr_low;
2087 };
2088
2089 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2090
2091 /* NVM Config Read (indirect 0x0704) */
2092 struct i40e_aqc_nvm_config_read {
2093 __le16 cmd_flags;
2094 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2095 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2096 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2097 __le16 element_count;
2098 __le16 element_id; /* Feature/field ID */
2099 __le16 element_id_msw; /* MSWord of field ID */
2100 __le32 address_high;
2101 __le32 address_low;
2102 };
2103
2104 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2105
2106 /* NVM Config Write (indirect 0x0705) */
2107 struct i40e_aqc_nvm_config_write {
2108 __le16 cmd_flags;
2109 __le16 element_count;
2110 u8 reserved[4];
2111 __le32 address_high;
2112 __le32 address_low;
2113 };
2114
2115 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2116
2117 /* Used for 0x0704 as well as for 0x0705 commands */
2118 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2119 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2120 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2121 #define I40E_AQ_ANVM_FEATURE 0
2122 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT)
2123 struct i40e_aqc_nvm_config_data_feature {
2124 __le16 feature_id;
2125 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2126 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2127 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2128 __le16 feature_options;
2129 __le16 feature_selection;
2130 };
2131
2132 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2133
2134 struct i40e_aqc_nvm_config_data_immediate_field {
2135 __le32 field_id;
2136 __le32 field_value;
2137 __le16 field_options;
2138 __le16 reserved;
2139 };
2140
2141 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2142
2143 /* OEM Post Update (indirect 0x0720)
2144 * no command data struct used
2145 */
2146 struct i40e_aqc_nvm_oem_post_update {
2147 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2148 u8 sel_data;
2149 u8 reserved[7];
2150 };
2151
2152 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2153
2154 struct i40e_aqc_nvm_oem_post_update_buffer {
2155 u8 str_len;
2156 u8 dev_addr;
2157 __le16 eeprom_addr;
2158 u8 data[36];
2159 };
2160
2161 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2162
2163 /* Thermal Sensor (indirect 0x0721)
2164 * read or set thermal sensor configs and values
2165 * takes a sensor and command specific data buffer, not detailed here
2166 */
2167 struct i40e_aqc_thermal_sensor {
2168 u8 sensor_action;
2169 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2170 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2171 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2172 u8 reserved[7];
2173 __le32 addr_high;
2174 __le32 addr_low;
2175 };
2176
2177 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2178
2179 /* Send to PF command (indirect 0x0801) id is only used by PF
2180 * Send to VF command (indirect 0x0802) id is only used by PF
2181 * Send to Peer PF command (indirect 0x0803)
2182 */
2183 struct i40e_aqc_pf_vf_message {
2184 __le32 id;
2185 u8 reserved[4];
2186 __le32 addr_high;
2187 __le32 addr_low;
2188 };
2189
2190 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2191
2192 /* Alternate structure */
2193
2194 /* Direct write (direct 0x0900)
2195 * Direct read (direct 0x0902)
2196 */
2197 struct i40e_aqc_alternate_write {
2198 __le32 address0;
2199 __le32 data0;
2200 __le32 address1;
2201 __le32 data1;
2202 };
2203
2204 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2205
2206 /* Indirect write (indirect 0x0901)
2207 * Indirect read (indirect 0x0903)
2208 */
2209
2210 struct i40e_aqc_alternate_ind_write {
2211 __le32 address;
2212 __le32 length;
2213 __le32 addr_high;
2214 __le32 addr_low;
2215 };
2216
2217 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2218
2219 /* Done alternate write (direct 0x0904)
2220 * uses i40e_aq_desc
2221 */
2222 struct i40e_aqc_alternate_write_done {
2223 __le16 cmd_flags;
2224 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2225 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2226 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2227 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2228 u8 reserved[14];
2229 };
2230
2231 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2232
2233 /* Set OEM mode (direct 0x0905) */
2234 struct i40e_aqc_alternate_set_mode {
2235 __le32 mode;
2236 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2237 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2238 u8 reserved[12];
2239 };
2240
2241 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2242
2243 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2244
2245 /* async events 0x10xx */
2246
2247 /* Lan Queue Overflow Event (direct, 0x1001) */
2248 struct i40e_aqc_lan_overflow {
2249 __le32 prtdcb_rupto;
2250 __le32 otx_ctl;
2251 u8 reserved[8];
2252 };
2253
2254 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2255
2256 /* Get LLDP MIB (indirect 0x0A00) */
2257 struct i40e_aqc_lldp_get_mib {
2258 u8 type;
2259 u8 reserved1;
2260 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2261 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2262 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2263 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2264 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2265 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2266 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2267 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2268 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2269 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2270 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2271 __le16 local_len;
2272 __le16 remote_len;
2273 u8 reserved2[2];
2274 __le32 addr_high;
2275 __le32 addr_low;
2276 };
2277
2278 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2279
2280 /* Configure LLDP MIB Change Event (direct 0x0A01)
2281 * also used for the event (with type in the command field)
2282 */
2283 struct i40e_aqc_lldp_update_mib {
2284 u8 command;
2285 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2286 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2287 u8 reserved[7];
2288 __le32 addr_high;
2289 __le32 addr_low;
2290 };
2291
2292 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2293
2294 /* Add LLDP TLV (indirect 0x0A02)
2295 * Delete LLDP TLV (indirect 0x0A04)
2296 */
2297 struct i40e_aqc_lldp_add_tlv {
2298 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2299 u8 reserved1[1];
2300 __le16 len;
2301 u8 reserved2[4];
2302 __le32 addr_high;
2303 __le32 addr_low;
2304 };
2305
2306 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2307
2308 /* Update LLDP TLV (indirect 0x0A03) */
2309 struct i40e_aqc_lldp_update_tlv {
2310 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2311 u8 reserved;
2312 __le16 old_len;
2313 __le16 new_offset;
2314 __le16 new_len;
2315 __le32 addr_high;
2316 __le32 addr_low;
2317 };
2318
2319 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2320
2321 /* Stop LLDP (direct 0x0A05) */
2322 struct i40e_aqc_lldp_stop {
2323 u8 command;
2324 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2325 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2326 u8 reserved[15];
2327 };
2328
2329 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2330
2331 /* Start LLDP (direct 0x0A06) */
2332
2333 struct i40e_aqc_lldp_start {
2334 u8 command;
2335 #define I40E_AQ_LLDP_AGENT_START 0x1
2336 u8 reserved[15];
2337 };
2338
2339 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2340
2341 /* Get CEE DCBX Oper Config (0x0A07)
2342 * uses the generic descriptor struct
2343 * returns below as indirect response
2344 */
2345
2346 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2347 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2348 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2349 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2350 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2351 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2352
2353 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2354 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2355 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2356 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2357 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2358 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2359 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2360 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2361 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2362 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2363 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2364 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2365
2366 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2367 * word boundary layout issues, which the Linux compilers silently deal
2368 * with by adding padding, making the actual struct larger than designed.
2369 * However, the FW compiler for the NIC is less lenient and complains
2370 * about the struct. Hence, the struct defined here has an extra byte in
2371 * fields reserved3 and reserved4 to directly acknowledge that padding,
2372 * and the new length is used in the length check macro.
2373 */
2374 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2375 u8 reserved1;
2376 u8 oper_num_tc;
2377 u8 oper_prio_tc[4];
2378 u8 reserved2;
2379 u8 oper_tc_bw[8];
2380 u8 oper_pfc_en;
2381 u8 reserved3[2];
2382 __le16 oper_app_prio;
2383 u8 reserved4[2];
2384 __le16 tlv_status;
2385 };
2386
2387 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2388
2389 struct i40e_aqc_get_cee_dcb_cfg_resp {
2390 u8 oper_num_tc;
2391 u8 oper_prio_tc[4];
2392 u8 oper_tc_bw[8];
2393 u8 oper_pfc_en;
2394 __le16 oper_app_prio;
2395 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2396 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2397 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2398 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2399 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2400 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2401 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2402 __le32 tlv_status;
2403 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2404 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2405 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2406 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2407 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2408 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2409 u8 reserved[12];
2410 };
2411
2412 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2413
2414 /* Set Local LLDP MIB (indirect 0x0A08)
2415 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2416 */
2417 struct i40e_aqc_lldp_set_local_mib {
2418 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2419 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2420 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2421 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2422 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \
2423 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2424 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2425 u8 type;
2426 u8 reserved0;
2427 __le16 length;
2428 u8 reserved1[4];
2429 __le32 address_high;
2430 __le32 address_low;
2431 };
2432
2433 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2434
2435 /* Stop/Start LLDP Agent (direct 0x0A09)
2436 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2437 */
2438 struct i40e_aqc_lldp_stop_start_specific_agent {
2439 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2440 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2441 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2442 u8 command;
2443 u8 reserved[15];
2444 };
2445
2446 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2447
2448 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2449 struct i40e_aqc_add_udp_tunnel {
2450 __le16 udp_port;
2451 u8 reserved0[3];
2452 u8 protocol_type;
2453 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2454 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2455 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2456 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2457 u8 reserved1[10];
2458 };
2459
2460 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2461
2462 struct i40e_aqc_add_udp_tunnel_completion {
2463 __le16 udp_port;
2464 u8 filter_entry_index;
2465 u8 multiple_pfs;
2466 #define I40E_AQC_SINGLE_PF 0x0
2467 #define I40E_AQC_MULTIPLE_PFS 0x1
2468 u8 total_filters;
2469 u8 reserved[11];
2470 };
2471
2472 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2473
2474 /* remove UDP Tunnel command (0x0B01) */
2475 struct i40e_aqc_remove_udp_tunnel {
2476 u8 reserved[2];
2477 u8 index; /* 0 to 15 */
2478 u8 reserved2[13];
2479 };
2480
2481 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2482
2483 struct i40e_aqc_del_udp_tunnel_completion {
2484 __le16 udp_port;
2485 u8 index; /* 0 to 15 */
2486 u8 multiple_pfs;
2487 u8 total_filters_used;
2488 u8 reserved1[11];
2489 };
2490
2491 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2492
2493 struct i40e_aqc_get_set_rss_key {
2494 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2495 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2496 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2497 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2498 __le16 vsi_id;
2499 u8 reserved[6];
2500 __le32 addr_high;
2501 __le32 addr_low;
2502 };
2503
2504 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2505
2506 struct i40e_aqc_get_set_rss_key_data {
2507 u8 standard_rss_key[0x28];
2508 u8 extended_hash_key[0xc];
2509 };
2510
2511 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2512
2513 struct i40e_aqc_get_set_rss_lut {
2514 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2515 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2516 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2517 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2518 __le16 vsi_id;
2519 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2520 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2521
2522 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2523 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2524 __le16 flags;
2525 u8 reserved[4];
2526 __le32 addr_high;
2527 __le32 addr_low;
2528 };
2529
2530 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2531
2532 /* tunnel key structure 0x0B10 */
2533
2534 struct i40e_aqc_tunnel_key_structure {
2535 u8 key1_off;
2536 u8 key2_off;
2537 u8 key1_len; /* 0 to 15 */
2538 u8 key2_len; /* 0 to 15 */
2539 u8 flags;
2540 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2541 /* response flags */
2542 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2543 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2544 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2545 u8 network_key_index;
2546 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2547 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2548 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2549 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2550 u8 reserved[10];
2551 };
2552
2553 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2554
2555 /* OEM mode commands (direct 0xFE0x) */
2556 struct i40e_aqc_oem_param_change {
2557 __le32 param_type;
2558 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2559 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2560 #define I40E_AQ_OEM_PARAM_MAC 2
2561 __le32 param_value1;
2562 __le16 param_value2;
2563 u8 reserved[6];
2564 };
2565
2566 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2567
2568 struct i40e_aqc_oem_state_change {
2569 __le32 state;
2570 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2571 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2572 u8 reserved[12];
2573 };
2574
2575 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2576
2577 /* Initialize OCSD (0xFE02, direct) */
2578 struct i40e_aqc_opc_oem_ocsd_initialize {
2579 u8 type_status;
2580 u8 reserved1[3];
2581 __le32 ocsd_memory_block_addr_high;
2582 __le32 ocsd_memory_block_addr_low;
2583 __le32 requested_update_interval;
2584 };
2585
2586 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2587
2588 /* Initialize OCBB (0xFE03, direct) */
2589 struct i40e_aqc_opc_oem_ocbb_initialize {
2590 u8 type_status;
2591 u8 reserved1[3];
2592 __le32 ocbb_memory_block_addr_high;
2593 __le32 ocbb_memory_block_addr_low;
2594 u8 reserved2[4];
2595 };
2596
2597 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2598
2599 /* debug commands */
2600
2601 /* get device id (0xFF00) uses the generic structure */
2602
2603 /* set test more (0xFF01, internal) */
2604
2605 struct i40e_acq_set_test_mode {
2606 u8 mode;
2607 #define I40E_AQ_TEST_PARTIAL 0
2608 #define I40E_AQ_TEST_FULL 1
2609 #define I40E_AQ_TEST_NVM 2
2610 u8 reserved[3];
2611 u8 command;
2612 #define I40E_AQ_TEST_OPEN 0
2613 #define I40E_AQ_TEST_CLOSE 1
2614 #define I40E_AQ_TEST_INC 2
2615 u8 reserved2[3];
2616 __le32 address_high;
2617 __le32 address_low;
2618 };
2619
2620 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2621
2622 /* Debug Read Register command (0xFF03)
2623 * Debug Write Register command (0xFF04)
2624 */
2625 struct i40e_aqc_debug_reg_read_write {
2626 __le32 reserved;
2627 __le32 address;
2628 __le32 value_high;
2629 __le32 value_low;
2630 };
2631
2632 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2633
2634 /* Scatter/gather Reg Read (indirect 0xFF05)
2635 * Scatter/gather Reg Write (indirect 0xFF06)
2636 */
2637
2638 /* i40e_aq_desc is used for the command */
2639 struct i40e_aqc_debug_reg_sg_element_data {
2640 __le32 address;
2641 __le32 value;
2642 };
2643
2644 /* Debug Modify register (direct 0xFF07) */
2645 struct i40e_aqc_debug_modify_reg {
2646 __le32 address;
2647 __le32 value;
2648 __le32 clear_mask;
2649 __le32 set_mask;
2650 };
2651
2652 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2653
2654 /* dump internal data (0xFF08, indirect) */
2655
2656 #define I40E_AQ_CLUSTER_ID_AUX 0
2657 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2658 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2659 #define I40E_AQ_CLUSTER_ID_HMC 3
2660 #define I40E_AQ_CLUSTER_ID_MAC0 4
2661 #define I40E_AQ_CLUSTER_ID_MAC1 5
2662 #define I40E_AQ_CLUSTER_ID_MAC2 6
2663 #define I40E_AQ_CLUSTER_ID_MAC3 7
2664 #define I40E_AQ_CLUSTER_ID_DCB 8
2665 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2666 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2667 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2668
2669 struct i40e_aqc_debug_dump_internals {
2670 u8 cluster_id;
2671 u8 table_id;
2672 __le16 data_size;
2673 __le32 idx;
2674 __le32 address_high;
2675 __le32 address_low;
2676 };
2677
2678 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2679
2680 struct i40e_aqc_debug_modify_internals {
2681 u8 cluster_id;
2682 u8 cluster_specific_params[7];
2683 __le32 address_high;
2684 __le32 address_low;
2685 };
2686
2687 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2688
2689 #endif /* _I40E_ADMINQ_CMD_H_ */
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