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i40e: Remove HMC AQ API implementation
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
52 case I40E_DEV_ID_10G_BASE_T:
53 case I40E_DEV_ID_10G_BASE_T4:
54 case I40E_DEV_ID_20G_KR2:
55 case I40E_DEV_ID_20G_KR2_A:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
63 case I40E_DEV_ID_SFP_I_X722:
64 case I40E_DEV_ID_QSFP_I_X722:
65 hw->mac.type = I40E_MAC_X722;
66 break;
67 default:
68 hw->mac.type = I40E_MAC_GENERIC;
69 break;
70 }
71 } else {
72 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
73 }
74
75 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
76 hw->mac.type, status);
77 return status;
78 }
79
80 /**
81 * i40e_aq_str - convert AQ err code to a string
82 * @hw: pointer to the HW structure
83 * @aq_err: the AQ error code to convert
84 **/
85 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
86 {
87 switch (aq_err) {
88 case I40E_AQ_RC_OK:
89 return "OK";
90 case I40E_AQ_RC_EPERM:
91 return "I40E_AQ_RC_EPERM";
92 case I40E_AQ_RC_ENOENT:
93 return "I40E_AQ_RC_ENOENT";
94 case I40E_AQ_RC_ESRCH:
95 return "I40E_AQ_RC_ESRCH";
96 case I40E_AQ_RC_EINTR:
97 return "I40E_AQ_RC_EINTR";
98 case I40E_AQ_RC_EIO:
99 return "I40E_AQ_RC_EIO";
100 case I40E_AQ_RC_ENXIO:
101 return "I40E_AQ_RC_ENXIO";
102 case I40E_AQ_RC_E2BIG:
103 return "I40E_AQ_RC_E2BIG";
104 case I40E_AQ_RC_EAGAIN:
105 return "I40E_AQ_RC_EAGAIN";
106 case I40E_AQ_RC_ENOMEM:
107 return "I40E_AQ_RC_ENOMEM";
108 case I40E_AQ_RC_EACCES:
109 return "I40E_AQ_RC_EACCES";
110 case I40E_AQ_RC_EFAULT:
111 return "I40E_AQ_RC_EFAULT";
112 case I40E_AQ_RC_EBUSY:
113 return "I40E_AQ_RC_EBUSY";
114 case I40E_AQ_RC_EEXIST:
115 return "I40E_AQ_RC_EEXIST";
116 case I40E_AQ_RC_EINVAL:
117 return "I40E_AQ_RC_EINVAL";
118 case I40E_AQ_RC_ENOTTY:
119 return "I40E_AQ_RC_ENOTTY";
120 case I40E_AQ_RC_ENOSPC:
121 return "I40E_AQ_RC_ENOSPC";
122 case I40E_AQ_RC_ENOSYS:
123 return "I40E_AQ_RC_ENOSYS";
124 case I40E_AQ_RC_ERANGE:
125 return "I40E_AQ_RC_ERANGE";
126 case I40E_AQ_RC_EFLUSHED:
127 return "I40E_AQ_RC_EFLUSHED";
128 case I40E_AQ_RC_BAD_ADDR:
129 return "I40E_AQ_RC_BAD_ADDR";
130 case I40E_AQ_RC_EMODE:
131 return "I40E_AQ_RC_EMODE";
132 case I40E_AQ_RC_EFBIG:
133 return "I40E_AQ_RC_EFBIG";
134 }
135
136 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
137 return hw->err_str;
138 }
139
140 /**
141 * i40e_stat_str - convert status err code to a string
142 * @hw: pointer to the HW structure
143 * @stat_err: the status error code to convert
144 **/
145 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
146 {
147 switch (stat_err) {
148 case 0:
149 return "OK";
150 case I40E_ERR_NVM:
151 return "I40E_ERR_NVM";
152 case I40E_ERR_NVM_CHECKSUM:
153 return "I40E_ERR_NVM_CHECKSUM";
154 case I40E_ERR_PHY:
155 return "I40E_ERR_PHY";
156 case I40E_ERR_CONFIG:
157 return "I40E_ERR_CONFIG";
158 case I40E_ERR_PARAM:
159 return "I40E_ERR_PARAM";
160 case I40E_ERR_MAC_TYPE:
161 return "I40E_ERR_MAC_TYPE";
162 case I40E_ERR_UNKNOWN_PHY:
163 return "I40E_ERR_UNKNOWN_PHY";
164 case I40E_ERR_LINK_SETUP:
165 return "I40E_ERR_LINK_SETUP";
166 case I40E_ERR_ADAPTER_STOPPED:
167 return "I40E_ERR_ADAPTER_STOPPED";
168 case I40E_ERR_INVALID_MAC_ADDR:
169 return "I40E_ERR_INVALID_MAC_ADDR";
170 case I40E_ERR_DEVICE_NOT_SUPPORTED:
171 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
172 case I40E_ERR_MASTER_REQUESTS_PENDING:
173 return "I40E_ERR_MASTER_REQUESTS_PENDING";
174 case I40E_ERR_INVALID_LINK_SETTINGS:
175 return "I40E_ERR_INVALID_LINK_SETTINGS";
176 case I40E_ERR_AUTONEG_NOT_COMPLETE:
177 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
178 case I40E_ERR_RESET_FAILED:
179 return "I40E_ERR_RESET_FAILED";
180 case I40E_ERR_SWFW_SYNC:
181 return "I40E_ERR_SWFW_SYNC";
182 case I40E_ERR_NO_AVAILABLE_VSI:
183 return "I40E_ERR_NO_AVAILABLE_VSI";
184 case I40E_ERR_NO_MEMORY:
185 return "I40E_ERR_NO_MEMORY";
186 case I40E_ERR_BAD_PTR:
187 return "I40E_ERR_BAD_PTR";
188 case I40E_ERR_RING_FULL:
189 return "I40E_ERR_RING_FULL";
190 case I40E_ERR_INVALID_PD_ID:
191 return "I40E_ERR_INVALID_PD_ID";
192 case I40E_ERR_INVALID_QP_ID:
193 return "I40E_ERR_INVALID_QP_ID";
194 case I40E_ERR_INVALID_CQ_ID:
195 return "I40E_ERR_INVALID_CQ_ID";
196 case I40E_ERR_INVALID_CEQ_ID:
197 return "I40E_ERR_INVALID_CEQ_ID";
198 case I40E_ERR_INVALID_AEQ_ID:
199 return "I40E_ERR_INVALID_AEQ_ID";
200 case I40E_ERR_INVALID_SIZE:
201 return "I40E_ERR_INVALID_SIZE";
202 case I40E_ERR_INVALID_ARP_INDEX:
203 return "I40E_ERR_INVALID_ARP_INDEX";
204 case I40E_ERR_INVALID_FPM_FUNC_ID:
205 return "I40E_ERR_INVALID_FPM_FUNC_ID";
206 case I40E_ERR_QP_INVALID_MSG_SIZE:
207 return "I40E_ERR_QP_INVALID_MSG_SIZE";
208 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
209 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
210 case I40E_ERR_INVALID_FRAG_COUNT:
211 return "I40E_ERR_INVALID_FRAG_COUNT";
212 case I40E_ERR_QUEUE_EMPTY:
213 return "I40E_ERR_QUEUE_EMPTY";
214 case I40E_ERR_INVALID_ALIGNMENT:
215 return "I40E_ERR_INVALID_ALIGNMENT";
216 case I40E_ERR_FLUSHED_QUEUE:
217 return "I40E_ERR_FLUSHED_QUEUE";
218 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
219 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
220 case I40E_ERR_INVALID_IMM_DATA_SIZE:
221 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
222 case I40E_ERR_TIMEOUT:
223 return "I40E_ERR_TIMEOUT";
224 case I40E_ERR_OPCODE_MISMATCH:
225 return "I40E_ERR_OPCODE_MISMATCH";
226 case I40E_ERR_CQP_COMPL_ERROR:
227 return "I40E_ERR_CQP_COMPL_ERROR";
228 case I40E_ERR_INVALID_VF_ID:
229 return "I40E_ERR_INVALID_VF_ID";
230 case I40E_ERR_INVALID_HMCFN_ID:
231 return "I40E_ERR_INVALID_HMCFN_ID";
232 case I40E_ERR_BACKING_PAGE_ERROR:
233 return "I40E_ERR_BACKING_PAGE_ERROR";
234 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
235 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
236 case I40E_ERR_INVALID_PBLE_INDEX:
237 return "I40E_ERR_INVALID_PBLE_INDEX";
238 case I40E_ERR_INVALID_SD_INDEX:
239 return "I40E_ERR_INVALID_SD_INDEX";
240 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
241 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
242 case I40E_ERR_INVALID_SD_TYPE:
243 return "I40E_ERR_INVALID_SD_TYPE";
244 case I40E_ERR_MEMCPY_FAILED:
245 return "I40E_ERR_MEMCPY_FAILED";
246 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
247 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
248 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
249 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
250 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
251 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
252 case I40E_ERR_SRQ_ENABLED:
253 return "I40E_ERR_SRQ_ENABLED";
254 case I40E_ERR_ADMIN_QUEUE_ERROR:
255 return "I40E_ERR_ADMIN_QUEUE_ERROR";
256 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
257 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
258 case I40E_ERR_BUF_TOO_SHORT:
259 return "I40E_ERR_BUF_TOO_SHORT";
260 case I40E_ERR_ADMIN_QUEUE_FULL:
261 return "I40E_ERR_ADMIN_QUEUE_FULL";
262 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
263 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
264 case I40E_ERR_BAD_IWARP_CQE:
265 return "I40E_ERR_BAD_IWARP_CQE";
266 case I40E_ERR_NVM_BLANK_MODE:
267 return "I40E_ERR_NVM_BLANK_MODE";
268 case I40E_ERR_NOT_IMPLEMENTED:
269 return "I40E_ERR_NOT_IMPLEMENTED";
270 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
271 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
272 case I40E_ERR_DIAG_TEST_FAILED:
273 return "I40E_ERR_DIAG_TEST_FAILED";
274 case I40E_ERR_NOT_READY:
275 return "I40E_ERR_NOT_READY";
276 case I40E_NOT_SUPPORTED:
277 return "I40E_NOT_SUPPORTED";
278 case I40E_ERR_FIRMWARE_API_VERSION:
279 return "I40E_ERR_FIRMWARE_API_VERSION";
280 }
281
282 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
283 return hw->err_str;
284 }
285
286 /**
287 * i40e_debug_aq
288 * @hw: debug mask related to admin queue
289 * @mask: debug mask
290 * @desc: pointer to admin queue descriptor
291 * @buffer: pointer to command buffer
292 * @buf_len: max length of buffer
293 *
294 * Dumps debug log about adminq command with descriptor contents.
295 **/
296 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
297 void *buffer, u16 buf_len)
298 {
299 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
300 u16 len = le16_to_cpu(aq_desc->datalen);
301 u8 *buf = (u8 *)buffer;
302 u16 i = 0;
303
304 if ((!(mask & hw->debug_mask)) || (desc == NULL))
305 return;
306
307 i40e_debug(hw, mask,
308 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
309 le16_to_cpu(aq_desc->opcode),
310 le16_to_cpu(aq_desc->flags),
311 le16_to_cpu(aq_desc->datalen),
312 le16_to_cpu(aq_desc->retval));
313 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
314 le32_to_cpu(aq_desc->cookie_high),
315 le32_to_cpu(aq_desc->cookie_low));
316 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
317 le32_to_cpu(aq_desc->params.internal.param0),
318 le32_to_cpu(aq_desc->params.internal.param1));
319 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
320 le32_to_cpu(aq_desc->params.external.addr_high),
321 le32_to_cpu(aq_desc->params.external.addr_low));
322
323 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
324 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
325 if (buf_len < len)
326 len = buf_len;
327 /* write the full 16-byte chunks */
328 for (i = 0; i < (len - 16); i += 16)
329 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
330 /* write whatever's left over without overrunning the buffer */
331 if (i < len)
332 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
333 i, len - i, buf + i);
334 }
335 }
336
337 /**
338 * i40e_check_asq_alive
339 * @hw: pointer to the hw struct
340 *
341 * Returns true if Queue is enabled else false.
342 **/
343 bool i40e_check_asq_alive(struct i40e_hw *hw)
344 {
345 if (hw->aq.asq.len)
346 return !!(rd32(hw, hw->aq.asq.len) &
347 I40E_PF_ATQLEN_ATQENABLE_MASK);
348 else
349 return false;
350 }
351
352 /**
353 * i40e_aq_queue_shutdown
354 * @hw: pointer to the hw struct
355 * @unloading: is the driver unloading itself
356 *
357 * Tell the Firmware that we're shutting down the AdminQ and whether
358 * or not the driver is unloading as well.
359 **/
360 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
361 bool unloading)
362 {
363 struct i40e_aq_desc desc;
364 struct i40e_aqc_queue_shutdown *cmd =
365 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
366 i40e_status status;
367
368 i40e_fill_default_direct_cmd_desc(&desc,
369 i40e_aqc_opc_queue_shutdown);
370
371 if (unloading)
372 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
373 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
374
375 return status;
376 }
377
378 /**
379 * i40e_aq_get_set_rss_lut
380 * @hw: pointer to the hardware structure
381 * @vsi_id: vsi fw index
382 * @pf_lut: for PF table set true, for VSI table set false
383 * @lut: pointer to the lut buffer provided by the caller
384 * @lut_size: size of the lut buffer
385 * @set: set true to set the table, false to get the table
386 *
387 * Internal function to get or set RSS look up table
388 **/
389 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
390 u16 vsi_id, bool pf_lut,
391 u8 *lut, u16 lut_size,
392 bool set)
393 {
394 i40e_status status;
395 struct i40e_aq_desc desc;
396 struct i40e_aqc_get_set_rss_lut *cmd_resp =
397 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
398
399 if (set)
400 i40e_fill_default_direct_cmd_desc(&desc,
401 i40e_aqc_opc_set_rss_lut);
402 else
403 i40e_fill_default_direct_cmd_desc(&desc,
404 i40e_aqc_opc_get_rss_lut);
405
406 /* Indirect command */
407 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
408 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
409
410 cmd_resp->vsi_id =
411 cpu_to_le16((u16)((vsi_id <<
412 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
413 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
414 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
415
416 if (pf_lut)
417 cmd_resp->flags |= cpu_to_le16((u16)
418 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
419 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
421 else
422 cmd_resp->flags |= cpu_to_le16((u16)
423 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
424 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
425 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
426
427 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
428
429 return status;
430 }
431
432 /**
433 * i40e_aq_get_rss_lut
434 * @hw: pointer to the hardware structure
435 * @vsi_id: vsi fw index
436 * @pf_lut: for PF table set true, for VSI table set false
437 * @lut: pointer to the lut buffer provided by the caller
438 * @lut_size: size of the lut buffer
439 *
440 * get the RSS lookup table, PF or VSI type
441 **/
442 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
443 bool pf_lut, u8 *lut, u16 lut_size)
444 {
445 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
446 false);
447 }
448
449 /**
450 * i40e_aq_set_rss_lut
451 * @hw: pointer to the hardware structure
452 * @vsi_id: vsi fw index
453 * @pf_lut: for PF table set true, for VSI table set false
454 * @lut: pointer to the lut buffer provided by the caller
455 * @lut_size: size of the lut buffer
456 *
457 * set the RSS lookup table, PF or VSI type
458 **/
459 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
460 bool pf_lut, u8 *lut, u16 lut_size)
461 {
462 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
463 }
464
465 /**
466 * i40e_aq_get_set_rss_key
467 * @hw: pointer to the hw struct
468 * @vsi_id: vsi fw index
469 * @key: pointer to key info struct
470 * @set: set true to set the key, false to get the key
471 *
472 * get the RSS key per VSI
473 **/
474 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
475 u16 vsi_id,
476 struct i40e_aqc_get_set_rss_key_data *key,
477 bool set)
478 {
479 i40e_status status;
480 struct i40e_aq_desc desc;
481 struct i40e_aqc_get_set_rss_key *cmd_resp =
482 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
483 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
484
485 if (set)
486 i40e_fill_default_direct_cmd_desc(&desc,
487 i40e_aqc_opc_set_rss_key);
488 else
489 i40e_fill_default_direct_cmd_desc(&desc,
490 i40e_aqc_opc_get_rss_key);
491
492 /* Indirect command */
493 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
494 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
495
496 cmd_resp->vsi_id =
497 cpu_to_le16((u16)((vsi_id <<
498 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
499 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
500 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
501
502 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
503
504 return status;
505 }
506
507 /**
508 * i40e_aq_get_rss_key
509 * @hw: pointer to the hw struct
510 * @vsi_id: vsi fw index
511 * @key: pointer to key info struct
512 *
513 **/
514 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
515 u16 vsi_id,
516 struct i40e_aqc_get_set_rss_key_data *key)
517 {
518 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
519 }
520
521 /**
522 * i40e_aq_set_rss_key
523 * @hw: pointer to the hw struct
524 * @vsi_id: vsi fw index
525 * @key: pointer to key info struct
526 *
527 * set the RSS key per VSI
528 **/
529 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
530 u16 vsi_id,
531 struct i40e_aqc_get_set_rss_key_data *key)
532 {
533 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
534 }
535
536 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
537 * hardware to a bit-field that can be used by SW to more easily determine the
538 * packet type.
539 *
540 * Macros are used to shorten the table lines and make this table human
541 * readable.
542 *
543 * We store the PTYPE in the top byte of the bit field - this is just so that
544 * we can check that the table doesn't have a row missing, as the index into
545 * the table should be the PTYPE.
546 *
547 * Typical work flow:
548 *
549 * IF NOT i40e_ptype_lookup[ptype].known
550 * THEN
551 * Packet is unknown
552 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
553 * Use the rest of the fields to look at the tunnels, inner protocols, etc
554 * ELSE
555 * Use the enum i40e_rx_l2_ptype to decode the packet type
556 * ENDIF
557 */
558
559 /* macro to make the table lines short */
560 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
561 { PTYPE, \
562 1, \
563 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
564 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
565 I40E_RX_PTYPE_##OUTER_FRAG, \
566 I40E_RX_PTYPE_TUNNEL_##T, \
567 I40E_RX_PTYPE_TUNNEL_END_##TE, \
568 I40E_RX_PTYPE_##TEF, \
569 I40E_RX_PTYPE_INNER_PROT_##I, \
570 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
571
572 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
573 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
574
575 /* shorter macros makes the table fit but are terse */
576 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
577 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
578 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
579
580 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
581 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
582 /* L2 Packet types */
583 I40E_PTT_UNUSED_ENTRY(0),
584 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
586 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
587 I40E_PTT_UNUSED_ENTRY(4),
588 I40E_PTT_UNUSED_ENTRY(5),
589 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
590 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
591 I40E_PTT_UNUSED_ENTRY(8),
592 I40E_PTT_UNUSED_ENTRY(9),
593 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
594 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
595 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605
606 /* Non Tunneled IPv4 */
607 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
608 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
609 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
610 I40E_PTT_UNUSED_ENTRY(25),
611 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
612 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
613 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
614
615 /* IPv4 --> IPv4 */
616 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
617 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
618 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
619 I40E_PTT_UNUSED_ENTRY(32),
620 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
621 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
622 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
623
624 /* IPv4 --> IPv6 */
625 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
626 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
627 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
628 I40E_PTT_UNUSED_ENTRY(39),
629 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
630 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
631 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
632
633 /* IPv4 --> GRE/NAT */
634 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
635
636 /* IPv4 --> GRE/NAT --> IPv4 */
637 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
638 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
639 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
640 I40E_PTT_UNUSED_ENTRY(47),
641 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
642 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
643 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
644
645 /* IPv4 --> GRE/NAT --> IPv6 */
646 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
647 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
648 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
649 I40E_PTT_UNUSED_ENTRY(54),
650 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
651 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
652 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
653
654 /* IPv4 --> GRE/NAT --> MAC */
655 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
656
657 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
658 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
659 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
660 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
661 I40E_PTT_UNUSED_ENTRY(62),
662 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
663 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
664 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
665
666 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
667 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
668 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
669 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
670 I40E_PTT_UNUSED_ENTRY(69),
671 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
672 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
673 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
674
675 /* IPv4 --> GRE/NAT --> MAC/VLAN */
676 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
677
678 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
679 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
680 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
681 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
682 I40E_PTT_UNUSED_ENTRY(77),
683 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
684 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
685 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
686
687 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
688 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
689 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
690 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
691 I40E_PTT_UNUSED_ENTRY(84),
692 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
693 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
694 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
695
696 /* Non Tunneled IPv6 */
697 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
698 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
699 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
700 I40E_PTT_UNUSED_ENTRY(91),
701 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
702 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
703 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
704
705 /* IPv6 --> IPv4 */
706 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
707 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
708 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
709 I40E_PTT_UNUSED_ENTRY(98),
710 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
711 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
712 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
713
714 /* IPv6 --> IPv6 */
715 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
716 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
717 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
718 I40E_PTT_UNUSED_ENTRY(105),
719 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
720 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
721 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
722
723 /* IPv6 --> GRE/NAT */
724 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
725
726 /* IPv6 --> GRE/NAT -> IPv4 */
727 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
728 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
729 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
730 I40E_PTT_UNUSED_ENTRY(113),
731 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
732 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
733 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
734
735 /* IPv6 --> GRE/NAT -> IPv6 */
736 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
737 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
738 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
739 I40E_PTT_UNUSED_ENTRY(120),
740 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
741 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
742 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
743
744 /* IPv6 --> GRE/NAT -> MAC */
745 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
746
747 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
748 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
749 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
750 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
751 I40E_PTT_UNUSED_ENTRY(128),
752 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
753 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
754 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
755
756 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
757 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
758 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
759 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
760 I40E_PTT_UNUSED_ENTRY(135),
761 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
762 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
763 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
764
765 /* IPv6 --> GRE/NAT -> MAC/VLAN */
766 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
767
768 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
769 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
770 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
771 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
772 I40E_PTT_UNUSED_ENTRY(143),
773 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
774 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
775 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
776
777 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
778 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
779 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
780 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
781 I40E_PTT_UNUSED_ENTRY(150),
782 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
783 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
784 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
785
786 /* unused entries */
787 I40E_PTT_UNUSED_ENTRY(154),
788 I40E_PTT_UNUSED_ENTRY(155),
789 I40E_PTT_UNUSED_ENTRY(156),
790 I40E_PTT_UNUSED_ENTRY(157),
791 I40E_PTT_UNUSED_ENTRY(158),
792 I40E_PTT_UNUSED_ENTRY(159),
793
794 I40E_PTT_UNUSED_ENTRY(160),
795 I40E_PTT_UNUSED_ENTRY(161),
796 I40E_PTT_UNUSED_ENTRY(162),
797 I40E_PTT_UNUSED_ENTRY(163),
798 I40E_PTT_UNUSED_ENTRY(164),
799 I40E_PTT_UNUSED_ENTRY(165),
800 I40E_PTT_UNUSED_ENTRY(166),
801 I40E_PTT_UNUSED_ENTRY(167),
802 I40E_PTT_UNUSED_ENTRY(168),
803 I40E_PTT_UNUSED_ENTRY(169),
804
805 I40E_PTT_UNUSED_ENTRY(170),
806 I40E_PTT_UNUSED_ENTRY(171),
807 I40E_PTT_UNUSED_ENTRY(172),
808 I40E_PTT_UNUSED_ENTRY(173),
809 I40E_PTT_UNUSED_ENTRY(174),
810 I40E_PTT_UNUSED_ENTRY(175),
811 I40E_PTT_UNUSED_ENTRY(176),
812 I40E_PTT_UNUSED_ENTRY(177),
813 I40E_PTT_UNUSED_ENTRY(178),
814 I40E_PTT_UNUSED_ENTRY(179),
815
816 I40E_PTT_UNUSED_ENTRY(180),
817 I40E_PTT_UNUSED_ENTRY(181),
818 I40E_PTT_UNUSED_ENTRY(182),
819 I40E_PTT_UNUSED_ENTRY(183),
820 I40E_PTT_UNUSED_ENTRY(184),
821 I40E_PTT_UNUSED_ENTRY(185),
822 I40E_PTT_UNUSED_ENTRY(186),
823 I40E_PTT_UNUSED_ENTRY(187),
824 I40E_PTT_UNUSED_ENTRY(188),
825 I40E_PTT_UNUSED_ENTRY(189),
826
827 I40E_PTT_UNUSED_ENTRY(190),
828 I40E_PTT_UNUSED_ENTRY(191),
829 I40E_PTT_UNUSED_ENTRY(192),
830 I40E_PTT_UNUSED_ENTRY(193),
831 I40E_PTT_UNUSED_ENTRY(194),
832 I40E_PTT_UNUSED_ENTRY(195),
833 I40E_PTT_UNUSED_ENTRY(196),
834 I40E_PTT_UNUSED_ENTRY(197),
835 I40E_PTT_UNUSED_ENTRY(198),
836 I40E_PTT_UNUSED_ENTRY(199),
837
838 I40E_PTT_UNUSED_ENTRY(200),
839 I40E_PTT_UNUSED_ENTRY(201),
840 I40E_PTT_UNUSED_ENTRY(202),
841 I40E_PTT_UNUSED_ENTRY(203),
842 I40E_PTT_UNUSED_ENTRY(204),
843 I40E_PTT_UNUSED_ENTRY(205),
844 I40E_PTT_UNUSED_ENTRY(206),
845 I40E_PTT_UNUSED_ENTRY(207),
846 I40E_PTT_UNUSED_ENTRY(208),
847 I40E_PTT_UNUSED_ENTRY(209),
848
849 I40E_PTT_UNUSED_ENTRY(210),
850 I40E_PTT_UNUSED_ENTRY(211),
851 I40E_PTT_UNUSED_ENTRY(212),
852 I40E_PTT_UNUSED_ENTRY(213),
853 I40E_PTT_UNUSED_ENTRY(214),
854 I40E_PTT_UNUSED_ENTRY(215),
855 I40E_PTT_UNUSED_ENTRY(216),
856 I40E_PTT_UNUSED_ENTRY(217),
857 I40E_PTT_UNUSED_ENTRY(218),
858 I40E_PTT_UNUSED_ENTRY(219),
859
860 I40E_PTT_UNUSED_ENTRY(220),
861 I40E_PTT_UNUSED_ENTRY(221),
862 I40E_PTT_UNUSED_ENTRY(222),
863 I40E_PTT_UNUSED_ENTRY(223),
864 I40E_PTT_UNUSED_ENTRY(224),
865 I40E_PTT_UNUSED_ENTRY(225),
866 I40E_PTT_UNUSED_ENTRY(226),
867 I40E_PTT_UNUSED_ENTRY(227),
868 I40E_PTT_UNUSED_ENTRY(228),
869 I40E_PTT_UNUSED_ENTRY(229),
870
871 I40E_PTT_UNUSED_ENTRY(230),
872 I40E_PTT_UNUSED_ENTRY(231),
873 I40E_PTT_UNUSED_ENTRY(232),
874 I40E_PTT_UNUSED_ENTRY(233),
875 I40E_PTT_UNUSED_ENTRY(234),
876 I40E_PTT_UNUSED_ENTRY(235),
877 I40E_PTT_UNUSED_ENTRY(236),
878 I40E_PTT_UNUSED_ENTRY(237),
879 I40E_PTT_UNUSED_ENTRY(238),
880 I40E_PTT_UNUSED_ENTRY(239),
881
882 I40E_PTT_UNUSED_ENTRY(240),
883 I40E_PTT_UNUSED_ENTRY(241),
884 I40E_PTT_UNUSED_ENTRY(242),
885 I40E_PTT_UNUSED_ENTRY(243),
886 I40E_PTT_UNUSED_ENTRY(244),
887 I40E_PTT_UNUSED_ENTRY(245),
888 I40E_PTT_UNUSED_ENTRY(246),
889 I40E_PTT_UNUSED_ENTRY(247),
890 I40E_PTT_UNUSED_ENTRY(248),
891 I40E_PTT_UNUSED_ENTRY(249),
892
893 I40E_PTT_UNUSED_ENTRY(250),
894 I40E_PTT_UNUSED_ENTRY(251),
895 I40E_PTT_UNUSED_ENTRY(252),
896 I40E_PTT_UNUSED_ENTRY(253),
897 I40E_PTT_UNUSED_ENTRY(254),
898 I40E_PTT_UNUSED_ENTRY(255)
899 };
900
901 /**
902 * i40e_init_shared_code - Initialize the shared code
903 * @hw: pointer to hardware structure
904 *
905 * This assigns the MAC type and PHY code and inits the NVM.
906 * Does not touch the hardware. This function must be called prior to any
907 * other function in the shared code. The i40e_hw structure should be
908 * memset to 0 prior to calling this function. The following fields in
909 * hw structure should be filled in prior to calling this function:
910 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
911 * subsystem_vendor_id, and revision_id
912 **/
913 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
914 {
915 i40e_status status = 0;
916 u32 port, ari, func_rid;
917
918 i40e_set_mac_type(hw);
919
920 switch (hw->mac.type) {
921 case I40E_MAC_XL710:
922 case I40E_MAC_X722:
923 break;
924 default:
925 return I40E_ERR_DEVICE_NOT_SUPPORTED;
926 }
927
928 hw->phy.get_link_info = true;
929
930 /* Determine port number and PF number*/
931 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
932 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
933 hw->port = (u8)port;
934 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
935 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
936 func_rid = rd32(hw, I40E_PF_FUNC_RID);
937 if (ari)
938 hw->pf_id = (u8)(func_rid & 0xff);
939 else
940 hw->pf_id = (u8)(func_rid & 0x7);
941
942 if (hw->mac.type == I40E_MAC_X722)
943 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
944
945 status = i40e_init_nvm(hw);
946 return status;
947 }
948
949 /**
950 * i40e_aq_mac_address_read - Retrieve the MAC addresses
951 * @hw: pointer to the hw struct
952 * @flags: a return indicator of what addresses were added to the addr store
953 * @addrs: the requestor's mac addr store
954 * @cmd_details: pointer to command details structure or NULL
955 **/
956 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
957 u16 *flags,
958 struct i40e_aqc_mac_address_read_data *addrs,
959 struct i40e_asq_cmd_details *cmd_details)
960 {
961 struct i40e_aq_desc desc;
962 struct i40e_aqc_mac_address_read *cmd_data =
963 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
964 i40e_status status;
965
966 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
967 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
968
969 status = i40e_asq_send_command(hw, &desc, addrs,
970 sizeof(*addrs), cmd_details);
971 *flags = le16_to_cpu(cmd_data->command_flags);
972
973 return status;
974 }
975
976 /**
977 * i40e_aq_mac_address_write - Change the MAC addresses
978 * @hw: pointer to the hw struct
979 * @flags: indicates which MAC to be written
980 * @mac_addr: address to write
981 * @cmd_details: pointer to command details structure or NULL
982 **/
983 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
984 u16 flags, u8 *mac_addr,
985 struct i40e_asq_cmd_details *cmd_details)
986 {
987 struct i40e_aq_desc desc;
988 struct i40e_aqc_mac_address_write *cmd_data =
989 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
990 i40e_status status;
991
992 i40e_fill_default_direct_cmd_desc(&desc,
993 i40e_aqc_opc_mac_address_write);
994 cmd_data->command_flags = cpu_to_le16(flags);
995 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
996 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
997 ((u32)mac_addr[3] << 16) |
998 ((u32)mac_addr[4] << 8) |
999 mac_addr[5]);
1000
1001 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1002
1003 return status;
1004 }
1005
1006 /**
1007 * i40e_get_mac_addr - get MAC address
1008 * @hw: pointer to the HW structure
1009 * @mac_addr: pointer to MAC address
1010 *
1011 * Reads the adapter's MAC address from register
1012 **/
1013 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1014 {
1015 struct i40e_aqc_mac_address_read_data addrs;
1016 i40e_status status;
1017 u16 flags = 0;
1018
1019 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1020
1021 if (flags & I40E_AQC_LAN_ADDR_VALID)
1022 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1023
1024 return status;
1025 }
1026
1027 /**
1028 * i40e_get_port_mac_addr - get Port MAC address
1029 * @hw: pointer to the HW structure
1030 * @mac_addr: pointer to Port MAC address
1031 *
1032 * Reads the adapter's Port MAC address
1033 **/
1034 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1035 {
1036 struct i40e_aqc_mac_address_read_data addrs;
1037 i40e_status status;
1038 u16 flags = 0;
1039
1040 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1041 if (status)
1042 return status;
1043
1044 if (flags & I40E_AQC_PORT_ADDR_VALID)
1045 ether_addr_copy(mac_addr, addrs.port_mac);
1046 else
1047 status = I40E_ERR_INVALID_MAC_ADDR;
1048
1049 return status;
1050 }
1051
1052 /**
1053 * i40e_pre_tx_queue_cfg - pre tx queue configure
1054 * @hw: pointer to the HW structure
1055 * @queue: target PF queue index
1056 * @enable: state change request
1057 *
1058 * Handles hw requirement to indicate intention to enable
1059 * or disable target queue.
1060 **/
1061 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1062 {
1063 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1064 u32 reg_block = 0;
1065 u32 reg_val;
1066
1067 if (abs_queue_idx >= 128) {
1068 reg_block = abs_queue_idx / 128;
1069 abs_queue_idx %= 128;
1070 }
1071
1072 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1073 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1074 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1075
1076 if (enable)
1077 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1078 else
1079 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1080
1081 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1082 }
1083 #ifdef I40E_FCOE
1084
1085 /**
1086 * i40e_get_san_mac_addr - get SAN MAC address
1087 * @hw: pointer to the HW structure
1088 * @mac_addr: pointer to SAN MAC address
1089 *
1090 * Reads the adapter's SAN MAC address from NVM
1091 **/
1092 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1093 {
1094 struct i40e_aqc_mac_address_read_data addrs;
1095 i40e_status status;
1096 u16 flags = 0;
1097
1098 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1099 if (status)
1100 return status;
1101
1102 if (flags & I40E_AQC_SAN_ADDR_VALID)
1103 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1104 else
1105 status = I40E_ERR_INVALID_MAC_ADDR;
1106
1107 return status;
1108 }
1109 #endif
1110
1111 /**
1112 * i40e_read_pba_string - Reads part number string from EEPROM
1113 * @hw: pointer to hardware structure
1114 * @pba_num: stores the part number string from the EEPROM
1115 * @pba_num_size: part number string buffer length
1116 *
1117 * Reads the part number string from the EEPROM.
1118 **/
1119 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1120 u32 pba_num_size)
1121 {
1122 i40e_status status = 0;
1123 u16 pba_word = 0;
1124 u16 pba_size = 0;
1125 u16 pba_ptr = 0;
1126 u16 i = 0;
1127
1128 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1129 if (status || (pba_word != 0xFAFA)) {
1130 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1131 return status;
1132 }
1133
1134 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1135 if (status) {
1136 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1137 return status;
1138 }
1139
1140 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1141 if (status) {
1142 hw_dbg(hw, "Failed to read PBA Block size.\n");
1143 return status;
1144 }
1145
1146 /* Subtract one to get PBA word count (PBA Size word is included in
1147 * total size)
1148 */
1149 pba_size--;
1150 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1151 hw_dbg(hw, "Buffer to small for PBA data.\n");
1152 return I40E_ERR_PARAM;
1153 }
1154
1155 for (i = 0; i < pba_size; i++) {
1156 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1157 if (status) {
1158 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1159 return status;
1160 }
1161
1162 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1163 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1164 }
1165 pba_num[(pba_size * 2)] = '\0';
1166
1167 return status;
1168 }
1169
1170 /**
1171 * i40e_get_media_type - Gets media type
1172 * @hw: pointer to the hardware structure
1173 **/
1174 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1175 {
1176 enum i40e_media_type media;
1177
1178 switch (hw->phy.link_info.phy_type) {
1179 case I40E_PHY_TYPE_10GBASE_SR:
1180 case I40E_PHY_TYPE_10GBASE_LR:
1181 case I40E_PHY_TYPE_1000BASE_SX:
1182 case I40E_PHY_TYPE_1000BASE_LX:
1183 case I40E_PHY_TYPE_40GBASE_SR4:
1184 case I40E_PHY_TYPE_40GBASE_LR4:
1185 media = I40E_MEDIA_TYPE_FIBER;
1186 break;
1187 case I40E_PHY_TYPE_100BASE_TX:
1188 case I40E_PHY_TYPE_1000BASE_T:
1189 case I40E_PHY_TYPE_10GBASE_T:
1190 media = I40E_MEDIA_TYPE_BASET;
1191 break;
1192 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1193 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1194 case I40E_PHY_TYPE_10GBASE_CR1:
1195 case I40E_PHY_TYPE_40GBASE_CR4:
1196 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1197 case I40E_PHY_TYPE_40GBASE_AOC:
1198 case I40E_PHY_TYPE_10GBASE_AOC:
1199 media = I40E_MEDIA_TYPE_DA;
1200 break;
1201 case I40E_PHY_TYPE_1000BASE_KX:
1202 case I40E_PHY_TYPE_10GBASE_KX4:
1203 case I40E_PHY_TYPE_10GBASE_KR:
1204 case I40E_PHY_TYPE_40GBASE_KR4:
1205 case I40E_PHY_TYPE_20GBASE_KR2:
1206 media = I40E_MEDIA_TYPE_BACKPLANE;
1207 break;
1208 case I40E_PHY_TYPE_SGMII:
1209 case I40E_PHY_TYPE_XAUI:
1210 case I40E_PHY_TYPE_XFI:
1211 case I40E_PHY_TYPE_XLAUI:
1212 case I40E_PHY_TYPE_XLPPI:
1213 default:
1214 media = I40E_MEDIA_TYPE_UNKNOWN;
1215 break;
1216 }
1217
1218 return media;
1219 }
1220
1221 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1222 #define I40E_PF_RESET_WAIT_COUNT 200
1223 /**
1224 * i40e_pf_reset - Reset the PF
1225 * @hw: pointer to the hardware structure
1226 *
1227 * Assuming someone else has triggered a global reset,
1228 * assure the global reset is complete and then reset the PF
1229 **/
1230 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1231 {
1232 u32 cnt = 0;
1233 u32 cnt1 = 0;
1234 u32 reg = 0;
1235 u32 grst_del;
1236
1237 /* Poll for Global Reset steady state in case of recent GRST.
1238 * The grst delay value is in 100ms units, and we'll wait a
1239 * couple counts longer to be sure we don't just miss the end.
1240 */
1241 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1242 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1243 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1244
1245 /* It can take upto 15 secs for GRST steady state.
1246 * Bump it to 16 secs max to be safe.
1247 */
1248 grst_del = grst_del * 20;
1249
1250 for (cnt = 0; cnt < grst_del; cnt++) {
1251 reg = rd32(hw, I40E_GLGEN_RSTAT);
1252 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1253 break;
1254 msleep(100);
1255 }
1256 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1257 hw_dbg(hw, "Global reset polling failed to complete.\n");
1258 return I40E_ERR_RESET_FAILED;
1259 }
1260
1261 /* Now Wait for the FW to be ready */
1262 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1263 reg = rd32(hw, I40E_GLNVM_ULD);
1264 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1266 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1267 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1268 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1269 break;
1270 }
1271 usleep_range(10000, 20000);
1272 }
1273 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1274 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1275 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1276 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1277 return I40E_ERR_RESET_FAILED;
1278 }
1279
1280 /* If there was a Global Reset in progress when we got here,
1281 * we don't need to do the PF Reset
1282 */
1283 if (!cnt) {
1284 if (hw->revision_id == 0)
1285 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1286 else
1287 cnt = I40E_PF_RESET_WAIT_COUNT;
1288 reg = rd32(hw, I40E_PFGEN_CTRL);
1289 wr32(hw, I40E_PFGEN_CTRL,
1290 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1291 for (; cnt; cnt--) {
1292 reg = rd32(hw, I40E_PFGEN_CTRL);
1293 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1294 break;
1295 usleep_range(1000, 2000);
1296 }
1297 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1298 hw_dbg(hw, "PF reset polling failed to complete.\n");
1299 return I40E_ERR_RESET_FAILED;
1300 }
1301 }
1302
1303 i40e_clear_pxe_mode(hw);
1304
1305 return 0;
1306 }
1307
1308 /**
1309 * i40e_clear_hw - clear out any left over hw state
1310 * @hw: pointer to the hw struct
1311 *
1312 * Clear queues and interrupts, typically called at init time,
1313 * but after the capabilities have been found so we know how many
1314 * queues and msix vectors have been allocated.
1315 **/
1316 void i40e_clear_hw(struct i40e_hw *hw)
1317 {
1318 u32 num_queues, base_queue;
1319 u32 num_pf_int;
1320 u32 num_vf_int;
1321 u32 num_vfs;
1322 u32 i, j;
1323 u32 val;
1324 u32 eol = 0x7ff;
1325
1326 /* get number of interrupts, queues, and VFs */
1327 val = rd32(hw, I40E_GLPCI_CNF2);
1328 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1329 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1330 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1331 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1332
1333 val = rd32(hw, I40E_PFLAN_QALLOC);
1334 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1335 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1336 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1337 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1338 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1339 num_queues = (j - base_queue) + 1;
1340 else
1341 num_queues = 0;
1342
1343 val = rd32(hw, I40E_PF_VT_PFALLOC);
1344 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1345 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1346 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1347 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1348 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1349 num_vfs = (j - i) + 1;
1350 else
1351 num_vfs = 0;
1352
1353 /* stop all the interrupts */
1354 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1355 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1356 for (i = 0; i < num_pf_int - 2; i++)
1357 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1358
1359 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1360 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1361 wr32(hw, I40E_PFINT_LNKLST0, val);
1362 for (i = 0; i < num_pf_int - 2; i++)
1363 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1364 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1365 for (i = 0; i < num_vfs; i++)
1366 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1367 for (i = 0; i < num_vf_int - 2; i++)
1368 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1369
1370 /* warn the HW of the coming Tx disables */
1371 for (i = 0; i < num_queues; i++) {
1372 u32 abs_queue_idx = base_queue + i;
1373 u32 reg_block = 0;
1374
1375 if (abs_queue_idx >= 128) {
1376 reg_block = abs_queue_idx / 128;
1377 abs_queue_idx %= 128;
1378 }
1379
1380 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1381 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1382 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1383 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1384
1385 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1386 }
1387 udelay(400);
1388
1389 /* stop all the queues */
1390 for (i = 0; i < num_queues; i++) {
1391 wr32(hw, I40E_QINT_TQCTL(i), 0);
1392 wr32(hw, I40E_QTX_ENA(i), 0);
1393 wr32(hw, I40E_QINT_RQCTL(i), 0);
1394 wr32(hw, I40E_QRX_ENA(i), 0);
1395 }
1396
1397 /* short wait for all queue disables to settle */
1398 udelay(50);
1399 }
1400
1401 /**
1402 * i40e_clear_pxe_mode - clear pxe operations mode
1403 * @hw: pointer to the hw struct
1404 *
1405 * Make sure all PXE mode settings are cleared, including things
1406 * like descriptor fetch/write-back mode.
1407 **/
1408 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1409 {
1410 u32 reg;
1411
1412 if (i40e_check_asq_alive(hw))
1413 i40e_aq_clear_pxe_mode(hw, NULL);
1414
1415 /* Clear single descriptor fetch/write-back mode */
1416 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1417
1418 if (hw->revision_id == 0) {
1419 /* As a work around clear PXE_MODE instead of setting it */
1420 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1421 } else {
1422 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1423 }
1424 }
1425
1426 /**
1427 * i40e_led_is_mine - helper to find matching led
1428 * @hw: pointer to the hw struct
1429 * @idx: index into GPIO registers
1430 *
1431 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1432 */
1433 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1434 {
1435 u32 gpio_val = 0;
1436 u32 port;
1437
1438 if (!hw->func_caps.led[idx])
1439 return 0;
1440
1441 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1442 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1443 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1444
1445 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1446 * if it is not our port then ignore
1447 */
1448 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1449 (port != hw->port))
1450 return 0;
1451
1452 return gpio_val;
1453 }
1454
1455 #define I40E_COMBINED_ACTIVITY 0xA
1456 #define I40E_FILTER_ACTIVITY 0xE
1457 #define I40E_LINK_ACTIVITY 0xC
1458 #define I40E_MAC_ACTIVITY 0xD
1459 #define I40E_LED0 22
1460
1461 /**
1462 * i40e_led_get - return current on/off mode
1463 * @hw: pointer to the hw struct
1464 *
1465 * The value returned is the 'mode' field as defined in the
1466 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1467 * values are variations of possible behaviors relating to
1468 * blink, link, and wire.
1469 **/
1470 u32 i40e_led_get(struct i40e_hw *hw)
1471 {
1472 u32 current_mode = 0;
1473 u32 mode = 0;
1474 int i;
1475
1476 /* as per the documentation GPIO 22-29 are the LED
1477 * GPIO pins named LED0..LED7
1478 */
1479 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1480 u32 gpio_val = i40e_led_is_mine(hw, i);
1481
1482 if (!gpio_val)
1483 continue;
1484
1485 /* ignore gpio LED src mode entries related to the activity
1486 * LEDs
1487 */
1488 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1489 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1490 switch (current_mode) {
1491 case I40E_COMBINED_ACTIVITY:
1492 case I40E_FILTER_ACTIVITY:
1493 case I40E_MAC_ACTIVITY:
1494 continue;
1495 default:
1496 break;
1497 }
1498
1499 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1500 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1501 break;
1502 }
1503
1504 return mode;
1505 }
1506
1507 /**
1508 * i40e_led_set - set new on/off mode
1509 * @hw: pointer to the hw struct
1510 * @mode: 0=off, 0xf=on (else see manual for mode details)
1511 * @blink: true if the LED should blink when on, false if steady
1512 *
1513 * if this function is used to turn on the blink it should
1514 * be used to disable the blink when restoring the original state.
1515 **/
1516 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1517 {
1518 u32 current_mode = 0;
1519 int i;
1520
1521 if (mode & 0xfffffff0)
1522 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1523
1524 /* as per the documentation GPIO 22-29 are the LED
1525 * GPIO pins named LED0..LED7
1526 */
1527 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1528 u32 gpio_val = i40e_led_is_mine(hw, i);
1529
1530 if (!gpio_val)
1531 continue;
1532
1533 /* ignore gpio LED src mode entries related to the activity
1534 * LEDs
1535 */
1536 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1537 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1538 switch (current_mode) {
1539 case I40E_COMBINED_ACTIVITY:
1540 case I40E_FILTER_ACTIVITY:
1541 case I40E_MAC_ACTIVITY:
1542 continue;
1543 default:
1544 break;
1545 }
1546
1547 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1548 /* this & is a bit of paranoia, but serves as a range check */
1549 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1550 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1551
1552 if (mode == I40E_LINK_ACTIVITY)
1553 blink = false;
1554
1555 if (blink)
1556 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1557 else
1558 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1559
1560 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1561 break;
1562 }
1563 }
1564
1565 /* Admin command wrappers */
1566
1567 /**
1568 * i40e_aq_get_phy_capabilities
1569 * @hw: pointer to the hw struct
1570 * @abilities: structure for PHY capabilities to be filled
1571 * @qualified_modules: report Qualified Modules
1572 * @report_init: report init capabilities (active are default)
1573 * @cmd_details: pointer to command details structure or NULL
1574 *
1575 * Returns the various PHY abilities supported on the Port.
1576 **/
1577 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1578 bool qualified_modules, bool report_init,
1579 struct i40e_aq_get_phy_abilities_resp *abilities,
1580 struct i40e_asq_cmd_details *cmd_details)
1581 {
1582 struct i40e_aq_desc desc;
1583 i40e_status status;
1584 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1585
1586 if (!abilities)
1587 return I40E_ERR_PARAM;
1588
1589 i40e_fill_default_direct_cmd_desc(&desc,
1590 i40e_aqc_opc_get_phy_abilities);
1591
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1593 if (abilities_size > I40E_AQ_LARGE_BUF)
1594 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1595
1596 if (qualified_modules)
1597 desc.params.external.param0 |=
1598 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1599
1600 if (report_init)
1601 desc.params.external.param0 |=
1602 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1603
1604 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1605 cmd_details);
1606
1607 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1608 status = I40E_ERR_UNKNOWN_PHY;
1609
1610 if (report_init)
1611 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1612
1613 return status;
1614 }
1615
1616 /**
1617 * i40e_aq_set_phy_config
1618 * @hw: pointer to the hw struct
1619 * @config: structure with PHY configuration to be set
1620 * @cmd_details: pointer to command details structure or NULL
1621 *
1622 * Set the various PHY configuration parameters
1623 * supported on the Port.One or more of the Set PHY config parameters may be
1624 * ignored in an MFP mode as the PF may not have the privilege to set some
1625 * of the PHY Config parameters. This status will be indicated by the
1626 * command response.
1627 **/
1628 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1629 struct i40e_aq_set_phy_config *config,
1630 struct i40e_asq_cmd_details *cmd_details)
1631 {
1632 struct i40e_aq_desc desc;
1633 struct i40e_aq_set_phy_config *cmd =
1634 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1635 enum i40e_status_code status;
1636
1637 if (!config)
1638 return I40E_ERR_PARAM;
1639
1640 i40e_fill_default_direct_cmd_desc(&desc,
1641 i40e_aqc_opc_set_phy_config);
1642
1643 *cmd = *config;
1644
1645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1646
1647 return status;
1648 }
1649
1650 /**
1651 * i40e_set_fc
1652 * @hw: pointer to the hw struct
1653 *
1654 * Set the requested flow control mode using set_phy_config.
1655 **/
1656 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1657 bool atomic_restart)
1658 {
1659 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1660 struct i40e_aq_get_phy_abilities_resp abilities;
1661 struct i40e_aq_set_phy_config config;
1662 enum i40e_status_code status;
1663 u8 pause_mask = 0x0;
1664
1665 *aq_failures = 0x0;
1666
1667 switch (fc_mode) {
1668 case I40E_FC_FULL:
1669 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1670 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1671 break;
1672 case I40E_FC_RX_PAUSE:
1673 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1674 break;
1675 case I40E_FC_TX_PAUSE:
1676 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1677 break;
1678 default:
1679 break;
1680 }
1681
1682 /* Get the current phy config */
1683 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1684 NULL);
1685 if (status) {
1686 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1687 return status;
1688 }
1689
1690 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1691 /* clear the old pause settings */
1692 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1693 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1694 /* set the new abilities */
1695 config.abilities |= pause_mask;
1696 /* If the abilities have changed, then set the new config */
1697 if (config.abilities != abilities.abilities) {
1698 /* Auto restart link so settings take effect */
1699 if (atomic_restart)
1700 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1701 /* Copy over all the old settings */
1702 config.phy_type = abilities.phy_type;
1703 config.link_speed = abilities.link_speed;
1704 config.eee_capability = abilities.eee_capability;
1705 config.eeer = abilities.eeer_val;
1706 config.low_power_ctrl = abilities.d3_lpan;
1707 status = i40e_aq_set_phy_config(hw, &config, NULL);
1708
1709 if (status)
1710 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1711 }
1712 /* Update the link info */
1713 status = i40e_update_link_info(hw);
1714 if (status) {
1715 /* Wait a little bit (on 40G cards it sometimes takes a really
1716 * long time for link to come back from the atomic reset)
1717 * and try once more
1718 */
1719 msleep(1000);
1720 status = i40e_update_link_info(hw);
1721 }
1722 if (status)
1723 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1724
1725 return status;
1726 }
1727
1728 /**
1729 * i40e_aq_clear_pxe_mode
1730 * @hw: pointer to the hw struct
1731 * @cmd_details: pointer to command details structure or NULL
1732 *
1733 * Tell the firmware that the driver is taking over from PXE
1734 **/
1735 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1736 struct i40e_asq_cmd_details *cmd_details)
1737 {
1738 i40e_status status;
1739 struct i40e_aq_desc desc;
1740 struct i40e_aqc_clear_pxe *cmd =
1741 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1742
1743 i40e_fill_default_direct_cmd_desc(&desc,
1744 i40e_aqc_opc_clear_pxe_mode);
1745
1746 cmd->rx_cnt = 0x2;
1747
1748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1749
1750 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1751
1752 return status;
1753 }
1754
1755 /**
1756 * i40e_aq_set_link_restart_an
1757 * @hw: pointer to the hw struct
1758 * @enable_link: if true: enable link, if false: disable link
1759 * @cmd_details: pointer to command details structure or NULL
1760 *
1761 * Sets up the link and restarts the Auto-Negotiation over the link.
1762 **/
1763 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1764 bool enable_link,
1765 struct i40e_asq_cmd_details *cmd_details)
1766 {
1767 struct i40e_aq_desc desc;
1768 struct i40e_aqc_set_link_restart_an *cmd =
1769 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1770 i40e_status status;
1771
1772 i40e_fill_default_direct_cmd_desc(&desc,
1773 i40e_aqc_opc_set_link_restart_an);
1774
1775 cmd->command = I40E_AQ_PHY_RESTART_AN;
1776 if (enable_link)
1777 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1778 else
1779 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1780
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1782
1783 return status;
1784 }
1785
1786 /**
1787 * i40e_aq_get_link_info
1788 * @hw: pointer to the hw struct
1789 * @enable_lse: enable/disable LinkStatusEvent reporting
1790 * @link: pointer to link status structure - optional
1791 * @cmd_details: pointer to command details structure or NULL
1792 *
1793 * Returns the link status of the adapter.
1794 **/
1795 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1796 bool enable_lse, struct i40e_link_status *link,
1797 struct i40e_asq_cmd_details *cmd_details)
1798 {
1799 struct i40e_aq_desc desc;
1800 struct i40e_aqc_get_link_status *resp =
1801 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1802 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1803 i40e_status status;
1804 bool tx_pause, rx_pause;
1805 u16 command_flags;
1806
1807 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1808
1809 if (enable_lse)
1810 command_flags = I40E_AQ_LSE_ENABLE;
1811 else
1812 command_flags = I40E_AQ_LSE_DISABLE;
1813 resp->command_flags = cpu_to_le16(command_flags);
1814
1815 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1816
1817 if (status)
1818 goto aq_get_link_info_exit;
1819
1820 /* save off old link status information */
1821 hw->phy.link_info_old = *hw_link_info;
1822
1823 /* update link status */
1824 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1825 hw->phy.media_type = i40e_get_media_type(hw);
1826 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1827 hw_link_info->link_info = resp->link_info;
1828 hw_link_info->an_info = resp->an_info;
1829 hw_link_info->ext_info = resp->ext_info;
1830 hw_link_info->loopback = resp->loopback;
1831 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1832 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1833
1834 /* update fc info */
1835 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1836 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1837 if (tx_pause & rx_pause)
1838 hw->fc.current_mode = I40E_FC_FULL;
1839 else if (tx_pause)
1840 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1841 else if (rx_pause)
1842 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1843 else
1844 hw->fc.current_mode = I40E_FC_NONE;
1845
1846 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1847 hw_link_info->crc_enable = true;
1848 else
1849 hw_link_info->crc_enable = false;
1850
1851 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1852 hw_link_info->lse_enable = true;
1853 else
1854 hw_link_info->lse_enable = false;
1855
1856 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1857 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1858 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1859
1860 /* save link status information */
1861 if (link)
1862 *link = *hw_link_info;
1863
1864 /* flag cleared so helper functions don't call AQ again */
1865 hw->phy.get_link_info = false;
1866
1867 aq_get_link_info_exit:
1868 return status;
1869 }
1870
1871 /**
1872 * i40e_aq_set_phy_int_mask
1873 * @hw: pointer to the hw struct
1874 * @mask: interrupt mask to be set
1875 * @cmd_details: pointer to command details structure or NULL
1876 *
1877 * Set link interrupt mask.
1878 **/
1879 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1880 u16 mask,
1881 struct i40e_asq_cmd_details *cmd_details)
1882 {
1883 struct i40e_aq_desc desc;
1884 struct i40e_aqc_set_phy_int_mask *cmd =
1885 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1886 i40e_status status;
1887
1888 i40e_fill_default_direct_cmd_desc(&desc,
1889 i40e_aqc_opc_set_phy_int_mask);
1890
1891 cmd->event_mask = cpu_to_le16(mask);
1892
1893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1894
1895 return status;
1896 }
1897
1898 /**
1899 * i40e_aq_set_phy_debug
1900 * @hw: pointer to the hw struct
1901 * @cmd_flags: debug command flags
1902 * @cmd_details: pointer to command details structure or NULL
1903 *
1904 * Reset the external PHY.
1905 **/
1906 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1907 struct i40e_asq_cmd_details *cmd_details)
1908 {
1909 struct i40e_aq_desc desc;
1910 struct i40e_aqc_set_phy_debug *cmd =
1911 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1912 i40e_status status;
1913
1914 i40e_fill_default_direct_cmd_desc(&desc,
1915 i40e_aqc_opc_set_phy_debug);
1916
1917 cmd->command_flags = cmd_flags;
1918
1919 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1920
1921 return status;
1922 }
1923
1924 /**
1925 * i40e_aq_add_vsi
1926 * @hw: pointer to the hw struct
1927 * @vsi_ctx: pointer to a vsi context struct
1928 * @cmd_details: pointer to command details structure or NULL
1929 *
1930 * Add a VSI context to the hardware.
1931 **/
1932 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1933 struct i40e_vsi_context *vsi_ctx,
1934 struct i40e_asq_cmd_details *cmd_details)
1935 {
1936 struct i40e_aq_desc desc;
1937 struct i40e_aqc_add_get_update_vsi *cmd =
1938 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1939 struct i40e_aqc_add_get_update_vsi_completion *resp =
1940 (struct i40e_aqc_add_get_update_vsi_completion *)
1941 &desc.params.raw;
1942 i40e_status status;
1943
1944 i40e_fill_default_direct_cmd_desc(&desc,
1945 i40e_aqc_opc_add_vsi);
1946
1947 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1948 cmd->connection_type = vsi_ctx->connection_type;
1949 cmd->vf_id = vsi_ctx->vf_num;
1950 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1951
1952 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1953
1954 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1955 sizeof(vsi_ctx->info), cmd_details);
1956
1957 if (status)
1958 goto aq_add_vsi_exit;
1959
1960 vsi_ctx->seid = le16_to_cpu(resp->seid);
1961 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1962 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1963 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1964
1965 aq_add_vsi_exit:
1966 return status;
1967 }
1968
1969 /**
1970 * i40e_aq_set_vsi_unicast_promiscuous
1971 * @hw: pointer to the hw struct
1972 * @seid: vsi number
1973 * @set: set unicast promiscuous enable/disable
1974 * @cmd_details: pointer to command details structure or NULL
1975 **/
1976 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1977 u16 seid, bool set,
1978 struct i40e_asq_cmd_details *cmd_details)
1979 {
1980 struct i40e_aq_desc desc;
1981 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1982 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1983 i40e_status status;
1984 u16 flags = 0;
1985
1986 i40e_fill_default_direct_cmd_desc(&desc,
1987 i40e_aqc_opc_set_vsi_promiscuous_modes);
1988
1989 if (set) {
1990 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1991 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
1992 (hw->aq.api_maj_ver > 1))
1993 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
1994 }
1995
1996 cmd->promiscuous_flags = cpu_to_le16(flags);
1997
1998 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1999 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2000 (hw->aq.api_maj_ver > 1))
2001 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2002
2003 cmd->seid = cpu_to_le16(seid);
2004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2005
2006 return status;
2007 }
2008
2009 /**
2010 * i40e_aq_set_vsi_multicast_promiscuous
2011 * @hw: pointer to the hw struct
2012 * @seid: vsi number
2013 * @set: set multicast promiscuous enable/disable
2014 * @cmd_details: pointer to command details structure or NULL
2015 **/
2016 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2017 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2018 {
2019 struct i40e_aq_desc desc;
2020 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2021 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2022 i40e_status status;
2023 u16 flags = 0;
2024
2025 i40e_fill_default_direct_cmd_desc(&desc,
2026 i40e_aqc_opc_set_vsi_promiscuous_modes);
2027
2028 if (set)
2029 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2030
2031 cmd->promiscuous_flags = cpu_to_le16(flags);
2032
2033 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2034
2035 cmd->seid = cpu_to_le16(seid);
2036 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2037
2038 return status;
2039 }
2040
2041 /**
2042 * i40e_aq_set_vsi_mc_promisc_on_vlan
2043 * @hw: pointer to the hw struct
2044 * @seid: vsi number
2045 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2046 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2047 * @cmd_details: pointer to command details structure or NULL
2048 **/
2049 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2050 u16 seid, bool enable,
2051 u16 vid,
2052 struct i40e_asq_cmd_details *cmd_details)
2053 {
2054 struct i40e_aq_desc desc;
2055 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2056 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2057 enum i40e_status_code status;
2058 u16 flags = 0;
2059
2060 i40e_fill_default_direct_cmd_desc(&desc,
2061 i40e_aqc_opc_set_vsi_promiscuous_modes);
2062
2063 if (enable)
2064 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2065
2066 cmd->promiscuous_flags = cpu_to_le16(flags);
2067 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2068 cmd->seid = cpu_to_le16(seid);
2069 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2070
2071 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2072
2073 return status;
2074 }
2075
2076 /**
2077 * i40e_aq_set_vsi_uc_promisc_on_vlan
2078 * @hw: pointer to the hw struct
2079 * @seid: vsi number
2080 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2081 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2082 * @cmd_details: pointer to command details structure or NULL
2083 **/
2084 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2085 u16 seid, bool enable,
2086 u16 vid,
2087 struct i40e_asq_cmd_details *cmd_details)
2088 {
2089 struct i40e_aq_desc desc;
2090 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2091 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2092 enum i40e_status_code status;
2093 u16 flags = 0;
2094
2095 i40e_fill_default_direct_cmd_desc(&desc,
2096 i40e_aqc_opc_set_vsi_promiscuous_modes);
2097
2098 if (enable)
2099 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2100
2101 cmd->promiscuous_flags = cpu_to_le16(flags);
2102 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2103 cmd->seid = cpu_to_le16(seid);
2104 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2105
2106 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2107
2108 return status;
2109 }
2110
2111 /**
2112 * i40e_aq_set_vsi_broadcast
2113 * @hw: pointer to the hw struct
2114 * @seid: vsi number
2115 * @set_filter: true to set filter, false to clear filter
2116 * @cmd_details: pointer to command details structure or NULL
2117 *
2118 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2119 **/
2120 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2121 u16 seid, bool set_filter,
2122 struct i40e_asq_cmd_details *cmd_details)
2123 {
2124 struct i40e_aq_desc desc;
2125 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2126 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2127 i40e_status status;
2128
2129 i40e_fill_default_direct_cmd_desc(&desc,
2130 i40e_aqc_opc_set_vsi_promiscuous_modes);
2131
2132 if (set_filter)
2133 cmd->promiscuous_flags
2134 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2135 else
2136 cmd->promiscuous_flags
2137 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2138
2139 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2140 cmd->seid = cpu_to_le16(seid);
2141 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2142
2143 return status;
2144 }
2145
2146 /**
2147 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2148 * @hw: pointer to the hw struct
2149 * @seid: vsi number
2150 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2151 * @cmd_details: pointer to command details structure or NULL
2152 **/
2153 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2154 u16 seid, bool enable,
2155 struct i40e_asq_cmd_details *cmd_details)
2156 {
2157 struct i40e_aq_desc desc;
2158 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2159 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2160 i40e_status status;
2161 u16 flags = 0;
2162
2163 i40e_fill_default_direct_cmd_desc(&desc,
2164 i40e_aqc_opc_set_vsi_promiscuous_modes);
2165 if (enable)
2166 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2167
2168 cmd->promiscuous_flags = cpu_to_le16(flags);
2169 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2170 cmd->seid = cpu_to_le16(seid);
2171
2172 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2173
2174 return status;
2175 }
2176
2177 /**
2178 * i40e_get_vsi_params - get VSI configuration info
2179 * @hw: pointer to the hw struct
2180 * @vsi_ctx: pointer to a vsi context struct
2181 * @cmd_details: pointer to command details structure or NULL
2182 **/
2183 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2184 struct i40e_vsi_context *vsi_ctx,
2185 struct i40e_asq_cmd_details *cmd_details)
2186 {
2187 struct i40e_aq_desc desc;
2188 struct i40e_aqc_add_get_update_vsi *cmd =
2189 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2190 struct i40e_aqc_add_get_update_vsi_completion *resp =
2191 (struct i40e_aqc_add_get_update_vsi_completion *)
2192 &desc.params.raw;
2193 i40e_status status;
2194
2195 i40e_fill_default_direct_cmd_desc(&desc,
2196 i40e_aqc_opc_get_vsi_parameters);
2197
2198 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2199
2200 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2201
2202 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2203 sizeof(vsi_ctx->info), NULL);
2204
2205 if (status)
2206 goto aq_get_vsi_params_exit;
2207
2208 vsi_ctx->seid = le16_to_cpu(resp->seid);
2209 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2210 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2211 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2212
2213 aq_get_vsi_params_exit:
2214 return status;
2215 }
2216
2217 /**
2218 * i40e_aq_update_vsi_params
2219 * @hw: pointer to the hw struct
2220 * @vsi_ctx: pointer to a vsi context struct
2221 * @cmd_details: pointer to command details structure or NULL
2222 *
2223 * Update a VSI context.
2224 **/
2225 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2226 struct i40e_vsi_context *vsi_ctx,
2227 struct i40e_asq_cmd_details *cmd_details)
2228 {
2229 struct i40e_aq_desc desc;
2230 struct i40e_aqc_add_get_update_vsi *cmd =
2231 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2232 struct i40e_aqc_add_get_update_vsi_completion *resp =
2233 (struct i40e_aqc_add_get_update_vsi_completion *)
2234 &desc.params.raw;
2235 i40e_status status;
2236
2237 i40e_fill_default_direct_cmd_desc(&desc,
2238 i40e_aqc_opc_update_vsi_parameters);
2239 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2240
2241 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2242
2243 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2244 sizeof(vsi_ctx->info), cmd_details);
2245
2246 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2247 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2248
2249 return status;
2250 }
2251
2252 /**
2253 * i40e_aq_get_switch_config
2254 * @hw: pointer to the hardware structure
2255 * @buf: pointer to the result buffer
2256 * @buf_size: length of input buffer
2257 * @start_seid: seid to start for the report, 0 == beginning
2258 * @cmd_details: pointer to command details structure or NULL
2259 *
2260 * Fill the buf with switch configuration returned from AdminQ command
2261 **/
2262 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2263 struct i40e_aqc_get_switch_config_resp *buf,
2264 u16 buf_size, u16 *start_seid,
2265 struct i40e_asq_cmd_details *cmd_details)
2266 {
2267 struct i40e_aq_desc desc;
2268 struct i40e_aqc_switch_seid *scfg =
2269 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2270 i40e_status status;
2271
2272 i40e_fill_default_direct_cmd_desc(&desc,
2273 i40e_aqc_opc_get_switch_config);
2274 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2275 if (buf_size > I40E_AQ_LARGE_BUF)
2276 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2277 scfg->seid = cpu_to_le16(*start_seid);
2278
2279 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2280 *start_seid = le16_to_cpu(scfg->seid);
2281
2282 return status;
2283 }
2284
2285 /**
2286 * i40e_aq_get_firmware_version
2287 * @hw: pointer to the hw struct
2288 * @fw_major_version: firmware major version
2289 * @fw_minor_version: firmware minor version
2290 * @fw_build: firmware build number
2291 * @api_major_version: major queue version
2292 * @api_minor_version: minor queue version
2293 * @cmd_details: pointer to command details structure or NULL
2294 *
2295 * Get the firmware version from the admin queue commands
2296 **/
2297 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2298 u16 *fw_major_version, u16 *fw_minor_version,
2299 u32 *fw_build,
2300 u16 *api_major_version, u16 *api_minor_version,
2301 struct i40e_asq_cmd_details *cmd_details)
2302 {
2303 struct i40e_aq_desc desc;
2304 struct i40e_aqc_get_version *resp =
2305 (struct i40e_aqc_get_version *)&desc.params.raw;
2306 i40e_status status;
2307
2308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2309
2310 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2311
2312 if (!status) {
2313 if (fw_major_version)
2314 *fw_major_version = le16_to_cpu(resp->fw_major);
2315 if (fw_minor_version)
2316 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2317 if (fw_build)
2318 *fw_build = le32_to_cpu(resp->fw_build);
2319 if (api_major_version)
2320 *api_major_version = le16_to_cpu(resp->api_major);
2321 if (api_minor_version)
2322 *api_minor_version = le16_to_cpu(resp->api_minor);
2323 }
2324
2325 return status;
2326 }
2327
2328 /**
2329 * i40e_aq_send_driver_version
2330 * @hw: pointer to the hw struct
2331 * @dv: driver's major, minor version
2332 * @cmd_details: pointer to command details structure or NULL
2333 *
2334 * Send the driver version to the firmware
2335 **/
2336 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2337 struct i40e_driver_version *dv,
2338 struct i40e_asq_cmd_details *cmd_details)
2339 {
2340 struct i40e_aq_desc desc;
2341 struct i40e_aqc_driver_version *cmd =
2342 (struct i40e_aqc_driver_version *)&desc.params.raw;
2343 i40e_status status;
2344 u16 len;
2345
2346 if (dv == NULL)
2347 return I40E_ERR_PARAM;
2348
2349 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2350
2351 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2352 cmd->driver_major_ver = dv->major_version;
2353 cmd->driver_minor_ver = dv->minor_version;
2354 cmd->driver_build_ver = dv->build_version;
2355 cmd->driver_subbuild_ver = dv->subbuild_version;
2356
2357 len = 0;
2358 while (len < sizeof(dv->driver_string) &&
2359 (dv->driver_string[len] < 0x80) &&
2360 dv->driver_string[len])
2361 len++;
2362 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2363 len, cmd_details);
2364
2365 return status;
2366 }
2367
2368 /**
2369 * i40e_get_link_status - get status of the HW network link
2370 * @hw: pointer to the hw struct
2371 * @link_up: pointer to bool (true/false = linkup/linkdown)
2372 *
2373 * Variable link_up true if link is up, false if link is down.
2374 * The variable link_up is invalid if returned value of status != 0
2375 *
2376 * Side effect: LinkStatusEvent reporting becomes enabled
2377 **/
2378 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2379 {
2380 i40e_status status = 0;
2381
2382 if (hw->phy.get_link_info) {
2383 status = i40e_update_link_info(hw);
2384
2385 if (status)
2386 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2387 status);
2388 }
2389
2390 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2391
2392 return status;
2393 }
2394
2395 /**
2396 * i40e_updatelink_status - update status of the HW network link
2397 * @hw: pointer to the hw struct
2398 **/
2399 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2400 {
2401 struct i40e_aq_get_phy_abilities_resp abilities;
2402 i40e_status status = 0;
2403
2404 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2405 if (status)
2406 return status;
2407
2408 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2409 status = i40e_aq_get_phy_capabilities(hw, false, false,
2410 &abilities, NULL);
2411 if (status)
2412 return status;
2413
2414 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2415 sizeof(hw->phy.link_info.module_type));
2416 }
2417
2418 return status;
2419 }
2420
2421 /**
2422 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2423 * @hw: pointer to the hw struct
2424 * @uplink_seid: the MAC or other gizmo SEID
2425 * @downlink_seid: the VSI SEID
2426 * @enabled_tc: bitmap of TCs to be enabled
2427 * @default_port: true for default port VSI, false for control port
2428 * @veb_seid: pointer to where to put the resulting VEB SEID
2429 * @enable_stats: true to turn on VEB stats
2430 * @cmd_details: pointer to command details structure or NULL
2431 *
2432 * This asks the FW to add a VEB between the uplink and downlink
2433 * elements. If the uplink SEID is 0, this will be a floating VEB.
2434 **/
2435 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2436 u16 downlink_seid, u8 enabled_tc,
2437 bool default_port, u16 *veb_seid,
2438 bool enable_stats,
2439 struct i40e_asq_cmd_details *cmd_details)
2440 {
2441 struct i40e_aq_desc desc;
2442 struct i40e_aqc_add_veb *cmd =
2443 (struct i40e_aqc_add_veb *)&desc.params.raw;
2444 struct i40e_aqc_add_veb_completion *resp =
2445 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2446 i40e_status status;
2447 u16 veb_flags = 0;
2448
2449 /* SEIDs need to either both be set or both be 0 for floating VEB */
2450 if (!!uplink_seid != !!downlink_seid)
2451 return I40E_ERR_PARAM;
2452
2453 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2454
2455 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2456 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2457 cmd->enable_tcs = enabled_tc;
2458 if (!uplink_seid)
2459 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2460 if (default_port)
2461 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2462 else
2463 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2464
2465 /* reverse logic here: set the bitflag to disable the stats */
2466 if (!enable_stats)
2467 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2468
2469 cmd->veb_flags = cpu_to_le16(veb_flags);
2470
2471 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2472
2473 if (!status && veb_seid)
2474 *veb_seid = le16_to_cpu(resp->veb_seid);
2475
2476 return status;
2477 }
2478
2479 /**
2480 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2481 * @hw: pointer to the hw struct
2482 * @veb_seid: the SEID of the VEB to query
2483 * @switch_id: the uplink switch id
2484 * @floating: set to true if the VEB is floating
2485 * @statistic_index: index of the stats counter block for this VEB
2486 * @vebs_used: number of VEB's used by function
2487 * @vebs_free: total VEB's not reserved by any function
2488 * @cmd_details: pointer to command details structure or NULL
2489 *
2490 * This retrieves the parameters for a particular VEB, specified by
2491 * uplink_seid, and returns them to the caller.
2492 **/
2493 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2494 u16 veb_seid, u16 *switch_id,
2495 bool *floating, u16 *statistic_index,
2496 u16 *vebs_used, u16 *vebs_free,
2497 struct i40e_asq_cmd_details *cmd_details)
2498 {
2499 struct i40e_aq_desc desc;
2500 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2501 (struct i40e_aqc_get_veb_parameters_completion *)
2502 &desc.params.raw;
2503 i40e_status status;
2504
2505 if (veb_seid == 0)
2506 return I40E_ERR_PARAM;
2507
2508 i40e_fill_default_direct_cmd_desc(&desc,
2509 i40e_aqc_opc_get_veb_parameters);
2510 cmd_resp->seid = cpu_to_le16(veb_seid);
2511
2512 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2513 if (status)
2514 goto get_veb_exit;
2515
2516 if (switch_id)
2517 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2518 if (statistic_index)
2519 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2520 if (vebs_used)
2521 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2522 if (vebs_free)
2523 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2524 if (floating) {
2525 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2526
2527 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2528 *floating = true;
2529 else
2530 *floating = false;
2531 }
2532
2533 get_veb_exit:
2534 return status;
2535 }
2536
2537 /**
2538 * i40e_aq_add_macvlan
2539 * @hw: pointer to the hw struct
2540 * @seid: VSI for the mac address
2541 * @mv_list: list of macvlans to be added
2542 * @count: length of the list
2543 * @cmd_details: pointer to command details structure or NULL
2544 *
2545 * Add MAC/VLAN addresses to the HW filtering
2546 **/
2547 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2548 struct i40e_aqc_add_macvlan_element_data *mv_list,
2549 u16 count, struct i40e_asq_cmd_details *cmd_details)
2550 {
2551 struct i40e_aq_desc desc;
2552 struct i40e_aqc_macvlan *cmd =
2553 (struct i40e_aqc_macvlan *)&desc.params.raw;
2554 i40e_status status;
2555 u16 buf_size;
2556 int i;
2557
2558 if (count == 0 || !mv_list || !hw)
2559 return I40E_ERR_PARAM;
2560
2561 buf_size = count * sizeof(*mv_list);
2562
2563 /* prep the rest of the request */
2564 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2565 cmd->num_addresses = cpu_to_le16(count);
2566 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2567 cmd->seid[1] = 0;
2568 cmd->seid[2] = 0;
2569
2570 for (i = 0; i < count; i++)
2571 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2572 mv_list[i].flags |=
2573 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2574
2575 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2576 if (buf_size > I40E_AQ_LARGE_BUF)
2577 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2578
2579 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2580 cmd_details);
2581
2582 return status;
2583 }
2584
2585 /**
2586 * i40e_aq_remove_macvlan
2587 * @hw: pointer to the hw struct
2588 * @seid: VSI for the mac address
2589 * @mv_list: list of macvlans to be removed
2590 * @count: length of the list
2591 * @cmd_details: pointer to command details structure or NULL
2592 *
2593 * Remove MAC/VLAN addresses from the HW filtering
2594 **/
2595 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2596 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2597 u16 count, struct i40e_asq_cmd_details *cmd_details)
2598 {
2599 struct i40e_aq_desc desc;
2600 struct i40e_aqc_macvlan *cmd =
2601 (struct i40e_aqc_macvlan *)&desc.params.raw;
2602 i40e_status status;
2603 u16 buf_size;
2604
2605 if (count == 0 || !mv_list || !hw)
2606 return I40E_ERR_PARAM;
2607
2608 buf_size = count * sizeof(*mv_list);
2609
2610 /* prep the rest of the request */
2611 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2612 cmd->num_addresses = cpu_to_le16(count);
2613 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2614 cmd->seid[1] = 0;
2615 cmd->seid[2] = 0;
2616
2617 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2618 if (buf_size > I40E_AQ_LARGE_BUF)
2619 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2620
2621 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2622 cmd_details);
2623
2624 return status;
2625 }
2626
2627 /**
2628 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2629 * @hw: pointer to the hw struct
2630 * @opcode: AQ opcode for add or delete mirror rule
2631 * @sw_seid: Switch SEID (to which rule refers)
2632 * @rule_type: Rule Type (ingress/egress/VLAN)
2633 * @id: Destination VSI SEID or Rule ID
2634 * @count: length of the list
2635 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2636 * @cmd_details: pointer to command details structure or NULL
2637 * @rule_id: Rule ID returned from FW
2638 * @rule_used: Number of rules used in internal switch
2639 * @rule_free: Number of rules free in internal switch
2640 *
2641 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2642 * VEBs/VEPA elements only
2643 **/
2644 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2645 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2646 u16 count, __le16 *mr_list,
2647 struct i40e_asq_cmd_details *cmd_details,
2648 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2649 {
2650 struct i40e_aq_desc desc;
2651 struct i40e_aqc_add_delete_mirror_rule *cmd =
2652 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2653 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2654 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2655 i40e_status status;
2656 u16 buf_size;
2657
2658 buf_size = count * sizeof(*mr_list);
2659
2660 /* prep the rest of the request */
2661 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2662 cmd->seid = cpu_to_le16(sw_seid);
2663 cmd->rule_type = cpu_to_le16(rule_type &
2664 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2665 cmd->num_entries = cpu_to_le16(count);
2666 /* Dest VSI for add, rule_id for delete */
2667 cmd->destination = cpu_to_le16(id);
2668 if (mr_list) {
2669 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2670 I40E_AQ_FLAG_RD));
2671 if (buf_size > I40E_AQ_LARGE_BUF)
2672 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2673 }
2674
2675 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2676 cmd_details);
2677 if (!status ||
2678 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2679 if (rule_id)
2680 *rule_id = le16_to_cpu(resp->rule_id);
2681 if (rules_used)
2682 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2683 if (rules_free)
2684 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2685 }
2686 return status;
2687 }
2688
2689 /**
2690 * i40e_aq_add_mirrorrule - add a mirror rule
2691 * @hw: pointer to the hw struct
2692 * @sw_seid: Switch SEID (to which rule refers)
2693 * @rule_type: Rule Type (ingress/egress/VLAN)
2694 * @dest_vsi: SEID of VSI to which packets will be mirrored
2695 * @count: length of the list
2696 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2697 * @cmd_details: pointer to command details structure or NULL
2698 * @rule_id: Rule ID returned from FW
2699 * @rule_used: Number of rules used in internal switch
2700 * @rule_free: Number of rules free in internal switch
2701 *
2702 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2703 **/
2704 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2705 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2706 struct i40e_asq_cmd_details *cmd_details,
2707 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2708 {
2709 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2710 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2711 if (count == 0 || !mr_list)
2712 return I40E_ERR_PARAM;
2713 }
2714
2715 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2716 rule_type, dest_vsi, count, mr_list,
2717 cmd_details, rule_id, rules_used, rules_free);
2718 }
2719
2720 /**
2721 * i40e_aq_delete_mirrorrule - delete a mirror rule
2722 * @hw: pointer to the hw struct
2723 * @sw_seid: Switch SEID (to which rule refers)
2724 * @rule_type: Rule Type (ingress/egress/VLAN)
2725 * @count: length of the list
2726 * @rule_id: Rule ID that is returned in the receive desc as part of
2727 * add_mirrorrule.
2728 * @mr_list: list of mirrored VLAN IDs to be removed
2729 * @cmd_details: pointer to command details structure or NULL
2730 * @rule_used: Number of rules used in internal switch
2731 * @rule_free: Number of rules free in internal switch
2732 *
2733 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2734 **/
2735 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2736 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2737 struct i40e_asq_cmd_details *cmd_details,
2738 u16 *rules_used, u16 *rules_free)
2739 {
2740 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2741 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2742 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2743 * mirroring. For other rule_type, count and rule_type should
2744 * not matter.
2745 */
2746 if (count == 0 || !mr_list)
2747 return I40E_ERR_PARAM;
2748 }
2749
2750 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2751 rule_type, rule_id, count, mr_list,
2752 cmd_details, NULL, rules_used, rules_free);
2753 }
2754
2755 /**
2756 * i40e_aq_send_msg_to_vf
2757 * @hw: pointer to the hardware structure
2758 * @vfid: VF id to send msg
2759 * @v_opcode: opcodes for VF-PF communication
2760 * @v_retval: return error code
2761 * @msg: pointer to the msg buffer
2762 * @msglen: msg length
2763 * @cmd_details: pointer to command details
2764 *
2765 * send msg to vf
2766 **/
2767 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2768 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2769 struct i40e_asq_cmd_details *cmd_details)
2770 {
2771 struct i40e_aq_desc desc;
2772 struct i40e_aqc_pf_vf_message *cmd =
2773 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2774 i40e_status status;
2775
2776 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2777 cmd->id = cpu_to_le32(vfid);
2778 desc.cookie_high = cpu_to_le32(v_opcode);
2779 desc.cookie_low = cpu_to_le32(v_retval);
2780 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2781 if (msglen) {
2782 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2783 I40E_AQ_FLAG_RD));
2784 if (msglen > I40E_AQ_LARGE_BUF)
2785 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2786 desc.datalen = cpu_to_le16(msglen);
2787 }
2788 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2789
2790 return status;
2791 }
2792
2793 /**
2794 * i40e_aq_debug_read_register
2795 * @hw: pointer to the hw struct
2796 * @reg_addr: register address
2797 * @reg_val: register value
2798 * @cmd_details: pointer to command details structure or NULL
2799 *
2800 * Read the register using the admin queue commands
2801 **/
2802 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2803 u32 reg_addr, u64 *reg_val,
2804 struct i40e_asq_cmd_details *cmd_details)
2805 {
2806 struct i40e_aq_desc desc;
2807 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2808 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2809 i40e_status status;
2810
2811 if (reg_val == NULL)
2812 return I40E_ERR_PARAM;
2813
2814 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2815
2816 cmd_resp->address = cpu_to_le32(reg_addr);
2817
2818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2819
2820 if (!status) {
2821 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2822 (u64)le32_to_cpu(cmd_resp->value_low);
2823 }
2824
2825 return status;
2826 }
2827
2828 /**
2829 * i40e_aq_debug_write_register
2830 * @hw: pointer to the hw struct
2831 * @reg_addr: register address
2832 * @reg_val: register value
2833 * @cmd_details: pointer to command details structure or NULL
2834 *
2835 * Write to a register using the admin queue commands
2836 **/
2837 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2838 u32 reg_addr, u64 reg_val,
2839 struct i40e_asq_cmd_details *cmd_details)
2840 {
2841 struct i40e_aq_desc desc;
2842 struct i40e_aqc_debug_reg_read_write *cmd =
2843 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2844 i40e_status status;
2845
2846 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2847
2848 cmd->address = cpu_to_le32(reg_addr);
2849 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2850 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2851
2852 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2853
2854 return status;
2855 }
2856
2857 /**
2858 * i40e_aq_request_resource
2859 * @hw: pointer to the hw struct
2860 * @resource: resource id
2861 * @access: access type
2862 * @sdp_number: resource number
2863 * @timeout: the maximum time in ms that the driver may hold the resource
2864 * @cmd_details: pointer to command details structure or NULL
2865 *
2866 * requests common resource using the admin queue commands
2867 **/
2868 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2869 enum i40e_aq_resources_ids resource,
2870 enum i40e_aq_resource_access_type access,
2871 u8 sdp_number, u64 *timeout,
2872 struct i40e_asq_cmd_details *cmd_details)
2873 {
2874 struct i40e_aq_desc desc;
2875 struct i40e_aqc_request_resource *cmd_resp =
2876 (struct i40e_aqc_request_resource *)&desc.params.raw;
2877 i40e_status status;
2878
2879 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2880
2881 cmd_resp->resource_id = cpu_to_le16(resource);
2882 cmd_resp->access_type = cpu_to_le16(access);
2883 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2884
2885 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2886 /* The completion specifies the maximum time in ms that the driver
2887 * may hold the resource in the Timeout field.
2888 * If the resource is held by someone else, the command completes with
2889 * busy return value and the timeout field indicates the maximum time
2890 * the current owner of the resource has to free it.
2891 */
2892 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2893 *timeout = le32_to_cpu(cmd_resp->timeout);
2894
2895 return status;
2896 }
2897
2898 /**
2899 * i40e_aq_release_resource
2900 * @hw: pointer to the hw struct
2901 * @resource: resource id
2902 * @sdp_number: resource number
2903 * @cmd_details: pointer to command details structure or NULL
2904 *
2905 * release common resource using the admin queue commands
2906 **/
2907 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2908 enum i40e_aq_resources_ids resource,
2909 u8 sdp_number,
2910 struct i40e_asq_cmd_details *cmd_details)
2911 {
2912 struct i40e_aq_desc desc;
2913 struct i40e_aqc_request_resource *cmd =
2914 (struct i40e_aqc_request_resource *)&desc.params.raw;
2915 i40e_status status;
2916
2917 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2918
2919 cmd->resource_id = cpu_to_le16(resource);
2920 cmd->resource_number = cpu_to_le32(sdp_number);
2921
2922 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2923
2924 return status;
2925 }
2926
2927 /**
2928 * i40e_aq_read_nvm
2929 * @hw: pointer to the hw struct
2930 * @module_pointer: module pointer location in words from the NVM beginning
2931 * @offset: byte offset from the module beginning
2932 * @length: length of the section to be read (in bytes from the offset)
2933 * @data: command buffer (size [bytes] = length)
2934 * @last_command: tells if this is the last command in a series
2935 * @cmd_details: pointer to command details structure or NULL
2936 *
2937 * Read the NVM using the admin queue commands
2938 **/
2939 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2940 u32 offset, u16 length, void *data,
2941 bool last_command,
2942 struct i40e_asq_cmd_details *cmd_details)
2943 {
2944 struct i40e_aq_desc desc;
2945 struct i40e_aqc_nvm_update *cmd =
2946 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2947 i40e_status status;
2948
2949 /* In offset the highest byte must be zeroed. */
2950 if (offset & 0xFF000000) {
2951 status = I40E_ERR_PARAM;
2952 goto i40e_aq_read_nvm_exit;
2953 }
2954
2955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2956
2957 /* If this is the last command in a series, set the proper flag. */
2958 if (last_command)
2959 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2960 cmd->module_pointer = module_pointer;
2961 cmd->offset = cpu_to_le32(offset);
2962 cmd->length = cpu_to_le16(length);
2963
2964 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2965 if (length > I40E_AQ_LARGE_BUF)
2966 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2967
2968 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2969
2970 i40e_aq_read_nvm_exit:
2971 return status;
2972 }
2973
2974 /**
2975 * i40e_aq_erase_nvm
2976 * @hw: pointer to the hw struct
2977 * @module_pointer: module pointer location in words from the NVM beginning
2978 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2979 * @length: length of the section to be erased (expressed in 4 KB)
2980 * @last_command: tells if this is the last command in a series
2981 * @cmd_details: pointer to command details structure or NULL
2982 *
2983 * Erase the NVM sector using the admin queue commands
2984 **/
2985 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2986 u32 offset, u16 length, bool last_command,
2987 struct i40e_asq_cmd_details *cmd_details)
2988 {
2989 struct i40e_aq_desc desc;
2990 struct i40e_aqc_nvm_update *cmd =
2991 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2992 i40e_status status;
2993
2994 /* In offset the highest byte must be zeroed. */
2995 if (offset & 0xFF000000) {
2996 status = I40E_ERR_PARAM;
2997 goto i40e_aq_erase_nvm_exit;
2998 }
2999
3000 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3001
3002 /* If this is the last command in a series, set the proper flag. */
3003 if (last_command)
3004 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3005 cmd->module_pointer = module_pointer;
3006 cmd->offset = cpu_to_le32(offset);
3007 cmd->length = cpu_to_le16(length);
3008
3009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3010
3011 i40e_aq_erase_nvm_exit:
3012 return status;
3013 }
3014
3015 /**
3016 * i40e_parse_discover_capabilities
3017 * @hw: pointer to the hw struct
3018 * @buff: pointer to a buffer containing device/function capability records
3019 * @cap_count: number of capability records in the list
3020 * @list_type_opc: type of capabilities list to parse
3021 *
3022 * Parse the device/function capabilities list.
3023 **/
3024 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3025 u32 cap_count,
3026 enum i40e_admin_queue_opc list_type_opc)
3027 {
3028 struct i40e_aqc_list_capabilities_element_resp *cap;
3029 u32 valid_functions, num_functions;
3030 u32 number, logical_id, phys_id;
3031 struct i40e_hw_capabilities *p;
3032 u8 major_rev;
3033 u32 i = 0;
3034 u16 id;
3035
3036 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3037
3038 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3039 p = &hw->dev_caps;
3040 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3041 p = &hw->func_caps;
3042 else
3043 return;
3044
3045 for (i = 0; i < cap_count; i++, cap++) {
3046 id = le16_to_cpu(cap->id);
3047 number = le32_to_cpu(cap->number);
3048 logical_id = le32_to_cpu(cap->logical_id);
3049 phys_id = le32_to_cpu(cap->phys_id);
3050 major_rev = cap->major_rev;
3051
3052 switch (id) {
3053 case I40E_AQ_CAP_ID_SWITCH_MODE:
3054 p->switch_mode = number;
3055 break;
3056 case I40E_AQ_CAP_ID_MNG_MODE:
3057 p->management_mode = number;
3058 break;
3059 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3060 p->npar_enable = number;
3061 break;
3062 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3063 p->os2bmc = number;
3064 break;
3065 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3066 p->valid_functions = number;
3067 break;
3068 case I40E_AQ_CAP_ID_SRIOV:
3069 if (number == 1)
3070 p->sr_iov_1_1 = true;
3071 break;
3072 case I40E_AQ_CAP_ID_VF:
3073 p->num_vfs = number;
3074 p->vf_base_id = logical_id;
3075 break;
3076 case I40E_AQ_CAP_ID_VMDQ:
3077 if (number == 1)
3078 p->vmdq = true;
3079 break;
3080 case I40E_AQ_CAP_ID_8021QBG:
3081 if (number == 1)
3082 p->evb_802_1_qbg = true;
3083 break;
3084 case I40E_AQ_CAP_ID_8021QBR:
3085 if (number == 1)
3086 p->evb_802_1_qbh = true;
3087 break;
3088 case I40E_AQ_CAP_ID_VSI:
3089 p->num_vsis = number;
3090 break;
3091 case I40E_AQ_CAP_ID_DCB:
3092 if (number == 1) {
3093 p->dcb = true;
3094 p->enabled_tcmap = logical_id;
3095 p->maxtc = phys_id;
3096 }
3097 break;
3098 case I40E_AQ_CAP_ID_FCOE:
3099 if (number == 1)
3100 p->fcoe = true;
3101 break;
3102 case I40E_AQ_CAP_ID_ISCSI:
3103 if (number == 1)
3104 p->iscsi = true;
3105 break;
3106 case I40E_AQ_CAP_ID_RSS:
3107 p->rss = true;
3108 p->rss_table_size = number;
3109 p->rss_table_entry_width = logical_id;
3110 break;
3111 case I40E_AQ_CAP_ID_RXQ:
3112 p->num_rx_qp = number;
3113 p->base_queue = phys_id;
3114 break;
3115 case I40E_AQ_CAP_ID_TXQ:
3116 p->num_tx_qp = number;
3117 p->base_queue = phys_id;
3118 break;
3119 case I40E_AQ_CAP_ID_MSIX:
3120 p->num_msix_vectors = number;
3121 i40e_debug(hw, I40E_DEBUG_INIT,
3122 "HW Capability: MSIX vector count = %d\n",
3123 p->num_msix_vectors);
3124 break;
3125 case I40E_AQ_CAP_ID_VF_MSIX:
3126 p->num_msix_vectors_vf = number;
3127 break;
3128 case I40E_AQ_CAP_ID_FLEX10:
3129 if (major_rev == 1) {
3130 if (number == 1) {
3131 p->flex10_enable = true;
3132 p->flex10_capable = true;
3133 }
3134 } else {
3135 /* Capability revision >= 2 */
3136 if (number & 1)
3137 p->flex10_enable = true;
3138 if (number & 2)
3139 p->flex10_capable = true;
3140 }
3141 p->flex10_mode = logical_id;
3142 p->flex10_status = phys_id;
3143 break;
3144 case I40E_AQ_CAP_ID_CEM:
3145 if (number == 1)
3146 p->mgmt_cem = true;
3147 break;
3148 case I40E_AQ_CAP_ID_IWARP:
3149 if (number == 1)
3150 p->iwarp = true;
3151 break;
3152 case I40E_AQ_CAP_ID_LED:
3153 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3154 p->led[phys_id] = true;
3155 break;
3156 case I40E_AQ_CAP_ID_SDP:
3157 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3158 p->sdp[phys_id] = true;
3159 break;
3160 case I40E_AQ_CAP_ID_MDIO:
3161 if (number == 1) {
3162 p->mdio_port_num = phys_id;
3163 p->mdio_port_mode = logical_id;
3164 }
3165 break;
3166 case I40E_AQ_CAP_ID_1588:
3167 if (number == 1)
3168 p->ieee_1588 = true;
3169 break;
3170 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3171 p->fd = true;
3172 p->fd_filters_guaranteed = number;
3173 p->fd_filters_best_effort = logical_id;
3174 break;
3175 case I40E_AQ_CAP_ID_WSR_PROT:
3176 p->wr_csr_prot = (u64)number;
3177 p->wr_csr_prot |= (u64)logical_id << 32;
3178 break;
3179 case I40E_AQ_CAP_ID_NVM_MGMT:
3180 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3181 p->sec_rev_disabled = true;
3182 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3183 p->update_disabled = true;
3184 break;
3185 default:
3186 break;
3187 }
3188 }
3189
3190 if (p->fcoe)
3191 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3192
3193 /* Software override ensuring FCoE is disabled if npar or mfp
3194 * mode because it is not supported in these modes.
3195 */
3196 if (p->npar_enable || p->flex10_enable)
3197 p->fcoe = false;
3198
3199 /* count the enabled ports (aka the "not disabled" ports) */
3200 hw->num_ports = 0;
3201 for (i = 0; i < 4; i++) {
3202 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3203 u64 port_cfg = 0;
3204
3205 /* use AQ read to get the physical register offset instead
3206 * of the port relative offset
3207 */
3208 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3209 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3210 hw->num_ports++;
3211 }
3212
3213 valid_functions = p->valid_functions;
3214 num_functions = 0;
3215 while (valid_functions) {
3216 if (valid_functions & 1)
3217 num_functions++;
3218 valid_functions >>= 1;
3219 }
3220
3221 /* partition id is 1-based, and functions are evenly spread
3222 * across the ports as partitions
3223 */
3224 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3225 hw->num_partitions = num_functions / hw->num_ports;
3226
3227 /* additional HW specific goodies that might
3228 * someday be HW version specific
3229 */
3230 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3231 }
3232
3233 /**
3234 * i40e_aq_discover_capabilities
3235 * @hw: pointer to the hw struct
3236 * @buff: a virtual buffer to hold the capabilities
3237 * @buff_size: Size of the virtual buffer
3238 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3239 * @list_type_opc: capabilities type to discover - pass in the command opcode
3240 * @cmd_details: pointer to command details structure or NULL
3241 *
3242 * Get the device capabilities descriptions from the firmware
3243 **/
3244 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3245 void *buff, u16 buff_size, u16 *data_size,
3246 enum i40e_admin_queue_opc list_type_opc,
3247 struct i40e_asq_cmd_details *cmd_details)
3248 {
3249 struct i40e_aqc_list_capabilites *cmd;
3250 struct i40e_aq_desc desc;
3251 i40e_status status = 0;
3252
3253 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3254
3255 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3256 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3257 status = I40E_ERR_PARAM;
3258 goto exit;
3259 }
3260
3261 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3262
3263 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3264 if (buff_size > I40E_AQ_LARGE_BUF)
3265 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3266
3267 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3268 *data_size = le16_to_cpu(desc.datalen);
3269
3270 if (status)
3271 goto exit;
3272
3273 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3274 list_type_opc);
3275
3276 exit:
3277 return status;
3278 }
3279
3280 /**
3281 * i40e_aq_update_nvm
3282 * @hw: pointer to the hw struct
3283 * @module_pointer: module pointer location in words from the NVM beginning
3284 * @offset: byte offset from the module beginning
3285 * @length: length of the section to be written (in bytes from the offset)
3286 * @data: command buffer (size [bytes] = length)
3287 * @last_command: tells if this is the last command in a series
3288 * @cmd_details: pointer to command details structure or NULL
3289 *
3290 * Update the NVM using the admin queue commands
3291 **/
3292 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3293 u32 offset, u16 length, void *data,
3294 bool last_command,
3295 struct i40e_asq_cmd_details *cmd_details)
3296 {
3297 struct i40e_aq_desc desc;
3298 struct i40e_aqc_nvm_update *cmd =
3299 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3300 i40e_status status;
3301
3302 /* In offset the highest byte must be zeroed. */
3303 if (offset & 0xFF000000) {
3304 status = I40E_ERR_PARAM;
3305 goto i40e_aq_update_nvm_exit;
3306 }
3307
3308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3309
3310 /* If this is the last command in a series, set the proper flag. */
3311 if (last_command)
3312 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3313 cmd->module_pointer = module_pointer;
3314 cmd->offset = cpu_to_le32(offset);
3315 cmd->length = cpu_to_le16(length);
3316
3317 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3318 if (length > I40E_AQ_LARGE_BUF)
3319 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3320
3321 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3322
3323 i40e_aq_update_nvm_exit:
3324 return status;
3325 }
3326
3327 /**
3328 * i40e_aq_get_lldp_mib
3329 * @hw: pointer to the hw struct
3330 * @bridge_type: type of bridge requested
3331 * @mib_type: Local, Remote or both Local and Remote MIBs
3332 * @buff: pointer to a user supplied buffer to store the MIB block
3333 * @buff_size: size of the buffer (in bytes)
3334 * @local_len : length of the returned Local LLDP MIB
3335 * @remote_len: length of the returned Remote LLDP MIB
3336 * @cmd_details: pointer to command details structure or NULL
3337 *
3338 * Requests the complete LLDP MIB (entire packet).
3339 **/
3340 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3341 u8 mib_type, void *buff, u16 buff_size,
3342 u16 *local_len, u16 *remote_len,
3343 struct i40e_asq_cmd_details *cmd_details)
3344 {
3345 struct i40e_aq_desc desc;
3346 struct i40e_aqc_lldp_get_mib *cmd =
3347 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3348 struct i40e_aqc_lldp_get_mib *resp =
3349 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3350 i40e_status status;
3351
3352 if (buff_size == 0 || !buff)
3353 return I40E_ERR_PARAM;
3354
3355 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3356 /* Indirect Command */
3357 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3358
3359 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3360 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3361 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3362
3363 desc.datalen = cpu_to_le16(buff_size);
3364
3365 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3366 if (buff_size > I40E_AQ_LARGE_BUF)
3367 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3368
3369 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3370 if (!status) {
3371 if (local_len != NULL)
3372 *local_len = le16_to_cpu(resp->local_len);
3373 if (remote_len != NULL)
3374 *remote_len = le16_to_cpu(resp->remote_len);
3375 }
3376
3377 return status;
3378 }
3379
3380 /**
3381 * i40e_aq_cfg_lldp_mib_change_event
3382 * @hw: pointer to the hw struct
3383 * @enable_update: Enable or Disable event posting
3384 * @cmd_details: pointer to command details structure or NULL
3385 *
3386 * Enable or Disable posting of an event on ARQ when LLDP MIB
3387 * associated with the interface changes
3388 **/
3389 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3390 bool enable_update,
3391 struct i40e_asq_cmd_details *cmd_details)
3392 {
3393 struct i40e_aq_desc desc;
3394 struct i40e_aqc_lldp_update_mib *cmd =
3395 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3396 i40e_status status;
3397
3398 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3399
3400 if (!enable_update)
3401 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3402
3403 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3404
3405 return status;
3406 }
3407
3408 /**
3409 * i40e_aq_stop_lldp
3410 * @hw: pointer to the hw struct
3411 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3412 * @cmd_details: pointer to command details structure or NULL
3413 *
3414 * Stop or Shutdown the embedded LLDP Agent
3415 **/
3416 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3417 struct i40e_asq_cmd_details *cmd_details)
3418 {
3419 struct i40e_aq_desc desc;
3420 struct i40e_aqc_lldp_stop *cmd =
3421 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3422 i40e_status status;
3423
3424 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3425
3426 if (shutdown_agent)
3427 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3428
3429 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3430
3431 return status;
3432 }
3433
3434 /**
3435 * i40e_aq_start_lldp
3436 * @hw: pointer to the hw struct
3437 * @cmd_details: pointer to command details structure or NULL
3438 *
3439 * Start the embedded LLDP Agent on all ports.
3440 **/
3441 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3442 struct i40e_asq_cmd_details *cmd_details)
3443 {
3444 struct i40e_aq_desc desc;
3445 struct i40e_aqc_lldp_start *cmd =
3446 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3447 i40e_status status;
3448
3449 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3450
3451 cmd->command = I40E_AQ_LLDP_AGENT_START;
3452
3453 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3454
3455 return status;
3456 }
3457
3458 /**
3459 * i40e_aq_get_cee_dcb_config
3460 * @hw: pointer to the hw struct
3461 * @buff: response buffer that stores CEE operational configuration
3462 * @buff_size: size of the buffer passed
3463 * @cmd_details: pointer to command details structure or NULL
3464 *
3465 * Get CEE DCBX mode operational configuration from firmware
3466 **/
3467 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3468 void *buff, u16 buff_size,
3469 struct i40e_asq_cmd_details *cmd_details)
3470 {
3471 struct i40e_aq_desc desc;
3472 i40e_status status;
3473
3474 if (buff_size == 0 || !buff)
3475 return I40E_ERR_PARAM;
3476
3477 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3478
3479 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3480 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3481 cmd_details);
3482
3483 return status;
3484 }
3485
3486 /**
3487 * i40e_aq_add_udp_tunnel
3488 * @hw: pointer to the hw struct
3489 * @udp_port: the UDP port to add
3490 * @header_len: length of the tunneling header length in DWords
3491 * @protocol_index: protocol index type
3492 * @filter_index: pointer to filter index
3493 * @cmd_details: pointer to command details structure or NULL
3494 **/
3495 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3496 u16 udp_port, u8 protocol_index,
3497 u8 *filter_index,
3498 struct i40e_asq_cmd_details *cmd_details)
3499 {
3500 struct i40e_aq_desc desc;
3501 struct i40e_aqc_add_udp_tunnel *cmd =
3502 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3503 struct i40e_aqc_del_udp_tunnel_completion *resp =
3504 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3505 i40e_status status;
3506
3507 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3508
3509 cmd->udp_port = cpu_to_le16(udp_port);
3510 cmd->protocol_type = protocol_index;
3511
3512 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3513
3514 if (!status && filter_index)
3515 *filter_index = resp->index;
3516
3517 return status;
3518 }
3519
3520 /**
3521 * i40e_aq_del_udp_tunnel
3522 * @hw: pointer to the hw struct
3523 * @index: filter index
3524 * @cmd_details: pointer to command details structure or NULL
3525 **/
3526 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3527 struct i40e_asq_cmd_details *cmd_details)
3528 {
3529 struct i40e_aq_desc desc;
3530 struct i40e_aqc_remove_udp_tunnel *cmd =
3531 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3532 i40e_status status;
3533
3534 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3535
3536 cmd->index = index;
3537
3538 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3539
3540 return status;
3541 }
3542
3543 /**
3544 * i40e_aq_delete_element - Delete switch element
3545 * @hw: pointer to the hw struct
3546 * @seid: the SEID to delete from the switch
3547 * @cmd_details: pointer to command details structure or NULL
3548 *
3549 * This deletes a switch element from the switch.
3550 **/
3551 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3552 struct i40e_asq_cmd_details *cmd_details)
3553 {
3554 struct i40e_aq_desc desc;
3555 struct i40e_aqc_switch_seid *cmd =
3556 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3557 i40e_status status;
3558
3559 if (seid == 0)
3560 return I40E_ERR_PARAM;
3561
3562 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3563
3564 cmd->seid = cpu_to_le16(seid);
3565
3566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3567
3568 return status;
3569 }
3570
3571 /**
3572 * i40e_aq_dcb_updated - DCB Updated Command
3573 * @hw: pointer to the hw struct
3574 * @cmd_details: pointer to command details structure or NULL
3575 *
3576 * EMP will return when the shared RPB settings have been
3577 * recomputed and modified. The retval field in the descriptor
3578 * will be set to 0 when RPB is modified.
3579 **/
3580 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3581 struct i40e_asq_cmd_details *cmd_details)
3582 {
3583 struct i40e_aq_desc desc;
3584 i40e_status status;
3585
3586 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3587
3588 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3589
3590 return status;
3591 }
3592
3593 /**
3594 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3595 * @hw: pointer to the hw struct
3596 * @seid: seid for the physical port/switching component/vsi
3597 * @buff: Indirect buffer to hold data parameters and response
3598 * @buff_size: Indirect buffer size
3599 * @opcode: Tx scheduler AQ command opcode
3600 * @cmd_details: pointer to command details structure or NULL
3601 *
3602 * Generic command handler for Tx scheduler AQ commands
3603 **/
3604 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3605 void *buff, u16 buff_size,
3606 enum i40e_admin_queue_opc opcode,
3607 struct i40e_asq_cmd_details *cmd_details)
3608 {
3609 struct i40e_aq_desc desc;
3610 struct i40e_aqc_tx_sched_ind *cmd =
3611 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3612 i40e_status status;
3613 bool cmd_param_flag = false;
3614
3615 switch (opcode) {
3616 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3617 case i40e_aqc_opc_configure_vsi_tc_bw:
3618 case i40e_aqc_opc_enable_switching_comp_ets:
3619 case i40e_aqc_opc_modify_switching_comp_ets:
3620 case i40e_aqc_opc_disable_switching_comp_ets:
3621 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3622 case i40e_aqc_opc_configure_switching_comp_bw_config:
3623 cmd_param_flag = true;
3624 break;
3625 case i40e_aqc_opc_query_vsi_bw_config:
3626 case i40e_aqc_opc_query_vsi_ets_sla_config:
3627 case i40e_aqc_opc_query_switching_comp_ets_config:
3628 case i40e_aqc_opc_query_port_ets_config:
3629 case i40e_aqc_opc_query_switching_comp_bw_config:
3630 cmd_param_flag = false;
3631 break;
3632 default:
3633 return I40E_ERR_PARAM;
3634 }
3635
3636 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3637
3638 /* Indirect command */
3639 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3640 if (cmd_param_flag)
3641 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3642 if (buff_size > I40E_AQ_LARGE_BUF)
3643 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3644
3645 desc.datalen = cpu_to_le16(buff_size);
3646
3647 cmd->vsi_seid = cpu_to_le16(seid);
3648
3649 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3650
3651 return status;
3652 }
3653
3654 /**
3655 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3656 * @hw: pointer to the hw struct
3657 * @seid: VSI seid
3658 * @credit: BW limit credits (0 = disabled)
3659 * @max_credit: Max BW limit credits
3660 * @cmd_details: pointer to command details structure or NULL
3661 **/
3662 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3663 u16 seid, u16 credit, u8 max_credit,
3664 struct i40e_asq_cmd_details *cmd_details)
3665 {
3666 struct i40e_aq_desc desc;
3667 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3668 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3669 i40e_status status;
3670
3671 i40e_fill_default_direct_cmd_desc(&desc,
3672 i40e_aqc_opc_configure_vsi_bw_limit);
3673
3674 cmd->vsi_seid = cpu_to_le16(seid);
3675 cmd->credit = cpu_to_le16(credit);
3676 cmd->max_credit = max_credit;
3677
3678 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3679
3680 return status;
3681 }
3682
3683 /**
3684 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3685 * @hw: pointer to the hw struct
3686 * @seid: VSI seid
3687 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3688 * @cmd_details: pointer to command details structure or NULL
3689 **/
3690 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3691 u16 seid,
3692 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3693 struct i40e_asq_cmd_details *cmd_details)
3694 {
3695 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3696 i40e_aqc_opc_configure_vsi_tc_bw,
3697 cmd_details);
3698 }
3699
3700 /**
3701 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3702 * @hw: pointer to the hw struct
3703 * @seid: seid of the switching component connected to Physical Port
3704 * @ets_data: Buffer holding ETS parameters
3705 * @cmd_details: pointer to command details structure or NULL
3706 **/
3707 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3708 u16 seid,
3709 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3710 enum i40e_admin_queue_opc opcode,
3711 struct i40e_asq_cmd_details *cmd_details)
3712 {
3713 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3714 sizeof(*ets_data), opcode, cmd_details);
3715 }
3716
3717 /**
3718 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3719 * @hw: pointer to the hw struct
3720 * @seid: seid of the switching component
3721 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3722 * @cmd_details: pointer to command details structure or NULL
3723 **/
3724 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3725 u16 seid,
3726 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3727 struct i40e_asq_cmd_details *cmd_details)
3728 {
3729 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3730 i40e_aqc_opc_configure_switching_comp_bw_config,
3731 cmd_details);
3732 }
3733
3734 /**
3735 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3736 * @hw: pointer to the hw struct
3737 * @seid: seid of the VSI
3738 * @bw_data: Buffer to hold VSI BW configuration
3739 * @cmd_details: pointer to command details structure or NULL
3740 **/
3741 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3742 u16 seid,
3743 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3744 struct i40e_asq_cmd_details *cmd_details)
3745 {
3746 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3747 i40e_aqc_opc_query_vsi_bw_config,
3748 cmd_details);
3749 }
3750
3751 /**
3752 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3753 * @hw: pointer to the hw struct
3754 * @seid: seid of the VSI
3755 * @bw_data: Buffer to hold VSI BW configuration per TC
3756 * @cmd_details: pointer to command details structure or NULL
3757 **/
3758 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3759 u16 seid,
3760 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3761 struct i40e_asq_cmd_details *cmd_details)
3762 {
3763 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3764 i40e_aqc_opc_query_vsi_ets_sla_config,
3765 cmd_details);
3766 }
3767
3768 /**
3769 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3770 * @hw: pointer to the hw struct
3771 * @seid: seid of the switching component
3772 * @bw_data: Buffer to hold switching component's per TC BW config
3773 * @cmd_details: pointer to command details structure or NULL
3774 **/
3775 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3776 u16 seid,
3777 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3778 struct i40e_asq_cmd_details *cmd_details)
3779 {
3780 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3781 i40e_aqc_opc_query_switching_comp_ets_config,
3782 cmd_details);
3783 }
3784
3785 /**
3786 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3787 * @hw: pointer to the hw struct
3788 * @seid: seid of the VSI or switching component connected to Physical Port
3789 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3790 * @cmd_details: pointer to command details structure or NULL
3791 **/
3792 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3793 u16 seid,
3794 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3795 struct i40e_asq_cmd_details *cmd_details)
3796 {
3797 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3798 i40e_aqc_opc_query_port_ets_config,
3799 cmd_details);
3800 }
3801
3802 /**
3803 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3804 * @hw: pointer to the hw struct
3805 * @seid: seid of the switching component
3806 * @bw_data: Buffer to hold switching component's BW configuration
3807 * @cmd_details: pointer to command details structure or NULL
3808 **/
3809 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3810 u16 seid,
3811 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3812 struct i40e_asq_cmd_details *cmd_details)
3813 {
3814 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3815 i40e_aqc_opc_query_switching_comp_bw_config,
3816 cmd_details);
3817 }
3818
3819 /**
3820 * i40e_validate_filter_settings
3821 * @hw: pointer to the hardware structure
3822 * @settings: Filter control settings
3823 *
3824 * Check and validate the filter control settings passed.
3825 * The function checks for the valid filter/context sizes being
3826 * passed for FCoE and PE.
3827 *
3828 * Returns 0 if the values passed are valid and within
3829 * range else returns an error.
3830 **/
3831 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3832 struct i40e_filter_control_settings *settings)
3833 {
3834 u32 fcoe_cntx_size, fcoe_filt_size;
3835 u32 pe_cntx_size, pe_filt_size;
3836 u32 fcoe_fmax;
3837 u32 val;
3838
3839 /* Validate FCoE settings passed */
3840 switch (settings->fcoe_filt_num) {
3841 case I40E_HASH_FILTER_SIZE_1K:
3842 case I40E_HASH_FILTER_SIZE_2K:
3843 case I40E_HASH_FILTER_SIZE_4K:
3844 case I40E_HASH_FILTER_SIZE_8K:
3845 case I40E_HASH_FILTER_SIZE_16K:
3846 case I40E_HASH_FILTER_SIZE_32K:
3847 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3848 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3849 break;
3850 default:
3851 return I40E_ERR_PARAM;
3852 }
3853
3854 switch (settings->fcoe_cntx_num) {
3855 case I40E_DMA_CNTX_SIZE_512:
3856 case I40E_DMA_CNTX_SIZE_1K:
3857 case I40E_DMA_CNTX_SIZE_2K:
3858 case I40E_DMA_CNTX_SIZE_4K:
3859 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3860 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3861 break;
3862 default:
3863 return I40E_ERR_PARAM;
3864 }
3865
3866 /* Validate PE settings passed */
3867 switch (settings->pe_filt_num) {
3868 case I40E_HASH_FILTER_SIZE_1K:
3869 case I40E_HASH_FILTER_SIZE_2K:
3870 case I40E_HASH_FILTER_SIZE_4K:
3871 case I40E_HASH_FILTER_SIZE_8K:
3872 case I40E_HASH_FILTER_SIZE_16K:
3873 case I40E_HASH_FILTER_SIZE_32K:
3874 case I40E_HASH_FILTER_SIZE_64K:
3875 case I40E_HASH_FILTER_SIZE_128K:
3876 case I40E_HASH_FILTER_SIZE_256K:
3877 case I40E_HASH_FILTER_SIZE_512K:
3878 case I40E_HASH_FILTER_SIZE_1M:
3879 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3880 pe_filt_size <<= (u32)settings->pe_filt_num;
3881 break;
3882 default:
3883 return I40E_ERR_PARAM;
3884 }
3885
3886 switch (settings->pe_cntx_num) {
3887 case I40E_DMA_CNTX_SIZE_512:
3888 case I40E_DMA_CNTX_SIZE_1K:
3889 case I40E_DMA_CNTX_SIZE_2K:
3890 case I40E_DMA_CNTX_SIZE_4K:
3891 case I40E_DMA_CNTX_SIZE_8K:
3892 case I40E_DMA_CNTX_SIZE_16K:
3893 case I40E_DMA_CNTX_SIZE_32K:
3894 case I40E_DMA_CNTX_SIZE_64K:
3895 case I40E_DMA_CNTX_SIZE_128K:
3896 case I40E_DMA_CNTX_SIZE_256K:
3897 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3898 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3899 break;
3900 default:
3901 return I40E_ERR_PARAM;
3902 }
3903
3904 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3905 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3906 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3907 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3908 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3909 return I40E_ERR_INVALID_SIZE;
3910
3911 return 0;
3912 }
3913
3914 /**
3915 * i40e_set_filter_control
3916 * @hw: pointer to the hardware structure
3917 * @settings: Filter control settings
3918 *
3919 * Set the Queue Filters for PE/FCoE and enable filters required
3920 * for a single PF. It is expected that these settings are programmed
3921 * at the driver initialization time.
3922 **/
3923 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3924 struct i40e_filter_control_settings *settings)
3925 {
3926 i40e_status ret = 0;
3927 u32 hash_lut_size = 0;
3928 u32 val;
3929
3930 if (!settings)
3931 return I40E_ERR_PARAM;
3932
3933 /* Validate the input settings */
3934 ret = i40e_validate_filter_settings(hw, settings);
3935 if (ret)
3936 return ret;
3937
3938 /* Read the PF Queue Filter control register */
3939 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
3940
3941 /* Program required PE hash buckets for the PF */
3942 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3943 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3944 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3945 /* Program required PE contexts for the PF */
3946 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3947 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3948 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3949
3950 /* Program required FCoE hash buckets for the PF */
3951 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3952 val |= ((u32)settings->fcoe_filt_num <<
3953 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3954 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3955 /* Program required FCoE DDP contexts for the PF */
3956 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3957 val |= ((u32)settings->fcoe_cntx_num <<
3958 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3959 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3960
3961 /* Program Hash LUT size for the PF */
3962 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3963 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3964 hash_lut_size = 1;
3965 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3966 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3967
3968 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3969 if (settings->enable_fdir)
3970 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3971 if (settings->enable_ethtype)
3972 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3973 if (settings->enable_macvlan)
3974 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3975
3976 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
3977
3978 return 0;
3979 }
3980
3981 /**
3982 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3983 * @hw: pointer to the hw struct
3984 * @mac_addr: MAC address to use in the filter
3985 * @ethtype: Ethertype to use in the filter
3986 * @flags: Flags that needs to be applied to the filter
3987 * @vsi_seid: seid of the control VSI
3988 * @queue: VSI queue number to send the packet to
3989 * @is_add: Add control packet filter if True else remove
3990 * @stats: Structure to hold information on control filter counts
3991 * @cmd_details: pointer to command details structure or NULL
3992 *
3993 * This command will Add or Remove control packet filter for a control VSI.
3994 * In return it will update the total number of perfect filter count in
3995 * the stats member.
3996 **/
3997 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3998 u8 *mac_addr, u16 ethtype, u16 flags,
3999 u16 vsi_seid, u16 queue, bool is_add,
4000 struct i40e_control_filter_stats *stats,
4001 struct i40e_asq_cmd_details *cmd_details)
4002 {
4003 struct i40e_aq_desc desc;
4004 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4005 (struct i40e_aqc_add_remove_control_packet_filter *)
4006 &desc.params.raw;
4007 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4008 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4009 &desc.params.raw;
4010 i40e_status status;
4011
4012 if (vsi_seid == 0)
4013 return I40E_ERR_PARAM;
4014
4015 if (is_add) {
4016 i40e_fill_default_direct_cmd_desc(&desc,
4017 i40e_aqc_opc_add_control_packet_filter);
4018 cmd->queue = cpu_to_le16(queue);
4019 } else {
4020 i40e_fill_default_direct_cmd_desc(&desc,
4021 i40e_aqc_opc_remove_control_packet_filter);
4022 }
4023
4024 if (mac_addr)
4025 ether_addr_copy(cmd->mac, mac_addr);
4026
4027 cmd->etype = cpu_to_le16(ethtype);
4028 cmd->flags = cpu_to_le16(flags);
4029 cmd->seid = cpu_to_le16(vsi_seid);
4030
4031 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4032
4033 if (!status && stats) {
4034 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4035 stats->etype_used = le16_to_cpu(resp->etype_used);
4036 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4037 stats->etype_free = le16_to_cpu(resp->etype_free);
4038 }
4039
4040 return status;
4041 }
4042
4043 /**
4044 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4045 * @hw: pointer to the hw struct
4046 * @seid: VSI seid to add ethertype filter from
4047 **/
4048 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4049 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4050 u16 seid)
4051 {
4052 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4053 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4054 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4055 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4056 i40e_status status;
4057
4058 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4059 seid, 0, true, NULL,
4060 NULL);
4061 if (status)
4062 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4063 }
4064
4065 /**
4066 * i40e_aq_alternate_read
4067 * @hw: pointer to the hardware structure
4068 * @reg_addr0: address of first dword to be read
4069 * @reg_val0: pointer for data read from 'reg_addr0'
4070 * @reg_addr1: address of second dword to be read
4071 * @reg_val1: pointer for data read from 'reg_addr1'
4072 *
4073 * Read one or two dwords from alternate structure. Fields are indicated
4074 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4075 * is not passed then only register at 'reg_addr0' is read.
4076 *
4077 **/
4078 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4079 u32 reg_addr0, u32 *reg_val0,
4080 u32 reg_addr1, u32 *reg_val1)
4081 {
4082 struct i40e_aq_desc desc;
4083 struct i40e_aqc_alternate_write *cmd_resp =
4084 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4085 i40e_status status;
4086
4087 if (!reg_val0)
4088 return I40E_ERR_PARAM;
4089
4090 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4091 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4092 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4093
4094 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4095
4096 if (!status) {
4097 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4098
4099 if (reg_val1)
4100 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4101 }
4102
4103 return status;
4104 }
4105
4106 /**
4107 * i40e_aq_resume_port_tx
4108 * @hw: pointer to the hardware structure
4109 * @cmd_details: pointer to command details structure or NULL
4110 *
4111 * Resume port's Tx traffic
4112 **/
4113 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4114 struct i40e_asq_cmd_details *cmd_details)
4115 {
4116 struct i40e_aq_desc desc;
4117 i40e_status status;
4118
4119 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4120
4121 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4122
4123 return status;
4124 }
4125
4126 /**
4127 * i40e_set_pci_config_data - store PCI bus info
4128 * @hw: pointer to hardware structure
4129 * @link_status: the link status word from PCI config space
4130 *
4131 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4132 **/
4133 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4134 {
4135 hw->bus.type = i40e_bus_type_pci_express;
4136
4137 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4138 case PCI_EXP_LNKSTA_NLW_X1:
4139 hw->bus.width = i40e_bus_width_pcie_x1;
4140 break;
4141 case PCI_EXP_LNKSTA_NLW_X2:
4142 hw->bus.width = i40e_bus_width_pcie_x2;
4143 break;
4144 case PCI_EXP_LNKSTA_NLW_X4:
4145 hw->bus.width = i40e_bus_width_pcie_x4;
4146 break;
4147 case PCI_EXP_LNKSTA_NLW_X8:
4148 hw->bus.width = i40e_bus_width_pcie_x8;
4149 break;
4150 default:
4151 hw->bus.width = i40e_bus_width_unknown;
4152 break;
4153 }
4154
4155 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4156 case PCI_EXP_LNKSTA_CLS_2_5GB:
4157 hw->bus.speed = i40e_bus_speed_2500;
4158 break;
4159 case PCI_EXP_LNKSTA_CLS_5_0GB:
4160 hw->bus.speed = i40e_bus_speed_5000;
4161 break;
4162 case PCI_EXP_LNKSTA_CLS_8_0GB:
4163 hw->bus.speed = i40e_bus_speed_8000;
4164 break;
4165 default:
4166 hw->bus.speed = i40e_bus_speed_unknown;
4167 break;
4168 }
4169 }
4170
4171 /**
4172 * i40e_aq_debug_dump
4173 * @hw: pointer to the hardware structure
4174 * @cluster_id: specific cluster to dump
4175 * @table_id: table id within cluster
4176 * @start_index: index of line in the block to read
4177 * @buff_size: dump buffer size
4178 * @buff: dump buffer
4179 * @ret_buff_size: actual buffer size returned
4180 * @ret_next_table: next block to read
4181 * @ret_next_index: next index to read
4182 *
4183 * Dump internal FW/HW data for debug purposes.
4184 *
4185 **/
4186 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4187 u8 table_id, u32 start_index, u16 buff_size,
4188 void *buff, u16 *ret_buff_size,
4189 u8 *ret_next_table, u32 *ret_next_index,
4190 struct i40e_asq_cmd_details *cmd_details)
4191 {
4192 struct i40e_aq_desc desc;
4193 struct i40e_aqc_debug_dump_internals *cmd =
4194 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4195 struct i40e_aqc_debug_dump_internals *resp =
4196 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4197 i40e_status status;
4198
4199 if (buff_size == 0 || !buff)
4200 return I40E_ERR_PARAM;
4201
4202 i40e_fill_default_direct_cmd_desc(&desc,
4203 i40e_aqc_opc_debug_dump_internals);
4204 /* Indirect Command */
4205 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4206 if (buff_size > I40E_AQ_LARGE_BUF)
4207 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4208
4209 cmd->cluster_id = cluster_id;
4210 cmd->table_id = table_id;
4211 cmd->idx = cpu_to_le32(start_index);
4212
4213 desc.datalen = cpu_to_le16(buff_size);
4214
4215 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4216 if (!status) {
4217 if (ret_buff_size)
4218 *ret_buff_size = le16_to_cpu(desc.datalen);
4219 if (ret_next_table)
4220 *ret_next_table = resp->table_id;
4221 if (ret_next_index)
4222 *ret_next_index = le32_to_cpu(resp->idx);
4223 }
4224
4225 return status;
4226 }
4227
4228 /**
4229 * i40e_read_bw_from_alt_ram
4230 * @hw: pointer to the hardware structure
4231 * @max_bw: pointer for max_bw read
4232 * @min_bw: pointer for min_bw read
4233 * @min_valid: pointer for bool that is true if min_bw is a valid value
4234 * @max_valid: pointer for bool that is true if max_bw is a valid value
4235 *
4236 * Read bw from the alternate ram for the given pf
4237 **/
4238 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4239 u32 *max_bw, u32 *min_bw,
4240 bool *min_valid, bool *max_valid)
4241 {
4242 i40e_status status;
4243 u32 max_bw_addr, min_bw_addr;
4244
4245 /* Calculate the address of the min/max bw registers */
4246 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4247 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4248 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4249 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4250 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4251 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4252
4253 /* Read the bandwidths from alt ram */
4254 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4255 min_bw_addr, min_bw);
4256
4257 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4258 *min_valid = true;
4259 else
4260 *min_valid = false;
4261
4262 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4263 *max_valid = true;
4264 else
4265 *max_valid = false;
4266
4267 return status;
4268 }
4269
4270 /**
4271 * i40e_aq_configure_partition_bw
4272 * @hw: pointer to the hardware structure
4273 * @bw_data: Buffer holding valid pfs and bw limits
4274 * @cmd_details: pointer to command details
4275 *
4276 * Configure partitions guaranteed/max bw
4277 **/
4278 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4279 struct i40e_aqc_configure_partition_bw_data *bw_data,
4280 struct i40e_asq_cmd_details *cmd_details)
4281 {
4282 i40e_status status;
4283 struct i40e_aq_desc desc;
4284 u16 bwd_size = sizeof(*bw_data);
4285
4286 i40e_fill_default_direct_cmd_desc(&desc,
4287 i40e_aqc_opc_configure_partition_bw);
4288
4289 /* Indirect command */
4290 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4291 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4292
4293 if (bwd_size > I40E_AQ_LARGE_BUF)
4294 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4295
4296 desc.datalen = cpu_to_le16(bwd_size);
4297
4298 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4299 cmd_details);
4300
4301 return status;
4302 }
4303
4304 /**
4305 * i40e_read_phy_register
4306 * @hw: pointer to the HW structure
4307 * @page: registers page number
4308 * @reg: register address in the page
4309 * @phy_adr: PHY address on MDIO interface
4310 * @value: PHY register value
4311 *
4312 * Reads specified PHY register value
4313 **/
4314 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4315 u8 page, u16 reg, u8 phy_addr,
4316 u16 *value)
4317 {
4318 i40e_status status = I40E_ERR_TIMEOUT;
4319 u32 command = 0;
4320 u16 retry = 1000;
4321 u8 port_num = hw->func_caps.mdio_port_num;
4322
4323 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4324 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4325 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4326 (I40E_MDIO_OPCODE_ADDRESS) |
4327 (I40E_MDIO_STCODE) |
4328 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4329 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4330 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4331 do {
4332 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4333 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4334 status = 0;
4335 break;
4336 }
4337 usleep_range(10, 20);
4338 retry--;
4339 } while (retry);
4340
4341 if (status) {
4342 i40e_debug(hw, I40E_DEBUG_PHY,
4343 "PHY: Can't write command to external PHY.\n");
4344 goto phy_read_end;
4345 }
4346
4347 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4348 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4349 (I40E_MDIO_OPCODE_READ) |
4350 (I40E_MDIO_STCODE) |
4351 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4352 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4353 status = I40E_ERR_TIMEOUT;
4354 retry = 1000;
4355 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4356 do {
4357 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4358 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4359 status = 0;
4360 break;
4361 }
4362 usleep_range(10, 20);
4363 retry--;
4364 } while (retry);
4365
4366 if (!status) {
4367 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4368 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4369 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4370 } else {
4371 i40e_debug(hw, I40E_DEBUG_PHY,
4372 "PHY: Can't read register value from external PHY.\n");
4373 }
4374
4375 phy_read_end:
4376 return status;
4377 }
4378
4379 /**
4380 * i40e_write_phy_register
4381 * @hw: pointer to the HW structure
4382 * @page: registers page number
4383 * @reg: register address in the page
4384 * @phy_adr: PHY address on MDIO interface
4385 * @value: PHY register value
4386 *
4387 * Writes value to specified PHY register
4388 **/
4389 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4390 u8 page, u16 reg, u8 phy_addr,
4391 u16 value)
4392 {
4393 i40e_status status = I40E_ERR_TIMEOUT;
4394 u32 command = 0;
4395 u16 retry = 1000;
4396 u8 port_num = hw->func_caps.mdio_port_num;
4397
4398 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4399 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4400 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4401 (I40E_MDIO_OPCODE_ADDRESS) |
4402 (I40E_MDIO_STCODE) |
4403 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4404 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4405 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4406 do {
4407 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4408 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4409 status = 0;
4410 break;
4411 }
4412 usleep_range(10, 20);
4413 retry--;
4414 } while (retry);
4415 if (status) {
4416 i40e_debug(hw, I40E_DEBUG_PHY,
4417 "PHY: Can't write command to external PHY.\n");
4418 goto phy_write_end;
4419 }
4420
4421 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4422 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4423
4424 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4425 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4426 (I40E_MDIO_OPCODE_WRITE) |
4427 (I40E_MDIO_STCODE) |
4428 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4429 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4430 status = I40E_ERR_TIMEOUT;
4431 retry = 1000;
4432 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4433 do {
4434 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4435 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4436 status = 0;
4437 break;
4438 }
4439 usleep_range(10, 20);
4440 retry--;
4441 } while (retry);
4442
4443 phy_write_end:
4444 return status;
4445 }
4446
4447 /**
4448 * i40e_get_phy_address
4449 * @hw: pointer to the HW structure
4450 * @dev_num: PHY port num that address we want
4451 * @phy_addr: Returned PHY address
4452 *
4453 * Gets PHY address for current port
4454 **/
4455 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4456 {
4457 u8 port_num = hw->func_caps.mdio_port_num;
4458 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4459
4460 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4461 }
4462
4463 /**
4464 * i40e_blink_phy_led
4465 * @hw: pointer to the HW structure
4466 * @time: time how long led will blinks in secs
4467 * @interval: gap between LED on and off in msecs
4468 *
4469 * Blinks PHY link LED
4470 **/
4471 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4472 u32 time, u32 interval)
4473 {
4474 i40e_status status = 0;
4475 u32 i;
4476 u16 led_ctl;
4477 u16 gpio_led_port;
4478 u16 led_reg;
4479 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4480 u8 phy_addr = 0;
4481 u8 port_num;
4482
4483 i = rd32(hw, I40E_PFGEN_PORTNUM);
4484 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4485 phy_addr = i40e_get_phy_address(hw, port_num);
4486
4487 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4488 led_addr++) {
4489 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4490 led_addr, phy_addr, &led_reg);
4491 if (status)
4492 goto phy_blinking_end;
4493 led_ctl = led_reg;
4494 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4495 led_reg = 0;
4496 status = i40e_write_phy_register(hw,
4497 I40E_PHY_COM_REG_PAGE,
4498 led_addr, phy_addr,
4499 led_reg);
4500 if (status)
4501 goto phy_blinking_end;
4502 break;
4503 }
4504 }
4505
4506 if (time > 0 && interval > 0) {
4507 for (i = 0; i < time * 1000; i += interval) {
4508 status = i40e_read_phy_register(hw,
4509 I40E_PHY_COM_REG_PAGE,
4510 led_addr, phy_addr,
4511 &led_reg);
4512 if (status)
4513 goto restore_config;
4514 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4515 led_reg = 0;
4516 else
4517 led_reg = I40E_PHY_LED_MANUAL_ON;
4518 status = i40e_write_phy_register(hw,
4519 I40E_PHY_COM_REG_PAGE,
4520 led_addr, phy_addr,
4521 led_reg);
4522 if (status)
4523 goto restore_config;
4524 msleep(interval);
4525 }
4526 }
4527
4528 restore_config:
4529 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4530 phy_addr, led_ctl);
4531
4532 phy_blinking_end:
4533 return status;
4534 }
4535
4536 /**
4537 * i40e_led_get_phy - return current on/off mode
4538 * @hw: pointer to the hw struct
4539 * @led_addr: address of led register to use
4540 * @val: original value of register to use
4541 *
4542 **/
4543 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4544 u16 *val)
4545 {
4546 i40e_status status = 0;
4547 u16 gpio_led_port;
4548 u8 phy_addr = 0;
4549 u16 reg_val;
4550 u16 temp_addr;
4551 u8 port_num;
4552 u32 i;
4553
4554 temp_addr = I40E_PHY_LED_PROV_REG_1;
4555 i = rd32(hw, I40E_PFGEN_PORTNUM);
4556 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4557 phy_addr = i40e_get_phy_address(hw, port_num);
4558
4559 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4560 temp_addr++) {
4561 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4562 temp_addr, phy_addr, &reg_val);
4563 if (status)
4564 return status;
4565 *val = reg_val;
4566 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4567 *led_addr = temp_addr;
4568 break;
4569 }
4570 }
4571 return status;
4572 }
4573
4574 /**
4575 * i40e_led_set_phy
4576 * @hw: pointer to the HW structure
4577 * @on: true or false
4578 * @mode: original val plus bit for set or ignore
4579 * Set led's on or off when controlled by the PHY
4580 *
4581 **/
4582 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4583 u16 led_addr, u32 mode)
4584 {
4585 i40e_status status = 0;
4586 u16 led_ctl = 0;
4587 u16 led_reg = 0;
4588 u8 phy_addr = 0;
4589 u8 port_num;
4590 u32 i;
4591
4592 i = rd32(hw, I40E_PFGEN_PORTNUM);
4593 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4594 phy_addr = i40e_get_phy_address(hw, port_num);
4595
4596 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4597 phy_addr, &led_reg);
4598 if (status)
4599 return status;
4600 led_ctl = led_reg;
4601 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4602 led_reg = 0;
4603 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4604 led_addr, phy_addr, led_reg);
4605 if (status)
4606 return status;
4607 }
4608 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4609 led_addr, phy_addr, &led_reg);
4610 if (status)
4611 goto restore_config;
4612 if (on)
4613 led_reg = I40E_PHY_LED_MANUAL_ON;
4614 else
4615 led_reg = 0;
4616 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4617 led_addr, phy_addr, led_reg);
4618 if (status)
4619 goto restore_config;
4620 if (mode & I40E_PHY_LED_MODE_ORIG) {
4621 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4622 status = i40e_write_phy_register(hw,
4623 I40E_PHY_COM_REG_PAGE,
4624 led_addr, phy_addr, led_ctl);
4625 }
4626 return status;
4627 restore_config:
4628 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4629 phy_addr, led_ctl);
4630 return status;
4631 }
4632
4633 /**
4634 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4635 * @hw: pointer to the hw struct
4636 * @reg_addr: register address
4637 * @reg_val: ptr to register value
4638 * @cmd_details: pointer to command details structure or NULL
4639 *
4640 * Use the firmware to read the Rx control register,
4641 * especially useful if the Rx unit is under heavy pressure
4642 **/
4643 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4644 u32 reg_addr, u32 *reg_val,
4645 struct i40e_asq_cmd_details *cmd_details)
4646 {
4647 struct i40e_aq_desc desc;
4648 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4649 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4650 i40e_status status;
4651
4652 if (!reg_val)
4653 return I40E_ERR_PARAM;
4654
4655 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4656
4657 cmd_resp->address = cpu_to_le32(reg_addr);
4658
4659 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4660
4661 if (status == 0)
4662 *reg_val = le32_to_cpu(cmd_resp->value);
4663
4664 return status;
4665 }
4666
4667 /**
4668 * i40e_read_rx_ctl - read from an Rx control register
4669 * @hw: pointer to the hw struct
4670 * @reg_addr: register address
4671 **/
4672 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4673 {
4674 i40e_status status = 0;
4675 bool use_register;
4676 int retry = 5;
4677 u32 val = 0;
4678
4679 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4680 if (!use_register) {
4681 do_retry:
4682 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4683 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4684 usleep_range(1000, 2000);
4685 retry--;
4686 goto do_retry;
4687 }
4688 }
4689
4690 /* if the AQ access failed, try the old-fashioned way */
4691 if (status || use_register)
4692 val = rd32(hw, reg_addr);
4693
4694 return val;
4695 }
4696
4697 /**
4698 * i40e_aq_rx_ctl_write_register
4699 * @hw: pointer to the hw struct
4700 * @reg_addr: register address
4701 * @reg_val: register value
4702 * @cmd_details: pointer to command details structure or NULL
4703 *
4704 * Use the firmware to write to an Rx control register,
4705 * especially useful if the Rx unit is under heavy pressure
4706 **/
4707 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4708 u32 reg_addr, u32 reg_val,
4709 struct i40e_asq_cmd_details *cmd_details)
4710 {
4711 struct i40e_aq_desc desc;
4712 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4713 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4714 i40e_status status;
4715
4716 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4717
4718 cmd->address = cpu_to_le32(reg_addr);
4719 cmd->value = cpu_to_le32(reg_val);
4720
4721 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4722
4723 return status;
4724 }
4725
4726 /**
4727 * i40e_write_rx_ctl - write to an Rx control register
4728 * @hw: pointer to the hw struct
4729 * @reg_addr: register address
4730 * @reg_val: register value
4731 **/
4732 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4733 {
4734 i40e_status status = 0;
4735 bool use_register;
4736 int retry = 5;
4737
4738 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4739 if (!use_register) {
4740 do_retry:
4741 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4742 reg_val, NULL);
4743 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4744 usleep_range(1000, 2000);
4745 retry--;
4746 goto do_retry;
4747 }
4748 }
4749
4750 /* if the AQ access failed, try the old-fashioned way */
4751 if (status || use_register)
4752 wr32(hw, reg_addr, reg_val);
4753 }
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