1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
39 static i40e_status
i40e_set_mac_type(struct i40e_hw
*hw
)
41 i40e_status status
= 0;
43 if (hw
->vendor_id
== PCI_VENDOR_ID_INTEL
) {
44 switch (hw
->device_id
) {
45 case I40E_DEV_ID_SFP_XL710
:
46 case I40E_DEV_ID_QEMU
:
47 case I40E_DEV_ID_KX_B
:
48 case I40E_DEV_ID_KX_C
:
49 case I40E_DEV_ID_QSFP_A
:
50 case I40E_DEV_ID_QSFP_B
:
51 case I40E_DEV_ID_QSFP_C
:
52 case I40E_DEV_ID_10G_BASE_T
:
53 case I40E_DEV_ID_10G_BASE_T4
:
54 case I40E_DEV_ID_20G_KR2
:
55 case I40E_DEV_ID_20G_KR2_A
:
56 hw
->mac
.type
= I40E_MAC_XL710
;
58 case I40E_DEV_ID_KX_X722
:
59 case I40E_DEV_ID_QSFP_X722
:
60 case I40E_DEV_ID_SFP_X722
:
61 case I40E_DEV_ID_1G_BASE_T_X722
:
62 case I40E_DEV_ID_10G_BASE_T_X722
:
63 hw
->mac
.type
= I40E_MAC_X722
;
66 hw
->mac
.type
= I40E_MAC_GENERIC
;
70 status
= I40E_ERR_DEVICE_NOT_SUPPORTED
;
73 hw_dbg(hw
, "i40e_set_mac_type found mac: %d, returns: %d\n",
74 hw
->mac
.type
, status
);
79 * i40e_aq_str - convert AQ err code to a string
80 * @hw: pointer to the HW structure
81 * @aq_err: the AQ error code to convert
83 const char *i40e_aq_str(struct i40e_hw
*hw
, enum i40e_admin_queue_err aq_err
)
88 case I40E_AQ_RC_EPERM
:
89 return "I40E_AQ_RC_EPERM";
90 case I40E_AQ_RC_ENOENT
:
91 return "I40E_AQ_RC_ENOENT";
92 case I40E_AQ_RC_ESRCH
:
93 return "I40E_AQ_RC_ESRCH";
94 case I40E_AQ_RC_EINTR
:
95 return "I40E_AQ_RC_EINTR";
97 return "I40E_AQ_RC_EIO";
98 case I40E_AQ_RC_ENXIO
:
99 return "I40E_AQ_RC_ENXIO";
100 case I40E_AQ_RC_E2BIG
:
101 return "I40E_AQ_RC_E2BIG";
102 case I40E_AQ_RC_EAGAIN
:
103 return "I40E_AQ_RC_EAGAIN";
104 case I40E_AQ_RC_ENOMEM
:
105 return "I40E_AQ_RC_ENOMEM";
106 case I40E_AQ_RC_EACCES
:
107 return "I40E_AQ_RC_EACCES";
108 case I40E_AQ_RC_EFAULT
:
109 return "I40E_AQ_RC_EFAULT";
110 case I40E_AQ_RC_EBUSY
:
111 return "I40E_AQ_RC_EBUSY";
112 case I40E_AQ_RC_EEXIST
:
113 return "I40E_AQ_RC_EEXIST";
114 case I40E_AQ_RC_EINVAL
:
115 return "I40E_AQ_RC_EINVAL";
116 case I40E_AQ_RC_ENOTTY
:
117 return "I40E_AQ_RC_ENOTTY";
118 case I40E_AQ_RC_ENOSPC
:
119 return "I40E_AQ_RC_ENOSPC";
120 case I40E_AQ_RC_ENOSYS
:
121 return "I40E_AQ_RC_ENOSYS";
122 case I40E_AQ_RC_ERANGE
:
123 return "I40E_AQ_RC_ERANGE";
124 case I40E_AQ_RC_EFLUSHED
:
125 return "I40E_AQ_RC_EFLUSHED";
126 case I40E_AQ_RC_BAD_ADDR
:
127 return "I40E_AQ_RC_BAD_ADDR";
128 case I40E_AQ_RC_EMODE
:
129 return "I40E_AQ_RC_EMODE";
130 case I40E_AQ_RC_EFBIG
:
131 return "I40E_AQ_RC_EFBIG";
134 snprintf(hw
->err_str
, sizeof(hw
->err_str
), "%d", aq_err
);
139 * i40e_stat_str - convert status err code to a string
140 * @hw: pointer to the HW structure
141 * @stat_err: the status error code to convert
143 const char *i40e_stat_str(struct i40e_hw
*hw
, i40e_status stat_err
)
149 return "I40E_ERR_NVM";
150 case I40E_ERR_NVM_CHECKSUM
:
151 return "I40E_ERR_NVM_CHECKSUM";
153 return "I40E_ERR_PHY";
154 case I40E_ERR_CONFIG
:
155 return "I40E_ERR_CONFIG";
157 return "I40E_ERR_PARAM";
158 case I40E_ERR_MAC_TYPE
:
159 return "I40E_ERR_MAC_TYPE";
160 case I40E_ERR_UNKNOWN_PHY
:
161 return "I40E_ERR_UNKNOWN_PHY";
162 case I40E_ERR_LINK_SETUP
:
163 return "I40E_ERR_LINK_SETUP";
164 case I40E_ERR_ADAPTER_STOPPED
:
165 return "I40E_ERR_ADAPTER_STOPPED";
166 case I40E_ERR_INVALID_MAC_ADDR
:
167 return "I40E_ERR_INVALID_MAC_ADDR";
168 case I40E_ERR_DEVICE_NOT_SUPPORTED
:
169 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
170 case I40E_ERR_MASTER_REQUESTS_PENDING
:
171 return "I40E_ERR_MASTER_REQUESTS_PENDING";
172 case I40E_ERR_INVALID_LINK_SETTINGS
:
173 return "I40E_ERR_INVALID_LINK_SETTINGS";
174 case I40E_ERR_AUTONEG_NOT_COMPLETE
:
175 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
176 case I40E_ERR_RESET_FAILED
:
177 return "I40E_ERR_RESET_FAILED";
178 case I40E_ERR_SWFW_SYNC
:
179 return "I40E_ERR_SWFW_SYNC";
180 case I40E_ERR_NO_AVAILABLE_VSI
:
181 return "I40E_ERR_NO_AVAILABLE_VSI";
182 case I40E_ERR_NO_MEMORY
:
183 return "I40E_ERR_NO_MEMORY";
184 case I40E_ERR_BAD_PTR
:
185 return "I40E_ERR_BAD_PTR";
186 case I40E_ERR_RING_FULL
:
187 return "I40E_ERR_RING_FULL";
188 case I40E_ERR_INVALID_PD_ID
:
189 return "I40E_ERR_INVALID_PD_ID";
190 case I40E_ERR_INVALID_QP_ID
:
191 return "I40E_ERR_INVALID_QP_ID";
192 case I40E_ERR_INVALID_CQ_ID
:
193 return "I40E_ERR_INVALID_CQ_ID";
194 case I40E_ERR_INVALID_CEQ_ID
:
195 return "I40E_ERR_INVALID_CEQ_ID";
196 case I40E_ERR_INVALID_AEQ_ID
:
197 return "I40E_ERR_INVALID_AEQ_ID";
198 case I40E_ERR_INVALID_SIZE
:
199 return "I40E_ERR_INVALID_SIZE";
200 case I40E_ERR_INVALID_ARP_INDEX
:
201 return "I40E_ERR_INVALID_ARP_INDEX";
202 case I40E_ERR_INVALID_FPM_FUNC_ID
:
203 return "I40E_ERR_INVALID_FPM_FUNC_ID";
204 case I40E_ERR_QP_INVALID_MSG_SIZE
:
205 return "I40E_ERR_QP_INVALID_MSG_SIZE";
206 case I40E_ERR_QP_TOOMANY_WRS_POSTED
:
207 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
208 case I40E_ERR_INVALID_FRAG_COUNT
:
209 return "I40E_ERR_INVALID_FRAG_COUNT";
210 case I40E_ERR_QUEUE_EMPTY
:
211 return "I40E_ERR_QUEUE_EMPTY";
212 case I40E_ERR_INVALID_ALIGNMENT
:
213 return "I40E_ERR_INVALID_ALIGNMENT";
214 case I40E_ERR_FLUSHED_QUEUE
:
215 return "I40E_ERR_FLUSHED_QUEUE";
216 case I40E_ERR_INVALID_PUSH_PAGE_INDEX
:
217 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
218 case I40E_ERR_INVALID_IMM_DATA_SIZE
:
219 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
220 case I40E_ERR_TIMEOUT
:
221 return "I40E_ERR_TIMEOUT";
222 case I40E_ERR_OPCODE_MISMATCH
:
223 return "I40E_ERR_OPCODE_MISMATCH";
224 case I40E_ERR_CQP_COMPL_ERROR
:
225 return "I40E_ERR_CQP_COMPL_ERROR";
226 case I40E_ERR_INVALID_VF_ID
:
227 return "I40E_ERR_INVALID_VF_ID";
228 case I40E_ERR_INVALID_HMCFN_ID
:
229 return "I40E_ERR_INVALID_HMCFN_ID";
230 case I40E_ERR_BACKING_PAGE_ERROR
:
231 return "I40E_ERR_BACKING_PAGE_ERROR";
232 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE
:
233 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
234 case I40E_ERR_INVALID_PBLE_INDEX
:
235 return "I40E_ERR_INVALID_PBLE_INDEX";
236 case I40E_ERR_INVALID_SD_INDEX
:
237 return "I40E_ERR_INVALID_SD_INDEX";
238 case I40E_ERR_INVALID_PAGE_DESC_INDEX
:
239 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
240 case I40E_ERR_INVALID_SD_TYPE
:
241 return "I40E_ERR_INVALID_SD_TYPE";
242 case I40E_ERR_MEMCPY_FAILED
:
243 return "I40E_ERR_MEMCPY_FAILED";
244 case I40E_ERR_INVALID_HMC_OBJ_INDEX
:
245 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
246 case I40E_ERR_INVALID_HMC_OBJ_COUNT
:
247 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
248 case I40E_ERR_INVALID_SRQ_ARM_LIMIT
:
249 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
250 case I40E_ERR_SRQ_ENABLED
:
251 return "I40E_ERR_SRQ_ENABLED";
252 case I40E_ERR_ADMIN_QUEUE_ERROR
:
253 return "I40E_ERR_ADMIN_QUEUE_ERROR";
254 case I40E_ERR_ADMIN_QUEUE_TIMEOUT
:
255 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
256 case I40E_ERR_BUF_TOO_SHORT
:
257 return "I40E_ERR_BUF_TOO_SHORT";
258 case I40E_ERR_ADMIN_QUEUE_FULL
:
259 return "I40E_ERR_ADMIN_QUEUE_FULL";
260 case I40E_ERR_ADMIN_QUEUE_NO_WORK
:
261 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
262 case I40E_ERR_BAD_IWARP_CQE
:
263 return "I40E_ERR_BAD_IWARP_CQE";
264 case I40E_ERR_NVM_BLANK_MODE
:
265 return "I40E_ERR_NVM_BLANK_MODE";
266 case I40E_ERR_NOT_IMPLEMENTED
:
267 return "I40E_ERR_NOT_IMPLEMENTED";
268 case I40E_ERR_PE_DOORBELL_NOT_ENABLED
:
269 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
270 case I40E_ERR_DIAG_TEST_FAILED
:
271 return "I40E_ERR_DIAG_TEST_FAILED";
272 case I40E_ERR_NOT_READY
:
273 return "I40E_ERR_NOT_READY";
274 case I40E_NOT_SUPPORTED
:
275 return "I40E_NOT_SUPPORTED";
276 case I40E_ERR_FIRMWARE_API_VERSION
:
277 return "I40E_ERR_FIRMWARE_API_VERSION";
280 snprintf(hw
->err_str
, sizeof(hw
->err_str
), "%d", stat_err
);
286 * @hw: debug mask related to admin queue
288 * @desc: pointer to admin queue descriptor
289 * @buffer: pointer to command buffer
290 * @buf_len: max length of buffer
292 * Dumps debug log about adminq command with descriptor contents.
294 void i40e_debug_aq(struct i40e_hw
*hw
, enum i40e_debug_mask mask
, void *desc
,
295 void *buffer
, u16 buf_len
)
297 struct i40e_aq_desc
*aq_desc
= (struct i40e_aq_desc
*)desc
;
298 u16 len
= le16_to_cpu(aq_desc
->datalen
);
299 u8
*buf
= (u8
*)buffer
;
302 if ((!(mask
& hw
->debug_mask
)) || (desc
== NULL
))
306 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
307 le16_to_cpu(aq_desc
->opcode
),
308 le16_to_cpu(aq_desc
->flags
),
309 le16_to_cpu(aq_desc
->datalen
),
310 le16_to_cpu(aq_desc
->retval
));
311 i40e_debug(hw
, mask
, "\tcookie (h,l) 0x%08X 0x%08X\n",
312 le32_to_cpu(aq_desc
->cookie_high
),
313 le32_to_cpu(aq_desc
->cookie_low
));
314 i40e_debug(hw
, mask
, "\tparam (0,1) 0x%08X 0x%08X\n",
315 le32_to_cpu(aq_desc
->params
.internal
.param0
),
316 le32_to_cpu(aq_desc
->params
.internal
.param1
));
317 i40e_debug(hw
, mask
, "\taddr (h,l) 0x%08X 0x%08X\n",
318 le32_to_cpu(aq_desc
->params
.external
.addr_high
),
319 le32_to_cpu(aq_desc
->params
.external
.addr_low
));
321 if ((buffer
!= NULL
) && (aq_desc
->datalen
!= 0)) {
322 i40e_debug(hw
, mask
, "AQ CMD Buffer:\n");
325 /* write the full 16-byte chunks */
326 for (i
= 0; i
< (len
- 16); i
+= 16)
327 i40e_debug(hw
, mask
, "\t0x%04X %16ph\n", i
, buf
+ i
);
328 /* write whatever's left over without overrunning the buffer */
330 i40e_debug(hw
, mask
, "\t0x%04X %*ph\n",
331 i
, len
- i
, buf
+ i
);
336 * i40e_check_asq_alive
337 * @hw: pointer to the hw struct
339 * Returns true if Queue is enabled else false.
341 bool i40e_check_asq_alive(struct i40e_hw
*hw
)
344 return !!(rd32(hw
, hw
->aq
.asq
.len
) &
345 I40E_PF_ATQLEN_ATQENABLE_MASK
);
351 * i40e_aq_queue_shutdown
352 * @hw: pointer to the hw struct
353 * @unloading: is the driver unloading itself
355 * Tell the Firmware that we're shutting down the AdminQ and whether
356 * or not the driver is unloading as well.
358 i40e_status
i40e_aq_queue_shutdown(struct i40e_hw
*hw
,
361 struct i40e_aq_desc desc
;
362 struct i40e_aqc_queue_shutdown
*cmd
=
363 (struct i40e_aqc_queue_shutdown
*)&desc
.params
.raw
;
366 i40e_fill_default_direct_cmd_desc(&desc
,
367 i40e_aqc_opc_queue_shutdown
);
370 cmd
->driver_unloading
= cpu_to_le32(I40E_AQ_DRIVER_UNLOADING
);
371 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
377 * i40e_aq_get_set_rss_lut
378 * @hw: pointer to the hardware structure
379 * @vsi_id: vsi fw index
380 * @pf_lut: for PF table set true, for VSI table set false
381 * @lut: pointer to the lut buffer provided by the caller
382 * @lut_size: size of the lut buffer
383 * @set: set true to set the table, false to get the table
385 * Internal function to get or set RSS look up table
387 static i40e_status
i40e_aq_get_set_rss_lut(struct i40e_hw
*hw
,
388 u16 vsi_id
, bool pf_lut
,
389 u8
*lut
, u16 lut_size
,
393 struct i40e_aq_desc desc
;
394 struct i40e_aqc_get_set_rss_lut
*cmd_resp
=
395 (struct i40e_aqc_get_set_rss_lut
*)&desc
.params
.raw
;
398 i40e_fill_default_direct_cmd_desc(&desc
,
399 i40e_aqc_opc_set_rss_lut
);
401 i40e_fill_default_direct_cmd_desc(&desc
,
402 i40e_aqc_opc_get_rss_lut
);
404 /* Indirect command */
405 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
406 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
409 cpu_to_le16((u16
)((vsi_id
<<
410 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT
) &
411 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK
));
412 cmd_resp
->vsi_id
|= cpu_to_le16((u16
)I40E_AQC_SET_RSS_LUT_VSI_VALID
);
415 cmd_resp
->flags
|= cpu_to_le16((u16
)
416 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF
<<
417 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT
) &
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK
));
420 cmd_resp
->flags
|= cpu_to_le16((u16
)
421 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI
<<
422 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT
) &
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK
));
425 status
= i40e_asq_send_command(hw
, &desc
, lut
, lut_size
, NULL
);
431 * i40e_aq_get_rss_lut
432 * @hw: pointer to the hardware structure
433 * @vsi_id: vsi fw index
434 * @pf_lut: for PF table set true, for VSI table set false
435 * @lut: pointer to the lut buffer provided by the caller
436 * @lut_size: size of the lut buffer
438 * get the RSS lookup table, PF or VSI type
440 i40e_status
i40e_aq_get_rss_lut(struct i40e_hw
*hw
, u16 vsi_id
,
441 bool pf_lut
, u8
*lut
, u16 lut_size
)
443 return i40e_aq_get_set_rss_lut(hw
, vsi_id
, pf_lut
, lut
, lut_size
,
448 * i40e_aq_set_rss_lut
449 * @hw: pointer to the hardware structure
450 * @vsi_id: vsi fw index
451 * @pf_lut: for PF table set true, for VSI table set false
452 * @lut: pointer to the lut buffer provided by the caller
453 * @lut_size: size of the lut buffer
455 * set the RSS lookup table, PF or VSI type
457 i40e_status
i40e_aq_set_rss_lut(struct i40e_hw
*hw
, u16 vsi_id
,
458 bool pf_lut
, u8
*lut
, u16 lut_size
)
460 return i40e_aq_get_set_rss_lut(hw
, vsi_id
, pf_lut
, lut
, lut_size
, true);
464 * i40e_aq_get_set_rss_key
465 * @hw: pointer to the hw struct
466 * @vsi_id: vsi fw index
467 * @key: pointer to key info struct
468 * @set: set true to set the key, false to get the key
470 * get the RSS key per VSI
472 static i40e_status
i40e_aq_get_set_rss_key(struct i40e_hw
*hw
,
474 struct i40e_aqc_get_set_rss_key_data
*key
,
478 struct i40e_aq_desc desc
;
479 struct i40e_aqc_get_set_rss_key
*cmd_resp
=
480 (struct i40e_aqc_get_set_rss_key
*)&desc
.params
.raw
;
481 u16 key_size
= sizeof(struct i40e_aqc_get_set_rss_key_data
);
484 i40e_fill_default_direct_cmd_desc(&desc
,
485 i40e_aqc_opc_set_rss_key
);
487 i40e_fill_default_direct_cmd_desc(&desc
,
488 i40e_aqc_opc_get_rss_key
);
490 /* Indirect command */
491 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
492 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
495 cpu_to_le16((u16
)((vsi_id
<<
496 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT
) &
497 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK
));
498 cmd_resp
->vsi_id
|= cpu_to_le16((u16
)I40E_AQC_SET_RSS_KEY_VSI_VALID
);
500 status
= i40e_asq_send_command(hw
, &desc
, key
, key_size
, NULL
);
506 * i40e_aq_get_rss_key
507 * @hw: pointer to the hw struct
508 * @vsi_id: vsi fw index
509 * @key: pointer to key info struct
512 i40e_status
i40e_aq_get_rss_key(struct i40e_hw
*hw
,
514 struct i40e_aqc_get_set_rss_key_data
*key
)
516 return i40e_aq_get_set_rss_key(hw
, vsi_id
, key
, false);
520 * i40e_aq_set_rss_key
521 * @hw: pointer to the hw struct
522 * @vsi_id: vsi fw index
523 * @key: pointer to key info struct
525 * set the RSS key per VSI
527 i40e_status
i40e_aq_set_rss_key(struct i40e_hw
*hw
,
529 struct i40e_aqc_get_set_rss_key_data
*key
)
531 return i40e_aq_get_set_rss_key(hw
, vsi_id
, key
, true);
534 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
535 * hardware to a bit-field that can be used by SW to more easily determine the
538 * Macros are used to shorten the table lines and make this table human
541 * We store the PTYPE in the top byte of the bit field - this is just so that
542 * we can check that the table doesn't have a row missing, as the index into
543 * the table should be the PTYPE.
547 * IF NOT i40e_ptype_lookup[ptype].known
550 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
551 * Use the rest of the fields to look at the tunnels, inner protocols, etc
553 * Use the enum i40e_rx_l2_ptype to decode the packet type
557 /* macro to make the table lines short */
558 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
561 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
562 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
563 I40E_RX_PTYPE_##OUTER_FRAG, \
564 I40E_RX_PTYPE_TUNNEL_##T, \
565 I40E_RX_PTYPE_TUNNEL_END_##TE, \
566 I40E_RX_PTYPE_##TEF, \
567 I40E_RX_PTYPE_INNER_PROT_##I, \
568 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
570 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
571 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
573 /* shorter macros makes the table fit but are terse */
574 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
575 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
576 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
578 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
579 struct i40e_rx_ptype_decoded i40e_ptype_lookup
[] = {
580 /* L2 Packet types */
581 I40E_PTT_UNUSED_ENTRY(0),
582 I40E_PTT(1, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
583 I40E_PTT(2, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, TS
, PAY2
),
584 I40E_PTT(3, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
585 I40E_PTT_UNUSED_ENTRY(4),
586 I40E_PTT_UNUSED_ENTRY(5),
587 I40E_PTT(6, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
588 I40E_PTT(7, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
589 I40E_PTT_UNUSED_ENTRY(8),
590 I40E_PTT_UNUSED_ENTRY(9),
591 I40E_PTT(10, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
592 I40E_PTT(11, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, NONE
),
593 I40E_PTT(12, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
594 I40E_PTT(13, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
595 I40E_PTT(14, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
596 I40E_PTT(15, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
597 I40E_PTT(16, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
598 I40E_PTT(17, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
599 I40E_PTT(18, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
600 I40E_PTT(19, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
601 I40E_PTT(20, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
602 I40E_PTT(21, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
604 /* Non Tunneled IPv4 */
605 I40E_PTT(22, IP
, IPV4
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
606 I40E_PTT(23, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
607 I40E_PTT(24, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY4
),
608 I40E_PTT_UNUSED_ENTRY(25),
609 I40E_PTT(26, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
610 I40E_PTT(27, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
611 I40E_PTT(28, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
614 I40E_PTT(29, IP
, IPV4
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
615 I40E_PTT(30, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
616 I40E_PTT(31, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
617 I40E_PTT_UNUSED_ENTRY(32),
618 I40E_PTT(33, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
619 I40E_PTT(34, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
620 I40E_PTT(35, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
623 I40E_PTT(36, IP
, IPV4
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
624 I40E_PTT(37, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
625 I40E_PTT(38, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
626 I40E_PTT_UNUSED_ENTRY(39),
627 I40E_PTT(40, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
628 I40E_PTT(41, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
629 I40E_PTT(42, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
631 /* IPv4 --> GRE/NAT */
632 I40E_PTT(43, IP
, IPV4
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
634 /* IPv4 --> GRE/NAT --> IPv4 */
635 I40E_PTT(44, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
636 I40E_PTT(45, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
637 I40E_PTT(46, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
638 I40E_PTT_UNUSED_ENTRY(47),
639 I40E_PTT(48, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
640 I40E_PTT(49, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
641 I40E_PTT(50, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
643 /* IPv4 --> GRE/NAT --> IPv6 */
644 I40E_PTT(51, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
645 I40E_PTT(52, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
646 I40E_PTT(53, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
647 I40E_PTT_UNUSED_ENTRY(54),
648 I40E_PTT(55, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
649 I40E_PTT(56, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
650 I40E_PTT(57, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
652 /* IPv4 --> GRE/NAT --> MAC */
653 I40E_PTT(58, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
655 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
656 I40E_PTT(59, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
657 I40E_PTT(60, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
658 I40E_PTT(61, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
659 I40E_PTT_UNUSED_ENTRY(62),
660 I40E_PTT(63, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
661 I40E_PTT(64, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
662 I40E_PTT(65, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
664 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
665 I40E_PTT(66, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
666 I40E_PTT(67, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
667 I40E_PTT(68, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
668 I40E_PTT_UNUSED_ENTRY(69),
669 I40E_PTT(70, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
670 I40E_PTT(71, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
671 I40E_PTT(72, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
673 /* IPv4 --> GRE/NAT --> MAC/VLAN */
674 I40E_PTT(73, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
676 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
677 I40E_PTT(74, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
678 I40E_PTT(75, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
679 I40E_PTT(76, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
680 I40E_PTT_UNUSED_ENTRY(77),
681 I40E_PTT(78, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
682 I40E_PTT(79, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
683 I40E_PTT(80, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
685 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
686 I40E_PTT(81, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
687 I40E_PTT(82, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
688 I40E_PTT(83, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
689 I40E_PTT_UNUSED_ENTRY(84),
690 I40E_PTT(85, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
691 I40E_PTT(86, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
692 I40E_PTT(87, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
694 /* Non Tunneled IPv6 */
695 I40E_PTT(88, IP
, IPV6
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
696 I40E_PTT(89, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
697 I40E_PTT(90, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY3
),
698 I40E_PTT_UNUSED_ENTRY(91),
699 I40E_PTT(92, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
700 I40E_PTT(93, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
701 I40E_PTT(94, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
704 I40E_PTT(95, IP
, IPV6
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
705 I40E_PTT(96, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
706 I40E_PTT(97, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
707 I40E_PTT_UNUSED_ENTRY(98),
708 I40E_PTT(99, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
709 I40E_PTT(100, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
710 I40E_PTT(101, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
713 I40E_PTT(102, IP
, IPV6
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
714 I40E_PTT(103, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
715 I40E_PTT(104, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
716 I40E_PTT_UNUSED_ENTRY(105),
717 I40E_PTT(106, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
718 I40E_PTT(107, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
719 I40E_PTT(108, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
721 /* IPv6 --> GRE/NAT */
722 I40E_PTT(109, IP
, IPV6
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
724 /* IPv6 --> GRE/NAT -> IPv4 */
725 I40E_PTT(110, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
726 I40E_PTT(111, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
727 I40E_PTT(112, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
728 I40E_PTT_UNUSED_ENTRY(113),
729 I40E_PTT(114, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
730 I40E_PTT(115, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
731 I40E_PTT(116, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
733 /* IPv6 --> GRE/NAT -> IPv6 */
734 I40E_PTT(117, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
735 I40E_PTT(118, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
736 I40E_PTT(119, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
737 I40E_PTT_UNUSED_ENTRY(120),
738 I40E_PTT(121, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
739 I40E_PTT(122, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
740 I40E_PTT(123, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
742 /* IPv6 --> GRE/NAT -> MAC */
743 I40E_PTT(124, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
745 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
746 I40E_PTT(125, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
747 I40E_PTT(126, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
748 I40E_PTT(127, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
749 I40E_PTT_UNUSED_ENTRY(128),
750 I40E_PTT(129, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
751 I40E_PTT(130, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
752 I40E_PTT(131, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
754 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
755 I40E_PTT(132, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
756 I40E_PTT(133, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
757 I40E_PTT(134, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
758 I40E_PTT_UNUSED_ENTRY(135),
759 I40E_PTT(136, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
760 I40E_PTT(137, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
761 I40E_PTT(138, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
763 /* IPv6 --> GRE/NAT -> MAC/VLAN */
764 I40E_PTT(139, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
766 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
767 I40E_PTT(140, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
768 I40E_PTT(141, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
769 I40E_PTT(142, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
770 I40E_PTT_UNUSED_ENTRY(143),
771 I40E_PTT(144, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
772 I40E_PTT(145, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
773 I40E_PTT(146, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
775 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
776 I40E_PTT(147, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
777 I40E_PTT(148, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
778 I40E_PTT(149, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
779 I40E_PTT_UNUSED_ENTRY(150),
780 I40E_PTT(151, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
781 I40E_PTT(152, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
782 I40E_PTT(153, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
785 I40E_PTT_UNUSED_ENTRY(154),
786 I40E_PTT_UNUSED_ENTRY(155),
787 I40E_PTT_UNUSED_ENTRY(156),
788 I40E_PTT_UNUSED_ENTRY(157),
789 I40E_PTT_UNUSED_ENTRY(158),
790 I40E_PTT_UNUSED_ENTRY(159),
792 I40E_PTT_UNUSED_ENTRY(160),
793 I40E_PTT_UNUSED_ENTRY(161),
794 I40E_PTT_UNUSED_ENTRY(162),
795 I40E_PTT_UNUSED_ENTRY(163),
796 I40E_PTT_UNUSED_ENTRY(164),
797 I40E_PTT_UNUSED_ENTRY(165),
798 I40E_PTT_UNUSED_ENTRY(166),
799 I40E_PTT_UNUSED_ENTRY(167),
800 I40E_PTT_UNUSED_ENTRY(168),
801 I40E_PTT_UNUSED_ENTRY(169),
803 I40E_PTT_UNUSED_ENTRY(170),
804 I40E_PTT_UNUSED_ENTRY(171),
805 I40E_PTT_UNUSED_ENTRY(172),
806 I40E_PTT_UNUSED_ENTRY(173),
807 I40E_PTT_UNUSED_ENTRY(174),
808 I40E_PTT_UNUSED_ENTRY(175),
809 I40E_PTT_UNUSED_ENTRY(176),
810 I40E_PTT_UNUSED_ENTRY(177),
811 I40E_PTT_UNUSED_ENTRY(178),
812 I40E_PTT_UNUSED_ENTRY(179),
814 I40E_PTT_UNUSED_ENTRY(180),
815 I40E_PTT_UNUSED_ENTRY(181),
816 I40E_PTT_UNUSED_ENTRY(182),
817 I40E_PTT_UNUSED_ENTRY(183),
818 I40E_PTT_UNUSED_ENTRY(184),
819 I40E_PTT_UNUSED_ENTRY(185),
820 I40E_PTT_UNUSED_ENTRY(186),
821 I40E_PTT_UNUSED_ENTRY(187),
822 I40E_PTT_UNUSED_ENTRY(188),
823 I40E_PTT_UNUSED_ENTRY(189),
825 I40E_PTT_UNUSED_ENTRY(190),
826 I40E_PTT_UNUSED_ENTRY(191),
827 I40E_PTT_UNUSED_ENTRY(192),
828 I40E_PTT_UNUSED_ENTRY(193),
829 I40E_PTT_UNUSED_ENTRY(194),
830 I40E_PTT_UNUSED_ENTRY(195),
831 I40E_PTT_UNUSED_ENTRY(196),
832 I40E_PTT_UNUSED_ENTRY(197),
833 I40E_PTT_UNUSED_ENTRY(198),
834 I40E_PTT_UNUSED_ENTRY(199),
836 I40E_PTT_UNUSED_ENTRY(200),
837 I40E_PTT_UNUSED_ENTRY(201),
838 I40E_PTT_UNUSED_ENTRY(202),
839 I40E_PTT_UNUSED_ENTRY(203),
840 I40E_PTT_UNUSED_ENTRY(204),
841 I40E_PTT_UNUSED_ENTRY(205),
842 I40E_PTT_UNUSED_ENTRY(206),
843 I40E_PTT_UNUSED_ENTRY(207),
844 I40E_PTT_UNUSED_ENTRY(208),
845 I40E_PTT_UNUSED_ENTRY(209),
847 I40E_PTT_UNUSED_ENTRY(210),
848 I40E_PTT_UNUSED_ENTRY(211),
849 I40E_PTT_UNUSED_ENTRY(212),
850 I40E_PTT_UNUSED_ENTRY(213),
851 I40E_PTT_UNUSED_ENTRY(214),
852 I40E_PTT_UNUSED_ENTRY(215),
853 I40E_PTT_UNUSED_ENTRY(216),
854 I40E_PTT_UNUSED_ENTRY(217),
855 I40E_PTT_UNUSED_ENTRY(218),
856 I40E_PTT_UNUSED_ENTRY(219),
858 I40E_PTT_UNUSED_ENTRY(220),
859 I40E_PTT_UNUSED_ENTRY(221),
860 I40E_PTT_UNUSED_ENTRY(222),
861 I40E_PTT_UNUSED_ENTRY(223),
862 I40E_PTT_UNUSED_ENTRY(224),
863 I40E_PTT_UNUSED_ENTRY(225),
864 I40E_PTT_UNUSED_ENTRY(226),
865 I40E_PTT_UNUSED_ENTRY(227),
866 I40E_PTT_UNUSED_ENTRY(228),
867 I40E_PTT_UNUSED_ENTRY(229),
869 I40E_PTT_UNUSED_ENTRY(230),
870 I40E_PTT_UNUSED_ENTRY(231),
871 I40E_PTT_UNUSED_ENTRY(232),
872 I40E_PTT_UNUSED_ENTRY(233),
873 I40E_PTT_UNUSED_ENTRY(234),
874 I40E_PTT_UNUSED_ENTRY(235),
875 I40E_PTT_UNUSED_ENTRY(236),
876 I40E_PTT_UNUSED_ENTRY(237),
877 I40E_PTT_UNUSED_ENTRY(238),
878 I40E_PTT_UNUSED_ENTRY(239),
880 I40E_PTT_UNUSED_ENTRY(240),
881 I40E_PTT_UNUSED_ENTRY(241),
882 I40E_PTT_UNUSED_ENTRY(242),
883 I40E_PTT_UNUSED_ENTRY(243),
884 I40E_PTT_UNUSED_ENTRY(244),
885 I40E_PTT_UNUSED_ENTRY(245),
886 I40E_PTT_UNUSED_ENTRY(246),
887 I40E_PTT_UNUSED_ENTRY(247),
888 I40E_PTT_UNUSED_ENTRY(248),
889 I40E_PTT_UNUSED_ENTRY(249),
891 I40E_PTT_UNUSED_ENTRY(250),
892 I40E_PTT_UNUSED_ENTRY(251),
893 I40E_PTT_UNUSED_ENTRY(252),
894 I40E_PTT_UNUSED_ENTRY(253),
895 I40E_PTT_UNUSED_ENTRY(254),
896 I40E_PTT_UNUSED_ENTRY(255)
900 * i40e_init_shared_code - Initialize the shared code
901 * @hw: pointer to hardware structure
903 * This assigns the MAC type and PHY code and inits the NVM.
904 * Does not touch the hardware. This function must be called prior to any
905 * other function in the shared code. The i40e_hw structure should be
906 * memset to 0 prior to calling this function. The following fields in
907 * hw structure should be filled in prior to calling this function:
908 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
909 * subsystem_vendor_id, and revision_id
911 i40e_status
i40e_init_shared_code(struct i40e_hw
*hw
)
913 i40e_status status
= 0;
914 u32 port
, ari
, func_rid
;
916 i40e_set_mac_type(hw
);
918 switch (hw
->mac
.type
) {
923 return I40E_ERR_DEVICE_NOT_SUPPORTED
;
926 hw
->phy
.get_link_info
= true;
928 /* Determine port number and PF number*/
929 port
= (rd32(hw
, I40E_PFGEN_PORTNUM
) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK
)
930 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT
;
932 ari
= (rd32(hw
, I40E_GLPCI_CAPSUP
) & I40E_GLPCI_CAPSUP_ARI_EN_MASK
) >>
933 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT
;
934 func_rid
= rd32(hw
, I40E_PF_FUNC_RID
);
936 hw
->pf_id
= (u8
)(func_rid
& 0xff);
938 hw
->pf_id
= (u8
)(func_rid
& 0x7);
940 if (hw
->mac
.type
== I40E_MAC_X722
)
941 hw
->flags
|= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE
;
943 status
= i40e_init_nvm(hw
);
948 * i40e_aq_mac_address_read - Retrieve the MAC addresses
949 * @hw: pointer to the hw struct
950 * @flags: a return indicator of what addresses were added to the addr store
951 * @addrs: the requestor's mac addr store
952 * @cmd_details: pointer to command details structure or NULL
954 static i40e_status
i40e_aq_mac_address_read(struct i40e_hw
*hw
,
956 struct i40e_aqc_mac_address_read_data
*addrs
,
957 struct i40e_asq_cmd_details
*cmd_details
)
959 struct i40e_aq_desc desc
;
960 struct i40e_aqc_mac_address_read
*cmd_data
=
961 (struct i40e_aqc_mac_address_read
*)&desc
.params
.raw
;
964 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_mac_address_read
);
965 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
);
967 status
= i40e_asq_send_command(hw
, &desc
, addrs
,
968 sizeof(*addrs
), cmd_details
);
969 *flags
= le16_to_cpu(cmd_data
->command_flags
);
975 * i40e_aq_mac_address_write - Change the MAC addresses
976 * @hw: pointer to the hw struct
977 * @flags: indicates which MAC to be written
978 * @mac_addr: address to write
979 * @cmd_details: pointer to command details structure or NULL
981 i40e_status
i40e_aq_mac_address_write(struct i40e_hw
*hw
,
982 u16 flags
, u8
*mac_addr
,
983 struct i40e_asq_cmd_details
*cmd_details
)
985 struct i40e_aq_desc desc
;
986 struct i40e_aqc_mac_address_write
*cmd_data
=
987 (struct i40e_aqc_mac_address_write
*)&desc
.params
.raw
;
990 i40e_fill_default_direct_cmd_desc(&desc
,
991 i40e_aqc_opc_mac_address_write
);
992 cmd_data
->command_flags
= cpu_to_le16(flags
);
993 cmd_data
->mac_sah
= cpu_to_le16((u16
)mac_addr
[0] << 8 | mac_addr
[1]);
994 cmd_data
->mac_sal
= cpu_to_le32(((u32
)mac_addr
[2] << 24) |
995 ((u32
)mac_addr
[3] << 16) |
996 ((u32
)mac_addr
[4] << 8) |
999 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1005 * i40e_get_mac_addr - get MAC address
1006 * @hw: pointer to the HW structure
1007 * @mac_addr: pointer to MAC address
1009 * Reads the adapter's MAC address from register
1011 i40e_status
i40e_get_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
1013 struct i40e_aqc_mac_address_read_data addrs
;
1017 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
1019 if (flags
& I40E_AQC_LAN_ADDR_VALID
)
1020 ether_addr_copy(mac_addr
, addrs
.pf_lan_mac
);
1026 * i40e_get_port_mac_addr - get Port MAC address
1027 * @hw: pointer to the HW structure
1028 * @mac_addr: pointer to Port MAC address
1030 * Reads the adapter's Port MAC address
1032 i40e_status
i40e_get_port_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
1034 struct i40e_aqc_mac_address_read_data addrs
;
1038 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
1042 if (flags
& I40E_AQC_PORT_ADDR_VALID
)
1043 ether_addr_copy(mac_addr
, addrs
.port_mac
);
1045 status
= I40E_ERR_INVALID_MAC_ADDR
;
1051 * i40e_pre_tx_queue_cfg - pre tx queue configure
1052 * @hw: pointer to the HW structure
1053 * @queue: target PF queue index
1054 * @enable: state change request
1056 * Handles hw requirement to indicate intention to enable
1057 * or disable target queue.
1059 void i40e_pre_tx_queue_cfg(struct i40e_hw
*hw
, u32 queue
, bool enable
)
1061 u32 abs_queue_idx
= hw
->func_caps
.base_queue
+ queue
;
1065 if (abs_queue_idx
>= 128) {
1066 reg_block
= abs_queue_idx
/ 128;
1067 abs_queue_idx
%= 128;
1070 reg_val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
1071 reg_val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
1072 reg_val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
1075 reg_val
|= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK
;
1077 reg_val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
1079 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), reg_val
);
1084 * i40e_get_san_mac_addr - get SAN MAC address
1085 * @hw: pointer to the HW structure
1086 * @mac_addr: pointer to SAN MAC address
1088 * Reads the adapter's SAN MAC address from NVM
1090 i40e_status
i40e_get_san_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
1092 struct i40e_aqc_mac_address_read_data addrs
;
1096 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
1100 if (flags
& I40E_AQC_SAN_ADDR_VALID
)
1101 ether_addr_copy(mac_addr
, addrs
.pf_san_mac
);
1103 status
= I40E_ERR_INVALID_MAC_ADDR
;
1110 * i40e_read_pba_string - Reads part number string from EEPROM
1111 * @hw: pointer to hardware structure
1112 * @pba_num: stores the part number string from the EEPROM
1113 * @pba_num_size: part number string buffer length
1115 * Reads the part number string from the EEPROM.
1117 i40e_status
i40e_read_pba_string(struct i40e_hw
*hw
, u8
*pba_num
,
1120 i40e_status status
= 0;
1126 status
= i40e_read_nvm_word(hw
, I40E_SR_PBA_FLAGS
, &pba_word
);
1127 if (status
|| (pba_word
!= 0xFAFA)) {
1128 hw_dbg(hw
, "Failed to read PBA flags or flag is invalid.\n");
1132 status
= i40e_read_nvm_word(hw
, I40E_SR_PBA_BLOCK_PTR
, &pba_ptr
);
1134 hw_dbg(hw
, "Failed to read PBA Block pointer.\n");
1138 status
= i40e_read_nvm_word(hw
, pba_ptr
, &pba_size
);
1140 hw_dbg(hw
, "Failed to read PBA Block size.\n");
1144 /* Subtract one to get PBA word count (PBA Size word is included in
1148 if (pba_num_size
< (((u32
)pba_size
* 2) + 1)) {
1149 hw_dbg(hw
, "Buffer to small for PBA data.\n");
1150 return I40E_ERR_PARAM
;
1153 for (i
= 0; i
< pba_size
; i
++) {
1154 status
= i40e_read_nvm_word(hw
, (pba_ptr
+ 1) + i
, &pba_word
);
1156 hw_dbg(hw
, "Failed to read PBA Block word %d.\n", i
);
1160 pba_num
[(i
* 2)] = (pba_word
>> 8) & 0xFF;
1161 pba_num
[(i
* 2) + 1] = pba_word
& 0xFF;
1163 pba_num
[(pba_size
* 2)] = '\0';
1169 * i40e_get_media_type - Gets media type
1170 * @hw: pointer to the hardware structure
1172 static enum i40e_media_type
i40e_get_media_type(struct i40e_hw
*hw
)
1174 enum i40e_media_type media
;
1176 switch (hw
->phy
.link_info
.phy_type
) {
1177 case I40E_PHY_TYPE_10GBASE_SR
:
1178 case I40E_PHY_TYPE_10GBASE_LR
:
1179 case I40E_PHY_TYPE_1000BASE_SX
:
1180 case I40E_PHY_TYPE_1000BASE_LX
:
1181 case I40E_PHY_TYPE_40GBASE_SR4
:
1182 case I40E_PHY_TYPE_40GBASE_LR4
:
1183 media
= I40E_MEDIA_TYPE_FIBER
;
1185 case I40E_PHY_TYPE_100BASE_TX
:
1186 case I40E_PHY_TYPE_1000BASE_T
:
1187 case I40E_PHY_TYPE_10GBASE_T
:
1188 media
= I40E_MEDIA_TYPE_BASET
;
1190 case I40E_PHY_TYPE_10GBASE_CR1_CU
:
1191 case I40E_PHY_TYPE_40GBASE_CR4_CU
:
1192 case I40E_PHY_TYPE_10GBASE_CR1
:
1193 case I40E_PHY_TYPE_40GBASE_CR4
:
1194 case I40E_PHY_TYPE_10GBASE_SFPP_CU
:
1195 case I40E_PHY_TYPE_40GBASE_AOC
:
1196 case I40E_PHY_TYPE_10GBASE_AOC
:
1197 media
= I40E_MEDIA_TYPE_DA
;
1199 case I40E_PHY_TYPE_1000BASE_KX
:
1200 case I40E_PHY_TYPE_10GBASE_KX4
:
1201 case I40E_PHY_TYPE_10GBASE_KR
:
1202 case I40E_PHY_TYPE_40GBASE_KR4
:
1203 case I40E_PHY_TYPE_20GBASE_KR2
:
1204 media
= I40E_MEDIA_TYPE_BACKPLANE
;
1206 case I40E_PHY_TYPE_SGMII
:
1207 case I40E_PHY_TYPE_XAUI
:
1208 case I40E_PHY_TYPE_XFI
:
1209 case I40E_PHY_TYPE_XLAUI
:
1210 case I40E_PHY_TYPE_XLPPI
:
1212 media
= I40E_MEDIA_TYPE_UNKNOWN
;
1219 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1220 #define I40E_PF_RESET_WAIT_COUNT 200
1222 * i40e_pf_reset - Reset the PF
1223 * @hw: pointer to the hardware structure
1225 * Assuming someone else has triggered a global reset,
1226 * assure the global reset is complete and then reset the PF
1228 i40e_status
i40e_pf_reset(struct i40e_hw
*hw
)
1235 /* Poll for Global Reset steady state in case of recent GRST.
1236 * The grst delay value is in 100ms units, and we'll wait a
1237 * couple counts longer to be sure we don't just miss the end.
1239 grst_del
= (rd32(hw
, I40E_GLGEN_RSTCTL
) &
1240 I40E_GLGEN_RSTCTL_GRSTDEL_MASK
) >>
1241 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT
;
1243 /* It can take upto 15 secs for GRST steady state.
1244 * Bump it to 16 secs max to be safe.
1246 grst_del
= grst_del
* 20;
1248 for (cnt
= 0; cnt
< grst_del
; cnt
++) {
1249 reg
= rd32(hw
, I40E_GLGEN_RSTAT
);
1250 if (!(reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
))
1254 if (reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
) {
1255 hw_dbg(hw
, "Global reset polling failed to complete.\n");
1256 return I40E_ERR_RESET_FAILED
;
1259 /* Now Wait for the FW to be ready */
1260 for (cnt1
= 0; cnt1
< I40E_PF_RESET_WAIT_COUNT
; cnt1
++) {
1261 reg
= rd32(hw
, I40E_GLNVM_ULD
);
1262 reg
&= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1263 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
);
1264 if (reg
== (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
)) {
1266 hw_dbg(hw
, "Core and Global modules ready %d\n", cnt1
);
1269 usleep_range(10000, 20000);
1271 if (!(reg
& (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1272 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
))) {
1273 hw_dbg(hw
, "wait for FW Reset complete timedout\n");
1274 hw_dbg(hw
, "I40E_GLNVM_ULD = 0x%x\n", reg
);
1275 return I40E_ERR_RESET_FAILED
;
1278 /* If there was a Global Reset in progress when we got here,
1279 * we don't need to do the PF Reset
1282 if (hw
->revision_id
== 0)
1283 cnt
= I40E_PF_RESET_WAIT_COUNT_A0
;
1285 cnt
= I40E_PF_RESET_WAIT_COUNT
;
1286 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
1287 wr32(hw
, I40E_PFGEN_CTRL
,
1288 (reg
| I40E_PFGEN_CTRL_PFSWR_MASK
));
1289 for (; cnt
; cnt
--) {
1290 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
1291 if (!(reg
& I40E_PFGEN_CTRL_PFSWR_MASK
))
1293 usleep_range(1000, 2000);
1295 if (reg
& I40E_PFGEN_CTRL_PFSWR_MASK
) {
1296 hw_dbg(hw
, "PF reset polling failed to complete.\n");
1297 return I40E_ERR_RESET_FAILED
;
1301 i40e_clear_pxe_mode(hw
);
1307 * i40e_clear_hw - clear out any left over hw state
1308 * @hw: pointer to the hw struct
1310 * Clear queues and interrupts, typically called at init time,
1311 * but after the capabilities have been found so we know how many
1312 * queues and msix vectors have been allocated.
1314 void i40e_clear_hw(struct i40e_hw
*hw
)
1316 u32 num_queues
, base_queue
;
1324 /* get number of interrupts, queues, and VFs */
1325 val
= rd32(hw
, I40E_GLPCI_CNF2
);
1326 num_pf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_PF_N_MASK
) >>
1327 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT
;
1328 num_vf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_VF_N_MASK
) >>
1329 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT
;
1331 val
= rd32(hw
, I40E_PFLAN_QALLOC
);
1332 base_queue
= (val
& I40E_PFLAN_QALLOC_FIRSTQ_MASK
) >>
1333 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT
;
1334 j
= (val
& I40E_PFLAN_QALLOC_LASTQ_MASK
) >>
1335 I40E_PFLAN_QALLOC_LASTQ_SHIFT
;
1336 if (val
& I40E_PFLAN_QALLOC_VALID_MASK
)
1337 num_queues
= (j
- base_queue
) + 1;
1341 val
= rd32(hw
, I40E_PF_VT_PFALLOC
);
1342 i
= (val
& I40E_PF_VT_PFALLOC_FIRSTVF_MASK
) >>
1343 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT
;
1344 j
= (val
& I40E_PF_VT_PFALLOC_LASTVF_MASK
) >>
1345 I40E_PF_VT_PFALLOC_LASTVF_SHIFT
;
1346 if (val
& I40E_PF_VT_PFALLOC_VALID_MASK
)
1347 num_vfs
= (j
- i
) + 1;
1351 /* stop all the interrupts */
1352 wr32(hw
, I40E_PFINT_ICR0_ENA
, 0);
1353 val
= 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT
;
1354 for (i
= 0; i
< num_pf_int
- 2; i
++)
1355 wr32(hw
, I40E_PFINT_DYN_CTLN(i
), val
);
1357 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1358 val
= eol
<< I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
1359 wr32(hw
, I40E_PFINT_LNKLST0
, val
);
1360 for (i
= 0; i
< num_pf_int
- 2; i
++)
1361 wr32(hw
, I40E_PFINT_LNKLSTN(i
), val
);
1362 val
= eol
<< I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
1363 for (i
= 0; i
< num_vfs
; i
++)
1364 wr32(hw
, I40E_VPINT_LNKLST0(i
), val
);
1365 for (i
= 0; i
< num_vf_int
- 2; i
++)
1366 wr32(hw
, I40E_VPINT_LNKLSTN(i
), val
);
1368 /* warn the HW of the coming Tx disables */
1369 for (i
= 0; i
< num_queues
; i
++) {
1370 u32 abs_queue_idx
= base_queue
+ i
;
1373 if (abs_queue_idx
>= 128) {
1374 reg_block
= abs_queue_idx
/ 128;
1375 abs_queue_idx
%= 128;
1378 val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
1379 val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
1380 val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
1381 val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
1383 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), val
);
1387 /* stop all the queues */
1388 for (i
= 0; i
< num_queues
; i
++) {
1389 wr32(hw
, I40E_QINT_TQCTL(i
), 0);
1390 wr32(hw
, I40E_QTX_ENA(i
), 0);
1391 wr32(hw
, I40E_QINT_RQCTL(i
), 0);
1392 wr32(hw
, I40E_QRX_ENA(i
), 0);
1395 /* short wait for all queue disables to settle */
1400 * i40e_clear_pxe_mode - clear pxe operations mode
1401 * @hw: pointer to the hw struct
1403 * Make sure all PXE mode settings are cleared, including things
1404 * like descriptor fetch/write-back mode.
1406 void i40e_clear_pxe_mode(struct i40e_hw
*hw
)
1410 if (i40e_check_asq_alive(hw
))
1411 i40e_aq_clear_pxe_mode(hw
, NULL
);
1413 /* Clear single descriptor fetch/write-back mode */
1414 reg
= rd32(hw
, I40E_GLLAN_RCTL_0
);
1416 if (hw
->revision_id
== 0) {
1417 /* As a work around clear PXE_MODE instead of setting it */
1418 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
& (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK
)));
1420 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
| I40E_GLLAN_RCTL_0_PXE_MODE_MASK
));
1425 * i40e_led_is_mine - helper to find matching led
1426 * @hw: pointer to the hw struct
1427 * @idx: index into GPIO registers
1429 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1431 static u32
i40e_led_is_mine(struct i40e_hw
*hw
, int idx
)
1436 if (!hw
->func_caps
.led
[idx
])
1439 gpio_val
= rd32(hw
, I40E_GLGEN_GPIO_CTL(idx
));
1440 port
= (gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK
) >>
1441 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT
;
1443 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1444 * if it is not our port then ignore
1446 if ((gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK
) ||
1453 #define I40E_COMBINED_ACTIVITY 0xA
1454 #define I40E_FILTER_ACTIVITY 0xE
1455 #define I40E_LINK_ACTIVITY 0xC
1456 #define I40E_MAC_ACTIVITY 0xD
1457 #define I40E_LED0 22
1460 * i40e_led_get - return current on/off mode
1461 * @hw: pointer to the hw struct
1463 * The value returned is the 'mode' field as defined in the
1464 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1465 * values are variations of possible behaviors relating to
1466 * blink, link, and wire.
1468 u32
i40e_led_get(struct i40e_hw
*hw
)
1470 u32 current_mode
= 0;
1474 /* as per the documentation GPIO 22-29 are the LED
1475 * GPIO pins named LED0..LED7
1477 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1478 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1483 /* ignore gpio LED src mode entries related to the activity
1486 current_mode
= ((gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
)
1487 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
);
1488 switch (current_mode
) {
1489 case I40E_COMBINED_ACTIVITY
:
1490 case I40E_FILTER_ACTIVITY
:
1491 case I40E_MAC_ACTIVITY
:
1497 mode
= (gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
) >>
1498 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
;
1506 * i40e_led_set - set new on/off mode
1507 * @hw: pointer to the hw struct
1508 * @mode: 0=off, 0xf=on (else see manual for mode details)
1509 * @blink: true if the LED should blink when on, false if steady
1511 * if this function is used to turn on the blink it should
1512 * be used to disable the blink when restoring the original state.
1514 void i40e_led_set(struct i40e_hw
*hw
, u32 mode
, bool blink
)
1516 u32 current_mode
= 0;
1519 if (mode
& 0xfffffff0)
1520 hw_dbg(hw
, "invalid mode passed in %X\n", mode
);
1522 /* as per the documentation GPIO 22-29 are the LED
1523 * GPIO pins named LED0..LED7
1525 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1526 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1531 /* ignore gpio LED src mode entries related to the activity
1534 current_mode
= ((gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
)
1535 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
);
1536 switch (current_mode
) {
1537 case I40E_COMBINED_ACTIVITY
:
1538 case I40E_FILTER_ACTIVITY
:
1539 case I40E_MAC_ACTIVITY
:
1545 gpio_val
&= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
;
1546 /* this & is a bit of paranoia, but serves as a range check */
1547 gpio_val
|= ((mode
<< I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
) &
1548 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
);
1550 if (mode
== I40E_LINK_ACTIVITY
)
1554 gpio_val
|= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
);
1556 gpio_val
&= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
);
1558 wr32(hw
, I40E_GLGEN_GPIO_CTL(i
), gpio_val
);
1563 /* Admin command wrappers */
1566 * i40e_aq_get_phy_capabilities
1567 * @hw: pointer to the hw struct
1568 * @abilities: structure for PHY capabilities to be filled
1569 * @qualified_modules: report Qualified Modules
1570 * @report_init: report init capabilities (active are default)
1571 * @cmd_details: pointer to command details structure or NULL
1573 * Returns the various PHY abilities supported on the Port.
1575 i40e_status
i40e_aq_get_phy_capabilities(struct i40e_hw
*hw
,
1576 bool qualified_modules
, bool report_init
,
1577 struct i40e_aq_get_phy_abilities_resp
*abilities
,
1578 struct i40e_asq_cmd_details
*cmd_details
)
1580 struct i40e_aq_desc desc
;
1582 u16 abilities_size
= sizeof(struct i40e_aq_get_phy_abilities_resp
);
1585 return I40E_ERR_PARAM
;
1587 i40e_fill_default_direct_cmd_desc(&desc
,
1588 i40e_aqc_opc_get_phy_abilities
);
1590 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1591 if (abilities_size
> I40E_AQ_LARGE_BUF
)
1592 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1594 if (qualified_modules
)
1595 desc
.params
.external
.param0
|=
1596 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES
);
1599 desc
.params
.external
.param0
|=
1600 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES
);
1602 status
= i40e_asq_send_command(hw
, &desc
, abilities
, abilities_size
,
1605 if (hw
->aq
.asq_last_status
== I40E_AQ_RC_EIO
)
1606 status
= I40E_ERR_UNKNOWN_PHY
;
1609 hw
->phy
.phy_types
= le32_to_cpu(abilities
->phy_type
);
1615 * i40e_aq_set_phy_config
1616 * @hw: pointer to the hw struct
1617 * @config: structure with PHY configuration to be set
1618 * @cmd_details: pointer to command details structure or NULL
1620 * Set the various PHY configuration parameters
1621 * supported on the Port.One or more of the Set PHY config parameters may be
1622 * ignored in an MFP mode as the PF may not have the privilege to set some
1623 * of the PHY Config parameters. This status will be indicated by the
1626 enum i40e_status_code
i40e_aq_set_phy_config(struct i40e_hw
*hw
,
1627 struct i40e_aq_set_phy_config
*config
,
1628 struct i40e_asq_cmd_details
*cmd_details
)
1630 struct i40e_aq_desc desc
;
1631 struct i40e_aq_set_phy_config
*cmd
=
1632 (struct i40e_aq_set_phy_config
*)&desc
.params
.raw
;
1633 enum i40e_status_code status
;
1636 return I40E_ERR_PARAM
;
1638 i40e_fill_default_direct_cmd_desc(&desc
,
1639 i40e_aqc_opc_set_phy_config
);
1643 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1650 * @hw: pointer to the hw struct
1652 * Set the requested flow control mode using set_phy_config.
1654 enum i40e_status_code
i40e_set_fc(struct i40e_hw
*hw
, u8
*aq_failures
,
1655 bool atomic_restart
)
1657 enum i40e_fc_mode fc_mode
= hw
->fc
.requested_mode
;
1658 struct i40e_aq_get_phy_abilities_resp abilities
;
1659 struct i40e_aq_set_phy_config config
;
1660 enum i40e_status_code status
;
1661 u8 pause_mask
= 0x0;
1667 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1668 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1670 case I40E_FC_RX_PAUSE
:
1671 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1673 case I40E_FC_TX_PAUSE
:
1674 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1680 /* Get the current phy config */
1681 status
= i40e_aq_get_phy_capabilities(hw
, false, false, &abilities
,
1684 *aq_failures
|= I40E_SET_FC_AQ_FAIL_GET
;
1688 memset(&config
, 0, sizeof(struct i40e_aq_set_phy_config
));
1689 /* clear the old pause settings */
1690 config
.abilities
= abilities
.abilities
& ~(I40E_AQ_PHY_FLAG_PAUSE_TX
) &
1691 ~(I40E_AQ_PHY_FLAG_PAUSE_RX
);
1692 /* set the new abilities */
1693 config
.abilities
|= pause_mask
;
1694 /* If the abilities have changed, then set the new config */
1695 if (config
.abilities
!= abilities
.abilities
) {
1696 /* Auto restart link so settings take effect */
1698 config
.abilities
|= I40E_AQ_PHY_ENABLE_ATOMIC_LINK
;
1699 /* Copy over all the old settings */
1700 config
.phy_type
= abilities
.phy_type
;
1701 config
.link_speed
= abilities
.link_speed
;
1702 config
.eee_capability
= abilities
.eee_capability
;
1703 config
.eeer
= abilities
.eeer_val
;
1704 config
.low_power_ctrl
= abilities
.d3_lpan
;
1705 status
= i40e_aq_set_phy_config(hw
, &config
, NULL
);
1708 *aq_failures
|= I40E_SET_FC_AQ_FAIL_SET
;
1710 /* Update the link info */
1711 status
= i40e_update_link_info(hw
);
1713 /* Wait a little bit (on 40G cards it sometimes takes a really
1714 * long time for link to come back from the atomic reset)
1718 status
= i40e_update_link_info(hw
);
1721 *aq_failures
|= I40E_SET_FC_AQ_FAIL_UPDATE
;
1727 * i40e_aq_clear_pxe_mode
1728 * @hw: pointer to the hw struct
1729 * @cmd_details: pointer to command details structure or NULL
1731 * Tell the firmware that the driver is taking over from PXE
1733 i40e_status
i40e_aq_clear_pxe_mode(struct i40e_hw
*hw
,
1734 struct i40e_asq_cmd_details
*cmd_details
)
1737 struct i40e_aq_desc desc
;
1738 struct i40e_aqc_clear_pxe
*cmd
=
1739 (struct i40e_aqc_clear_pxe
*)&desc
.params
.raw
;
1741 i40e_fill_default_direct_cmd_desc(&desc
,
1742 i40e_aqc_opc_clear_pxe_mode
);
1746 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1748 wr32(hw
, I40E_GLLAN_RCTL_0
, 0x1);
1754 * i40e_aq_set_link_restart_an
1755 * @hw: pointer to the hw struct
1756 * @enable_link: if true: enable link, if false: disable link
1757 * @cmd_details: pointer to command details structure or NULL
1759 * Sets up the link and restarts the Auto-Negotiation over the link.
1761 i40e_status
i40e_aq_set_link_restart_an(struct i40e_hw
*hw
,
1763 struct i40e_asq_cmd_details
*cmd_details
)
1765 struct i40e_aq_desc desc
;
1766 struct i40e_aqc_set_link_restart_an
*cmd
=
1767 (struct i40e_aqc_set_link_restart_an
*)&desc
.params
.raw
;
1770 i40e_fill_default_direct_cmd_desc(&desc
,
1771 i40e_aqc_opc_set_link_restart_an
);
1773 cmd
->command
= I40E_AQ_PHY_RESTART_AN
;
1775 cmd
->command
|= I40E_AQ_PHY_LINK_ENABLE
;
1777 cmd
->command
&= ~I40E_AQ_PHY_LINK_ENABLE
;
1779 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1785 * i40e_aq_get_link_info
1786 * @hw: pointer to the hw struct
1787 * @enable_lse: enable/disable LinkStatusEvent reporting
1788 * @link: pointer to link status structure - optional
1789 * @cmd_details: pointer to command details structure or NULL
1791 * Returns the link status of the adapter.
1793 i40e_status
i40e_aq_get_link_info(struct i40e_hw
*hw
,
1794 bool enable_lse
, struct i40e_link_status
*link
,
1795 struct i40e_asq_cmd_details
*cmd_details
)
1797 struct i40e_aq_desc desc
;
1798 struct i40e_aqc_get_link_status
*resp
=
1799 (struct i40e_aqc_get_link_status
*)&desc
.params
.raw
;
1800 struct i40e_link_status
*hw_link_info
= &hw
->phy
.link_info
;
1802 bool tx_pause
, rx_pause
;
1805 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_link_status
);
1808 command_flags
= I40E_AQ_LSE_ENABLE
;
1810 command_flags
= I40E_AQ_LSE_DISABLE
;
1811 resp
->command_flags
= cpu_to_le16(command_flags
);
1813 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1816 goto aq_get_link_info_exit
;
1818 /* save off old link status information */
1819 hw
->phy
.link_info_old
= *hw_link_info
;
1821 /* update link status */
1822 hw_link_info
->phy_type
= (enum i40e_aq_phy_type
)resp
->phy_type
;
1823 hw
->phy
.media_type
= i40e_get_media_type(hw
);
1824 hw_link_info
->link_speed
= (enum i40e_aq_link_speed
)resp
->link_speed
;
1825 hw_link_info
->link_info
= resp
->link_info
;
1826 hw_link_info
->an_info
= resp
->an_info
;
1827 hw_link_info
->ext_info
= resp
->ext_info
;
1828 hw_link_info
->loopback
= resp
->loopback
;
1829 hw_link_info
->max_frame_size
= le16_to_cpu(resp
->max_frame_size
);
1830 hw_link_info
->pacing
= resp
->config
& I40E_AQ_CONFIG_PACING_MASK
;
1832 /* update fc info */
1833 tx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_TX
);
1834 rx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_RX
);
1835 if (tx_pause
& rx_pause
)
1836 hw
->fc
.current_mode
= I40E_FC_FULL
;
1838 hw
->fc
.current_mode
= I40E_FC_TX_PAUSE
;
1840 hw
->fc
.current_mode
= I40E_FC_RX_PAUSE
;
1842 hw
->fc
.current_mode
= I40E_FC_NONE
;
1844 if (resp
->config
& I40E_AQ_CONFIG_CRC_ENA
)
1845 hw_link_info
->crc_enable
= true;
1847 hw_link_info
->crc_enable
= false;
1849 if (resp
->command_flags
& cpu_to_le16(I40E_AQ_LSE_ENABLE
))
1850 hw_link_info
->lse_enable
= true;
1852 hw_link_info
->lse_enable
= false;
1854 if ((hw
->aq
.fw_maj_ver
< 4 || (hw
->aq
.fw_maj_ver
== 4 &&
1855 hw
->aq
.fw_min_ver
< 40)) && hw_link_info
->phy_type
== 0xE)
1856 hw_link_info
->phy_type
= I40E_PHY_TYPE_10GBASE_SFPP_CU
;
1858 /* save link status information */
1860 *link
= *hw_link_info
;
1862 /* flag cleared so helper functions don't call AQ again */
1863 hw
->phy
.get_link_info
= false;
1865 aq_get_link_info_exit
:
1870 * i40e_aq_set_phy_int_mask
1871 * @hw: pointer to the hw struct
1872 * @mask: interrupt mask to be set
1873 * @cmd_details: pointer to command details structure or NULL
1875 * Set link interrupt mask.
1877 i40e_status
i40e_aq_set_phy_int_mask(struct i40e_hw
*hw
,
1879 struct i40e_asq_cmd_details
*cmd_details
)
1881 struct i40e_aq_desc desc
;
1882 struct i40e_aqc_set_phy_int_mask
*cmd
=
1883 (struct i40e_aqc_set_phy_int_mask
*)&desc
.params
.raw
;
1886 i40e_fill_default_direct_cmd_desc(&desc
,
1887 i40e_aqc_opc_set_phy_int_mask
);
1889 cmd
->event_mask
= cpu_to_le16(mask
);
1891 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1897 * i40e_aq_set_phy_debug
1898 * @hw: pointer to the hw struct
1899 * @cmd_flags: debug command flags
1900 * @cmd_details: pointer to command details structure or NULL
1902 * Reset the external PHY.
1904 enum i40e_status_code
i40e_aq_set_phy_debug(struct i40e_hw
*hw
, u8 cmd_flags
,
1905 struct i40e_asq_cmd_details
*cmd_details
)
1907 struct i40e_aq_desc desc
;
1908 struct i40e_aqc_set_phy_debug
*cmd
=
1909 (struct i40e_aqc_set_phy_debug
*)&desc
.params
.raw
;
1910 enum i40e_status_code status
;
1912 i40e_fill_default_direct_cmd_desc(&desc
,
1913 i40e_aqc_opc_set_phy_debug
);
1915 cmd
->command_flags
= cmd_flags
;
1917 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1924 * @hw: pointer to the hw struct
1925 * @vsi_ctx: pointer to a vsi context struct
1926 * @cmd_details: pointer to command details structure or NULL
1928 * Add a VSI context to the hardware.
1930 i40e_status
i40e_aq_add_vsi(struct i40e_hw
*hw
,
1931 struct i40e_vsi_context
*vsi_ctx
,
1932 struct i40e_asq_cmd_details
*cmd_details
)
1934 struct i40e_aq_desc desc
;
1935 struct i40e_aqc_add_get_update_vsi
*cmd
=
1936 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1937 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1938 (struct i40e_aqc_add_get_update_vsi_completion
*)
1942 i40e_fill_default_direct_cmd_desc(&desc
,
1943 i40e_aqc_opc_add_vsi
);
1945 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->uplink_seid
);
1946 cmd
->connection_type
= vsi_ctx
->connection_type
;
1947 cmd
->vf_id
= vsi_ctx
->vf_num
;
1948 cmd
->vsi_flags
= cpu_to_le16(vsi_ctx
->flags
);
1950 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1952 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1953 sizeof(vsi_ctx
->info
), cmd_details
);
1956 goto aq_add_vsi_exit
;
1958 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1959 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1960 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1961 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1968 * i40e_aq_set_vsi_unicast_promiscuous
1969 * @hw: pointer to the hw struct
1971 * @set: set unicast promiscuous enable/disable
1972 * @cmd_details: pointer to command details structure or NULL
1974 i40e_status
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw
*hw
,
1976 struct i40e_asq_cmd_details
*cmd_details
)
1978 struct i40e_aq_desc desc
;
1979 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1980 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1984 i40e_fill_default_direct_cmd_desc(&desc
,
1985 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1988 flags
|= I40E_AQC_SET_VSI_PROMISC_UNICAST
;
1989 if (((hw
->aq
.api_maj_ver
== 1) && (hw
->aq
.api_min_ver
>= 5)) ||
1990 (hw
->aq
.api_maj_ver
> 1))
1991 flags
|= I40E_AQC_SET_VSI_PROMISC_TX
;
1994 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1996 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST
);
1997 if (((hw
->aq
.api_maj_ver
>= 1) && (hw
->aq
.api_min_ver
>= 5)) ||
1998 (hw
->aq
.api_maj_ver
> 1))
1999 cmd
->valid_flags
|= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX
);
2001 cmd
->seid
= cpu_to_le16(seid
);
2002 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2008 * i40e_aq_set_vsi_multicast_promiscuous
2009 * @hw: pointer to the hw struct
2011 * @set: set multicast promiscuous enable/disable
2012 * @cmd_details: pointer to command details structure or NULL
2014 i40e_status
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw
*hw
,
2015 u16 seid
, bool set
, struct i40e_asq_cmd_details
*cmd_details
)
2017 struct i40e_aq_desc desc
;
2018 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
2019 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
2023 i40e_fill_default_direct_cmd_desc(&desc
,
2024 i40e_aqc_opc_set_vsi_promiscuous_modes
);
2027 flags
|= I40E_AQC_SET_VSI_PROMISC_MULTICAST
;
2029 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
2031 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST
);
2033 cmd
->seid
= cpu_to_le16(seid
);
2034 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2040 * i40e_aq_set_vsi_broadcast
2041 * @hw: pointer to the hw struct
2043 * @set_filter: true to set filter, false to clear filter
2044 * @cmd_details: pointer to command details structure or NULL
2046 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2048 i40e_status
i40e_aq_set_vsi_broadcast(struct i40e_hw
*hw
,
2049 u16 seid
, bool set_filter
,
2050 struct i40e_asq_cmd_details
*cmd_details
)
2052 struct i40e_aq_desc desc
;
2053 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
2054 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
2057 i40e_fill_default_direct_cmd_desc(&desc
,
2058 i40e_aqc_opc_set_vsi_promiscuous_modes
);
2061 cmd
->promiscuous_flags
2062 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
2064 cmd
->promiscuous_flags
2065 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
2067 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
2068 cmd
->seid
= cpu_to_le16(seid
);
2069 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2075 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2076 * @hw: pointer to the hw struct
2078 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2079 * @cmd_details: pointer to command details structure or NULL
2081 i40e_status
i40e_aq_set_vsi_vlan_promisc(struct i40e_hw
*hw
,
2082 u16 seid
, bool enable
,
2083 struct i40e_asq_cmd_details
*cmd_details
)
2085 struct i40e_aq_desc desc
;
2086 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
2087 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
2091 i40e_fill_default_direct_cmd_desc(&desc
,
2092 i40e_aqc_opc_set_vsi_promiscuous_modes
);
2094 flags
|= I40E_AQC_SET_VSI_PROMISC_VLAN
;
2096 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
2097 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN
);
2098 cmd
->seid
= cpu_to_le16(seid
);
2100 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2106 * i40e_get_vsi_params - get VSI configuration info
2107 * @hw: pointer to the hw struct
2108 * @vsi_ctx: pointer to a vsi context struct
2109 * @cmd_details: pointer to command details structure or NULL
2111 i40e_status
i40e_aq_get_vsi_params(struct i40e_hw
*hw
,
2112 struct i40e_vsi_context
*vsi_ctx
,
2113 struct i40e_asq_cmd_details
*cmd_details
)
2115 struct i40e_aq_desc desc
;
2116 struct i40e_aqc_add_get_update_vsi
*cmd
=
2117 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
2118 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
2119 (struct i40e_aqc_add_get_update_vsi_completion
*)
2123 i40e_fill_default_direct_cmd_desc(&desc
,
2124 i40e_aqc_opc_get_vsi_parameters
);
2126 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
2128 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2130 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
2131 sizeof(vsi_ctx
->info
), NULL
);
2134 goto aq_get_vsi_params_exit
;
2136 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
2137 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
2138 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
2139 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
2141 aq_get_vsi_params_exit
:
2146 * i40e_aq_update_vsi_params
2147 * @hw: pointer to the hw struct
2148 * @vsi_ctx: pointer to a vsi context struct
2149 * @cmd_details: pointer to command details structure or NULL
2151 * Update a VSI context.
2153 i40e_status
i40e_aq_update_vsi_params(struct i40e_hw
*hw
,
2154 struct i40e_vsi_context
*vsi_ctx
,
2155 struct i40e_asq_cmd_details
*cmd_details
)
2157 struct i40e_aq_desc desc
;
2158 struct i40e_aqc_add_get_update_vsi
*cmd
=
2159 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
2162 i40e_fill_default_direct_cmd_desc(&desc
,
2163 i40e_aqc_opc_update_vsi_parameters
);
2164 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
2166 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2168 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
2169 sizeof(vsi_ctx
->info
), cmd_details
);
2175 * i40e_aq_get_switch_config
2176 * @hw: pointer to the hardware structure
2177 * @buf: pointer to the result buffer
2178 * @buf_size: length of input buffer
2179 * @start_seid: seid to start for the report, 0 == beginning
2180 * @cmd_details: pointer to command details structure or NULL
2182 * Fill the buf with switch configuration returned from AdminQ command
2184 i40e_status
i40e_aq_get_switch_config(struct i40e_hw
*hw
,
2185 struct i40e_aqc_get_switch_config_resp
*buf
,
2186 u16 buf_size
, u16
*start_seid
,
2187 struct i40e_asq_cmd_details
*cmd_details
)
2189 struct i40e_aq_desc desc
;
2190 struct i40e_aqc_switch_seid
*scfg
=
2191 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
2194 i40e_fill_default_direct_cmd_desc(&desc
,
2195 i40e_aqc_opc_get_switch_config
);
2196 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2197 if (buf_size
> I40E_AQ_LARGE_BUF
)
2198 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2199 scfg
->seid
= cpu_to_le16(*start_seid
);
2201 status
= i40e_asq_send_command(hw
, &desc
, buf
, buf_size
, cmd_details
);
2202 *start_seid
= le16_to_cpu(scfg
->seid
);
2208 * i40e_aq_get_firmware_version
2209 * @hw: pointer to the hw struct
2210 * @fw_major_version: firmware major version
2211 * @fw_minor_version: firmware minor version
2212 * @fw_build: firmware build number
2213 * @api_major_version: major queue version
2214 * @api_minor_version: minor queue version
2215 * @cmd_details: pointer to command details structure or NULL
2217 * Get the firmware version from the admin queue commands
2219 i40e_status
i40e_aq_get_firmware_version(struct i40e_hw
*hw
,
2220 u16
*fw_major_version
, u16
*fw_minor_version
,
2222 u16
*api_major_version
, u16
*api_minor_version
,
2223 struct i40e_asq_cmd_details
*cmd_details
)
2225 struct i40e_aq_desc desc
;
2226 struct i40e_aqc_get_version
*resp
=
2227 (struct i40e_aqc_get_version
*)&desc
.params
.raw
;
2230 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_version
);
2232 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2235 if (fw_major_version
)
2236 *fw_major_version
= le16_to_cpu(resp
->fw_major
);
2237 if (fw_minor_version
)
2238 *fw_minor_version
= le16_to_cpu(resp
->fw_minor
);
2240 *fw_build
= le32_to_cpu(resp
->fw_build
);
2241 if (api_major_version
)
2242 *api_major_version
= le16_to_cpu(resp
->api_major
);
2243 if (api_minor_version
)
2244 *api_minor_version
= le16_to_cpu(resp
->api_minor
);
2251 * i40e_aq_send_driver_version
2252 * @hw: pointer to the hw struct
2253 * @dv: driver's major, minor version
2254 * @cmd_details: pointer to command details structure or NULL
2256 * Send the driver version to the firmware
2258 i40e_status
i40e_aq_send_driver_version(struct i40e_hw
*hw
,
2259 struct i40e_driver_version
*dv
,
2260 struct i40e_asq_cmd_details
*cmd_details
)
2262 struct i40e_aq_desc desc
;
2263 struct i40e_aqc_driver_version
*cmd
=
2264 (struct i40e_aqc_driver_version
*)&desc
.params
.raw
;
2269 return I40E_ERR_PARAM
;
2271 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_driver_version
);
2273 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
);
2274 cmd
->driver_major_ver
= dv
->major_version
;
2275 cmd
->driver_minor_ver
= dv
->minor_version
;
2276 cmd
->driver_build_ver
= dv
->build_version
;
2277 cmd
->driver_subbuild_ver
= dv
->subbuild_version
;
2280 while (len
< sizeof(dv
->driver_string
) &&
2281 (dv
->driver_string
[len
] < 0x80) &&
2282 dv
->driver_string
[len
])
2284 status
= i40e_asq_send_command(hw
, &desc
, dv
->driver_string
,
2291 * i40e_get_link_status - get status of the HW network link
2292 * @hw: pointer to the hw struct
2293 * @link_up: pointer to bool (true/false = linkup/linkdown)
2295 * Variable link_up true if link is up, false if link is down.
2296 * The variable link_up is invalid if returned value of status != 0
2298 * Side effect: LinkStatusEvent reporting becomes enabled
2300 i40e_status
i40e_get_link_status(struct i40e_hw
*hw
, bool *link_up
)
2302 i40e_status status
= 0;
2304 if (hw
->phy
.get_link_info
) {
2305 status
= i40e_update_link_info(hw
);
2308 i40e_debug(hw
, I40E_DEBUG_LINK
, "get link failed: status %d\n",
2312 *link_up
= hw
->phy
.link_info
.link_info
& I40E_AQ_LINK_UP
;
2318 * i40e_updatelink_status - update status of the HW network link
2319 * @hw: pointer to the hw struct
2321 i40e_status
i40e_update_link_info(struct i40e_hw
*hw
)
2323 struct i40e_aq_get_phy_abilities_resp abilities
;
2324 i40e_status status
= 0;
2326 status
= i40e_aq_get_link_info(hw
, true, NULL
, NULL
);
2330 if (hw
->phy
.link_info
.link_info
& I40E_AQ_MEDIA_AVAILABLE
) {
2331 status
= i40e_aq_get_phy_capabilities(hw
, false, false,
2336 memcpy(hw
->phy
.link_info
.module_type
, &abilities
.module_type
,
2337 sizeof(hw
->phy
.link_info
.module_type
));
2344 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2345 * @hw: pointer to the hw struct
2346 * @uplink_seid: the MAC or other gizmo SEID
2347 * @downlink_seid: the VSI SEID
2348 * @enabled_tc: bitmap of TCs to be enabled
2349 * @default_port: true for default port VSI, false for control port
2350 * @veb_seid: pointer to where to put the resulting VEB SEID
2351 * @enable_stats: true to turn on VEB stats
2352 * @cmd_details: pointer to command details structure or NULL
2354 * This asks the FW to add a VEB between the uplink and downlink
2355 * elements. If the uplink SEID is 0, this will be a floating VEB.
2357 i40e_status
i40e_aq_add_veb(struct i40e_hw
*hw
, u16 uplink_seid
,
2358 u16 downlink_seid
, u8 enabled_tc
,
2359 bool default_port
, u16
*veb_seid
,
2361 struct i40e_asq_cmd_details
*cmd_details
)
2363 struct i40e_aq_desc desc
;
2364 struct i40e_aqc_add_veb
*cmd
=
2365 (struct i40e_aqc_add_veb
*)&desc
.params
.raw
;
2366 struct i40e_aqc_add_veb_completion
*resp
=
2367 (struct i40e_aqc_add_veb_completion
*)&desc
.params
.raw
;
2371 /* SEIDs need to either both be set or both be 0 for floating VEB */
2372 if (!!uplink_seid
!= !!downlink_seid
)
2373 return I40E_ERR_PARAM
;
2375 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_veb
);
2377 cmd
->uplink_seid
= cpu_to_le16(uplink_seid
);
2378 cmd
->downlink_seid
= cpu_to_le16(downlink_seid
);
2379 cmd
->enable_tcs
= enabled_tc
;
2381 veb_flags
|= I40E_AQC_ADD_VEB_FLOATING
;
2383 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT
;
2385 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DATA
;
2387 /* reverse logic here: set the bitflag to disable the stats */
2389 veb_flags
|= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS
;
2391 cmd
->veb_flags
= cpu_to_le16(veb_flags
);
2393 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2395 if (!status
&& veb_seid
)
2396 *veb_seid
= le16_to_cpu(resp
->veb_seid
);
2402 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2403 * @hw: pointer to the hw struct
2404 * @veb_seid: the SEID of the VEB to query
2405 * @switch_id: the uplink switch id
2406 * @floating: set to true if the VEB is floating
2407 * @statistic_index: index of the stats counter block for this VEB
2408 * @vebs_used: number of VEB's used by function
2409 * @vebs_free: total VEB's not reserved by any function
2410 * @cmd_details: pointer to command details structure or NULL
2412 * This retrieves the parameters for a particular VEB, specified by
2413 * uplink_seid, and returns them to the caller.
2415 i40e_status
i40e_aq_get_veb_parameters(struct i40e_hw
*hw
,
2416 u16 veb_seid
, u16
*switch_id
,
2417 bool *floating
, u16
*statistic_index
,
2418 u16
*vebs_used
, u16
*vebs_free
,
2419 struct i40e_asq_cmd_details
*cmd_details
)
2421 struct i40e_aq_desc desc
;
2422 struct i40e_aqc_get_veb_parameters_completion
*cmd_resp
=
2423 (struct i40e_aqc_get_veb_parameters_completion
*)
2428 return I40E_ERR_PARAM
;
2430 i40e_fill_default_direct_cmd_desc(&desc
,
2431 i40e_aqc_opc_get_veb_parameters
);
2432 cmd_resp
->seid
= cpu_to_le16(veb_seid
);
2434 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2439 *switch_id
= le16_to_cpu(cmd_resp
->switch_id
);
2440 if (statistic_index
)
2441 *statistic_index
= le16_to_cpu(cmd_resp
->statistic_index
);
2443 *vebs_used
= le16_to_cpu(cmd_resp
->vebs_used
);
2445 *vebs_free
= le16_to_cpu(cmd_resp
->vebs_free
);
2447 u16 flags
= le16_to_cpu(cmd_resp
->veb_flags
);
2449 if (flags
& I40E_AQC_ADD_VEB_FLOATING
)
2460 * i40e_aq_add_macvlan
2461 * @hw: pointer to the hw struct
2462 * @seid: VSI for the mac address
2463 * @mv_list: list of macvlans to be added
2464 * @count: length of the list
2465 * @cmd_details: pointer to command details structure or NULL
2467 * Add MAC/VLAN addresses to the HW filtering
2469 i40e_status
i40e_aq_add_macvlan(struct i40e_hw
*hw
, u16 seid
,
2470 struct i40e_aqc_add_macvlan_element_data
*mv_list
,
2471 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
2473 struct i40e_aq_desc desc
;
2474 struct i40e_aqc_macvlan
*cmd
=
2475 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
2480 if (count
== 0 || !mv_list
|| !hw
)
2481 return I40E_ERR_PARAM
;
2483 buf_size
= count
* sizeof(*mv_list
);
2485 /* prep the rest of the request */
2486 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_macvlan
);
2487 cmd
->num_addresses
= cpu_to_le16(count
);
2488 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
2492 for (i
= 0; i
< count
; i
++)
2493 if (is_multicast_ether_addr(mv_list
[i
].mac_addr
))
2495 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC
);
2497 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2498 if (buf_size
> I40E_AQ_LARGE_BUF
)
2499 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2501 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
2508 * i40e_aq_remove_macvlan
2509 * @hw: pointer to the hw struct
2510 * @seid: VSI for the mac address
2511 * @mv_list: list of macvlans to be removed
2512 * @count: length of the list
2513 * @cmd_details: pointer to command details structure or NULL
2515 * Remove MAC/VLAN addresses from the HW filtering
2517 i40e_status
i40e_aq_remove_macvlan(struct i40e_hw
*hw
, u16 seid
,
2518 struct i40e_aqc_remove_macvlan_element_data
*mv_list
,
2519 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
2521 struct i40e_aq_desc desc
;
2522 struct i40e_aqc_macvlan
*cmd
=
2523 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
2527 if (count
== 0 || !mv_list
|| !hw
)
2528 return I40E_ERR_PARAM
;
2530 buf_size
= count
* sizeof(*mv_list
);
2532 /* prep the rest of the request */
2533 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_remove_macvlan
);
2534 cmd
->num_addresses
= cpu_to_le16(count
);
2535 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
2539 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2540 if (buf_size
> I40E_AQ_LARGE_BUF
)
2541 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2543 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
2550 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2551 * @hw: pointer to the hw struct
2552 * @opcode: AQ opcode for add or delete mirror rule
2553 * @sw_seid: Switch SEID (to which rule refers)
2554 * @rule_type: Rule Type (ingress/egress/VLAN)
2555 * @id: Destination VSI SEID or Rule ID
2556 * @count: length of the list
2557 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2558 * @cmd_details: pointer to command details structure or NULL
2559 * @rule_id: Rule ID returned from FW
2560 * @rule_used: Number of rules used in internal switch
2561 * @rule_free: Number of rules free in internal switch
2563 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2564 * VEBs/VEPA elements only
2566 static i40e_status
i40e_mirrorrule_op(struct i40e_hw
*hw
,
2567 u16 opcode
, u16 sw_seid
, u16 rule_type
, u16 id
,
2568 u16 count
, __le16
*mr_list
,
2569 struct i40e_asq_cmd_details
*cmd_details
,
2570 u16
*rule_id
, u16
*rules_used
, u16
*rules_free
)
2572 struct i40e_aq_desc desc
;
2573 struct i40e_aqc_add_delete_mirror_rule
*cmd
=
2574 (struct i40e_aqc_add_delete_mirror_rule
*)&desc
.params
.raw
;
2575 struct i40e_aqc_add_delete_mirror_rule_completion
*resp
=
2576 (struct i40e_aqc_add_delete_mirror_rule_completion
*)&desc
.params
.raw
;
2580 buf_size
= count
* sizeof(*mr_list
);
2582 /* prep the rest of the request */
2583 i40e_fill_default_direct_cmd_desc(&desc
, opcode
);
2584 cmd
->seid
= cpu_to_le16(sw_seid
);
2585 cmd
->rule_type
= cpu_to_le16(rule_type
&
2586 I40E_AQC_MIRROR_RULE_TYPE_MASK
);
2587 cmd
->num_entries
= cpu_to_le16(count
);
2588 /* Dest VSI for add, rule_id for delete */
2589 cmd
->destination
= cpu_to_le16(id
);
2591 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
|
2593 if (buf_size
> I40E_AQ_LARGE_BUF
)
2594 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2597 status
= i40e_asq_send_command(hw
, &desc
, mr_list
, buf_size
,
2600 hw
->aq
.asq_last_status
== I40E_AQ_RC_ENOSPC
) {
2602 *rule_id
= le16_to_cpu(resp
->rule_id
);
2604 *rules_used
= le16_to_cpu(resp
->mirror_rules_used
);
2606 *rules_free
= le16_to_cpu(resp
->mirror_rules_free
);
2612 * i40e_aq_add_mirrorrule - add a mirror rule
2613 * @hw: pointer to the hw struct
2614 * @sw_seid: Switch SEID (to which rule refers)
2615 * @rule_type: Rule Type (ingress/egress/VLAN)
2616 * @dest_vsi: SEID of VSI to which packets will be mirrored
2617 * @count: length of the list
2618 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2619 * @cmd_details: pointer to command details structure or NULL
2620 * @rule_id: Rule ID returned from FW
2621 * @rule_used: Number of rules used in internal switch
2622 * @rule_free: Number of rules free in internal switch
2624 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2626 i40e_status
i40e_aq_add_mirrorrule(struct i40e_hw
*hw
, u16 sw_seid
,
2627 u16 rule_type
, u16 dest_vsi
, u16 count
, __le16
*mr_list
,
2628 struct i40e_asq_cmd_details
*cmd_details
,
2629 u16
*rule_id
, u16
*rules_used
, u16
*rules_free
)
2631 if (!(rule_type
== I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS
||
2632 rule_type
== I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS
)) {
2633 if (count
== 0 || !mr_list
)
2634 return I40E_ERR_PARAM
;
2637 return i40e_mirrorrule_op(hw
, i40e_aqc_opc_add_mirror_rule
, sw_seid
,
2638 rule_type
, dest_vsi
, count
, mr_list
,
2639 cmd_details
, rule_id
, rules_used
, rules_free
);
2643 * i40e_aq_delete_mirrorrule - delete a mirror rule
2644 * @hw: pointer to the hw struct
2645 * @sw_seid: Switch SEID (to which rule refers)
2646 * @rule_type: Rule Type (ingress/egress/VLAN)
2647 * @count: length of the list
2648 * @rule_id: Rule ID that is returned in the receive desc as part of
2650 * @mr_list: list of mirrored VLAN IDs to be removed
2651 * @cmd_details: pointer to command details structure or NULL
2652 * @rule_used: Number of rules used in internal switch
2653 * @rule_free: Number of rules free in internal switch
2655 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2657 i40e_status
i40e_aq_delete_mirrorrule(struct i40e_hw
*hw
, u16 sw_seid
,
2658 u16 rule_type
, u16 rule_id
, u16 count
, __le16
*mr_list
,
2659 struct i40e_asq_cmd_details
*cmd_details
,
2660 u16
*rules_used
, u16
*rules_free
)
2662 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2663 if (rule_type
!= I40E_AQC_MIRROR_RULE_TYPE_VLAN
) {
2665 return I40E_ERR_PARAM
;
2667 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2668 * mirroring. For other rule_type, count and rule_type should
2671 if (count
== 0 || !mr_list
)
2672 return I40E_ERR_PARAM
;
2675 return i40e_mirrorrule_op(hw
, i40e_aqc_opc_delete_mirror_rule
, sw_seid
,
2676 rule_type
, rule_id
, count
, mr_list
,
2677 cmd_details
, NULL
, rules_used
, rules_free
);
2681 * i40e_aq_send_msg_to_vf
2682 * @hw: pointer to the hardware structure
2683 * @vfid: VF id to send msg
2684 * @v_opcode: opcodes for VF-PF communication
2685 * @v_retval: return error code
2686 * @msg: pointer to the msg buffer
2687 * @msglen: msg length
2688 * @cmd_details: pointer to command details
2692 i40e_status
i40e_aq_send_msg_to_vf(struct i40e_hw
*hw
, u16 vfid
,
2693 u32 v_opcode
, u32 v_retval
, u8
*msg
, u16 msglen
,
2694 struct i40e_asq_cmd_details
*cmd_details
)
2696 struct i40e_aq_desc desc
;
2697 struct i40e_aqc_pf_vf_message
*cmd
=
2698 (struct i40e_aqc_pf_vf_message
*)&desc
.params
.raw
;
2701 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_send_msg_to_vf
);
2702 cmd
->id
= cpu_to_le32(vfid
);
2703 desc
.cookie_high
= cpu_to_le32(v_opcode
);
2704 desc
.cookie_low
= cpu_to_le32(v_retval
);
2705 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_SI
);
2707 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
|
2709 if (msglen
> I40E_AQ_LARGE_BUF
)
2710 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2711 desc
.datalen
= cpu_to_le16(msglen
);
2713 status
= i40e_asq_send_command(hw
, &desc
, msg
, msglen
, cmd_details
);
2719 * i40e_aq_debug_read_register
2720 * @hw: pointer to the hw struct
2721 * @reg_addr: register address
2722 * @reg_val: register value
2723 * @cmd_details: pointer to command details structure or NULL
2725 * Read the register using the admin queue commands
2727 i40e_status
i40e_aq_debug_read_register(struct i40e_hw
*hw
,
2728 u32 reg_addr
, u64
*reg_val
,
2729 struct i40e_asq_cmd_details
*cmd_details
)
2731 struct i40e_aq_desc desc
;
2732 struct i40e_aqc_debug_reg_read_write
*cmd_resp
=
2733 (struct i40e_aqc_debug_reg_read_write
*)&desc
.params
.raw
;
2736 if (reg_val
== NULL
)
2737 return I40E_ERR_PARAM
;
2739 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_debug_read_reg
);
2741 cmd_resp
->address
= cpu_to_le32(reg_addr
);
2743 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2746 *reg_val
= ((u64
)le32_to_cpu(cmd_resp
->value_high
) << 32) |
2747 (u64
)le32_to_cpu(cmd_resp
->value_low
);
2754 * i40e_aq_debug_write_register
2755 * @hw: pointer to the hw struct
2756 * @reg_addr: register address
2757 * @reg_val: register value
2758 * @cmd_details: pointer to command details structure or NULL
2760 * Write to a register using the admin queue commands
2762 i40e_status
i40e_aq_debug_write_register(struct i40e_hw
*hw
,
2763 u32 reg_addr
, u64 reg_val
,
2764 struct i40e_asq_cmd_details
*cmd_details
)
2766 struct i40e_aq_desc desc
;
2767 struct i40e_aqc_debug_reg_read_write
*cmd
=
2768 (struct i40e_aqc_debug_reg_read_write
*)&desc
.params
.raw
;
2771 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_debug_write_reg
);
2773 cmd
->address
= cpu_to_le32(reg_addr
);
2774 cmd
->value_high
= cpu_to_le32((u32
)(reg_val
>> 32));
2775 cmd
->value_low
= cpu_to_le32((u32
)(reg_val
& 0xFFFFFFFF));
2777 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2783 * i40e_aq_set_hmc_resource_profile
2784 * @hw: pointer to the hw struct
2785 * @profile: type of profile the HMC is to be set as
2786 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2787 * @cmd_details: pointer to command details structure or NULL
2789 * set the HMC profile of the device.
2791 i40e_status
i40e_aq_set_hmc_resource_profile(struct i40e_hw
*hw
,
2792 enum i40e_aq_hmc_profile profile
,
2793 u8 pe_vf_enabled_count
,
2794 struct i40e_asq_cmd_details
*cmd_details
)
2796 struct i40e_aq_desc desc
;
2797 struct i40e_aq_get_set_hmc_resource_profile
*cmd
=
2798 (struct i40e_aq_get_set_hmc_resource_profile
*)&desc
.params
.raw
;
2801 i40e_fill_default_direct_cmd_desc(&desc
,
2802 i40e_aqc_opc_set_hmc_resource_profile
);
2804 cmd
->pm_profile
= (u8
)profile
;
2805 cmd
->pe_vf_enabled
= pe_vf_enabled_count
;
2807 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2813 * i40e_aq_request_resource
2814 * @hw: pointer to the hw struct
2815 * @resource: resource id
2816 * @access: access type
2817 * @sdp_number: resource number
2818 * @timeout: the maximum time in ms that the driver may hold the resource
2819 * @cmd_details: pointer to command details structure or NULL
2821 * requests common resource using the admin queue commands
2823 i40e_status
i40e_aq_request_resource(struct i40e_hw
*hw
,
2824 enum i40e_aq_resources_ids resource
,
2825 enum i40e_aq_resource_access_type access
,
2826 u8 sdp_number
, u64
*timeout
,
2827 struct i40e_asq_cmd_details
*cmd_details
)
2829 struct i40e_aq_desc desc
;
2830 struct i40e_aqc_request_resource
*cmd_resp
=
2831 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2834 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_request_resource
);
2836 cmd_resp
->resource_id
= cpu_to_le16(resource
);
2837 cmd_resp
->access_type
= cpu_to_le16(access
);
2838 cmd_resp
->resource_number
= cpu_to_le32(sdp_number
);
2840 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2841 /* The completion specifies the maximum time in ms that the driver
2842 * may hold the resource in the Timeout field.
2843 * If the resource is held by someone else, the command completes with
2844 * busy return value and the timeout field indicates the maximum time
2845 * the current owner of the resource has to free it.
2847 if (!status
|| hw
->aq
.asq_last_status
== I40E_AQ_RC_EBUSY
)
2848 *timeout
= le32_to_cpu(cmd_resp
->timeout
);
2854 * i40e_aq_release_resource
2855 * @hw: pointer to the hw struct
2856 * @resource: resource id
2857 * @sdp_number: resource number
2858 * @cmd_details: pointer to command details structure or NULL
2860 * release common resource using the admin queue commands
2862 i40e_status
i40e_aq_release_resource(struct i40e_hw
*hw
,
2863 enum i40e_aq_resources_ids resource
,
2865 struct i40e_asq_cmd_details
*cmd_details
)
2867 struct i40e_aq_desc desc
;
2868 struct i40e_aqc_request_resource
*cmd
=
2869 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2872 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_release_resource
);
2874 cmd
->resource_id
= cpu_to_le16(resource
);
2875 cmd
->resource_number
= cpu_to_le32(sdp_number
);
2877 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2884 * @hw: pointer to the hw struct
2885 * @module_pointer: module pointer location in words from the NVM beginning
2886 * @offset: byte offset from the module beginning
2887 * @length: length of the section to be read (in bytes from the offset)
2888 * @data: command buffer (size [bytes] = length)
2889 * @last_command: tells if this is the last command in a series
2890 * @cmd_details: pointer to command details structure or NULL
2892 * Read the NVM using the admin queue commands
2894 i40e_status
i40e_aq_read_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2895 u32 offset
, u16 length
, void *data
,
2897 struct i40e_asq_cmd_details
*cmd_details
)
2899 struct i40e_aq_desc desc
;
2900 struct i40e_aqc_nvm_update
*cmd
=
2901 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2904 /* In offset the highest byte must be zeroed. */
2905 if (offset
& 0xFF000000) {
2906 status
= I40E_ERR_PARAM
;
2907 goto i40e_aq_read_nvm_exit
;
2910 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_read
);
2912 /* If this is the last command in a series, set the proper flag. */
2914 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2915 cmd
->module_pointer
= module_pointer
;
2916 cmd
->offset
= cpu_to_le32(offset
);
2917 cmd
->length
= cpu_to_le16(length
);
2919 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2920 if (length
> I40E_AQ_LARGE_BUF
)
2921 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2923 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
2925 i40e_aq_read_nvm_exit
:
2931 * @hw: pointer to the hw struct
2932 * @module_pointer: module pointer location in words from the NVM beginning
2933 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2934 * @length: length of the section to be erased (expressed in 4 KB)
2935 * @last_command: tells if this is the last command in a series
2936 * @cmd_details: pointer to command details structure or NULL
2938 * Erase the NVM sector using the admin queue commands
2940 i40e_status
i40e_aq_erase_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2941 u32 offset
, u16 length
, bool last_command
,
2942 struct i40e_asq_cmd_details
*cmd_details
)
2944 struct i40e_aq_desc desc
;
2945 struct i40e_aqc_nvm_update
*cmd
=
2946 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2949 /* In offset the highest byte must be zeroed. */
2950 if (offset
& 0xFF000000) {
2951 status
= I40E_ERR_PARAM
;
2952 goto i40e_aq_erase_nvm_exit
;
2955 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_erase
);
2957 /* If this is the last command in a series, set the proper flag. */
2959 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2960 cmd
->module_pointer
= module_pointer
;
2961 cmd
->offset
= cpu_to_le32(offset
);
2962 cmd
->length
= cpu_to_le16(length
);
2964 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2966 i40e_aq_erase_nvm_exit
:
2971 * i40e_parse_discover_capabilities
2972 * @hw: pointer to the hw struct
2973 * @buff: pointer to a buffer containing device/function capability records
2974 * @cap_count: number of capability records in the list
2975 * @list_type_opc: type of capabilities list to parse
2977 * Parse the device/function capabilities list.
2979 static void i40e_parse_discover_capabilities(struct i40e_hw
*hw
, void *buff
,
2981 enum i40e_admin_queue_opc list_type_opc
)
2983 struct i40e_aqc_list_capabilities_element_resp
*cap
;
2984 u32 valid_functions
, num_functions
;
2985 u32 number
, logical_id
, phys_id
;
2986 struct i40e_hw_capabilities
*p
;
2991 cap
= (struct i40e_aqc_list_capabilities_element_resp
*) buff
;
2993 if (list_type_opc
== i40e_aqc_opc_list_dev_capabilities
)
2995 else if (list_type_opc
== i40e_aqc_opc_list_func_capabilities
)
3000 for (i
= 0; i
< cap_count
; i
++, cap
++) {
3001 id
= le16_to_cpu(cap
->id
);
3002 number
= le32_to_cpu(cap
->number
);
3003 logical_id
= le32_to_cpu(cap
->logical_id
);
3004 phys_id
= le32_to_cpu(cap
->phys_id
);
3005 major_rev
= cap
->major_rev
;
3008 case I40E_AQ_CAP_ID_SWITCH_MODE
:
3009 p
->switch_mode
= number
;
3011 case I40E_AQ_CAP_ID_MNG_MODE
:
3012 p
->management_mode
= number
;
3014 case I40E_AQ_CAP_ID_NPAR_ACTIVE
:
3015 p
->npar_enable
= number
;
3017 case I40E_AQ_CAP_ID_OS2BMC_CAP
:
3020 case I40E_AQ_CAP_ID_FUNCTIONS_VALID
:
3021 p
->valid_functions
= number
;
3023 case I40E_AQ_CAP_ID_SRIOV
:
3025 p
->sr_iov_1_1
= true;
3027 case I40E_AQ_CAP_ID_VF
:
3028 p
->num_vfs
= number
;
3029 p
->vf_base_id
= logical_id
;
3031 case I40E_AQ_CAP_ID_VMDQ
:
3035 case I40E_AQ_CAP_ID_8021QBG
:
3037 p
->evb_802_1_qbg
= true;
3039 case I40E_AQ_CAP_ID_8021QBR
:
3041 p
->evb_802_1_qbh
= true;
3043 case I40E_AQ_CAP_ID_VSI
:
3044 p
->num_vsis
= number
;
3046 case I40E_AQ_CAP_ID_DCB
:
3049 p
->enabled_tcmap
= logical_id
;
3053 case I40E_AQ_CAP_ID_FCOE
:
3057 case I40E_AQ_CAP_ID_ISCSI
:
3061 case I40E_AQ_CAP_ID_RSS
:
3063 p
->rss_table_size
= number
;
3064 p
->rss_table_entry_width
= logical_id
;
3066 case I40E_AQ_CAP_ID_RXQ
:
3067 p
->num_rx_qp
= number
;
3068 p
->base_queue
= phys_id
;
3070 case I40E_AQ_CAP_ID_TXQ
:
3071 p
->num_tx_qp
= number
;
3072 p
->base_queue
= phys_id
;
3074 case I40E_AQ_CAP_ID_MSIX
:
3075 p
->num_msix_vectors
= number
;
3077 case I40E_AQ_CAP_ID_VF_MSIX
:
3078 p
->num_msix_vectors_vf
= number
;
3080 case I40E_AQ_CAP_ID_FLEX10
:
3081 if (major_rev
== 1) {
3083 p
->flex10_enable
= true;
3084 p
->flex10_capable
= true;
3087 /* Capability revision >= 2 */
3089 p
->flex10_enable
= true;
3091 p
->flex10_capable
= true;
3093 p
->flex10_mode
= logical_id
;
3094 p
->flex10_status
= phys_id
;
3096 case I40E_AQ_CAP_ID_CEM
:
3100 case I40E_AQ_CAP_ID_IWARP
:
3104 case I40E_AQ_CAP_ID_LED
:
3105 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
3106 p
->led
[phys_id
] = true;
3108 case I40E_AQ_CAP_ID_SDP
:
3109 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
3110 p
->sdp
[phys_id
] = true;
3112 case I40E_AQ_CAP_ID_MDIO
:
3114 p
->mdio_port_num
= phys_id
;
3115 p
->mdio_port_mode
= logical_id
;
3118 case I40E_AQ_CAP_ID_1588
:
3120 p
->ieee_1588
= true;
3122 case I40E_AQ_CAP_ID_FLOW_DIRECTOR
:
3124 p
->fd_filters_guaranteed
= number
;
3125 p
->fd_filters_best_effort
= logical_id
;
3127 case I40E_AQ_CAP_ID_WSR_PROT
:
3128 p
->wr_csr_prot
= (u64
)number
;
3129 p
->wr_csr_prot
|= (u64
)logical_id
<< 32;
3137 i40e_debug(hw
, I40E_DEBUG_ALL
, "device is FCoE capable\n");
3139 /* Software override ensuring FCoE is disabled if npar or mfp
3140 * mode because it is not supported in these modes.
3142 if (p
->npar_enable
|| p
->flex10_enable
)
3145 /* count the enabled ports (aka the "not disabled" ports) */
3147 for (i
= 0; i
< 4; i
++) {
3148 u32 port_cfg_reg
= I40E_PRTGEN_CNF
+ (4 * i
);
3151 /* use AQ read to get the physical register offset instead
3152 * of the port relative offset
3154 i40e_aq_debug_read_register(hw
, port_cfg_reg
, &port_cfg
, NULL
);
3155 if (!(port_cfg
& I40E_PRTGEN_CNF_PORT_DIS_MASK
))
3159 valid_functions
= p
->valid_functions
;
3161 while (valid_functions
) {
3162 if (valid_functions
& 1)
3164 valid_functions
>>= 1;
3167 /* partition id is 1-based, and functions are evenly spread
3168 * across the ports as partitions
3170 hw
->partition_id
= (hw
->pf_id
/ hw
->num_ports
) + 1;
3171 hw
->num_partitions
= num_functions
/ hw
->num_ports
;
3173 /* additional HW specific goodies that might
3174 * someday be HW version specific
3176 p
->rx_buf_chain_len
= I40E_MAX_CHAINED_RX_BUFFERS
;
3180 * i40e_aq_discover_capabilities
3181 * @hw: pointer to the hw struct
3182 * @buff: a virtual buffer to hold the capabilities
3183 * @buff_size: Size of the virtual buffer
3184 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3185 * @list_type_opc: capabilities type to discover - pass in the command opcode
3186 * @cmd_details: pointer to command details structure or NULL
3188 * Get the device capabilities descriptions from the firmware
3190 i40e_status
i40e_aq_discover_capabilities(struct i40e_hw
*hw
,
3191 void *buff
, u16 buff_size
, u16
*data_size
,
3192 enum i40e_admin_queue_opc list_type_opc
,
3193 struct i40e_asq_cmd_details
*cmd_details
)
3195 struct i40e_aqc_list_capabilites
*cmd
;
3196 struct i40e_aq_desc desc
;
3197 i40e_status status
= 0;
3199 cmd
= (struct i40e_aqc_list_capabilites
*)&desc
.params
.raw
;
3201 if (list_type_opc
!= i40e_aqc_opc_list_func_capabilities
&&
3202 list_type_opc
!= i40e_aqc_opc_list_dev_capabilities
) {
3203 status
= I40E_ERR_PARAM
;
3207 i40e_fill_default_direct_cmd_desc(&desc
, list_type_opc
);
3209 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3210 if (buff_size
> I40E_AQ_LARGE_BUF
)
3211 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3213 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3214 *data_size
= le16_to_cpu(desc
.datalen
);
3219 i40e_parse_discover_capabilities(hw
, buff
, le32_to_cpu(cmd
->count
),
3227 * i40e_aq_update_nvm
3228 * @hw: pointer to the hw struct
3229 * @module_pointer: module pointer location in words from the NVM beginning
3230 * @offset: byte offset from the module beginning
3231 * @length: length of the section to be written (in bytes from the offset)
3232 * @data: command buffer (size [bytes] = length)
3233 * @last_command: tells if this is the last command in a series
3234 * @cmd_details: pointer to command details structure or NULL
3236 * Update the NVM using the admin queue commands
3238 i40e_status
i40e_aq_update_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
3239 u32 offset
, u16 length
, void *data
,
3241 struct i40e_asq_cmd_details
*cmd_details
)
3243 struct i40e_aq_desc desc
;
3244 struct i40e_aqc_nvm_update
*cmd
=
3245 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
3248 /* In offset the highest byte must be zeroed. */
3249 if (offset
& 0xFF000000) {
3250 status
= I40E_ERR_PARAM
;
3251 goto i40e_aq_update_nvm_exit
;
3254 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_update
);
3256 /* If this is the last command in a series, set the proper flag. */
3258 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
3259 cmd
->module_pointer
= module_pointer
;
3260 cmd
->offset
= cpu_to_le32(offset
);
3261 cmd
->length
= cpu_to_le16(length
);
3263 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
3264 if (length
> I40E_AQ_LARGE_BUF
)
3265 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3267 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
3269 i40e_aq_update_nvm_exit
:
3274 * i40e_aq_get_lldp_mib
3275 * @hw: pointer to the hw struct
3276 * @bridge_type: type of bridge requested
3277 * @mib_type: Local, Remote or both Local and Remote MIBs
3278 * @buff: pointer to a user supplied buffer to store the MIB block
3279 * @buff_size: size of the buffer (in bytes)
3280 * @local_len : length of the returned Local LLDP MIB
3281 * @remote_len: length of the returned Remote LLDP MIB
3282 * @cmd_details: pointer to command details structure or NULL
3284 * Requests the complete LLDP MIB (entire packet).
3286 i40e_status
i40e_aq_get_lldp_mib(struct i40e_hw
*hw
, u8 bridge_type
,
3287 u8 mib_type
, void *buff
, u16 buff_size
,
3288 u16
*local_len
, u16
*remote_len
,
3289 struct i40e_asq_cmd_details
*cmd_details
)
3291 struct i40e_aq_desc desc
;
3292 struct i40e_aqc_lldp_get_mib
*cmd
=
3293 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
3294 struct i40e_aqc_lldp_get_mib
*resp
=
3295 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
3298 if (buff_size
== 0 || !buff
)
3299 return I40E_ERR_PARAM
;
3301 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_get_mib
);
3302 /* Indirect Command */
3303 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3305 cmd
->type
= mib_type
& I40E_AQ_LLDP_MIB_TYPE_MASK
;
3306 cmd
->type
|= ((bridge_type
<< I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT
) &
3307 I40E_AQ_LLDP_BRIDGE_TYPE_MASK
);
3309 desc
.datalen
= cpu_to_le16(buff_size
);
3311 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3312 if (buff_size
> I40E_AQ_LARGE_BUF
)
3313 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3315 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3317 if (local_len
!= NULL
)
3318 *local_len
= le16_to_cpu(resp
->local_len
);
3319 if (remote_len
!= NULL
)
3320 *remote_len
= le16_to_cpu(resp
->remote_len
);
3327 * i40e_aq_cfg_lldp_mib_change_event
3328 * @hw: pointer to the hw struct
3329 * @enable_update: Enable or Disable event posting
3330 * @cmd_details: pointer to command details structure or NULL
3332 * Enable or Disable posting of an event on ARQ when LLDP MIB
3333 * associated with the interface changes
3335 i40e_status
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw
*hw
,
3337 struct i40e_asq_cmd_details
*cmd_details
)
3339 struct i40e_aq_desc desc
;
3340 struct i40e_aqc_lldp_update_mib
*cmd
=
3341 (struct i40e_aqc_lldp_update_mib
*)&desc
.params
.raw
;
3344 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_update_mib
);
3347 cmd
->command
|= I40E_AQ_LLDP_MIB_UPDATE_DISABLE
;
3349 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3356 * @hw: pointer to the hw struct
3357 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3358 * @cmd_details: pointer to command details structure or NULL
3360 * Stop or Shutdown the embedded LLDP Agent
3362 i40e_status
i40e_aq_stop_lldp(struct i40e_hw
*hw
, bool shutdown_agent
,
3363 struct i40e_asq_cmd_details
*cmd_details
)
3365 struct i40e_aq_desc desc
;
3366 struct i40e_aqc_lldp_stop
*cmd
=
3367 (struct i40e_aqc_lldp_stop
*)&desc
.params
.raw
;
3370 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_stop
);
3373 cmd
->command
|= I40E_AQ_LLDP_AGENT_SHUTDOWN
;
3375 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3381 * i40e_aq_start_lldp
3382 * @hw: pointer to the hw struct
3383 * @cmd_details: pointer to command details structure or NULL
3385 * Start the embedded LLDP Agent on all ports.
3387 i40e_status
i40e_aq_start_lldp(struct i40e_hw
*hw
,
3388 struct i40e_asq_cmd_details
*cmd_details
)
3390 struct i40e_aq_desc desc
;
3391 struct i40e_aqc_lldp_start
*cmd
=
3392 (struct i40e_aqc_lldp_start
*)&desc
.params
.raw
;
3395 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_start
);
3397 cmd
->command
= I40E_AQ_LLDP_AGENT_START
;
3399 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3405 * i40e_aq_get_cee_dcb_config
3406 * @hw: pointer to the hw struct
3407 * @buff: response buffer that stores CEE operational configuration
3408 * @buff_size: size of the buffer passed
3409 * @cmd_details: pointer to command details structure or NULL
3411 * Get CEE DCBX mode operational configuration from firmware
3413 i40e_status
i40e_aq_get_cee_dcb_config(struct i40e_hw
*hw
,
3414 void *buff
, u16 buff_size
,
3415 struct i40e_asq_cmd_details
*cmd_details
)
3417 struct i40e_aq_desc desc
;
3420 if (buff_size
== 0 || !buff
)
3421 return I40E_ERR_PARAM
;
3423 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_cee_dcb_cfg
);
3425 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3426 status
= i40e_asq_send_command(hw
, &desc
, (void *)buff
, buff_size
,
3433 * i40e_aq_add_udp_tunnel
3434 * @hw: pointer to the hw struct
3435 * @udp_port: the UDP port to add
3436 * @header_len: length of the tunneling header length in DWords
3437 * @protocol_index: protocol index type
3438 * @filter_index: pointer to filter index
3439 * @cmd_details: pointer to command details structure or NULL
3441 i40e_status
i40e_aq_add_udp_tunnel(struct i40e_hw
*hw
,
3442 u16 udp_port
, u8 protocol_index
,
3444 struct i40e_asq_cmd_details
*cmd_details
)
3446 struct i40e_aq_desc desc
;
3447 struct i40e_aqc_add_udp_tunnel
*cmd
=
3448 (struct i40e_aqc_add_udp_tunnel
*)&desc
.params
.raw
;
3449 struct i40e_aqc_del_udp_tunnel_completion
*resp
=
3450 (struct i40e_aqc_del_udp_tunnel_completion
*)&desc
.params
.raw
;
3453 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_udp_tunnel
);
3455 cmd
->udp_port
= cpu_to_le16(udp_port
);
3456 cmd
->protocol_type
= protocol_index
;
3458 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3460 if (!status
&& filter_index
)
3461 *filter_index
= resp
->index
;
3467 * i40e_aq_del_udp_tunnel
3468 * @hw: pointer to the hw struct
3469 * @index: filter index
3470 * @cmd_details: pointer to command details structure or NULL
3472 i40e_status
i40e_aq_del_udp_tunnel(struct i40e_hw
*hw
, u8 index
,
3473 struct i40e_asq_cmd_details
*cmd_details
)
3475 struct i40e_aq_desc desc
;
3476 struct i40e_aqc_remove_udp_tunnel
*cmd
=
3477 (struct i40e_aqc_remove_udp_tunnel
*)&desc
.params
.raw
;
3480 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_del_udp_tunnel
);
3484 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3490 * i40e_aq_delete_element - Delete switch element
3491 * @hw: pointer to the hw struct
3492 * @seid: the SEID to delete from the switch
3493 * @cmd_details: pointer to command details structure or NULL
3495 * This deletes a switch element from the switch.
3497 i40e_status
i40e_aq_delete_element(struct i40e_hw
*hw
, u16 seid
,
3498 struct i40e_asq_cmd_details
*cmd_details
)
3500 struct i40e_aq_desc desc
;
3501 struct i40e_aqc_switch_seid
*cmd
=
3502 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
3506 return I40E_ERR_PARAM
;
3508 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_delete_element
);
3510 cmd
->seid
= cpu_to_le16(seid
);
3512 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3518 * i40e_aq_dcb_updated - DCB Updated Command
3519 * @hw: pointer to the hw struct
3520 * @cmd_details: pointer to command details structure or NULL
3522 * EMP will return when the shared RPB settings have been
3523 * recomputed and modified. The retval field in the descriptor
3524 * will be set to 0 when RPB is modified.
3526 i40e_status
i40e_aq_dcb_updated(struct i40e_hw
*hw
,
3527 struct i40e_asq_cmd_details
*cmd_details
)
3529 struct i40e_aq_desc desc
;
3532 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_dcb_updated
);
3534 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3540 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3541 * @hw: pointer to the hw struct
3542 * @seid: seid for the physical port/switching component/vsi
3543 * @buff: Indirect buffer to hold data parameters and response
3544 * @buff_size: Indirect buffer size
3545 * @opcode: Tx scheduler AQ command opcode
3546 * @cmd_details: pointer to command details structure or NULL
3548 * Generic command handler for Tx scheduler AQ commands
3550 static i40e_status
i40e_aq_tx_sched_cmd(struct i40e_hw
*hw
, u16 seid
,
3551 void *buff
, u16 buff_size
,
3552 enum i40e_admin_queue_opc opcode
,
3553 struct i40e_asq_cmd_details
*cmd_details
)
3555 struct i40e_aq_desc desc
;
3556 struct i40e_aqc_tx_sched_ind
*cmd
=
3557 (struct i40e_aqc_tx_sched_ind
*)&desc
.params
.raw
;
3559 bool cmd_param_flag
= false;
3562 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
:
3563 case i40e_aqc_opc_configure_vsi_tc_bw
:
3564 case i40e_aqc_opc_enable_switching_comp_ets
:
3565 case i40e_aqc_opc_modify_switching_comp_ets
:
3566 case i40e_aqc_opc_disable_switching_comp_ets
:
3567 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit
:
3568 case i40e_aqc_opc_configure_switching_comp_bw_config
:
3569 cmd_param_flag
= true;
3571 case i40e_aqc_opc_query_vsi_bw_config
:
3572 case i40e_aqc_opc_query_vsi_ets_sla_config
:
3573 case i40e_aqc_opc_query_switching_comp_ets_config
:
3574 case i40e_aqc_opc_query_port_ets_config
:
3575 case i40e_aqc_opc_query_switching_comp_bw_config
:
3576 cmd_param_flag
= false;
3579 return I40E_ERR_PARAM
;
3582 i40e_fill_default_direct_cmd_desc(&desc
, opcode
);
3584 /* Indirect command */
3585 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3587 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
3588 if (buff_size
> I40E_AQ_LARGE_BUF
)
3589 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3591 desc
.datalen
= cpu_to_le16(buff_size
);
3593 cmd
->vsi_seid
= cpu_to_le16(seid
);
3595 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3601 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3602 * @hw: pointer to the hw struct
3604 * @credit: BW limit credits (0 = disabled)
3605 * @max_credit: Max BW limit credits
3606 * @cmd_details: pointer to command details structure or NULL
3608 i40e_status
i40e_aq_config_vsi_bw_limit(struct i40e_hw
*hw
,
3609 u16 seid
, u16 credit
, u8 max_credit
,
3610 struct i40e_asq_cmd_details
*cmd_details
)
3612 struct i40e_aq_desc desc
;
3613 struct i40e_aqc_configure_vsi_bw_limit
*cmd
=
3614 (struct i40e_aqc_configure_vsi_bw_limit
*)&desc
.params
.raw
;
3617 i40e_fill_default_direct_cmd_desc(&desc
,
3618 i40e_aqc_opc_configure_vsi_bw_limit
);
3620 cmd
->vsi_seid
= cpu_to_le16(seid
);
3621 cmd
->credit
= cpu_to_le16(credit
);
3622 cmd
->max_credit
= max_credit
;
3624 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3630 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3631 * @hw: pointer to the hw struct
3633 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3634 * @cmd_details: pointer to command details structure or NULL
3636 i40e_status
i40e_aq_config_vsi_tc_bw(struct i40e_hw
*hw
,
3638 struct i40e_aqc_configure_vsi_tc_bw_data
*bw_data
,
3639 struct i40e_asq_cmd_details
*cmd_details
)
3641 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3642 i40e_aqc_opc_configure_vsi_tc_bw
,
3647 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3648 * @hw: pointer to the hw struct
3649 * @seid: seid of the switching component connected to Physical Port
3650 * @ets_data: Buffer holding ETS parameters
3651 * @cmd_details: pointer to command details structure or NULL
3653 i40e_status
i40e_aq_config_switch_comp_ets(struct i40e_hw
*hw
,
3655 struct i40e_aqc_configure_switching_comp_ets_data
*ets_data
,
3656 enum i40e_admin_queue_opc opcode
,
3657 struct i40e_asq_cmd_details
*cmd_details
)
3659 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)ets_data
,
3660 sizeof(*ets_data
), opcode
, cmd_details
);
3664 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3665 * @hw: pointer to the hw struct
3666 * @seid: seid of the switching component
3667 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3668 * @cmd_details: pointer to command details structure or NULL
3670 i40e_status
i40e_aq_config_switch_comp_bw_config(struct i40e_hw
*hw
,
3672 struct i40e_aqc_configure_switching_comp_bw_config_data
*bw_data
,
3673 struct i40e_asq_cmd_details
*cmd_details
)
3675 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3676 i40e_aqc_opc_configure_switching_comp_bw_config
,
3681 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3682 * @hw: pointer to the hw struct
3683 * @seid: seid of the VSI
3684 * @bw_data: Buffer to hold VSI BW configuration
3685 * @cmd_details: pointer to command details structure or NULL
3687 i40e_status
i40e_aq_query_vsi_bw_config(struct i40e_hw
*hw
,
3689 struct i40e_aqc_query_vsi_bw_config_resp
*bw_data
,
3690 struct i40e_asq_cmd_details
*cmd_details
)
3692 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3693 i40e_aqc_opc_query_vsi_bw_config
,
3698 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3699 * @hw: pointer to the hw struct
3700 * @seid: seid of the VSI
3701 * @bw_data: Buffer to hold VSI BW configuration per TC
3702 * @cmd_details: pointer to command details structure or NULL
3704 i40e_status
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw
*hw
,
3706 struct i40e_aqc_query_vsi_ets_sla_config_resp
*bw_data
,
3707 struct i40e_asq_cmd_details
*cmd_details
)
3709 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3710 i40e_aqc_opc_query_vsi_ets_sla_config
,
3715 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3716 * @hw: pointer to the hw struct
3717 * @seid: seid of the switching component
3718 * @bw_data: Buffer to hold switching component's per TC BW config
3719 * @cmd_details: pointer to command details structure or NULL
3721 i40e_status
i40e_aq_query_switch_comp_ets_config(struct i40e_hw
*hw
,
3723 struct i40e_aqc_query_switching_comp_ets_config_resp
*bw_data
,
3724 struct i40e_asq_cmd_details
*cmd_details
)
3726 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3727 i40e_aqc_opc_query_switching_comp_ets_config
,
3732 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3733 * @hw: pointer to the hw struct
3734 * @seid: seid of the VSI or switching component connected to Physical Port
3735 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3736 * @cmd_details: pointer to command details structure or NULL
3738 i40e_status
i40e_aq_query_port_ets_config(struct i40e_hw
*hw
,
3740 struct i40e_aqc_query_port_ets_config_resp
*bw_data
,
3741 struct i40e_asq_cmd_details
*cmd_details
)
3743 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3744 i40e_aqc_opc_query_port_ets_config
,
3749 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3750 * @hw: pointer to the hw struct
3751 * @seid: seid of the switching component
3752 * @bw_data: Buffer to hold switching component's BW configuration
3753 * @cmd_details: pointer to command details structure or NULL
3755 i40e_status
i40e_aq_query_switch_comp_bw_config(struct i40e_hw
*hw
,
3757 struct i40e_aqc_query_switching_comp_bw_config_resp
*bw_data
,
3758 struct i40e_asq_cmd_details
*cmd_details
)
3760 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3761 i40e_aqc_opc_query_switching_comp_bw_config
,
3766 * i40e_validate_filter_settings
3767 * @hw: pointer to the hardware structure
3768 * @settings: Filter control settings
3770 * Check and validate the filter control settings passed.
3771 * The function checks for the valid filter/context sizes being
3772 * passed for FCoE and PE.
3774 * Returns 0 if the values passed are valid and within
3775 * range else returns an error.
3777 static i40e_status
i40e_validate_filter_settings(struct i40e_hw
*hw
,
3778 struct i40e_filter_control_settings
*settings
)
3780 u32 fcoe_cntx_size
, fcoe_filt_size
;
3781 u32 pe_cntx_size
, pe_filt_size
;
3785 /* Validate FCoE settings passed */
3786 switch (settings
->fcoe_filt_num
) {
3787 case I40E_HASH_FILTER_SIZE_1K
:
3788 case I40E_HASH_FILTER_SIZE_2K
:
3789 case I40E_HASH_FILTER_SIZE_4K
:
3790 case I40E_HASH_FILTER_SIZE_8K
:
3791 case I40E_HASH_FILTER_SIZE_16K
:
3792 case I40E_HASH_FILTER_SIZE_32K
:
3793 fcoe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
3794 fcoe_filt_size
<<= (u32
)settings
->fcoe_filt_num
;
3797 return I40E_ERR_PARAM
;
3800 switch (settings
->fcoe_cntx_num
) {
3801 case I40E_DMA_CNTX_SIZE_512
:
3802 case I40E_DMA_CNTX_SIZE_1K
:
3803 case I40E_DMA_CNTX_SIZE_2K
:
3804 case I40E_DMA_CNTX_SIZE_4K
:
3805 fcoe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3806 fcoe_cntx_size
<<= (u32
)settings
->fcoe_cntx_num
;
3809 return I40E_ERR_PARAM
;
3812 /* Validate PE settings passed */
3813 switch (settings
->pe_filt_num
) {
3814 case I40E_HASH_FILTER_SIZE_1K
:
3815 case I40E_HASH_FILTER_SIZE_2K
:
3816 case I40E_HASH_FILTER_SIZE_4K
:
3817 case I40E_HASH_FILTER_SIZE_8K
:
3818 case I40E_HASH_FILTER_SIZE_16K
:
3819 case I40E_HASH_FILTER_SIZE_32K
:
3820 case I40E_HASH_FILTER_SIZE_64K
:
3821 case I40E_HASH_FILTER_SIZE_128K
:
3822 case I40E_HASH_FILTER_SIZE_256K
:
3823 case I40E_HASH_FILTER_SIZE_512K
:
3824 case I40E_HASH_FILTER_SIZE_1M
:
3825 pe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
3826 pe_filt_size
<<= (u32
)settings
->pe_filt_num
;
3829 return I40E_ERR_PARAM
;
3832 switch (settings
->pe_cntx_num
) {
3833 case I40E_DMA_CNTX_SIZE_512
:
3834 case I40E_DMA_CNTX_SIZE_1K
:
3835 case I40E_DMA_CNTX_SIZE_2K
:
3836 case I40E_DMA_CNTX_SIZE_4K
:
3837 case I40E_DMA_CNTX_SIZE_8K
:
3838 case I40E_DMA_CNTX_SIZE_16K
:
3839 case I40E_DMA_CNTX_SIZE_32K
:
3840 case I40E_DMA_CNTX_SIZE_64K
:
3841 case I40E_DMA_CNTX_SIZE_128K
:
3842 case I40E_DMA_CNTX_SIZE_256K
:
3843 pe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3844 pe_cntx_size
<<= (u32
)settings
->pe_cntx_num
;
3847 return I40E_ERR_PARAM
;
3850 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3851 val
= rd32(hw
, I40E_GLHMC_FCOEFMAX
);
3852 fcoe_fmax
= (val
& I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK
)
3853 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT
;
3854 if (fcoe_filt_size
+ fcoe_cntx_size
> fcoe_fmax
)
3855 return I40E_ERR_INVALID_SIZE
;
3861 * i40e_set_filter_control
3862 * @hw: pointer to the hardware structure
3863 * @settings: Filter control settings
3865 * Set the Queue Filters for PE/FCoE and enable filters required
3866 * for a single PF. It is expected that these settings are programmed
3867 * at the driver initialization time.
3869 i40e_status
i40e_set_filter_control(struct i40e_hw
*hw
,
3870 struct i40e_filter_control_settings
*settings
)
3872 i40e_status ret
= 0;
3873 u32 hash_lut_size
= 0;
3877 return I40E_ERR_PARAM
;
3879 /* Validate the input settings */
3880 ret
= i40e_validate_filter_settings(hw
, settings
);
3884 /* Read the PF Queue Filter control register */
3885 val
= i40e_read_rx_ctl(hw
, I40E_PFQF_CTL_0
);
3887 /* Program required PE hash buckets for the PF */
3888 val
&= ~I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3889 val
|= ((u32
)settings
->pe_filt_num
<< I40E_PFQF_CTL_0_PEHSIZE_SHIFT
) &
3890 I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3891 /* Program required PE contexts for the PF */
3892 val
&= ~I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3893 val
|= ((u32
)settings
->pe_cntx_num
<< I40E_PFQF_CTL_0_PEDSIZE_SHIFT
) &
3894 I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3896 /* Program required FCoE hash buckets for the PF */
3897 val
&= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3898 val
|= ((u32
)settings
->fcoe_filt_num
<<
3899 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT
) &
3900 I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3901 /* Program required FCoE DDP contexts for the PF */
3902 val
&= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3903 val
|= ((u32
)settings
->fcoe_cntx_num
<<
3904 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT
) &
3905 I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3907 /* Program Hash LUT size for the PF */
3908 val
&= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3909 if (settings
->hash_lut_size
== I40E_HASH_LUT_SIZE_512
)
3911 val
|= (hash_lut_size
<< I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT
) &
3912 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3914 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3915 if (settings
->enable_fdir
)
3916 val
|= I40E_PFQF_CTL_0_FD_ENA_MASK
;
3917 if (settings
->enable_ethtype
)
3918 val
|= I40E_PFQF_CTL_0_ETYPE_ENA_MASK
;
3919 if (settings
->enable_macvlan
)
3920 val
|= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK
;
3922 i40e_write_rx_ctl(hw
, I40E_PFQF_CTL_0
, val
);
3928 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3929 * @hw: pointer to the hw struct
3930 * @mac_addr: MAC address to use in the filter
3931 * @ethtype: Ethertype to use in the filter
3932 * @flags: Flags that needs to be applied to the filter
3933 * @vsi_seid: seid of the control VSI
3934 * @queue: VSI queue number to send the packet to
3935 * @is_add: Add control packet filter if True else remove
3936 * @stats: Structure to hold information on control filter counts
3937 * @cmd_details: pointer to command details structure or NULL
3939 * This command will Add or Remove control packet filter for a control VSI.
3940 * In return it will update the total number of perfect filter count in
3943 i40e_status
i40e_aq_add_rem_control_packet_filter(struct i40e_hw
*hw
,
3944 u8
*mac_addr
, u16 ethtype
, u16 flags
,
3945 u16 vsi_seid
, u16 queue
, bool is_add
,
3946 struct i40e_control_filter_stats
*stats
,
3947 struct i40e_asq_cmd_details
*cmd_details
)
3949 struct i40e_aq_desc desc
;
3950 struct i40e_aqc_add_remove_control_packet_filter
*cmd
=
3951 (struct i40e_aqc_add_remove_control_packet_filter
*)
3953 struct i40e_aqc_add_remove_control_packet_filter_completion
*resp
=
3954 (struct i40e_aqc_add_remove_control_packet_filter_completion
*)
3959 return I40E_ERR_PARAM
;
3962 i40e_fill_default_direct_cmd_desc(&desc
,
3963 i40e_aqc_opc_add_control_packet_filter
);
3964 cmd
->queue
= cpu_to_le16(queue
);
3966 i40e_fill_default_direct_cmd_desc(&desc
,
3967 i40e_aqc_opc_remove_control_packet_filter
);
3971 ether_addr_copy(cmd
->mac
, mac_addr
);
3973 cmd
->etype
= cpu_to_le16(ethtype
);
3974 cmd
->flags
= cpu_to_le16(flags
);
3975 cmd
->seid
= cpu_to_le16(vsi_seid
);
3977 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3979 if (!status
&& stats
) {
3980 stats
->mac_etype_used
= le16_to_cpu(resp
->mac_etype_used
);
3981 stats
->etype_used
= le16_to_cpu(resp
->etype_used
);
3982 stats
->mac_etype_free
= le16_to_cpu(resp
->mac_etype_free
);
3983 stats
->etype_free
= le16_to_cpu(resp
->etype_free
);
3990 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3991 * @hw: pointer to the hw struct
3992 * @seid: VSI seid to add ethertype filter from
3994 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3995 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw
*hw
,
3998 u16 flag
= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC
|
3999 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP
|
4000 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX
;
4001 u16 ethtype
= I40E_FLOW_CONTROL_ETHTYPE
;
4004 status
= i40e_aq_add_rem_control_packet_filter(hw
, NULL
, ethtype
, flag
,
4005 seid
, 0, true, NULL
,
4008 hw_dbg(hw
, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4012 * i40e_aq_alternate_read
4013 * @hw: pointer to the hardware structure
4014 * @reg_addr0: address of first dword to be read
4015 * @reg_val0: pointer for data read from 'reg_addr0'
4016 * @reg_addr1: address of second dword to be read
4017 * @reg_val1: pointer for data read from 'reg_addr1'
4019 * Read one or two dwords from alternate structure. Fields are indicated
4020 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4021 * is not passed then only register at 'reg_addr0' is read.
4024 static i40e_status
i40e_aq_alternate_read(struct i40e_hw
*hw
,
4025 u32 reg_addr0
, u32
*reg_val0
,
4026 u32 reg_addr1
, u32
*reg_val1
)
4028 struct i40e_aq_desc desc
;
4029 struct i40e_aqc_alternate_write
*cmd_resp
=
4030 (struct i40e_aqc_alternate_write
*)&desc
.params
.raw
;
4034 return I40E_ERR_PARAM
;
4036 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_alternate_read
);
4037 cmd_resp
->address0
= cpu_to_le32(reg_addr0
);
4038 cmd_resp
->address1
= cpu_to_le32(reg_addr1
);
4040 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
4043 *reg_val0
= le32_to_cpu(cmd_resp
->data0
);
4046 *reg_val1
= le32_to_cpu(cmd_resp
->data1
);
4053 * i40e_aq_resume_port_tx
4054 * @hw: pointer to the hardware structure
4055 * @cmd_details: pointer to command details structure or NULL
4057 * Resume port's Tx traffic
4059 i40e_status
i40e_aq_resume_port_tx(struct i40e_hw
*hw
,
4060 struct i40e_asq_cmd_details
*cmd_details
)
4062 struct i40e_aq_desc desc
;
4065 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_resume_port_tx
);
4067 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
4073 * i40e_set_pci_config_data - store PCI bus info
4074 * @hw: pointer to hardware structure
4075 * @link_status: the link status word from PCI config space
4077 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4079 void i40e_set_pci_config_data(struct i40e_hw
*hw
, u16 link_status
)
4081 hw
->bus
.type
= i40e_bus_type_pci_express
;
4083 switch (link_status
& PCI_EXP_LNKSTA_NLW
) {
4084 case PCI_EXP_LNKSTA_NLW_X1
:
4085 hw
->bus
.width
= i40e_bus_width_pcie_x1
;
4087 case PCI_EXP_LNKSTA_NLW_X2
:
4088 hw
->bus
.width
= i40e_bus_width_pcie_x2
;
4090 case PCI_EXP_LNKSTA_NLW_X4
:
4091 hw
->bus
.width
= i40e_bus_width_pcie_x4
;
4093 case PCI_EXP_LNKSTA_NLW_X8
:
4094 hw
->bus
.width
= i40e_bus_width_pcie_x8
;
4097 hw
->bus
.width
= i40e_bus_width_unknown
;
4101 switch (link_status
& PCI_EXP_LNKSTA_CLS
) {
4102 case PCI_EXP_LNKSTA_CLS_2_5GB
:
4103 hw
->bus
.speed
= i40e_bus_speed_2500
;
4105 case PCI_EXP_LNKSTA_CLS_5_0GB
:
4106 hw
->bus
.speed
= i40e_bus_speed_5000
;
4108 case PCI_EXP_LNKSTA_CLS_8_0GB
:
4109 hw
->bus
.speed
= i40e_bus_speed_8000
;
4112 hw
->bus
.speed
= i40e_bus_speed_unknown
;
4118 * i40e_aq_debug_dump
4119 * @hw: pointer to the hardware structure
4120 * @cluster_id: specific cluster to dump
4121 * @table_id: table id within cluster
4122 * @start_index: index of line in the block to read
4123 * @buff_size: dump buffer size
4124 * @buff: dump buffer
4125 * @ret_buff_size: actual buffer size returned
4126 * @ret_next_table: next block to read
4127 * @ret_next_index: next index to read
4129 * Dump internal FW/HW data for debug purposes.
4132 i40e_status
i40e_aq_debug_dump(struct i40e_hw
*hw
, u8 cluster_id
,
4133 u8 table_id
, u32 start_index
, u16 buff_size
,
4134 void *buff
, u16
*ret_buff_size
,
4135 u8
*ret_next_table
, u32
*ret_next_index
,
4136 struct i40e_asq_cmd_details
*cmd_details
)
4138 struct i40e_aq_desc desc
;
4139 struct i40e_aqc_debug_dump_internals
*cmd
=
4140 (struct i40e_aqc_debug_dump_internals
*)&desc
.params
.raw
;
4141 struct i40e_aqc_debug_dump_internals
*resp
=
4142 (struct i40e_aqc_debug_dump_internals
*)&desc
.params
.raw
;
4145 if (buff_size
== 0 || !buff
)
4146 return I40E_ERR_PARAM
;
4148 i40e_fill_default_direct_cmd_desc(&desc
,
4149 i40e_aqc_opc_debug_dump_internals
);
4150 /* Indirect Command */
4151 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
4152 if (buff_size
> I40E_AQ_LARGE_BUF
)
4153 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
4155 cmd
->cluster_id
= cluster_id
;
4156 cmd
->table_id
= table_id
;
4157 cmd
->idx
= cpu_to_le32(start_index
);
4159 desc
.datalen
= cpu_to_le16(buff_size
);
4161 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
4164 *ret_buff_size
= le16_to_cpu(desc
.datalen
);
4166 *ret_next_table
= resp
->table_id
;
4168 *ret_next_index
= le32_to_cpu(resp
->idx
);
4175 * i40e_read_bw_from_alt_ram
4176 * @hw: pointer to the hardware structure
4177 * @max_bw: pointer for max_bw read
4178 * @min_bw: pointer for min_bw read
4179 * @min_valid: pointer for bool that is true if min_bw is a valid value
4180 * @max_valid: pointer for bool that is true if max_bw is a valid value
4182 * Read bw from the alternate ram for the given pf
4184 i40e_status
i40e_read_bw_from_alt_ram(struct i40e_hw
*hw
,
4185 u32
*max_bw
, u32
*min_bw
,
4186 bool *min_valid
, bool *max_valid
)
4189 u32 max_bw_addr
, min_bw_addr
;
4191 /* Calculate the address of the min/max bw registers */
4192 max_bw_addr
= I40E_ALT_STRUCT_FIRST_PF_OFFSET
+
4193 I40E_ALT_STRUCT_MAX_BW_OFFSET
+
4194 (I40E_ALT_STRUCT_DWORDS_PER_PF
* hw
->pf_id
);
4195 min_bw_addr
= I40E_ALT_STRUCT_FIRST_PF_OFFSET
+
4196 I40E_ALT_STRUCT_MIN_BW_OFFSET
+
4197 (I40E_ALT_STRUCT_DWORDS_PER_PF
* hw
->pf_id
);
4199 /* Read the bandwidths from alt ram */
4200 status
= i40e_aq_alternate_read(hw
, max_bw_addr
, max_bw
,
4201 min_bw_addr
, min_bw
);
4203 if (*min_bw
& I40E_ALT_BW_VALID_MASK
)
4208 if (*max_bw
& I40E_ALT_BW_VALID_MASK
)
4217 * i40e_aq_configure_partition_bw
4218 * @hw: pointer to the hardware structure
4219 * @bw_data: Buffer holding valid pfs and bw limits
4220 * @cmd_details: pointer to command details
4222 * Configure partitions guaranteed/max bw
4224 i40e_status
i40e_aq_configure_partition_bw(struct i40e_hw
*hw
,
4225 struct i40e_aqc_configure_partition_bw_data
*bw_data
,
4226 struct i40e_asq_cmd_details
*cmd_details
)
4229 struct i40e_aq_desc desc
;
4230 u16 bwd_size
= sizeof(*bw_data
);
4232 i40e_fill_default_direct_cmd_desc(&desc
,
4233 i40e_aqc_opc_configure_partition_bw
);
4235 /* Indirect command */
4236 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
4237 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
4239 if (bwd_size
> I40E_AQ_LARGE_BUF
)
4240 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
4242 desc
.datalen
= cpu_to_le16(bwd_size
);
4244 status
= i40e_asq_send_command(hw
, &desc
, bw_data
, bwd_size
,
4251 * i40e_read_phy_register
4252 * @hw: pointer to the HW structure
4253 * @page: registers page number
4254 * @reg: register address in the page
4255 * @phy_adr: PHY address on MDIO interface
4256 * @value: PHY register value
4258 * Reads specified PHY register value
4260 i40e_status
i40e_read_phy_register(struct i40e_hw
*hw
,
4261 u8 page
, u16 reg
, u8 phy_addr
,
4264 i40e_status status
= I40E_ERR_TIMEOUT
;
4267 u8 port_num
= hw
->func_caps
.mdio_port_num
;
4269 command
= (reg
<< I40E_GLGEN_MSCA_MDIADD_SHIFT
) |
4270 (page
<< I40E_GLGEN_MSCA_DEVADD_SHIFT
) |
4271 (phy_addr
<< I40E_GLGEN_MSCA_PHYADD_SHIFT
) |
4272 (I40E_MDIO_OPCODE_ADDRESS
) |
4273 (I40E_MDIO_STCODE
) |
4274 (I40E_GLGEN_MSCA_MDICMD_MASK
) |
4275 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK
);
4276 wr32(hw
, I40E_GLGEN_MSCA(port_num
), command
);
4278 command
= rd32(hw
, I40E_GLGEN_MSCA(port_num
));
4279 if (!(command
& I40E_GLGEN_MSCA_MDICMD_MASK
)) {
4283 usleep_range(10, 20);
4288 i40e_debug(hw
, I40E_DEBUG_PHY
,
4289 "PHY: Can't write command to external PHY.\n");
4293 command
= (page
<< I40E_GLGEN_MSCA_DEVADD_SHIFT
) |
4294 (phy_addr
<< I40E_GLGEN_MSCA_PHYADD_SHIFT
) |
4295 (I40E_MDIO_OPCODE_READ
) |
4296 (I40E_MDIO_STCODE
) |
4297 (I40E_GLGEN_MSCA_MDICMD_MASK
) |
4298 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK
);
4299 status
= I40E_ERR_TIMEOUT
;
4301 wr32(hw
, I40E_GLGEN_MSCA(port_num
), command
);
4303 command
= rd32(hw
, I40E_GLGEN_MSCA(port_num
));
4304 if (!(command
& I40E_GLGEN_MSCA_MDICMD_MASK
)) {
4308 usleep_range(10, 20);
4313 command
= rd32(hw
, I40E_GLGEN_MSRWD(port_num
));
4314 *value
= (command
& I40E_GLGEN_MSRWD_MDIRDDATA_MASK
) >>
4315 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT
;
4317 i40e_debug(hw
, I40E_DEBUG_PHY
,
4318 "PHY: Can't read register value from external PHY.\n");
4326 * i40e_write_phy_register
4327 * @hw: pointer to the HW structure
4328 * @page: registers page number
4329 * @reg: register address in the page
4330 * @phy_adr: PHY address on MDIO interface
4331 * @value: PHY register value
4333 * Writes value to specified PHY register
4335 i40e_status
i40e_write_phy_register(struct i40e_hw
*hw
,
4336 u8 page
, u16 reg
, u8 phy_addr
,
4339 i40e_status status
= I40E_ERR_TIMEOUT
;
4342 u8 port_num
= hw
->func_caps
.mdio_port_num
;
4344 command
= (reg
<< I40E_GLGEN_MSCA_MDIADD_SHIFT
) |
4345 (page
<< I40E_GLGEN_MSCA_DEVADD_SHIFT
) |
4346 (phy_addr
<< I40E_GLGEN_MSCA_PHYADD_SHIFT
) |
4347 (I40E_MDIO_OPCODE_ADDRESS
) |
4348 (I40E_MDIO_STCODE
) |
4349 (I40E_GLGEN_MSCA_MDICMD_MASK
) |
4350 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK
);
4351 wr32(hw
, I40E_GLGEN_MSCA(port_num
), command
);
4353 command
= rd32(hw
, I40E_GLGEN_MSCA(port_num
));
4354 if (!(command
& I40E_GLGEN_MSCA_MDICMD_MASK
)) {
4358 usleep_range(10, 20);
4362 i40e_debug(hw
, I40E_DEBUG_PHY
,
4363 "PHY: Can't write command to external PHY.\n");
4367 command
= value
<< I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT
;
4368 wr32(hw
, I40E_GLGEN_MSRWD(port_num
), command
);
4370 command
= (page
<< I40E_GLGEN_MSCA_DEVADD_SHIFT
) |
4371 (phy_addr
<< I40E_GLGEN_MSCA_PHYADD_SHIFT
) |
4372 (I40E_MDIO_OPCODE_WRITE
) |
4373 (I40E_MDIO_STCODE
) |
4374 (I40E_GLGEN_MSCA_MDICMD_MASK
) |
4375 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK
);
4376 status
= I40E_ERR_TIMEOUT
;
4378 wr32(hw
, I40E_GLGEN_MSCA(port_num
), command
);
4380 command
= rd32(hw
, I40E_GLGEN_MSCA(port_num
));
4381 if (!(command
& I40E_GLGEN_MSCA_MDICMD_MASK
)) {
4385 usleep_range(10, 20);
4394 * i40e_get_phy_address
4395 * @hw: pointer to the HW structure
4396 * @dev_num: PHY port num that address we want
4397 * @phy_addr: Returned PHY address
4399 * Gets PHY address for current port
4401 u8
i40e_get_phy_address(struct i40e_hw
*hw
, u8 dev_num
)
4403 u8 port_num
= hw
->func_caps
.mdio_port_num
;
4404 u32 reg_val
= rd32(hw
, I40E_GLGEN_MDIO_I2C_SEL(port_num
));
4406 return (u8
)(reg_val
>> ((dev_num
+ 1) * 5)) & 0x1f;
4410 * i40e_blink_phy_led
4411 * @hw: pointer to the HW structure
4412 * @time: time how long led will blinks in secs
4413 * @interval: gap between LED on and off in msecs
4415 * Blinks PHY link LED
4417 i40e_status
i40e_blink_phy_link_led(struct i40e_hw
*hw
,
4418 u32 time
, u32 interval
)
4420 i40e_status status
= 0;
4425 u16 led_addr
= I40E_PHY_LED_PROV_REG_1
;
4429 i
= rd32(hw
, I40E_PFGEN_PORTNUM
);
4430 port_num
= (u8
)(i
& I40E_PFGEN_PORTNUM_PORT_NUM_MASK
);
4431 phy_addr
= i40e_get_phy_address(hw
, port_num
);
4433 for (gpio_led_port
= 0; gpio_led_port
< 3; gpio_led_port
++,
4435 status
= i40e_read_phy_register(hw
, I40E_PHY_COM_REG_PAGE
,
4436 led_addr
, phy_addr
, &led_reg
);
4438 goto phy_blinking_end
;
4440 if (led_reg
& I40E_PHY_LED_LINK_MODE_MASK
) {
4442 status
= i40e_write_phy_register(hw
,
4443 I40E_PHY_COM_REG_PAGE
,
4447 goto phy_blinking_end
;
4452 if (time
> 0 && interval
> 0) {
4453 for (i
= 0; i
< time
* 1000; i
+= interval
) {
4454 status
= i40e_read_phy_register(hw
,
4455 I40E_PHY_COM_REG_PAGE
,
4459 goto restore_config
;
4460 if (led_reg
& I40E_PHY_LED_MANUAL_ON
)
4463 led_reg
= I40E_PHY_LED_MANUAL_ON
;
4464 status
= i40e_write_phy_register(hw
,
4465 I40E_PHY_COM_REG_PAGE
,
4469 goto restore_config
;
4475 status
= i40e_write_phy_register(hw
, I40E_PHY_COM_REG_PAGE
, led_addr
,
4483 * i40e_led_get_phy - return current on/off mode
4484 * @hw: pointer to the hw struct
4485 * @led_addr: address of led register to use
4486 * @val: original value of register to use
4489 i40e_status
i40e_led_get_phy(struct i40e_hw
*hw
, u16
*led_addr
,
4492 i40e_status status
= 0;
4500 temp_addr
= I40E_PHY_LED_PROV_REG_1
;
4501 i
= rd32(hw
, I40E_PFGEN_PORTNUM
);
4502 port_num
= (u8
)(i
& I40E_PFGEN_PORTNUM_PORT_NUM_MASK
);
4503 phy_addr
= i40e_get_phy_address(hw
, port_num
);
4505 for (gpio_led_port
= 0; gpio_led_port
< 3; gpio_led_port
++,
4507 status
= i40e_read_phy_register(hw
, I40E_PHY_COM_REG_PAGE
,
4508 temp_addr
, phy_addr
, ®_val
);
4512 if (reg_val
& I40E_PHY_LED_LINK_MODE_MASK
) {
4513 *led_addr
= temp_addr
;
4522 * @hw: pointer to the HW structure
4523 * @on: true or false
4524 * @mode: original val plus bit for set or ignore
4525 * Set led's on or off when controlled by the PHY
4528 i40e_status
i40e_led_set_phy(struct i40e_hw
*hw
, bool on
,
4529 u16 led_addr
, u32 mode
)
4531 i40e_status status
= 0;
4538 i
= rd32(hw
, I40E_PFGEN_PORTNUM
);
4539 port_num
= (u8
)(i
& I40E_PFGEN_PORTNUM_PORT_NUM_MASK
);
4540 phy_addr
= i40e_get_phy_address(hw
, port_num
);
4542 status
= i40e_read_phy_register(hw
, I40E_PHY_COM_REG_PAGE
, led_addr
,
4543 phy_addr
, &led_reg
);
4547 if (led_reg
& I40E_PHY_LED_LINK_MODE_MASK
) {
4549 status
= i40e_write_phy_register(hw
, I40E_PHY_COM_REG_PAGE
,
4550 led_addr
, phy_addr
, led_reg
);
4554 status
= i40e_read_phy_register(hw
, I40E_PHY_COM_REG_PAGE
,
4555 led_addr
, phy_addr
, &led_reg
);
4557 goto restore_config
;
4559 led_reg
= I40E_PHY_LED_MANUAL_ON
;
4562 status
= i40e_write_phy_register(hw
, I40E_PHY_COM_REG_PAGE
,
4563 led_addr
, phy_addr
, led_reg
);
4565 goto restore_config
;
4566 if (mode
& I40E_PHY_LED_MODE_ORIG
) {
4567 led_ctl
= (mode
& I40E_PHY_LED_MODE_MASK
);
4568 status
= i40e_write_phy_register(hw
,
4569 I40E_PHY_COM_REG_PAGE
,
4570 led_addr
, phy_addr
, led_ctl
);
4574 status
= i40e_write_phy_register(hw
, I40E_PHY_COM_REG_PAGE
, led_addr
,
4580 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4581 * @hw: pointer to the hw struct
4582 * @reg_addr: register address
4583 * @reg_val: ptr to register value
4584 * @cmd_details: pointer to command details structure or NULL
4586 * Use the firmware to read the Rx control register,
4587 * especially useful if the Rx unit is under heavy pressure
4589 i40e_status
i40e_aq_rx_ctl_read_register(struct i40e_hw
*hw
,
4590 u32 reg_addr
, u32
*reg_val
,
4591 struct i40e_asq_cmd_details
*cmd_details
)
4593 struct i40e_aq_desc desc
;
4594 struct i40e_aqc_rx_ctl_reg_read_write
*cmd_resp
=
4595 (struct i40e_aqc_rx_ctl_reg_read_write
*)&desc
.params
.raw
;
4599 return I40E_ERR_PARAM
;
4601 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_rx_ctl_reg_read
);
4603 cmd_resp
->address
= cpu_to_le32(reg_addr
);
4605 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
4608 *reg_val
= le32_to_cpu(cmd_resp
->value
);
4614 * i40e_read_rx_ctl - read from an Rx control register
4615 * @hw: pointer to the hw struct
4616 * @reg_addr: register address
4618 u32
i40e_read_rx_ctl(struct i40e_hw
*hw
, u32 reg_addr
)
4620 i40e_status status
= 0;
4625 use_register
= (hw
->aq
.api_maj_ver
== 1) && (hw
->aq
.api_min_ver
< 5);
4626 if (!use_register
) {
4628 status
= i40e_aq_rx_ctl_read_register(hw
, reg_addr
, &val
, NULL
);
4629 if (hw
->aq
.asq_last_status
== I40E_AQ_RC_EAGAIN
&& retry
) {
4630 usleep_range(1000, 2000);
4636 /* if the AQ access failed, try the old-fashioned way */
4637 if (status
|| use_register
)
4638 val
= rd32(hw
, reg_addr
);
4644 * i40e_aq_rx_ctl_write_register
4645 * @hw: pointer to the hw struct
4646 * @reg_addr: register address
4647 * @reg_val: register value
4648 * @cmd_details: pointer to command details structure or NULL
4650 * Use the firmware to write to an Rx control register,
4651 * especially useful if the Rx unit is under heavy pressure
4653 i40e_status
i40e_aq_rx_ctl_write_register(struct i40e_hw
*hw
,
4654 u32 reg_addr
, u32 reg_val
,
4655 struct i40e_asq_cmd_details
*cmd_details
)
4657 struct i40e_aq_desc desc
;
4658 struct i40e_aqc_rx_ctl_reg_read_write
*cmd
=
4659 (struct i40e_aqc_rx_ctl_reg_read_write
*)&desc
.params
.raw
;
4662 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_rx_ctl_reg_write
);
4664 cmd
->address
= cpu_to_le32(reg_addr
);
4665 cmd
->value
= cpu_to_le32(reg_val
);
4667 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
4673 * i40e_write_rx_ctl - write to an Rx control register
4674 * @hw: pointer to the hw struct
4675 * @reg_addr: register address
4676 * @reg_val: register value
4678 void i40e_write_rx_ctl(struct i40e_hw
*hw
, u32 reg_addr
, u32 reg_val
)
4680 i40e_status status
= 0;
4684 use_register
= (hw
->aq
.api_maj_ver
== 1) && (hw
->aq
.api_min_ver
< 5);
4685 if (!use_register
) {
4687 status
= i40e_aq_rx_ctl_write_register(hw
, reg_addr
,
4689 if (hw
->aq
.asq_last_status
== I40E_AQ_RC_EAGAIN
&& retry
) {
4690 usleep_range(1000, 2000);
4696 /* if the AQ access failed, try the old-fashioned way */
4697 if (status
|| use_register
)
4698 wr32(hw
, reg_addr
, reg_val
);