]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/net/ethernet/intel/i40e/i40e_common.c
projects / mirror_ubuntu-hirsute-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
52 case I40E_DEV_ID_10G_BASE_T:
53 case I40E_DEV_ID_10G_BASE_T4:
54 case I40E_DEV_ID_20G_KR2:
55 case I40E_DEV_ID_20G_KR2_A:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
63 case I40E_DEV_ID_SFP_I_X722:
64 hw->mac.type = I40E_MAC_X722;
65 break;
66 default:
67 hw->mac.type = I40E_MAC_GENERIC;
68 break;
69 }
70 } else {
71 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
72 }
73
74 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
75 hw->mac.type, status);
76 return status;
77 }
78
79 /**
80 * i40e_aq_str - convert AQ err code to a string
81 * @hw: pointer to the HW structure
82 * @aq_err: the AQ error code to convert
83 **/
84 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
85 {
86 switch (aq_err) {
87 case I40E_AQ_RC_OK:
88 return "OK";
89 case I40E_AQ_RC_EPERM:
90 return "I40E_AQ_RC_EPERM";
91 case I40E_AQ_RC_ENOENT:
92 return "I40E_AQ_RC_ENOENT";
93 case I40E_AQ_RC_ESRCH:
94 return "I40E_AQ_RC_ESRCH";
95 case I40E_AQ_RC_EINTR:
96 return "I40E_AQ_RC_EINTR";
97 case I40E_AQ_RC_EIO:
98 return "I40E_AQ_RC_EIO";
99 case I40E_AQ_RC_ENXIO:
100 return "I40E_AQ_RC_ENXIO";
101 case I40E_AQ_RC_E2BIG:
102 return "I40E_AQ_RC_E2BIG";
103 case I40E_AQ_RC_EAGAIN:
104 return "I40E_AQ_RC_EAGAIN";
105 case I40E_AQ_RC_ENOMEM:
106 return "I40E_AQ_RC_ENOMEM";
107 case I40E_AQ_RC_EACCES:
108 return "I40E_AQ_RC_EACCES";
109 case I40E_AQ_RC_EFAULT:
110 return "I40E_AQ_RC_EFAULT";
111 case I40E_AQ_RC_EBUSY:
112 return "I40E_AQ_RC_EBUSY";
113 case I40E_AQ_RC_EEXIST:
114 return "I40E_AQ_RC_EEXIST";
115 case I40E_AQ_RC_EINVAL:
116 return "I40E_AQ_RC_EINVAL";
117 case I40E_AQ_RC_ENOTTY:
118 return "I40E_AQ_RC_ENOTTY";
119 case I40E_AQ_RC_ENOSPC:
120 return "I40E_AQ_RC_ENOSPC";
121 case I40E_AQ_RC_ENOSYS:
122 return "I40E_AQ_RC_ENOSYS";
123 case I40E_AQ_RC_ERANGE:
124 return "I40E_AQ_RC_ERANGE";
125 case I40E_AQ_RC_EFLUSHED:
126 return "I40E_AQ_RC_EFLUSHED";
127 case I40E_AQ_RC_BAD_ADDR:
128 return "I40E_AQ_RC_BAD_ADDR";
129 case I40E_AQ_RC_EMODE:
130 return "I40E_AQ_RC_EMODE";
131 case I40E_AQ_RC_EFBIG:
132 return "I40E_AQ_RC_EFBIG";
133 }
134
135 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
136 return hw->err_str;
137 }
138
139 /**
140 * i40e_stat_str - convert status err code to a string
141 * @hw: pointer to the HW structure
142 * @stat_err: the status error code to convert
143 **/
144 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
145 {
146 switch (stat_err) {
147 case 0:
148 return "OK";
149 case I40E_ERR_NVM:
150 return "I40E_ERR_NVM";
151 case I40E_ERR_NVM_CHECKSUM:
152 return "I40E_ERR_NVM_CHECKSUM";
153 case I40E_ERR_PHY:
154 return "I40E_ERR_PHY";
155 case I40E_ERR_CONFIG:
156 return "I40E_ERR_CONFIG";
157 case I40E_ERR_PARAM:
158 return "I40E_ERR_PARAM";
159 case I40E_ERR_MAC_TYPE:
160 return "I40E_ERR_MAC_TYPE";
161 case I40E_ERR_UNKNOWN_PHY:
162 return "I40E_ERR_UNKNOWN_PHY";
163 case I40E_ERR_LINK_SETUP:
164 return "I40E_ERR_LINK_SETUP";
165 case I40E_ERR_ADAPTER_STOPPED:
166 return "I40E_ERR_ADAPTER_STOPPED";
167 case I40E_ERR_INVALID_MAC_ADDR:
168 return "I40E_ERR_INVALID_MAC_ADDR";
169 case I40E_ERR_DEVICE_NOT_SUPPORTED:
170 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
171 case I40E_ERR_MASTER_REQUESTS_PENDING:
172 return "I40E_ERR_MASTER_REQUESTS_PENDING";
173 case I40E_ERR_INVALID_LINK_SETTINGS:
174 return "I40E_ERR_INVALID_LINK_SETTINGS";
175 case I40E_ERR_AUTONEG_NOT_COMPLETE:
176 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
177 case I40E_ERR_RESET_FAILED:
178 return "I40E_ERR_RESET_FAILED";
179 case I40E_ERR_SWFW_SYNC:
180 return "I40E_ERR_SWFW_SYNC";
181 case I40E_ERR_NO_AVAILABLE_VSI:
182 return "I40E_ERR_NO_AVAILABLE_VSI";
183 case I40E_ERR_NO_MEMORY:
184 return "I40E_ERR_NO_MEMORY";
185 case I40E_ERR_BAD_PTR:
186 return "I40E_ERR_BAD_PTR";
187 case I40E_ERR_RING_FULL:
188 return "I40E_ERR_RING_FULL";
189 case I40E_ERR_INVALID_PD_ID:
190 return "I40E_ERR_INVALID_PD_ID";
191 case I40E_ERR_INVALID_QP_ID:
192 return "I40E_ERR_INVALID_QP_ID";
193 case I40E_ERR_INVALID_CQ_ID:
194 return "I40E_ERR_INVALID_CQ_ID";
195 case I40E_ERR_INVALID_CEQ_ID:
196 return "I40E_ERR_INVALID_CEQ_ID";
197 case I40E_ERR_INVALID_AEQ_ID:
198 return "I40E_ERR_INVALID_AEQ_ID";
199 case I40E_ERR_INVALID_SIZE:
200 return "I40E_ERR_INVALID_SIZE";
201 case I40E_ERR_INVALID_ARP_INDEX:
202 return "I40E_ERR_INVALID_ARP_INDEX";
203 case I40E_ERR_INVALID_FPM_FUNC_ID:
204 return "I40E_ERR_INVALID_FPM_FUNC_ID";
205 case I40E_ERR_QP_INVALID_MSG_SIZE:
206 return "I40E_ERR_QP_INVALID_MSG_SIZE";
207 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
208 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
209 case I40E_ERR_INVALID_FRAG_COUNT:
210 return "I40E_ERR_INVALID_FRAG_COUNT";
211 case I40E_ERR_QUEUE_EMPTY:
212 return "I40E_ERR_QUEUE_EMPTY";
213 case I40E_ERR_INVALID_ALIGNMENT:
214 return "I40E_ERR_INVALID_ALIGNMENT";
215 case I40E_ERR_FLUSHED_QUEUE:
216 return "I40E_ERR_FLUSHED_QUEUE";
217 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
218 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
219 case I40E_ERR_INVALID_IMM_DATA_SIZE:
220 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
221 case I40E_ERR_TIMEOUT:
222 return "I40E_ERR_TIMEOUT";
223 case I40E_ERR_OPCODE_MISMATCH:
224 return "I40E_ERR_OPCODE_MISMATCH";
225 case I40E_ERR_CQP_COMPL_ERROR:
226 return "I40E_ERR_CQP_COMPL_ERROR";
227 case I40E_ERR_INVALID_VF_ID:
228 return "I40E_ERR_INVALID_VF_ID";
229 case I40E_ERR_INVALID_HMCFN_ID:
230 return "I40E_ERR_INVALID_HMCFN_ID";
231 case I40E_ERR_BACKING_PAGE_ERROR:
232 return "I40E_ERR_BACKING_PAGE_ERROR";
233 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
234 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
235 case I40E_ERR_INVALID_PBLE_INDEX:
236 return "I40E_ERR_INVALID_PBLE_INDEX";
237 case I40E_ERR_INVALID_SD_INDEX:
238 return "I40E_ERR_INVALID_SD_INDEX";
239 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
240 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
241 case I40E_ERR_INVALID_SD_TYPE:
242 return "I40E_ERR_INVALID_SD_TYPE";
243 case I40E_ERR_MEMCPY_FAILED:
244 return "I40E_ERR_MEMCPY_FAILED";
245 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
246 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
247 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
248 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
249 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
250 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
251 case I40E_ERR_SRQ_ENABLED:
252 return "I40E_ERR_SRQ_ENABLED";
253 case I40E_ERR_ADMIN_QUEUE_ERROR:
254 return "I40E_ERR_ADMIN_QUEUE_ERROR";
255 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
256 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
257 case I40E_ERR_BUF_TOO_SHORT:
258 return "I40E_ERR_BUF_TOO_SHORT";
259 case I40E_ERR_ADMIN_QUEUE_FULL:
260 return "I40E_ERR_ADMIN_QUEUE_FULL";
261 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
262 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
263 case I40E_ERR_BAD_IWARP_CQE:
264 return "I40E_ERR_BAD_IWARP_CQE";
265 case I40E_ERR_NVM_BLANK_MODE:
266 return "I40E_ERR_NVM_BLANK_MODE";
267 case I40E_ERR_NOT_IMPLEMENTED:
268 return "I40E_ERR_NOT_IMPLEMENTED";
269 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
270 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
271 case I40E_ERR_DIAG_TEST_FAILED:
272 return "I40E_ERR_DIAG_TEST_FAILED";
273 case I40E_ERR_NOT_READY:
274 return "I40E_ERR_NOT_READY";
275 case I40E_NOT_SUPPORTED:
276 return "I40E_NOT_SUPPORTED";
277 case I40E_ERR_FIRMWARE_API_VERSION:
278 return "I40E_ERR_FIRMWARE_API_VERSION";
279 }
280
281 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
282 return hw->err_str;
283 }
284
285 /**
286 * i40e_debug_aq
287 * @hw: debug mask related to admin queue
288 * @mask: debug mask
289 * @desc: pointer to admin queue descriptor
290 * @buffer: pointer to command buffer
291 * @buf_len: max length of buffer
292 *
293 * Dumps debug log about adminq command with descriptor contents.
294 **/
295 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
296 void *buffer, u16 buf_len)
297 {
298 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
299 u16 len = le16_to_cpu(aq_desc->datalen);
300 u8 *buf = (u8 *)buffer;
301 u16 i = 0;
302
303 if ((!(mask & hw->debug_mask)) || (desc == NULL))
304 return;
305
306 i40e_debug(hw, mask,
307 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
308 le16_to_cpu(aq_desc->opcode),
309 le16_to_cpu(aq_desc->flags),
310 le16_to_cpu(aq_desc->datalen),
311 le16_to_cpu(aq_desc->retval));
312 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
313 le32_to_cpu(aq_desc->cookie_high),
314 le32_to_cpu(aq_desc->cookie_low));
315 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
316 le32_to_cpu(aq_desc->params.internal.param0),
317 le32_to_cpu(aq_desc->params.internal.param1));
318 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
319 le32_to_cpu(aq_desc->params.external.addr_high),
320 le32_to_cpu(aq_desc->params.external.addr_low));
321
322 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
323 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
324 if (buf_len < len)
325 len = buf_len;
326 /* write the full 16-byte chunks */
327 for (i = 0; i < (len - 16); i += 16)
328 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
329 /* write whatever's left over without overrunning the buffer */
330 if (i < len)
331 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
332 i, len - i, buf + i);
333 }
334 }
335
336 /**
337 * i40e_check_asq_alive
338 * @hw: pointer to the hw struct
339 *
340 * Returns true if Queue is enabled else false.
341 **/
342 bool i40e_check_asq_alive(struct i40e_hw *hw)
343 {
344 if (hw->aq.asq.len)
345 return !!(rd32(hw, hw->aq.asq.len) &
346 I40E_PF_ATQLEN_ATQENABLE_MASK);
347 else
348 return false;
349 }
350
351 /**
352 * i40e_aq_queue_shutdown
353 * @hw: pointer to the hw struct
354 * @unloading: is the driver unloading itself
355 *
356 * Tell the Firmware that we're shutting down the AdminQ and whether
357 * or not the driver is unloading as well.
358 **/
359 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
360 bool unloading)
361 {
362 struct i40e_aq_desc desc;
363 struct i40e_aqc_queue_shutdown *cmd =
364 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
365 i40e_status status;
366
367 i40e_fill_default_direct_cmd_desc(&desc,
368 i40e_aqc_opc_queue_shutdown);
369
370 if (unloading)
371 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
372 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
373
374 return status;
375 }
376
377 /**
378 * i40e_aq_get_set_rss_lut
379 * @hw: pointer to the hardware structure
380 * @vsi_id: vsi fw index
381 * @pf_lut: for PF table set true, for VSI table set false
382 * @lut: pointer to the lut buffer provided by the caller
383 * @lut_size: size of the lut buffer
384 * @set: set true to set the table, false to get the table
385 *
386 * Internal function to get or set RSS look up table
387 **/
388 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
389 u16 vsi_id, bool pf_lut,
390 u8 *lut, u16 lut_size,
391 bool set)
392 {
393 i40e_status status;
394 struct i40e_aq_desc desc;
395 struct i40e_aqc_get_set_rss_lut *cmd_resp =
396 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
397
398 if (set)
399 i40e_fill_default_direct_cmd_desc(&desc,
400 i40e_aqc_opc_set_rss_lut);
401 else
402 i40e_fill_default_direct_cmd_desc(&desc,
403 i40e_aqc_opc_get_rss_lut);
404
405 /* Indirect command */
406 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
407 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
408
409 cmd_resp->vsi_id =
410 cpu_to_le16((u16)((vsi_id <<
411 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
412 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
413 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
414
415 if (pf_lut)
416 cmd_resp->flags |= cpu_to_le16((u16)
417 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
419 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
420 else
421 cmd_resp->flags |= cpu_to_le16((u16)
422 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
424 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
425
426 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
427
428 return status;
429 }
430
431 /**
432 * i40e_aq_get_rss_lut
433 * @hw: pointer to the hardware structure
434 * @vsi_id: vsi fw index
435 * @pf_lut: for PF table set true, for VSI table set false
436 * @lut: pointer to the lut buffer provided by the caller
437 * @lut_size: size of the lut buffer
438 *
439 * get the RSS lookup table, PF or VSI type
440 **/
441 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
442 bool pf_lut, u8 *lut, u16 lut_size)
443 {
444 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
445 false);
446 }
447
448 /**
449 * i40e_aq_set_rss_lut
450 * @hw: pointer to the hardware structure
451 * @vsi_id: vsi fw index
452 * @pf_lut: for PF table set true, for VSI table set false
453 * @lut: pointer to the lut buffer provided by the caller
454 * @lut_size: size of the lut buffer
455 *
456 * set the RSS lookup table, PF or VSI type
457 **/
458 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
459 bool pf_lut, u8 *lut, u16 lut_size)
460 {
461 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
462 }
463
464 /**
465 * i40e_aq_get_set_rss_key
466 * @hw: pointer to the hw struct
467 * @vsi_id: vsi fw index
468 * @key: pointer to key info struct
469 * @set: set true to set the key, false to get the key
470 *
471 * get the RSS key per VSI
472 **/
473 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
474 u16 vsi_id,
475 struct i40e_aqc_get_set_rss_key_data *key,
476 bool set)
477 {
478 i40e_status status;
479 struct i40e_aq_desc desc;
480 struct i40e_aqc_get_set_rss_key *cmd_resp =
481 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
482 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
483
484 if (set)
485 i40e_fill_default_direct_cmd_desc(&desc,
486 i40e_aqc_opc_set_rss_key);
487 else
488 i40e_fill_default_direct_cmd_desc(&desc,
489 i40e_aqc_opc_get_rss_key);
490
491 /* Indirect command */
492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
493 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
494
495 cmd_resp->vsi_id =
496 cpu_to_le16((u16)((vsi_id <<
497 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
498 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
499 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
500
501 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
502
503 return status;
504 }
505
506 /**
507 * i40e_aq_get_rss_key
508 * @hw: pointer to the hw struct
509 * @vsi_id: vsi fw index
510 * @key: pointer to key info struct
511 *
512 **/
513 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
514 u16 vsi_id,
515 struct i40e_aqc_get_set_rss_key_data *key)
516 {
517 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
518 }
519
520 /**
521 * i40e_aq_set_rss_key
522 * @hw: pointer to the hw struct
523 * @vsi_id: vsi fw index
524 * @key: pointer to key info struct
525 *
526 * set the RSS key per VSI
527 **/
528 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
529 u16 vsi_id,
530 struct i40e_aqc_get_set_rss_key_data *key)
531 {
532 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
533 }
534
535 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
536 * hardware to a bit-field that can be used by SW to more easily determine the
537 * packet type.
538 *
539 * Macros are used to shorten the table lines and make this table human
540 * readable.
541 *
542 * We store the PTYPE in the top byte of the bit field - this is just so that
543 * we can check that the table doesn't have a row missing, as the index into
544 * the table should be the PTYPE.
545 *
546 * Typical work flow:
547 *
548 * IF NOT i40e_ptype_lookup[ptype].known
549 * THEN
550 * Packet is unknown
551 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
552 * Use the rest of the fields to look at the tunnels, inner protocols, etc
553 * ELSE
554 * Use the enum i40e_rx_l2_ptype to decode the packet type
555 * ENDIF
556 */
557
558 /* macro to make the table lines short */
559 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
560 { PTYPE, \
561 1, \
562 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
563 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
564 I40E_RX_PTYPE_##OUTER_FRAG, \
565 I40E_RX_PTYPE_TUNNEL_##T, \
566 I40E_RX_PTYPE_TUNNEL_END_##TE, \
567 I40E_RX_PTYPE_##TEF, \
568 I40E_RX_PTYPE_INNER_PROT_##I, \
569 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
570
571 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
572 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
573
574 /* shorter macros makes the table fit but are terse */
575 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
576 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
577 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
578
579 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
580 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
581 /* L2 Packet types */
582 I40E_PTT_UNUSED_ENTRY(0),
583 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
584 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
585 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
586 I40E_PTT_UNUSED_ENTRY(4),
587 I40E_PTT_UNUSED_ENTRY(5),
588 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
590 I40E_PTT_UNUSED_ENTRY(8),
591 I40E_PTT_UNUSED_ENTRY(9),
592 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
593 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
594 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604
605 /* Non Tunneled IPv4 */
606 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
608 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
609 I40E_PTT_UNUSED_ENTRY(25),
610 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
611 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
612 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
613
614 /* IPv4 --> IPv4 */
615 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
616 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
617 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
618 I40E_PTT_UNUSED_ENTRY(32),
619 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
620 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
621 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
622
623 /* IPv4 --> IPv6 */
624 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
625 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
626 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
627 I40E_PTT_UNUSED_ENTRY(39),
628 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
629 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
630 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
631
632 /* IPv4 --> GRE/NAT */
633 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
634
635 /* IPv4 --> GRE/NAT --> IPv4 */
636 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
637 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
638 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
639 I40E_PTT_UNUSED_ENTRY(47),
640 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
641 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
642 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
643
644 /* IPv4 --> GRE/NAT --> IPv6 */
645 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
646 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
647 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
648 I40E_PTT_UNUSED_ENTRY(54),
649 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
650 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
651 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
652
653 /* IPv4 --> GRE/NAT --> MAC */
654 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
655
656 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
657 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
658 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
659 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
660 I40E_PTT_UNUSED_ENTRY(62),
661 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
662 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
663 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
664
665 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
666 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
667 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
668 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
669 I40E_PTT_UNUSED_ENTRY(69),
670 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
671 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
672 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
673
674 /* IPv4 --> GRE/NAT --> MAC/VLAN */
675 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
676
677 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
678 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
679 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
680 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
681 I40E_PTT_UNUSED_ENTRY(77),
682 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
683 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
684 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
685
686 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
687 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
688 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
689 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
690 I40E_PTT_UNUSED_ENTRY(84),
691 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
692 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
693 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
694
695 /* Non Tunneled IPv6 */
696 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
697 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
698 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
699 I40E_PTT_UNUSED_ENTRY(91),
700 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
701 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
702 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
703
704 /* IPv6 --> IPv4 */
705 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
706 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
707 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
708 I40E_PTT_UNUSED_ENTRY(98),
709 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
710 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
711 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
712
713 /* IPv6 --> IPv6 */
714 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
715 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
716 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
717 I40E_PTT_UNUSED_ENTRY(105),
718 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
719 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
720 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
721
722 /* IPv6 --> GRE/NAT */
723 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
724
725 /* IPv6 --> GRE/NAT -> IPv4 */
726 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
727 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
728 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
729 I40E_PTT_UNUSED_ENTRY(113),
730 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
731 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
732 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
733
734 /* IPv6 --> GRE/NAT -> IPv6 */
735 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
736 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
737 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
738 I40E_PTT_UNUSED_ENTRY(120),
739 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
740 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
741 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
742
743 /* IPv6 --> GRE/NAT -> MAC */
744 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
745
746 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
747 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
748 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
749 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
750 I40E_PTT_UNUSED_ENTRY(128),
751 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
752 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
753 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
754
755 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
756 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
757 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
758 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
759 I40E_PTT_UNUSED_ENTRY(135),
760 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
761 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
762 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
763
764 /* IPv6 --> GRE/NAT -> MAC/VLAN */
765 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
766
767 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
768 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
769 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
770 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
771 I40E_PTT_UNUSED_ENTRY(143),
772 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
773 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
774 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
775
776 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
777 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
778 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
779 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
780 I40E_PTT_UNUSED_ENTRY(150),
781 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
782 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
783 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
784
785 /* unused entries */
786 I40E_PTT_UNUSED_ENTRY(154),
787 I40E_PTT_UNUSED_ENTRY(155),
788 I40E_PTT_UNUSED_ENTRY(156),
789 I40E_PTT_UNUSED_ENTRY(157),
790 I40E_PTT_UNUSED_ENTRY(158),
791 I40E_PTT_UNUSED_ENTRY(159),
792
793 I40E_PTT_UNUSED_ENTRY(160),
794 I40E_PTT_UNUSED_ENTRY(161),
795 I40E_PTT_UNUSED_ENTRY(162),
796 I40E_PTT_UNUSED_ENTRY(163),
797 I40E_PTT_UNUSED_ENTRY(164),
798 I40E_PTT_UNUSED_ENTRY(165),
799 I40E_PTT_UNUSED_ENTRY(166),
800 I40E_PTT_UNUSED_ENTRY(167),
801 I40E_PTT_UNUSED_ENTRY(168),
802 I40E_PTT_UNUSED_ENTRY(169),
803
804 I40E_PTT_UNUSED_ENTRY(170),
805 I40E_PTT_UNUSED_ENTRY(171),
806 I40E_PTT_UNUSED_ENTRY(172),
807 I40E_PTT_UNUSED_ENTRY(173),
808 I40E_PTT_UNUSED_ENTRY(174),
809 I40E_PTT_UNUSED_ENTRY(175),
810 I40E_PTT_UNUSED_ENTRY(176),
811 I40E_PTT_UNUSED_ENTRY(177),
812 I40E_PTT_UNUSED_ENTRY(178),
813 I40E_PTT_UNUSED_ENTRY(179),
814
815 I40E_PTT_UNUSED_ENTRY(180),
816 I40E_PTT_UNUSED_ENTRY(181),
817 I40E_PTT_UNUSED_ENTRY(182),
818 I40E_PTT_UNUSED_ENTRY(183),
819 I40E_PTT_UNUSED_ENTRY(184),
820 I40E_PTT_UNUSED_ENTRY(185),
821 I40E_PTT_UNUSED_ENTRY(186),
822 I40E_PTT_UNUSED_ENTRY(187),
823 I40E_PTT_UNUSED_ENTRY(188),
824 I40E_PTT_UNUSED_ENTRY(189),
825
826 I40E_PTT_UNUSED_ENTRY(190),
827 I40E_PTT_UNUSED_ENTRY(191),
828 I40E_PTT_UNUSED_ENTRY(192),
829 I40E_PTT_UNUSED_ENTRY(193),
830 I40E_PTT_UNUSED_ENTRY(194),
831 I40E_PTT_UNUSED_ENTRY(195),
832 I40E_PTT_UNUSED_ENTRY(196),
833 I40E_PTT_UNUSED_ENTRY(197),
834 I40E_PTT_UNUSED_ENTRY(198),
835 I40E_PTT_UNUSED_ENTRY(199),
836
837 I40E_PTT_UNUSED_ENTRY(200),
838 I40E_PTT_UNUSED_ENTRY(201),
839 I40E_PTT_UNUSED_ENTRY(202),
840 I40E_PTT_UNUSED_ENTRY(203),
841 I40E_PTT_UNUSED_ENTRY(204),
842 I40E_PTT_UNUSED_ENTRY(205),
843 I40E_PTT_UNUSED_ENTRY(206),
844 I40E_PTT_UNUSED_ENTRY(207),
845 I40E_PTT_UNUSED_ENTRY(208),
846 I40E_PTT_UNUSED_ENTRY(209),
847
848 I40E_PTT_UNUSED_ENTRY(210),
849 I40E_PTT_UNUSED_ENTRY(211),
850 I40E_PTT_UNUSED_ENTRY(212),
851 I40E_PTT_UNUSED_ENTRY(213),
852 I40E_PTT_UNUSED_ENTRY(214),
853 I40E_PTT_UNUSED_ENTRY(215),
854 I40E_PTT_UNUSED_ENTRY(216),
855 I40E_PTT_UNUSED_ENTRY(217),
856 I40E_PTT_UNUSED_ENTRY(218),
857 I40E_PTT_UNUSED_ENTRY(219),
858
859 I40E_PTT_UNUSED_ENTRY(220),
860 I40E_PTT_UNUSED_ENTRY(221),
861 I40E_PTT_UNUSED_ENTRY(222),
862 I40E_PTT_UNUSED_ENTRY(223),
863 I40E_PTT_UNUSED_ENTRY(224),
864 I40E_PTT_UNUSED_ENTRY(225),
865 I40E_PTT_UNUSED_ENTRY(226),
866 I40E_PTT_UNUSED_ENTRY(227),
867 I40E_PTT_UNUSED_ENTRY(228),
868 I40E_PTT_UNUSED_ENTRY(229),
869
870 I40E_PTT_UNUSED_ENTRY(230),
871 I40E_PTT_UNUSED_ENTRY(231),
872 I40E_PTT_UNUSED_ENTRY(232),
873 I40E_PTT_UNUSED_ENTRY(233),
874 I40E_PTT_UNUSED_ENTRY(234),
875 I40E_PTT_UNUSED_ENTRY(235),
876 I40E_PTT_UNUSED_ENTRY(236),
877 I40E_PTT_UNUSED_ENTRY(237),
878 I40E_PTT_UNUSED_ENTRY(238),
879 I40E_PTT_UNUSED_ENTRY(239),
880
881 I40E_PTT_UNUSED_ENTRY(240),
882 I40E_PTT_UNUSED_ENTRY(241),
883 I40E_PTT_UNUSED_ENTRY(242),
884 I40E_PTT_UNUSED_ENTRY(243),
885 I40E_PTT_UNUSED_ENTRY(244),
886 I40E_PTT_UNUSED_ENTRY(245),
887 I40E_PTT_UNUSED_ENTRY(246),
888 I40E_PTT_UNUSED_ENTRY(247),
889 I40E_PTT_UNUSED_ENTRY(248),
890 I40E_PTT_UNUSED_ENTRY(249),
891
892 I40E_PTT_UNUSED_ENTRY(250),
893 I40E_PTT_UNUSED_ENTRY(251),
894 I40E_PTT_UNUSED_ENTRY(252),
895 I40E_PTT_UNUSED_ENTRY(253),
896 I40E_PTT_UNUSED_ENTRY(254),
897 I40E_PTT_UNUSED_ENTRY(255)
898 };
899
900 /**
901 * i40e_init_shared_code - Initialize the shared code
902 * @hw: pointer to hardware structure
903 *
904 * This assigns the MAC type and PHY code and inits the NVM.
905 * Does not touch the hardware. This function must be called prior to any
906 * other function in the shared code. The i40e_hw structure should be
907 * memset to 0 prior to calling this function. The following fields in
908 * hw structure should be filled in prior to calling this function:
909 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
910 * subsystem_vendor_id, and revision_id
911 **/
912 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
913 {
914 i40e_status status = 0;
915 u32 port, ari, func_rid;
916
917 i40e_set_mac_type(hw);
918
919 switch (hw->mac.type) {
920 case I40E_MAC_XL710:
921 case I40E_MAC_X722:
922 break;
923 default:
924 return I40E_ERR_DEVICE_NOT_SUPPORTED;
925 }
926
927 hw->phy.get_link_info = true;
928
929 /* Determine port number and PF number*/
930 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
931 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
932 hw->port = (u8)port;
933 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
934 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
935 func_rid = rd32(hw, I40E_PF_FUNC_RID);
936 if (ari)
937 hw->pf_id = (u8)(func_rid & 0xff);
938 else
939 hw->pf_id = (u8)(func_rid & 0x7);
940
941 if (hw->mac.type == I40E_MAC_X722)
942 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
943
944 status = i40e_init_nvm(hw);
945 return status;
946 }
947
948 /**
949 * i40e_aq_mac_address_read - Retrieve the MAC addresses
950 * @hw: pointer to the hw struct
951 * @flags: a return indicator of what addresses were added to the addr store
952 * @addrs: the requestor's mac addr store
953 * @cmd_details: pointer to command details structure or NULL
954 **/
955 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
956 u16 *flags,
957 struct i40e_aqc_mac_address_read_data *addrs,
958 struct i40e_asq_cmd_details *cmd_details)
959 {
960 struct i40e_aq_desc desc;
961 struct i40e_aqc_mac_address_read *cmd_data =
962 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
963 i40e_status status;
964
965 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
966 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
967
968 status = i40e_asq_send_command(hw, &desc, addrs,
969 sizeof(*addrs), cmd_details);
970 *flags = le16_to_cpu(cmd_data->command_flags);
971
972 return status;
973 }
974
975 /**
976 * i40e_aq_mac_address_write - Change the MAC addresses
977 * @hw: pointer to the hw struct
978 * @flags: indicates which MAC to be written
979 * @mac_addr: address to write
980 * @cmd_details: pointer to command details structure or NULL
981 **/
982 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
983 u16 flags, u8 *mac_addr,
984 struct i40e_asq_cmd_details *cmd_details)
985 {
986 struct i40e_aq_desc desc;
987 struct i40e_aqc_mac_address_write *cmd_data =
988 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
989 i40e_status status;
990
991 i40e_fill_default_direct_cmd_desc(&desc,
992 i40e_aqc_opc_mac_address_write);
993 cmd_data->command_flags = cpu_to_le16(flags);
994 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
995 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
996 ((u32)mac_addr[3] << 16) |
997 ((u32)mac_addr[4] << 8) |
998 mac_addr[5]);
999
1000 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1001
1002 return status;
1003 }
1004
1005 /**
1006 * i40e_get_mac_addr - get MAC address
1007 * @hw: pointer to the HW structure
1008 * @mac_addr: pointer to MAC address
1009 *
1010 * Reads the adapter's MAC address from register
1011 **/
1012 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1013 {
1014 struct i40e_aqc_mac_address_read_data addrs;
1015 i40e_status status;
1016 u16 flags = 0;
1017
1018 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1019
1020 if (flags & I40E_AQC_LAN_ADDR_VALID)
1021 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1022
1023 return status;
1024 }
1025
1026 /**
1027 * i40e_get_port_mac_addr - get Port MAC address
1028 * @hw: pointer to the HW structure
1029 * @mac_addr: pointer to Port MAC address
1030 *
1031 * Reads the adapter's Port MAC address
1032 **/
1033 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1034 {
1035 struct i40e_aqc_mac_address_read_data addrs;
1036 i40e_status status;
1037 u16 flags = 0;
1038
1039 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1040 if (status)
1041 return status;
1042
1043 if (flags & I40E_AQC_PORT_ADDR_VALID)
1044 ether_addr_copy(mac_addr, addrs.port_mac);
1045 else
1046 status = I40E_ERR_INVALID_MAC_ADDR;
1047
1048 return status;
1049 }
1050
1051 /**
1052 * i40e_pre_tx_queue_cfg - pre tx queue configure
1053 * @hw: pointer to the HW structure
1054 * @queue: target PF queue index
1055 * @enable: state change request
1056 *
1057 * Handles hw requirement to indicate intention to enable
1058 * or disable target queue.
1059 **/
1060 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1061 {
1062 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1063 u32 reg_block = 0;
1064 u32 reg_val;
1065
1066 if (abs_queue_idx >= 128) {
1067 reg_block = abs_queue_idx / 128;
1068 abs_queue_idx %= 128;
1069 }
1070
1071 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1072 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1073 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1074
1075 if (enable)
1076 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1077 else
1078 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1079
1080 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1081 }
1082 #ifdef I40E_FCOE
1083
1084 /**
1085 * i40e_get_san_mac_addr - get SAN MAC address
1086 * @hw: pointer to the HW structure
1087 * @mac_addr: pointer to SAN MAC address
1088 *
1089 * Reads the adapter's SAN MAC address from NVM
1090 **/
1091 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1092 {
1093 struct i40e_aqc_mac_address_read_data addrs;
1094 i40e_status status;
1095 u16 flags = 0;
1096
1097 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1098 if (status)
1099 return status;
1100
1101 if (flags & I40E_AQC_SAN_ADDR_VALID)
1102 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1103 else
1104 status = I40E_ERR_INVALID_MAC_ADDR;
1105
1106 return status;
1107 }
1108 #endif
1109
1110 /**
1111 * i40e_read_pba_string - Reads part number string from EEPROM
1112 * @hw: pointer to hardware structure
1113 * @pba_num: stores the part number string from the EEPROM
1114 * @pba_num_size: part number string buffer length
1115 *
1116 * Reads the part number string from the EEPROM.
1117 **/
1118 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1119 u32 pba_num_size)
1120 {
1121 i40e_status status = 0;
1122 u16 pba_word = 0;
1123 u16 pba_size = 0;
1124 u16 pba_ptr = 0;
1125 u16 i = 0;
1126
1127 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1128 if (status || (pba_word != 0xFAFA)) {
1129 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1130 return status;
1131 }
1132
1133 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1134 if (status) {
1135 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1136 return status;
1137 }
1138
1139 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1140 if (status) {
1141 hw_dbg(hw, "Failed to read PBA Block size.\n");
1142 return status;
1143 }
1144
1145 /* Subtract one to get PBA word count (PBA Size word is included in
1146 * total size)
1147 */
1148 pba_size--;
1149 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1150 hw_dbg(hw, "Buffer to small for PBA data.\n");
1151 return I40E_ERR_PARAM;
1152 }
1153
1154 for (i = 0; i < pba_size; i++) {
1155 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1156 if (status) {
1157 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1158 return status;
1159 }
1160
1161 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1162 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1163 }
1164 pba_num[(pba_size * 2)] = '\0';
1165
1166 return status;
1167 }
1168
1169 /**
1170 * i40e_get_media_type - Gets media type
1171 * @hw: pointer to the hardware structure
1172 **/
1173 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1174 {
1175 enum i40e_media_type media;
1176
1177 switch (hw->phy.link_info.phy_type) {
1178 case I40E_PHY_TYPE_10GBASE_SR:
1179 case I40E_PHY_TYPE_10GBASE_LR:
1180 case I40E_PHY_TYPE_1000BASE_SX:
1181 case I40E_PHY_TYPE_1000BASE_LX:
1182 case I40E_PHY_TYPE_40GBASE_SR4:
1183 case I40E_PHY_TYPE_40GBASE_LR4:
1184 media = I40E_MEDIA_TYPE_FIBER;
1185 break;
1186 case I40E_PHY_TYPE_100BASE_TX:
1187 case I40E_PHY_TYPE_1000BASE_T:
1188 case I40E_PHY_TYPE_10GBASE_T:
1189 media = I40E_MEDIA_TYPE_BASET;
1190 break;
1191 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1192 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1193 case I40E_PHY_TYPE_10GBASE_CR1:
1194 case I40E_PHY_TYPE_40GBASE_CR4:
1195 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1196 case I40E_PHY_TYPE_40GBASE_AOC:
1197 case I40E_PHY_TYPE_10GBASE_AOC:
1198 media = I40E_MEDIA_TYPE_DA;
1199 break;
1200 case I40E_PHY_TYPE_1000BASE_KX:
1201 case I40E_PHY_TYPE_10GBASE_KX4:
1202 case I40E_PHY_TYPE_10GBASE_KR:
1203 case I40E_PHY_TYPE_40GBASE_KR4:
1204 case I40E_PHY_TYPE_20GBASE_KR2:
1205 media = I40E_MEDIA_TYPE_BACKPLANE;
1206 break;
1207 case I40E_PHY_TYPE_SGMII:
1208 case I40E_PHY_TYPE_XAUI:
1209 case I40E_PHY_TYPE_XFI:
1210 case I40E_PHY_TYPE_XLAUI:
1211 case I40E_PHY_TYPE_XLPPI:
1212 default:
1213 media = I40E_MEDIA_TYPE_UNKNOWN;
1214 break;
1215 }
1216
1217 return media;
1218 }
1219
1220 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1221 #define I40E_PF_RESET_WAIT_COUNT 200
1222 /**
1223 * i40e_pf_reset - Reset the PF
1224 * @hw: pointer to the hardware structure
1225 *
1226 * Assuming someone else has triggered a global reset,
1227 * assure the global reset is complete and then reset the PF
1228 **/
1229 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1230 {
1231 u32 cnt = 0;
1232 u32 cnt1 = 0;
1233 u32 reg = 0;
1234 u32 grst_del;
1235
1236 /* Poll for Global Reset steady state in case of recent GRST.
1237 * The grst delay value is in 100ms units, and we'll wait a
1238 * couple counts longer to be sure we don't just miss the end.
1239 */
1240 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1241 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1242 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1243
1244 /* It can take upto 15 secs for GRST steady state.
1245 * Bump it to 16 secs max to be safe.
1246 */
1247 grst_del = grst_del * 20;
1248
1249 for (cnt = 0; cnt < grst_del; cnt++) {
1250 reg = rd32(hw, I40E_GLGEN_RSTAT);
1251 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1252 break;
1253 msleep(100);
1254 }
1255 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1256 hw_dbg(hw, "Global reset polling failed to complete.\n");
1257 return I40E_ERR_RESET_FAILED;
1258 }
1259
1260 /* Now Wait for the FW to be ready */
1261 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1262 reg = rd32(hw, I40E_GLNVM_ULD);
1263 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1264 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1265 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1267 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1268 break;
1269 }
1270 usleep_range(10000, 20000);
1271 }
1272 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1273 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1274 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1275 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1276 return I40E_ERR_RESET_FAILED;
1277 }
1278
1279 /* If there was a Global Reset in progress when we got here,
1280 * we don't need to do the PF Reset
1281 */
1282 if (!cnt) {
1283 if (hw->revision_id == 0)
1284 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1285 else
1286 cnt = I40E_PF_RESET_WAIT_COUNT;
1287 reg = rd32(hw, I40E_PFGEN_CTRL);
1288 wr32(hw, I40E_PFGEN_CTRL,
1289 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1290 for (; cnt; cnt--) {
1291 reg = rd32(hw, I40E_PFGEN_CTRL);
1292 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1293 break;
1294 usleep_range(1000, 2000);
1295 }
1296 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1297 hw_dbg(hw, "PF reset polling failed to complete.\n");
1298 return I40E_ERR_RESET_FAILED;
1299 }
1300 }
1301
1302 i40e_clear_pxe_mode(hw);
1303
1304 return 0;
1305 }
1306
1307 /**
1308 * i40e_clear_hw - clear out any left over hw state
1309 * @hw: pointer to the hw struct
1310 *
1311 * Clear queues and interrupts, typically called at init time,
1312 * but after the capabilities have been found so we know how many
1313 * queues and msix vectors have been allocated.
1314 **/
1315 void i40e_clear_hw(struct i40e_hw *hw)
1316 {
1317 u32 num_queues, base_queue;
1318 u32 num_pf_int;
1319 u32 num_vf_int;
1320 u32 num_vfs;
1321 u32 i, j;
1322 u32 val;
1323 u32 eol = 0x7ff;
1324
1325 /* get number of interrupts, queues, and VFs */
1326 val = rd32(hw, I40E_GLPCI_CNF2);
1327 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1328 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1329 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1330 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1331
1332 val = rd32(hw, I40E_PFLAN_QALLOC);
1333 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1334 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1335 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1336 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1337 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1338 num_queues = (j - base_queue) + 1;
1339 else
1340 num_queues = 0;
1341
1342 val = rd32(hw, I40E_PF_VT_PFALLOC);
1343 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1344 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1345 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1346 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1347 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1348 num_vfs = (j - i) + 1;
1349 else
1350 num_vfs = 0;
1351
1352 /* stop all the interrupts */
1353 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1354 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1355 for (i = 0; i < num_pf_int - 2; i++)
1356 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1357
1358 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1359 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1360 wr32(hw, I40E_PFINT_LNKLST0, val);
1361 for (i = 0; i < num_pf_int - 2; i++)
1362 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1363 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1364 for (i = 0; i < num_vfs; i++)
1365 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1366 for (i = 0; i < num_vf_int - 2; i++)
1367 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1368
1369 /* warn the HW of the coming Tx disables */
1370 for (i = 0; i < num_queues; i++) {
1371 u32 abs_queue_idx = base_queue + i;
1372 u32 reg_block = 0;
1373
1374 if (abs_queue_idx >= 128) {
1375 reg_block = abs_queue_idx / 128;
1376 abs_queue_idx %= 128;
1377 }
1378
1379 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1380 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1381 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1382 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1383
1384 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1385 }
1386 udelay(400);
1387
1388 /* stop all the queues */
1389 for (i = 0; i < num_queues; i++) {
1390 wr32(hw, I40E_QINT_TQCTL(i), 0);
1391 wr32(hw, I40E_QTX_ENA(i), 0);
1392 wr32(hw, I40E_QINT_RQCTL(i), 0);
1393 wr32(hw, I40E_QRX_ENA(i), 0);
1394 }
1395
1396 /* short wait for all queue disables to settle */
1397 udelay(50);
1398 }
1399
1400 /**
1401 * i40e_clear_pxe_mode - clear pxe operations mode
1402 * @hw: pointer to the hw struct
1403 *
1404 * Make sure all PXE mode settings are cleared, including things
1405 * like descriptor fetch/write-back mode.
1406 **/
1407 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1408 {
1409 u32 reg;
1410
1411 if (i40e_check_asq_alive(hw))
1412 i40e_aq_clear_pxe_mode(hw, NULL);
1413
1414 /* Clear single descriptor fetch/write-back mode */
1415 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1416
1417 if (hw->revision_id == 0) {
1418 /* As a work around clear PXE_MODE instead of setting it */
1419 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1420 } else {
1421 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1422 }
1423 }
1424
1425 /**
1426 * i40e_led_is_mine - helper to find matching led
1427 * @hw: pointer to the hw struct
1428 * @idx: index into GPIO registers
1429 *
1430 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1431 */
1432 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1433 {
1434 u32 gpio_val = 0;
1435 u32 port;
1436
1437 if (!hw->func_caps.led[idx])
1438 return 0;
1439
1440 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1441 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1442 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1443
1444 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1445 * if it is not our port then ignore
1446 */
1447 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1448 (port != hw->port))
1449 return 0;
1450
1451 return gpio_val;
1452 }
1453
1454 #define I40E_COMBINED_ACTIVITY 0xA
1455 #define I40E_FILTER_ACTIVITY 0xE
1456 #define I40E_LINK_ACTIVITY 0xC
1457 #define I40E_MAC_ACTIVITY 0xD
1458 #define I40E_LED0 22
1459
1460 /**
1461 * i40e_led_get - return current on/off mode
1462 * @hw: pointer to the hw struct
1463 *
1464 * The value returned is the 'mode' field as defined in the
1465 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1466 * values are variations of possible behaviors relating to
1467 * blink, link, and wire.
1468 **/
1469 u32 i40e_led_get(struct i40e_hw *hw)
1470 {
1471 u32 current_mode = 0;
1472 u32 mode = 0;
1473 int i;
1474
1475 /* as per the documentation GPIO 22-29 are the LED
1476 * GPIO pins named LED0..LED7
1477 */
1478 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1479 u32 gpio_val = i40e_led_is_mine(hw, i);
1480
1481 if (!gpio_val)
1482 continue;
1483
1484 /* ignore gpio LED src mode entries related to the activity
1485 * LEDs
1486 */
1487 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1488 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1489 switch (current_mode) {
1490 case I40E_COMBINED_ACTIVITY:
1491 case I40E_FILTER_ACTIVITY:
1492 case I40E_MAC_ACTIVITY:
1493 continue;
1494 default:
1495 break;
1496 }
1497
1498 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1499 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1500 break;
1501 }
1502
1503 return mode;
1504 }
1505
1506 /**
1507 * i40e_led_set - set new on/off mode
1508 * @hw: pointer to the hw struct
1509 * @mode: 0=off, 0xf=on (else see manual for mode details)
1510 * @blink: true if the LED should blink when on, false if steady
1511 *
1512 * if this function is used to turn on the blink it should
1513 * be used to disable the blink when restoring the original state.
1514 **/
1515 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1516 {
1517 u32 current_mode = 0;
1518 int i;
1519
1520 if (mode & 0xfffffff0)
1521 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1522
1523 /* as per the documentation GPIO 22-29 are the LED
1524 * GPIO pins named LED0..LED7
1525 */
1526 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1527 u32 gpio_val = i40e_led_is_mine(hw, i);
1528
1529 if (!gpio_val)
1530 continue;
1531
1532 /* ignore gpio LED src mode entries related to the activity
1533 * LEDs
1534 */
1535 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1536 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1537 switch (current_mode) {
1538 case I40E_COMBINED_ACTIVITY:
1539 case I40E_FILTER_ACTIVITY:
1540 case I40E_MAC_ACTIVITY:
1541 continue;
1542 default:
1543 break;
1544 }
1545
1546 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1547 /* this & is a bit of paranoia, but serves as a range check */
1548 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1549 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1550
1551 if (mode == I40E_LINK_ACTIVITY)
1552 blink = false;
1553
1554 if (blink)
1555 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1556 else
1557 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1558
1559 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1560 break;
1561 }
1562 }
1563
1564 /* Admin command wrappers */
1565
1566 /**
1567 * i40e_aq_get_phy_capabilities
1568 * @hw: pointer to the hw struct
1569 * @abilities: structure for PHY capabilities to be filled
1570 * @qualified_modules: report Qualified Modules
1571 * @report_init: report init capabilities (active are default)
1572 * @cmd_details: pointer to command details structure or NULL
1573 *
1574 * Returns the various PHY abilities supported on the Port.
1575 **/
1576 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1577 bool qualified_modules, bool report_init,
1578 struct i40e_aq_get_phy_abilities_resp *abilities,
1579 struct i40e_asq_cmd_details *cmd_details)
1580 {
1581 struct i40e_aq_desc desc;
1582 i40e_status status;
1583 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1584
1585 if (!abilities)
1586 return I40E_ERR_PARAM;
1587
1588 i40e_fill_default_direct_cmd_desc(&desc,
1589 i40e_aqc_opc_get_phy_abilities);
1590
1591 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1592 if (abilities_size > I40E_AQ_LARGE_BUF)
1593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1594
1595 if (qualified_modules)
1596 desc.params.external.param0 |=
1597 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1598
1599 if (report_init)
1600 desc.params.external.param0 |=
1601 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1602
1603 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1604 cmd_details);
1605
1606 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1607 status = I40E_ERR_UNKNOWN_PHY;
1608
1609 if (report_init)
1610 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1611
1612 return status;
1613 }
1614
1615 /**
1616 * i40e_aq_set_phy_config
1617 * @hw: pointer to the hw struct
1618 * @config: structure with PHY configuration to be set
1619 * @cmd_details: pointer to command details structure or NULL
1620 *
1621 * Set the various PHY configuration parameters
1622 * supported on the Port.One or more of the Set PHY config parameters may be
1623 * ignored in an MFP mode as the PF may not have the privilege to set some
1624 * of the PHY Config parameters. This status will be indicated by the
1625 * command response.
1626 **/
1627 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1628 struct i40e_aq_set_phy_config *config,
1629 struct i40e_asq_cmd_details *cmd_details)
1630 {
1631 struct i40e_aq_desc desc;
1632 struct i40e_aq_set_phy_config *cmd =
1633 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1634 enum i40e_status_code status;
1635
1636 if (!config)
1637 return I40E_ERR_PARAM;
1638
1639 i40e_fill_default_direct_cmd_desc(&desc,
1640 i40e_aqc_opc_set_phy_config);
1641
1642 *cmd = *config;
1643
1644 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1645
1646 return status;
1647 }
1648
1649 /**
1650 * i40e_set_fc
1651 * @hw: pointer to the hw struct
1652 *
1653 * Set the requested flow control mode using set_phy_config.
1654 **/
1655 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1656 bool atomic_restart)
1657 {
1658 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1659 struct i40e_aq_get_phy_abilities_resp abilities;
1660 struct i40e_aq_set_phy_config config;
1661 enum i40e_status_code status;
1662 u8 pause_mask = 0x0;
1663
1664 *aq_failures = 0x0;
1665
1666 switch (fc_mode) {
1667 case I40E_FC_FULL:
1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1669 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1670 break;
1671 case I40E_FC_RX_PAUSE:
1672 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1673 break;
1674 case I40E_FC_TX_PAUSE:
1675 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1676 break;
1677 default:
1678 break;
1679 }
1680
1681 /* Get the current phy config */
1682 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1683 NULL);
1684 if (status) {
1685 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1686 return status;
1687 }
1688
1689 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1690 /* clear the old pause settings */
1691 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1692 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1693 /* set the new abilities */
1694 config.abilities |= pause_mask;
1695 /* If the abilities have changed, then set the new config */
1696 if (config.abilities != abilities.abilities) {
1697 /* Auto restart link so settings take effect */
1698 if (atomic_restart)
1699 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1700 /* Copy over all the old settings */
1701 config.phy_type = abilities.phy_type;
1702 config.link_speed = abilities.link_speed;
1703 config.eee_capability = abilities.eee_capability;
1704 config.eeer = abilities.eeer_val;
1705 config.low_power_ctrl = abilities.d3_lpan;
1706 status = i40e_aq_set_phy_config(hw, &config, NULL);
1707
1708 if (status)
1709 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1710 }
1711 /* Update the link info */
1712 status = i40e_update_link_info(hw);
1713 if (status) {
1714 /* Wait a little bit (on 40G cards it sometimes takes a really
1715 * long time for link to come back from the atomic reset)
1716 * and try once more
1717 */
1718 msleep(1000);
1719 status = i40e_update_link_info(hw);
1720 }
1721 if (status)
1722 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1723
1724 return status;
1725 }
1726
1727 /**
1728 * i40e_aq_clear_pxe_mode
1729 * @hw: pointer to the hw struct
1730 * @cmd_details: pointer to command details structure or NULL
1731 *
1732 * Tell the firmware that the driver is taking over from PXE
1733 **/
1734 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1735 struct i40e_asq_cmd_details *cmd_details)
1736 {
1737 i40e_status status;
1738 struct i40e_aq_desc desc;
1739 struct i40e_aqc_clear_pxe *cmd =
1740 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1741
1742 i40e_fill_default_direct_cmd_desc(&desc,
1743 i40e_aqc_opc_clear_pxe_mode);
1744
1745 cmd->rx_cnt = 0x2;
1746
1747 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1748
1749 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1750
1751 return status;
1752 }
1753
1754 /**
1755 * i40e_aq_set_link_restart_an
1756 * @hw: pointer to the hw struct
1757 * @enable_link: if true: enable link, if false: disable link
1758 * @cmd_details: pointer to command details structure or NULL
1759 *
1760 * Sets up the link and restarts the Auto-Negotiation over the link.
1761 **/
1762 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1763 bool enable_link,
1764 struct i40e_asq_cmd_details *cmd_details)
1765 {
1766 struct i40e_aq_desc desc;
1767 struct i40e_aqc_set_link_restart_an *cmd =
1768 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1769 i40e_status status;
1770
1771 i40e_fill_default_direct_cmd_desc(&desc,
1772 i40e_aqc_opc_set_link_restart_an);
1773
1774 cmd->command = I40E_AQ_PHY_RESTART_AN;
1775 if (enable_link)
1776 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1777 else
1778 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1779
1780 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1781
1782 return status;
1783 }
1784
1785 /**
1786 * i40e_aq_get_link_info
1787 * @hw: pointer to the hw struct
1788 * @enable_lse: enable/disable LinkStatusEvent reporting
1789 * @link: pointer to link status structure - optional
1790 * @cmd_details: pointer to command details structure or NULL
1791 *
1792 * Returns the link status of the adapter.
1793 **/
1794 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1795 bool enable_lse, struct i40e_link_status *link,
1796 struct i40e_asq_cmd_details *cmd_details)
1797 {
1798 struct i40e_aq_desc desc;
1799 struct i40e_aqc_get_link_status *resp =
1800 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1801 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1802 i40e_status status;
1803 bool tx_pause, rx_pause;
1804 u16 command_flags;
1805
1806 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1807
1808 if (enable_lse)
1809 command_flags = I40E_AQ_LSE_ENABLE;
1810 else
1811 command_flags = I40E_AQ_LSE_DISABLE;
1812 resp->command_flags = cpu_to_le16(command_flags);
1813
1814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816 if (status)
1817 goto aq_get_link_info_exit;
1818
1819 /* save off old link status information */
1820 hw->phy.link_info_old = *hw_link_info;
1821
1822 /* update link status */
1823 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1824 hw->phy.media_type = i40e_get_media_type(hw);
1825 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1826 hw_link_info->link_info = resp->link_info;
1827 hw_link_info->an_info = resp->an_info;
1828 hw_link_info->ext_info = resp->ext_info;
1829 hw_link_info->loopback = resp->loopback;
1830 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1831 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1832
1833 /* update fc info */
1834 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1835 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1836 if (tx_pause & rx_pause)
1837 hw->fc.current_mode = I40E_FC_FULL;
1838 else if (tx_pause)
1839 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1840 else if (rx_pause)
1841 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1842 else
1843 hw->fc.current_mode = I40E_FC_NONE;
1844
1845 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1846 hw_link_info->crc_enable = true;
1847 else
1848 hw_link_info->crc_enable = false;
1849
1850 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1851 hw_link_info->lse_enable = true;
1852 else
1853 hw_link_info->lse_enable = false;
1854
1855 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1856 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1857 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1858
1859 /* save link status information */
1860 if (link)
1861 *link = *hw_link_info;
1862
1863 /* flag cleared so helper functions don't call AQ again */
1864 hw->phy.get_link_info = false;
1865
1866 aq_get_link_info_exit:
1867 return status;
1868 }
1869
1870 /**
1871 * i40e_aq_set_phy_int_mask
1872 * @hw: pointer to the hw struct
1873 * @mask: interrupt mask to be set
1874 * @cmd_details: pointer to command details structure or NULL
1875 *
1876 * Set link interrupt mask.
1877 **/
1878 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1879 u16 mask,
1880 struct i40e_asq_cmd_details *cmd_details)
1881 {
1882 struct i40e_aq_desc desc;
1883 struct i40e_aqc_set_phy_int_mask *cmd =
1884 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1885 i40e_status status;
1886
1887 i40e_fill_default_direct_cmd_desc(&desc,
1888 i40e_aqc_opc_set_phy_int_mask);
1889
1890 cmd->event_mask = cpu_to_le16(mask);
1891
1892 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1893
1894 return status;
1895 }
1896
1897 /**
1898 * i40e_aq_set_phy_debug
1899 * @hw: pointer to the hw struct
1900 * @cmd_flags: debug command flags
1901 * @cmd_details: pointer to command details structure or NULL
1902 *
1903 * Reset the external PHY.
1904 **/
1905 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1906 struct i40e_asq_cmd_details *cmd_details)
1907 {
1908 struct i40e_aq_desc desc;
1909 struct i40e_aqc_set_phy_debug *cmd =
1910 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1911 i40e_status status;
1912
1913 i40e_fill_default_direct_cmd_desc(&desc,
1914 i40e_aqc_opc_set_phy_debug);
1915
1916 cmd->command_flags = cmd_flags;
1917
1918 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1919
1920 return status;
1921 }
1922
1923 /**
1924 * i40e_aq_add_vsi
1925 * @hw: pointer to the hw struct
1926 * @vsi_ctx: pointer to a vsi context struct
1927 * @cmd_details: pointer to command details structure or NULL
1928 *
1929 * Add a VSI context to the hardware.
1930 **/
1931 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1932 struct i40e_vsi_context *vsi_ctx,
1933 struct i40e_asq_cmd_details *cmd_details)
1934 {
1935 struct i40e_aq_desc desc;
1936 struct i40e_aqc_add_get_update_vsi *cmd =
1937 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1938 struct i40e_aqc_add_get_update_vsi_completion *resp =
1939 (struct i40e_aqc_add_get_update_vsi_completion *)
1940 &desc.params.raw;
1941 i40e_status status;
1942
1943 i40e_fill_default_direct_cmd_desc(&desc,
1944 i40e_aqc_opc_add_vsi);
1945
1946 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1947 cmd->connection_type = vsi_ctx->connection_type;
1948 cmd->vf_id = vsi_ctx->vf_num;
1949 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1950
1951 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1952
1953 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1954 sizeof(vsi_ctx->info), cmd_details);
1955
1956 if (status)
1957 goto aq_add_vsi_exit;
1958
1959 vsi_ctx->seid = le16_to_cpu(resp->seid);
1960 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1961 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1962 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1963
1964 aq_add_vsi_exit:
1965 return status;
1966 }
1967
1968 /**
1969 * i40e_aq_set_vsi_unicast_promiscuous
1970 * @hw: pointer to the hw struct
1971 * @seid: vsi number
1972 * @set: set unicast promiscuous enable/disable
1973 * @cmd_details: pointer to command details structure or NULL
1974 **/
1975 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1976 u16 seid, bool set,
1977 struct i40e_asq_cmd_details *cmd_details)
1978 {
1979 struct i40e_aq_desc desc;
1980 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1981 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1982 i40e_status status;
1983 u16 flags = 0;
1984
1985 i40e_fill_default_direct_cmd_desc(&desc,
1986 i40e_aqc_opc_set_vsi_promiscuous_modes);
1987
1988 if (set) {
1989 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1990 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
1991 (hw->aq.api_maj_ver > 1))
1992 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
1993 }
1994
1995 cmd->promiscuous_flags = cpu_to_le16(flags);
1996
1997 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1998 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
1999 (hw->aq.api_maj_ver > 1))
2000 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2001
2002 cmd->seid = cpu_to_le16(seid);
2003 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2004
2005 return status;
2006 }
2007
2008 /**
2009 * i40e_aq_set_vsi_multicast_promiscuous
2010 * @hw: pointer to the hw struct
2011 * @seid: vsi number
2012 * @set: set multicast promiscuous enable/disable
2013 * @cmd_details: pointer to command details structure or NULL
2014 **/
2015 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2016 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2017 {
2018 struct i40e_aq_desc desc;
2019 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2020 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2021 i40e_status status;
2022 u16 flags = 0;
2023
2024 i40e_fill_default_direct_cmd_desc(&desc,
2025 i40e_aqc_opc_set_vsi_promiscuous_modes);
2026
2027 if (set)
2028 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2029
2030 cmd->promiscuous_flags = cpu_to_le16(flags);
2031
2032 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2033
2034 cmd->seid = cpu_to_le16(seid);
2035 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2036
2037 return status;
2038 }
2039
2040 /**
2041 * i40e_aq_set_vsi_broadcast
2042 * @hw: pointer to the hw struct
2043 * @seid: vsi number
2044 * @set_filter: true to set filter, false to clear filter
2045 * @cmd_details: pointer to command details structure or NULL
2046 *
2047 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2048 **/
2049 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2050 u16 seid, bool set_filter,
2051 struct i40e_asq_cmd_details *cmd_details)
2052 {
2053 struct i40e_aq_desc desc;
2054 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2055 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2056 i40e_status status;
2057
2058 i40e_fill_default_direct_cmd_desc(&desc,
2059 i40e_aqc_opc_set_vsi_promiscuous_modes);
2060
2061 if (set_filter)
2062 cmd->promiscuous_flags
2063 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2064 else
2065 cmd->promiscuous_flags
2066 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2067
2068 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2069 cmd->seid = cpu_to_le16(seid);
2070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2071
2072 return status;
2073 }
2074
2075 /**
2076 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2077 * @hw: pointer to the hw struct
2078 * @seid: vsi number
2079 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2080 * @cmd_details: pointer to command details structure or NULL
2081 **/
2082 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2083 u16 seid, bool enable,
2084 struct i40e_asq_cmd_details *cmd_details)
2085 {
2086 struct i40e_aq_desc desc;
2087 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2088 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2089 i40e_status status;
2090 u16 flags = 0;
2091
2092 i40e_fill_default_direct_cmd_desc(&desc,
2093 i40e_aqc_opc_set_vsi_promiscuous_modes);
2094 if (enable)
2095 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2096
2097 cmd->promiscuous_flags = cpu_to_le16(flags);
2098 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2099 cmd->seid = cpu_to_le16(seid);
2100
2101 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2102
2103 return status;
2104 }
2105
2106 /**
2107 * i40e_get_vsi_params - get VSI configuration info
2108 * @hw: pointer to the hw struct
2109 * @vsi_ctx: pointer to a vsi context struct
2110 * @cmd_details: pointer to command details structure or NULL
2111 **/
2112 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2113 struct i40e_vsi_context *vsi_ctx,
2114 struct i40e_asq_cmd_details *cmd_details)
2115 {
2116 struct i40e_aq_desc desc;
2117 struct i40e_aqc_add_get_update_vsi *cmd =
2118 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2119 struct i40e_aqc_add_get_update_vsi_completion *resp =
2120 (struct i40e_aqc_add_get_update_vsi_completion *)
2121 &desc.params.raw;
2122 i40e_status status;
2123
2124 i40e_fill_default_direct_cmd_desc(&desc,
2125 i40e_aqc_opc_get_vsi_parameters);
2126
2127 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2128
2129 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2130
2131 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2132 sizeof(vsi_ctx->info), NULL);
2133
2134 if (status)
2135 goto aq_get_vsi_params_exit;
2136
2137 vsi_ctx->seid = le16_to_cpu(resp->seid);
2138 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2139 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2140 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2141
2142 aq_get_vsi_params_exit:
2143 return status;
2144 }
2145
2146 /**
2147 * i40e_aq_update_vsi_params
2148 * @hw: pointer to the hw struct
2149 * @vsi_ctx: pointer to a vsi context struct
2150 * @cmd_details: pointer to command details structure or NULL
2151 *
2152 * Update a VSI context.
2153 **/
2154 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2155 struct i40e_vsi_context *vsi_ctx,
2156 struct i40e_asq_cmd_details *cmd_details)
2157 {
2158 struct i40e_aq_desc desc;
2159 struct i40e_aqc_add_get_update_vsi *cmd =
2160 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2161 struct i40e_aqc_add_get_update_vsi_completion *resp =
2162 (struct i40e_aqc_add_get_update_vsi_completion *)
2163 &desc.params.raw;
2164 i40e_status status;
2165
2166 i40e_fill_default_direct_cmd_desc(&desc,
2167 i40e_aqc_opc_update_vsi_parameters);
2168 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2169
2170 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2171
2172 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2173 sizeof(vsi_ctx->info), cmd_details);
2174
2175 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2176 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2177
2178 return status;
2179 }
2180
2181 /**
2182 * i40e_aq_get_switch_config
2183 * @hw: pointer to the hardware structure
2184 * @buf: pointer to the result buffer
2185 * @buf_size: length of input buffer
2186 * @start_seid: seid to start for the report, 0 == beginning
2187 * @cmd_details: pointer to command details structure or NULL
2188 *
2189 * Fill the buf with switch configuration returned from AdminQ command
2190 **/
2191 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2192 struct i40e_aqc_get_switch_config_resp *buf,
2193 u16 buf_size, u16 *start_seid,
2194 struct i40e_asq_cmd_details *cmd_details)
2195 {
2196 struct i40e_aq_desc desc;
2197 struct i40e_aqc_switch_seid *scfg =
2198 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2199 i40e_status status;
2200
2201 i40e_fill_default_direct_cmd_desc(&desc,
2202 i40e_aqc_opc_get_switch_config);
2203 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2204 if (buf_size > I40E_AQ_LARGE_BUF)
2205 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2206 scfg->seid = cpu_to_le16(*start_seid);
2207
2208 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2209 *start_seid = le16_to_cpu(scfg->seid);
2210
2211 return status;
2212 }
2213
2214 /**
2215 * i40e_aq_get_firmware_version
2216 * @hw: pointer to the hw struct
2217 * @fw_major_version: firmware major version
2218 * @fw_minor_version: firmware minor version
2219 * @fw_build: firmware build number
2220 * @api_major_version: major queue version
2221 * @api_minor_version: minor queue version
2222 * @cmd_details: pointer to command details structure or NULL
2223 *
2224 * Get the firmware version from the admin queue commands
2225 **/
2226 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2227 u16 *fw_major_version, u16 *fw_minor_version,
2228 u32 *fw_build,
2229 u16 *api_major_version, u16 *api_minor_version,
2230 struct i40e_asq_cmd_details *cmd_details)
2231 {
2232 struct i40e_aq_desc desc;
2233 struct i40e_aqc_get_version *resp =
2234 (struct i40e_aqc_get_version *)&desc.params.raw;
2235 i40e_status status;
2236
2237 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2238
2239 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2240
2241 if (!status) {
2242 if (fw_major_version)
2243 *fw_major_version = le16_to_cpu(resp->fw_major);
2244 if (fw_minor_version)
2245 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2246 if (fw_build)
2247 *fw_build = le32_to_cpu(resp->fw_build);
2248 if (api_major_version)
2249 *api_major_version = le16_to_cpu(resp->api_major);
2250 if (api_minor_version)
2251 *api_minor_version = le16_to_cpu(resp->api_minor);
2252 }
2253
2254 return status;
2255 }
2256
2257 /**
2258 * i40e_aq_send_driver_version
2259 * @hw: pointer to the hw struct
2260 * @dv: driver's major, minor version
2261 * @cmd_details: pointer to command details structure or NULL
2262 *
2263 * Send the driver version to the firmware
2264 **/
2265 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2266 struct i40e_driver_version *dv,
2267 struct i40e_asq_cmd_details *cmd_details)
2268 {
2269 struct i40e_aq_desc desc;
2270 struct i40e_aqc_driver_version *cmd =
2271 (struct i40e_aqc_driver_version *)&desc.params.raw;
2272 i40e_status status;
2273 u16 len;
2274
2275 if (dv == NULL)
2276 return I40E_ERR_PARAM;
2277
2278 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2279
2280 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2281 cmd->driver_major_ver = dv->major_version;
2282 cmd->driver_minor_ver = dv->minor_version;
2283 cmd->driver_build_ver = dv->build_version;
2284 cmd->driver_subbuild_ver = dv->subbuild_version;
2285
2286 len = 0;
2287 while (len < sizeof(dv->driver_string) &&
2288 (dv->driver_string[len] < 0x80) &&
2289 dv->driver_string[len])
2290 len++;
2291 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2292 len, cmd_details);
2293
2294 return status;
2295 }
2296
2297 /**
2298 * i40e_get_link_status - get status of the HW network link
2299 * @hw: pointer to the hw struct
2300 * @link_up: pointer to bool (true/false = linkup/linkdown)
2301 *
2302 * Variable link_up true if link is up, false if link is down.
2303 * The variable link_up is invalid if returned value of status != 0
2304 *
2305 * Side effect: LinkStatusEvent reporting becomes enabled
2306 **/
2307 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2308 {
2309 i40e_status status = 0;
2310
2311 if (hw->phy.get_link_info) {
2312 status = i40e_update_link_info(hw);
2313
2314 if (status)
2315 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2316 status);
2317 }
2318
2319 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2320
2321 return status;
2322 }
2323
2324 /**
2325 * i40e_updatelink_status - update status of the HW network link
2326 * @hw: pointer to the hw struct
2327 **/
2328 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2329 {
2330 struct i40e_aq_get_phy_abilities_resp abilities;
2331 i40e_status status = 0;
2332
2333 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2334 if (status)
2335 return status;
2336
2337 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2338 status = i40e_aq_get_phy_capabilities(hw, false, false,
2339 &abilities, NULL);
2340 if (status)
2341 return status;
2342
2343 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2344 sizeof(hw->phy.link_info.module_type));
2345 }
2346
2347 return status;
2348 }
2349
2350 /**
2351 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2352 * @hw: pointer to the hw struct
2353 * @uplink_seid: the MAC or other gizmo SEID
2354 * @downlink_seid: the VSI SEID
2355 * @enabled_tc: bitmap of TCs to be enabled
2356 * @default_port: true for default port VSI, false for control port
2357 * @veb_seid: pointer to where to put the resulting VEB SEID
2358 * @enable_stats: true to turn on VEB stats
2359 * @cmd_details: pointer to command details structure or NULL
2360 *
2361 * This asks the FW to add a VEB between the uplink and downlink
2362 * elements. If the uplink SEID is 0, this will be a floating VEB.
2363 **/
2364 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2365 u16 downlink_seid, u8 enabled_tc,
2366 bool default_port, u16 *veb_seid,
2367 bool enable_stats,
2368 struct i40e_asq_cmd_details *cmd_details)
2369 {
2370 struct i40e_aq_desc desc;
2371 struct i40e_aqc_add_veb *cmd =
2372 (struct i40e_aqc_add_veb *)&desc.params.raw;
2373 struct i40e_aqc_add_veb_completion *resp =
2374 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2375 i40e_status status;
2376 u16 veb_flags = 0;
2377
2378 /* SEIDs need to either both be set or both be 0 for floating VEB */
2379 if (!!uplink_seid != !!downlink_seid)
2380 return I40E_ERR_PARAM;
2381
2382 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2383
2384 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2385 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2386 cmd->enable_tcs = enabled_tc;
2387 if (!uplink_seid)
2388 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2389 if (default_port)
2390 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2391 else
2392 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2393
2394 /* reverse logic here: set the bitflag to disable the stats */
2395 if (!enable_stats)
2396 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2397
2398 cmd->veb_flags = cpu_to_le16(veb_flags);
2399
2400 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2401
2402 if (!status && veb_seid)
2403 *veb_seid = le16_to_cpu(resp->veb_seid);
2404
2405 return status;
2406 }
2407
2408 /**
2409 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2410 * @hw: pointer to the hw struct
2411 * @veb_seid: the SEID of the VEB to query
2412 * @switch_id: the uplink switch id
2413 * @floating: set to true if the VEB is floating
2414 * @statistic_index: index of the stats counter block for this VEB
2415 * @vebs_used: number of VEB's used by function
2416 * @vebs_free: total VEB's not reserved by any function
2417 * @cmd_details: pointer to command details structure or NULL
2418 *
2419 * This retrieves the parameters for a particular VEB, specified by
2420 * uplink_seid, and returns them to the caller.
2421 **/
2422 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2423 u16 veb_seid, u16 *switch_id,
2424 bool *floating, u16 *statistic_index,
2425 u16 *vebs_used, u16 *vebs_free,
2426 struct i40e_asq_cmd_details *cmd_details)
2427 {
2428 struct i40e_aq_desc desc;
2429 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2430 (struct i40e_aqc_get_veb_parameters_completion *)
2431 &desc.params.raw;
2432 i40e_status status;
2433
2434 if (veb_seid == 0)
2435 return I40E_ERR_PARAM;
2436
2437 i40e_fill_default_direct_cmd_desc(&desc,
2438 i40e_aqc_opc_get_veb_parameters);
2439 cmd_resp->seid = cpu_to_le16(veb_seid);
2440
2441 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2442 if (status)
2443 goto get_veb_exit;
2444
2445 if (switch_id)
2446 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2447 if (statistic_index)
2448 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2449 if (vebs_used)
2450 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2451 if (vebs_free)
2452 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2453 if (floating) {
2454 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2455
2456 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2457 *floating = true;
2458 else
2459 *floating = false;
2460 }
2461
2462 get_veb_exit:
2463 return status;
2464 }
2465
2466 /**
2467 * i40e_aq_add_macvlan
2468 * @hw: pointer to the hw struct
2469 * @seid: VSI for the mac address
2470 * @mv_list: list of macvlans to be added
2471 * @count: length of the list
2472 * @cmd_details: pointer to command details structure or NULL
2473 *
2474 * Add MAC/VLAN addresses to the HW filtering
2475 **/
2476 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2477 struct i40e_aqc_add_macvlan_element_data *mv_list,
2478 u16 count, struct i40e_asq_cmd_details *cmd_details)
2479 {
2480 struct i40e_aq_desc desc;
2481 struct i40e_aqc_macvlan *cmd =
2482 (struct i40e_aqc_macvlan *)&desc.params.raw;
2483 i40e_status status;
2484 u16 buf_size;
2485 int i;
2486
2487 if (count == 0 || !mv_list || !hw)
2488 return I40E_ERR_PARAM;
2489
2490 buf_size = count * sizeof(*mv_list);
2491
2492 /* prep the rest of the request */
2493 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2494 cmd->num_addresses = cpu_to_le16(count);
2495 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2496 cmd->seid[1] = 0;
2497 cmd->seid[2] = 0;
2498
2499 for (i = 0; i < count; i++)
2500 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2501 mv_list[i].flags |=
2502 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2503
2504 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2505 if (buf_size > I40E_AQ_LARGE_BUF)
2506 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2507
2508 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2509 cmd_details);
2510
2511 return status;
2512 }
2513
2514 /**
2515 * i40e_aq_remove_macvlan
2516 * @hw: pointer to the hw struct
2517 * @seid: VSI for the mac address
2518 * @mv_list: list of macvlans to be removed
2519 * @count: length of the list
2520 * @cmd_details: pointer to command details structure or NULL
2521 *
2522 * Remove MAC/VLAN addresses from the HW filtering
2523 **/
2524 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2525 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2526 u16 count, struct i40e_asq_cmd_details *cmd_details)
2527 {
2528 struct i40e_aq_desc desc;
2529 struct i40e_aqc_macvlan *cmd =
2530 (struct i40e_aqc_macvlan *)&desc.params.raw;
2531 i40e_status status;
2532 u16 buf_size;
2533
2534 if (count == 0 || !mv_list || !hw)
2535 return I40E_ERR_PARAM;
2536
2537 buf_size = count * sizeof(*mv_list);
2538
2539 /* prep the rest of the request */
2540 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2541 cmd->num_addresses = cpu_to_le16(count);
2542 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2543 cmd->seid[1] = 0;
2544 cmd->seid[2] = 0;
2545
2546 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2547 if (buf_size > I40E_AQ_LARGE_BUF)
2548 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2549
2550 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2551 cmd_details);
2552
2553 return status;
2554 }
2555
2556 /**
2557 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2558 * @hw: pointer to the hw struct
2559 * @opcode: AQ opcode for add or delete mirror rule
2560 * @sw_seid: Switch SEID (to which rule refers)
2561 * @rule_type: Rule Type (ingress/egress/VLAN)
2562 * @id: Destination VSI SEID or Rule ID
2563 * @count: length of the list
2564 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2565 * @cmd_details: pointer to command details structure or NULL
2566 * @rule_id: Rule ID returned from FW
2567 * @rule_used: Number of rules used in internal switch
2568 * @rule_free: Number of rules free in internal switch
2569 *
2570 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2571 * VEBs/VEPA elements only
2572 **/
2573 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2574 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2575 u16 count, __le16 *mr_list,
2576 struct i40e_asq_cmd_details *cmd_details,
2577 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2578 {
2579 struct i40e_aq_desc desc;
2580 struct i40e_aqc_add_delete_mirror_rule *cmd =
2581 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2582 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2583 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2584 i40e_status status;
2585 u16 buf_size;
2586
2587 buf_size = count * sizeof(*mr_list);
2588
2589 /* prep the rest of the request */
2590 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2591 cmd->seid = cpu_to_le16(sw_seid);
2592 cmd->rule_type = cpu_to_le16(rule_type &
2593 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2594 cmd->num_entries = cpu_to_le16(count);
2595 /* Dest VSI for add, rule_id for delete */
2596 cmd->destination = cpu_to_le16(id);
2597 if (mr_list) {
2598 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2599 I40E_AQ_FLAG_RD));
2600 if (buf_size > I40E_AQ_LARGE_BUF)
2601 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2602 }
2603
2604 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2605 cmd_details);
2606 if (!status ||
2607 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2608 if (rule_id)
2609 *rule_id = le16_to_cpu(resp->rule_id);
2610 if (rules_used)
2611 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2612 if (rules_free)
2613 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2614 }
2615 return status;
2616 }
2617
2618 /**
2619 * i40e_aq_add_mirrorrule - add a mirror rule
2620 * @hw: pointer to the hw struct
2621 * @sw_seid: Switch SEID (to which rule refers)
2622 * @rule_type: Rule Type (ingress/egress/VLAN)
2623 * @dest_vsi: SEID of VSI to which packets will be mirrored
2624 * @count: length of the list
2625 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2626 * @cmd_details: pointer to command details structure or NULL
2627 * @rule_id: Rule ID returned from FW
2628 * @rule_used: Number of rules used in internal switch
2629 * @rule_free: Number of rules free in internal switch
2630 *
2631 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2632 **/
2633 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2634 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2635 struct i40e_asq_cmd_details *cmd_details,
2636 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2637 {
2638 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2639 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2640 if (count == 0 || !mr_list)
2641 return I40E_ERR_PARAM;
2642 }
2643
2644 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2645 rule_type, dest_vsi, count, mr_list,
2646 cmd_details, rule_id, rules_used, rules_free);
2647 }
2648
2649 /**
2650 * i40e_aq_delete_mirrorrule - delete a mirror rule
2651 * @hw: pointer to the hw struct
2652 * @sw_seid: Switch SEID (to which rule refers)
2653 * @rule_type: Rule Type (ingress/egress/VLAN)
2654 * @count: length of the list
2655 * @rule_id: Rule ID that is returned in the receive desc as part of
2656 * add_mirrorrule.
2657 * @mr_list: list of mirrored VLAN IDs to be removed
2658 * @cmd_details: pointer to command details structure or NULL
2659 * @rule_used: Number of rules used in internal switch
2660 * @rule_free: Number of rules free in internal switch
2661 *
2662 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2663 **/
2664 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2665 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2666 struct i40e_asq_cmd_details *cmd_details,
2667 u16 *rules_used, u16 *rules_free)
2668 {
2669 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2670 if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2671 if (!rule_id)
2672 return I40E_ERR_PARAM;
2673 } else {
2674 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2675 * mirroring. For other rule_type, count and rule_type should
2676 * not matter.
2677 */
2678 if (count == 0 || !mr_list)
2679 return I40E_ERR_PARAM;
2680 }
2681
2682 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2683 rule_type, rule_id, count, mr_list,
2684 cmd_details, NULL, rules_used, rules_free);
2685 }
2686
2687 /**
2688 * i40e_aq_send_msg_to_vf
2689 * @hw: pointer to the hardware structure
2690 * @vfid: VF id to send msg
2691 * @v_opcode: opcodes for VF-PF communication
2692 * @v_retval: return error code
2693 * @msg: pointer to the msg buffer
2694 * @msglen: msg length
2695 * @cmd_details: pointer to command details
2696 *
2697 * send msg to vf
2698 **/
2699 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2700 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2701 struct i40e_asq_cmd_details *cmd_details)
2702 {
2703 struct i40e_aq_desc desc;
2704 struct i40e_aqc_pf_vf_message *cmd =
2705 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2706 i40e_status status;
2707
2708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2709 cmd->id = cpu_to_le32(vfid);
2710 desc.cookie_high = cpu_to_le32(v_opcode);
2711 desc.cookie_low = cpu_to_le32(v_retval);
2712 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2713 if (msglen) {
2714 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2715 I40E_AQ_FLAG_RD));
2716 if (msglen > I40E_AQ_LARGE_BUF)
2717 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2718 desc.datalen = cpu_to_le16(msglen);
2719 }
2720 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2721
2722 return status;
2723 }
2724
2725 /**
2726 * i40e_aq_debug_read_register
2727 * @hw: pointer to the hw struct
2728 * @reg_addr: register address
2729 * @reg_val: register value
2730 * @cmd_details: pointer to command details structure or NULL
2731 *
2732 * Read the register using the admin queue commands
2733 **/
2734 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2735 u32 reg_addr, u64 *reg_val,
2736 struct i40e_asq_cmd_details *cmd_details)
2737 {
2738 struct i40e_aq_desc desc;
2739 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2740 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2741 i40e_status status;
2742
2743 if (reg_val == NULL)
2744 return I40E_ERR_PARAM;
2745
2746 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2747
2748 cmd_resp->address = cpu_to_le32(reg_addr);
2749
2750 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2751
2752 if (!status) {
2753 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2754 (u64)le32_to_cpu(cmd_resp->value_low);
2755 }
2756
2757 return status;
2758 }
2759
2760 /**
2761 * i40e_aq_debug_write_register
2762 * @hw: pointer to the hw struct
2763 * @reg_addr: register address
2764 * @reg_val: register value
2765 * @cmd_details: pointer to command details structure or NULL
2766 *
2767 * Write to a register using the admin queue commands
2768 **/
2769 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2770 u32 reg_addr, u64 reg_val,
2771 struct i40e_asq_cmd_details *cmd_details)
2772 {
2773 struct i40e_aq_desc desc;
2774 struct i40e_aqc_debug_reg_read_write *cmd =
2775 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2776 i40e_status status;
2777
2778 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2779
2780 cmd->address = cpu_to_le32(reg_addr);
2781 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2782 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2783
2784 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2785
2786 return status;
2787 }
2788
2789 /**
2790 * i40e_aq_set_hmc_resource_profile
2791 * @hw: pointer to the hw struct
2792 * @profile: type of profile the HMC is to be set as
2793 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2794 * @cmd_details: pointer to command details structure or NULL
2795 *
2796 * set the HMC profile of the device.
2797 **/
2798 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2799 enum i40e_aq_hmc_profile profile,
2800 u8 pe_vf_enabled_count,
2801 struct i40e_asq_cmd_details *cmd_details)
2802 {
2803 struct i40e_aq_desc desc;
2804 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2805 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2806 i40e_status status;
2807
2808 i40e_fill_default_direct_cmd_desc(&desc,
2809 i40e_aqc_opc_set_hmc_resource_profile);
2810
2811 cmd->pm_profile = (u8)profile;
2812 cmd->pe_vf_enabled = pe_vf_enabled_count;
2813
2814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2815
2816 return status;
2817 }
2818
2819 /**
2820 * i40e_aq_request_resource
2821 * @hw: pointer to the hw struct
2822 * @resource: resource id
2823 * @access: access type
2824 * @sdp_number: resource number
2825 * @timeout: the maximum time in ms that the driver may hold the resource
2826 * @cmd_details: pointer to command details structure or NULL
2827 *
2828 * requests common resource using the admin queue commands
2829 **/
2830 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2831 enum i40e_aq_resources_ids resource,
2832 enum i40e_aq_resource_access_type access,
2833 u8 sdp_number, u64 *timeout,
2834 struct i40e_asq_cmd_details *cmd_details)
2835 {
2836 struct i40e_aq_desc desc;
2837 struct i40e_aqc_request_resource *cmd_resp =
2838 (struct i40e_aqc_request_resource *)&desc.params.raw;
2839 i40e_status status;
2840
2841 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2842
2843 cmd_resp->resource_id = cpu_to_le16(resource);
2844 cmd_resp->access_type = cpu_to_le16(access);
2845 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2846
2847 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2848 /* The completion specifies the maximum time in ms that the driver
2849 * may hold the resource in the Timeout field.
2850 * If the resource is held by someone else, the command completes with
2851 * busy return value and the timeout field indicates the maximum time
2852 * the current owner of the resource has to free it.
2853 */
2854 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2855 *timeout = le32_to_cpu(cmd_resp->timeout);
2856
2857 return status;
2858 }
2859
2860 /**
2861 * i40e_aq_release_resource
2862 * @hw: pointer to the hw struct
2863 * @resource: resource id
2864 * @sdp_number: resource number
2865 * @cmd_details: pointer to command details structure or NULL
2866 *
2867 * release common resource using the admin queue commands
2868 **/
2869 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2870 enum i40e_aq_resources_ids resource,
2871 u8 sdp_number,
2872 struct i40e_asq_cmd_details *cmd_details)
2873 {
2874 struct i40e_aq_desc desc;
2875 struct i40e_aqc_request_resource *cmd =
2876 (struct i40e_aqc_request_resource *)&desc.params.raw;
2877 i40e_status status;
2878
2879 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2880
2881 cmd->resource_id = cpu_to_le16(resource);
2882 cmd->resource_number = cpu_to_le32(sdp_number);
2883
2884 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2885
2886 return status;
2887 }
2888
2889 /**
2890 * i40e_aq_read_nvm
2891 * @hw: pointer to the hw struct
2892 * @module_pointer: module pointer location in words from the NVM beginning
2893 * @offset: byte offset from the module beginning
2894 * @length: length of the section to be read (in bytes from the offset)
2895 * @data: command buffer (size [bytes] = length)
2896 * @last_command: tells if this is the last command in a series
2897 * @cmd_details: pointer to command details structure or NULL
2898 *
2899 * Read the NVM using the admin queue commands
2900 **/
2901 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2902 u32 offset, u16 length, void *data,
2903 bool last_command,
2904 struct i40e_asq_cmd_details *cmd_details)
2905 {
2906 struct i40e_aq_desc desc;
2907 struct i40e_aqc_nvm_update *cmd =
2908 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2909 i40e_status status;
2910
2911 /* In offset the highest byte must be zeroed. */
2912 if (offset & 0xFF000000) {
2913 status = I40E_ERR_PARAM;
2914 goto i40e_aq_read_nvm_exit;
2915 }
2916
2917 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2918
2919 /* If this is the last command in a series, set the proper flag. */
2920 if (last_command)
2921 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2922 cmd->module_pointer = module_pointer;
2923 cmd->offset = cpu_to_le32(offset);
2924 cmd->length = cpu_to_le16(length);
2925
2926 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2927 if (length > I40E_AQ_LARGE_BUF)
2928 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2929
2930 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2931
2932 i40e_aq_read_nvm_exit:
2933 return status;
2934 }
2935
2936 /**
2937 * i40e_aq_erase_nvm
2938 * @hw: pointer to the hw struct
2939 * @module_pointer: module pointer location in words from the NVM beginning
2940 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2941 * @length: length of the section to be erased (expressed in 4 KB)
2942 * @last_command: tells if this is the last command in a series
2943 * @cmd_details: pointer to command details structure or NULL
2944 *
2945 * Erase the NVM sector using the admin queue commands
2946 **/
2947 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2948 u32 offset, u16 length, bool last_command,
2949 struct i40e_asq_cmd_details *cmd_details)
2950 {
2951 struct i40e_aq_desc desc;
2952 struct i40e_aqc_nvm_update *cmd =
2953 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2954 i40e_status status;
2955
2956 /* In offset the highest byte must be zeroed. */
2957 if (offset & 0xFF000000) {
2958 status = I40E_ERR_PARAM;
2959 goto i40e_aq_erase_nvm_exit;
2960 }
2961
2962 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2963
2964 /* If this is the last command in a series, set the proper flag. */
2965 if (last_command)
2966 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2967 cmd->module_pointer = module_pointer;
2968 cmd->offset = cpu_to_le32(offset);
2969 cmd->length = cpu_to_le16(length);
2970
2971 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2972
2973 i40e_aq_erase_nvm_exit:
2974 return status;
2975 }
2976
2977 /**
2978 * i40e_parse_discover_capabilities
2979 * @hw: pointer to the hw struct
2980 * @buff: pointer to a buffer containing device/function capability records
2981 * @cap_count: number of capability records in the list
2982 * @list_type_opc: type of capabilities list to parse
2983 *
2984 * Parse the device/function capabilities list.
2985 **/
2986 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2987 u32 cap_count,
2988 enum i40e_admin_queue_opc list_type_opc)
2989 {
2990 struct i40e_aqc_list_capabilities_element_resp *cap;
2991 u32 valid_functions, num_functions;
2992 u32 number, logical_id, phys_id;
2993 struct i40e_hw_capabilities *p;
2994 u8 major_rev;
2995 u32 i = 0;
2996 u16 id;
2997
2998 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2999
3000 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3001 p = &hw->dev_caps;
3002 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3003 p = &hw->func_caps;
3004 else
3005 return;
3006
3007 for (i = 0; i < cap_count; i++, cap++) {
3008 id = le16_to_cpu(cap->id);
3009 number = le32_to_cpu(cap->number);
3010 logical_id = le32_to_cpu(cap->logical_id);
3011 phys_id = le32_to_cpu(cap->phys_id);
3012 major_rev = cap->major_rev;
3013
3014 switch (id) {
3015 case I40E_AQ_CAP_ID_SWITCH_MODE:
3016 p->switch_mode = number;
3017 break;
3018 case I40E_AQ_CAP_ID_MNG_MODE:
3019 p->management_mode = number;
3020 break;
3021 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3022 p->npar_enable = number;
3023 break;
3024 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3025 p->os2bmc = number;
3026 break;
3027 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3028 p->valid_functions = number;
3029 break;
3030 case I40E_AQ_CAP_ID_SRIOV:
3031 if (number == 1)
3032 p->sr_iov_1_1 = true;
3033 break;
3034 case I40E_AQ_CAP_ID_VF:
3035 p->num_vfs = number;
3036 p->vf_base_id = logical_id;
3037 break;
3038 case I40E_AQ_CAP_ID_VMDQ:
3039 if (number == 1)
3040 p->vmdq = true;
3041 break;
3042 case I40E_AQ_CAP_ID_8021QBG:
3043 if (number == 1)
3044 p->evb_802_1_qbg = true;
3045 break;
3046 case I40E_AQ_CAP_ID_8021QBR:
3047 if (number == 1)
3048 p->evb_802_1_qbh = true;
3049 break;
3050 case I40E_AQ_CAP_ID_VSI:
3051 p->num_vsis = number;
3052 break;
3053 case I40E_AQ_CAP_ID_DCB:
3054 if (number == 1) {
3055 p->dcb = true;
3056 p->enabled_tcmap = logical_id;
3057 p->maxtc = phys_id;
3058 }
3059 break;
3060 case I40E_AQ_CAP_ID_FCOE:
3061 if (number == 1)
3062 p->fcoe = true;
3063 break;
3064 case I40E_AQ_CAP_ID_ISCSI:
3065 if (number == 1)
3066 p->iscsi = true;
3067 break;
3068 case I40E_AQ_CAP_ID_RSS:
3069 p->rss = true;
3070 p->rss_table_size = number;
3071 p->rss_table_entry_width = logical_id;
3072 break;
3073 case I40E_AQ_CAP_ID_RXQ:
3074 p->num_rx_qp = number;
3075 p->base_queue = phys_id;
3076 break;
3077 case I40E_AQ_CAP_ID_TXQ:
3078 p->num_tx_qp = number;
3079 p->base_queue = phys_id;
3080 break;
3081 case I40E_AQ_CAP_ID_MSIX:
3082 p->num_msix_vectors = number;
3083 i40e_debug(hw, I40E_DEBUG_INIT,
3084 "HW Capability: MSIX vector count = %d\n",
3085 p->num_msix_vectors);
3086 break;
3087 case I40E_AQ_CAP_ID_VF_MSIX:
3088 p->num_msix_vectors_vf = number;
3089 break;
3090 case I40E_AQ_CAP_ID_FLEX10:
3091 if (major_rev == 1) {
3092 if (number == 1) {
3093 p->flex10_enable = true;
3094 p->flex10_capable = true;
3095 }
3096 } else {
3097 /* Capability revision >= 2 */
3098 if (number & 1)
3099 p->flex10_enable = true;
3100 if (number & 2)
3101 p->flex10_capable = true;
3102 }
3103 p->flex10_mode = logical_id;
3104 p->flex10_status = phys_id;
3105 break;
3106 case I40E_AQ_CAP_ID_CEM:
3107 if (number == 1)
3108 p->mgmt_cem = true;
3109 break;
3110 case I40E_AQ_CAP_ID_IWARP:
3111 if (number == 1)
3112 p->iwarp = true;
3113 break;
3114 case I40E_AQ_CAP_ID_LED:
3115 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3116 p->led[phys_id] = true;
3117 break;
3118 case I40E_AQ_CAP_ID_SDP:
3119 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3120 p->sdp[phys_id] = true;
3121 break;
3122 case I40E_AQ_CAP_ID_MDIO:
3123 if (number == 1) {
3124 p->mdio_port_num = phys_id;
3125 p->mdio_port_mode = logical_id;
3126 }
3127 break;
3128 case I40E_AQ_CAP_ID_1588:
3129 if (number == 1)
3130 p->ieee_1588 = true;
3131 break;
3132 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3133 p->fd = true;
3134 p->fd_filters_guaranteed = number;
3135 p->fd_filters_best_effort = logical_id;
3136 break;
3137 case I40E_AQ_CAP_ID_WSR_PROT:
3138 p->wr_csr_prot = (u64)number;
3139 p->wr_csr_prot |= (u64)logical_id << 32;
3140 break;
3141 default:
3142 break;
3143 }
3144 }
3145
3146 if (p->fcoe)
3147 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3148
3149 /* Software override ensuring FCoE is disabled if npar or mfp
3150 * mode because it is not supported in these modes.
3151 */
3152 if (p->npar_enable || p->flex10_enable)
3153 p->fcoe = false;
3154
3155 /* count the enabled ports (aka the "not disabled" ports) */
3156 hw->num_ports = 0;
3157 for (i = 0; i < 4; i++) {
3158 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3159 u64 port_cfg = 0;
3160
3161 /* use AQ read to get the physical register offset instead
3162 * of the port relative offset
3163 */
3164 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3165 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3166 hw->num_ports++;
3167 }
3168
3169 valid_functions = p->valid_functions;
3170 num_functions = 0;
3171 while (valid_functions) {
3172 if (valid_functions & 1)
3173 num_functions++;
3174 valid_functions >>= 1;
3175 }
3176
3177 /* partition id is 1-based, and functions are evenly spread
3178 * across the ports as partitions
3179 */
3180 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3181 hw->num_partitions = num_functions / hw->num_ports;
3182
3183 /* additional HW specific goodies that might
3184 * someday be HW version specific
3185 */
3186 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3187 }
3188
3189 /**
3190 * i40e_aq_discover_capabilities
3191 * @hw: pointer to the hw struct
3192 * @buff: a virtual buffer to hold the capabilities
3193 * @buff_size: Size of the virtual buffer
3194 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3195 * @list_type_opc: capabilities type to discover - pass in the command opcode
3196 * @cmd_details: pointer to command details structure or NULL
3197 *
3198 * Get the device capabilities descriptions from the firmware
3199 **/
3200 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3201 void *buff, u16 buff_size, u16 *data_size,
3202 enum i40e_admin_queue_opc list_type_opc,
3203 struct i40e_asq_cmd_details *cmd_details)
3204 {
3205 struct i40e_aqc_list_capabilites *cmd;
3206 struct i40e_aq_desc desc;
3207 i40e_status status = 0;
3208
3209 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3210
3211 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3212 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3213 status = I40E_ERR_PARAM;
3214 goto exit;
3215 }
3216
3217 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3218
3219 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3220 if (buff_size > I40E_AQ_LARGE_BUF)
3221 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3222
3223 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3224 *data_size = le16_to_cpu(desc.datalen);
3225
3226 if (status)
3227 goto exit;
3228
3229 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3230 list_type_opc);
3231
3232 exit:
3233 return status;
3234 }
3235
3236 /**
3237 * i40e_aq_update_nvm
3238 * @hw: pointer to the hw struct
3239 * @module_pointer: module pointer location in words from the NVM beginning
3240 * @offset: byte offset from the module beginning
3241 * @length: length of the section to be written (in bytes from the offset)
3242 * @data: command buffer (size [bytes] = length)
3243 * @last_command: tells if this is the last command in a series
3244 * @cmd_details: pointer to command details structure or NULL
3245 *
3246 * Update the NVM using the admin queue commands
3247 **/
3248 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3249 u32 offset, u16 length, void *data,
3250 bool last_command,
3251 struct i40e_asq_cmd_details *cmd_details)
3252 {
3253 struct i40e_aq_desc desc;
3254 struct i40e_aqc_nvm_update *cmd =
3255 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3256 i40e_status status;
3257
3258 /* In offset the highest byte must be zeroed. */
3259 if (offset & 0xFF000000) {
3260 status = I40E_ERR_PARAM;
3261 goto i40e_aq_update_nvm_exit;
3262 }
3263
3264 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3265
3266 /* If this is the last command in a series, set the proper flag. */
3267 if (last_command)
3268 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3269 cmd->module_pointer = module_pointer;
3270 cmd->offset = cpu_to_le32(offset);
3271 cmd->length = cpu_to_le16(length);
3272
3273 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3274 if (length > I40E_AQ_LARGE_BUF)
3275 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3276
3277 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3278
3279 i40e_aq_update_nvm_exit:
3280 return status;
3281 }
3282
3283 /**
3284 * i40e_aq_get_lldp_mib
3285 * @hw: pointer to the hw struct
3286 * @bridge_type: type of bridge requested
3287 * @mib_type: Local, Remote or both Local and Remote MIBs
3288 * @buff: pointer to a user supplied buffer to store the MIB block
3289 * @buff_size: size of the buffer (in bytes)
3290 * @local_len : length of the returned Local LLDP MIB
3291 * @remote_len: length of the returned Remote LLDP MIB
3292 * @cmd_details: pointer to command details structure or NULL
3293 *
3294 * Requests the complete LLDP MIB (entire packet).
3295 **/
3296 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3297 u8 mib_type, void *buff, u16 buff_size,
3298 u16 *local_len, u16 *remote_len,
3299 struct i40e_asq_cmd_details *cmd_details)
3300 {
3301 struct i40e_aq_desc desc;
3302 struct i40e_aqc_lldp_get_mib *cmd =
3303 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3304 struct i40e_aqc_lldp_get_mib *resp =
3305 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3306 i40e_status status;
3307
3308 if (buff_size == 0 || !buff)
3309 return I40E_ERR_PARAM;
3310
3311 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3312 /* Indirect Command */
3313 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3314
3315 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3316 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3317 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3318
3319 desc.datalen = cpu_to_le16(buff_size);
3320
3321 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3322 if (buff_size > I40E_AQ_LARGE_BUF)
3323 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3324
3325 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3326 if (!status) {
3327 if (local_len != NULL)
3328 *local_len = le16_to_cpu(resp->local_len);
3329 if (remote_len != NULL)
3330 *remote_len = le16_to_cpu(resp->remote_len);
3331 }
3332
3333 return status;
3334 }
3335
3336 /**
3337 * i40e_aq_cfg_lldp_mib_change_event
3338 * @hw: pointer to the hw struct
3339 * @enable_update: Enable or Disable event posting
3340 * @cmd_details: pointer to command details structure or NULL
3341 *
3342 * Enable or Disable posting of an event on ARQ when LLDP MIB
3343 * associated with the interface changes
3344 **/
3345 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3346 bool enable_update,
3347 struct i40e_asq_cmd_details *cmd_details)
3348 {
3349 struct i40e_aq_desc desc;
3350 struct i40e_aqc_lldp_update_mib *cmd =
3351 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3352 i40e_status status;
3353
3354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3355
3356 if (!enable_update)
3357 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3358
3359 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3360
3361 return status;
3362 }
3363
3364 /**
3365 * i40e_aq_stop_lldp
3366 * @hw: pointer to the hw struct
3367 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3368 * @cmd_details: pointer to command details structure or NULL
3369 *
3370 * Stop or Shutdown the embedded LLDP Agent
3371 **/
3372 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3373 struct i40e_asq_cmd_details *cmd_details)
3374 {
3375 struct i40e_aq_desc desc;
3376 struct i40e_aqc_lldp_stop *cmd =
3377 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3378 i40e_status status;
3379
3380 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3381
3382 if (shutdown_agent)
3383 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3384
3385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3386
3387 return status;
3388 }
3389
3390 /**
3391 * i40e_aq_start_lldp
3392 * @hw: pointer to the hw struct
3393 * @cmd_details: pointer to command details structure or NULL
3394 *
3395 * Start the embedded LLDP Agent on all ports.
3396 **/
3397 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3398 struct i40e_asq_cmd_details *cmd_details)
3399 {
3400 struct i40e_aq_desc desc;
3401 struct i40e_aqc_lldp_start *cmd =
3402 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3403 i40e_status status;
3404
3405 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3406
3407 cmd->command = I40E_AQ_LLDP_AGENT_START;
3408
3409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3410
3411 return status;
3412 }
3413
3414 /**
3415 * i40e_aq_get_cee_dcb_config
3416 * @hw: pointer to the hw struct
3417 * @buff: response buffer that stores CEE operational configuration
3418 * @buff_size: size of the buffer passed
3419 * @cmd_details: pointer to command details structure or NULL
3420 *
3421 * Get CEE DCBX mode operational configuration from firmware
3422 **/
3423 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3424 void *buff, u16 buff_size,
3425 struct i40e_asq_cmd_details *cmd_details)
3426 {
3427 struct i40e_aq_desc desc;
3428 i40e_status status;
3429
3430 if (buff_size == 0 || !buff)
3431 return I40E_ERR_PARAM;
3432
3433 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3434
3435 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3436 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3437 cmd_details);
3438
3439 return status;
3440 }
3441
3442 /**
3443 * i40e_aq_add_udp_tunnel
3444 * @hw: pointer to the hw struct
3445 * @udp_port: the UDP port to add
3446 * @header_len: length of the tunneling header length in DWords
3447 * @protocol_index: protocol index type
3448 * @filter_index: pointer to filter index
3449 * @cmd_details: pointer to command details structure or NULL
3450 **/
3451 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3452 u16 udp_port, u8 protocol_index,
3453 u8 *filter_index,
3454 struct i40e_asq_cmd_details *cmd_details)
3455 {
3456 struct i40e_aq_desc desc;
3457 struct i40e_aqc_add_udp_tunnel *cmd =
3458 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3459 struct i40e_aqc_del_udp_tunnel_completion *resp =
3460 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3461 i40e_status status;
3462
3463 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3464
3465 cmd->udp_port = cpu_to_le16(udp_port);
3466 cmd->protocol_type = protocol_index;
3467
3468 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3469
3470 if (!status && filter_index)
3471 *filter_index = resp->index;
3472
3473 return status;
3474 }
3475
3476 /**
3477 * i40e_aq_del_udp_tunnel
3478 * @hw: pointer to the hw struct
3479 * @index: filter index
3480 * @cmd_details: pointer to command details structure or NULL
3481 **/
3482 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3483 struct i40e_asq_cmd_details *cmd_details)
3484 {
3485 struct i40e_aq_desc desc;
3486 struct i40e_aqc_remove_udp_tunnel *cmd =
3487 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3488 i40e_status status;
3489
3490 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3491
3492 cmd->index = index;
3493
3494 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3495
3496 return status;
3497 }
3498
3499 /**
3500 * i40e_aq_delete_element - Delete switch element
3501 * @hw: pointer to the hw struct
3502 * @seid: the SEID to delete from the switch
3503 * @cmd_details: pointer to command details structure or NULL
3504 *
3505 * This deletes a switch element from the switch.
3506 **/
3507 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3508 struct i40e_asq_cmd_details *cmd_details)
3509 {
3510 struct i40e_aq_desc desc;
3511 struct i40e_aqc_switch_seid *cmd =
3512 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3513 i40e_status status;
3514
3515 if (seid == 0)
3516 return I40E_ERR_PARAM;
3517
3518 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3519
3520 cmd->seid = cpu_to_le16(seid);
3521
3522 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3523
3524 return status;
3525 }
3526
3527 /**
3528 * i40e_aq_dcb_updated - DCB Updated Command
3529 * @hw: pointer to the hw struct
3530 * @cmd_details: pointer to command details structure or NULL
3531 *
3532 * EMP will return when the shared RPB settings have been
3533 * recomputed and modified. The retval field in the descriptor
3534 * will be set to 0 when RPB is modified.
3535 **/
3536 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3537 struct i40e_asq_cmd_details *cmd_details)
3538 {
3539 struct i40e_aq_desc desc;
3540 i40e_status status;
3541
3542 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3543
3544 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3545
3546 return status;
3547 }
3548
3549 /**
3550 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3551 * @hw: pointer to the hw struct
3552 * @seid: seid for the physical port/switching component/vsi
3553 * @buff: Indirect buffer to hold data parameters and response
3554 * @buff_size: Indirect buffer size
3555 * @opcode: Tx scheduler AQ command opcode
3556 * @cmd_details: pointer to command details structure or NULL
3557 *
3558 * Generic command handler for Tx scheduler AQ commands
3559 **/
3560 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3561 void *buff, u16 buff_size,
3562 enum i40e_admin_queue_opc opcode,
3563 struct i40e_asq_cmd_details *cmd_details)
3564 {
3565 struct i40e_aq_desc desc;
3566 struct i40e_aqc_tx_sched_ind *cmd =
3567 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3568 i40e_status status;
3569 bool cmd_param_flag = false;
3570
3571 switch (opcode) {
3572 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3573 case i40e_aqc_opc_configure_vsi_tc_bw:
3574 case i40e_aqc_opc_enable_switching_comp_ets:
3575 case i40e_aqc_opc_modify_switching_comp_ets:
3576 case i40e_aqc_opc_disable_switching_comp_ets:
3577 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3578 case i40e_aqc_opc_configure_switching_comp_bw_config:
3579 cmd_param_flag = true;
3580 break;
3581 case i40e_aqc_opc_query_vsi_bw_config:
3582 case i40e_aqc_opc_query_vsi_ets_sla_config:
3583 case i40e_aqc_opc_query_switching_comp_ets_config:
3584 case i40e_aqc_opc_query_port_ets_config:
3585 case i40e_aqc_opc_query_switching_comp_bw_config:
3586 cmd_param_flag = false;
3587 break;
3588 default:
3589 return I40E_ERR_PARAM;
3590 }
3591
3592 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3593
3594 /* Indirect command */
3595 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3596 if (cmd_param_flag)
3597 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3598 if (buff_size > I40E_AQ_LARGE_BUF)
3599 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3600
3601 desc.datalen = cpu_to_le16(buff_size);
3602
3603 cmd->vsi_seid = cpu_to_le16(seid);
3604
3605 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3606
3607 return status;
3608 }
3609
3610 /**
3611 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3612 * @hw: pointer to the hw struct
3613 * @seid: VSI seid
3614 * @credit: BW limit credits (0 = disabled)
3615 * @max_credit: Max BW limit credits
3616 * @cmd_details: pointer to command details structure or NULL
3617 **/
3618 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3619 u16 seid, u16 credit, u8 max_credit,
3620 struct i40e_asq_cmd_details *cmd_details)
3621 {
3622 struct i40e_aq_desc desc;
3623 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3624 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3625 i40e_status status;
3626
3627 i40e_fill_default_direct_cmd_desc(&desc,
3628 i40e_aqc_opc_configure_vsi_bw_limit);
3629
3630 cmd->vsi_seid = cpu_to_le16(seid);
3631 cmd->credit = cpu_to_le16(credit);
3632 cmd->max_credit = max_credit;
3633
3634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3635
3636 return status;
3637 }
3638
3639 /**
3640 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3641 * @hw: pointer to the hw struct
3642 * @seid: VSI seid
3643 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3644 * @cmd_details: pointer to command details structure or NULL
3645 **/
3646 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3647 u16 seid,
3648 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3649 struct i40e_asq_cmd_details *cmd_details)
3650 {
3651 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3652 i40e_aqc_opc_configure_vsi_tc_bw,
3653 cmd_details);
3654 }
3655
3656 /**
3657 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3658 * @hw: pointer to the hw struct
3659 * @seid: seid of the switching component connected to Physical Port
3660 * @ets_data: Buffer holding ETS parameters
3661 * @cmd_details: pointer to command details structure or NULL
3662 **/
3663 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3664 u16 seid,
3665 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3666 enum i40e_admin_queue_opc opcode,
3667 struct i40e_asq_cmd_details *cmd_details)
3668 {
3669 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3670 sizeof(*ets_data), opcode, cmd_details);
3671 }
3672
3673 /**
3674 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3675 * @hw: pointer to the hw struct
3676 * @seid: seid of the switching component
3677 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3678 * @cmd_details: pointer to command details structure or NULL
3679 **/
3680 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3681 u16 seid,
3682 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3683 struct i40e_asq_cmd_details *cmd_details)
3684 {
3685 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3686 i40e_aqc_opc_configure_switching_comp_bw_config,
3687 cmd_details);
3688 }
3689
3690 /**
3691 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3692 * @hw: pointer to the hw struct
3693 * @seid: seid of the VSI
3694 * @bw_data: Buffer to hold VSI BW configuration
3695 * @cmd_details: pointer to command details structure or NULL
3696 **/
3697 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3698 u16 seid,
3699 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3700 struct i40e_asq_cmd_details *cmd_details)
3701 {
3702 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3703 i40e_aqc_opc_query_vsi_bw_config,
3704 cmd_details);
3705 }
3706
3707 /**
3708 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3709 * @hw: pointer to the hw struct
3710 * @seid: seid of the VSI
3711 * @bw_data: Buffer to hold VSI BW configuration per TC
3712 * @cmd_details: pointer to command details structure or NULL
3713 **/
3714 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3715 u16 seid,
3716 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3717 struct i40e_asq_cmd_details *cmd_details)
3718 {
3719 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3720 i40e_aqc_opc_query_vsi_ets_sla_config,
3721 cmd_details);
3722 }
3723
3724 /**
3725 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3726 * @hw: pointer to the hw struct
3727 * @seid: seid of the switching component
3728 * @bw_data: Buffer to hold switching component's per TC BW config
3729 * @cmd_details: pointer to command details structure or NULL
3730 **/
3731 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3732 u16 seid,
3733 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3734 struct i40e_asq_cmd_details *cmd_details)
3735 {
3736 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3737 i40e_aqc_opc_query_switching_comp_ets_config,
3738 cmd_details);
3739 }
3740
3741 /**
3742 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3743 * @hw: pointer to the hw struct
3744 * @seid: seid of the VSI or switching component connected to Physical Port
3745 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3746 * @cmd_details: pointer to command details structure or NULL
3747 **/
3748 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3749 u16 seid,
3750 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3751 struct i40e_asq_cmd_details *cmd_details)
3752 {
3753 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3754 i40e_aqc_opc_query_port_ets_config,
3755 cmd_details);
3756 }
3757
3758 /**
3759 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3760 * @hw: pointer to the hw struct
3761 * @seid: seid of the switching component
3762 * @bw_data: Buffer to hold switching component's BW configuration
3763 * @cmd_details: pointer to command details structure or NULL
3764 **/
3765 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3766 u16 seid,
3767 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3768 struct i40e_asq_cmd_details *cmd_details)
3769 {
3770 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3771 i40e_aqc_opc_query_switching_comp_bw_config,
3772 cmd_details);
3773 }
3774
3775 /**
3776 * i40e_validate_filter_settings
3777 * @hw: pointer to the hardware structure
3778 * @settings: Filter control settings
3779 *
3780 * Check and validate the filter control settings passed.
3781 * The function checks for the valid filter/context sizes being
3782 * passed for FCoE and PE.
3783 *
3784 * Returns 0 if the values passed are valid and within
3785 * range else returns an error.
3786 **/
3787 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3788 struct i40e_filter_control_settings *settings)
3789 {
3790 u32 fcoe_cntx_size, fcoe_filt_size;
3791 u32 pe_cntx_size, pe_filt_size;
3792 u32 fcoe_fmax;
3793 u32 val;
3794
3795 /* Validate FCoE settings passed */
3796 switch (settings->fcoe_filt_num) {
3797 case I40E_HASH_FILTER_SIZE_1K:
3798 case I40E_HASH_FILTER_SIZE_2K:
3799 case I40E_HASH_FILTER_SIZE_4K:
3800 case I40E_HASH_FILTER_SIZE_8K:
3801 case I40E_HASH_FILTER_SIZE_16K:
3802 case I40E_HASH_FILTER_SIZE_32K:
3803 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3804 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3805 break;
3806 default:
3807 return I40E_ERR_PARAM;
3808 }
3809
3810 switch (settings->fcoe_cntx_num) {
3811 case I40E_DMA_CNTX_SIZE_512:
3812 case I40E_DMA_CNTX_SIZE_1K:
3813 case I40E_DMA_CNTX_SIZE_2K:
3814 case I40E_DMA_CNTX_SIZE_4K:
3815 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3816 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3817 break;
3818 default:
3819 return I40E_ERR_PARAM;
3820 }
3821
3822 /* Validate PE settings passed */
3823 switch (settings->pe_filt_num) {
3824 case I40E_HASH_FILTER_SIZE_1K:
3825 case I40E_HASH_FILTER_SIZE_2K:
3826 case I40E_HASH_FILTER_SIZE_4K:
3827 case I40E_HASH_FILTER_SIZE_8K:
3828 case I40E_HASH_FILTER_SIZE_16K:
3829 case I40E_HASH_FILTER_SIZE_32K:
3830 case I40E_HASH_FILTER_SIZE_64K:
3831 case I40E_HASH_FILTER_SIZE_128K:
3832 case I40E_HASH_FILTER_SIZE_256K:
3833 case I40E_HASH_FILTER_SIZE_512K:
3834 case I40E_HASH_FILTER_SIZE_1M:
3835 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3836 pe_filt_size <<= (u32)settings->pe_filt_num;
3837 break;
3838 default:
3839 return I40E_ERR_PARAM;
3840 }
3841
3842 switch (settings->pe_cntx_num) {
3843 case I40E_DMA_CNTX_SIZE_512:
3844 case I40E_DMA_CNTX_SIZE_1K:
3845 case I40E_DMA_CNTX_SIZE_2K:
3846 case I40E_DMA_CNTX_SIZE_4K:
3847 case I40E_DMA_CNTX_SIZE_8K:
3848 case I40E_DMA_CNTX_SIZE_16K:
3849 case I40E_DMA_CNTX_SIZE_32K:
3850 case I40E_DMA_CNTX_SIZE_64K:
3851 case I40E_DMA_CNTX_SIZE_128K:
3852 case I40E_DMA_CNTX_SIZE_256K:
3853 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3854 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3855 break;
3856 default:
3857 return I40E_ERR_PARAM;
3858 }
3859
3860 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3861 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3862 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3863 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3864 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3865 return I40E_ERR_INVALID_SIZE;
3866
3867 return 0;
3868 }
3869
3870 /**
3871 * i40e_set_filter_control
3872 * @hw: pointer to the hardware structure
3873 * @settings: Filter control settings
3874 *
3875 * Set the Queue Filters for PE/FCoE and enable filters required
3876 * for a single PF. It is expected that these settings are programmed
3877 * at the driver initialization time.
3878 **/
3879 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3880 struct i40e_filter_control_settings *settings)
3881 {
3882 i40e_status ret = 0;
3883 u32 hash_lut_size = 0;
3884 u32 val;
3885
3886 if (!settings)
3887 return I40E_ERR_PARAM;
3888
3889 /* Validate the input settings */
3890 ret = i40e_validate_filter_settings(hw, settings);
3891 if (ret)
3892 return ret;
3893
3894 /* Read the PF Queue Filter control register */
3895 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
3896
3897 /* Program required PE hash buckets for the PF */
3898 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3899 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3900 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3901 /* Program required PE contexts for the PF */
3902 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3903 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3904 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3905
3906 /* Program required FCoE hash buckets for the PF */
3907 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3908 val |= ((u32)settings->fcoe_filt_num <<
3909 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3910 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3911 /* Program required FCoE DDP contexts for the PF */
3912 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3913 val |= ((u32)settings->fcoe_cntx_num <<
3914 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3915 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3916
3917 /* Program Hash LUT size for the PF */
3918 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3919 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3920 hash_lut_size = 1;
3921 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3922 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3923
3924 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3925 if (settings->enable_fdir)
3926 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3927 if (settings->enable_ethtype)
3928 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3929 if (settings->enable_macvlan)
3930 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3931
3932 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
3933
3934 return 0;
3935 }
3936
3937 /**
3938 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3939 * @hw: pointer to the hw struct
3940 * @mac_addr: MAC address to use in the filter
3941 * @ethtype: Ethertype to use in the filter
3942 * @flags: Flags that needs to be applied to the filter
3943 * @vsi_seid: seid of the control VSI
3944 * @queue: VSI queue number to send the packet to
3945 * @is_add: Add control packet filter if True else remove
3946 * @stats: Structure to hold information on control filter counts
3947 * @cmd_details: pointer to command details structure or NULL
3948 *
3949 * This command will Add or Remove control packet filter for a control VSI.
3950 * In return it will update the total number of perfect filter count in
3951 * the stats member.
3952 **/
3953 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3954 u8 *mac_addr, u16 ethtype, u16 flags,
3955 u16 vsi_seid, u16 queue, bool is_add,
3956 struct i40e_control_filter_stats *stats,
3957 struct i40e_asq_cmd_details *cmd_details)
3958 {
3959 struct i40e_aq_desc desc;
3960 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3961 (struct i40e_aqc_add_remove_control_packet_filter *)
3962 &desc.params.raw;
3963 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3964 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3965 &desc.params.raw;
3966 i40e_status status;
3967
3968 if (vsi_seid == 0)
3969 return I40E_ERR_PARAM;
3970
3971 if (is_add) {
3972 i40e_fill_default_direct_cmd_desc(&desc,
3973 i40e_aqc_opc_add_control_packet_filter);
3974 cmd->queue = cpu_to_le16(queue);
3975 } else {
3976 i40e_fill_default_direct_cmd_desc(&desc,
3977 i40e_aqc_opc_remove_control_packet_filter);
3978 }
3979
3980 if (mac_addr)
3981 ether_addr_copy(cmd->mac, mac_addr);
3982
3983 cmd->etype = cpu_to_le16(ethtype);
3984 cmd->flags = cpu_to_le16(flags);
3985 cmd->seid = cpu_to_le16(vsi_seid);
3986
3987 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3988
3989 if (!status && stats) {
3990 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3991 stats->etype_used = le16_to_cpu(resp->etype_used);
3992 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3993 stats->etype_free = le16_to_cpu(resp->etype_free);
3994 }
3995
3996 return status;
3997 }
3998
3999 /**
4000 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4001 * @hw: pointer to the hw struct
4002 * @seid: VSI seid to add ethertype filter from
4003 **/
4004 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4005 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4006 u16 seid)
4007 {
4008 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4009 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4010 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4011 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4012 i40e_status status;
4013
4014 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4015 seid, 0, true, NULL,
4016 NULL);
4017 if (status)
4018 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4019 }
4020
4021 /**
4022 * i40e_aq_alternate_read
4023 * @hw: pointer to the hardware structure
4024 * @reg_addr0: address of first dword to be read
4025 * @reg_val0: pointer for data read from 'reg_addr0'
4026 * @reg_addr1: address of second dword to be read
4027 * @reg_val1: pointer for data read from 'reg_addr1'
4028 *
4029 * Read one or two dwords from alternate structure. Fields are indicated
4030 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4031 * is not passed then only register at 'reg_addr0' is read.
4032 *
4033 **/
4034 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4035 u32 reg_addr0, u32 *reg_val0,
4036 u32 reg_addr1, u32 *reg_val1)
4037 {
4038 struct i40e_aq_desc desc;
4039 struct i40e_aqc_alternate_write *cmd_resp =
4040 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4041 i40e_status status;
4042
4043 if (!reg_val0)
4044 return I40E_ERR_PARAM;
4045
4046 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4047 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4048 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4049
4050 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4051
4052 if (!status) {
4053 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4054
4055 if (reg_val1)
4056 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4057 }
4058
4059 return status;
4060 }
4061
4062 /**
4063 * i40e_aq_resume_port_tx
4064 * @hw: pointer to the hardware structure
4065 * @cmd_details: pointer to command details structure or NULL
4066 *
4067 * Resume port's Tx traffic
4068 **/
4069 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4070 struct i40e_asq_cmd_details *cmd_details)
4071 {
4072 struct i40e_aq_desc desc;
4073 i40e_status status;
4074
4075 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4076
4077 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4078
4079 return status;
4080 }
4081
4082 /**
4083 * i40e_set_pci_config_data - store PCI bus info
4084 * @hw: pointer to hardware structure
4085 * @link_status: the link status word from PCI config space
4086 *
4087 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4088 **/
4089 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4090 {
4091 hw->bus.type = i40e_bus_type_pci_express;
4092
4093 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4094 case PCI_EXP_LNKSTA_NLW_X1:
4095 hw->bus.width = i40e_bus_width_pcie_x1;
4096 break;
4097 case PCI_EXP_LNKSTA_NLW_X2:
4098 hw->bus.width = i40e_bus_width_pcie_x2;
4099 break;
4100 case PCI_EXP_LNKSTA_NLW_X4:
4101 hw->bus.width = i40e_bus_width_pcie_x4;
4102 break;
4103 case PCI_EXP_LNKSTA_NLW_X8:
4104 hw->bus.width = i40e_bus_width_pcie_x8;
4105 break;
4106 default:
4107 hw->bus.width = i40e_bus_width_unknown;
4108 break;
4109 }
4110
4111 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4112 case PCI_EXP_LNKSTA_CLS_2_5GB:
4113 hw->bus.speed = i40e_bus_speed_2500;
4114 break;
4115 case PCI_EXP_LNKSTA_CLS_5_0GB:
4116 hw->bus.speed = i40e_bus_speed_5000;
4117 break;
4118 case PCI_EXP_LNKSTA_CLS_8_0GB:
4119 hw->bus.speed = i40e_bus_speed_8000;
4120 break;
4121 default:
4122 hw->bus.speed = i40e_bus_speed_unknown;
4123 break;
4124 }
4125 }
4126
4127 /**
4128 * i40e_aq_debug_dump
4129 * @hw: pointer to the hardware structure
4130 * @cluster_id: specific cluster to dump
4131 * @table_id: table id within cluster
4132 * @start_index: index of line in the block to read
4133 * @buff_size: dump buffer size
4134 * @buff: dump buffer
4135 * @ret_buff_size: actual buffer size returned
4136 * @ret_next_table: next block to read
4137 * @ret_next_index: next index to read
4138 *
4139 * Dump internal FW/HW data for debug purposes.
4140 *
4141 **/
4142 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4143 u8 table_id, u32 start_index, u16 buff_size,
4144 void *buff, u16 *ret_buff_size,
4145 u8 *ret_next_table, u32 *ret_next_index,
4146 struct i40e_asq_cmd_details *cmd_details)
4147 {
4148 struct i40e_aq_desc desc;
4149 struct i40e_aqc_debug_dump_internals *cmd =
4150 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4151 struct i40e_aqc_debug_dump_internals *resp =
4152 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4153 i40e_status status;
4154
4155 if (buff_size == 0 || !buff)
4156 return I40E_ERR_PARAM;
4157
4158 i40e_fill_default_direct_cmd_desc(&desc,
4159 i40e_aqc_opc_debug_dump_internals);
4160 /* Indirect Command */
4161 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4162 if (buff_size > I40E_AQ_LARGE_BUF)
4163 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4164
4165 cmd->cluster_id = cluster_id;
4166 cmd->table_id = table_id;
4167 cmd->idx = cpu_to_le32(start_index);
4168
4169 desc.datalen = cpu_to_le16(buff_size);
4170
4171 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4172 if (!status) {
4173 if (ret_buff_size)
4174 *ret_buff_size = le16_to_cpu(desc.datalen);
4175 if (ret_next_table)
4176 *ret_next_table = resp->table_id;
4177 if (ret_next_index)
4178 *ret_next_index = le32_to_cpu(resp->idx);
4179 }
4180
4181 return status;
4182 }
4183
4184 /**
4185 * i40e_read_bw_from_alt_ram
4186 * @hw: pointer to the hardware structure
4187 * @max_bw: pointer for max_bw read
4188 * @min_bw: pointer for min_bw read
4189 * @min_valid: pointer for bool that is true if min_bw is a valid value
4190 * @max_valid: pointer for bool that is true if max_bw is a valid value
4191 *
4192 * Read bw from the alternate ram for the given pf
4193 **/
4194 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4195 u32 *max_bw, u32 *min_bw,
4196 bool *min_valid, bool *max_valid)
4197 {
4198 i40e_status status;
4199 u32 max_bw_addr, min_bw_addr;
4200
4201 /* Calculate the address of the min/max bw registers */
4202 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4203 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4204 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4205 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4206 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4207 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4208
4209 /* Read the bandwidths from alt ram */
4210 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4211 min_bw_addr, min_bw);
4212
4213 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4214 *min_valid = true;
4215 else
4216 *min_valid = false;
4217
4218 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4219 *max_valid = true;
4220 else
4221 *max_valid = false;
4222
4223 return status;
4224 }
4225
4226 /**
4227 * i40e_aq_configure_partition_bw
4228 * @hw: pointer to the hardware structure
4229 * @bw_data: Buffer holding valid pfs and bw limits
4230 * @cmd_details: pointer to command details
4231 *
4232 * Configure partitions guaranteed/max bw
4233 **/
4234 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4235 struct i40e_aqc_configure_partition_bw_data *bw_data,
4236 struct i40e_asq_cmd_details *cmd_details)
4237 {
4238 i40e_status status;
4239 struct i40e_aq_desc desc;
4240 u16 bwd_size = sizeof(*bw_data);
4241
4242 i40e_fill_default_direct_cmd_desc(&desc,
4243 i40e_aqc_opc_configure_partition_bw);
4244
4245 /* Indirect command */
4246 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4247 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4248
4249 if (bwd_size > I40E_AQ_LARGE_BUF)
4250 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4251
4252 desc.datalen = cpu_to_le16(bwd_size);
4253
4254 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4255 cmd_details);
4256
4257 return status;
4258 }
4259
4260 /**
4261 * i40e_read_phy_register
4262 * @hw: pointer to the HW structure
4263 * @page: registers page number
4264 * @reg: register address in the page
4265 * @phy_adr: PHY address on MDIO interface
4266 * @value: PHY register value
4267 *
4268 * Reads specified PHY register value
4269 **/
4270 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4271 u8 page, u16 reg, u8 phy_addr,
4272 u16 *value)
4273 {
4274 i40e_status status = I40E_ERR_TIMEOUT;
4275 u32 command = 0;
4276 u16 retry = 1000;
4277 u8 port_num = hw->func_caps.mdio_port_num;
4278
4279 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4280 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4281 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4282 (I40E_MDIO_OPCODE_ADDRESS) |
4283 (I40E_MDIO_STCODE) |
4284 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4285 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4286 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4287 do {
4288 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4289 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4290 status = 0;
4291 break;
4292 }
4293 usleep_range(10, 20);
4294 retry--;
4295 } while (retry);
4296
4297 if (status) {
4298 i40e_debug(hw, I40E_DEBUG_PHY,
4299 "PHY: Can't write command to external PHY.\n");
4300 goto phy_read_end;
4301 }
4302
4303 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4304 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4305 (I40E_MDIO_OPCODE_READ) |
4306 (I40E_MDIO_STCODE) |
4307 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4308 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4309 status = I40E_ERR_TIMEOUT;
4310 retry = 1000;
4311 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4312 do {
4313 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4314 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4315 status = 0;
4316 break;
4317 }
4318 usleep_range(10, 20);
4319 retry--;
4320 } while (retry);
4321
4322 if (!status) {
4323 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4324 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4325 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4326 } else {
4327 i40e_debug(hw, I40E_DEBUG_PHY,
4328 "PHY: Can't read register value from external PHY.\n");
4329 }
4330
4331 phy_read_end:
4332 return status;
4333 }
4334
4335 /**
4336 * i40e_write_phy_register
4337 * @hw: pointer to the HW structure
4338 * @page: registers page number
4339 * @reg: register address in the page
4340 * @phy_adr: PHY address on MDIO interface
4341 * @value: PHY register value
4342 *
4343 * Writes value to specified PHY register
4344 **/
4345 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4346 u8 page, u16 reg, u8 phy_addr,
4347 u16 value)
4348 {
4349 i40e_status status = I40E_ERR_TIMEOUT;
4350 u32 command = 0;
4351 u16 retry = 1000;
4352 u8 port_num = hw->func_caps.mdio_port_num;
4353
4354 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4355 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4356 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4357 (I40E_MDIO_OPCODE_ADDRESS) |
4358 (I40E_MDIO_STCODE) |
4359 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4360 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4361 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4362 do {
4363 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4364 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4365 status = 0;
4366 break;
4367 }
4368 usleep_range(10, 20);
4369 retry--;
4370 } while (retry);
4371 if (status) {
4372 i40e_debug(hw, I40E_DEBUG_PHY,
4373 "PHY: Can't write command to external PHY.\n");
4374 goto phy_write_end;
4375 }
4376
4377 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4378 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4379
4380 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4381 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4382 (I40E_MDIO_OPCODE_WRITE) |
4383 (I40E_MDIO_STCODE) |
4384 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4385 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4386 status = I40E_ERR_TIMEOUT;
4387 retry = 1000;
4388 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4389 do {
4390 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4391 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4392 status = 0;
4393 break;
4394 }
4395 usleep_range(10, 20);
4396 retry--;
4397 } while (retry);
4398
4399 phy_write_end:
4400 return status;
4401 }
4402
4403 /**
4404 * i40e_get_phy_address
4405 * @hw: pointer to the HW structure
4406 * @dev_num: PHY port num that address we want
4407 * @phy_addr: Returned PHY address
4408 *
4409 * Gets PHY address for current port
4410 **/
4411 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4412 {
4413 u8 port_num = hw->func_caps.mdio_port_num;
4414 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4415
4416 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4417 }
4418
4419 /**
4420 * i40e_blink_phy_led
4421 * @hw: pointer to the HW structure
4422 * @time: time how long led will blinks in secs
4423 * @interval: gap between LED on and off in msecs
4424 *
4425 * Blinks PHY link LED
4426 **/
4427 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4428 u32 time, u32 interval)
4429 {
4430 i40e_status status = 0;
4431 u32 i;
4432 u16 led_ctl;
4433 u16 gpio_led_port;
4434 u16 led_reg;
4435 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4436 u8 phy_addr = 0;
4437 u8 port_num;
4438
4439 i = rd32(hw, I40E_PFGEN_PORTNUM);
4440 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4441 phy_addr = i40e_get_phy_address(hw, port_num);
4442
4443 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4444 led_addr++) {
4445 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4446 led_addr, phy_addr, &led_reg);
4447 if (status)
4448 goto phy_blinking_end;
4449 led_ctl = led_reg;
4450 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4451 led_reg = 0;
4452 status = i40e_write_phy_register(hw,
4453 I40E_PHY_COM_REG_PAGE,
4454 led_addr, phy_addr,
4455 led_reg);
4456 if (status)
4457 goto phy_blinking_end;
4458 break;
4459 }
4460 }
4461
4462 if (time > 0 && interval > 0) {
4463 for (i = 0; i < time * 1000; i += interval) {
4464 status = i40e_read_phy_register(hw,
4465 I40E_PHY_COM_REG_PAGE,
4466 led_addr, phy_addr,
4467 &led_reg);
4468 if (status)
4469 goto restore_config;
4470 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4471 led_reg = 0;
4472 else
4473 led_reg = I40E_PHY_LED_MANUAL_ON;
4474 status = i40e_write_phy_register(hw,
4475 I40E_PHY_COM_REG_PAGE,
4476 led_addr, phy_addr,
4477 led_reg);
4478 if (status)
4479 goto restore_config;
4480 msleep(interval);
4481 }
4482 }
4483
4484 restore_config:
4485 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4486 phy_addr, led_ctl);
4487
4488 phy_blinking_end:
4489 return status;
4490 }
4491
4492 /**
4493 * i40e_led_get_phy - return current on/off mode
4494 * @hw: pointer to the hw struct
4495 * @led_addr: address of led register to use
4496 * @val: original value of register to use
4497 *
4498 **/
4499 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4500 u16 *val)
4501 {
4502 i40e_status status = 0;
4503 u16 gpio_led_port;
4504 u8 phy_addr = 0;
4505 u16 reg_val;
4506 u16 temp_addr;
4507 u8 port_num;
4508 u32 i;
4509
4510 temp_addr = I40E_PHY_LED_PROV_REG_1;
4511 i = rd32(hw, I40E_PFGEN_PORTNUM);
4512 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4513 phy_addr = i40e_get_phy_address(hw, port_num);
4514
4515 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4516 temp_addr++) {
4517 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4518 temp_addr, phy_addr, &reg_val);
4519 if (status)
4520 return status;
4521 *val = reg_val;
4522 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4523 *led_addr = temp_addr;
4524 break;
4525 }
4526 }
4527 return status;
4528 }
4529
4530 /**
4531 * i40e_led_set_phy
4532 * @hw: pointer to the HW structure
4533 * @on: true or false
4534 * @mode: original val plus bit for set or ignore
4535 * Set led's on or off when controlled by the PHY
4536 *
4537 **/
4538 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4539 u16 led_addr, u32 mode)
4540 {
4541 i40e_status status = 0;
4542 u16 led_ctl = 0;
4543 u16 led_reg = 0;
4544 u8 phy_addr = 0;
4545 u8 port_num;
4546 u32 i;
4547
4548 i = rd32(hw, I40E_PFGEN_PORTNUM);
4549 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4550 phy_addr = i40e_get_phy_address(hw, port_num);
4551
4552 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4553 phy_addr, &led_reg);
4554 if (status)
4555 return status;
4556 led_ctl = led_reg;
4557 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4558 led_reg = 0;
4559 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4560 led_addr, phy_addr, led_reg);
4561 if (status)
4562 return status;
4563 }
4564 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4565 led_addr, phy_addr, &led_reg);
4566 if (status)
4567 goto restore_config;
4568 if (on)
4569 led_reg = I40E_PHY_LED_MANUAL_ON;
4570 else
4571 led_reg = 0;
4572 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4573 led_addr, phy_addr, led_reg);
4574 if (status)
4575 goto restore_config;
4576 if (mode & I40E_PHY_LED_MODE_ORIG) {
4577 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4578 status = i40e_write_phy_register(hw,
4579 I40E_PHY_COM_REG_PAGE,
4580 led_addr, phy_addr, led_ctl);
4581 }
4582 return status;
4583 restore_config:
4584 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4585 phy_addr, led_ctl);
4586 return status;
4587 }
4588
4589 /**
4590 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4591 * @hw: pointer to the hw struct
4592 * @reg_addr: register address
4593 * @reg_val: ptr to register value
4594 * @cmd_details: pointer to command details structure or NULL
4595 *
4596 * Use the firmware to read the Rx control register,
4597 * especially useful if the Rx unit is under heavy pressure
4598 **/
4599 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4600 u32 reg_addr, u32 *reg_val,
4601 struct i40e_asq_cmd_details *cmd_details)
4602 {
4603 struct i40e_aq_desc desc;
4604 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4605 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4606 i40e_status status;
4607
4608 if (!reg_val)
4609 return I40E_ERR_PARAM;
4610
4611 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4612
4613 cmd_resp->address = cpu_to_le32(reg_addr);
4614
4615 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4616
4617 if (status == 0)
4618 *reg_val = le32_to_cpu(cmd_resp->value);
4619
4620 return status;
4621 }
4622
4623 /**
4624 * i40e_read_rx_ctl - read from an Rx control register
4625 * @hw: pointer to the hw struct
4626 * @reg_addr: register address
4627 **/
4628 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4629 {
4630 i40e_status status = 0;
4631 bool use_register;
4632 int retry = 5;
4633 u32 val = 0;
4634
4635 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4636 if (!use_register) {
4637 do_retry:
4638 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4639 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4640 usleep_range(1000, 2000);
4641 retry--;
4642 goto do_retry;
4643 }
4644 }
4645
4646 /* if the AQ access failed, try the old-fashioned way */
4647 if (status || use_register)
4648 val = rd32(hw, reg_addr);
4649
4650 return val;
4651 }
4652
4653 /**
4654 * i40e_aq_rx_ctl_write_register
4655 * @hw: pointer to the hw struct
4656 * @reg_addr: register address
4657 * @reg_val: register value
4658 * @cmd_details: pointer to command details structure or NULL
4659 *
4660 * Use the firmware to write to an Rx control register,
4661 * especially useful if the Rx unit is under heavy pressure
4662 **/
4663 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4664 u32 reg_addr, u32 reg_val,
4665 struct i40e_asq_cmd_details *cmd_details)
4666 {
4667 struct i40e_aq_desc desc;
4668 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4669 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4670 i40e_status status;
4671
4672 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4673
4674 cmd->address = cpu_to_le32(reg_addr);
4675 cmd->value = cpu_to_le32(reg_val);
4676
4677 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4678
4679 return status;
4680 }
4681
4682 /**
4683 * i40e_write_rx_ctl - write to an Rx control register
4684 * @hw: pointer to the hw struct
4685 * @reg_addr: register address
4686 * @reg_val: register value
4687 **/
4688 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4689 {
4690 i40e_status status = 0;
4691 bool use_register;
4692 int retry = 5;
4693
4694 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4695 if (!use_register) {
4696 do_retry:
4697 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4698 reg_val, NULL);
4699 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4700 usleep_range(1000, 2000);
4701 retry--;
4702 goto do_retry;
4703 }
4704 }
4705
4706 /* if the AQ access failed, try the old-fashioned way */
4707 if (status || use_register)
4708 wr32(hw, reg_addr, reg_val);
4709 }
Ubuntu Hirsute Linux kernel mirror