1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
28 #include <linux/ptp_classify.h>
30 /* The XL710 timesync is very much like Intel's 82599 design when it comes to
31 * the fundamental clock design. However, the clock operations are much simpler
32 * in the XL710 because the device supports a full 64 bits of nanoseconds.
33 * Because the field is so wide, we can forgo the cycle counter and just
34 * operate with the nanosecond field directly without fear of overflow.
36 * Much like the 82599, the update period is dependent upon the link speed:
37 * At 40Gb link or no link, the period is 1.6ns.
38 * At 10Gb link, the period is multiplied by 2. (3.2ns)
39 * At 1Gb link, the period is multiplied by 20. (32ns)
40 * 1588 functionality is not supported at 100Mbps.
42 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
43 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
44 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
46 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 (0x1 << \
47 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
48 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (0x2 << \
49 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
52 * i40e_ptp_read - Read the PHC time from the device
53 * @pf: Board private structure
54 * @ts: timespec structure to hold the current time value
56 * This function reads the PRTTSYN_TIME registers and stores them in a
57 * timespec. However, since the registers are 64 bits of nanoseconds, we must
58 * convert the result to a timespec before we can return.
60 static void i40e_ptp_read(struct i40e_pf
*pf
, struct timespec
*ts
)
62 struct i40e_hw
*hw
= &pf
->hw
;
66 /* The timer latches on the lowest register read. */
67 lo
= rd32(hw
, I40E_PRTTSYN_TIME_L
);
68 hi
= rd32(hw
, I40E_PRTTSYN_TIME_H
);
70 ns
= (((u64
)hi
) << 32) | lo
;
72 *ts
= ns_to_timespec(ns
);
76 * i40e_ptp_write - Write the PHC time to the device
77 * @pf: Board private structure
78 * @ts: timespec structure that holds the new time value
80 * This function writes the PRTTSYN_TIME registers with the user value. Since
81 * we receive a timespec from the stack, we must convert that timespec into
82 * nanoseconds before programming the registers.
84 static void i40e_ptp_write(struct i40e_pf
*pf
, const struct timespec
*ts
)
86 struct i40e_hw
*hw
= &pf
->hw
;
87 u64 ns
= timespec_to_ns(ts
);
89 /* The timer will not update until the high register is written, so
90 * write the low register first.
92 wr32(hw
, I40E_PRTTSYN_TIME_L
, ns
& 0xFFFFFFFF);
93 wr32(hw
, I40E_PRTTSYN_TIME_H
, ns
>> 32);
97 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
98 * @hwtstamps: Timestamp structure to update
99 * @timestamp: Timestamp from the hardware
101 * We need to convert the NIC clock value into a hwtstamp which can be used by
102 * the upper level timestamping functions. Since the timestamp is simply a 64-
103 * bit nanosecond value, we can call ns_to_ktime directly to handle this.
105 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps
*hwtstamps
,
108 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
110 hwtstamps
->hwtstamp
= ns_to_ktime(timestamp
);
114 * i40e_ptp_adjfreq - Adjust the PHC frequency
115 * @ptp: The PTP clock structure
116 * @ppb: Parts per billion adjustment from the base
118 * Adjust the frequency of the PHC by the indicated parts per billion from the
121 static int i40e_ptp_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
123 struct i40e_pf
*pf
= container_of(ptp
, struct i40e_pf
, ptp_caps
);
124 struct i40e_hw
*hw
= &pf
->hw
;
133 smp_mb(); /* Force any pending update before accessing. */
134 adj
= ACCESS_ONCE(pf
->ptp_base_adj
);
138 diff
= div_u64(freq
, 1000000000ULL);
145 wr32(hw
, I40E_PRTTSYN_INC_L
, adj
& 0xFFFFFFFF);
146 wr32(hw
, I40E_PRTTSYN_INC_H
, adj
>> 32);
152 * i40e_ptp_adjtime - Adjust the PHC time
153 * @ptp: The PTP clock structure
154 * @delta: Offset in nanoseconds to adjust the PHC time by
156 * Adjust the frequency of the PHC by the indicated parts per billion from the
159 static int i40e_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
161 struct i40e_pf
*pf
= container_of(ptp
, struct i40e_pf
, ptp_caps
);
162 struct timespec now
, then
= ns_to_timespec(delta
);
165 spin_lock_irqsave(&pf
->tmreg_lock
, flags
);
167 i40e_ptp_read(pf
, &now
);
168 now
= timespec_add(now
, then
);
169 i40e_ptp_write(pf
, (const struct timespec
*)&now
);
171 spin_unlock_irqrestore(&pf
->tmreg_lock
, flags
);
177 * i40e_ptp_gettime - Get the time of the PHC
178 * @ptp: The PTP clock structure
179 * @ts: timespec structure to hold the current time value
181 * Read the device clock and return the correct value on ns, after converting it
182 * into a timespec struct.
184 static int i40e_ptp_gettime(struct ptp_clock_info
*ptp
, struct timespec
*ts
)
186 struct i40e_pf
*pf
= container_of(ptp
, struct i40e_pf
, ptp_caps
);
189 spin_lock_irqsave(&pf
->tmreg_lock
, flags
);
190 i40e_ptp_read(pf
, ts
);
191 spin_unlock_irqrestore(&pf
->tmreg_lock
, flags
);
197 * i40e_ptp_settime - Set the time of the PHC
198 * @ptp: The PTP clock structure
199 * @ts: timespec structure that holds the new time value
201 * Set the device clock to the user input value. The conversion from timespec
202 * to ns happens in the write function.
204 static int i40e_ptp_settime(struct ptp_clock_info
*ptp
,
205 const struct timespec
*ts
)
207 struct i40e_pf
*pf
= container_of(ptp
, struct i40e_pf
, ptp_caps
);
210 spin_lock_irqsave(&pf
->tmreg_lock
, flags
);
211 i40e_ptp_write(pf
, ts
);
212 spin_unlock_irqrestore(&pf
->tmreg_lock
, flags
);
218 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem
219 * @ptp: The PTP clock structure
220 * @rq: The requested feature to change
221 * @on: Enable/disable flag
223 * The XL710 does not support any of the ancillary features of the PHC
224 * subsystem, so this function may just return.
226 static int i40e_ptp_feature_enable(struct ptp_clock_info
*ptp
,
227 struct ptp_clock_request
*rq
, int on
)
233 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
234 * @vsi: The VSI with the rings relevant to 1588
236 * This watchdog task is scheduled to detect error case where hardware has
237 * dropped an Rx packet that was timestamped when the ring is full. The
238 * particular error is rare but leaves the device in a state unable to timestamp
239 * any future packets.
241 void i40e_ptp_rx_hang(struct i40e_vsi
*vsi
)
243 struct i40e_pf
*pf
= vsi
->back
;
244 struct i40e_hw
*hw
= &pf
->hw
;
245 struct i40e_ring
*rx_ring
;
246 unsigned long rx_event
;
250 if (!(pf
->flags
& I40E_FLAG_PTP
))
253 prttsyn_stat
= rd32(hw
, I40E_PRTTSYN_STAT_1
);
255 /* Unless all four receive timestamp registers are latched, we are not
256 * concerned about a possible PTP Rx hang, so just update the timeout
259 if (!(prttsyn_stat
& ((I40E_PRTTSYN_STAT_1_RXT0_MASK
<<
260 I40E_PRTTSYN_STAT_1_RXT0_SHIFT
) |
261 (I40E_PRTTSYN_STAT_1_RXT1_MASK
<<
262 I40E_PRTTSYN_STAT_1_RXT1_SHIFT
) |
263 (I40E_PRTTSYN_STAT_1_RXT2_MASK
<<
264 I40E_PRTTSYN_STAT_1_RXT2_SHIFT
) |
265 (I40E_PRTTSYN_STAT_1_RXT3_MASK
<<
266 I40E_PRTTSYN_STAT_1_RXT3_SHIFT
)))) {
267 pf
->last_rx_ptp_check
= jiffies
;
271 /* Determine the most recent watchdog or rx_timestamp event. */
272 rx_event
= pf
->last_rx_ptp_check
;
273 for (n
= 0; n
< vsi
->num_queue_pairs
; n
++) {
274 rx_ring
= vsi
->rx_rings
[n
];
275 if (time_after(rx_ring
->last_rx_timestamp
, rx_event
))
276 rx_event
= rx_ring
->last_rx_timestamp
;
279 /* Only need to read the high RXSTMP register to clear the lock */
280 if (time_is_before_jiffies(rx_event
+ 5 * HZ
)) {
281 rd32(hw
, I40E_PRTTSYN_RXTIME_H(0));
282 rd32(hw
, I40E_PRTTSYN_RXTIME_H(1));
283 rd32(hw
, I40E_PRTTSYN_RXTIME_H(2));
284 rd32(hw
, I40E_PRTTSYN_RXTIME_H(3));
285 pf
->last_rx_ptp_check
= jiffies
;
286 pf
->rx_hwtstamp_cleared
++;
287 dev_warn(&vsi
->back
->pdev
->dev
,
288 "%s: clearing Rx timestamp hang\n",
294 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
295 * @pf: Board private structure
297 * Read the value of the Tx timestamp from the registers, convert it into a
298 * value consumable by the stack, and store that result into the shhwtstamps
299 * struct before returning it up the stack.
301 void i40e_ptp_tx_hwtstamp(struct i40e_pf
*pf
)
303 struct skb_shared_hwtstamps shhwtstamps
;
304 struct i40e_hw
*hw
= &pf
->hw
;
308 lo
= rd32(hw
, I40E_PRTTSYN_TXTIME_L
);
309 hi
= rd32(hw
, I40E_PRTTSYN_TXTIME_H
);
311 ns
= (((u64
)hi
) << 32) | lo
;
313 i40e_ptp_convert_to_hwtstamp(&shhwtstamps
, ns
);
314 skb_tstamp_tx(pf
->ptp_tx_skb
, &shhwtstamps
);
315 dev_kfree_skb_any(pf
->ptp_tx_skb
);
316 pf
->ptp_tx_skb
= NULL
;
317 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS
, &pf
->state
);
321 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
322 * @pf: Board private structure
323 * @skb: Particular skb to send timestamp with
324 * @index: Index into the receive timestamp registers for the timestamp
326 * The XL710 receives a notification in the receive descriptor with an offset
327 * into the set of RXTIME registers where the timestamp is for that skb. This
328 * function goes and fetches the receive timestamp from that offset, if a valid
329 * one exists. The RXTIME registers are in ns, so we must convert the result
332 void i40e_ptp_rx_hwtstamp(struct i40e_pf
*pf
, struct sk_buff
*skb
, u8 index
)
334 u32 prttsyn_stat
, hi
, lo
;
338 /* Since we cannot turn off the Rx timestamp logic if the device is
339 * doing Tx timestamping, check if Rx timestamping is configured.
346 prttsyn_stat
= rd32(hw
, I40E_PRTTSYN_STAT_1
);
348 if (!(prttsyn_stat
& (1 << index
)))
351 lo
= rd32(hw
, I40E_PRTTSYN_RXTIME_L(index
));
352 hi
= rd32(hw
, I40E_PRTTSYN_RXTIME_H(index
));
354 ns
= (((u64
)hi
) << 32) | lo
;
356 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb
), ns
);
360 * i40e_ptp_set_increment - Utility function to update clock increment rate
361 * @pf: Board private structure
363 * During a link change, the DMA frequency that drives the 1588 logic will
364 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
365 * we must update the increment value per clock tick.
367 void i40e_ptp_set_increment(struct i40e_pf
*pf
)
369 struct i40e_link_status
*hw_link_info
;
370 struct i40e_hw
*hw
= &pf
->hw
;
373 hw_link_info
= &hw
->phy
.link_info
;
375 i40e_aq_get_link_info(&pf
->hw
, true, NULL
, NULL
);
377 switch (hw_link_info
->link_speed
) {
378 case I40E_LINK_SPEED_10GB
:
379 incval
= I40E_PTP_10GB_INCVAL
;
381 case I40E_LINK_SPEED_1GB
:
382 incval
= I40E_PTP_1GB_INCVAL
;
384 case I40E_LINK_SPEED_100MB
:
385 dev_warn(&pf
->pdev
->dev
,
386 "%s: 1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n",
390 case I40E_LINK_SPEED_40GB
:
392 incval
= I40E_PTP_40GB_INCVAL
;
396 /* Write the new increment value into the increment register. The
397 * hardware will not update the clock until both registers have been
400 wr32(hw
, I40E_PRTTSYN_INC_L
, incval
& 0xFFFFFFFF);
401 wr32(hw
, I40E_PRTTSYN_INC_H
, incval
>> 32);
403 /* Update the base adjustement value. */
404 ACCESS_ONCE(pf
->ptp_base_adj
) = incval
;
405 smp_mb(); /* Force the above update. */
409 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
410 * @pf: Board private structure
413 * Obtain the current hardware timestamping settigs as requested. To do this,
414 * keep a shadow copy of the timestamp settings rather than attempting to
415 * deconstruct it from the registers.
417 int i40e_ptp_get_ts_config(struct i40e_pf
*pf
, struct ifreq
*ifr
)
419 struct hwtstamp_config
*config
= &pf
->tstamp_config
;
421 return copy_to_user(ifr
->ifr_data
, config
, sizeof(*config
)) ?
426 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode
427 * @pf: Board private structure
428 * @config: hwtstamp settings requested or saved
430 * Control hardware registers to enter the specific mode requested by the
431 * user. Also used during reset path to ensure that timestamp settings are
434 * Note: modifies config in place, and may update the requested mode to be
435 * more broad if the specific filter is not directly supported.
437 static int i40e_ptp_set_timestamp_mode(struct i40e_pf
*pf
,
438 struct hwtstamp_config
*config
)
440 struct i40e_hw
*hw
= &pf
->hw
;
441 u32 pf_id
, tsyntype
, regval
;
443 /* Reserved for future extensions. */
447 /* Confirm that 1588 is supported on this PF. */
448 pf_id
= (rd32(hw
, I40E_PRTTSYN_CTL0
) & I40E_PRTTSYN_CTL0_PF_ID_MASK
) >>
449 I40E_PRTTSYN_CTL0_PF_ID_SHIFT
;
450 if (hw
->pf_id
!= pf_id
) {
451 dev_err(&pf
->pdev
->dev
,
452 "PF %d attempted to control timestamp mode on port %d, which is owned by PF %d\n",
453 hw
->pf_id
, hw
->port
, pf_id
);
457 switch (config
->tx_type
) {
458 case HWTSTAMP_TX_OFF
:
468 switch (config
->rx_filter
) {
469 case HWTSTAMP_FILTER_NONE
:
473 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
474 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
475 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
477 tsyntype
= I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK
|
478 I40E_PRTTSYN_CTL1_TSYNTYPE_V1
|
479 I40E_PRTTSYN_CTL1_UDP_ENA_MASK
;
480 config
->rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
482 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
483 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
484 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
485 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
486 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
487 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
488 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
489 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
490 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
492 tsyntype
= I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK
|
493 I40E_PRTTSYN_CTL1_TSYNTYPE_V2
|
494 I40E_PRTTSYN_CTL1_UDP_ENA_MASK
;
495 config
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
497 case HWTSTAMP_FILTER_ALL
:
502 /* Clear out all 1588-related registers to clear and unlatch them. */
503 rd32(hw
, I40E_PRTTSYN_STAT_0
);
504 rd32(hw
, I40E_PRTTSYN_TXTIME_H
);
505 rd32(hw
, I40E_PRTTSYN_RXTIME_H(0));
506 rd32(hw
, I40E_PRTTSYN_RXTIME_H(1));
507 rd32(hw
, I40E_PRTTSYN_RXTIME_H(2));
508 rd32(hw
, I40E_PRTTSYN_RXTIME_H(3));
510 /* Enable/disable the Tx timestamp interrupt based on user input. */
511 regval
= rd32(hw
, I40E_PRTTSYN_CTL0
);
513 regval
|= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK
;
515 regval
&= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK
;
516 wr32(hw
, I40E_PRTTSYN_CTL0
, regval
);
518 regval
= rd32(hw
, I40E_PFINT_ICR0_ENA
);
520 regval
|= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK
;
522 regval
&= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK
;
523 wr32(hw
, I40E_PFINT_ICR0_ENA
, regval
);
525 /* There is no simple on/off switch for Rx. To "disable" Rx support,
526 * ignore any received timestamps, rather than turn off the clock.
529 regval
= rd32(hw
, I40E_PRTTSYN_CTL1
);
530 /* clear everything but the enable bit */
531 regval
&= I40E_PRTTSYN_CTL1_TSYNENA_MASK
;
532 /* now enable bits for desired Rx timestamps */
534 wr32(hw
, I40E_PRTTSYN_CTL1
, regval
);
541 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
542 * @pf: Board private structure
545 * Respond to the user filter requests and make the appropriate hardware
546 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
547 * logic, so keep track in software of whether to indicate these timestamps
550 * It is permissible to "upgrade" the user request to a broader filter, as long
551 * as the user receives the timestamps they care about and the user is notified
552 * the filter has been broadened.
554 int i40e_ptp_set_ts_config(struct i40e_pf
*pf
, struct ifreq
*ifr
)
556 struct hwtstamp_config config
;
559 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
562 err
= i40e_ptp_set_timestamp_mode(pf
, &config
);
566 /* save these settings for future reference */
567 pf
->tstamp_config
= config
;
569 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
574 * i40e_ptp_create_clock - Create PTP clock device for userspace
575 * @pf: Board private structure
577 * This function creates a new PTP clock device. It only creates one if we
578 * don't already have one, so it is safe to call. Will return error if it
579 * can't create one, but success if we already have a device. Should be used
580 * by i40e_ptp_init to create clock initially, and prevent global resets from
581 * creating new clock devices.
583 static long i40e_ptp_create_clock(struct i40e_pf
*pf
)
585 /* no need to create a clock device if we already have one */
586 if (!IS_ERR_OR_NULL(pf
->ptp_clock
))
589 strncpy(pf
->ptp_caps
.name
, i40e_driver_name
, sizeof(pf
->ptp_caps
.name
));
590 pf
->ptp_caps
.owner
= THIS_MODULE
;
591 pf
->ptp_caps
.max_adj
= 999999999;
592 pf
->ptp_caps
.n_ext_ts
= 0;
593 pf
->ptp_caps
.pps
= 0;
594 pf
->ptp_caps
.adjfreq
= i40e_ptp_adjfreq
;
595 pf
->ptp_caps
.adjtime
= i40e_ptp_adjtime
;
596 pf
->ptp_caps
.gettime
= i40e_ptp_gettime
;
597 pf
->ptp_caps
.settime
= i40e_ptp_settime
;
598 pf
->ptp_caps
.enable
= i40e_ptp_feature_enable
;
600 /* Attempt to register the clock before enabling the hardware. */
601 pf
->ptp_clock
= ptp_clock_register(&pf
->ptp_caps
, &pf
->pdev
->dev
);
602 if (IS_ERR(pf
->ptp_clock
)) {
603 return PTR_ERR(pf
->ptp_clock
);
606 /* clear the hwtstamp settings here during clock create, instead of
607 * during regular init, so that we can maintain settings across a
610 pf
->tstamp_config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
611 pf
->tstamp_config
.tx_type
= HWTSTAMP_TX_OFF
;
617 * i40e_ptp_init - Initialize the 1588 support after device probe or reset
618 * @pf: Board private structure
620 * This function sets device up for 1588 support. The first time it is run, it
621 * will create a PHC clock device. It does not create a clock device if one
622 * already exists. It also reconfigures the device after a reset.
624 void i40e_ptp_init(struct i40e_pf
*pf
)
626 struct net_device
*netdev
= pf
->vsi
[pf
->lan_vsi
]->netdev
;
627 struct i40e_hw
*hw
= &pf
->hw
;
630 /* we have to initialize the lock first, since we can't control
631 * when the user will enter the PHC device entry points
633 spin_lock_init(&pf
->tmreg_lock
);
635 /* ensure we have a clock device */
636 err
= i40e_ptp_create_clock(pf
);
638 pf
->ptp_clock
= NULL
;
639 dev_err(&pf
->pdev
->dev
, "%s: ptp_clock_register failed\n",
645 dev_info(&pf
->pdev
->dev
, "%s: added PHC on %s\n", __func__
,
647 pf
->flags
|= I40E_FLAG_PTP
;
649 /* Ensure the clocks are running. */
650 regval
= rd32(hw
, I40E_PRTTSYN_CTL0
);
651 regval
|= I40E_PRTTSYN_CTL0_TSYNENA_MASK
;
652 wr32(hw
, I40E_PRTTSYN_CTL0
, regval
);
653 regval
= rd32(hw
, I40E_PRTTSYN_CTL1
);
654 regval
|= I40E_PRTTSYN_CTL1_TSYNENA_MASK
;
655 wr32(hw
, I40E_PRTTSYN_CTL1
, regval
);
657 /* Set the increment value per clock tick. */
658 i40e_ptp_set_increment(pf
);
660 /* reset timestamping mode */
661 i40e_ptp_set_timestamp_mode(pf
, &pf
->tstamp_config
);
663 /* Set the clock value. */
664 ts
= ktime_to_timespec(ktime_get_real());
665 i40e_ptp_settime(&pf
->ptp_caps
, &ts
);
670 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
671 * @pf: Board private structure
673 * This function handles the cleanup work required from the initialization by
674 * clearing out the important information and unregistering the PHC.
676 void i40e_ptp_stop(struct i40e_pf
*pf
)
678 pf
->flags
&= ~I40E_FLAG_PTP
;
682 if (pf
->ptp_tx_skb
) {
683 dev_kfree_skb_any(pf
->ptp_tx_skb
);
684 pf
->ptp_tx_skb
= NULL
;
685 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS
, &pf
->state
);
689 ptp_clock_unregister(pf
->ptp_clock
);
690 pf
->ptp_clock
= NULL
;
691 dev_info(&pf
->pdev
->dev
, "%s: removed PHC on %s\n", __func__
,
692 pf
->vsi
[pf
->lan_vsi
]->netdev
->name
);