drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36
  37 /* Device IDs */
  38 #define I40E_DEV_ID_SFP_XL710           0x1572
  39 #define I40E_DEV_ID_QEMU                0x1574
  40 #define I40E_DEV_ID_KX_A                0x157F
  41 #define I40E_DEV_ID_KX_B                0x1580
  42 #define I40E_DEV_ID_KX_C                0x1581
  43 #define I40E_DEV_ID_QSFP_A              0x1583
  44 #define I40E_DEV_ID_QSFP_B              0x1584
  45 #define I40E_DEV_ID_QSFP_C              0x1585
  46 #define I40E_DEV_ID_VF                  0x154C
  47 #define I40E_DEV_ID_VF_HV               0x1571
  48
  49 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  50                                          (d) == I40E_DEV_ID_QSFP_B  || \
  51                                          (d) == I40E_DEV_ID_QSFP_C)
  52
  53 /* I40E_MASK is a macro used on 32 bit registers */
  54 #define I40E_MASK(mask, shift) (mask << shift)
  55
  56 #define I40E_MAX_VSI_QP                 16
  57 #define I40E_MAX_VF_VSI                 3
  58 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  59 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  60
  61 /* Max default timeout in ms, */
  62 #define I40E_MAX_NVM_TIMEOUT            18000
  63
  64 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  65 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  66
  67 /* forward declaration */
  68 struct i40e_hw;
  69 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  70
  71 /* Data type manipulation macros. */
  72
  73 #define I40E_DESC_UNUSED(R)     \
  74         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  75         (R)->next_to_clean - (R)->next_to_use - 1)
  76
  77 /* bitfields for Tx queue mapping in QTX_CTL */
  78 #define I40E_QTX_CTL_VF_QUEUE   0x0
  79 #define I40E_QTX_CTL_VM_QUEUE   0x1
  80 #define I40E_QTX_CTL_PF_QUEUE   0x2
  81
  82 /* debug masks - set these bits in hw->debug_mask to control output */
  83 enum i40e_debug_mask {
  84         I40E_DEBUG_INIT                 = 0x00000001,
  85         I40E_DEBUG_RELEASE              = 0x00000002,
  86
  87         I40E_DEBUG_LINK                 = 0x00000010,
  88         I40E_DEBUG_PHY                  = 0x00000020,
  89         I40E_DEBUG_HMC                  = 0x00000040,
  90         I40E_DEBUG_NVM                  = 0x00000080,
  91         I40E_DEBUG_LAN                  = 0x00000100,
  92         I40E_DEBUG_FLOW                 = 0x00000200,
  93         I40E_DEBUG_DCB                  = 0x00000400,
  94         I40E_DEBUG_DIAG                 = 0x00000800,
  95         I40E_DEBUG_FD                   = 0x00001000,
  96
  97         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  98         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  99         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 100         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 101         I40E_DEBUG_AQ                   = 0x0F000000,
 102
 103         I40E_DEBUG_USER                 = 0xF0000000,
 104
 105         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 106 };
 107
 108 /* These are structs for managing the hardware information and the operations.
 109  * The structures of function pointers are filled out at init time when we
 110  * know for sure exactly which hardware we're working with.  This gives us the
 111  * flexibility of using the same main driver code but adapting to slightly
 112  * different hardware needs as new parts are developed.  For this architecture,
 113  * the Firmware and AdminQ are intended to insulate the driver from most of the
 114  * future changes, but these structures will also do part of the job.
 115  */
 116 enum i40e_mac_type {
 117         I40E_MAC_UNKNOWN = 0,
 118         I40E_MAC_X710,
 119         I40E_MAC_XL710,
 120         I40E_MAC_VF,
 121         I40E_MAC_GENERIC,
 122 };
 123
 124 enum i40e_media_type {
 125         I40E_MEDIA_TYPE_UNKNOWN = 0,
 126         I40E_MEDIA_TYPE_FIBER,
 127         I40E_MEDIA_TYPE_BASET,
 128         I40E_MEDIA_TYPE_BACKPLANE,
 129         I40E_MEDIA_TYPE_CX4,
 130         I40E_MEDIA_TYPE_DA,
 131         I40E_MEDIA_TYPE_VIRTUAL
 132 };
 133
 134 enum i40e_fc_mode {
 135         I40E_FC_NONE = 0,
 136         I40E_FC_RX_PAUSE,
 137         I40E_FC_TX_PAUSE,
 138         I40E_FC_FULL,
 139         I40E_FC_PFC,
 140         I40E_FC_DEFAULT
 141 };
 142
 143 enum i40e_set_fc_aq_failures {
 144         I40E_SET_FC_AQ_FAIL_NONE = 0,
 145         I40E_SET_FC_AQ_FAIL_GET = 1,
 146         I40E_SET_FC_AQ_FAIL_SET = 2,
 147         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 148         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 149 };
 150
 151 enum i40e_vsi_type {
 152         I40E_VSI_MAIN = 0,
 153         I40E_VSI_VMDQ1,
 154         I40E_VSI_VMDQ2,
 155         I40E_VSI_CTRL,
 156         I40E_VSI_FCOE,
 157         I40E_VSI_MIRROR,
 158         I40E_VSI_SRIOV,
 159         I40E_VSI_FDIR,
 160         I40E_VSI_TYPE_UNKNOWN
 161 };
 162
 163 enum i40e_queue_type {
 164         I40E_QUEUE_TYPE_RX = 0,
 165         I40E_QUEUE_TYPE_TX,
 166         I40E_QUEUE_TYPE_PE_CEQ,
 167         I40E_QUEUE_TYPE_UNKNOWN
 168 };
 169
 170 struct i40e_link_status {
 171         enum i40e_aq_phy_type phy_type;
 172         enum i40e_aq_link_speed link_speed;
 173         u8 link_info;
 174         u8 an_info;
 175         u8 ext_info;
 176         u8 loopback;
 177         bool an_enabled;
 178         /* is Link Status Event notification to SW enabled */
 179         bool lse_enable;
 180         u16 max_frame_size;
 181         bool crc_enable;
 182         u8 pacing;
 183 };
 184
 185 struct i40e_phy_info {
 186         struct i40e_link_status link_info;
 187         struct i40e_link_status link_info_old;
 188         u32 autoneg_advertised;
 189         u32 phy_id;
 190         u32 module_type;
 191         bool get_link_info;
 192         enum i40e_media_type media_type;
 193 };
 194
 195 #define I40E_HW_CAP_MAX_GPIO                    30
 196 /* Capabilities of a PF or a VF or the whole device */
 197 struct i40e_hw_capabilities {
 198         u32  switch_mode;
 199 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 200 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 201 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 202
 203         u32  management_mode;
 204         u32  npar_enable;
 205         u32  os2bmc;
 206         u32  valid_functions;
 207         bool sr_iov_1_1;
 208         bool vmdq;
 209         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 210         bool evb_802_1_qbh; /* Bridge Port Extension */
 211         bool dcb;
 212         bool fcoe;
 213         bool mfp_mode_1;
 214         bool mgmt_cem;
 215         bool ieee_1588;
 216         bool iwarp;
 217         bool fd;
 218         u32 fd_filters_guaranteed;
 219         u32 fd_filters_best_effort;
 220         bool rss;
 221         u32 rss_table_size;
 222         u32 rss_table_entry_width;
 223         bool led[I40E_HW_CAP_MAX_GPIO];
 224         bool sdp[I40E_HW_CAP_MAX_GPIO];
 225         u32 nvm_image_type;
 226         u32 num_flow_director_filters;
 227         u32 num_vfs;
 228         u32 vf_base_id;
 229         u32 num_vsis;
 230         u32 num_rx_qp;
 231         u32 num_tx_qp;
 232         u32 base_queue;
 233         u32 num_msix_vectors;
 234         u32 num_msix_vectors_vf;
 235         u32 led_pin_num;
 236         u32 sdp_pin_num;
 237         u32 mdio_port_num;
 238         u32 mdio_port_mode;
 239         u8 rx_buf_chain_len;
 240         u32 enabled_tcmap;
 241         u32 maxtc;
 242 };
 243
 244 struct i40e_mac_info {
 245         enum i40e_mac_type type;
 246         u8 addr[ETH_ALEN];
 247         u8 perm_addr[ETH_ALEN];
 248         u8 san_addr[ETH_ALEN];
 249         u8 port_addr[ETH_ALEN];
 250         u16 max_fcoeq;
 251 };
 252
 253 enum i40e_aq_resources_ids {
 254         I40E_NVM_RESOURCE_ID = 1
 255 };
 256
 257 enum i40e_aq_resource_access_type {
 258         I40E_RESOURCE_READ = 1,
 259         I40E_RESOURCE_WRITE
 260 };
 261
 262 struct i40e_nvm_info {
 263         u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
 264         u64 hw_semaphore_wait;    /* - || - */
 265         u32 timeout;              /* [ms] */
 266         u16 sr_size;              /* Shadow RAM size in words */
 267         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 268         u16 version;              /* NVM package version */
 269         u32 eetrack;              /* NVM data version */
 270 };
 271
 272 /* definitions used in NVM update support */
 273
 274 enum i40e_nvmupd_cmd {
 275         I40E_NVMUPD_INVALID,
 276         I40E_NVMUPD_READ_CON,
 277         I40E_NVMUPD_READ_SNT,
 278         I40E_NVMUPD_READ_LCB,
 279         I40E_NVMUPD_READ_SA,
 280         I40E_NVMUPD_WRITE_ERA,
 281         I40E_NVMUPD_WRITE_CON,
 282         I40E_NVMUPD_WRITE_SNT,
 283         I40E_NVMUPD_WRITE_LCB,
 284         I40E_NVMUPD_WRITE_SA,
 285         I40E_NVMUPD_CSUM_CON,
 286         I40E_NVMUPD_CSUM_SA,
 287         I40E_NVMUPD_CSUM_LCB,
 288 };
 289
 290 enum i40e_nvmupd_state {
 291         I40E_NVMUPD_STATE_INIT,
 292         I40E_NVMUPD_STATE_READING,
 293         I40E_NVMUPD_STATE_WRITING
 294 };
 295
 296 /* nvm_access definition and its masks/shifts need to be accessible to
 297  * application, core driver, and shared code.  Where is the right file?
 298  */
 299 #define I40E_NVM_READ   0xB
 300 #define I40E_NVM_WRITE  0xC
 301
 302 #define I40E_NVM_MOD_PNT_MASK 0xFF
 303
 304 #define I40E_NVM_TRANS_SHIFT    8
 305 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 306 #define I40E_NVM_CON            0x0
 307 #define I40E_NVM_SNT            0x1
 308 #define I40E_NVM_LCB            0x2
 309 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 310 #define I40E_NVM_ERA            0x4
 311 #define I40E_NVM_CSUM           0x8
 312
 313 #define I40E_NVM_ADAPT_SHIFT    16
 314 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 315
 316 #define I40E_NVMUPD_MAX_DATA    4096
 317 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 318
 319 struct i40e_nvm_access {
 320         u32 command;
 321         u32 config;
 322         u32 offset;     /* in bytes */
 323         u32 data_size;  /* in bytes */
 324         u8 data[1];
 325 };
 326
 327 /* PCI bus types */
 328 enum i40e_bus_type {
 329         i40e_bus_type_unknown = 0,
 330         i40e_bus_type_pci,
 331         i40e_bus_type_pcix,
 332         i40e_bus_type_pci_express,
 333         i40e_bus_type_reserved
 334 };
 335
 336 /* PCI bus speeds */
 337 enum i40e_bus_speed {
 338         i40e_bus_speed_unknown  = 0,
 339         i40e_bus_speed_33       = 33,
 340         i40e_bus_speed_66       = 66,
 341         i40e_bus_speed_100      = 100,
 342         i40e_bus_speed_120      = 120,
 343         i40e_bus_speed_133      = 133,
 344         i40e_bus_speed_2500     = 2500,
 345         i40e_bus_speed_5000     = 5000,
 346         i40e_bus_speed_8000     = 8000,
 347         i40e_bus_speed_reserved
 348 };
 349
 350 /* PCI bus widths */
 351 enum i40e_bus_width {
 352         i40e_bus_width_unknown  = 0,
 353         i40e_bus_width_pcie_x1  = 1,
 354         i40e_bus_width_pcie_x2  = 2,
 355         i40e_bus_width_pcie_x4  = 4,
 356         i40e_bus_width_pcie_x8  = 8,
 357         i40e_bus_width_32       = 32,
 358         i40e_bus_width_64       = 64,
 359         i40e_bus_width_reserved
 360 };
 361
 362 /* Bus parameters */
 363 struct i40e_bus_info {
 364         enum i40e_bus_speed speed;
 365         enum i40e_bus_width width;
 366         enum i40e_bus_type type;
 367
 368         u16 func;
 369         u16 device;
 370         u16 lan_id;
 371 };
 372
 373 /* Flow control (FC) parameters */
 374 struct i40e_fc_info {
 375         enum i40e_fc_mode current_mode; /* FC mode in effect */
 376         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 377 };
 378
 379 #define I40E_MAX_TRAFFIC_CLASS          8
 380 #define I40E_MAX_USER_PRIORITY          8
 381 #define I40E_DCBX_MAX_APPS              32
 382 #define I40E_LLDPDU_SIZE                1500
 383
 384 /* IEEE 802.1Qaz ETS Configuration data */
 385 struct i40e_ieee_ets_config {
 386         u8 willing;
 387         u8 cbs;
 388         u8 maxtcs;
 389         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 390         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 391         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 392 };
 393
 394 /* IEEE 802.1Qaz ETS Recommendation data */
 395 struct i40e_ieee_ets_recommend {
 396         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 397         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 398         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 399 };
 400
 401 /* IEEE 802.1Qaz PFC Configuration data */
 402 struct i40e_ieee_pfc_config {
 403         u8 willing;
 404         u8 mbc;
 405         u8 pfccap;
 406         u8 pfcenable;
 407 };
 408
 409 /* IEEE 802.1Qaz Application Priority data */
 410 struct i40e_ieee_app_priority_table {
 411         u8  priority;
 412         u8  selector;
 413         u16 protocolid;
 414 };
 415
 416 struct i40e_dcbx_config {
 417         u32 numapps;
 418         struct i40e_ieee_ets_config etscfg;
 419         struct i40e_ieee_ets_recommend etsrec;
 420         struct i40e_ieee_pfc_config pfc;
 421         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 422 };
 423
 424 /* Port hardware description */
 425 struct i40e_hw {
 426         u8 __iomem *hw_addr;
 427         void *back;
 428
 429         /* function pointer structs */
 430         struct i40e_phy_info phy;
 431         struct i40e_mac_info mac;
 432         struct i40e_bus_info bus;
 433         struct i40e_nvm_info nvm;
 434         struct i40e_fc_info fc;
 435
 436         /* pci info */
 437         u16 device_id;
 438         u16 vendor_id;
 439         u16 subsystem_device_id;
 440         u16 subsystem_vendor_id;
 441         u8 revision_id;
 442         u8 port;
 443         bool adapter_stopped;
 444
 445         /* capabilities for entire device and PCI func */
 446         struct i40e_hw_capabilities dev_caps;
 447         struct i40e_hw_capabilities func_caps;
 448
 449         /* Flow Director shared filter space */
 450         u16 fdir_shared_filter_count;
 451
 452         /* device profile info */
 453         u8  pf_id;
 454         u16 main_vsi_seid;
 455
 456         /* Closest numa node to the device */
 457         u16 numa_node;
 458
 459         /* Admin Queue info */
 460         struct i40e_adminq_info aq;
 461
 462         /* state of nvm update process */
 463         enum i40e_nvmupd_state nvmupd_state;
 464
 465         /* HMC info */
 466         struct i40e_hmc_info hmc; /* HMC info struct */
 467
 468         /* LLDP/DCBX Status */
 469         u16 dcbx_status;
 470
 471         /* DCBX info */
 472         struct i40e_dcbx_config local_dcbx_config;
 473         struct i40e_dcbx_config remote_dcbx_config;
 474
 475         /* debug mask */
 476         u32 debug_mask;
 477 };
 478
 479 struct i40e_driver_version {
 480         u8 major_version;
 481         u8 minor_version;
 482         u8 build_version;
 483         u8 subbuild_version;
 484         u8 driver_string[32];
 485 };
 486
 487 /* RX Descriptors */
 488 union i40e_16byte_rx_desc {
 489         struct {
 490                 __le64 pkt_addr; /* Packet buffer address */
 491                 __le64 hdr_addr; /* Header buffer address */
 492         } read;
 493         struct {
 494                 struct {
 495                         struct {
 496                                 union {
 497                                         __le16 mirroring_status;
 498                                         __le16 fcoe_ctx_id;
 499                                 } mirr_fcoe;
 500                                 __le16 l2tag1;
 501                         } lo_dword;
 502                         union {
 503                                 __le32 rss; /* RSS Hash */
 504                                 __le32 fd_id; /* Flow director filter id */
 505                                 __le32 fcoe_param; /* FCoE DDP Context id */
 506                         } hi_dword;
 507                 } qword0;
 508                 struct {
 509                         /* ext status/error/pktype/length */
 510                         __le64 status_error_len;
 511                 } qword1;
 512         } wb;  /* writeback */
 513 };
 514
 515 union i40e_32byte_rx_desc {
 516         struct {
 517                 __le64  pkt_addr; /* Packet buffer address */
 518                 __le64  hdr_addr; /* Header buffer address */
 519                         /* bit 0 of hdr_buffer_addr is DD bit */
 520                 __le64  rsvd1;
 521                 __le64  rsvd2;
 522         } read;
 523         struct {
 524                 struct {
 525                         struct {
 526                                 union {
 527                                         __le16 mirroring_status;
 528                                         __le16 fcoe_ctx_id;
 529                                 } mirr_fcoe;
 530                                 __le16 l2tag1;
 531                         } lo_dword;
 532                         union {
 533                                 __le32 rss; /* RSS Hash */
 534                                 __le32 fcoe_param; /* FCoE DDP Context id */
 535                                 /* Flow director filter id in case of
 536                                  * Programming status desc WB
 537                                  */
 538                                 __le32 fd_id;
 539                         } hi_dword;
 540                 } qword0;
 541                 struct {
 542                         /* status/error/pktype/length */
 543                         __le64 status_error_len;
 544                 } qword1;
 545                 struct {
 546                         __le16 ext_status; /* extended status */
 547                         __le16 rsvd;
 548                         __le16 l2tag2_1;
 549                         __le16 l2tag2_2;
 550                 } qword2;
 551                 struct {
 552                         union {
 553                                 __le32 flex_bytes_lo;
 554                                 __le32 pe_status;
 555                         } lo_dword;
 556                         union {
 557                                 __le32 flex_bytes_hi;
 558                                 __le32 fd_id;
 559                         } hi_dword;
 560                 } qword3;
 561         } wb;  /* writeback */
 562 };
 563
 564 enum i40e_rx_desc_status_bits {
 565         /* Note: These are predefined bit offsets */
 566         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 567         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 568         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 569         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 570         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 571         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 572         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 573         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 574         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 575         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 576         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 577         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 578         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 579         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 580         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 581         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 582 };
 583
 584 #define I40E_RXD_QW1_STATUS_SHIFT       0
 585 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
 586                                          << I40E_RXD_QW1_STATUS_SHIFT)
 587
 588 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 589 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 590                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 591
 592 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 593 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 594                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 595
 596 enum i40e_rx_desc_fltstat_values {
 597         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 598         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 599         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 600         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 601 };
 602
 603 #define I40E_RXD_QW1_ERROR_SHIFT        19
 604 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 605
 606 enum i40e_rx_desc_error_bits {
 607         /* Note: These are predefined bit offsets */
 608         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 609         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 610         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 611         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 612         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 613         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 614         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 615         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 616         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 617 };
 618
 619 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 620         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 621         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 622         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 623         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 624         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 625 };
 626
 627 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 628 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 629
 630 /* Packet type non-ip values */
 631 enum i40e_rx_l2_ptype {
 632         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 633         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 634         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 635         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 636         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 637         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 638         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 639         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 640         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 641         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 642         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 643         I40E_RX_PTYPE_L2_ARP                            = 11,
 644         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 645         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 646         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 647         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 648         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 649         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 650         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 651         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 652         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 653         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 654         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 655         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 656         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 657         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 658 };
 659
 660 struct i40e_rx_ptype_decoded {
 661         u32 ptype:8;
 662         u32 known:1;
 663         u32 outer_ip:1;
 664         u32 outer_ip_ver:1;
 665         u32 outer_frag:1;
 666         u32 tunnel_type:3;
 667         u32 tunnel_end_prot:2;
 668         u32 tunnel_end_frag:1;
 669         u32 inner_prot:4;
 670         u32 payload_layer:3;
 671 };
 672
 673 enum i40e_rx_ptype_outer_ip {
 674         I40E_RX_PTYPE_OUTER_L2  = 0,
 675         I40E_RX_PTYPE_OUTER_IP  = 1
 676 };
 677
 678 enum i40e_rx_ptype_outer_ip_ver {
 679         I40E_RX_PTYPE_OUTER_NONE        = 0,
 680         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 681         I40E_RX_PTYPE_OUTER_IPV6        = 1
 682 };
 683
 684 enum i40e_rx_ptype_outer_fragmented {
 685         I40E_RX_PTYPE_NOT_FRAG  = 0,
 686         I40E_RX_PTYPE_FRAG      = 1
 687 };
 688
 689 enum i40e_rx_ptype_tunnel_type {
 690         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 691         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 692         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 693         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 694         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 695 };
 696
 697 enum i40e_rx_ptype_tunnel_end_prot {
 698         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 699         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 700         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 701 };
 702
 703 enum i40e_rx_ptype_inner_prot {
 704         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 705         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 706         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 707         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 708         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 709         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 710 };
 711
 712 enum i40e_rx_ptype_payload_layer {
 713         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 714         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 715         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 716         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 717 };
 718
 719 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 720 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 721                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 722
 723 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 724 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 725                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 726
 727 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 728 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 729                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 730
 731 enum i40e_rx_desc_ext_status_bits {
 732         /* Note: These are predefined bit offsets */
 733         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 734         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 735         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 736         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 737         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 738         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 739         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 740 };
 741
 742 enum i40e_rx_desc_pe_status_bits {
 743         /* Note: These are predefined bit offsets */
 744         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 745         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 746         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 747         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 748         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 749         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 750         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 751         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 752         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 753 };
 754
 755 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 756 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 757
 758 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 759 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 760                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 761
 762 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 763 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 764                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 765
 766 enum i40e_rx_prog_status_desc_status_bits {
 767         /* Note: These are predefined bit offsets */
 768         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 769         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 770 };
 771
 772 enum i40e_rx_prog_status_desc_prog_id_masks {
 773         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 774         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 775         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 776 };
 777
 778 enum i40e_rx_prog_status_desc_error_bits {
 779         /* Note: These are predefined bit offsets */
 780         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 781         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 782         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 783         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 784 };
 785
 786 /* TX Descriptor */
 787 struct i40e_tx_desc {
 788         __le64 buffer_addr; /* Address of descriptor's data buf */
 789         __le64 cmd_type_offset_bsz;
 790 };
 791
 792 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 793 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 794
 795 enum i40e_tx_desc_dtype_value {
 796         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 797         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 798         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 799         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 800         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 801         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 802         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 803         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 804         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 805         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 806 };
 807
 808 #define I40E_TXD_QW1_CMD_SHIFT  4
 809 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 810
 811 enum i40e_tx_desc_cmd_bits {
 812         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 813         I40E_TX_DESC_CMD_RS                     = 0x0002,
 814         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 815         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 816         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 817         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 818         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 819         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 820         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 821         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 822         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 823         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 824         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 825         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 826         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 827         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 828         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 829         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 830 };
 831
 832 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 833 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 834                                          I40E_TXD_QW1_OFFSET_SHIFT)
 835
 836 enum i40e_tx_desc_length_fields {
 837         /* Note: These are predefined bit offsets */
 838         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 839         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 840         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 841 };
 842
 843 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 844 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 845                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 846
 847 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 848 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 849
 850 /* Context descriptors */
 851 struct i40e_tx_context_desc {
 852         __le32 tunneling_params;
 853         __le16 l2tag2;
 854         __le16 rsvd;
 855         __le64 type_cmd_tso_mss;
 856 };
 857
 858 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 859 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 860
 861 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 862 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 863
 864 enum i40e_tx_ctx_desc_cmd_bits {
 865         I40E_TX_CTX_DESC_TSO            = 0x01,
 866         I40E_TX_CTX_DESC_TSYN           = 0x02,
 867         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 868         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 869         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 870         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 871         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 872         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 873         I40E_TX_CTX_DESC_SWPE           = 0x40
 874 };
 875
 876 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 877 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 878                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 879
 880 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 881 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 882                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 883
 884 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 885 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 886
 887 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 888 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 889                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 890
 891 enum i40e_tx_ctx_desc_eipt_offload {
 892         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 893         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 894         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 895         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 896 };
 897
 898 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 899 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 900                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 901
 902 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 903 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 904
 905 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 906 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 907
 908 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 909 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
 910                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 911
 912 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 913
 914 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 915 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 916                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 917
 918 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 919 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 920                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 921
 922 struct i40e_filter_program_desc {
 923         __le32 qindex_flex_ptype_vsi;
 924         __le32 rsvd;
 925         __le32 dtype_cmd_cntindex;
 926         __le32 fd_id;
 927 };
 928 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 929 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 930                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 931 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 932 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 933                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 934 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 935 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 936                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 937
 938 /* Packet Classifier Types for filters */
 939 enum i40e_filter_pctype {
 940         /* Note: Values 0-30 are reserved for future use */
 941         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 942         /* Note: Value 32 is reserved for future use */
 943         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 944         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 945         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 946         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 947         /* Note: Values 37-40 are reserved for future use */
 948         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 949         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 950         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 951         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 952         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 953         /* Note: Value 47 is reserved for future use */
 954         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
 955         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
 956         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
 957         /* Note: Values 51-62 are reserved for future use */
 958         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 959 };
 960
 961 enum i40e_filter_program_desc_dest {
 962         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
 963         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
 964         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
 965 };
 966
 967 enum i40e_filter_program_desc_fd_status {
 968         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
 969         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
 970         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
 971         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
 972 };
 973
 974 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
 975 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
 976                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
 977
 978 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
 979 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
 980                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
 981
 982 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 983 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
 984
 985 enum i40e_filter_program_desc_pcmd {
 986         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
 987         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
 988 };
 989
 990 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 991 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
 992
 993 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 994 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
 995                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
 996
 997 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
 998                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
 999 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1000                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1001
1002 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1003 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1004                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1005
1006 enum i40e_filter_type {
1007         I40E_FLOW_DIRECTOR_FLTR = 0,
1008         I40E_PE_QUAD_HASH_FLTR = 1,
1009         I40E_ETHERTYPE_FLTR,
1010         I40E_FCOE_CTX_FLTR,
1011         I40E_MAC_VLAN_FLTR,
1012         I40E_HASH_FLTR
1013 };
1014
1015 struct i40e_vsi_context {
1016         u16 seid;
1017         u16 uplink_seid;
1018         u16 vsi_number;
1019         u16 vsis_allocated;
1020         u16 vsis_unallocated;
1021         u16 flags;
1022         u8 pf_num;
1023         u8 vf_num;
1024         u8 connection_type;
1025         struct i40e_aqc_vsi_properties_data info;
1026 };
1027
1028 struct i40e_veb_context {
1029         u16 seid;
1030         u16 uplink_seid;
1031         u16 veb_number;
1032         u16 vebs_allocated;
1033         u16 vebs_unallocated;
1034         u16 flags;
1035         struct i40e_aqc_get_veb_parameters_completion info;
1036 };
1037
1038 /* Statistics collected by each port, VSI, VEB, and S-channel */
1039 struct i40e_eth_stats {
1040         u64 rx_bytes;                   /* gorc */
1041         u64 rx_unicast;                 /* uprc */
1042         u64 rx_multicast;               /* mprc */
1043         u64 rx_broadcast;               /* bprc */
1044         u64 rx_discards;                /* rdpc */
1045         u64 rx_unknown_protocol;        /* rupp */
1046         u64 tx_bytes;                   /* gotc */
1047         u64 tx_unicast;                 /* uptc */
1048         u64 tx_multicast;               /* mptc */
1049         u64 tx_broadcast;               /* bptc */
1050         u64 tx_discards;                /* tdpc */
1051         u64 tx_errors;                  /* tepc */
1052 };
1053
1054 #ifdef I40E_FCOE
1055 /* Statistics collected per function for FCoE */
1056 struct i40e_fcoe_stats {
1057         u64 rx_fcoe_packets;            /* fcoeprc */
1058         u64 rx_fcoe_dwords;             /* focedwrc */
1059         u64 rx_fcoe_dropped;            /* fcoerpdc */
1060         u64 tx_fcoe_packets;            /* fcoeptc */
1061         u64 tx_fcoe_dwords;             /* focedwtc */
1062         u64 fcoe_bad_fccrc;             /* fcoecrc */
1063         u64 fcoe_last_error;            /* fcoelast */
1064         u64 fcoe_ddp_count;             /* fcoeddpc */
1065 };
1066
1067 /* offset to per function FCoE statistics block */
1068 #define I40E_FCOE_VF_STAT_OFFSET        0
1069 #define I40E_FCOE_PF_STAT_OFFSET        128
1070 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1071
1072 #endif
1073 /* Statistics collected by the MAC */
1074 struct i40e_hw_port_stats {
1075         /* eth stats collected by the port */
1076         struct i40e_eth_stats eth;
1077
1078         /* additional port specific stats */
1079         u64 tx_dropped_link_down;       /* tdold */
1080         u64 crc_errors;                 /* crcerrs */
1081         u64 illegal_bytes;              /* illerrc */
1082         u64 error_bytes;                /* errbc */
1083         u64 mac_local_faults;           /* mlfc */
1084         u64 mac_remote_faults;          /* mrfc */
1085         u64 rx_length_errors;           /* rlec */
1086         u64 link_xon_rx;                /* lxonrxc */
1087         u64 link_xoff_rx;               /* lxoffrxc */
1088         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1089         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1090         u64 link_xon_tx;                /* lxontxc */
1091         u64 link_xoff_tx;               /* lxofftxc */
1092         u64 priority_xon_tx[8];         /* pxontxc[8] */
1093         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1094         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1095         u64 rx_size_64;                 /* prc64 */
1096         u64 rx_size_127;                /* prc127 */
1097         u64 rx_size_255;                /* prc255 */
1098         u64 rx_size_511;                /* prc511 */
1099         u64 rx_size_1023;               /* prc1023 */
1100         u64 rx_size_1522;               /* prc1522 */
1101         u64 rx_size_big;                /* prc9522 */
1102         u64 rx_undersize;               /* ruc */
1103         u64 rx_fragments;               /* rfc */
1104         u64 rx_oversize;                /* roc */
1105         u64 rx_jabber;                  /* rjc */
1106         u64 tx_size_64;                 /* ptc64 */
1107         u64 tx_size_127;                /* ptc127 */
1108         u64 tx_size_255;                /* ptc255 */
1109         u64 tx_size_511;                /* ptc511 */
1110         u64 tx_size_1023;               /* ptc1023 */
1111         u64 tx_size_1522;               /* ptc1522 */
1112         u64 tx_size_big;                /* ptc9522 */
1113         u64 mac_short_packet_dropped;   /* mspdc */
1114         u64 checksum_error;             /* xec */
1115         /* flow director stats */
1116         u64 fd_atr_match;
1117         u64 fd_sb_match;
1118         /* EEE LPI */
1119         u32 tx_lpi_status;
1120         u32 rx_lpi_status;
1121         u64 tx_lpi_count;               /* etlpic */
1122         u64 rx_lpi_count;               /* erlpic */
1123 };
1124
1125 /* Checksum and Shadow RAM pointers */
1126 #define I40E_SR_NVM_CONTROL_WORD                0x00
1127 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1128 #define I40E_SR_NVM_IMAGE_VERSION               0x18
1129 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1130 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1131 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1132 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1133 #define I40E_SR_VPD_PTR                         0x2F
1134 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1135 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1136
1137 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1138 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1139 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1140 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1141 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1142
1143 /* Shadow RAM related */
1144 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1145 #define I40E_SR_WORDS_IN_1KB            512
1146 /* Checksum should be calculated such that after adding all the words,
1147  * including the checksum word itself, the sum should be 0xBABA.
1148  */
1149 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1150
1151 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1152
1153 #ifdef I40E_FCOE
1154 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1155
1156 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1157         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1158         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1159         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1160         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1161         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1162         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1163         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1164         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1165         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1166         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1167         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1168         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1169         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1170 };
1171
1172 /* FCoE DDP Context descriptor */
1173 struct i40e_fcoe_ddp_context_desc {
1174         __le64 rsvd;
1175         __le64 type_cmd_foff_lsize;
1176 };
1177
1178 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1179 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1180                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1181
1182 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1183 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1184                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1185
1186 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1187         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1188         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1189         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1190         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1191         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1192         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1193 };
1194
1195 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1196 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1197                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1198
1199 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1200 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1201                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1202
1203 /* FCoE DDP/DWO Queue Context descriptor */
1204 struct i40e_fcoe_queue_context_desc {
1205         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1206         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1207 };
1208
1209 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1210 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1211                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1212
1213 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1214 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1215                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1216
1217 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1218 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1219                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1220
1221 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1222 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1223                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1224
1225 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1226         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1227         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1228 };
1229
1230 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1231 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1232                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1233
1234 /* FCoE DDP/DWO Filter Context descriptor */
1235 struct i40e_fcoe_filter_context_desc {
1236         __le32 param;
1237         __le16 seqn;
1238
1239         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1240         __le16 rsvd_dmaindx;
1241
1242         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1243         __le64 flags_rsvd_lanq;
1244 };
1245
1246 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1247 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1248                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1249
1250 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1251         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1252         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1253         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1254         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1255         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1256         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1257 };
1258
1259 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1260 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1261                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1262
1263 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1264 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1265                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1266
1267 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1268 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1269                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1270
1271 #endif /* I40E_FCOE */
1272 enum i40e_switch_element_types {
1273         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1274         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1275         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1276         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1277         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1278         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1279         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1280         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1281         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1282 };
1283
1284 /* Supported EtherType filters */
1285 enum i40e_ether_type_index {
1286         I40E_ETHER_TYPE_1588            = 0,
1287         I40E_ETHER_TYPE_FIP             = 1,
1288         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1289         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1290         I40E_ETHER_TYPE_LLDP            = 4,
1291         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1292         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1293         I40E_ETHER_TYPE_QCN_CNM         = 7,
1294         I40E_ETHER_TYPE_8021X           = 8,
1295         I40E_ETHER_TYPE_ARP             = 9,
1296         I40E_ETHER_TYPE_RSV1            = 10,
1297         I40E_ETHER_TYPE_RSV2            = 11,
1298 };
1299
1300 /* Filter context base size is 1K */
1301 #define I40E_HASH_FILTER_BASE_SIZE      1024
1302 /* Supported Hash filter values */
1303 enum i40e_hash_filter_size {
1304         I40E_HASH_FILTER_SIZE_1K        = 0,
1305         I40E_HASH_FILTER_SIZE_2K        = 1,
1306         I40E_HASH_FILTER_SIZE_4K        = 2,
1307         I40E_HASH_FILTER_SIZE_8K        = 3,
1308         I40E_HASH_FILTER_SIZE_16K       = 4,
1309         I40E_HASH_FILTER_SIZE_32K       = 5,
1310         I40E_HASH_FILTER_SIZE_64K       = 6,
1311         I40E_HASH_FILTER_SIZE_128K      = 7,
1312         I40E_HASH_FILTER_SIZE_256K      = 8,
1313         I40E_HASH_FILTER_SIZE_512K      = 9,
1314         I40E_HASH_FILTER_SIZE_1M        = 10,
1315 };
1316
1317 /* DMA context base size is 0.5K */
1318 #define I40E_DMA_CNTX_BASE_SIZE         512
1319 /* Supported DMA context values */
1320 enum i40e_dma_cntx_size {
1321         I40E_DMA_CNTX_SIZE_512          = 0,
1322         I40E_DMA_CNTX_SIZE_1K           = 1,
1323         I40E_DMA_CNTX_SIZE_2K           = 2,
1324         I40E_DMA_CNTX_SIZE_4K           = 3,
1325         I40E_DMA_CNTX_SIZE_8K           = 4,
1326         I40E_DMA_CNTX_SIZE_16K          = 5,
1327         I40E_DMA_CNTX_SIZE_32K          = 6,
1328         I40E_DMA_CNTX_SIZE_64K          = 7,
1329         I40E_DMA_CNTX_SIZE_128K         = 8,
1330         I40E_DMA_CNTX_SIZE_256K         = 9,
1331 };
1332
1333 /* Supported Hash look up table (LUT) sizes */
1334 enum i40e_hash_lut_size {
1335         I40E_HASH_LUT_SIZE_128          = 0,
1336         I40E_HASH_LUT_SIZE_512          = 1,
1337 };
1338
1339 /* Structure to hold a per PF filter control settings */
1340 struct i40e_filter_control_settings {
1341         /* number of PE Quad Hash filter buckets */
1342         enum i40e_hash_filter_size pe_filt_num;
1343         /* number of PE Quad Hash contexts */
1344         enum i40e_dma_cntx_size pe_cntx_num;
1345         /* number of FCoE filter buckets */
1346         enum i40e_hash_filter_size fcoe_filt_num;
1347         /* number of FCoE DDP contexts */
1348         enum i40e_dma_cntx_size fcoe_cntx_num;
1349         /* size of the Hash LUT */
1350         enum i40e_hash_lut_size hash_lut_size;
1351         /* enable FDIR filters for PF and its VFs */
1352         bool enable_fdir;
1353         /* enable Ethertype filters for PF and its VFs */
1354         bool enable_ethtype;
1355         /* enable MAC/VLAN filters for PF and its VFs */
1356         bool enable_macvlan;
1357 };
1358
1359 /* Structure to hold device level control filter counts */
1360 struct i40e_control_filter_stats {
1361         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1362         u16 etype_used;       /* Used perfect EtherType filters */
1363         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1364         u16 etype_free;       /* Un-used perfect EtherType filters */
1365 };
1366
1367 enum i40e_reset_type {
1368         I40E_RESET_POR          = 0,
1369         I40E_RESET_CORER        = 1,
1370         I40E_RESET_GLOBR        = 2,
1371         I40E_RESET_EMPR         = 3,
1372 };
1373
1374 /* RSS Hash Table Size */
1375 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1376 #endif /* _I40E_TYPE_H_ */