drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2015 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36
  37 /* Device IDs */
  38 #define I40E_DEV_ID_SFP_XL710           0x1572
  39 #define I40E_DEV_ID_QEMU                0x1574
  40 #define I40E_DEV_ID_KX_A                0x157F
  41 #define I40E_DEV_ID_KX_B                0x1580
  42 #define I40E_DEV_ID_KX_C                0x1581
  43 #define I40E_DEV_ID_QSFP_A              0x1583
  44 #define I40E_DEV_ID_QSFP_B              0x1584
  45 #define I40E_DEV_ID_QSFP_C              0x1585
  46 #define I40E_DEV_ID_10G_BASE_T          0x1586
  47 #define I40E_DEV_ID_20G_KR2             0x1587
  48 #define I40E_DEV_ID_VF                  0x154C
  49 #define I40E_DEV_ID_VF_HV               0x1571
  50
  51 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  52                                          (d) == I40E_DEV_ID_QSFP_B  || \
  53                                          (d) == I40E_DEV_ID_QSFP_C)
  54
  55 /* I40E_MASK is a macro used on 32 bit registers */
  56 #define I40E_MASK(mask, shift) (mask << shift)
  57
  58 #define I40E_MAX_VSI_QP                 16
  59 #define I40E_MAX_VF_VSI                 3
  60 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  62
  63 /* Max default timeout in ms, */
  64 #define I40E_MAX_NVM_TIMEOUT            18000
  65
  66 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  67 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  68
  69 /* forward declaration */
  70 struct i40e_hw;
  71 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  72
  73 /* Data type manipulation macros. */
  74
  75 #define I40E_DESC_UNUSED(R)     \
  76         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  77         (R)->next_to_clean - (R)->next_to_use - 1)
  78
  79 /* bitfields for Tx queue mapping in QTX_CTL */
  80 #define I40E_QTX_CTL_VF_QUEUE   0x0
  81 #define I40E_QTX_CTL_VM_QUEUE   0x1
  82 #define I40E_QTX_CTL_PF_QUEUE   0x2
  83
  84 /* debug masks - set these bits in hw->debug_mask to control output */
  85 enum i40e_debug_mask {
  86         I40E_DEBUG_INIT                 = 0x00000001,
  87         I40E_DEBUG_RELEASE              = 0x00000002,
  88
  89         I40E_DEBUG_LINK                 = 0x00000010,
  90         I40E_DEBUG_PHY                  = 0x00000020,
  91         I40E_DEBUG_HMC                  = 0x00000040,
  92         I40E_DEBUG_NVM                  = 0x00000080,
  93         I40E_DEBUG_LAN                  = 0x00000100,
  94         I40E_DEBUG_FLOW                 = 0x00000200,
  95         I40E_DEBUG_DCB                  = 0x00000400,
  96         I40E_DEBUG_DIAG                 = 0x00000800,
  97         I40E_DEBUG_FD                   = 0x00001000,
  98
  99         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 100         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 101         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 102         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 103         I40E_DEBUG_AQ                   = 0x0F000000,
 104
 105         I40E_DEBUG_USER                 = 0xF0000000,
 106
 107         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 108 };
 109
 110 /* These are structs for managing the hardware information and the operations.
 111  * The structures of function pointers are filled out at init time when we
 112  * know for sure exactly which hardware we're working with.  This gives us the
 113  * flexibility of using the same main driver code but adapting to slightly
 114  * different hardware needs as new parts are developed.  For this architecture,
 115  * the Firmware and AdminQ are intended to insulate the driver from most of the
 116  * future changes, but these structures will also do part of the job.
 117  */
 118 enum i40e_mac_type {
 119         I40E_MAC_UNKNOWN = 0,
 120         I40E_MAC_X710,
 121         I40E_MAC_XL710,
 122         I40E_MAC_VF,
 123         I40E_MAC_GENERIC,
 124 };
 125
 126 enum i40e_media_type {
 127         I40E_MEDIA_TYPE_UNKNOWN = 0,
 128         I40E_MEDIA_TYPE_FIBER,
 129         I40E_MEDIA_TYPE_BASET,
 130         I40E_MEDIA_TYPE_BACKPLANE,
 131         I40E_MEDIA_TYPE_CX4,
 132         I40E_MEDIA_TYPE_DA,
 133         I40E_MEDIA_TYPE_VIRTUAL
 134 };
 135
 136 enum i40e_fc_mode {
 137         I40E_FC_NONE = 0,
 138         I40E_FC_RX_PAUSE,
 139         I40E_FC_TX_PAUSE,
 140         I40E_FC_FULL,
 141         I40E_FC_PFC,
 142         I40E_FC_DEFAULT
 143 };
 144
 145 enum i40e_set_fc_aq_failures {
 146         I40E_SET_FC_AQ_FAIL_NONE = 0,
 147         I40E_SET_FC_AQ_FAIL_GET = 1,
 148         I40E_SET_FC_AQ_FAIL_SET = 2,
 149         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 150         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 151 };
 152
 153 enum i40e_vsi_type {
 154         I40E_VSI_MAIN = 0,
 155         I40E_VSI_VMDQ1,
 156         I40E_VSI_VMDQ2,
 157         I40E_VSI_CTRL,
 158         I40E_VSI_FCOE,
 159         I40E_VSI_MIRROR,
 160         I40E_VSI_SRIOV,
 161         I40E_VSI_FDIR,
 162         I40E_VSI_TYPE_UNKNOWN
 163 };
 164
 165 enum i40e_queue_type {
 166         I40E_QUEUE_TYPE_RX = 0,
 167         I40E_QUEUE_TYPE_TX,
 168         I40E_QUEUE_TYPE_PE_CEQ,
 169         I40E_QUEUE_TYPE_UNKNOWN
 170 };
 171
 172 struct i40e_link_status {
 173         enum i40e_aq_phy_type phy_type;
 174         enum i40e_aq_link_speed link_speed;
 175         u8 link_info;
 176         u8 an_info;
 177         u8 ext_info;
 178         u8 loopback;
 179         /* is Link Status Event notification to SW enabled */
 180         bool lse_enable;
 181         u16 max_frame_size;
 182         bool crc_enable;
 183         u8 pacing;
 184         u8 requested_speeds;
 185 };
 186
 187 struct i40e_phy_info {
 188         struct i40e_link_status link_info;
 189         struct i40e_link_status link_info_old;
 190         u32 autoneg_advertised;
 191         u32 phy_id;
 192         u32 module_type;
 193         bool get_link_info;
 194         enum i40e_media_type media_type;
 195 };
 196
 197 #define I40E_HW_CAP_MAX_GPIO                    30
 198 /* Capabilities of a PF or a VF or the whole device */
 199 struct i40e_hw_capabilities {
 200         u32  switch_mode;
 201 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 202 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 203 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 204
 205         u32  management_mode;
 206         u32  npar_enable;
 207         u32  os2bmc;
 208         u32  valid_functions;
 209         bool sr_iov_1_1;
 210         bool vmdq;
 211         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 212         bool evb_802_1_qbh; /* Bridge Port Extension */
 213         bool dcb;
 214         bool fcoe;
 215         bool iscsi; /* Indicates iSCSI enabled */
 216         bool flex10_enable;
 217         bool flex10_capable;
 218         u32  flex10_mode;
 219 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 220 #define I40E_FLEX10_MODE_DCC            0x1
 221 #define I40E_FLEX10_MODE_DCI            0x2
 222
 223         u32 flex10_status;
 224 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 225 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 226
 227         bool mgmt_cem;
 228         bool ieee_1588;
 229         bool iwarp;
 230         bool fd;
 231         u32 fd_filters_guaranteed;
 232         u32 fd_filters_best_effort;
 233         bool rss;
 234         u32 rss_table_size;
 235         u32 rss_table_entry_width;
 236         bool led[I40E_HW_CAP_MAX_GPIO];
 237         bool sdp[I40E_HW_CAP_MAX_GPIO];
 238         u32 nvm_image_type;
 239         u32 num_flow_director_filters;
 240         u32 num_vfs;
 241         u32 vf_base_id;
 242         u32 num_vsis;
 243         u32 num_rx_qp;
 244         u32 num_tx_qp;
 245         u32 base_queue;
 246         u32 num_msix_vectors;
 247         u32 num_msix_vectors_vf;
 248         u32 led_pin_num;
 249         u32 sdp_pin_num;
 250         u32 mdio_port_num;
 251         u32 mdio_port_mode;
 252         u8 rx_buf_chain_len;
 253         u32 enabled_tcmap;
 254         u32 maxtc;
 255         u64 wr_csr_prot;
 256 };
 257
 258 struct i40e_mac_info {
 259         enum i40e_mac_type type;
 260         u8 addr[ETH_ALEN];
 261         u8 perm_addr[ETH_ALEN];
 262         u8 san_addr[ETH_ALEN];
 263         u8 port_addr[ETH_ALEN];
 264         u16 max_fcoeq;
 265 };
 266
 267 enum i40e_aq_resources_ids {
 268         I40E_NVM_RESOURCE_ID = 1
 269 };
 270
 271 enum i40e_aq_resource_access_type {
 272         I40E_RESOURCE_READ = 1,
 273         I40E_RESOURCE_WRITE
 274 };
 275
 276 struct i40e_nvm_info {
 277         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 278         u32 timeout;              /* [ms] */
 279         u16 sr_size;              /* Shadow RAM size in words */
 280         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 281         u16 version;              /* NVM package version */
 282         u32 eetrack;              /* NVM data version */
 283 };
 284
 285 /* definitions used in NVM update support */
 286
 287 enum i40e_nvmupd_cmd {
 288         I40E_NVMUPD_INVALID,
 289         I40E_NVMUPD_READ_CON,
 290         I40E_NVMUPD_READ_SNT,
 291         I40E_NVMUPD_READ_LCB,
 292         I40E_NVMUPD_READ_SA,
 293         I40E_NVMUPD_WRITE_ERA,
 294         I40E_NVMUPD_WRITE_CON,
 295         I40E_NVMUPD_WRITE_SNT,
 296         I40E_NVMUPD_WRITE_LCB,
 297         I40E_NVMUPD_WRITE_SA,
 298         I40E_NVMUPD_CSUM_CON,
 299         I40E_NVMUPD_CSUM_SA,
 300         I40E_NVMUPD_CSUM_LCB,
 301 };
 302
 303 enum i40e_nvmupd_state {
 304         I40E_NVMUPD_STATE_INIT,
 305         I40E_NVMUPD_STATE_READING,
 306         I40E_NVMUPD_STATE_WRITING
 307 };
 308
 309 /* nvm_access definition and its masks/shifts need to be accessible to
 310  * application, core driver, and shared code.  Where is the right file?
 311  */
 312 #define I40E_NVM_READ   0xB
 313 #define I40E_NVM_WRITE  0xC
 314
 315 #define I40E_NVM_MOD_PNT_MASK 0xFF
 316
 317 #define I40E_NVM_TRANS_SHIFT    8
 318 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 319 #define I40E_NVM_CON            0x0
 320 #define I40E_NVM_SNT            0x1
 321 #define I40E_NVM_LCB            0x2
 322 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 323 #define I40E_NVM_ERA            0x4
 324 #define I40E_NVM_CSUM           0x8
 325
 326 #define I40E_NVM_ADAPT_SHIFT    16
 327 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 328
 329 #define I40E_NVMUPD_MAX_DATA    4096
 330 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 331
 332 struct i40e_nvm_access {
 333         u32 command;
 334         u32 config;
 335         u32 offset;     /* in bytes */
 336         u32 data_size;  /* in bytes */
 337         u8 data[1];
 338 };
 339
 340 /* PCI bus types */
 341 enum i40e_bus_type {
 342         i40e_bus_type_unknown = 0,
 343         i40e_bus_type_pci,
 344         i40e_bus_type_pcix,
 345         i40e_bus_type_pci_express,
 346         i40e_bus_type_reserved
 347 };
 348
 349 /* PCI bus speeds */
 350 enum i40e_bus_speed {
 351         i40e_bus_speed_unknown  = 0,
 352         i40e_bus_speed_33       = 33,
 353         i40e_bus_speed_66       = 66,
 354         i40e_bus_speed_100      = 100,
 355         i40e_bus_speed_120      = 120,
 356         i40e_bus_speed_133      = 133,
 357         i40e_bus_speed_2500     = 2500,
 358         i40e_bus_speed_5000     = 5000,
 359         i40e_bus_speed_8000     = 8000,
 360         i40e_bus_speed_reserved
 361 };
 362
 363 /* PCI bus widths */
 364 enum i40e_bus_width {
 365         i40e_bus_width_unknown  = 0,
 366         i40e_bus_width_pcie_x1  = 1,
 367         i40e_bus_width_pcie_x2  = 2,
 368         i40e_bus_width_pcie_x4  = 4,
 369         i40e_bus_width_pcie_x8  = 8,
 370         i40e_bus_width_32       = 32,
 371         i40e_bus_width_64       = 64,
 372         i40e_bus_width_reserved
 373 };
 374
 375 /* Bus parameters */
 376 struct i40e_bus_info {
 377         enum i40e_bus_speed speed;
 378         enum i40e_bus_width width;
 379         enum i40e_bus_type type;
 380
 381         u16 func;
 382         u16 device;
 383         u16 lan_id;
 384 };
 385
 386 /* Flow control (FC) parameters */
 387 struct i40e_fc_info {
 388         enum i40e_fc_mode current_mode; /* FC mode in effect */
 389         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 390 };
 391
 392 #define I40E_MAX_TRAFFIC_CLASS          8
 393 #define I40E_MAX_USER_PRIORITY          8
 394 #define I40E_DCBX_MAX_APPS              32
 395 #define I40E_LLDPDU_SIZE                1500
 396 #define I40E_TLV_STATUS_OPER            0x1
 397 #define I40E_TLV_STATUS_SYNC            0x2
 398 #define I40E_TLV_STATUS_ERR             0x4
 399 #define I40E_CEE_OPER_MAX_APPS          3
 400 #define I40E_APP_PROTOID_FCOE           0x8906
 401 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 402 #define I40E_APP_PROTOID_FIP            0x8914
 403 #define I40E_APP_SEL_ETHTYPE            0x1
 404 #define I40E_APP_SEL_TCPIP              0x2
 405
 406 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 407 struct i40e_dcb_ets_config {
 408         u8 willing;
 409         u8 cbs;
 410         u8 maxtcs;
 411         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 412         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 413         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 414 };
 415
 416 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 417 struct i40e_dcb_pfc_config {
 418         u8 willing;
 419         u8 mbc;
 420         u8 pfccap;
 421         u8 pfcenable;
 422 };
 423
 424 /* CEE or IEEE 802.1Qaz Application Priority data */
 425 struct i40e_dcb_app_priority_table {
 426         u8  priority;
 427         u8  selector;
 428         u16 protocolid;
 429 };
 430
 431 struct i40e_dcbx_config {
 432         u8  dcbx_mode;
 433 #define I40E_DCBX_MODE_CEE      0x1
 434 #define I40E_DCBX_MODE_IEEE     0x2
 435         u32 numapps;
 436         struct i40e_dcb_ets_config etscfg;
 437         struct i40e_dcb_ets_config etsrec;
 438         struct i40e_dcb_pfc_config pfc;
 439         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 440 };
 441
 442 /* Port hardware description */
 443 struct i40e_hw {
 444         u8 __iomem *hw_addr;
 445         void *back;
 446
 447         /* subsystem structs */
 448         struct i40e_phy_info phy;
 449         struct i40e_mac_info mac;
 450         struct i40e_bus_info bus;
 451         struct i40e_nvm_info nvm;
 452         struct i40e_fc_info fc;
 453
 454         /* pci info */
 455         u16 device_id;
 456         u16 vendor_id;
 457         u16 subsystem_device_id;
 458         u16 subsystem_vendor_id;
 459         u8 revision_id;
 460         u8 port;
 461         bool adapter_stopped;
 462
 463         /* capabilities for entire device and PCI func */
 464         struct i40e_hw_capabilities dev_caps;
 465         struct i40e_hw_capabilities func_caps;
 466
 467         /* Flow Director shared filter space */
 468         u16 fdir_shared_filter_count;
 469
 470         /* device profile info */
 471         u8  pf_id;
 472         u16 main_vsi_seid;
 473
 474         /* for multi-function MACs */
 475         u16 partition_id;
 476         u16 num_partitions;
 477         u16 num_ports;
 478
 479         /* Closest numa node to the device */
 480         u16 numa_node;
 481
 482         /* Admin Queue info */
 483         struct i40e_adminq_info aq;
 484
 485         /* state of nvm update process */
 486         enum i40e_nvmupd_state nvmupd_state;
 487
 488         /* HMC info */
 489         struct i40e_hmc_info hmc; /* HMC info struct */
 490
 491         /* LLDP/DCBX Status */
 492         u16 dcbx_status;
 493
 494         /* DCBX info */
 495         struct i40e_dcbx_config local_dcbx_config;
 496         struct i40e_dcbx_config remote_dcbx_config;
 497
 498         /* debug mask */
 499         u32 debug_mask;
 500         char err_str[16];
 501 };
 502
 503 static inline bool i40e_is_vf(struct i40e_hw *hw)
 504 {
 505         return hw->mac.type == I40E_MAC_VF;
 506 }
 507
 508 struct i40e_driver_version {
 509         u8 major_version;
 510         u8 minor_version;
 511         u8 build_version;
 512         u8 subbuild_version;
 513         u8 driver_string[32];
 514 };
 515
 516 /* RX Descriptors */
 517 union i40e_16byte_rx_desc {
 518         struct {
 519                 __le64 pkt_addr; /* Packet buffer address */
 520                 __le64 hdr_addr; /* Header buffer address */
 521         } read;
 522         struct {
 523                 struct {
 524                         struct {
 525                                 union {
 526                                         __le16 mirroring_status;
 527                                         __le16 fcoe_ctx_id;
 528                                 } mirr_fcoe;
 529                                 __le16 l2tag1;
 530                         } lo_dword;
 531                         union {
 532                                 __le32 rss; /* RSS Hash */
 533                                 __le32 fd_id; /* Flow director filter id */
 534                                 __le32 fcoe_param; /* FCoE DDP Context id */
 535                         } hi_dword;
 536                 } qword0;
 537                 struct {
 538                         /* ext status/error/pktype/length */
 539                         __le64 status_error_len;
 540                 } qword1;
 541         } wb;  /* writeback */
 542 };
 543
 544 union i40e_32byte_rx_desc {
 545         struct {
 546                 __le64  pkt_addr; /* Packet buffer address */
 547                 __le64  hdr_addr; /* Header buffer address */
 548                         /* bit 0 of hdr_buffer_addr is DD bit */
 549                 __le64  rsvd1;
 550                 __le64  rsvd2;
 551         } read;
 552         struct {
 553                 struct {
 554                         struct {
 555                                 union {
 556                                         __le16 mirroring_status;
 557                                         __le16 fcoe_ctx_id;
 558                                 } mirr_fcoe;
 559                                 __le16 l2tag1;
 560                         } lo_dword;
 561                         union {
 562                                 __le32 rss; /* RSS Hash */
 563                                 __le32 fcoe_param; /* FCoE DDP Context id */
 564                                 /* Flow director filter id in case of
 565                                  * Programming status desc WB
 566                                  */
 567                                 __le32 fd_id;
 568                         } hi_dword;
 569                 } qword0;
 570                 struct {
 571                         /* status/error/pktype/length */
 572                         __le64 status_error_len;
 573                 } qword1;
 574                 struct {
 575                         __le16 ext_status; /* extended status */
 576                         __le16 rsvd;
 577                         __le16 l2tag2_1;
 578                         __le16 l2tag2_2;
 579                 } qword2;
 580                 struct {
 581                         union {
 582                                 __le32 flex_bytes_lo;
 583                                 __le32 pe_status;
 584                         } lo_dword;
 585                         union {
 586                                 __le32 flex_bytes_hi;
 587                                 __le32 fd_id;
 588                         } hi_dword;
 589                 } qword3;
 590         } wb;  /* writeback */
 591 };
 592
 593 enum i40e_rx_desc_status_bits {
 594         /* Note: These are predefined bit offsets */
 595         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 596         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 597         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 598         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 599         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 600         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 601         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 602         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 603         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 604         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 605         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 606         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 607         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 608         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 609         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 610         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 611 };
 612
 613 #define I40E_RXD_QW1_STATUS_SHIFT       0
 614 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 615                                          << I40E_RXD_QW1_STATUS_SHIFT)
 616
 617 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 618 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 619                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 620
 621 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 622 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 623                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 624
 625 enum i40e_rx_desc_fltstat_values {
 626         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 627         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 628         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 629         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 630 };
 631
 632 #define I40E_RXD_QW1_ERROR_SHIFT        19
 633 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 634
 635 enum i40e_rx_desc_error_bits {
 636         /* Note: These are predefined bit offsets */
 637         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 638         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 639         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 640         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 641         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 642         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 643         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 644         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 645         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 646 };
 647
 648 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 649         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 650         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 651         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 652         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 653         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 654 };
 655
 656 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 657 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 658
 659 /* Packet type non-ip values */
 660 enum i40e_rx_l2_ptype {
 661         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 662         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 663         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 664         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 665         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 666         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 667         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 668         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 669         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 670         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 671         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 672         I40E_RX_PTYPE_L2_ARP                            = 11,
 673         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 674         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 675         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 676         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 677         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 678         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 679         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 680         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 681         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 682         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 683         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 684         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 685         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 686         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 687 };
 688
 689 struct i40e_rx_ptype_decoded {
 690         u32 ptype:8;
 691         u32 known:1;
 692         u32 outer_ip:1;
 693         u32 outer_ip_ver:1;
 694         u32 outer_frag:1;
 695         u32 tunnel_type:3;
 696         u32 tunnel_end_prot:2;
 697         u32 tunnel_end_frag:1;
 698         u32 inner_prot:4;
 699         u32 payload_layer:3;
 700 };
 701
 702 enum i40e_rx_ptype_outer_ip {
 703         I40E_RX_PTYPE_OUTER_L2  = 0,
 704         I40E_RX_PTYPE_OUTER_IP  = 1
 705 };
 706
 707 enum i40e_rx_ptype_outer_ip_ver {
 708         I40E_RX_PTYPE_OUTER_NONE        = 0,
 709         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 710         I40E_RX_PTYPE_OUTER_IPV6        = 1
 711 };
 712
 713 enum i40e_rx_ptype_outer_fragmented {
 714         I40E_RX_PTYPE_NOT_FRAG  = 0,
 715         I40E_RX_PTYPE_FRAG      = 1
 716 };
 717
 718 enum i40e_rx_ptype_tunnel_type {
 719         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 720         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 721         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 722         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 723         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 724 };
 725
 726 enum i40e_rx_ptype_tunnel_end_prot {
 727         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 728         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 729         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 730 };
 731
 732 enum i40e_rx_ptype_inner_prot {
 733         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 734         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 735         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 736         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 737         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 738         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 739 };
 740
 741 enum i40e_rx_ptype_payload_layer {
 742         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 743         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 744         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 745         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 746 };
 747
 748 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 749 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 750                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 751
 752 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 753 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 754                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 755
 756 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 757 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 758
 759 enum i40e_rx_desc_ext_status_bits {
 760         /* Note: These are predefined bit offsets */
 761         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 762         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 763         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 764         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 765         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 766         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 767         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 768 };
 769
 770 enum i40e_rx_desc_pe_status_bits {
 771         /* Note: These are predefined bit offsets */
 772         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 773         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 774         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 775         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 776         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 777         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 778         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 779         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 780         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 781 };
 782
 783 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 784 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 785
 786 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 787 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 788                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 789
 790 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 791 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 792                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 793
 794 enum i40e_rx_prog_status_desc_status_bits {
 795         /* Note: These are predefined bit offsets */
 796         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 797         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 798 };
 799
 800 enum i40e_rx_prog_status_desc_prog_id_masks {
 801         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 802         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 803         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 804 };
 805
 806 enum i40e_rx_prog_status_desc_error_bits {
 807         /* Note: These are predefined bit offsets */
 808         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 809         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 810         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 811         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 812 };
 813
 814 /* TX Descriptor */
 815 struct i40e_tx_desc {
 816         __le64 buffer_addr; /* Address of descriptor's data buf */
 817         __le64 cmd_type_offset_bsz;
 818 };
 819
 820 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 821 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 822
 823 enum i40e_tx_desc_dtype_value {
 824         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 825         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 826         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 827         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 828         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 829         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 830         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 831         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 832         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 833         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 834 };
 835
 836 #define I40E_TXD_QW1_CMD_SHIFT  4
 837 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 838
 839 enum i40e_tx_desc_cmd_bits {
 840         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 841         I40E_TX_DESC_CMD_RS                     = 0x0002,
 842         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 843         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 844         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 845         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 846         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 847         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 848         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 849         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 850         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 851         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 852         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 853         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 854         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 855         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 856         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 857         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 858 };
 859
 860 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 861 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 862                                          I40E_TXD_QW1_OFFSET_SHIFT)
 863
 864 enum i40e_tx_desc_length_fields {
 865         /* Note: These are predefined bit offsets */
 866         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 867         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 868         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 869 };
 870
 871 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 872 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 873                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 874
 875 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 876 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 877
 878 /* Context descriptors */
 879 struct i40e_tx_context_desc {
 880         __le32 tunneling_params;
 881         __le16 l2tag2;
 882         __le16 rsvd;
 883         __le64 type_cmd_tso_mss;
 884 };
 885
 886 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 887 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 888
 889 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 890 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 891
 892 enum i40e_tx_ctx_desc_cmd_bits {
 893         I40E_TX_CTX_DESC_TSO            = 0x01,
 894         I40E_TX_CTX_DESC_TSYN           = 0x02,
 895         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 896         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 897         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 898         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 899         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 900         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 901         I40E_TX_CTX_DESC_SWPE           = 0x40
 902 };
 903
 904 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 905 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 906                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 907
 908 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 909 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 910                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 911
 912 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 913 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 914
 915 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 916 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 917                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 918
 919 enum i40e_tx_ctx_desc_eipt_offload {
 920         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 921         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 922         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 923         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 924 };
 925
 926 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 927 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 928                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 929
 930 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 931 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 932
 933 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
 934 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 935
 936 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 937 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
 938                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 939
 940 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 941
 942 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 943 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 944                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 945
 946 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 947 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 948                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 949
 950 struct i40e_filter_program_desc {
 951         __le32 qindex_flex_ptype_vsi;
 952         __le32 rsvd;
 953         __le32 dtype_cmd_cntindex;
 954         __le32 fd_id;
 955 };
 956 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 957 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 958                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 959 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 960 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 961                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 962 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 963 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 964                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 965
 966 /* Packet Classifier Types for filters */
 967 enum i40e_filter_pctype {
 968         /* Note: Values 0-30 are reserved for future use */
 969         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 970         /* Note: Value 32 is reserved for future use */
 971         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 972         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 973         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 974         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 975         /* Note: Values 37-40 are reserved for future use */
 976         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 977         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 978         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 979         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 980         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 981         /* Note: Value 47 is reserved for future use */
 982         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
 983         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
 984         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
 985         /* Note: Values 51-62 are reserved for future use */
 986         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 987 };
 988
 989 enum i40e_filter_program_desc_dest {
 990         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
 991         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
 992         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
 993 };
 994
 995 enum i40e_filter_program_desc_fd_status {
 996         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
 997         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
 998         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
 999         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1000 };
1001
1002 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1003 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1004                                        BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1005
1006 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1007 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1008                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1009
1010 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1011 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1012
1013 enum i40e_filter_program_desc_pcmd {
1014         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1015         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1016 };
1017
1018 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1019 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1020
1021 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1022 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1023
1024 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1025                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1026 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1027                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1028
1029 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1030 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1031                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1032
1033 enum i40e_filter_type {
1034         I40E_FLOW_DIRECTOR_FLTR = 0,
1035         I40E_PE_QUAD_HASH_FLTR = 1,
1036         I40E_ETHERTYPE_FLTR,
1037         I40E_FCOE_CTX_FLTR,
1038         I40E_MAC_VLAN_FLTR,
1039         I40E_HASH_FLTR
1040 };
1041
1042 struct i40e_vsi_context {
1043         u16 seid;
1044         u16 uplink_seid;
1045         u16 vsi_number;
1046         u16 vsis_allocated;
1047         u16 vsis_unallocated;
1048         u16 flags;
1049         u8 pf_num;
1050         u8 vf_num;
1051         u8 connection_type;
1052         struct i40e_aqc_vsi_properties_data info;
1053 };
1054
1055 struct i40e_veb_context {
1056         u16 seid;
1057         u16 uplink_seid;
1058         u16 veb_number;
1059         u16 vebs_allocated;
1060         u16 vebs_unallocated;
1061         u16 flags;
1062         struct i40e_aqc_get_veb_parameters_completion info;
1063 };
1064
1065 /* Statistics collected by each port, VSI, VEB, and S-channel */
1066 struct i40e_eth_stats {
1067         u64 rx_bytes;                   /* gorc */
1068         u64 rx_unicast;                 /* uprc */
1069         u64 rx_multicast;               /* mprc */
1070         u64 rx_broadcast;               /* bprc */
1071         u64 rx_discards;                /* rdpc */
1072         u64 rx_unknown_protocol;        /* rupp */
1073         u64 tx_bytes;                   /* gotc */
1074         u64 tx_unicast;                 /* uptc */
1075         u64 tx_multicast;               /* mptc */
1076         u64 tx_broadcast;               /* bptc */
1077         u64 tx_discards;                /* tdpc */
1078         u64 tx_errors;                  /* tepc */
1079 };
1080
1081 #ifdef I40E_FCOE
1082 /* Statistics collected per function for FCoE */
1083 struct i40e_fcoe_stats {
1084         u64 rx_fcoe_packets;            /* fcoeprc */
1085         u64 rx_fcoe_dwords;             /* focedwrc */
1086         u64 rx_fcoe_dropped;            /* fcoerpdc */
1087         u64 tx_fcoe_packets;            /* fcoeptc */
1088         u64 tx_fcoe_dwords;             /* focedwtc */
1089         u64 fcoe_bad_fccrc;             /* fcoecrc */
1090         u64 fcoe_last_error;            /* fcoelast */
1091         u64 fcoe_ddp_count;             /* fcoeddpc */
1092 };
1093
1094 /* offset to per function FCoE statistics block */
1095 #define I40E_FCOE_VF_STAT_OFFSET        0
1096 #define I40E_FCOE_PF_STAT_OFFSET        128
1097 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1098
1099 #endif
1100 /* Statistics collected by the MAC */
1101 struct i40e_hw_port_stats {
1102         /* eth stats collected by the port */
1103         struct i40e_eth_stats eth;
1104
1105         /* additional port specific stats */
1106         u64 tx_dropped_link_down;       /* tdold */
1107         u64 crc_errors;                 /* crcerrs */
1108         u64 illegal_bytes;              /* illerrc */
1109         u64 error_bytes;                /* errbc */
1110         u64 mac_local_faults;           /* mlfc */
1111         u64 mac_remote_faults;          /* mrfc */
1112         u64 rx_length_errors;           /* rlec */
1113         u64 link_xon_rx;                /* lxonrxc */
1114         u64 link_xoff_rx;               /* lxoffrxc */
1115         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1116         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1117         u64 link_xon_tx;                /* lxontxc */
1118         u64 link_xoff_tx;               /* lxofftxc */
1119         u64 priority_xon_tx[8];         /* pxontxc[8] */
1120         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1121         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1122         u64 rx_size_64;                 /* prc64 */
1123         u64 rx_size_127;                /* prc127 */
1124         u64 rx_size_255;                /* prc255 */
1125         u64 rx_size_511;                /* prc511 */
1126         u64 rx_size_1023;               /* prc1023 */
1127         u64 rx_size_1522;               /* prc1522 */
1128         u64 rx_size_big;                /* prc9522 */
1129         u64 rx_undersize;               /* ruc */
1130         u64 rx_fragments;               /* rfc */
1131         u64 rx_oversize;                /* roc */
1132         u64 rx_jabber;                  /* rjc */
1133         u64 tx_size_64;                 /* ptc64 */
1134         u64 tx_size_127;                /* ptc127 */
1135         u64 tx_size_255;                /* ptc255 */
1136         u64 tx_size_511;                /* ptc511 */
1137         u64 tx_size_1023;               /* ptc1023 */
1138         u64 tx_size_1522;               /* ptc1522 */
1139         u64 tx_size_big;                /* ptc9522 */
1140         u64 mac_short_packet_dropped;   /* mspdc */
1141         u64 checksum_error;             /* xec */
1142         /* flow director stats */
1143         u64 fd_atr_match;
1144         u64 fd_sb_match;
1145         u64 fd_atr_tunnel_match;
1146         u32 fd_atr_status;
1147         u32 fd_sb_status;
1148         /* EEE LPI */
1149         u32 tx_lpi_status;
1150         u32 rx_lpi_status;
1151         u64 tx_lpi_count;               /* etlpic */
1152         u64 rx_lpi_count;               /* erlpic */
1153 };
1154
1155 /* Checksum and Shadow RAM pointers */
1156 #define I40E_SR_NVM_CONTROL_WORD                0x00
1157 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1158 #define I40E_SR_PBA_FLAGS                       0x15
1159 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1160 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1161 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1162 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1163 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1164 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1165 #define I40E_SR_VPD_PTR                         0x2F
1166 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1167 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1168
1169 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1170 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1171 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1172 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1173 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1174
1175 /* Shadow RAM related */
1176 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1177 #define I40E_SR_WORDS_IN_1KB            512
1178 /* Checksum should be calculated such that after adding all the words,
1179  * including the checksum word itself, the sum should be 0xBABA.
1180  */
1181 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1182
1183 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1184
1185 #ifdef I40E_FCOE
1186 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1187
1188 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1189         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1190         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1191         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1192         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1193         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1194         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1195         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1196         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1197         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1198         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1199         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1200         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1201         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1202 };
1203
1204 /* FCoE DDP Context descriptor */
1205 struct i40e_fcoe_ddp_context_desc {
1206         __le64 rsvd;
1207         __le64 type_cmd_foff_lsize;
1208 };
1209
1210 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1211 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1212                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1213
1214 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1215 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1216                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1217
1218 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1219         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1220         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1221         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1222         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1223         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1224         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1225 };
1226
1227 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1228 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1229                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1230
1231 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1232 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1233                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1234
1235 /* FCoE DDP/DWO Queue Context descriptor */
1236 struct i40e_fcoe_queue_context_desc {
1237         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1238         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1239 };
1240
1241 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1242 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1243                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1244
1245 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1246 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1247                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1248
1249 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1250 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1251                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1252
1253 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1254 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1255                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1256
1257 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1258         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1259         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1260 };
1261
1262 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1263 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1264                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1265
1266 /* FCoE DDP/DWO Filter Context descriptor */
1267 struct i40e_fcoe_filter_context_desc {
1268         __le32 param;
1269         __le16 seqn;
1270
1271         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1272         __le16 rsvd_dmaindx;
1273
1274         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1275         __le64 flags_rsvd_lanq;
1276 };
1277
1278 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1279 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1280                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1281
1282 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1283         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1284         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1285         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1286         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1287         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1288         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1289 };
1290
1291 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1292 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1293                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1294
1295 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1296 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1297                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1298
1299 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1300 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1301                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1302
1303 #endif /* I40E_FCOE */
1304 enum i40e_switch_element_types {
1305         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1306         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1307         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1308         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1309         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1310         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1311         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1312         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1313         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1314 };
1315
1316 /* Supported EtherType filters */
1317 enum i40e_ether_type_index {
1318         I40E_ETHER_TYPE_1588            = 0,
1319         I40E_ETHER_TYPE_FIP             = 1,
1320         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1321         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1322         I40E_ETHER_TYPE_LLDP            = 4,
1323         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1324         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1325         I40E_ETHER_TYPE_QCN_CNM         = 7,
1326         I40E_ETHER_TYPE_8021X           = 8,
1327         I40E_ETHER_TYPE_ARP             = 9,
1328         I40E_ETHER_TYPE_RSV1            = 10,
1329         I40E_ETHER_TYPE_RSV2            = 11,
1330 };
1331
1332 /* Filter context base size is 1K */
1333 #define I40E_HASH_FILTER_BASE_SIZE      1024
1334 /* Supported Hash filter values */
1335 enum i40e_hash_filter_size {
1336         I40E_HASH_FILTER_SIZE_1K        = 0,
1337         I40E_HASH_FILTER_SIZE_2K        = 1,
1338         I40E_HASH_FILTER_SIZE_4K        = 2,
1339         I40E_HASH_FILTER_SIZE_8K        = 3,
1340         I40E_HASH_FILTER_SIZE_16K       = 4,
1341         I40E_HASH_FILTER_SIZE_32K       = 5,
1342         I40E_HASH_FILTER_SIZE_64K       = 6,
1343         I40E_HASH_FILTER_SIZE_128K      = 7,
1344         I40E_HASH_FILTER_SIZE_256K      = 8,
1345         I40E_HASH_FILTER_SIZE_512K      = 9,
1346         I40E_HASH_FILTER_SIZE_1M        = 10,
1347 };
1348
1349 /* DMA context base size is 0.5K */
1350 #define I40E_DMA_CNTX_BASE_SIZE         512
1351 /* Supported DMA context values */
1352 enum i40e_dma_cntx_size {
1353         I40E_DMA_CNTX_SIZE_512          = 0,
1354         I40E_DMA_CNTX_SIZE_1K           = 1,
1355         I40E_DMA_CNTX_SIZE_2K           = 2,
1356         I40E_DMA_CNTX_SIZE_4K           = 3,
1357         I40E_DMA_CNTX_SIZE_8K           = 4,
1358         I40E_DMA_CNTX_SIZE_16K          = 5,
1359         I40E_DMA_CNTX_SIZE_32K          = 6,
1360         I40E_DMA_CNTX_SIZE_64K          = 7,
1361         I40E_DMA_CNTX_SIZE_128K         = 8,
1362         I40E_DMA_CNTX_SIZE_256K         = 9,
1363 };
1364
1365 /* Supported Hash look up table (LUT) sizes */
1366 enum i40e_hash_lut_size {
1367         I40E_HASH_LUT_SIZE_128          = 0,
1368         I40E_HASH_LUT_SIZE_512          = 1,
1369 };
1370
1371 /* Structure to hold a per PF filter control settings */
1372 struct i40e_filter_control_settings {
1373         /* number of PE Quad Hash filter buckets */
1374         enum i40e_hash_filter_size pe_filt_num;
1375         /* number of PE Quad Hash contexts */
1376         enum i40e_dma_cntx_size pe_cntx_num;
1377         /* number of FCoE filter buckets */
1378         enum i40e_hash_filter_size fcoe_filt_num;
1379         /* number of FCoE DDP contexts */
1380         enum i40e_dma_cntx_size fcoe_cntx_num;
1381         /* size of the Hash LUT */
1382         enum i40e_hash_lut_size hash_lut_size;
1383         /* enable FDIR filters for PF and its VFs */
1384         bool enable_fdir;
1385         /* enable Ethertype filters for PF and its VFs */
1386         bool enable_ethtype;
1387         /* enable MAC/VLAN filters for PF and its VFs */
1388         bool enable_macvlan;
1389 };
1390
1391 /* Structure to hold device level control filter counts */
1392 struct i40e_control_filter_stats {
1393         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1394         u16 etype_used;       /* Used perfect EtherType filters */
1395         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1396         u16 etype_free;       /* Un-used perfect EtherType filters */
1397 };
1398
1399 enum i40e_reset_type {
1400         I40E_RESET_POR          = 0,
1401         I40E_RESET_CORER        = 1,
1402         I40E_RESET_GLOBR        = 2,
1403         I40E_RESET_EMPR         = 3,
1404 };
1405
1406 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1407 #define I40E_NVM_LLDP_CFG_PTR           0xD
1408 struct i40e_lldp_variables {
1409         u16 length;
1410         u16 adminstatus;
1411         u16 msgfasttx;
1412         u16 msgtxinterval;
1413         u16 txparams;
1414         u16 timers;
1415         u16 crc8;
1416 };
1417
1418 /* Offsets into Alternate Ram */
1419 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1420 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1421 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1422 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1423 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1424 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1425
1426 /* Alternate Ram Bandwidth Masks */
1427 #define I40E_ALT_BW_VALUE_MASK          0xFF
1428 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1429 #define I40E_ALT_BW_VALID_MASK          0x80000000
1430
1431 /* RSS Hash Table Size */
1432 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1433 #endif /* _I40E_TYPE_H_ */