1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_20G_KR2 0x1587
48 #define I40E_DEV_ID_VF 0x154C
49 #define I40E_DEV_ID_VF_HV 0x1571
50 #define I40E_DEV_ID_SFP_X722 0x37D0
51 #define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
52 #define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
53 #define I40E_DEV_ID_X722_VF 0x37CD
54 #define I40E_DEV_ID_X722_VF_HV 0x37D9
56 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
57 (d) == I40E_DEV_ID_QSFP_B || \
58 (d) == I40E_DEV_ID_QSFP_C)
60 /* I40E_MASK is a macro used on 32 bit registers */
61 #define I40E_MASK(mask, shift) (mask << shift)
63 #define I40E_MAX_VSI_QP 16
64 #define I40E_MAX_VF_VSI 3
65 #define I40E_MAX_CHAINED_RX_BUFFERS 5
66 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
68 /* Max default timeout in ms, */
69 #define I40E_MAX_NVM_TIMEOUT 18000
71 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
72 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
74 /* forward declaration */
76 typedef void (*I40E_ADMINQ_CALLBACK
)(struct i40e_hw
*, struct i40e_aq_desc
*);
78 /* Data type manipulation macros. */
80 #define I40E_DESC_UNUSED(R) \
81 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
82 (R)->next_to_clean - (R)->next_to_use - 1)
84 /* bitfields for Tx queue mapping in QTX_CTL */
85 #define I40E_QTX_CTL_VF_QUEUE 0x0
86 #define I40E_QTX_CTL_VM_QUEUE 0x1
87 #define I40E_QTX_CTL_PF_QUEUE 0x2
89 /* debug masks - set these bits in hw->debug_mask to control output */
90 enum i40e_debug_mask
{
91 I40E_DEBUG_INIT
= 0x00000001,
92 I40E_DEBUG_RELEASE
= 0x00000002,
94 I40E_DEBUG_LINK
= 0x00000010,
95 I40E_DEBUG_PHY
= 0x00000020,
96 I40E_DEBUG_HMC
= 0x00000040,
97 I40E_DEBUG_NVM
= 0x00000080,
98 I40E_DEBUG_LAN
= 0x00000100,
99 I40E_DEBUG_FLOW
= 0x00000200,
100 I40E_DEBUG_DCB
= 0x00000400,
101 I40E_DEBUG_DIAG
= 0x00000800,
102 I40E_DEBUG_FD
= 0x00001000,
104 I40E_DEBUG_AQ_MESSAGE
= 0x01000000,
105 I40E_DEBUG_AQ_DESCRIPTOR
= 0x02000000,
106 I40E_DEBUG_AQ_DESC_BUFFER
= 0x04000000,
107 I40E_DEBUG_AQ_COMMAND
= 0x06000000,
108 I40E_DEBUG_AQ
= 0x0F000000,
110 I40E_DEBUG_USER
= 0xF0000000,
112 I40E_DEBUG_ALL
= 0xFFFFFFFF
115 /* These are structs for managing the hardware information and the operations.
116 * The structures of function pointers are filled out at init time when we
117 * know for sure exactly which hardware we're working with. This gives us the
118 * flexibility of using the same main driver code but adapting to slightly
119 * different hardware needs as new parts are developed. For this architecture,
120 * the Firmware and AdminQ are intended to insulate the driver from most of the
121 * future changes, but these structures will also do part of the job.
124 I40E_MAC_UNKNOWN
= 0,
133 enum i40e_media_type
{
134 I40E_MEDIA_TYPE_UNKNOWN
= 0,
135 I40E_MEDIA_TYPE_FIBER
,
136 I40E_MEDIA_TYPE_BASET
,
137 I40E_MEDIA_TYPE_BACKPLANE
,
140 I40E_MEDIA_TYPE_VIRTUAL
152 enum i40e_set_fc_aq_failures
{
153 I40E_SET_FC_AQ_FAIL_NONE
= 0,
154 I40E_SET_FC_AQ_FAIL_GET
= 1,
155 I40E_SET_FC_AQ_FAIL_SET
= 2,
156 I40E_SET_FC_AQ_FAIL_UPDATE
= 4,
157 I40E_SET_FC_AQ_FAIL_SET_UPDATE
= 6
169 I40E_VSI_TYPE_UNKNOWN
172 enum i40e_queue_type
{
173 I40E_QUEUE_TYPE_RX
= 0,
175 I40E_QUEUE_TYPE_PE_CEQ
,
176 I40E_QUEUE_TYPE_UNKNOWN
179 struct i40e_link_status
{
180 enum i40e_aq_phy_type phy_type
;
181 enum i40e_aq_link_speed link_speed
;
186 /* is Link Status Event notification to SW enabled */
194 struct i40e_phy_info
{
195 struct i40e_link_status link_info
;
196 struct i40e_link_status link_info_old
;
197 u32 autoneg_advertised
;
201 enum i40e_media_type media_type
;
204 #define I40E_HW_CAP_MAX_GPIO 30
205 /* Capabilities of a PF or a VF or the whole device */
206 struct i40e_hw_capabilities
{
208 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
209 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
210 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
218 bool evb_802_1_qbg
; /* Edge Virtual Bridging */
219 bool evb_802_1_qbh
; /* Bridge Port Extension */
222 bool iscsi
; /* Indicates iSCSI enabled */
226 #define I40E_FLEX10_MODE_UNKNOWN 0x0
227 #define I40E_FLEX10_MODE_DCC 0x1
228 #define I40E_FLEX10_MODE_DCI 0x2
231 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
232 #define I40E_FLEX10_STATUS_VC_MODE 0x2
238 u32 fd_filters_guaranteed
;
239 u32 fd_filters_best_effort
;
242 u32 rss_table_entry_width
;
243 bool led
[I40E_HW_CAP_MAX_GPIO
];
244 bool sdp
[I40E_HW_CAP_MAX_GPIO
];
246 u32 num_flow_director_filters
;
253 u32 num_msix_vectors
;
254 u32 num_msix_vectors_vf
;
265 struct i40e_mac_info
{
266 enum i40e_mac_type type
;
268 u8 perm_addr
[ETH_ALEN
];
269 u8 san_addr
[ETH_ALEN
];
270 u8 port_addr
[ETH_ALEN
];
274 enum i40e_aq_resources_ids
{
275 I40E_NVM_RESOURCE_ID
= 1
278 enum i40e_aq_resource_access_type
{
279 I40E_RESOURCE_READ
= 1,
283 struct i40e_nvm_info
{
284 u64 hw_semaphore_timeout
; /* usec global time (GTIME resolution) */
285 u32 timeout
; /* [ms] */
286 u16 sr_size
; /* Shadow RAM size in words */
287 bool blank_nvm_mode
; /* is NVM empty (no FW present)*/
288 u16 version
; /* NVM package version */
289 u32 eetrack
; /* NVM data version */
292 /* definitions used in NVM update support */
294 enum i40e_nvmupd_cmd
{
296 I40E_NVMUPD_READ_CON
,
297 I40E_NVMUPD_READ_SNT
,
298 I40E_NVMUPD_READ_LCB
,
300 I40E_NVMUPD_WRITE_ERA
,
301 I40E_NVMUPD_WRITE_CON
,
302 I40E_NVMUPD_WRITE_SNT
,
303 I40E_NVMUPD_WRITE_LCB
,
304 I40E_NVMUPD_WRITE_SA
,
305 I40E_NVMUPD_CSUM_CON
,
307 I40E_NVMUPD_CSUM_LCB
,
310 enum i40e_nvmupd_state
{
311 I40E_NVMUPD_STATE_INIT
,
312 I40E_NVMUPD_STATE_READING
,
313 I40E_NVMUPD_STATE_WRITING
316 /* nvm_access definition and its masks/shifts need to be accessible to
317 * application, core driver, and shared code. Where is the right file?
319 #define I40E_NVM_READ 0xB
320 #define I40E_NVM_WRITE 0xC
322 #define I40E_NVM_MOD_PNT_MASK 0xFF
324 #define I40E_NVM_TRANS_SHIFT 8
325 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
326 #define I40E_NVM_CON 0x0
327 #define I40E_NVM_SNT 0x1
328 #define I40E_NVM_LCB 0x2
329 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
330 #define I40E_NVM_ERA 0x4
331 #define I40E_NVM_CSUM 0x8
333 #define I40E_NVM_ADAPT_SHIFT 16
334 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
336 #define I40E_NVMUPD_MAX_DATA 4096
337 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
339 struct i40e_nvm_access
{
342 u32 offset
; /* in bytes */
343 u32 data_size
; /* in bytes */
349 i40e_bus_type_unknown
= 0,
352 i40e_bus_type_pci_express
,
353 i40e_bus_type_reserved
357 enum i40e_bus_speed
{
358 i40e_bus_speed_unknown
= 0,
359 i40e_bus_speed_33
= 33,
360 i40e_bus_speed_66
= 66,
361 i40e_bus_speed_100
= 100,
362 i40e_bus_speed_120
= 120,
363 i40e_bus_speed_133
= 133,
364 i40e_bus_speed_2500
= 2500,
365 i40e_bus_speed_5000
= 5000,
366 i40e_bus_speed_8000
= 8000,
367 i40e_bus_speed_reserved
371 enum i40e_bus_width
{
372 i40e_bus_width_unknown
= 0,
373 i40e_bus_width_pcie_x1
= 1,
374 i40e_bus_width_pcie_x2
= 2,
375 i40e_bus_width_pcie_x4
= 4,
376 i40e_bus_width_pcie_x8
= 8,
377 i40e_bus_width_32
= 32,
378 i40e_bus_width_64
= 64,
379 i40e_bus_width_reserved
383 struct i40e_bus_info
{
384 enum i40e_bus_speed speed
;
385 enum i40e_bus_width width
;
386 enum i40e_bus_type type
;
393 /* Flow control (FC) parameters */
394 struct i40e_fc_info
{
395 enum i40e_fc_mode current_mode
; /* FC mode in effect */
396 enum i40e_fc_mode requested_mode
; /* FC mode requested by caller */
399 #define I40E_MAX_TRAFFIC_CLASS 8
400 #define I40E_MAX_USER_PRIORITY 8
401 #define I40E_DCBX_MAX_APPS 32
402 #define I40E_LLDPDU_SIZE 1500
403 #define I40E_TLV_STATUS_OPER 0x1
404 #define I40E_TLV_STATUS_SYNC 0x2
405 #define I40E_TLV_STATUS_ERR 0x4
406 #define I40E_CEE_OPER_MAX_APPS 3
407 #define I40E_APP_PROTOID_FCOE 0x8906
408 #define I40E_APP_PROTOID_ISCSI 0x0cbc
409 #define I40E_APP_PROTOID_FIP 0x8914
410 #define I40E_APP_SEL_ETHTYPE 0x1
411 #define I40E_APP_SEL_TCPIP 0x2
413 /* CEE or IEEE 802.1Qaz ETS Configuration data */
414 struct i40e_dcb_ets_config
{
418 u8 prioritytable
[I40E_MAX_TRAFFIC_CLASS
];
419 u8 tcbwtable
[I40E_MAX_TRAFFIC_CLASS
];
420 u8 tsatable
[I40E_MAX_TRAFFIC_CLASS
];
423 /* CEE or IEEE 802.1Qaz PFC Configuration data */
424 struct i40e_dcb_pfc_config
{
431 /* CEE or IEEE 802.1Qaz Application Priority data */
432 struct i40e_dcb_app_priority_table
{
438 struct i40e_dcbx_config
{
440 #define I40E_DCBX_MODE_CEE 0x1
441 #define I40E_DCBX_MODE_IEEE 0x2
443 struct i40e_dcb_ets_config etscfg
;
444 struct i40e_dcb_ets_config etsrec
;
445 struct i40e_dcb_pfc_config pfc
;
446 struct i40e_dcb_app_priority_table app
[I40E_DCBX_MAX_APPS
];
449 /* Port hardware description */
454 /* subsystem structs */
455 struct i40e_phy_info phy
;
456 struct i40e_mac_info mac
;
457 struct i40e_bus_info bus
;
458 struct i40e_nvm_info nvm
;
459 struct i40e_fc_info fc
;
464 u16 subsystem_device_id
;
465 u16 subsystem_vendor_id
;
468 bool adapter_stopped
;
470 /* capabilities for entire device and PCI func */
471 struct i40e_hw_capabilities dev_caps
;
472 struct i40e_hw_capabilities func_caps
;
474 /* Flow Director shared filter space */
475 u16 fdir_shared_filter_count
;
477 /* device profile info */
481 /* for multi-function MACs */
486 /* Closest numa node to the device */
489 /* Admin Queue info */
490 struct i40e_adminq_info aq
;
492 /* state of nvm update process */
493 enum i40e_nvmupd_state nvmupd_state
;
496 struct i40e_hmc_info hmc
; /* HMC info struct */
498 /* LLDP/DCBX Status */
502 struct i40e_dcbx_config local_dcbx_config
;
503 struct i40e_dcbx_config remote_dcbx_config
;
510 static inline bool i40e_is_vf(struct i40e_hw
*hw
)
512 return (hw
->mac
.type
== I40E_MAC_VF
||
513 hw
->mac
.type
== I40E_MAC_X722_VF
);
516 struct i40e_driver_version
{
521 u8 driver_string
[32];
525 union i40e_16byte_rx_desc
{
527 __le64 pkt_addr
; /* Packet buffer address */
528 __le64 hdr_addr
; /* Header buffer address */
534 __le16 mirroring_status
;
540 __le32 rss
; /* RSS Hash */
541 __le32 fd_id
; /* Flow director filter id */
542 __le32 fcoe_param
; /* FCoE DDP Context id */
546 /* ext status/error/pktype/length */
547 __le64 status_error_len
;
549 } wb
; /* writeback */
552 union i40e_32byte_rx_desc
{
554 __le64 pkt_addr
; /* Packet buffer address */
555 __le64 hdr_addr
; /* Header buffer address */
556 /* bit 0 of hdr_buffer_addr is DD bit */
564 __le16 mirroring_status
;
570 __le32 rss
; /* RSS Hash */
571 __le32 fcoe_param
; /* FCoE DDP Context id */
572 /* Flow director filter id in case of
573 * Programming status desc WB
579 /* status/error/pktype/length */
580 __le64 status_error_len
;
583 __le16 ext_status
; /* extended status */
590 __le32 flex_bytes_lo
;
594 __le32 flex_bytes_hi
;
598 } wb
; /* writeback */
601 enum i40e_rx_desc_status_bits
{
602 /* Note: These are predefined bit offsets */
603 I40E_RX_DESC_STATUS_DD_SHIFT
= 0,
604 I40E_RX_DESC_STATUS_EOF_SHIFT
= 1,
605 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
= 2,
606 I40E_RX_DESC_STATUS_L3L4P_SHIFT
= 3,
607 I40E_RX_DESC_STATUS_CRCP_SHIFT
= 4,
608 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
= 5, /* 2 BITS */
609 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
= 7,
610 I40E_RX_DESC_STATUS_PIF_SHIFT
= 8,
611 I40E_RX_DESC_STATUS_UMBCAST_SHIFT
= 9, /* 2 BITS */
612 I40E_RX_DESC_STATUS_FLM_SHIFT
= 11,
613 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT
= 12, /* 2 BITS */
614 I40E_RX_DESC_STATUS_LPBK_SHIFT
= 14,
615 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT
= 15,
616 I40E_RX_DESC_STATUS_RESERVED_SHIFT
= 16, /* 2 BITS */
617 I40E_RX_DESC_STATUS_UDP_0_SHIFT
= 18,
618 I40E_RX_DESC_STATUS_LAST
/* this entry must be last!!! */
621 #define I40E_RXD_QW1_STATUS_SHIFT 0
622 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
623 << I40E_RXD_QW1_STATUS_SHIFT)
625 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
626 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
627 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
629 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
630 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
631 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
633 enum i40e_rx_desc_fltstat_values
{
634 I40E_RX_DESC_FLTSTAT_NO_DATA
= 0,
635 I40E_RX_DESC_FLTSTAT_RSV_FD_ID
= 1, /* 16byte desc? FD_ID : RSV */
636 I40E_RX_DESC_FLTSTAT_RSV
= 2,
637 I40E_RX_DESC_FLTSTAT_RSS_HASH
= 3,
640 #define I40E_RXD_QW1_ERROR_SHIFT 19
641 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
643 enum i40e_rx_desc_error_bits
{
644 /* Note: These are predefined bit offsets */
645 I40E_RX_DESC_ERROR_RXE_SHIFT
= 0,
646 I40E_RX_DESC_ERROR_RECIPE_SHIFT
= 1,
647 I40E_RX_DESC_ERROR_HBO_SHIFT
= 2,
648 I40E_RX_DESC_ERROR_L3L4E_SHIFT
= 3, /* 3 BITS */
649 I40E_RX_DESC_ERROR_IPE_SHIFT
= 3,
650 I40E_RX_DESC_ERROR_L4E_SHIFT
= 4,
651 I40E_RX_DESC_ERROR_EIPE_SHIFT
= 5,
652 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT
= 6,
653 I40E_RX_DESC_ERROR_PPRS_SHIFT
= 7
656 enum i40e_rx_desc_error_l3l4e_fcoe_masks
{
657 I40E_RX_DESC_ERROR_L3L4E_NONE
= 0,
658 I40E_RX_DESC_ERROR_L3L4E_PROT
= 1,
659 I40E_RX_DESC_ERROR_L3L4E_FC
= 2,
660 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR
= 3,
661 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN
= 4
664 #define I40E_RXD_QW1_PTYPE_SHIFT 30
665 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
667 /* Packet type non-ip values */
668 enum i40e_rx_l2_ptype
{
669 I40E_RX_PTYPE_L2_RESERVED
= 0,
670 I40E_RX_PTYPE_L2_MAC_PAY2
= 1,
671 I40E_RX_PTYPE_L2_TIMESYNC_PAY2
= 2,
672 I40E_RX_PTYPE_L2_FIP_PAY2
= 3,
673 I40E_RX_PTYPE_L2_OUI_PAY2
= 4,
674 I40E_RX_PTYPE_L2_MACCNTRL_PAY2
= 5,
675 I40E_RX_PTYPE_L2_LLDP_PAY2
= 6,
676 I40E_RX_PTYPE_L2_ECP_PAY2
= 7,
677 I40E_RX_PTYPE_L2_EVB_PAY2
= 8,
678 I40E_RX_PTYPE_L2_QCN_PAY2
= 9,
679 I40E_RX_PTYPE_L2_EAPOL_PAY2
= 10,
680 I40E_RX_PTYPE_L2_ARP
= 11,
681 I40E_RX_PTYPE_L2_FCOE_PAY3
= 12,
682 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3
= 13,
683 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3
= 14,
684 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3
= 15,
685 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA
= 16,
686 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3
= 17,
687 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA
= 18,
688 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY
= 19,
689 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP
= 20,
690 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER
= 21,
691 I40E_RX_PTYPE_GRENAT4_MAC_PAY3
= 58,
692 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4
= 87,
693 I40E_RX_PTYPE_GRENAT6_MAC_PAY3
= 124,
694 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4
= 153
697 struct i40e_rx_ptype_decoded
{
704 u32 tunnel_end_prot
:2;
705 u32 tunnel_end_frag
:1;
710 enum i40e_rx_ptype_outer_ip
{
711 I40E_RX_PTYPE_OUTER_L2
= 0,
712 I40E_RX_PTYPE_OUTER_IP
= 1
715 enum i40e_rx_ptype_outer_ip_ver
{
716 I40E_RX_PTYPE_OUTER_NONE
= 0,
717 I40E_RX_PTYPE_OUTER_IPV4
= 0,
718 I40E_RX_PTYPE_OUTER_IPV6
= 1
721 enum i40e_rx_ptype_outer_fragmented
{
722 I40E_RX_PTYPE_NOT_FRAG
= 0,
723 I40E_RX_PTYPE_FRAG
= 1
726 enum i40e_rx_ptype_tunnel_type
{
727 I40E_RX_PTYPE_TUNNEL_NONE
= 0,
728 I40E_RX_PTYPE_TUNNEL_IP_IP
= 1,
729 I40E_RX_PTYPE_TUNNEL_IP_GRENAT
= 2,
730 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC
= 3,
731 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN
= 4,
734 enum i40e_rx_ptype_tunnel_end_prot
{
735 I40E_RX_PTYPE_TUNNEL_END_NONE
= 0,
736 I40E_RX_PTYPE_TUNNEL_END_IPV4
= 1,
737 I40E_RX_PTYPE_TUNNEL_END_IPV6
= 2,
740 enum i40e_rx_ptype_inner_prot
{
741 I40E_RX_PTYPE_INNER_PROT_NONE
= 0,
742 I40E_RX_PTYPE_INNER_PROT_UDP
= 1,
743 I40E_RX_PTYPE_INNER_PROT_TCP
= 2,
744 I40E_RX_PTYPE_INNER_PROT_SCTP
= 3,
745 I40E_RX_PTYPE_INNER_PROT_ICMP
= 4,
746 I40E_RX_PTYPE_INNER_PROT_TIMESYNC
= 5
749 enum i40e_rx_ptype_payload_layer
{
750 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE
= 0,
751 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2
= 1,
752 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3
= 2,
753 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4
= 3,
756 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
757 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
758 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
760 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
761 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
762 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
764 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
765 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
767 enum i40e_rx_desc_ext_status_bits
{
768 /* Note: These are predefined bit offsets */
769 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT
= 0,
770 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT
= 1,
771 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT
= 2, /* 2 BITS */
772 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT
= 4, /* 2 BITS */
773 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT
= 9,
774 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT
= 10,
775 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT
= 11,
778 enum i40e_rx_desc_pe_status_bits
{
779 /* Note: These are predefined bit offsets */
780 I40E_RX_DESC_PE_STATUS_QPID_SHIFT
= 0, /* 18 BITS */
781 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT
= 0, /* 16 BITS */
782 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT
= 16, /* 8 BITS */
783 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT
= 24,
784 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT
= 25,
785 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT
= 26,
786 I40E_RX_DESC_PE_STATUS_URG_SHIFT
= 27,
787 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT
= 28,
788 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT
= 29
791 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
792 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
794 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
795 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
796 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
798 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
799 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
800 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
802 enum i40e_rx_prog_status_desc_status_bits
{
803 /* Note: These are predefined bit offsets */
804 I40E_RX_PROG_STATUS_DESC_DD_SHIFT
= 0,
805 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT
= 2 /* 3 BITS */
808 enum i40e_rx_prog_status_desc_prog_id_masks
{
809 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS
= 1,
810 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS
= 2,
811 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS
= 4,
814 enum i40e_rx_prog_status_desc_error_bits
{
815 /* Note: These are predefined bit offsets */
816 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT
= 0,
817 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT
= 1,
818 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT
= 2,
819 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT
= 3
823 struct i40e_tx_desc
{
824 __le64 buffer_addr
; /* Address of descriptor's data buf */
825 __le64 cmd_type_offset_bsz
;
828 #define I40E_TXD_QW1_DTYPE_SHIFT 0
829 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
831 enum i40e_tx_desc_dtype_value
{
832 I40E_TX_DESC_DTYPE_DATA
= 0x0,
833 I40E_TX_DESC_DTYPE_NOP
= 0x1, /* same as Context desc */
834 I40E_TX_DESC_DTYPE_CONTEXT
= 0x1,
835 I40E_TX_DESC_DTYPE_FCOE_CTX
= 0x2,
836 I40E_TX_DESC_DTYPE_FILTER_PROG
= 0x8,
837 I40E_TX_DESC_DTYPE_DDP_CTX
= 0x9,
838 I40E_TX_DESC_DTYPE_FLEX_DATA
= 0xB,
839 I40E_TX_DESC_DTYPE_FLEX_CTX_1
= 0xC,
840 I40E_TX_DESC_DTYPE_FLEX_CTX_2
= 0xD,
841 I40E_TX_DESC_DTYPE_DESC_DONE
= 0xF
844 #define I40E_TXD_QW1_CMD_SHIFT 4
845 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
847 enum i40e_tx_desc_cmd_bits
{
848 I40E_TX_DESC_CMD_EOP
= 0x0001,
849 I40E_TX_DESC_CMD_RS
= 0x0002,
850 I40E_TX_DESC_CMD_ICRC
= 0x0004,
851 I40E_TX_DESC_CMD_IL2TAG1
= 0x0008,
852 I40E_TX_DESC_CMD_DUMMY
= 0x0010,
853 I40E_TX_DESC_CMD_IIPT_NONIP
= 0x0000, /* 2 BITS */
854 I40E_TX_DESC_CMD_IIPT_IPV6
= 0x0020, /* 2 BITS */
855 I40E_TX_DESC_CMD_IIPT_IPV4
= 0x0040, /* 2 BITS */
856 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM
= 0x0060, /* 2 BITS */
857 I40E_TX_DESC_CMD_FCOET
= 0x0080,
858 I40E_TX_DESC_CMD_L4T_EOFT_UNK
= 0x0000, /* 2 BITS */
859 I40E_TX_DESC_CMD_L4T_EOFT_TCP
= 0x0100, /* 2 BITS */
860 I40E_TX_DESC_CMD_L4T_EOFT_SCTP
= 0x0200, /* 2 BITS */
861 I40E_TX_DESC_CMD_L4T_EOFT_UDP
= 0x0300, /* 2 BITS */
862 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N
= 0x0000, /* 2 BITS */
863 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T
= 0x0100, /* 2 BITS */
864 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI
= 0x0200, /* 2 BITS */
865 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A
= 0x0300, /* 2 BITS */
868 #define I40E_TXD_QW1_OFFSET_SHIFT 16
869 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
870 I40E_TXD_QW1_OFFSET_SHIFT)
872 enum i40e_tx_desc_length_fields
{
873 /* Note: These are predefined bit offsets */
874 I40E_TX_DESC_LENGTH_MACLEN_SHIFT
= 0, /* 7 BITS */
875 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
= 7, /* 7 BITS */
876 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
= 14 /* 4 BITS */
879 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
880 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
881 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
883 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
884 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
886 /* Context descriptors */
887 struct i40e_tx_context_desc
{
888 __le32 tunneling_params
;
891 __le64 type_cmd_tso_mss
;
894 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
895 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
897 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
898 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
900 enum i40e_tx_ctx_desc_cmd_bits
{
901 I40E_TX_CTX_DESC_TSO
= 0x01,
902 I40E_TX_CTX_DESC_TSYN
= 0x02,
903 I40E_TX_CTX_DESC_IL2TAG2
= 0x04,
904 I40E_TX_CTX_DESC_IL2TAG2_IL2H
= 0x08,
905 I40E_TX_CTX_DESC_SWTCH_NOTAG
= 0x00,
906 I40E_TX_CTX_DESC_SWTCH_UPLINK
= 0x10,
907 I40E_TX_CTX_DESC_SWTCH_LOCAL
= 0x20,
908 I40E_TX_CTX_DESC_SWTCH_VSI
= 0x30,
909 I40E_TX_CTX_DESC_SWPE
= 0x40
912 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
913 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
914 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
916 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
917 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
918 I40E_TXD_CTX_QW1_MSS_SHIFT)
920 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
921 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
923 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
924 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
925 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
927 enum i40e_tx_ctx_desc_eipt_offload
{
928 I40E_TX_CTX_EXT_IP_NONE
= 0x0,
929 I40E_TX_CTX_EXT_IP_IPV6
= 0x1,
930 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
= 0x2,
931 I40E_TX_CTX_EXT_IP_IPV4
= 0x3
934 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
935 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
936 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
938 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
939 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
941 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
942 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
944 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
945 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
946 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
948 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
950 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
951 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
952 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
954 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
955 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
956 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
958 struct i40e_filter_program_desc
{
959 __le32 qindex_flex_ptype_vsi
;
961 __le32 dtype_cmd_cntindex
;
964 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
965 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
966 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
967 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
968 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
969 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
970 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
971 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
972 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
974 /* Packet Classifier Types for filters */
975 enum i40e_filter_pctype
{
976 /* Note: Values 0-30 are reserved for future use */
977 I40E_FILTER_PCTYPE_NONF_IPV4_UDP
= 31,
978 /* Note: Value 32 is reserved for future use */
979 I40E_FILTER_PCTYPE_NONF_IPV4_TCP
= 33,
980 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP
= 34,
981 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER
= 35,
982 I40E_FILTER_PCTYPE_FRAG_IPV4
= 36,
983 /* Note: Values 37-40 are reserved for future use */
984 I40E_FILTER_PCTYPE_NONF_IPV6_UDP
= 41,
985 I40E_FILTER_PCTYPE_NONF_IPV6_TCP
= 43,
986 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP
= 44,
987 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER
= 45,
988 I40E_FILTER_PCTYPE_FRAG_IPV6
= 46,
989 /* Note: Value 47 is reserved for future use */
990 I40E_FILTER_PCTYPE_FCOE_OX
= 48,
991 I40E_FILTER_PCTYPE_FCOE_RX
= 49,
992 I40E_FILTER_PCTYPE_FCOE_OTHER
= 50,
993 /* Note: Values 51-62 are reserved for future use */
994 I40E_FILTER_PCTYPE_L2_PAYLOAD
= 63,
997 enum i40e_filter_program_desc_dest
{
998 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET
= 0x0,
999 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX
= 0x1,
1000 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER
= 0x2,
1003 enum i40e_filter_program_desc_fd_status
{
1004 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE
= 0x0,
1005 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID
= 0x1,
1006 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES
= 0x2,
1007 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES
= 0x3,
1010 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1011 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1012 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1014 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1015 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1016 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1018 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1019 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1021 enum i40e_filter_program_desc_pcmd
{
1022 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE
= 0x1,
1023 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE
= 0x2,
1026 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1027 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1029 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1030 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1032 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1033 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1034 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1035 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1037 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1038 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1039 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1041 enum i40e_filter_type
{
1042 I40E_FLOW_DIRECTOR_FLTR
= 0,
1043 I40E_PE_QUAD_HASH_FLTR
= 1,
1044 I40E_ETHERTYPE_FLTR
,
1050 struct i40e_vsi_context
{
1055 u16 vsis_unallocated
;
1060 struct i40e_aqc_vsi_properties_data info
;
1063 struct i40e_veb_context
{
1068 u16 vebs_unallocated
;
1070 struct i40e_aqc_get_veb_parameters_completion info
;
1073 /* Statistics collected by each port, VSI, VEB, and S-channel */
1074 struct i40e_eth_stats
{
1075 u64 rx_bytes
; /* gorc */
1076 u64 rx_unicast
; /* uprc */
1077 u64 rx_multicast
; /* mprc */
1078 u64 rx_broadcast
; /* bprc */
1079 u64 rx_discards
; /* rdpc */
1080 u64 rx_unknown_protocol
; /* rupp */
1081 u64 tx_bytes
; /* gotc */
1082 u64 tx_unicast
; /* uptc */
1083 u64 tx_multicast
; /* mptc */
1084 u64 tx_broadcast
; /* bptc */
1085 u64 tx_discards
; /* tdpc */
1086 u64 tx_errors
; /* tepc */
1090 /* Statistics collected per function for FCoE */
1091 struct i40e_fcoe_stats
{
1092 u64 rx_fcoe_packets
; /* fcoeprc */
1093 u64 rx_fcoe_dwords
; /* focedwrc */
1094 u64 rx_fcoe_dropped
; /* fcoerpdc */
1095 u64 tx_fcoe_packets
; /* fcoeptc */
1096 u64 tx_fcoe_dwords
; /* focedwtc */
1097 u64 fcoe_bad_fccrc
; /* fcoecrc */
1098 u64 fcoe_last_error
; /* fcoelast */
1099 u64 fcoe_ddp_count
; /* fcoeddpc */
1102 /* offset to per function FCoE statistics block */
1103 #define I40E_FCOE_VF_STAT_OFFSET 0
1104 #define I40E_FCOE_PF_STAT_OFFSET 128
1105 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1108 /* Statistics collected by the MAC */
1109 struct i40e_hw_port_stats
{
1110 /* eth stats collected by the port */
1111 struct i40e_eth_stats eth
;
1113 /* additional port specific stats */
1114 u64 tx_dropped_link_down
; /* tdold */
1115 u64 crc_errors
; /* crcerrs */
1116 u64 illegal_bytes
; /* illerrc */
1117 u64 error_bytes
; /* errbc */
1118 u64 mac_local_faults
; /* mlfc */
1119 u64 mac_remote_faults
; /* mrfc */
1120 u64 rx_length_errors
; /* rlec */
1121 u64 link_xon_rx
; /* lxonrxc */
1122 u64 link_xoff_rx
; /* lxoffrxc */
1123 u64 priority_xon_rx
[8]; /* pxonrxc[8] */
1124 u64 priority_xoff_rx
[8]; /* pxoffrxc[8] */
1125 u64 link_xon_tx
; /* lxontxc */
1126 u64 link_xoff_tx
; /* lxofftxc */
1127 u64 priority_xon_tx
[8]; /* pxontxc[8] */
1128 u64 priority_xoff_tx
[8]; /* pxofftxc[8] */
1129 u64 priority_xon_2_xoff
[8]; /* pxon2offc[8] */
1130 u64 rx_size_64
; /* prc64 */
1131 u64 rx_size_127
; /* prc127 */
1132 u64 rx_size_255
; /* prc255 */
1133 u64 rx_size_511
; /* prc511 */
1134 u64 rx_size_1023
; /* prc1023 */
1135 u64 rx_size_1522
; /* prc1522 */
1136 u64 rx_size_big
; /* prc9522 */
1137 u64 rx_undersize
; /* ruc */
1138 u64 rx_fragments
; /* rfc */
1139 u64 rx_oversize
; /* roc */
1140 u64 rx_jabber
; /* rjc */
1141 u64 tx_size_64
; /* ptc64 */
1142 u64 tx_size_127
; /* ptc127 */
1143 u64 tx_size_255
; /* ptc255 */
1144 u64 tx_size_511
; /* ptc511 */
1145 u64 tx_size_1023
; /* ptc1023 */
1146 u64 tx_size_1522
; /* ptc1522 */
1147 u64 tx_size_big
; /* ptc9522 */
1148 u64 mac_short_packet_dropped
; /* mspdc */
1149 u64 checksum_error
; /* xec */
1150 /* flow director stats */
1153 u64 fd_atr_tunnel_match
;
1159 u64 tx_lpi_count
; /* etlpic */
1160 u64 rx_lpi_count
; /* erlpic */
1163 /* Checksum and Shadow RAM pointers */
1164 #define I40E_SR_NVM_CONTROL_WORD 0x00
1165 #define I40E_SR_EMP_MODULE_PTR 0x0F
1166 #define I40E_SR_PBA_FLAGS 0x15
1167 #define I40E_SR_PBA_BLOCK_PTR 0x16
1168 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1169 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1170 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1171 #define I40E_SR_NVM_EETRACK_LO 0x2D
1172 #define I40E_SR_NVM_EETRACK_HI 0x2E
1173 #define I40E_SR_VPD_PTR 0x2F
1174 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1175 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1177 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1178 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1179 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1180 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1181 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1183 /* Shadow RAM related */
1184 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1185 #define I40E_SR_WORDS_IN_1KB 512
1186 /* Checksum should be calculated such that after adding all the words,
1187 * including the checksum word itself, the sum should be 0xBABA.
1189 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1191 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1194 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1196 enum i40E_fcoe_tx_ctx_desc_cmd_bits
{
1197 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND
= 0x00, /* 4 BITS */
1198 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2
= 0x01, /* 4 BITS */
1199 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3
= 0x05, /* 4 BITS */
1200 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2
= 0x02, /* 4 BITS */
1201 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3
= 0x06, /* 4 BITS */
1202 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2
= 0x03, /* 4 BITS */
1203 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3
= 0x07, /* 4 BITS */
1204 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL
= 0x08, /* 4 BITS */
1205 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL
= 0x09, /* 4 BITS */
1206 I40E_FCOE_TX_CTX_DESC_RELOFF
= 0x10,
1207 I40E_FCOE_TX_CTX_DESC_CLRSEQ
= 0x20,
1208 I40E_FCOE_TX_CTX_DESC_DIFENA
= 0x40,
1209 I40E_FCOE_TX_CTX_DESC_IL2TAG2
= 0x80
1212 /* FCoE DDP Context descriptor */
1213 struct i40e_fcoe_ddp_context_desc
{
1215 __le64 type_cmd_foff_lsize
;
1218 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1219 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1220 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1222 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1223 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1224 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1226 enum i40e_fcoe_ddp_ctx_desc_cmd_bits
{
1227 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B
= 0x00, /* 2 BITS */
1228 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K
= 0x01, /* 2 BITS */
1229 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K
= 0x02, /* 2 BITS */
1230 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K
= 0x03, /* 2 BITS */
1231 I40E_FCOE_DDP_CTX_DESC_DIFENA
= 0x04, /* 1 BIT */
1232 I40E_FCOE_DDP_CTX_DESC_LASTSEQH
= 0x08, /* 1 BIT */
1235 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1236 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1237 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1239 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1240 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1241 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1243 /* FCoE DDP/DWO Queue Context descriptor */
1244 struct i40e_fcoe_queue_context_desc
{
1245 __le64 dmaindx_fbase
; /* 0:11 DMAINDX, 12:63 FBASE */
1246 __le64 flen_tph
; /* 0:12 FLEN, 13:15 TPH */
1249 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1250 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1251 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1253 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1254 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1255 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1257 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1258 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1259 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1261 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1262 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1263 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1265 enum i40e_fcoe_queue_ctx_desc_tph_bits
{
1266 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC
= 0x1,
1267 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA
= 0x2
1270 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1271 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1272 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1274 /* FCoE DDP/DWO Filter Context descriptor */
1275 struct i40e_fcoe_filter_context_desc
{
1279 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1280 __le16 rsvd_dmaindx
;
1282 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1283 __le64 flags_rsvd_lanq
;
1286 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1287 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1288 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1290 enum i40e_fcoe_filter_ctx_desc_flags_bits
{
1291 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP
= 0x00,
1292 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO
= 0x01,
1293 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT
= 0x00,
1294 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP
= 0x02,
1295 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2
= 0x00,
1296 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3
= 0x04
1299 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1300 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1301 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1303 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1304 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1305 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1307 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1308 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1309 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1311 #endif /* I40E_FCOE */
1312 enum i40e_switch_element_types
{
1313 I40E_SWITCH_ELEMENT_TYPE_MAC
= 1,
1314 I40E_SWITCH_ELEMENT_TYPE_PF
= 2,
1315 I40E_SWITCH_ELEMENT_TYPE_VF
= 3,
1316 I40E_SWITCH_ELEMENT_TYPE_EMP
= 4,
1317 I40E_SWITCH_ELEMENT_TYPE_BMC
= 6,
1318 I40E_SWITCH_ELEMENT_TYPE_PE
= 16,
1319 I40E_SWITCH_ELEMENT_TYPE_VEB
= 17,
1320 I40E_SWITCH_ELEMENT_TYPE_PA
= 18,
1321 I40E_SWITCH_ELEMENT_TYPE_VSI
= 19,
1324 /* Supported EtherType filters */
1325 enum i40e_ether_type_index
{
1326 I40E_ETHER_TYPE_1588
= 0,
1327 I40E_ETHER_TYPE_FIP
= 1,
1328 I40E_ETHER_TYPE_OUI_EXTENDED
= 2,
1329 I40E_ETHER_TYPE_MAC_CONTROL
= 3,
1330 I40E_ETHER_TYPE_LLDP
= 4,
1331 I40E_ETHER_TYPE_EVB_PROTOCOL1
= 5,
1332 I40E_ETHER_TYPE_EVB_PROTOCOL2
= 6,
1333 I40E_ETHER_TYPE_QCN_CNM
= 7,
1334 I40E_ETHER_TYPE_8021X
= 8,
1335 I40E_ETHER_TYPE_ARP
= 9,
1336 I40E_ETHER_TYPE_RSV1
= 10,
1337 I40E_ETHER_TYPE_RSV2
= 11,
1340 /* Filter context base size is 1K */
1341 #define I40E_HASH_FILTER_BASE_SIZE 1024
1342 /* Supported Hash filter values */
1343 enum i40e_hash_filter_size
{
1344 I40E_HASH_FILTER_SIZE_1K
= 0,
1345 I40E_HASH_FILTER_SIZE_2K
= 1,
1346 I40E_HASH_FILTER_SIZE_4K
= 2,
1347 I40E_HASH_FILTER_SIZE_8K
= 3,
1348 I40E_HASH_FILTER_SIZE_16K
= 4,
1349 I40E_HASH_FILTER_SIZE_32K
= 5,
1350 I40E_HASH_FILTER_SIZE_64K
= 6,
1351 I40E_HASH_FILTER_SIZE_128K
= 7,
1352 I40E_HASH_FILTER_SIZE_256K
= 8,
1353 I40E_HASH_FILTER_SIZE_512K
= 9,
1354 I40E_HASH_FILTER_SIZE_1M
= 10,
1357 /* DMA context base size is 0.5K */
1358 #define I40E_DMA_CNTX_BASE_SIZE 512
1359 /* Supported DMA context values */
1360 enum i40e_dma_cntx_size
{
1361 I40E_DMA_CNTX_SIZE_512
= 0,
1362 I40E_DMA_CNTX_SIZE_1K
= 1,
1363 I40E_DMA_CNTX_SIZE_2K
= 2,
1364 I40E_DMA_CNTX_SIZE_4K
= 3,
1365 I40E_DMA_CNTX_SIZE_8K
= 4,
1366 I40E_DMA_CNTX_SIZE_16K
= 5,
1367 I40E_DMA_CNTX_SIZE_32K
= 6,
1368 I40E_DMA_CNTX_SIZE_64K
= 7,
1369 I40E_DMA_CNTX_SIZE_128K
= 8,
1370 I40E_DMA_CNTX_SIZE_256K
= 9,
1373 /* Supported Hash look up table (LUT) sizes */
1374 enum i40e_hash_lut_size
{
1375 I40E_HASH_LUT_SIZE_128
= 0,
1376 I40E_HASH_LUT_SIZE_512
= 1,
1379 /* Structure to hold a per PF filter control settings */
1380 struct i40e_filter_control_settings
{
1381 /* number of PE Quad Hash filter buckets */
1382 enum i40e_hash_filter_size pe_filt_num
;
1383 /* number of PE Quad Hash contexts */
1384 enum i40e_dma_cntx_size pe_cntx_num
;
1385 /* number of FCoE filter buckets */
1386 enum i40e_hash_filter_size fcoe_filt_num
;
1387 /* number of FCoE DDP contexts */
1388 enum i40e_dma_cntx_size fcoe_cntx_num
;
1389 /* size of the Hash LUT */
1390 enum i40e_hash_lut_size hash_lut_size
;
1391 /* enable FDIR filters for PF and its VFs */
1393 /* enable Ethertype filters for PF and its VFs */
1394 bool enable_ethtype
;
1395 /* enable MAC/VLAN filters for PF and its VFs */
1396 bool enable_macvlan
;
1399 /* Structure to hold device level control filter counts */
1400 struct i40e_control_filter_stats
{
1401 u16 mac_etype_used
; /* Used perfect match MAC/EtherType filters */
1402 u16 etype_used
; /* Used perfect EtherType filters */
1403 u16 mac_etype_free
; /* Un-used perfect match MAC/EtherType filters */
1404 u16 etype_free
; /* Un-used perfect EtherType filters */
1407 enum i40e_reset_type
{
1409 I40E_RESET_CORER
= 1,
1410 I40E_RESET_GLOBR
= 2,
1411 I40E_RESET_EMPR
= 3,
1414 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1415 #define I40E_NVM_LLDP_CFG_PTR 0xD
1416 struct i40e_lldp_variables
{
1426 /* Offsets into Alternate Ram */
1427 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1428 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1429 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1430 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1431 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1432 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1434 /* Alternate Ram Bandwidth Masks */
1435 #define I40E_ALT_BW_VALUE_MASK 0xFF
1436 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1437 #define I40E_ALT_BW_VALID_MASK 0x80000000
1439 /* RSS Hash Table Size */
1440 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1441 #endif /* _I40E_TYPE_H_ */