1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2017 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
33 * This file needs to comply with the Linux Kernel coding style.
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0005
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
81 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
94 enum i40e_admin_queue_err
{
95 I40E_AQ_RC_OK
= 0, /* success */
96 I40E_AQ_RC_EPERM
= 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT
= 2, /* No such element */
98 I40E_AQ_RC_ESRCH
= 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR
= 4, /* operation interrupted */
100 I40E_AQ_RC_EIO
= 5, /* I/O error */
101 I40E_AQ_RC_ENXIO
= 6, /* No such resource */
102 I40E_AQ_RC_E2BIG
= 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN
= 8, /* Try again */
104 I40E_AQ_RC_ENOMEM
= 9, /* Out of memory */
105 I40E_AQ_RC_EACCES
= 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT
= 11, /* Bad address */
107 I40E_AQ_RC_EBUSY
= 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST
= 13, /* object already exists */
109 I40E_AQ_RC_EINVAL
= 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY
= 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC
= 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS
= 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE
= 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED
= 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR
= 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE
= 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG
= 22, /* File too large */
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc
{
123 i40e_aqc_opc_get_version
= 0x0001,
124 i40e_aqc_opc_driver_version
= 0x0002,
125 i40e_aqc_opc_queue_shutdown
= 0x0003,
126 i40e_aqc_opc_set_pf_context
= 0x0004,
128 /* resource ownership */
129 i40e_aqc_opc_request_resource
= 0x0008,
130 i40e_aqc_opc_release_resource
= 0x0009,
132 i40e_aqc_opc_list_func_capabilities
= 0x000A,
133 i40e_aqc_opc_list_dev_capabilities
= 0x000B,
136 i40e_aqc_opc_set_proxy_config
= 0x0104,
137 i40e_aqc_opc_set_ns_proxy_table_entry
= 0x0105,
140 i40e_aqc_opc_mac_address_read
= 0x0107,
141 i40e_aqc_opc_mac_address_write
= 0x0108,
144 i40e_aqc_opc_clear_pxe_mode
= 0x0110,
147 i40e_aqc_opc_set_wol_filter
= 0x0120,
148 i40e_aqc_opc_get_wake_reason
= 0x0121,
150 /* internal switch commands */
151 i40e_aqc_opc_get_switch_config
= 0x0200,
152 i40e_aqc_opc_add_statistics
= 0x0201,
153 i40e_aqc_opc_remove_statistics
= 0x0202,
154 i40e_aqc_opc_set_port_parameters
= 0x0203,
155 i40e_aqc_opc_get_switch_resource_alloc
= 0x0204,
156 i40e_aqc_opc_set_switch_config
= 0x0205,
157 i40e_aqc_opc_rx_ctl_reg_read
= 0x0206,
158 i40e_aqc_opc_rx_ctl_reg_write
= 0x0207,
160 i40e_aqc_opc_add_vsi
= 0x0210,
161 i40e_aqc_opc_update_vsi_parameters
= 0x0211,
162 i40e_aqc_opc_get_vsi_parameters
= 0x0212,
164 i40e_aqc_opc_add_pv
= 0x0220,
165 i40e_aqc_opc_update_pv_parameters
= 0x0221,
166 i40e_aqc_opc_get_pv_parameters
= 0x0222,
168 i40e_aqc_opc_add_veb
= 0x0230,
169 i40e_aqc_opc_update_veb_parameters
= 0x0231,
170 i40e_aqc_opc_get_veb_parameters
= 0x0232,
172 i40e_aqc_opc_delete_element
= 0x0243,
174 i40e_aqc_opc_add_macvlan
= 0x0250,
175 i40e_aqc_opc_remove_macvlan
= 0x0251,
176 i40e_aqc_opc_add_vlan
= 0x0252,
177 i40e_aqc_opc_remove_vlan
= 0x0253,
178 i40e_aqc_opc_set_vsi_promiscuous_modes
= 0x0254,
179 i40e_aqc_opc_add_tag
= 0x0255,
180 i40e_aqc_opc_remove_tag
= 0x0256,
181 i40e_aqc_opc_add_multicast_etag
= 0x0257,
182 i40e_aqc_opc_remove_multicast_etag
= 0x0258,
183 i40e_aqc_opc_update_tag
= 0x0259,
184 i40e_aqc_opc_add_control_packet_filter
= 0x025A,
185 i40e_aqc_opc_remove_control_packet_filter
= 0x025B,
186 i40e_aqc_opc_add_cloud_filters
= 0x025C,
187 i40e_aqc_opc_remove_cloud_filters
= 0x025D,
188 i40e_aqc_opc_clear_wol_switch_filters
= 0x025E,
190 i40e_aqc_opc_add_mirror_rule
= 0x0260,
191 i40e_aqc_opc_delete_mirror_rule
= 0x0261,
193 /* Pipeline Personalization Profile */
194 i40e_aqc_opc_write_personalization_profile
= 0x0270,
195 i40e_aqc_opc_get_personalization_profile_list
= 0x0271,
198 i40e_aqc_opc_dcb_ignore_pfc
= 0x0301,
199 i40e_aqc_opc_dcb_updated
= 0x0302,
202 i40e_aqc_opc_configure_vsi_bw_limit
= 0x0400,
203 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
= 0x0406,
204 i40e_aqc_opc_configure_vsi_tc_bw
= 0x0407,
205 i40e_aqc_opc_query_vsi_bw_config
= 0x0408,
206 i40e_aqc_opc_query_vsi_ets_sla_config
= 0x040A,
207 i40e_aqc_opc_configure_switching_comp_bw_limit
= 0x0410,
209 i40e_aqc_opc_enable_switching_comp_ets
= 0x0413,
210 i40e_aqc_opc_modify_switching_comp_ets
= 0x0414,
211 i40e_aqc_opc_disable_switching_comp_ets
= 0x0415,
212 i40e_aqc_opc_configure_switching_comp_ets_bw_limit
= 0x0416,
213 i40e_aqc_opc_configure_switching_comp_bw_config
= 0x0417,
214 i40e_aqc_opc_query_switching_comp_ets_config
= 0x0418,
215 i40e_aqc_opc_query_port_ets_config
= 0x0419,
216 i40e_aqc_opc_query_switching_comp_bw_config
= 0x041A,
217 i40e_aqc_opc_suspend_port_tx
= 0x041B,
218 i40e_aqc_opc_resume_port_tx
= 0x041C,
219 i40e_aqc_opc_configure_partition_bw
= 0x041D,
221 i40e_aqc_opc_query_hmc_resource_profile
= 0x0500,
222 i40e_aqc_opc_set_hmc_resource_profile
= 0x0501,
225 i40e_aqc_opc_get_phy_abilities
= 0x0600,
226 i40e_aqc_opc_set_phy_config
= 0x0601,
227 i40e_aqc_opc_set_mac_config
= 0x0603,
228 i40e_aqc_opc_set_link_restart_an
= 0x0605,
229 i40e_aqc_opc_get_link_status
= 0x0607,
230 i40e_aqc_opc_set_phy_int_mask
= 0x0613,
231 i40e_aqc_opc_get_local_advt_reg
= 0x0614,
232 i40e_aqc_opc_set_local_advt_reg
= 0x0615,
233 i40e_aqc_opc_get_partner_advt
= 0x0616,
234 i40e_aqc_opc_set_lb_modes
= 0x0618,
235 i40e_aqc_opc_get_phy_wol_caps
= 0x0621,
236 i40e_aqc_opc_set_phy_debug
= 0x0622,
237 i40e_aqc_opc_upload_ext_phy_fm
= 0x0625,
238 i40e_aqc_opc_run_phy_activity
= 0x0626,
241 i40e_aqc_opc_nvm_read
= 0x0701,
242 i40e_aqc_opc_nvm_erase
= 0x0702,
243 i40e_aqc_opc_nvm_update
= 0x0703,
244 i40e_aqc_opc_nvm_config_read
= 0x0704,
245 i40e_aqc_opc_nvm_config_write
= 0x0705,
246 i40e_aqc_opc_oem_post_update
= 0x0720,
247 i40e_aqc_opc_thermal_sensor
= 0x0721,
249 /* virtualization commands */
250 i40e_aqc_opc_send_msg_to_pf
= 0x0801,
251 i40e_aqc_opc_send_msg_to_vf
= 0x0802,
252 i40e_aqc_opc_send_msg_to_peer
= 0x0803,
254 /* alternate structure */
255 i40e_aqc_opc_alternate_write
= 0x0900,
256 i40e_aqc_opc_alternate_write_indirect
= 0x0901,
257 i40e_aqc_opc_alternate_read
= 0x0902,
258 i40e_aqc_opc_alternate_read_indirect
= 0x0903,
259 i40e_aqc_opc_alternate_write_done
= 0x0904,
260 i40e_aqc_opc_alternate_set_mode
= 0x0905,
261 i40e_aqc_opc_alternate_clear_port
= 0x0906,
264 i40e_aqc_opc_lldp_get_mib
= 0x0A00,
265 i40e_aqc_opc_lldp_update_mib
= 0x0A01,
266 i40e_aqc_opc_lldp_add_tlv
= 0x0A02,
267 i40e_aqc_opc_lldp_update_tlv
= 0x0A03,
268 i40e_aqc_opc_lldp_delete_tlv
= 0x0A04,
269 i40e_aqc_opc_lldp_stop
= 0x0A05,
270 i40e_aqc_opc_lldp_start
= 0x0A06,
272 /* Tunnel commands */
273 i40e_aqc_opc_add_udp_tunnel
= 0x0B00,
274 i40e_aqc_opc_del_udp_tunnel
= 0x0B01,
275 i40e_aqc_opc_set_rss_key
= 0x0B02,
276 i40e_aqc_opc_set_rss_lut
= 0x0B03,
277 i40e_aqc_opc_get_rss_key
= 0x0B04,
278 i40e_aqc_opc_get_rss_lut
= 0x0B05,
281 i40e_aqc_opc_event_lan_overflow
= 0x1001,
284 i40e_aqc_opc_oem_parameter_change
= 0xFE00,
285 i40e_aqc_opc_oem_device_status_change
= 0xFE01,
286 i40e_aqc_opc_oem_ocsd_initialize
= 0xFE02,
287 i40e_aqc_opc_oem_ocbb_initialize
= 0xFE03,
290 i40e_aqc_opc_debug_read_reg
= 0xFF03,
291 i40e_aqc_opc_debug_write_reg
= 0xFF04,
292 i40e_aqc_opc_debug_modify_reg
= 0xFF07,
293 i40e_aqc_opc_debug_dump_internals
= 0xFF08,
296 /* command structures and indirect data structures */
298 /* Structure naming conventions:
299 * - no suffix for direct command descriptor structures
300 * - _data for indirect sent data
301 * - _resp for indirect return data (data which is both will use _data)
302 * - _completion for direct return data
303 * - _element_ for repeated elements (may also be _data or _resp)
305 * Command structures are expected to overlay the params.raw member of the basic
306 * descriptor, and as such cannot exceed 16 bytes in length.
309 /* This macro is used to generate a compilation error if a structure
310 * is not exactly the correct length. It gives a divide by zero error if the
311 * structure is not of the correct size, otherwise it creates an enum that is
314 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
315 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
317 /* This macro is used extensively to ensure that command structures are 16
318 * bytes in length as they have to map to the raw array of that size.
320 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
322 /* internal (0x00XX) commands */
324 /* Get version (direct 0x0001) */
325 struct i40e_aqc_get_version
{
334 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version
);
336 /* Send driver version (indirect 0x0002) */
337 struct i40e_aqc_driver_version
{
341 u8 driver_subbuild_ver
;
347 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version
);
349 /* Queue Shutdown (direct 0x0003) */
350 struct i40e_aqc_queue_shutdown
{
351 __le32 driver_unloading
;
352 #define I40E_AQ_DRIVER_UNLOADING 0x1
356 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown
);
358 /* Set PF context (0x0004, direct) */
359 struct i40e_aqc_set_pf_context
{
364 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context
);
366 /* Request resource ownership (direct 0x0008)
367 * Release resource ownership (direct 0x0009)
369 #define I40E_AQ_RESOURCE_NVM 1
370 #define I40E_AQ_RESOURCE_SDP 2
371 #define I40E_AQ_RESOURCE_ACCESS_READ 1
372 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
373 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
374 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
376 struct i40e_aqc_request_resource
{
380 __le32 resource_number
;
384 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource
);
386 /* Get function capabilities (indirect 0x000A)
387 * Get device capabilities (indirect 0x000B)
389 struct i40e_aqc_list_capabilites
{
391 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
399 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites
);
401 struct i40e_aqc_list_capabilities_element_resp
{
413 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
414 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
415 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
416 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
417 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
418 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
419 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
420 #define I40E_AQ_CAP_ID_SRIOV 0x0012
421 #define I40E_AQ_CAP_ID_VF 0x0013
422 #define I40E_AQ_CAP_ID_VMDQ 0x0014
423 #define I40E_AQ_CAP_ID_8021QBG 0x0015
424 #define I40E_AQ_CAP_ID_8021QBR 0x0016
425 #define I40E_AQ_CAP_ID_VSI 0x0017
426 #define I40E_AQ_CAP_ID_DCB 0x0018
427 #define I40E_AQ_CAP_ID_FCOE 0x0021
428 #define I40E_AQ_CAP_ID_ISCSI 0x0022
429 #define I40E_AQ_CAP_ID_RSS 0x0040
430 #define I40E_AQ_CAP_ID_RXQ 0x0041
431 #define I40E_AQ_CAP_ID_TXQ 0x0042
432 #define I40E_AQ_CAP_ID_MSIX 0x0043
433 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
434 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
435 #define I40E_AQ_CAP_ID_1588 0x0046
436 #define I40E_AQ_CAP_ID_IWARP 0x0051
437 #define I40E_AQ_CAP_ID_LED 0x0061
438 #define I40E_AQ_CAP_ID_SDP 0x0062
439 #define I40E_AQ_CAP_ID_MDIO 0x0063
440 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
441 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
442 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
443 #define I40E_AQ_CAP_ID_CEM 0x00F2
445 /* Set CPPM Configuration (direct 0x0103) */
446 struct i40e_aqc_cppm_configuration
{
447 __le16 command_flags
;
448 #define I40E_AQ_CPPM_EN_LTRC 0x0800
449 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
450 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
451 #define I40E_AQ_CPPM_EN_HPTC 0x4000
452 #define I40E_AQ_CPPM_EN_DMARC 0x8000
461 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration
);
463 /* Set ARP Proxy command / response (indirect 0x0104) */
464 struct i40e_aqc_arp_proxy_data
{
465 __le16 command_flags
;
466 #define I40E_AQ_ARP_INIT_IPV4 0x0800
467 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
468 #define I40E_AQ_ARP_ENA 0x2000
469 #define I40E_AQ_ARP_ADD_IPV4 0x4000
470 #define I40E_AQ_ARP_DEL_IPV4 0x8000
472 __le32 enabled_offloads
;
473 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
474 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
480 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data
);
482 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
483 struct i40e_aqc_ns_proxy_data
{
484 __le16 table_idx_mac_addr_0
;
485 __le16 table_idx_mac_addr_1
;
486 __le16 table_idx_ipv6_0
;
487 __le16 table_idx_ipv6_1
;
489 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
490 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
491 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
492 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
493 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
494 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
495 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
496 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
497 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
498 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
499 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
500 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
501 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
504 u8 local_mac_addr
[6];
505 u8 ipv6_addr_0
[16]; /* Warning! spec specifies BE byte order */
509 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data
);
511 /* Manage LAA Command (0x0106) - obsolete */
512 struct i40e_aqc_mng_laa
{
513 __le16 command_flags
;
514 #define I40E_AQ_LAA_FLAG_WR 0x8000
521 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa
);
523 /* Manage MAC Address Read Command (indirect 0x0107) */
524 struct i40e_aqc_mac_address_read
{
525 __le16 command_flags
;
526 #define I40E_AQC_LAN_ADDR_VALID 0x10
527 #define I40E_AQC_SAN_ADDR_VALID 0x20
528 #define I40E_AQC_PORT_ADDR_VALID 0x40
529 #define I40E_AQC_WOL_ADDR_VALID 0x80
530 #define I40E_AQC_MC_MAG_EN_VALID 0x100
531 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
537 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read
);
539 struct i40e_aqc_mac_address_read_data
{
546 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data
);
548 /* Manage MAC Address Write Command (0x0108) */
549 struct i40e_aqc_mac_address_write
{
550 __le16 command_flags
;
551 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
552 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
553 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
554 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
555 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
562 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write
);
564 /* PXE commands (0x011x) */
566 /* Clear PXE Command and response (direct 0x0110) */
567 struct i40e_aqc_clear_pxe
{
572 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe
);
574 /* Set WoL Filter (0x0120) */
576 struct i40e_aqc_set_wol_filter
{
578 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
579 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
580 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
581 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
583 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
584 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
585 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
587 #define I40E_AQC_SET_WOL_FILTER 0x8000
588 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
589 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
590 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
591 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
593 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
594 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
600 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter
);
602 struct i40e_aqc_set_wol_filter_data
{
607 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data
);
609 /* Get Wake Reason (0x0121) */
611 struct i40e_aqc_get_wake_reason_completion
{
614 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
615 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
616 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
617 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
618 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
619 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
623 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion
);
625 /* Switch configuration commands (0x02xx) */
627 /* Used by many indirect commands that only pass an seid and a buffer in the
630 struct i40e_aqc_switch_seid
{
637 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid
);
639 /* Get Switch Configuration command (indirect 0x0200)
640 * uses i40e_aqc_switch_seid for the descriptor
642 struct i40e_aqc_get_switch_config_header_resp
{
648 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp
);
650 struct i40e_aqc_switch_config_element_resp
{
652 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
653 #define I40E_AQ_SW_ELEM_TYPE_PF 2
654 #define I40E_AQ_SW_ELEM_TYPE_VF 3
655 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
656 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
657 #define I40E_AQ_SW_ELEM_TYPE_PV 16
658 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
659 #define I40E_AQ_SW_ELEM_TYPE_PA 18
660 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
662 #define I40E_AQ_SW_ELEM_REV_1 1
665 __le16 downlink_seid
;
668 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
669 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
670 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
675 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp
);
677 /* Get Switch Configuration (indirect 0x0200)
678 * an array of elements are returned in the response buffer
679 * the first in the array is the header, remainder are elements
681 struct i40e_aqc_get_switch_config_resp
{
682 struct i40e_aqc_get_switch_config_header_resp header
;
683 struct i40e_aqc_switch_config_element_resp element
[1];
686 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp
);
688 /* Add Statistics (direct 0x0201)
689 * Remove Statistics (direct 0x0202)
691 struct i40e_aqc_add_remove_statistics
{
698 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics
);
700 /* Set Port Parameters command (direct 0x0203) */
701 struct i40e_aqc_set_port_parameters
{
702 __le16 command_flags
;
703 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
704 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
705 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
706 __le16 bad_frame_vsi
;
707 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
708 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
709 __le16 default_seid
; /* reserved for command */
713 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters
);
715 /* Get Switch Resource Allocation (indirect 0x0204) */
716 struct i40e_aqc_get_switch_resource_alloc
{
717 u8 num_entries
; /* reserved for command */
723 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc
);
725 /* expect an array of these structs in the response buffer */
726 struct i40e_aqc_switch_resource_alloc_element_resp
{
728 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
729 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
730 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
731 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
732 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
733 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
734 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
735 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
736 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
737 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
738 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
739 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
740 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
741 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
742 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
743 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
744 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
745 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
746 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
751 __le16 total_unalloced
;
755 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp
);
757 /* Set Switch Configuration (direct 0x0205) */
758 struct i40e_aqc_set_switch_config
{
760 /* flags used for both fields below */
761 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
762 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
767 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config
);
769 /* Read Receive control registers (direct 0x0206)
770 * Write Receive control registers (direct 0x0207)
771 * used for accessing Rx control registers that can be
772 * slow and need special handling when under high Rx load
774 struct i40e_aqc_rx_ctl_reg_read_write
{
781 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write
);
783 /* Add VSI (indirect 0x0210)
784 * this indirect command uses struct i40e_aqc_vsi_properties_data
785 * as the indirect buffer (128 bytes)
787 * Update VSI (indirect 0x211)
788 * uses the same data structure as Add VSI
790 * Get VSI (indirect 0x0212)
791 * uses the same completion and data structure as Add VSI
793 struct i40e_aqc_add_get_update_vsi
{
796 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
797 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
798 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
803 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
804 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
805 #define I40E_AQ_VSI_TYPE_VF 0x0
806 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
807 #define I40E_AQ_VSI_TYPE_PF 0x2
808 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
809 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
814 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi
);
816 struct i40e_aqc_add_get_update_vsi_completion
{
825 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion
);
827 struct i40e_aqc_vsi_properties_data
{
828 /* first 96 byte are written by SW */
829 __le16 valid_sections
;
830 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
831 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
832 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
833 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
834 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
835 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
836 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
837 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
838 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
839 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
841 __le16 switch_id
; /* 12bit id combined with flags below */
842 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
843 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
844 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
845 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
846 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
848 /* security section */
850 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
851 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
852 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
855 __le16 pvid
; /* VLANS include priority bits */
858 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
859 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
860 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
861 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
862 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
863 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
864 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
865 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
866 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
867 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
868 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
869 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
870 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
871 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
872 u8 pvlan_reserved
[3];
873 /* ingress egress up sections */
874 __le32 ingress_table
; /* bitmap, 3 bits per up */
875 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
876 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
877 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
878 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
879 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
880 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
881 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
882 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
883 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
884 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
885 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
886 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
887 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
888 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
889 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
890 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
891 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
892 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
893 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
894 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
895 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
896 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
897 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
898 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
899 __le32 egress_table
; /* same defines as for ingress table */
900 /* cascaded PV section */
903 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
904 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
905 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
906 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
907 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
908 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
909 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
910 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
911 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
913 /* queue mapping section */
914 __le16 mapping_flags
;
915 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
916 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
917 __le16 queue_mapping
[16];
918 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
919 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
920 __le16 tc_mapping
[8];
921 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
922 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
923 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
924 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
925 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
926 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
927 /* queueing option section */
928 u8 queueing_opt_flags
;
929 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
930 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
931 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
932 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
933 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
934 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
935 u8 queueing_opt_reserved
[3];
936 /* scheduler section */
939 /* outer up section */
940 __le32 outer_up_table
; /* same structure and defines as ingress tbl */
942 /* last 32 bytes are written by FW */
944 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
945 __le16 stat_counter_idx
;
947 u8 resp_reserved
[12];
950 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data
);
952 /* Add Port Virtualizer (direct 0x0220)
953 * also used for update PV (direct 0x0221) but only flags are used
954 * (IS_CTRL_PORT only works on add PV)
956 struct i40e_aqc_add_update_pv
{
957 __le16 command_flags
;
958 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
959 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
960 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
961 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
963 __le16 connected_seid
;
967 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv
);
969 struct i40e_aqc_add_update_pv_completion
{
970 /* reserved for update; for add also encodes error if rc == ENOSPC */
972 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
973 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
974 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
975 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
979 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion
);
981 /* Get PV Params (direct 0x0222)
982 * uses i40e_aqc_switch_seid for the descriptor
985 struct i40e_aqc_get_pv_params_completion
{
988 __le16 pv_flags
; /* same flags as add_pv */
989 #define I40E_AQC_GET_PV_PV_TYPE 0x1
990 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
991 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
993 __le16 default_port_seid
;
996 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion
);
998 /* Add VEB (direct 0x0230) */
999 struct i40e_aqc_add_veb
{
1001 __le16 downlink_seid
;
1003 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1004 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1005 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1006 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1007 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1008 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1009 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1010 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1015 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb
);
1017 struct i40e_aqc_add_veb_completion
{
1020 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1022 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1023 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1024 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1025 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1026 __le16 statistic_index
;
1031 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion
);
1033 /* Get VEB Parameters (direct 0x0232)
1034 * uses i40e_aqc_switch_seid for the descriptor
1036 struct i40e_aqc_get_veb_parameters_completion
{
1039 __le16 veb_flags
; /* only the first/last flags from 0x0230 is valid */
1040 __le16 statistic_index
;
1046 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion
);
1048 /* Delete Element (direct 0x0243)
1049 * uses the generic i40e_aqc_switch_seid
1052 /* Add MAC-VLAN (indirect 0x0250) */
1054 /* used for the command for most vlan commands */
1055 struct i40e_aqc_macvlan
{
1056 __le16 num_addresses
;
1058 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1059 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1060 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1061 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1066 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan
);
1068 /* indirect data for command and response */
1069 struct i40e_aqc_add_macvlan_element_data
{
1073 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1074 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1075 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1076 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1077 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1078 __le16 queue_number
;
1079 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1080 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1081 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1082 /* response section */
1084 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1085 #define I40E_AQC_MM_HASH_MATCH 0x02
1086 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1090 struct i40e_aqc_add_remove_macvlan_completion
{
1091 __le16 perfect_mac_used
;
1092 __le16 perfect_mac_free
;
1093 __le16 unicast_hash_free
;
1094 __le16 multicast_hash_free
;
1099 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion
);
1101 /* Remove MAC-VLAN (indirect 0x0251)
1102 * uses i40e_aqc_macvlan for the descriptor
1103 * data points to an array of num_addresses of elements
1106 struct i40e_aqc_remove_macvlan_element_data
{
1110 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1111 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1112 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1113 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1117 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1118 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1119 u8 reply_reserved
[3];
1122 /* Add VLAN (indirect 0x0252)
1123 * Remove VLAN (indirect 0x0253)
1124 * use the generic i40e_aqc_macvlan for the command
1126 struct i40e_aqc_add_remove_vlan_element_data
{
1129 /* flags for add VLAN */
1130 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1131 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1132 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1133 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1134 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1135 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1136 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1137 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1138 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1139 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1140 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1141 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1142 /* flags for remove VLAN */
1143 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1146 /* flags for add VLAN */
1147 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1148 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1149 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1150 /* flags for remove VLAN */
1151 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1152 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1156 struct i40e_aqc_add_remove_vlan_completion
{
1164 /* Set VSI Promiscuous Modes (direct 0x0254) */
1165 struct i40e_aqc_set_vsi_promiscuous_modes
{
1166 __le16 promiscuous_flags
;
1168 /* flags used for both fields above */
1169 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1170 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1171 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1172 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1173 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1174 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1176 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1178 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1179 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1183 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes
);
1185 /* Add S/E-tag command (direct 0x0255)
1186 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1188 struct i40e_aqc_add_tag
{
1190 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1192 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1193 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1194 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1196 __le16 queue_number
;
1200 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag
);
1202 struct i40e_aqc_add_remove_tag_completion
{
1208 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion
);
1210 /* Remove S/E-tag command (direct 0x0256)
1211 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1213 struct i40e_aqc_remove_tag
{
1215 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1216 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1217 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1222 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag
);
1224 /* Add multicast E-Tag (direct 0x0257)
1225 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1226 * and no external data
1228 struct i40e_aqc_add_remove_mcast_etag
{
1231 u8 num_unicast_etags
;
1233 __le32 addr_high
; /* address of array of 2-byte s-tags */
1237 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag
);
1239 struct i40e_aqc_add_remove_mcast_etag_completion
{
1241 __le16 mcast_etags_used
;
1242 __le16 mcast_etags_free
;
1248 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion
);
1250 /* Update S/E-Tag (direct 0x0259) */
1251 struct i40e_aqc_update_tag
{
1253 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1254 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1255 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1261 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag
);
1263 struct i40e_aqc_update_tag_completion
{
1269 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion
);
1271 /* Add Control Packet filter (direct 0x025A)
1272 * Remove Control Packet filter (direct 0x025B)
1273 * uses the i40e_aqc_add_oveb_cloud,
1274 * and the generic direct completion structure
1276 struct i40e_aqc_add_remove_control_packet_filter
{
1280 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1281 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1282 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1283 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1284 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1286 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1287 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1288 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1293 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter
);
1295 struct i40e_aqc_add_remove_control_packet_filter_completion
{
1296 __le16 mac_etype_used
;
1298 __le16 mac_etype_free
;
1303 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion
);
1305 /* Add Cloud filters (indirect 0x025C)
1306 * Remove Cloud filters (indirect 0x025D)
1307 * uses the i40e_aqc_add_remove_cloud_filters,
1308 * and the generic indirect completion structure
1310 struct i40e_aqc_add_remove_cloud_filters
{
1314 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1315 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1316 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1322 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters
);
1324 struct i40e_aqc_add_remove_cloud_filters_element_data
{
1338 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1339 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1340 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1341 /* 0x0000 reserved */
1342 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1343 /* 0x0002 reserved */
1344 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1345 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1346 /* 0x0005 reserved */
1347 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1348 /* 0x0007 reserved */
1349 /* 0x0008 reserved */
1350 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1351 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1352 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1353 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1355 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1356 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1357 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1358 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1359 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1361 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1362 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1363 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1364 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1365 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1366 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1367 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1368 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1370 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1371 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1372 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1376 __le16 queue_number
;
1377 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1378 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1379 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1381 /* response section */
1382 u8 allocation_result
;
1383 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1384 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1385 u8 response_reserved
[7];
1388 struct i40e_aqc_remove_cloud_filters_completion
{
1389 __le16 perfect_ovlan_used
;
1390 __le16 perfect_ovlan_free
;
1397 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion
);
1399 /* Add Mirror Rule (indirect or direct 0x0260)
1400 * Delete Mirror Rule (indirect or direct 0x0261)
1401 * note: some rule types (4,5) do not use an external buffer.
1402 * take care to set the flags correctly.
1404 struct i40e_aqc_add_delete_mirror_rule
{
1407 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1408 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1409 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1410 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1411 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1412 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1413 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1414 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1416 __le16 destination
; /* VSI for add, rule id for delete */
1417 __le32 addr_high
; /* address of array of 2-byte VSI or VLAN ids */
1421 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule
);
1423 struct i40e_aqc_add_delete_mirror_rule_completion
{
1425 __le16 rule_id
; /* only used on add */
1426 __le16 mirror_rules_used
;
1427 __le16 mirror_rules_free
;
1432 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion
);
1434 /* Pipeline Personalization Profile */
1435 struct i40e_aqc_write_personalization_profile
{
1438 __le32 profile_track_id
;
1443 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile
);
1445 struct i40e_aqc_write_ppp_resp
{
1446 __le32 error_offset
;
1452 struct i40e_aqc_get_applied_profiles
{
1454 #define I40E_AQC_GET_PPP_GET_CONF 0x1
1455 #define I40E_AQC_GET_PPP_GET_RDPU_CONF 0x2
1462 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles
);
1466 /* PFC Ignore (direct 0x0301)
1467 * the command and response use the same descriptor structure
1469 struct i40e_aqc_pfc_ignore
{
1471 u8 command_flags
; /* unused on response */
1472 #define I40E_AQC_PFC_IGNORE_SET 0x80
1473 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1477 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore
);
1479 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1480 * with no parameters
1483 /* TX scheduler 0x04xx */
1485 /* Almost all the indirect commands use
1486 * this generic struct to pass the SEID in param0
1488 struct i40e_aqc_tx_sched_ind
{
1495 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind
);
1497 /* Several commands respond with a set of queue set handles */
1498 struct i40e_aqc_qs_handles_resp
{
1499 __le16 qs_handles
[8];
1502 /* Configure VSI BW limits (direct 0x0400) */
1503 struct i40e_aqc_configure_vsi_bw_limit
{
1508 u8 max_credit
; /* 0-3, limit = 2^max */
1512 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit
);
1514 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1515 * responds with i40e_aqc_qs_handles_resp
1517 struct i40e_aqc_configure_vsi_ets_sla_bw_data
{
1520 __le16 tc_bw_credits
[8]; /* FW writesback QS handles here */
1522 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1523 __le16 tc_bw_max
[2];
1527 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data
);
1529 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1530 * responds with i40e_aqc_qs_handles_resp
1532 struct i40e_aqc_configure_vsi_tc_bw_data
{
1535 u8 tc_bw_credits
[8];
1537 __le16 qs_handles
[8];
1540 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data
);
1542 /* Query vsi bw configuration (indirect 0x0408) */
1543 struct i40e_aqc_query_vsi_bw_config_resp
{
1545 u8 tc_suspended_bits
;
1547 __le16 qs_handles
[8];
1549 __le16 port_bw_limit
;
1551 u8 max_bw
; /* 0-3, limit = 2^max */
1555 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp
);
1557 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1558 struct i40e_aqc_query_vsi_ets_sla_config_resp
{
1561 u8 share_credits
[8];
1564 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1565 __le16 tc_bw_max
[2];
1568 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp
);
1570 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1571 struct i40e_aqc_configure_switching_comp_bw_limit
{
1576 u8 max_bw
; /* 0-3, limit = 2^max */
1580 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit
);
1582 /* Enable Physical Port ETS (indirect 0x0413)
1583 * Modify Physical Port ETS (indirect 0x0414)
1584 * Disable Physical Port ETS (indirect 0x0415)
1586 struct i40e_aqc_configure_switching_comp_ets_data
{
1590 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1591 u8 tc_strict_priority_flags
;
1593 u8 tc_bw_share_credits
[8];
1597 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data
);
1599 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1600 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data
{
1603 __le16 tc_bw_credit
[8];
1605 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1606 __le16 tc_bw_max
[2];
1610 I40E_CHECK_STRUCT_LEN(0x40,
1611 i40e_aqc_configure_switching_comp_ets_bw_limit_data
);
1613 /* Configure Switching Component Bandwidth Allocation per Tc
1616 struct i40e_aqc_configure_switching_comp_bw_config_data
{
1619 u8 absolute_credits
; /* bool */
1620 u8 tc_bw_share_credits
[8];
1624 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data
);
1626 /* Query Switching Component Configuration (indirect 0x0418) */
1627 struct i40e_aqc_query_switching_comp_ets_config_resp
{
1630 __le16 port_bw_limit
;
1632 u8 tc_bw_max
; /* 0-3, limit = 2^max */
1636 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp
);
1638 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1639 struct i40e_aqc_query_port_ets_config_resp
{
1643 u8 tc_strict_priority_bits
;
1645 u8 tc_bw_share_credits
[8];
1646 __le16 tc_bw_limits
[8];
1648 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1649 __le16 tc_bw_max
[2];
1653 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp
);
1655 /* Query Switching Component Bandwidth Allocation per Traffic Type
1658 struct i40e_aqc_query_switching_comp_bw_config_resp
{
1661 u8 absolute_credits_enable
; /* bool */
1662 u8 tc_bw_share_credits
[8];
1663 __le16 tc_bw_limits
[8];
1665 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1666 __le16 tc_bw_max
[2];
1669 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp
);
1671 /* Suspend/resume port TX traffic
1672 * (direct 0x041B and 0x041C) uses the generic SEID struct
1675 /* Configure partition BW
1678 struct i40e_aqc_configure_partition_bw_data
{
1679 __le16 pf_valid_bits
;
1680 u8 min_bw
[16]; /* guaranteed bandwidth */
1681 u8 max_bw
[16]; /* bandwidth limit */
1684 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data
);
1686 /* Get and set the active HMC resource profile and status.
1687 * (direct 0x0500) and (direct 0x0501)
1689 struct i40e_aq_get_set_hmc_resource_profile
{
1695 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile
);
1697 enum i40e_aq_hmc_profile
{
1698 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1699 I40E_HMC_PROFILE_DEFAULT
= 1,
1700 I40E_HMC_PROFILE_FAVOR_VF
= 2,
1701 I40E_HMC_PROFILE_EQUAL
= 3,
1704 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1706 /* set in param0 for get phy abilities to report qualified modules */
1707 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1708 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1710 enum i40e_aq_phy_type
{
1711 I40E_PHY_TYPE_SGMII
= 0x0,
1712 I40E_PHY_TYPE_1000BASE_KX
= 0x1,
1713 I40E_PHY_TYPE_10GBASE_KX4
= 0x2,
1714 I40E_PHY_TYPE_10GBASE_KR
= 0x3,
1715 I40E_PHY_TYPE_40GBASE_KR4
= 0x4,
1716 I40E_PHY_TYPE_XAUI
= 0x5,
1717 I40E_PHY_TYPE_XFI
= 0x6,
1718 I40E_PHY_TYPE_SFI
= 0x7,
1719 I40E_PHY_TYPE_XLAUI
= 0x8,
1720 I40E_PHY_TYPE_XLPPI
= 0x9,
1721 I40E_PHY_TYPE_40GBASE_CR4_CU
= 0xA,
1722 I40E_PHY_TYPE_10GBASE_CR1_CU
= 0xB,
1723 I40E_PHY_TYPE_10GBASE_AOC
= 0xC,
1724 I40E_PHY_TYPE_40GBASE_AOC
= 0xD,
1725 I40E_PHY_TYPE_100BASE_TX
= 0x11,
1726 I40E_PHY_TYPE_1000BASE_T
= 0x12,
1727 I40E_PHY_TYPE_10GBASE_T
= 0x13,
1728 I40E_PHY_TYPE_10GBASE_SR
= 0x14,
1729 I40E_PHY_TYPE_10GBASE_LR
= 0x15,
1730 I40E_PHY_TYPE_10GBASE_SFPP_CU
= 0x16,
1731 I40E_PHY_TYPE_10GBASE_CR1
= 0x17,
1732 I40E_PHY_TYPE_40GBASE_CR4
= 0x18,
1733 I40E_PHY_TYPE_40GBASE_SR4
= 0x19,
1734 I40E_PHY_TYPE_40GBASE_LR4
= 0x1A,
1735 I40E_PHY_TYPE_1000BASE_SX
= 0x1B,
1736 I40E_PHY_TYPE_1000BASE_LX
= 0x1C,
1737 I40E_PHY_TYPE_1000BASE_T_OPTICAL
= 0x1D,
1738 I40E_PHY_TYPE_20GBASE_KR2
= 0x1E,
1739 I40E_PHY_TYPE_25GBASE_KR
= 0x1F,
1740 I40E_PHY_TYPE_25GBASE_CR
= 0x20,
1741 I40E_PHY_TYPE_25GBASE_SR
= 0x21,
1742 I40E_PHY_TYPE_25GBASE_LR
= 0x22,
1746 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1747 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1748 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1749 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1750 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1751 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1753 enum i40e_aq_link_speed
{
1754 I40E_LINK_SPEED_UNKNOWN
= 0,
1755 I40E_LINK_SPEED_100MB
= BIT(I40E_LINK_SPEED_100MB_SHIFT
),
1756 I40E_LINK_SPEED_1GB
= BIT(I40E_LINK_SPEED_1000MB_SHIFT
),
1757 I40E_LINK_SPEED_10GB
= BIT(I40E_LINK_SPEED_10GB_SHIFT
),
1758 I40E_LINK_SPEED_40GB
= BIT(I40E_LINK_SPEED_40GB_SHIFT
),
1759 I40E_LINK_SPEED_20GB
= BIT(I40E_LINK_SPEED_20GB_SHIFT
),
1760 I40E_LINK_SPEED_25GB
= BIT(I40E_LINK_SPEED_25GB_SHIFT
),
1763 struct i40e_aqc_module_desc
{
1771 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc
);
1773 struct i40e_aq_get_phy_abilities_resp
{
1774 __le32 phy_type
; /* bitmap using the above enum for offsets */
1775 u8 link_speed
; /* bitmap using the above enum bit patterns */
1777 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1778 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1779 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1780 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1781 #define I40E_AQ_PHY_AN_ENABLED 0x10
1782 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1783 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1784 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1785 __le16 eee_capability
;
1786 #define I40E_AQ_EEE_100BASE_TX 0x0002
1787 #define I40E_AQ_EEE_1000BASE_T 0x0004
1788 #define I40E_AQ_EEE_10GBASE_T 0x0008
1789 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1790 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1791 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1794 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1796 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1797 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1798 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1799 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1800 u8 fec_cfg_curr_mod_ext_info
;
1801 #define I40E_AQ_ENABLE_FEC_KR 0x01
1802 #define I40E_AQ_ENABLE_FEC_RS 0x02
1803 #define I40E_AQ_REQUEST_FEC_KR 0x04
1804 #define I40E_AQ_REQUEST_FEC_RS 0x08
1805 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1807 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1808 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1813 u8 qualified_module_count
;
1814 #define I40E_AQ_PHY_MAX_QMS 16
1815 struct i40e_aqc_module_desc qualified_module
[I40E_AQ_PHY_MAX_QMS
];
1818 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp
);
1820 /* Set PHY Config (direct 0x0601) */
1821 struct i40e_aq_set_phy_config
{ /* same bits as above in all */
1825 /* bits 0-2 use the values from get_phy_abilities_resp */
1826 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1827 #define I40E_AQ_PHY_ENABLE_AN 0x10
1828 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1829 __le16 eee_capability
;
1833 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1834 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1835 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1836 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1838 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1839 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1840 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1841 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1842 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1843 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1844 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1848 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config
);
1850 /* Set MAC Config command data structure (direct 0x0603) */
1851 struct i40e_aq_set_mac_config
{
1852 __le16 max_frame_size
;
1854 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1855 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1856 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1857 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1858 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1859 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1860 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1861 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1862 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1863 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1864 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1865 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1866 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1867 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1868 u8 tx_timer_priority
; /* bitmap */
1869 __le16 tx_timer_value
;
1870 __le16 fc_refresh_threshold
;
1874 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config
);
1876 /* Restart Auto-Negotiation (direct 0x605) */
1877 struct i40e_aqc_set_link_restart_an
{
1879 #define I40E_AQ_PHY_RESTART_AN 0x02
1880 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1884 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an
);
1886 /* Get Link Status cmd & response data structure (direct 0x0607) */
1887 struct i40e_aqc_get_link_status
{
1888 __le16 command_flags
; /* only field set on command */
1889 #define I40E_AQ_LSE_MASK 0x3
1890 #define I40E_AQ_LSE_NOP 0x0
1891 #define I40E_AQ_LSE_DISABLE 0x2
1892 #define I40E_AQ_LSE_ENABLE 0x3
1893 /* only response uses this flag */
1894 #define I40E_AQ_LSE_IS_ENABLED 0x1
1895 u8 phy_type
; /* i40e_aq_phy_type */
1896 u8 link_speed
; /* i40e_aq_link_speed */
1898 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1899 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1900 #define I40E_AQ_LINK_FAULT 0x02
1901 #define I40E_AQ_LINK_FAULT_TX 0x04
1902 #define I40E_AQ_LINK_FAULT_RX 0x08
1903 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1904 #define I40E_AQ_LINK_UP_PORT 0x20
1905 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1906 #define I40E_AQ_SIGNAL_DETECT 0x80
1908 #define I40E_AQ_AN_COMPLETED 0x01
1909 #define I40E_AQ_LP_AN_ABILITY 0x02
1910 #define I40E_AQ_PD_FAULT 0x04
1911 #define I40E_AQ_FEC_EN 0x08
1912 #define I40E_AQ_PHY_LOW_POWER 0x10
1913 #define I40E_AQ_LINK_PAUSE_TX 0x20
1914 #define I40E_AQ_LINK_PAUSE_RX 0x40
1915 #define I40E_AQ_QUALIFIED_MODULE 0x80
1917 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1918 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1919 #define I40E_AQ_LINK_TX_SHIFT 0x02
1920 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1921 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1922 #define I40E_AQ_LINK_TX_DRAINED 0x01
1923 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1924 #define I40E_AQ_LINK_FORCED_40G 0x10
1925 /* 25G Error Codes */
1926 #define I40E_AQ_25G_NO_ERR 0X00
1927 #define I40E_AQ_25G_NOT_PRESENT 0X01
1928 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
1929 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1930 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1931 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1932 u8 loopback
; /* use defines from i40e_aqc_set_lb_mode */
1933 __le16 max_frame_size
;
1935 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1936 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1937 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1938 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1940 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1941 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1942 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1943 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1944 #define I40E_AQ_PWR_CLASS_MASK 0x03
1948 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status
);
1950 /* Set event mask command (direct 0x613) */
1951 struct i40e_aqc_set_phy_int_mask
{
1954 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1955 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1956 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1957 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1958 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1959 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1960 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1961 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1962 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1966 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask
);
1968 /* Get Local AN advt register (direct 0x0614)
1969 * Set Local AN advt register (direct 0x0615)
1970 * Get Link Partner AN advt register (direct 0x0616)
1972 struct i40e_aqc_an_advt_reg
{
1973 __le32 local_an_reg0
;
1974 __le16 local_an_reg1
;
1978 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg
);
1980 /* Set Loopback mode (0x0618) */
1981 struct i40e_aqc_set_lb_mode
{
1983 #define I40E_AQ_LB_PHY_LOCAL 0x01
1984 #define I40E_AQ_LB_PHY_REMOTE 0x02
1985 #define I40E_AQ_LB_MAC_LOCAL 0x04
1989 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode
);
1991 /* Set PHY Debug command (0x0622) */
1992 struct i40e_aqc_set_phy_debug
{
1994 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1995 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1996 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1997 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1998 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1999 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2000 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2001 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2005 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug
);
2007 enum i40e_aq_phy_reg_type
{
2008 I40E_AQC_PHY_REG_INTERNAL
= 0x1,
2009 I40E_AQC_PHY_REG_EXERNAL_BASET
= 0x2,
2010 I40E_AQC_PHY_REG_EXERNAL_MODULE
= 0x3
2013 /* Run PHY Activity (0x0626) */
2014 struct i40e_aqc_run_phy_activity
{
2023 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity
);
2025 /* NVM Read command (indirect 0x0701)
2026 * NVM Erase commands (direct 0x0702)
2027 * NVM Update commands (indirect 0x0703)
2029 struct i40e_aqc_nvm_update
{
2031 #define I40E_AQ_NVM_LAST_CMD 0x01
2032 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2040 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update
);
2042 /* NVM Config Read (indirect 0x0704) */
2043 struct i40e_aqc_nvm_config_read
{
2045 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2046 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2047 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2048 __le16 element_count
;
2049 __le16 element_id
; /* Feature/field ID */
2050 __le16 element_id_msw
; /* MSWord of field ID */
2051 __le32 address_high
;
2055 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read
);
2057 /* NVM Config Write (indirect 0x0705) */
2058 struct i40e_aqc_nvm_config_write
{
2060 __le16 element_count
;
2062 __le32 address_high
;
2066 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write
);
2068 /* Used for 0x0704 as well as for 0x0705 commands */
2069 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2070 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2071 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2072 #define I40E_AQ_ANVM_FEATURE 0
2073 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT)
2074 struct i40e_aqc_nvm_config_data_feature
{
2076 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2077 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2078 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2079 __le16 feature_options
;
2080 __le16 feature_selection
;
2083 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature
);
2085 struct i40e_aqc_nvm_config_data_immediate_field
{
2088 __le16 field_options
;
2092 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field
);
2094 /* OEM Post Update (indirect 0x0720)
2095 * no command data struct used
2097 struct i40e_aqc_nvm_oem_post_update
{
2098 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2103 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update
);
2105 struct i40e_aqc_nvm_oem_post_update_buffer
{
2112 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer
);
2114 /* Thermal Sensor (indirect 0x0721)
2115 * read or set thermal sensor configs and values
2116 * takes a sensor and command specific data buffer, not detailed here
2118 struct i40e_aqc_thermal_sensor
{
2120 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2121 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2122 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2128 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor
);
2130 /* Send to PF command (indirect 0x0801) id is only used by PF
2131 * Send to VF command (indirect 0x0802) id is only used by PF
2132 * Send to Peer PF command (indirect 0x0803)
2134 struct i40e_aqc_pf_vf_message
{
2141 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message
);
2143 /* Alternate structure */
2145 /* Direct write (direct 0x0900)
2146 * Direct read (direct 0x0902)
2148 struct i40e_aqc_alternate_write
{
2155 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write
);
2157 /* Indirect write (indirect 0x0901)
2158 * Indirect read (indirect 0x0903)
2161 struct i40e_aqc_alternate_ind_write
{
2168 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write
);
2170 /* Done alternate write (direct 0x0904)
2173 struct i40e_aqc_alternate_write_done
{
2175 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2176 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2177 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2178 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2182 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done
);
2184 /* Set OEM mode (direct 0x0905) */
2185 struct i40e_aqc_alternate_set_mode
{
2187 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2188 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2192 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode
);
2194 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2196 /* async events 0x10xx */
2198 /* Lan Queue Overflow Event (direct, 0x1001) */
2199 struct i40e_aqc_lan_overflow
{
2200 __le32 prtdcb_rupto
;
2205 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow
);
2207 /* Get LLDP MIB (indirect 0x0A00) */
2208 struct i40e_aqc_lldp_get_mib
{
2211 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2212 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2213 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2214 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2215 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2216 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2217 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2218 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2219 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2220 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2221 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2229 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib
);
2231 /* Configure LLDP MIB Change Event (direct 0x0A01)
2232 * also used for the event (with type in the command field)
2234 struct i40e_aqc_lldp_update_mib
{
2236 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2237 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2243 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib
);
2245 /* Add LLDP TLV (indirect 0x0A02)
2246 * Delete LLDP TLV (indirect 0x0A04)
2248 struct i40e_aqc_lldp_add_tlv
{
2249 u8 type
; /* only nearest bridge and non-TPMR from 0x0A00 */
2257 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv
);
2259 /* Update LLDP TLV (indirect 0x0A03) */
2260 struct i40e_aqc_lldp_update_tlv
{
2261 u8 type
; /* only nearest bridge and non-TPMR from 0x0A00 */
2270 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv
);
2272 /* Stop LLDP (direct 0x0A05) */
2273 struct i40e_aqc_lldp_stop
{
2275 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2276 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2280 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop
);
2282 /* Start LLDP (direct 0x0A06) */
2284 struct i40e_aqc_lldp_start
{
2286 #define I40E_AQ_LLDP_AGENT_START 0x1
2290 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start
);
2292 /* Apply MIB changes (0x0A07)
2293 * uses the generic struc as it contains no data
2296 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2297 struct i40e_aqc_add_udp_tunnel
{
2301 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2302 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2303 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2304 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2308 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel
);
2310 struct i40e_aqc_add_udp_tunnel_completion
{
2312 u8 filter_entry_index
;
2314 #define I40E_AQC_SINGLE_PF 0x0
2315 #define I40E_AQC_MULTIPLE_PFS 0x1
2320 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion
);
2322 /* remove UDP Tunnel command (0x0B01) */
2323 struct i40e_aqc_remove_udp_tunnel
{
2325 u8 index
; /* 0 to 15 */
2329 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel
);
2331 struct i40e_aqc_del_udp_tunnel_completion
{
2333 u8 index
; /* 0 to 15 */
2335 u8 total_filters_used
;
2339 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion
);
2341 struct i40e_aqc_get_set_rss_key
{
2342 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2343 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2344 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2345 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2352 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key
);
2354 struct i40e_aqc_get_set_rss_key_data
{
2355 u8 standard_rss_key
[0x28];
2356 u8 extended_hash_key
[0xc];
2359 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data
);
2361 struct i40e_aqc_get_set_rss_lut
{
2362 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2363 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2364 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2365 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2367 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2368 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \
2369 BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2371 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2372 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2379 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut
);
2381 /* tunnel key structure 0x0B10 */
2383 struct i40e_aqc_tunnel_key_structure_A0
{
2389 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2390 /* response flags */
2391 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2392 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2393 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2397 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0
);
2399 struct i40e_aqc_tunnel_key_structure
{
2402 u8 key1_len
; /* 0 to 15 */
2403 u8 key2_len
; /* 0 to 15 */
2405 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2406 /* response flags */
2407 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2408 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2409 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2410 u8 network_key_index
;
2411 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2412 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2413 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2414 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2418 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure
);
2420 /* OEM mode commands (direct 0xFE0x) */
2421 struct i40e_aqc_oem_param_change
{
2423 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2424 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2425 #define I40E_AQ_OEM_PARAM_MAC 2
2426 __le32 param_value1
;
2427 __le16 param_value2
;
2431 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change
);
2433 struct i40e_aqc_oem_state_change
{
2435 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2436 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2440 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change
);
2442 /* Initialize OCSD (0xFE02, direct) */
2443 struct i40e_aqc_opc_oem_ocsd_initialize
{
2446 __le32 ocsd_memory_block_addr_high
;
2447 __le32 ocsd_memory_block_addr_low
;
2448 __le32 requested_update_interval
;
2451 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize
);
2453 /* Initialize OCBB (0xFE03, direct) */
2454 struct i40e_aqc_opc_oem_ocbb_initialize
{
2457 __le32 ocbb_memory_block_addr_high
;
2458 __le32 ocbb_memory_block_addr_low
;
2462 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize
);
2464 /* debug commands */
2466 /* get device id (0xFF00) uses the generic structure */
2468 /* set test more (0xFF01, internal) */
2470 struct i40e_acq_set_test_mode
{
2472 #define I40E_AQ_TEST_PARTIAL 0
2473 #define I40E_AQ_TEST_FULL 1
2474 #define I40E_AQ_TEST_NVM 2
2477 #define I40E_AQ_TEST_OPEN 0
2478 #define I40E_AQ_TEST_CLOSE 1
2479 #define I40E_AQ_TEST_INC 2
2481 __le32 address_high
;
2485 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode
);
2487 /* Debug Read Register command (0xFF03)
2488 * Debug Write Register command (0xFF04)
2490 struct i40e_aqc_debug_reg_read_write
{
2497 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write
);
2499 /* Scatter/gather Reg Read (indirect 0xFF05)
2500 * Scatter/gather Reg Write (indirect 0xFF06)
2503 /* i40e_aq_desc is used for the command */
2504 struct i40e_aqc_debug_reg_sg_element_data
{
2509 /* Debug Modify register (direct 0xFF07) */
2510 struct i40e_aqc_debug_modify_reg
{
2517 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg
);
2519 /* dump internal data (0xFF08, indirect) */
2521 #define I40E_AQ_CLUSTER_ID_AUX 0
2522 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2523 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2524 #define I40E_AQ_CLUSTER_ID_HMC 3
2525 #define I40E_AQ_CLUSTER_ID_MAC0 4
2526 #define I40E_AQ_CLUSTER_ID_MAC1 5
2527 #define I40E_AQ_CLUSTER_ID_MAC2 6
2528 #define I40E_AQ_CLUSTER_ID_MAC3 7
2529 #define I40E_AQ_CLUSTER_ID_DCB 8
2530 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2531 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2532 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2534 struct i40e_aqc_debug_dump_internals
{
2539 __le32 address_high
;
2543 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals
);
2545 struct i40e_aqc_debug_modify_internals
{
2547 u8 cluster_specific_params
[7];
2548 __le32 address_high
;
2552 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals
);
2554 #endif /* _I40E_ADMINQ_CMD_H_ */