1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
30 #include "i40e_prototype.h"
32 static inline __le64
build_ctob(u32 td_cmd
, u32 td_offset
, unsigned int size
,
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA
|
36 ((u64
)td_cmd
<< I40E_TXD_QW1_CMD_SHIFT
) |
37 ((u64
)td_offset
<< I40E_TXD_QW1_OFFSET_SHIFT
) |
38 ((u64
)size
<< I40E_TXD_QW1_TX_BUF_SZ_SHIFT
) |
39 ((u64
)td_tag
<< I40E_TXD_QW1_L2TAG1_SHIFT
));
42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
45 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
46 * @ring: the ring that owns the buffer
47 * @tx_buffer: the buffer to free
49 static void i40e_unmap_and_free_tx_resource(struct i40e_ring
*ring
,
50 struct i40e_tx_buffer
*tx_buffer
)
53 if (tx_buffer
->tx_flags
& I40E_TX_FLAGS_FD_SB
)
54 kfree(tx_buffer
->raw_buf
);
56 dev_kfree_skb_any(tx_buffer
->skb
);
58 if (dma_unmap_len(tx_buffer
, len
))
59 dma_unmap_single(ring
->dev
,
60 dma_unmap_addr(tx_buffer
, dma
),
61 dma_unmap_len(tx_buffer
, len
),
63 } else if (dma_unmap_len(tx_buffer
, len
)) {
64 dma_unmap_page(ring
->dev
,
65 dma_unmap_addr(tx_buffer
, dma
),
66 dma_unmap_len(tx_buffer
, len
),
69 tx_buffer
->next_to_watch
= NULL
;
70 tx_buffer
->skb
= NULL
;
71 dma_unmap_len_set(tx_buffer
, len
, 0);
72 /* tx_buffer must be completely set up in the transmit path */
76 * i40evf_clean_tx_ring - Free any empty Tx buffers
77 * @tx_ring: ring to be cleaned
79 void i40evf_clean_tx_ring(struct i40e_ring
*tx_ring
)
81 unsigned long bi_size
;
84 /* ring already cleared, nothing to do */
88 /* Free all the Tx ring sk_buffs */
89 for (i
= 0; i
< tx_ring
->count
; i
++)
90 i40e_unmap_and_free_tx_resource(tx_ring
, &tx_ring
->tx_bi
[i
]);
92 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
93 memset(tx_ring
->tx_bi
, 0, bi_size
);
95 /* Zero out the descriptor ring */
96 memset(tx_ring
->desc
, 0, tx_ring
->size
);
98 tx_ring
->next_to_use
= 0;
99 tx_ring
->next_to_clean
= 0;
101 if (!tx_ring
->netdev
)
104 /* cleanup Tx queue statistics */
105 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring
->netdev
,
106 tx_ring
->queue_index
));
110 * i40evf_free_tx_resources - Free Tx resources per queue
111 * @tx_ring: Tx descriptor ring for a specific queue
113 * Free all transmit software resources
115 void i40evf_free_tx_resources(struct i40e_ring
*tx_ring
)
117 i40evf_clean_tx_ring(tx_ring
);
118 kfree(tx_ring
->tx_bi
);
119 tx_ring
->tx_bi
= NULL
;
122 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
123 tx_ring
->desc
, tx_ring
->dma
);
124 tx_ring
->desc
= NULL
;
129 * i40e_get_tx_pending - how many tx descriptors not processed
130 * @tx_ring: the ring of descriptors
132 * Since there is no access to the ring head register
133 * in XL710, we need to use our local copies
135 static u32
i40e_get_tx_pending(struct i40e_ring
*ring
)
137 u32 ntu
= ((ring
->next_to_clean
<= ring
->next_to_use
)
139 : ring
->next_to_use
+ ring
->count
);
140 return ntu
- ring
->next_to_clean
;
144 * i40e_check_tx_hang - Is there a hang in the Tx queue
145 * @tx_ring: the ring of descriptors
147 static bool i40e_check_tx_hang(struct i40e_ring
*tx_ring
)
149 u32 tx_pending
= i40e_get_tx_pending(tx_ring
);
152 clear_check_for_tx_hang(tx_ring
);
154 /* Check for a hung queue, but be thorough. This verifies
155 * that a transmit has been completed since the previous
156 * check AND there is at least one packet pending. The
157 * ARMED bit is set to indicate a potential hang. The
158 * bit is cleared if a pause frame is received to remove
159 * false hang detection due to PFC or 802.3x frames. By
160 * requiring this to fail twice we avoid races with
161 * PFC clearing the ARMED bit and conditions where we
162 * run the check_tx_hang logic with a transmit completion
163 * pending but without time to complete it yet.
165 if ((tx_ring
->tx_stats
.tx_done_old
== tx_ring
->stats
.packets
) &&
166 (tx_pending
>= I40E_MIN_DESC_PENDING
)) {
167 /* make sure it is true for two checks in a row */
168 ret
= test_and_set_bit(__I40E_HANG_CHECK_ARMED
,
170 } else if (!(tx_ring
->tx_stats
.tx_done_old
== tx_ring
->stats
.packets
) ||
171 !(tx_pending
< I40E_MIN_DESC_PENDING
) ||
173 /* update completed stats and disarm the hang check */
174 tx_ring
->tx_stats
.tx_done_old
= tx_ring
->stats
.packets
;
175 clear_bit(__I40E_HANG_CHECK_ARMED
, &tx_ring
->state
);
182 * i40e_get_head - Retrieve head from head writeback
183 * @tx_ring: tx ring to fetch head of
185 * Returns value of Tx ring head based on value stored
186 * in head write-back location
188 static inline u32
i40e_get_head(struct i40e_ring
*tx_ring
)
190 void *head
= (struct i40e_tx_desc
*)tx_ring
->desc
+ tx_ring
->count
;
192 return le32_to_cpu(*(volatile __le32
*)head
);
195 #define WB_STRIDE 0x3
198 * i40e_clean_tx_irq - Reclaim resources after transmit completes
199 * @tx_ring: tx ring to clean
200 * @budget: how many cleans we're allowed
202 * Returns true if there's any budget left (e.g. the clean is finished)
204 static bool i40e_clean_tx_irq(struct i40e_ring
*tx_ring
, int budget
)
206 u16 i
= tx_ring
->next_to_clean
;
207 struct i40e_tx_buffer
*tx_buf
;
208 struct i40e_tx_desc
*tx_head
;
209 struct i40e_tx_desc
*tx_desc
;
210 unsigned int total_packets
= 0;
211 unsigned int total_bytes
= 0;
213 tx_buf
= &tx_ring
->tx_bi
[i
];
214 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
217 tx_head
= I40E_TX_DESC(tx_ring
, i40e_get_head(tx_ring
));
220 struct i40e_tx_desc
*eop_desc
= tx_buf
->next_to_watch
;
222 /* if next_to_watch is not set then there is no work pending */
226 /* prevent any other reads prior to eop_desc */
227 read_barrier_depends();
229 /* we have caught up to head, no work left to do */
230 if (tx_head
== tx_desc
)
233 /* clear next_to_watch to prevent false hangs */
234 tx_buf
->next_to_watch
= NULL
;
236 /* update the statistics for this packet */
237 total_bytes
+= tx_buf
->bytecount
;
238 total_packets
+= tx_buf
->gso_segs
;
241 dev_kfree_skb_any(tx_buf
->skb
);
243 /* unmap skb header data */
244 dma_unmap_single(tx_ring
->dev
,
245 dma_unmap_addr(tx_buf
, dma
),
246 dma_unmap_len(tx_buf
, len
),
249 /* clear tx_buffer data */
251 dma_unmap_len_set(tx_buf
, len
, 0);
253 /* unmap remaining buffers */
254 while (tx_desc
!= eop_desc
) {
261 tx_buf
= tx_ring
->tx_bi
;
262 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
265 /* unmap any remaining paged data */
266 if (dma_unmap_len(tx_buf
, len
)) {
267 dma_unmap_page(tx_ring
->dev
,
268 dma_unmap_addr(tx_buf
, dma
),
269 dma_unmap_len(tx_buf
, len
),
271 dma_unmap_len_set(tx_buf
, len
, 0);
275 /* move us one more past the eop_desc for start of next pkt */
281 tx_buf
= tx_ring
->tx_bi
;
282 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
285 /* update budget accounting */
287 } while (likely(budget
));
290 tx_ring
->next_to_clean
= i
;
291 u64_stats_update_begin(&tx_ring
->syncp
);
292 tx_ring
->stats
.bytes
+= total_bytes
;
293 tx_ring
->stats
.packets
+= total_packets
;
294 u64_stats_update_end(&tx_ring
->syncp
);
295 tx_ring
->q_vector
->tx
.total_bytes
+= total_bytes
;
296 tx_ring
->q_vector
->tx
.total_packets
+= total_packets
;
299 !((i
& WB_STRIDE
) == WB_STRIDE
) &&
300 !test_bit(__I40E_DOWN
, &tx_ring
->vsi
->state
) &&
301 (I40E_DESC_UNUSED(tx_ring
) != tx_ring
->count
))
302 tx_ring
->arm_wb
= true;
304 tx_ring
->arm_wb
= false;
306 if (check_for_tx_hang(tx_ring
) && i40e_check_tx_hang(tx_ring
)) {
307 /* schedule immediate reset if we believe we hung */
308 dev_info(tx_ring
->dev
, "Detected Tx Unit Hang\n"
311 " next_to_use <%x>\n"
312 " next_to_clean <%x>\n",
314 tx_ring
->queue_index
,
315 tx_ring
->next_to_use
, i
);
316 dev_info(tx_ring
->dev
, "tx_bi[next_to_clean]\n"
317 " time_stamp <%lx>\n"
319 tx_ring
->tx_bi
[i
].time_stamp
, jiffies
);
321 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
323 dev_info(tx_ring
->dev
,
324 "tx hang detected on queue %d, resetting adapter\n",
325 tx_ring
->queue_index
);
327 tx_ring
->netdev
->netdev_ops
->ndo_tx_timeout(tx_ring
->netdev
);
329 /* the adapter is about to reset, no point in enabling stuff */
333 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring
->netdev
,
334 tx_ring
->queue_index
),
335 total_packets
, total_bytes
);
337 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
338 if (unlikely(total_packets
&& netif_carrier_ok(tx_ring
->netdev
) &&
339 (I40E_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
340 /* Make sure that anybody stopping the queue after this
341 * sees the new next_to_clean.
344 if (__netif_subqueue_stopped(tx_ring
->netdev
,
345 tx_ring
->queue_index
) &&
346 !test_bit(__I40E_DOWN
, &tx_ring
->vsi
->state
)) {
347 netif_wake_subqueue(tx_ring
->netdev
,
348 tx_ring
->queue_index
);
349 ++tx_ring
->tx_stats
.restart_queue
;
357 * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
358 * @vsi: the VSI we care about
359 * @q_vector: the vector on which to force writeback
362 static void i40e_force_wb(struct i40e_vsi
*vsi
, struct i40e_q_vector
*q_vector
)
364 u32 val
= I40E_VFINT_DYN_CTLN_INTENA_MASK
|
365 I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK
|
366 I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK
;
367 /* allow 00 to be written to the index */
370 I40E_VFINT_DYN_CTLN1(q_vector
->v_idx
+ vsi
->base_vector
- 1),
375 * i40e_set_new_dynamic_itr - Find new ITR level
376 * @rc: structure containing ring performance data
378 * Stores a new ITR value based on packets and byte counts during
379 * the last interrupt. The advantage of per interrupt computation
380 * is faster updates and more accurate ITR for the current traffic
381 * pattern. Constants in this function were computed based on
382 * theoretical maximum wire speed and thresholds were set based on
383 * testing data as well as attempting to minimize response time
384 * while increasing bulk throughput.
386 static void i40e_set_new_dynamic_itr(struct i40e_ring_container
*rc
)
388 enum i40e_latency_range new_latency_range
= rc
->latency_range
;
389 u32 new_itr
= rc
->itr
;
392 if (rc
->total_packets
== 0 || !rc
->itr
)
395 /* simple throttlerate management
396 * 0-10MB/s lowest (100000 ints/s)
397 * 10-20MB/s low (20000 ints/s)
398 * 20-1249MB/s bulk (8000 ints/s)
400 bytes_per_int
= rc
->total_bytes
/ rc
->itr
;
402 case I40E_LOWEST_LATENCY
:
403 if (bytes_per_int
> 10)
404 new_latency_range
= I40E_LOW_LATENCY
;
406 case I40E_LOW_LATENCY
:
407 if (bytes_per_int
> 20)
408 new_latency_range
= I40E_BULK_LATENCY
;
409 else if (bytes_per_int
<= 10)
410 new_latency_range
= I40E_LOWEST_LATENCY
;
412 case I40E_BULK_LATENCY
:
413 if (bytes_per_int
<= 20)
414 rc
->latency_range
= I40E_LOW_LATENCY
;
418 switch (new_latency_range
) {
419 case I40E_LOWEST_LATENCY
:
420 new_itr
= I40E_ITR_100K
;
422 case I40E_LOW_LATENCY
:
423 new_itr
= I40E_ITR_20K
;
425 case I40E_BULK_LATENCY
:
426 new_itr
= I40E_ITR_8K
;
432 if (new_itr
!= rc
->itr
) {
433 /* do an exponential smoothing */
434 new_itr
= (10 * new_itr
* rc
->itr
) /
435 ((9 * new_itr
) + rc
->itr
);
436 rc
->itr
= new_itr
& I40E_MAX_ITR
;
440 rc
->total_packets
= 0;
444 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
445 * @q_vector: the vector to adjust
447 static void i40e_update_dynamic_itr(struct i40e_q_vector
*q_vector
)
449 u16 vector
= q_vector
->vsi
->base_vector
+ q_vector
->v_idx
;
450 struct i40e_hw
*hw
= &q_vector
->vsi
->back
->hw
;
454 reg_addr
= I40E_VFINT_ITRN1(I40E_RX_ITR
, vector
- 1);
455 old_itr
= q_vector
->rx
.itr
;
456 i40e_set_new_dynamic_itr(&q_vector
->rx
);
457 if (old_itr
!= q_vector
->rx
.itr
)
458 wr32(hw
, reg_addr
, q_vector
->rx
.itr
);
460 reg_addr
= I40E_VFINT_ITRN1(I40E_TX_ITR
, vector
- 1);
461 old_itr
= q_vector
->tx
.itr
;
462 i40e_set_new_dynamic_itr(&q_vector
->tx
);
463 if (old_itr
!= q_vector
->tx
.itr
)
464 wr32(hw
, reg_addr
, q_vector
->tx
.itr
);
468 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
469 * @tx_ring: the tx ring to set up
471 * Return 0 on success, negative on error
473 int i40evf_setup_tx_descriptors(struct i40e_ring
*tx_ring
)
475 struct device
*dev
= tx_ring
->dev
;
481 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
482 tx_ring
->tx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
486 /* round up to nearest 4K */
487 tx_ring
->size
= tx_ring
->count
* sizeof(struct i40e_tx_desc
);
488 /* add u32 for head writeback, align after this takes care of
489 * guaranteeing this is at least one cache line in size
491 tx_ring
->size
+= sizeof(u32
);
492 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
493 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
494 &tx_ring
->dma
, GFP_KERNEL
);
495 if (!tx_ring
->desc
) {
496 dev_info(dev
, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
501 tx_ring
->next_to_use
= 0;
502 tx_ring
->next_to_clean
= 0;
506 kfree(tx_ring
->tx_bi
);
507 tx_ring
->tx_bi
= NULL
;
512 * i40evf_clean_rx_ring - Free Rx buffers
513 * @rx_ring: ring to be cleaned
515 void i40evf_clean_rx_ring(struct i40e_ring
*rx_ring
)
517 struct device
*dev
= rx_ring
->dev
;
518 struct i40e_rx_buffer
*rx_bi
;
519 unsigned long bi_size
;
522 /* ring already cleared, nothing to do */
526 /* Free all the Rx ring sk_buffs */
527 for (i
= 0; i
< rx_ring
->count
; i
++) {
528 rx_bi
= &rx_ring
->rx_bi
[i
];
530 dma_unmap_single(dev
,
537 dev_kfree_skb(rx_bi
->skb
);
541 if (rx_bi
->page_dma
) {
548 __free_page(rx_bi
->page
);
550 rx_bi
->page_offset
= 0;
554 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
555 memset(rx_ring
->rx_bi
, 0, bi_size
);
557 /* Zero out the descriptor ring */
558 memset(rx_ring
->desc
, 0, rx_ring
->size
);
560 rx_ring
->next_to_clean
= 0;
561 rx_ring
->next_to_use
= 0;
565 * i40evf_free_rx_resources - Free Rx resources
566 * @rx_ring: ring to clean the resources from
568 * Free all receive software resources
570 void i40evf_free_rx_resources(struct i40e_ring
*rx_ring
)
572 i40evf_clean_rx_ring(rx_ring
);
573 kfree(rx_ring
->rx_bi
);
574 rx_ring
->rx_bi
= NULL
;
577 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
578 rx_ring
->desc
, rx_ring
->dma
);
579 rx_ring
->desc
= NULL
;
584 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
585 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
587 * Returns 0 on success, negative on failure
589 int i40evf_setup_rx_descriptors(struct i40e_ring
*rx_ring
)
591 struct device
*dev
= rx_ring
->dev
;
594 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
595 rx_ring
->rx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
599 u64_stats_init(&rx_ring
->syncp
);
601 /* Round up to nearest 4K */
602 rx_ring
->size
= ring_is_16byte_desc_enabled(rx_ring
)
603 ? rx_ring
->count
* sizeof(union i40e_16byte_rx_desc
)
604 : rx_ring
->count
* sizeof(union i40e_32byte_rx_desc
);
605 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
606 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
607 &rx_ring
->dma
, GFP_KERNEL
);
609 if (!rx_ring
->desc
) {
610 dev_info(dev
, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
615 rx_ring
->next_to_clean
= 0;
616 rx_ring
->next_to_use
= 0;
620 kfree(rx_ring
->rx_bi
);
621 rx_ring
->rx_bi
= NULL
;
626 * i40e_release_rx_desc - Store the new tail and head values
627 * @rx_ring: ring to bump
628 * @val: new head index
630 static inline void i40e_release_rx_desc(struct i40e_ring
*rx_ring
, u32 val
)
632 rx_ring
->next_to_use
= val
;
633 /* Force memory writes to complete before letting h/w
634 * know there are new descriptors to fetch. (Only
635 * applicable for weak-ordered memory model archs,
639 writel(val
, rx_ring
->tail
);
643 * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
644 * @rx_ring: ring to place buffers on
645 * @cleaned_count: number of buffers to replace
647 void i40evf_alloc_rx_buffers(struct i40e_ring
*rx_ring
, u16 cleaned_count
)
649 u16 i
= rx_ring
->next_to_use
;
650 union i40e_rx_desc
*rx_desc
;
651 struct i40e_rx_buffer
*bi
;
654 /* do nothing if no valid netdev defined */
655 if (!rx_ring
->netdev
|| !cleaned_count
)
658 while (cleaned_count
--) {
659 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
660 bi
= &rx_ring
->rx_bi
[i
];
664 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
665 rx_ring
->rx_buf_len
);
667 rx_ring
->rx_stats
.alloc_buff_failed
++;
670 /* initialize queue mapping */
671 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
676 bi
->dma
= dma_map_single(rx_ring
->dev
,
680 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
681 rx_ring
->rx_stats
.alloc_buff_failed
++;
687 if (ring_is_ps_enabled(rx_ring
)) {
689 bi
->page
= alloc_page(GFP_ATOMIC
);
691 rx_ring
->rx_stats
.alloc_page_failed
++;
697 /* use a half page if we're re-using */
698 bi
->page_offset
^= PAGE_SIZE
/ 2;
699 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
704 if (dma_mapping_error(rx_ring
->dev
,
706 rx_ring
->rx_stats
.alloc_page_failed
++;
712 /* Refresh the desc even if buffer_addrs didn't change
713 * because each write-back erases this info.
715 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
716 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
718 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
719 rx_desc
->read
.hdr_addr
= 0;
722 if (i
== rx_ring
->count
)
727 if (rx_ring
->next_to_use
!= i
)
728 i40e_release_rx_desc(rx_ring
, i
);
732 * i40e_receive_skb - Send a completed packet up the stack
733 * @rx_ring: rx ring in play
734 * @skb: packet to send up
735 * @vlan_tag: vlan tag for packet
737 static void i40e_receive_skb(struct i40e_ring
*rx_ring
,
738 struct sk_buff
*skb
, u16 vlan_tag
)
740 struct i40e_q_vector
*q_vector
= rx_ring
->q_vector
;
741 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
742 u64 flags
= vsi
->back
->flags
;
744 if (vlan_tag
& VLAN_VID_MASK
)
745 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlan_tag
);
747 if (flags
& I40E_FLAG_IN_NETPOLL
)
750 napi_gro_receive(&q_vector
->napi
, skb
);
754 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
755 * @vsi: the VSI we care about
756 * @skb: skb currently being received and modified
757 * @rx_status: status value of last descriptor in packet
758 * @rx_error: error value of last descriptor in packet
759 * @rx_ptype: ptype value of last descriptor in packet
761 static inline void i40e_rx_checksum(struct i40e_vsi
*vsi
,
767 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(rx_ptype
);
768 bool ipv4
= false, ipv6
= false;
769 bool ipv4_tunnel
, ipv6_tunnel
;
774 ipv4_tunnel
= (rx_ptype
> I40E_RX_PTYPE_GRENAT4_MAC_PAY3
) &&
775 (rx_ptype
< I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4
);
776 ipv6_tunnel
= (rx_ptype
> I40E_RX_PTYPE_GRENAT6_MAC_PAY3
) &&
777 (rx_ptype
< I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4
);
779 skb
->ip_summed
= CHECKSUM_NONE
;
781 /* Rx csum enabled and ip headers found? */
782 if (!(vsi
->netdev
->features
& NETIF_F_RXCSUM
))
785 /* did the hardware decode the packet and checksum? */
786 if (!(rx_status
& (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT
)))
789 /* both known and outer_ip must be set for the below code to work */
790 if (!(decoded
.known
&& decoded
.outer_ip
))
793 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
794 decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV4
)
796 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
797 decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV6
)
801 (rx_error
& ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT
) |
802 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT
))))
805 /* likely incorrect csum if alternate IP extension headers found */
807 rx_status
& (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT
))
808 /* don't increment checksum err here, non-fatal err */
811 /* there was some L4 error, count error and punt packet to the stack */
812 if (rx_error
& (1 << I40E_RX_DESC_ERROR_L4E_SHIFT
))
815 /* handle packets that were not able to be checksummed due
816 * to arrival speed, in this case the stack can compute
819 if (rx_error
& (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT
))
822 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
823 * it in the driver, hardware does not do it for us.
824 * Since L3L4P bit was set we assume a valid IHL value (>=5)
825 * so the total length of IPv4 header is IHL*4 bytes
826 * The UDP_0 bit *may* bet set if the *inner* header is UDP
829 (decoded
.inner_prot
!= I40E_RX_PTYPE_INNER_PROT_UDP
) &&
830 !(rx_status
& (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT
))) {
831 skb
->transport_header
= skb
->mac_header
+
832 sizeof(struct ethhdr
) +
833 (ip_hdr(skb
)->ihl
* 4);
835 /* Add 4 bytes for VLAN tagged packets */
836 skb
->transport_header
+= (skb
->protocol
== htons(ETH_P_8021Q
) ||
837 skb
->protocol
== htons(ETH_P_8021AD
))
840 rx_udp_csum
= udp_csum(skb
);
842 csum
= csum_tcpudp_magic(
843 iph
->saddr
, iph
->daddr
,
844 (skb
->len
- skb_transport_offset(skb
)),
845 IPPROTO_UDP
, rx_udp_csum
);
847 if (udp_hdr(skb
)->check
!= csum
)
851 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
852 skb
->csum_level
= ipv4_tunnel
|| ipv6_tunnel
;
857 vsi
->back
->hw_csum_rx_error
++;
861 * i40e_rx_hash - returns the hash value from the Rx descriptor
862 * @ring: descriptor ring
863 * @rx_desc: specific descriptor
865 static inline u32
i40e_rx_hash(struct i40e_ring
*ring
,
866 union i40e_rx_desc
*rx_desc
)
868 const __le64 rss_mask
=
869 cpu_to_le64((u64
)I40E_RX_DESC_FLTSTAT_RSS_HASH
<<
870 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT
);
872 if ((ring
->netdev
->features
& NETIF_F_RXHASH
) &&
873 (rx_desc
->wb
.qword1
.status_error_len
& rss_mask
) == rss_mask
)
874 return le32_to_cpu(rx_desc
->wb
.qword0
.hi_dword
.rss
);
880 * i40e_ptype_to_hash - get a hash type
881 * @ptype: the ptype value from the descriptor
883 * Returns a hash type to be used by skb_set_hash
885 static inline enum pkt_hash_types
i40e_ptype_to_hash(u8 ptype
)
887 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(ptype
);
890 return PKT_HASH_TYPE_NONE
;
892 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
893 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4
)
894 return PKT_HASH_TYPE_L4
;
895 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
896 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3
)
897 return PKT_HASH_TYPE_L3
;
899 return PKT_HASH_TYPE_L2
;
903 * i40e_clean_rx_irq - Reclaim resources after receive completes
904 * @rx_ring: rx ring to clean
905 * @budget: how many cleans we're allowed
907 * Returns true if there's any budget left (e.g. the clean is finished)
909 static int i40e_clean_rx_irq(struct i40e_ring
*rx_ring
, int budget
)
911 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
912 u16 rx_packet_len
, rx_header_len
, rx_sph
, rx_hbo
;
913 u16 cleaned_count
= I40E_DESC_UNUSED(rx_ring
);
914 const int current_node
= numa_node_id();
915 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
916 u16 i
= rx_ring
->next_to_clean
;
917 union i40e_rx_desc
*rx_desc
;
918 u32 rx_error
, rx_status
;
922 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
923 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
924 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
925 I40E_RXD_QW1_STATUS_SHIFT
;
927 while (rx_status
& (1 << I40E_RX_DESC_STATUS_DD_SHIFT
)) {
928 union i40e_rx_desc
*next_rxd
;
929 struct i40e_rx_buffer
*rx_bi
;
932 rx_bi
= &rx_ring
->rx_bi
[i
];
936 rx_packet_len
= (qword
& I40E_RXD_QW1_LENGTH_PBUF_MASK
) >>
937 I40E_RXD_QW1_LENGTH_PBUF_SHIFT
;
938 rx_header_len
= (qword
& I40E_RXD_QW1_LENGTH_HBUF_MASK
) >>
939 I40E_RXD_QW1_LENGTH_HBUF_SHIFT
;
940 rx_sph
= (qword
& I40E_RXD_QW1_LENGTH_SPH_MASK
) >>
941 I40E_RXD_QW1_LENGTH_SPH_SHIFT
;
943 rx_error
= (qword
& I40E_RXD_QW1_ERROR_MASK
) >>
944 I40E_RXD_QW1_ERROR_SHIFT
;
945 rx_hbo
= rx_error
& (1 << I40E_RX_DESC_ERROR_HBO_SHIFT
);
946 rx_error
&= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT
);
948 rx_ptype
= (qword
& I40E_RXD_QW1_PTYPE_MASK
) >>
949 I40E_RXD_QW1_PTYPE_SHIFT
;
952 /* This memory barrier is needed to keep us from reading
953 * any other fields out of the rx_desc until we know the
954 * STATUS_DD bit is set
958 /* Get the header and possibly the whole packet
959 * If this is an skb from previous receive dma will be 0
965 len
= I40E_RX_HDR_SIZE
;
968 else if (rx_packet_len
)
969 len
= rx_packet_len
; /* 1buf/no split found */
971 len
= rx_header_len
; /* split always mode */
974 dma_unmap_single(rx_ring
->dev
,
981 /* Get the rest of the data if this was a header split */
982 if (ring_is_ps_enabled(rx_ring
) && rx_packet_len
) {
984 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
989 skb
->len
+= rx_packet_len
;
990 skb
->data_len
+= rx_packet_len
;
991 skb
->truesize
+= rx_packet_len
;
993 if ((page_count(rx_bi
->page
) == 1) &&
994 (page_to_nid(rx_bi
->page
) == current_node
))
995 get_page(rx_bi
->page
);
999 dma_unmap_page(rx_ring
->dev
,
1003 rx_bi
->page_dma
= 0;
1005 I40E_RX_NEXT_DESC_PREFETCH(rx_ring
, i
, next_rxd
);
1008 !(rx_status
& (1 << I40E_RX_DESC_STATUS_EOF_SHIFT
)))) {
1009 struct i40e_rx_buffer
*next_buffer
;
1011 next_buffer
= &rx_ring
->rx_bi
[i
];
1013 if (ring_is_ps_enabled(rx_ring
)) {
1014 rx_bi
->skb
= next_buffer
->skb
;
1015 rx_bi
->dma
= next_buffer
->dma
;
1016 next_buffer
->skb
= skb
;
1017 next_buffer
->dma
= 0;
1019 rx_ring
->rx_stats
.non_eop_descs
++;
1023 /* ERR_MASK will only have valid bits if EOP set */
1024 if (unlikely(rx_error
& (1 << I40E_RX_DESC_ERROR_RXE_SHIFT
))) {
1025 dev_kfree_skb_any(skb
);
1026 /* TODO: shouldn't we increment a counter indicating the
1032 skb_set_hash(skb
, i40e_rx_hash(rx_ring
, rx_desc
),
1033 i40e_ptype_to_hash(rx_ptype
));
1034 /* probably a little skewed due to removing CRC */
1035 total_rx_bytes
+= skb
->len
;
1038 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1040 i40e_rx_checksum(vsi
, skb
, rx_status
, rx_error
, rx_ptype
);
1042 vlan_tag
= rx_status
& (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
)
1043 ? le16_to_cpu(rx_desc
->wb
.qword0
.lo_dword
.l2tag1
)
1045 i40e_receive_skb(rx_ring
, skb
, vlan_tag
);
1047 rx_ring
->netdev
->last_rx
= jiffies
;
1050 rx_desc
->wb
.qword1
.status_error_len
= 0;
1055 /* return some buffers to hardware, one at a time is too slow */
1056 if (cleaned_count
>= I40E_RX_BUFFER_WRITE
) {
1057 i40evf_alloc_rx_buffers(rx_ring
, cleaned_count
);
1061 /* use prefetched values */
1063 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
1064 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
1065 I40E_RXD_QW1_STATUS_SHIFT
;
1068 rx_ring
->next_to_clean
= i
;
1069 u64_stats_update_begin(&rx_ring
->syncp
);
1070 rx_ring
->stats
.packets
+= total_rx_packets
;
1071 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1072 u64_stats_update_end(&rx_ring
->syncp
);
1073 rx_ring
->q_vector
->rx
.total_packets
+= total_rx_packets
;
1074 rx_ring
->q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1077 i40evf_alloc_rx_buffers(rx_ring
, cleaned_count
);
1083 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1084 * @napi: napi struct with our devices info in it
1085 * @budget: amount of work driver is allowed to do this pass, in packets
1087 * This function will clean all queues associated with a q_vector.
1089 * Returns the amount of work done
1091 int i40evf_napi_poll(struct napi_struct
*napi
, int budget
)
1093 struct i40e_q_vector
*q_vector
=
1094 container_of(napi
, struct i40e_q_vector
, napi
);
1095 struct i40e_vsi
*vsi
= q_vector
->vsi
;
1096 struct i40e_ring
*ring
;
1097 bool clean_complete
= true;
1098 bool arm_wb
= false;
1099 int budget_per_ring
;
1101 if (test_bit(__I40E_DOWN
, &vsi
->state
)) {
1102 napi_complete(napi
);
1106 /* Since the actual Tx work is minimal, we can give the Tx a larger
1107 * budget and be more aggressive about cleaning up the Tx descriptors.
1109 i40e_for_each_ring(ring
, q_vector
->tx
) {
1110 clean_complete
&= i40e_clean_tx_irq(ring
, vsi
->work_limit
);
1111 arm_wb
|= ring
->arm_wb
;
1114 /* We attempt to distribute budget to each Rx queue fairly, but don't
1115 * allow the budget to go below 1 because that would exit polling early.
1117 budget_per_ring
= max(budget
/q_vector
->num_ringpairs
, 1);
1119 i40e_for_each_ring(ring
, q_vector
->rx
)
1120 clean_complete
&= i40e_clean_rx_irq(ring
, budget_per_ring
);
1122 /* If work not completed, return budget and polling will return */
1123 if (!clean_complete
) {
1125 i40e_force_wb(vsi
, q_vector
);
1129 /* Work is done so exit the polling mode and re-enable the interrupt */
1130 napi_complete(napi
);
1131 if (ITR_IS_DYNAMIC(vsi
->rx_itr_setting
) ||
1132 ITR_IS_DYNAMIC(vsi
->tx_itr_setting
))
1133 i40e_update_dynamic_itr(q_vector
);
1135 if (!test_bit(__I40E_DOWN
, &vsi
->state
))
1136 i40evf_irq_enable_queues(vsi
->back
, 1 << q_vector
->v_idx
);
1142 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1144 * @tx_ring: ring to send buffer on
1145 * @flags: the tx flags to be set
1147 * Checks the skb and set up correspondingly several generic transmit flags
1148 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1150 * Returns error code indicate the frame should be dropped upon error and the
1151 * otherwise returns 0 to indicate the flags has been set properly.
1153 static int i40e_tx_prepare_vlan_flags(struct sk_buff
*skb
,
1154 struct i40e_ring
*tx_ring
,
1157 __be16 protocol
= skb
->protocol
;
1160 /* if we have a HW VLAN tag being added, default to the HW one */
1161 if (skb_vlan_tag_present(skb
)) {
1162 tx_flags
|= skb_vlan_tag_get(skb
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1163 tx_flags
|= I40E_TX_FLAGS_HW_VLAN
;
1164 /* else if it is a SW VLAN, check the next protocol and store the tag */
1165 } else if (protocol
== htons(ETH_P_8021Q
)) {
1166 struct vlan_hdr
*vhdr
, _vhdr
;
1167 vhdr
= skb_header_pointer(skb
, ETH_HLEN
, sizeof(_vhdr
), &_vhdr
);
1171 protocol
= vhdr
->h_vlan_encapsulated_proto
;
1172 tx_flags
|= ntohs(vhdr
->h_vlan_TCI
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1173 tx_flags
|= I40E_TX_FLAGS_SW_VLAN
;
1181 * i40e_tso - set up the tso context descriptor
1182 * @tx_ring: ptr to the ring to send
1183 * @skb: ptr to the skb we're sending
1184 * @tx_flags: the collected send information
1185 * @protocol: the send protocol
1186 * @hdr_len: ptr to the size of the packet header
1187 * @cd_tunneling: ptr to context descriptor bits
1189 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1191 static int i40e_tso(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1192 u32 tx_flags
, __be16 protocol
, u8
*hdr_len
,
1193 u64
*cd_type_cmd_tso_mss
, u32
*cd_tunneling
)
1195 u32 cd_cmd
, cd_tso_len
, cd_mss
;
1196 struct ipv6hdr
*ipv6h
;
1197 struct tcphdr
*tcph
;
1202 if (!skb_is_gso(skb
))
1205 err
= skb_cow_head(skb
, 0);
1209 if (protocol
== htons(ETH_P_IP
)) {
1210 iph
= skb
->encapsulation
? inner_ip_hdr(skb
) : ip_hdr(skb
);
1211 tcph
= skb
->encapsulation
? inner_tcp_hdr(skb
) : tcp_hdr(skb
);
1214 tcph
->check
= ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
,
1216 } else if (skb_is_gso_v6(skb
)) {
1218 ipv6h
= skb
->encapsulation
? inner_ipv6_hdr(skb
)
1220 tcph
= skb
->encapsulation
? inner_tcp_hdr(skb
) : tcp_hdr(skb
);
1221 ipv6h
->payload_len
= 0;
1222 tcph
->check
= ~csum_ipv6_magic(&ipv6h
->saddr
, &ipv6h
->daddr
,
1226 l4len
= skb
->encapsulation
? inner_tcp_hdrlen(skb
) : tcp_hdrlen(skb
);
1227 *hdr_len
= (skb
->encapsulation
1228 ? (skb_inner_transport_header(skb
) - skb
->data
)
1229 : skb_transport_offset(skb
)) + l4len
;
1231 /* find the field values */
1232 cd_cmd
= I40E_TX_CTX_DESC_TSO
;
1233 cd_tso_len
= skb
->len
- *hdr_len
;
1234 cd_mss
= skb_shinfo(skb
)->gso_size
;
1235 *cd_type_cmd_tso_mss
|= ((u64
)cd_cmd
<< I40E_TXD_CTX_QW1_CMD_SHIFT
) |
1237 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT
) |
1238 ((u64
)cd_mss
<< I40E_TXD_CTX_QW1_MSS_SHIFT
);
1243 * i40e_tx_enable_csum - Enable Tx checksum offloads
1245 * @tx_flags: Tx flags currently set
1246 * @td_cmd: Tx descriptor command bits to set
1247 * @td_offset: Tx descriptor header offsets to set
1248 * @cd_tunneling: ptr to context desc bits
1250 static void i40e_tx_enable_csum(struct sk_buff
*skb
, u32 tx_flags
,
1251 u32
*td_cmd
, u32
*td_offset
,
1252 struct i40e_ring
*tx_ring
,
1255 struct ipv6hdr
*this_ipv6_hdr
;
1256 unsigned int this_tcp_hdrlen
;
1257 struct iphdr
*this_ip_hdr
;
1258 u32 network_hdr_len
;
1261 if (skb
->encapsulation
) {
1262 network_hdr_len
= skb_inner_network_header_len(skb
);
1263 this_ip_hdr
= inner_ip_hdr(skb
);
1264 this_ipv6_hdr
= inner_ipv6_hdr(skb
);
1265 this_tcp_hdrlen
= inner_tcp_hdrlen(skb
);
1267 if (tx_flags
& I40E_TX_FLAGS_IPV4
) {
1269 if (tx_flags
& I40E_TX_FLAGS_TSO
) {
1270 *cd_tunneling
|= I40E_TX_CTX_EXT_IP_IPV4
;
1271 ip_hdr(skb
)->check
= 0;
1274 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
;
1276 } else if (tx_flags
& I40E_TX_FLAGS_IPV6
) {
1277 if (tx_flags
& I40E_TX_FLAGS_TSO
) {
1278 *cd_tunneling
|= I40E_TX_CTX_EXT_IP_IPV6
;
1279 ip_hdr(skb
)->check
= 0;
1282 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
;
1286 /* Now set the ctx descriptor fields */
1287 *cd_tunneling
|= (skb_network_header_len(skb
) >> 2) <<
1288 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT
|
1289 I40E_TXD_CTX_UDP_TUNNELING
|
1290 ((skb_inner_network_offset(skb
) -
1291 skb_transport_offset(skb
)) >> 1) <<
1292 I40E_TXD_CTX_QW0_NATLEN_SHIFT
;
1295 network_hdr_len
= skb_network_header_len(skb
);
1296 this_ip_hdr
= ip_hdr(skb
);
1297 this_ipv6_hdr
= ipv6_hdr(skb
);
1298 this_tcp_hdrlen
= tcp_hdrlen(skb
);
1301 /* Enable IP checksum offloads */
1302 if (tx_flags
& I40E_TX_FLAGS_IPV4
) {
1303 l4_hdr
= this_ip_hdr
->protocol
;
1304 /* the stack computes the IP header already, the only time we
1305 * need the hardware to recompute it is in the case of TSO.
1307 if (tx_flags
& I40E_TX_FLAGS_TSO
) {
1308 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM
;
1309 this_ip_hdr
->check
= 0;
1311 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV4
;
1313 /* Now set the td_offset for IP header length */
1314 *td_offset
= (network_hdr_len
>> 2) <<
1315 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1316 } else if (tx_flags
& I40E_TX_FLAGS_IPV6
) {
1317 l4_hdr
= this_ipv6_hdr
->nexthdr
;
1318 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV6
;
1319 /* Now set the td_offset for IP header length */
1320 *td_offset
= (network_hdr_len
>> 2) <<
1321 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1323 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1324 *td_offset
|= (skb_network_offset(skb
) >> 1) <<
1325 I40E_TX_DESC_LENGTH_MACLEN_SHIFT
;
1327 /* Enable L4 checksum offloads */
1330 /* enable checksum offloads */
1331 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_TCP
;
1332 *td_offset
|= (this_tcp_hdrlen
>> 2) <<
1333 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1336 /* enable SCTP checksum offload */
1337 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_SCTP
;
1338 *td_offset
|= (sizeof(struct sctphdr
) >> 2) <<
1339 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1342 /* enable UDP checksum offload */
1343 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_UDP
;
1344 *td_offset
|= (sizeof(struct udphdr
) >> 2) <<
1345 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1353 * i40e_create_tx_ctx Build the Tx context descriptor
1354 * @tx_ring: ring to create the descriptor on
1355 * @cd_type_cmd_tso_mss: Quad Word 1
1356 * @cd_tunneling: Quad Word 0 - bits 0-31
1357 * @cd_l2tag2: Quad Word 0 - bits 32-63
1359 static void i40e_create_tx_ctx(struct i40e_ring
*tx_ring
,
1360 const u64 cd_type_cmd_tso_mss
,
1361 const u32 cd_tunneling
, const u32 cd_l2tag2
)
1363 struct i40e_tx_context_desc
*context_desc
;
1364 int i
= tx_ring
->next_to_use
;
1366 if ((cd_type_cmd_tso_mss
== I40E_TX_DESC_DTYPE_CONTEXT
) &&
1367 !cd_tunneling
&& !cd_l2tag2
)
1370 /* grab the next descriptor */
1371 context_desc
= I40E_TX_CTXTDESC(tx_ring
, i
);
1374 tx_ring
->next_to_use
= (i
< tx_ring
->count
) ? i
: 0;
1376 /* cpu_to_le32 and assign to struct fields */
1377 context_desc
->tunneling_params
= cpu_to_le32(cd_tunneling
);
1378 context_desc
->l2tag2
= cpu_to_le16(cd_l2tag2
);
1379 context_desc
->rsvd
= cpu_to_le16(0);
1380 context_desc
->type_cmd_tso_mss
= cpu_to_le64(cd_type_cmd_tso_mss
);
1384 * i40e_tx_map - Build the Tx descriptor
1385 * @tx_ring: ring to send buffer on
1387 * @first: first buffer info buffer to use
1388 * @tx_flags: collected send information
1389 * @hdr_len: size of the packet header
1390 * @td_cmd: the command field in the descriptor
1391 * @td_offset: offset for checksum or crc
1393 static void i40e_tx_map(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1394 struct i40e_tx_buffer
*first
, u32 tx_flags
,
1395 const u8 hdr_len
, u32 td_cmd
, u32 td_offset
)
1397 unsigned int data_len
= skb
->data_len
;
1398 unsigned int size
= skb_headlen(skb
);
1399 struct skb_frag_struct
*frag
;
1400 struct i40e_tx_buffer
*tx_bi
;
1401 struct i40e_tx_desc
*tx_desc
;
1402 u16 i
= tx_ring
->next_to_use
;
1407 if (tx_flags
& I40E_TX_FLAGS_HW_VLAN
) {
1408 td_cmd
|= I40E_TX_DESC_CMD_IL2TAG1
;
1409 td_tag
= (tx_flags
& I40E_TX_FLAGS_VLAN_MASK
) >>
1410 I40E_TX_FLAGS_VLAN_SHIFT
;
1413 if (tx_flags
& (I40E_TX_FLAGS_TSO
| I40E_TX_FLAGS_FSO
))
1414 gso_segs
= skb_shinfo(skb
)->gso_segs
;
1418 /* multiply data chunks by size of headers */
1419 first
->bytecount
= skb
->len
- hdr_len
+ (gso_segs
* hdr_len
);
1420 first
->gso_segs
= gso_segs
;
1422 first
->tx_flags
= tx_flags
;
1424 dma
= dma_map_single(tx_ring
->dev
, skb
->data
, size
, DMA_TO_DEVICE
);
1426 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
1429 for (frag
= &skb_shinfo(skb
)->frags
[0];; frag
++) {
1430 if (dma_mapping_error(tx_ring
->dev
, dma
))
1433 /* record length, and DMA address */
1434 dma_unmap_len_set(tx_bi
, len
, size
);
1435 dma_unmap_addr_set(tx_bi
, dma
, dma
);
1437 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1439 while (unlikely(size
> I40E_MAX_DATA_PER_TXD
)) {
1440 tx_desc
->cmd_type_offset_bsz
=
1441 build_ctob(td_cmd
, td_offset
,
1442 I40E_MAX_DATA_PER_TXD
, td_tag
);
1446 if (i
== tx_ring
->count
) {
1447 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1451 dma
+= I40E_MAX_DATA_PER_TXD
;
1452 size
-= I40E_MAX_DATA_PER_TXD
;
1454 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1457 if (likely(!data_len
))
1460 tx_desc
->cmd_type_offset_bsz
= build_ctob(td_cmd
, td_offset
,
1465 if (i
== tx_ring
->count
) {
1466 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1470 size
= skb_frag_size(frag
);
1473 dma
= skb_frag_dma_map(tx_ring
->dev
, frag
, 0, size
,
1476 tx_bi
= &tx_ring
->tx_bi
[i
];
1479 /* Place RS bit on last descriptor of any packet that spans across the
1480 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1482 #define WB_STRIDE 0x3
1483 if (((i
& WB_STRIDE
) != WB_STRIDE
) &&
1484 (first
<= &tx_ring
->tx_bi
[i
]) &&
1485 (first
>= &tx_ring
->tx_bi
[i
& ~WB_STRIDE
])) {
1486 tx_desc
->cmd_type_offset_bsz
=
1487 build_ctob(td_cmd
, td_offset
, size
, td_tag
) |
1488 cpu_to_le64((u64
)I40E_TX_DESC_CMD_EOP
<<
1489 I40E_TXD_QW1_CMD_SHIFT
);
1491 tx_desc
->cmd_type_offset_bsz
=
1492 build_ctob(td_cmd
, td_offset
, size
, td_tag
) |
1493 cpu_to_le64((u64
)I40E_TXD_CMD
<<
1494 I40E_TXD_QW1_CMD_SHIFT
);
1497 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring
->netdev
,
1498 tx_ring
->queue_index
),
1501 /* set the timestamp */
1502 first
->time_stamp
= jiffies
;
1504 /* Force memory writes to complete before letting h/w
1505 * know there are new descriptors to fetch. (Only
1506 * applicable for weak-ordered memory model archs,
1511 /* set next_to_watch value indicating a packet is present */
1512 first
->next_to_watch
= tx_desc
;
1515 if (i
== tx_ring
->count
)
1518 tx_ring
->next_to_use
= i
;
1520 /* notify HW of packet */
1521 writel(i
, tx_ring
->tail
);
1526 dev_info(tx_ring
->dev
, "TX DMA map failed\n");
1528 /* clear dma mappings for failed tx_bi map */
1530 tx_bi
= &tx_ring
->tx_bi
[i
];
1531 i40e_unmap_and_free_tx_resource(tx_ring
, tx_bi
);
1539 tx_ring
->next_to_use
= i
;
1543 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1544 * @tx_ring: the ring to be checked
1545 * @size: the size buffer we want to assure is available
1547 * Returns -EBUSY if a stop is needed, else 0
1549 static inline int __i40e_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1551 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1552 /* Memory barrier before checking head and tail */
1555 /* Check again in a case another CPU has just made room available. */
1556 if (likely(I40E_DESC_UNUSED(tx_ring
) < size
))
1559 /* A reprieve! - use start_queue because it doesn't call schedule */
1560 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1561 ++tx_ring
->tx_stats
.restart_queue
;
1566 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1567 * @tx_ring: the ring to be checked
1568 * @size: the size buffer we want to assure is available
1570 * Returns 0 if stop is not needed
1572 static int i40e_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1574 if (likely(I40E_DESC_UNUSED(tx_ring
) >= size
))
1576 return __i40e_maybe_stop_tx(tx_ring
, size
);
1580 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1582 * @tx_ring: ring to send buffer on
1584 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1585 * there is not enough descriptors available in this ring since we need at least
1588 static int i40e_xmit_descriptor_count(struct sk_buff
*skb
,
1589 struct i40e_ring
*tx_ring
)
1594 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1595 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1596 * + 4 desc gap to avoid the cache line where head is,
1597 * + 1 desc for context descriptor,
1598 * otherwise try next time
1600 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
1601 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
1603 count
+= TXD_USE_COUNT(skb_headlen(skb
));
1604 if (i40e_maybe_stop_tx(tx_ring
, count
+ 4 + 1)) {
1605 tx_ring
->tx_stats
.tx_busy
++;
1612 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1614 * @tx_ring: ring to send buffer on
1616 * Returns NETDEV_TX_OK if sent, else an error code
1618 static netdev_tx_t
i40e_xmit_frame_ring(struct sk_buff
*skb
,
1619 struct i40e_ring
*tx_ring
)
1621 u64 cd_type_cmd_tso_mss
= I40E_TX_DESC_DTYPE_CONTEXT
;
1622 u32 cd_tunneling
= 0, cd_l2tag2
= 0;
1623 struct i40e_tx_buffer
*first
;
1630 if (0 == i40e_xmit_descriptor_count(skb
, tx_ring
))
1631 return NETDEV_TX_BUSY
;
1633 /* prepare the xmit flags */
1634 if (i40e_tx_prepare_vlan_flags(skb
, tx_ring
, &tx_flags
))
1637 /* obtain protocol of skb */
1638 protocol
= vlan_get_protocol(skb
);
1640 /* record the location of the first descriptor for this packet */
1641 first
= &tx_ring
->tx_bi
[tx_ring
->next_to_use
];
1643 /* setup IPv4/IPv6 offloads */
1644 if (protocol
== htons(ETH_P_IP
))
1645 tx_flags
|= I40E_TX_FLAGS_IPV4
;
1646 else if (protocol
== htons(ETH_P_IPV6
))
1647 tx_flags
|= I40E_TX_FLAGS_IPV6
;
1649 tso
= i40e_tso(tx_ring
, skb
, tx_flags
, protocol
, &hdr_len
,
1650 &cd_type_cmd_tso_mss
, &cd_tunneling
);
1655 tx_flags
|= I40E_TX_FLAGS_TSO
;
1657 skb_tx_timestamp(skb
);
1659 /* always enable CRC insertion offload */
1660 td_cmd
|= I40E_TX_DESC_CMD_ICRC
;
1662 /* Always offload the checksum, since it's in the data descriptor */
1663 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1664 tx_flags
|= I40E_TX_FLAGS_CSUM
;
1666 i40e_tx_enable_csum(skb
, tx_flags
, &td_cmd
, &td_offset
,
1667 tx_ring
, &cd_tunneling
);
1670 i40e_create_tx_ctx(tx_ring
, cd_type_cmd_tso_mss
,
1671 cd_tunneling
, cd_l2tag2
);
1673 i40e_tx_map(tx_ring
, skb
, first
, tx_flags
, hdr_len
,
1676 i40e_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
1678 return NETDEV_TX_OK
;
1681 dev_kfree_skb_any(skb
);
1682 return NETDEV_TX_OK
;
1686 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1688 * @netdev: network interface device structure
1690 * Returns NETDEV_TX_OK if sent, else an error code
1692 netdev_tx_t
i40evf_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
1694 struct i40evf_adapter
*adapter
= netdev_priv(netdev
);
1695 struct i40e_ring
*tx_ring
= adapter
->tx_rings
[skb
->queue_mapping
];
1697 /* hardware can't handle really short frames, hardware padding works
1700 if (unlikely(skb
->len
< I40E_MIN_TX_LEN
)) {
1701 if (skb_pad(skb
, I40E_MIN_TX_LEN
- skb
->len
))
1702 return NETDEV_TX_OK
;
1703 skb
->len
= I40E_MIN_TX_LEN
;
1704 skb_set_tail_pointer(skb
, I40E_MIN_TX_LEN
);
1707 return i40e_xmit_frame_ring(skb
, tx_ring
);