1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
31 #include "i40e_prototype.h"
33 static inline __le64
build_ctob(u32 td_cmd
, u32 td_offset
, unsigned int size
,
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA
|
37 ((u64
)td_cmd
<< I40E_TXD_QW1_CMD_SHIFT
) |
38 ((u64
)td_offset
<< I40E_TXD_QW1_OFFSET_SHIFT
) |
39 ((u64
)size
<< I40E_TXD_QW1_TX_BUF_SZ_SHIFT
) |
40 ((u64
)td_tag
<< I40E_TXD_QW1_L2TAG1_SHIFT
));
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring
*ring
,
51 struct i40e_tx_buffer
*tx_buffer
)
54 dev_kfree_skb_any(tx_buffer
->skb
);
55 if (dma_unmap_len(tx_buffer
, len
))
56 dma_unmap_single(ring
->dev
,
57 dma_unmap_addr(tx_buffer
, dma
),
58 dma_unmap_len(tx_buffer
, len
),
60 } else if (dma_unmap_len(tx_buffer
, len
)) {
61 dma_unmap_page(ring
->dev
,
62 dma_unmap_addr(tx_buffer
, dma
),
63 dma_unmap_len(tx_buffer
, len
),
67 if (tx_buffer
->tx_flags
& I40E_TX_FLAGS_FD_SB
)
68 kfree(tx_buffer
->raw_buf
);
70 tx_buffer
->next_to_watch
= NULL
;
71 tx_buffer
->skb
= NULL
;
72 dma_unmap_len_set(tx_buffer
, len
, 0);
73 /* tx_buffer must be completely set up in the transmit path */
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
80 void i40evf_clean_tx_ring(struct i40e_ring
*tx_ring
)
82 unsigned long bi_size
;
85 /* ring already cleared, nothing to do */
89 /* Free all the Tx ring sk_buffs */
90 for (i
= 0; i
< tx_ring
->count
; i
++)
91 i40e_unmap_and_free_tx_resource(tx_ring
, &tx_ring
->tx_bi
[i
]);
93 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
94 memset(tx_ring
->tx_bi
, 0, bi_size
);
96 /* Zero out the descriptor ring */
97 memset(tx_ring
->desc
, 0, tx_ring
->size
);
99 tx_ring
->next_to_use
= 0;
100 tx_ring
->next_to_clean
= 0;
102 if (!tx_ring
->netdev
)
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring
->netdev
,
107 tx_ring
->queue_index
));
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
114 * Free all transmit software resources
116 void i40evf_free_tx_resources(struct i40e_ring
*tx_ring
)
118 i40evf_clean_tx_ring(tx_ring
);
119 kfree(tx_ring
->tx_bi
);
120 tx_ring
->tx_bi
= NULL
;
123 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
124 tx_ring
->desc
, tx_ring
->dma
);
125 tx_ring
->desc
= NULL
;
130 * i40evf_get_tx_pending - how many Tx descriptors not processed
131 * @tx_ring: the ring of descriptors
133 * Since there is no access to the ring head register
134 * in XL710, we need to use our local copies
136 u32
i40evf_get_tx_pending(struct i40e_ring
*ring
)
140 head
= i40e_get_head(ring
);
141 tail
= readl(ring
->tail
);
144 return (head
< tail
) ?
145 tail
- head
: (tail
+ ring
->count
- head
);
150 #define WB_STRIDE 0x3
153 * i40e_clean_tx_irq - Reclaim resources after transmit completes
154 * @tx_ring: tx ring to clean
155 * @budget: how many cleans we're allowed
157 * Returns true if there's any budget left (e.g. the clean is finished)
159 static bool i40e_clean_tx_irq(struct i40e_ring
*tx_ring
, int budget
)
161 u16 i
= tx_ring
->next_to_clean
;
162 struct i40e_tx_buffer
*tx_buf
;
163 struct i40e_tx_desc
*tx_head
;
164 struct i40e_tx_desc
*tx_desc
;
165 unsigned int total_packets
= 0;
166 unsigned int total_bytes
= 0;
168 tx_buf
= &tx_ring
->tx_bi
[i
];
169 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
172 tx_head
= I40E_TX_DESC(tx_ring
, i40e_get_head(tx_ring
));
175 struct i40e_tx_desc
*eop_desc
= tx_buf
->next_to_watch
;
177 /* if next_to_watch is not set then there is no work pending */
181 /* prevent any other reads prior to eop_desc */
182 read_barrier_depends();
184 /* we have caught up to head, no work left to do */
185 if (tx_head
== tx_desc
)
188 /* clear next_to_watch to prevent false hangs */
189 tx_buf
->next_to_watch
= NULL
;
191 /* update the statistics for this packet */
192 total_bytes
+= tx_buf
->bytecount
;
193 total_packets
+= tx_buf
->gso_segs
;
196 dev_kfree_skb_any(tx_buf
->skb
);
198 /* unmap skb header data */
199 dma_unmap_single(tx_ring
->dev
,
200 dma_unmap_addr(tx_buf
, dma
),
201 dma_unmap_len(tx_buf
, len
),
204 /* clear tx_buffer data */
206 dma_unmap_len_set(tx_buf
, len
, 0);
208 /* unmap remaining buffers */
209 while (tx_desc
!= eop_desc
) {
216 tx_buf
= tx_ring
->tx_bi
;
217 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
220 /* unmap any remaining paged data */
221 if (dma_unmap_len(tx_buf
, len
)) {
222 dma_unmap_page(tx_ring
->dev
,
223 dma_unmap_addr(tx_buf
, dma
),
224 dma_unmap_len(tx_buf
, len
),
226 dma_unmap_len_set(tx_buf
, len
, 0);
230 /* move us one more past the eop_desc for start of next pkt */
236 tx_buf
= tx_ring
->tx_bi
;
237 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
242 /* update budget accounting */
244 } while (likely(budget
));
247 tx_ring
->next_to_clean
= i
;
248 u64_stats_update_begin(&tx_ring
->syncp
);
249 tx_ring
->stats
.bytes
+= total_bytes
;
250 tx_ring
->stats
.packets
+= total_packets
;
251 u64_stats_update_end(&tx_ring
->syncp
);
252 tx_ring
->q_vector
->tx
.total_bytes
+= total_bytes
;
253 tx_ring
->q_vector
->tx
.total_packets
+= total_packets
;
255 if (tx_ring
->flags
& I40E_TXR_FLAGS_WB_ON_ITR
) {
257 /* check to see if there are < 4 descriptors
258 * waiting to be written back, then kick the hardware to force
259 * them to be written back in case we stay in NAPI.
260 * In this mode on X722 we do not enable Interrupt.
262 j
= i40evf_get_tx_pending(tx_ring
);
265 ((j
/ (WB_STRIDE
+ 1)) == 0) && (j
> 0) &&
266 !test_bit(__I40E_DOWN
, &tx_ring
->vsi
->state
) &&
267 (I40E_DESC_UNUSED(tx_ring
) != tx_ring
->count
))
268 tx_ring
->arm_wb
= true;
271 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring
->netdev
,
272 tx_ring
->queue_index
),
273 total_packets
, total_bytes
);
275 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
276 if (unlikely(total_packets
&& netif_carrier_ok(tx_ring
->netdev
) &&
277 (I40E_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
278 /* Make sure that anybody stopping the queue after this
279 * sees the new next_to_clean.
282 if (__netif_subqueue_stopped(tx_ring
->netdev
,
283 tx_ring
->queue_index
) &&
284 !test_bit(__I40E_DOWN
, &tx_ring
->vsi
->state
)) {
285 netif_wake_subqueue(tx_ring
->netdev
,
286 tx_ring
->queue_index
);
287 ++tx_ring
->tx_stats
.restart_queue
;
295 * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
296 * @vsi: the VSI we care about
297 * @q_vector: the vector on which to force writeback
300 static void i40evf_force_wb(struct i40e_vsi
*vsi
, struct i40e_q_vector
*q_vector
)
302 u16 flags
= q_vector
->tx
.ring
[0].flags
;
304 if (flags
& I40E_TXR_FLAGS_WB_ON_ITR
) {
307 if (q_vector
->arm_wb_state
)
310 val
= I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK
|
311 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK
; /* set noitr */
314 I40E_VFINT_DYN_CTLN1(q_vector
->v_idx
+
315 vsi
->base_vector
- 1),
317 q_vector
->arm_wb_state
= true;
319 u32 val
= I40E_VFINT_DYN_CTLN1_INTENA_MASK
|
320 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK
| /* set noitr */
321 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK
|
322 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
;
323 /* allow 00 to be written to the index */
326 I40E_VFINT_DYN_CTLN1(q_vector
->v_idx
+
327 vsi
->base_vector
- 1), val
);
332 * i40e_set_new_dynamic_itr - Find new ITR level
333 * @rc: structure containing ring performance data
335 * Returns true if ITR changed, false if not
337 * Stores a new ITR value based on packets and byte counts during
338 * the last interrupt. The advantage of per interrupt computation
339 * is faster updates and more accurate ITR for the current traffic
340 * pattern. Constants in this function were computed based on
341 * theoretical maximum wire speed and thresholds were set based on
342 * testing data as well as attempting to minimize response time
343 * while increasing bulk throughput.
345 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container
*rc
)
347 enum i40e_latency_range new_latency_range
= rc
->latency_range
;
348 struct i40e_q_vector
*qv
= rc
->ring
->q_vector
;
349 u32 new_itr
= rc
->itr
;
353 if (rc
->total_packets
== 0 || !rc
->itr
)
356 /* simple throttlerate management
357 * 0-10MB/s lowest (50000 ints/s)
358 * 10-20MB/s low (20000 ints/s)
359 * 20-1249MB/s bulk (18000 ints/s)
360 * > 40000 Rx packets per second (8000 ints/s)
362 * The math works out because the divisor is in 10^(-6) which
363 * turns the bytes/us input value into MB/s values, but
364 * make sure to use usecs, as the register values written
365 * are in 2 usec increments in the ITR registers, and make sure
366 * to use the smoothed values that the countdown timer gives us.
368 usecs
= (rc
->itr
<< 1) * ITR_COUNTDOWN_START
;
369 bytes_per_int
= rc
->total_bytes
/ usecs
;
371 switch (new_latency_range
) {
372 case I40E_LOWEST_LATENCY
:
373 if (bytes_per_int
> 10)
374 new_latency_range
= I40E_LOW_LATENCY
;
376 case I40E_LOW_LATENCY
:
377 if (bytes_per_int
> 20)
378 new_latency_range
= I40E_BULK_LATENCY
;
379 else if (bytes_per_int
<= 10)
380 new_latency_range
= I40E_LOWEST_LATENCY
;
382 case I40E_BULK_LATENCY
:
383 case I40E_ULTRA_LATENCY
:
385 if (bytes_per_int
<= 20)
386 new_latency_range
= I40E_LOW_LATENCY
;
390 /* this is to adjust RX more aggressively when streaming small
391 * packets. The value of 40000 was picked as it is just beyond
392 * what the hardware can receive per second if in low latency
395 #define RX_ULTRA_PACKET_RATE 40000
397 if ((((rc
->total_packets
* 1000000) / usecs
) > RX_ULTRA_PACKET_RATE
) &&
399 new_latency_range
= I40E_ULTRA_LATENCY
;
401 rc
->latency_range
= new_latency_range
;
403 switch (new_latency_range
) {
404 case I40E_LOWEST_LATENCY
:
405 new_itr
= I40E_ITR_50K
;
407 case I40E_LOW_LATENCY
:
408 new_itr
= I40E_ITR_20K
;
410 case I40E_BULK_LATENCY
:
411 new_itr
= I40E_ITR_18K
;
413 case I40E_ULTRA_LATENCY
:
414 new_itr
= I40E_ITR_8K
;
421 rc
->total_packets
= 0;
423 if (new_itr
!= rc
->itr
) {
432 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
433 * @tx_ring: the tx ring to set up
435 * Return 0 on success, negative on error
437 int i40evf_setup_tx_descriptors(struct i40e_ring
*tx_ring
)
439 struct device
*dev
= tx_ring
->dev
;
445 /* warn if we are about to overwrite the pointer */
446 WARN_ON(tx_ring
->tx_bi
);
447 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
448 tx_ring
->tx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
452 /* round up to nearest 4K */
453 tx_ring
->size
= tx_ring
->count
* sizeof(struct i40e_tx_desc
);
454 /* add u32 for head writeback, align after this takes care of
455 * guaranteeing this is at least one cache line in size
457 tx_ring
->size
+= sizeof(u32
);
458 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
459 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
460 &tx_ring
->dma
, GFP_KERNEL
);
461 if (!tx_ring
->desc
) {
462 dev_info(dev
, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
467 tx_ring
->next_to_use
= 0;
468 tx_ring
->next_to_clean
= 0;
472 kfree(tx_ring
->tx_bi
);
473 tx_ring
->tx_bi
= NULL
;
478 * i40evf_clean_rx_ring - Free Rx buffers
479 * @rx_ring: ring to be cleaned
481 void i40evf_clean_rx_ring(struct i40e_ring
*rx_ring
)
483 struct device
*dev
= rx_ring
->dev
;
484 struct i40e_rx_buffer
*rx_bi
;
485 unsigned long bi_size
;
488 /* ring already cleared, nothing to do */
492 if (ring_is_ps_enabled(rx_ring
)) {
493 int bufsz
= ALIGN(rx_ring
->rx_hdr_len
, 256) * rx_ring
->count
;
495 rx_bi
= &rx_ring
->rx_bi
[0];
496 if (rx_bi
->hdr_buf
) {
497 dma_free_coherent(dev
,
501 for (i
= 0; i
< rx_ring
->count
; i
++) {
502 rx_bi
= &rx_ring
->rx_bi
[i
];
504 rx_bi
->hdr_buf
= NULL
;
508 /* Free all the Rx ring sk_buffs */
509 for (i
= 0; i
< rx_ring
->count
; i
++) {
510 rx_bi
= &rx_ring
->rx_bi
[i
];
512 dma_unmap_single(dev
,
519 dev_kfree_skb(rx_bi
->skb
);
523 if (rx_bi
->page_dma
) {
530 __free_page(rx_bi
->page
);
532 rx_bi
->page_offset
= 0;
536 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
537 memset(rx_ring
->rx_bi
, 0, bi_size
);
539 /* Zero out the descriptor ring */
540 memset(rx_ring
->desc
, 0, rx_ring
->size
);
542 rx_ring
->next_to_clean
= 0;
543 rx_ring
->next_to_use
= 0;
547 * i40evf_free_rx_resources - Free Rx resources
548 * @rx_ring: ring to clean the resources from
550 * Free all receive software resources
552 void i40evf_free_rx_resources(struct i40e_ring
*rx_ring
)
554 i40evf_clean_rx_ring(rx_ring
);
555 kfree(rx_ring
->rx_bi
);
556 rx_ring
->rx_bi
= NULL
;
559 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
560 rx_ring
->desc
, rx_ring
->dma
);
561 rx_ring
->desc
= NULL
;
566 * i40evf_alloc_rx_headers - allocate rx header buffers
567 * @rx_ring: ring to alloc buffers
569 * Allocate rx header buffers for the entire ring. As these are static,
570 * this is only called when setting up a new ring.
572 void i40evf_alloc_rx_headers(struct i40e_ring
*rx_ring
)
574 struct device
*dev
= rx_ring
->dev
;
575 struct i40e_rx_buffer
*rx_bi
;
581 if (rx_ring
->rx_bi
[0].hdr_buf
)
583 /* Make sure the buffers don't cross cache line boundaries. */
584 buf_size
= ALIGN(rx_ring
->rx_hdr_len
, 256);
585 buffer
= dma_alloc_coherent(dev
, buf_size
* rx_ring
->count
,
589 for (i
= 0; i
< rx_ring
->count
; i
++) {
590 rx_bi
= &rx_ring
->rx_bi
[i
];
591 rx_bi
->dma
= dma
+ (i
* buf_size
);
592 rx_bi
->hdr_buf
= buffer
+ (i
* buf_size
);
597 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
598 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
600 * Returns 0 on success, negative on failure
602 int i40evf_setup_rx_descriptors(struct i40e_ring
*rx_ring
)
604 struct device
*dev
= rx_ring
->dev
;
607 /* warn if we are about to overwrite the pointer */
608 WARN_ON(rx_ring
->rx_bi
);
609 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
610 rx_ring
->rx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
614 u64_stats_init(&rx_ring
->syncp
);
616 /* Round up to nearest 4K */
617 rx_ring
->size
= ring_is_16byte_desc_enabled(rx_ring
)
618 ? rx_ring
->count
* sizeof(union i40e_16byte_rx_desc
)
619 : rx_ring
->count
* sizeof(union i40e_32byte_rx_desc
);
620 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
621 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
622 &rx_ring
->dma
, GFP_KERNEL
);
624 if (!rx_ring
->desc
) {
625 dev_info(dev
, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
630 rx_ring
->next_to_clean
= 0;
631 rx_ring
->next_to_use
= 0;
635 kfree(rx_ring
->rx_bi
);
636 rx_ring
->rx_bi
= NULL
;
641 * i40e_release_rx_desc - Store the new tail and head values
642 * @rx_ring: ring to bump
643 * @val: new head index
645 static inline void i40e_release_rx_desc(struct i40e_ring
*rx_ring
, u32 val
)
647 rx_ring
->next_to_use
= val
;
648 /* Force memory writes to complete before letting h/w
649 * know there are new descriptors to fetch. (Only
650 * applicable for weak-ordered memory model archs,
654 writel(val
, rx_ring
->tail
);
658 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
659 * @rx_ring: ring to place buffers on
660 * @cleaned_count: number of buffers to replace
662 void i40evf_alloc_rx_buffers_ps(struct i40e_ring
*rx_ring
, u16 cleaned_count
)
664 u16 i
= rx_ring
->next_to_use
;
665 union i40e_rx_desc
*rx_desc
;
666 struct i40e_rx_buffer
*bi
;
668 /* do nothing if no valid netdev defined */
669 if (!rx_ring
->netdev
|| !cleaned_count
)
672 while (cleaned_count
--) {
673 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
674 bi
= &rx_ring
->rx_bi
[i
];
676 if (bi
->skb
) /* desc is in use */
679 bi
->page
= alloc_page(GFP_ATOMIC
);
681 rx_ring
->rx_stats
.alloc_page_failed
++;
687 /* use a half page if we're re-using */
688 bi
->page_offset
^= PAGE_SIZE
/ 2;
689 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
694 if (dma_mapping_error(rx_ring
->dev
,
696 rx_ring
->rx_stats
.alloc_page_failed
++;
702 dma_sync_single_range_for_device(rx_ring
->dev
,
703 rx_ring
->rx_bi
[0].dma
,
704 i
* rx_ring
->rx_hdr_len
,
707 /* Refresh the desc even if buffer_addrs didn't change
708 * because each write-back erases this info.
710 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
711 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
713 if (i
== rx_ring
->count
)
718 if (rx_ring
->next_to_use
!= i
)
719 i40e_release_rx_desc(rx_ring
, i
);
723 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
724 * @rx_ring: ring to place buffers on
725 * @cleaned_count: number of buffers to replace
727 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring
*rx_ring
, u16 cleaned_count
)
729 u16 i
= rx_ring
->next_to_use
;
730 union i40e_rx_desc
*rx_desc
;
731 struct i40e_rx_buffer
*bi
;
734 /* do nothing if no valid netdev defined */
735 if (!rx_ring
->netdev
|| !cleaned_count
)
738 while (cleaned_count
--) {
739 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
740 bi
= &rx_ring
->rx_bi
[i
];
744 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
745 rx_ring
->rx_buf_len
);
747 rx_ring
->rx_stats
.alloc_buff_failed
++;
750 /* initialize queue mapping */
751 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
756 bi
->dma
= dma_map_single(rx_ring
->dev
,
760 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
761 rx_ring
->rx_stats
.alloc_buff_failed
++;
767 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
768 rx_desc
->read
.hdr_addr
= 0;
770 if (i
== rx_ring
->count
)
775 if (rx_ring
->next_to_use
!= i
)
776 i40e_release_rx_desc(rx_ring
, i
);
780 * i40e_receive_skb - Send a completed packet up the stack
781 * @rx_ring: rx ring in play
782 * @skb: packet to send up
783 * @vlan_tag: vlan tag for packet
785 static void i40e_receive_skb(struct i40e_ring
*rx_ring
,
786 struct sk_buff
*skb
, u16 vlan_tag
)
788 struct i40e_q_vector
*q_vector
= rx_ring
->q_vector
;
790 if (vlan_tag
& VLAN_VID_MASK
)
791 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlan_tag
);
793 napi_gro_receive(&q_vector
->napi
, skb
);
797 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
798 * @vsi: the VSI we care about
799 * @skb: skb currently being received and modified
800 * @rx_status: status value of last descriptor in packet
801 * @rx_error: error value of last descriptor in packet
802 * @rx_ptype: ptype value of last descriptor in packet
804 static inline void i40e_rx_checksum(struct i40e_vsi
*vsi
,
810 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(rx_ptype
);
811 bool ipv4
= false, ipv6
= false;
812 bool ipv4_tunnel
, ipv6_tunnel
;
817 ipv4_tunnel
= (rx_ptype
>= I40E_RX_PTYPE_GRENAT4_MAC_PAY3
) &&
818 (rx_ptype
<= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4
);
819 ipv6_tunnel
= (rx_ptype
>= I40E_RX_PTYPE_GRENAT6_MAC_PAY3
) &&
820 (rx_ptype
<= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4
);
822 skb
->ip_summed
= CHECKSUM_NONE
;
824 /* Rx csum enabled and ip headers found? */
825 if (!(vsi
->netdev
->features
& NETIF_F_RXCSUM
))
828 /* did the hardware decode the packet and checksum? */
829 if (!(rx_status
& BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT
)))
832 /* both known and outer_ip must be set for the below code to work */
833 if (!(decoded
.known
&& decoded
.outer_ip
))
836 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
837 decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV4
)
839 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
840 decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV6
)
844 (rx_error
& (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT
) |
845 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT
))))
848 /* likely incorrect csum if alternate IP extension headers found */
850 rx_status
& BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT
))
851 /* don't increment checksum err here, non-fatal err */
854 /* there was some L4 error, count error and punt packet to the stack */
855 if (rx_error
& BIT(I40E_RX_DESC_ERROR_L4E_SHIFT
))
858 /* handle packets that were not able to be checksummed due
859 * to arrival speed, in this case the stack can compute
862 if (rx_error
& BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT
))
865 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
866 * it in the driver, hardware does not do it for us.
867 * Since L3L4P bit was set we assume a valid IHL value (>=5)
868 * so the total length of IPv4 header is IHL*4 bytes
869 * The UDP_0 bit *may* bet set if the *inner* header is UDP
872 skb
->transport_header
= skb
->mac_header
+
873 sizeof(struct ethhdr
) +
874 (ip_hdr(skb
)->ihl
* 4);
876 /* Add 4 bytes for VLAN tagged packets */
877 skb
->transport_header
+= (skb
->protocol
== htons(ETH_P_8021Q
) ||
878 skb
->protocol
== htons(ETH_P_8021AD
))
881 if ((ip_hdr(skb
)->protocol
== IPPROTO_UDP
) &&
882 (udp_hdr(skb
)->check
!= 0)) {
883 rx_udp_csum
= udp_csum(skb
);
885 csum
= csum_tcpudp_magic(iph
->saddr
, iph
->daddr
,
887 skb_transport_offset(skb
)),
888 IPPROTO_UDP
, rx_udp_csum
);
890 if (udp_hdr(skb
)->check
!= csum
)
893 } /* else its GRE and so no outer UDP header */
896 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
897 skb
->csum_level
= ipv4_tunnel
|| ipv6_tunnel
;
902 vsi
->back
->hw_csum_rx_error
++;
906 * i40e_ptype_to_htype - get a hash type
907 * @ptype: the ptype value from the descriptor
909 * Returns a hash type to be used by skb_set_hash
911 static inline enum pkt_hash_types
i40e_ptype_to_htype(u8 ptype
)
913 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(ptype
);
916 return PKT_HASH_TYPE_NONE
;
918 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
919 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4
)
920 return PKT_HASH_TYPE_L4
;
921 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
922 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3
)
923 return PKT_HASH_TYPE_L3
;
925 return PKT_HASH_TYPE_L2
;
929 * i40e_rx_hash - set the hash value in the skb
930 * @ring: descriptor ring
931 * @rx_desc: specific descriptor
933 static inline void i40e_rx_hash(struct i40e_ring
*ring
,
934 union i40e_rx_desc
*rx_desc
,
939 const __le64 rss_mask
=
940 cpu_to_le64((u64
)I40E_RX_DESC_FLTSTAT_RSS_HASH
<<
941 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT
);
943 if (ring
->netdev
->features
& NETIF_F_RXHASH
)
946 if ((rx_desc
->wb
.qword1
.status_error_len
& rss_mask
) == rss_mask
) {
947 hash
= le32_to_cpu(rx_desc
->wb
.qword0
.hi_dword
.rss
);
948 skb_set_hash(skb
, hash
, i40e_ptype_to_htype(rx_ptype
));
953 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
954 * @rx_ring: rx ring to clean
955 * @budget: how many cleans we're allowed
957 * Returns true if there's any budget left (e.g. the clean is finished)
959 static int i40e_clean_rx_irq_ps(struct i40e_ring
*rx_ring
, int budget
)
961 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
962 u16 rx_packet_len
, rx_header_len
, rx_sph
, rx_hbo
;
963 u16 cleaned_count
= I40E_DESC_UNUSED(rx_ring
);
964 const int current_node
= numa_mem_id();
965 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
966 u16 i
= rx_ring
->next_to_clean
;
967 union i40e_rx_desc
*rx_desc
;
968 u32 rx_error
, rx_status
;
973 struct i40e_rx_buffer
*rx_bi
;
976 /* return some buffers to hardware, one at a time is too slow */
977 if (cleaned_count
>= I40E_RX_BUFFER_WRITE
) {
978 i40evf_alloc_rx_buffers_ps(rx_ring
, cleaned_count
);
982 i
= rx_ring
->next_to_clean
;
983 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
984 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
985 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
986 I40E_RXD_QW1_STATUS_SHIFT
;
988 if (!(rx_status
& BIT(I40E_RX_DESC_STATUS_DD_SHIFT
)))
991 /* This memory barrier is needed to keep us from reading
992 * any other fields out of the rx_desc until we know the
996 rx_bi
= &rx_ring
->rx_bi
[i
];
999 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1000 rx_ring
->rx_hdr_len
);
1002 rx_ring
->rx_stats
.alloc_buff_failed
++;
1006 /* initialize queue mapping */
1007 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1008 /* we are reusing so sync this buffer for CPU use */
1009 dma_sync_single_range_for_cpu(rx_ring
->dev
,
1010 rx_ring
->rx_bi
[0].dma
,
1011 i
* rx_ring
->rx_hdr_len
,
1012 rx_ring
->rx_hdr_len
,
1015 rx_packet_len
= (qword
& I40E_RXD_QW1_LENGTH_PBUF_MASK
) >>
1016 I40E_RXD_QW1_LENGTH_PBUF_SHIFT
;
1017 rx_header_len
= (qword
& I40E_RXD_QW1_LENGTH_HBUF_MASK
) >>
1018 I40E_RXD_QW1_LENGTH_HBUF_SHIFT
;
1019 rx_sph
= (qword
& I40E_RXD_QW1_LENGTH_SPH_MASK
) >>
1020 I40E_RXD_QW1_LENGTH_SPH_SHIFT
;
1022 rx_error
= (qword
& I40E_RXD_QW1_ERROR_MASK
) >>
1023 I40E_RXD_QW1_ERROR_SHIFT
;
1024 rx_hbo
= rx_error
& BIT(I40E_RX_DESC_ERROR_HBO_SHIFT
);
1025 rx_error
&= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT
);
1027 rx_ptype
= (qword
& I40E_RXD_QW1_PTYPE_MASK
) >>
1028 I40E_RXD_QW1_PTYPE_SHIFT
;
1029 prefetch(rx_bi
->page
);
1032 if (rx_hbo
|| rx_sph
) {
1036 len
= I40E_RX_HDR_SIZE
;
1038 len
= rx_header_len
;
1039 memcpy(__skb_put(skb
, len
), rx_bi
->hdr_buf
, len
);
1040 } else if (skb
->len
== 0) {
1043 len
= (rx_packet_len
> skb_headlen(skb
) ?
1044 skb_headlen(skb
) : rx_packet_len
);
1045 memcpy(__skb_put(skb
, len
),
1046 rx_bi
->page
+ rx_bi
->page_offset
,
1048 rx_bi
->page_offset
+= len
;
1049 rx_packet_len
-= len
;
1052 /* Get the rest of the data if this was a header split */
1053 if (rx_packet_len
) {
1054 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1059 skb
->len
+= rx_packet_len
;
1060 skb
->data_len
+= rx_packet_len
;
1061 skb
->truesize
+= rx_packet_len
;
1063 if ((page_count(rx_bi
->page
) == 1) &&
1064 (page_to_nid(rx_bi
->page
) == current_node
))
1065 get_page(rx_bi
->page
);
1069 dma_unmap_page(rx_ring
->dev
,
1073 rx_bi
->page_dma
= 0;
1075 I40E_RX_INCREMENT(rx_ring
, i
);
1078 !(rx_status
& BIT(I40E_RX_DESC_STATUS_EOF_SHIFT
)))) {
1079 struct i40e_rx_buffer
*next_buffer
;
1081 next_buffer
= &rx_ring
->rx_bi
[i
];
1082 next_buffer
->skb
= skb
;
1083 rx_ring
->rx_stats
.non_eop_descs
++;
1087 /* ERR_MASK will only have valid bits if EOP set */
1088 if (unlikely(rx_error
& BIT(I40E_RX_DESC_ERROR_RXE_SHIFT
))) {
1089 dev_kfree_skb_any(skb
);
1093 i40e_rx_hash(rx_ring
, rx_desc
, skb
, rx_ptype
);
1095 /* probably a little skewed due to removing CRC */
1096 total_rx_bytes
+= skb
->len
;
1099 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1101 i40e_rx_checksum(vsi
, skb
, rx_status
, rx_error
, rx_ptype
);
1103 vlan_tag
= rx_status
& BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
)
1104 ? le16_to_cpu(rx_desc
->wb
.qword0
.lo_dword
.l2tag1
)
1107 if (!i40e_fcoe_handle_offload(rx_ring
, rx_desc
, skb
)) {
1108 dev_kfree_skb_any(skb
);
1112 i40e_receive_skb(rx_ring
, skb
, vlan_tag
);
1114 rx_desc
->wb
.qword1
.status_error_len
= 0;
1116 } while (likely(total_rx_packets
< budget
));
1118 u64_stats_update_begin(&rx_ring
->syncp
);
1119 rx_ring
->stats
.packets
+= total_rx_packets
;
1120 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1121 u64_stats_update_end(&rx_ring
->syncp
);
1122 rx_ring
->q_vector
->rx
.total_packets
+= total_rx_packets
;
1123 rx_ring
->q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1125 return total_rx_packets
;
1129 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1130 * @rx_ring: rx ring to clean
1131 * @budget: how many cleans we're allowed
1133 * Returns number of packets cleaned
1135 static int i40e_clean_rx_irq_1buf(struct i40e_ring
*rx_ring
, int budget
)
1137 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1138 u16 cleaned_count
= I40E_DESC_UNUSED(rx_ring
);
1139 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
1140 union i40e_rx_desc
*rx_desc
;
1141 u32 rx_error
, rx_status
;
1148 struct i40e_rx_buffer
*rx_bi
;
1149 struct sk_buff
*skb
;
1151 /* return some buffers to hardware, one at a time is too slow */
1152 if (cleaned_count
>= I40E_RX_BUFFER_WRITE
) {
1153 i40evf_alloc_rx_buffers_1buf(rx_ring
, cleaned_count
);
1157 i
= rx_ring
->next_to_clean
;
1158 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
1159 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
1160 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
1161 I40E_RXD_QW1_STATUS_SHIFT
;
1163 if (!(rx_status
& BIT(I40E_RX_DESC_STATUS_DD_SHIFT
)))
1166 /* This memory barrier is needed to keep us from reading
1167 * any other fields out of the rx_desc until we know the
1172 rx_bi
= &rx_ring
->rx_bi
[i
];
1174 prefetch(skb
->data
);
1176 rx_packet_len
= (qword
& I40E_RXD_QW1_LENGTH_PBUF_MASK
) >>
1177 I40E_RXD_QW1_LENGTH_PBUF_SHIFT
;
1179 rx_error
= (qword
& I40E_RXD_QW1_ERROR_MASK
) >>
1180 I40E_RXD_QW1_ERROR_SHIFT
;
1181 rx_error
&= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT
);
1183 rx_ptype
= (qword
& I40E_RXD_QW1_PTYPE_MASK
) >>
1184 I40E_RXD_QW1_PTYPE_SHIFT
;
1188 /* Get the header and possibly the whole packet
1189 * If this is an skb from previous receive dma will be 0
1191 skb_put(skb
, rx_packet_len
);
1192 dma_unmap_single(rx_ring
->dev
, rx_bi
->dma
, rx_ring
->rx_buf_len
,
1196 I40E_RX_INCREMENT(rx_ring
, i
);
1199 !(rx_status
& BIT(I40E_RX_DESC_STATUS_EOF_SHIFT
)))) {
1200 rx_ring
->rx_stats
.non_eop_descs
++;
1204 /* ERR_MASK will only have valid bits if EOP set */
1205 if (unlikely(rx_error
& BIT(I40E_RX_DESC_ERROR_RXE_SHIFT
))) {
1206 dev_kfree_skb_any(skb
);
1210 i40e_rx_hash(rx_ring
, rx_desc
, skb
, rx_ptype
);
1211 /* probably a little skewed due to removing CRC */
1212 total_rx_bytes
+= skb
->len
;
1215 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1217 i40e_rx_checksum(vsi
, skb
, rx_status
, rx_error
, rx_ptype
);
1219 vlan_tag
= rx_status
& BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
)
1220 ? le16_to_cpu(rx_desc
->wb
.qword0
.lo_dword
.l2tag1
)
1222 i40e_receive_skb(rx_ring
, skb
, vlan_tag
);
1224 rx_desc
->wb
.qword1
.status_error_len
= 0;
1225 } while (likely(total_rx_packets
< budget
));
1227 u64_stats_update_begin(&rx_ring
->syncp
);
1228 rx_ring
->stats
.packets
+= total_rx_packets
;
1229 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1230 u64_stats_update_end(&rx_ring
->syncp
);
1231 rx_ring
->q_vector
->rx
.total_packets
+= total_rx_packets
;
1232 rx_ring
->q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1234 return total_rx_packets
;
1237 static u32
i40e_buildreg_itr(const int type
, const u16 itr
)
1241 val
= I40E_VFINT_DYN_CTLN1_INTENA_MASK
|
1242 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK
|
1243 (type
<< I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT
) |
1244 (itr
<< I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT
);
1249 /* a small macro to shorten up some long lines */
1250 #define INTREG I40E_VFINT_DYN_CTLN1
1253 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1254 * @vsi: the VSI we care about
1255 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1258 static inline void i40e_update_enable_itr(struct i40e_vsi
*vsi
,
1259 struct i40e_q_vector
*q_vector
)
1261 struct i40e_hw
*hw
= &vsi
->back
->hw
;
1262 bool rx
= false, tx
= false;
1266 vector
= (q_vector
->v_idx
+ vsi
->base_vector
);
1268 /* avoid dynamic calculation if in countdown mode OR if
1269 * all dynamic is disabled
1271 rxval
= txval
= i40e_buildreg_itr(I40E_ITR_NONE
, 0);
1273 if (q_vector
->itr_countdown
> 0 ||
1274 (!ITR_IS_DYNAMIC(vsi
->rx_itr_setting
) &&
1275 !ITR_IS_DYNAMIC(vsi
->tx_itr_setting
))) {
1279 if (ITR_IS_DYNAMIC(vsi
->rx_itr_setting
)) {
1280 rx
= i40e_set_new_dynamic_itr(&q_vector
->rx
);
1281 rxval
= i40e_buildreg_itr(I40E_RX_ITR
, q_vector
->rx
.itr
);
1284 if (ITR_IS_DYNAMIC(vsi
->tx_itr_setting
)) {
1285 tx
= i40e_set_new_dynamic_itr(&q_vector
->tx
);
1286 txval
= i40e_buildreg_itr(I40E_TX_ITR
, q_vector
->tx
.itr
);
1290 /* get the higher of the two ITR adjustments and
1291 * use the same value for both ITR registers
1292 * when in adaptive mode (Rx and/or Tx)
1294 u16 itr
= max(q_vector
->tx
.itr
, q_vector
->rx
.itr
);
1296 q_vector
->tx
.itr
= q_vector
->rx
.itr
= itr
;
1297 txval
= i40e_buildreg_itr(I40E_TX_ITR
, itr
);
1299 rxval
= i40e_buildreg_itr(I40E_RX_ITR
, itr
);
1303 /* only need to enable the interrupt once, but need
1304 * to possibly update both ITR values
1307 /* set the INTENA_MSK_MASK so that this first write
1308 * won't actually enable the interrupt, instead just
1309 * updating the ITR (it's bit 31 PF and VF)
1312 /* don't check _DOWN because interrupt isn't being enabled */
1313 wr32(hw
, INTREG(vector
- 1), rxval
);
1317 if (!test_bit(__I40E_DOWN
, &vsi
->state
))
1318 wr32(hw
, INTREG(vector
- 1), txval
);
1320 if (q_vector
->itr_countdown
)
1321 q_vector
->itr_countdown
--;
1323 q_vector
->itr_countdown
= ITR_COUNTDOWN_START
;
1327 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1328 * @napi: napi struct with our devices info in it
1329 * @budget: amount of work driver is allowed to do this pass, in packets
1331 * This function will clean all queues associated with a q_vector.
1333 * Returns the amount of work done
1335 int i40evf_napi_poll(struct napi_struct
*napi
, int budget
)
1337 struct i40e_q_vector
*q_vector
=
1338 container_of(napi
, struct i40e_q_vector
, napi
);
1339 struct i40e_vsi
*vsi
= q_vector
->vsi
;
1340 struct i40e_ring
*ring
;
1341 bool clean_complete
= true;
1342 bool arm_wb
= false;
1343 int budget_per_ring
;
1346 if (test_bit(__I40E_DOWN
, &vsi
->state
)) {
1347 napi_complete(napi
);
1351 /* Since the actual Tx work is minimal, we can give the Tx a larger
1352 * budget and be more aggressive about cleaning up the Tx descriptors.
1354 i40e_for_each_ring(ring
, q_vector
->tx
) {
1355 clean_complete
&= i40e_clean_tx_irq(ring
, vsi
->work_limit
);
1356 arm_wb
= arm_wb
|| ring
->arm_wb
;
1357 ring
->arm_wb
= false;
1360 /* Handle case where we are called by netpoll with a budget of 0 */
1364 /* We attempt to distribute budget to each Rx queue fairly, but don't
1365 * allow the budget to go below 1 because that would exit polling early.
1367 budget_per_ring
= max(budget
/q_vector
->num_ringpairs
, 1);
1369 i40e_for_each_ring(ring
, q_vector
->rx
) {
1372 if (ring_is_ps_enabled(ring
))
1373 cleaned
= i40e_clean_rx_irq_ps(ring
, budget_per_ring
);
1375 cleaned
= i40e_clean_rx_irq_1buf(ring
, budget_per_ring
);
1377 work_done
+= cleaned
;
1378 /* if we didn't clean as many as budgeted, we must be done */
1379 clean_complete
&= (budget_per_ring
!= cleaned
);
1382 /* If work not completed, return budget and polling will return */
1383 if (!clean_complete
) {
1386 q_vector
->tx
.ring
[0].tx_stats
.tx_force_wb
++;
1387 i40evf_force_wb(vsi
, q_vector
);
1392 if (vsi
->back
->flags
& I40E_TXR_FLAGS_WB_ON_ITR
)
1393 q_vector
->arm_wb_state
= false;
1395 /* Work is done so exit the polling mode and re-enable the interrupt */
1396 napi_complete_done(napi
, work_done
);
1397 i40e_update_enable_itr(vsi
, q_vector
);
1402 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1404 * @tx_ring: ring to send buffer on
1405 * @flags: the tx flags to be set
1407 * Checks the skb and set up correspondingly several generic transmit flags
1408 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1410 * Returns error code indicate the frame should be dropped upon error and the
1411 * otherwise returns 0 to indicate the flags has been set properly.
1413 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff
*skb
,
1414 struct i40e_ring
*tx_ring
,
1417 __be16 protocol
= skb
->protocol
;
1420 if (protocol
== htons(ETH_P_8021Q
) &&
1421 !(tx_ring
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)) {
1422 /* When HW VLAN acceleration is turned off by the user the
1423 * stack sets the protocol to 8021q so that the driver
1424 * can take any steps required to support the SW only
1425 * VLAN handling. In our case the driver doesn't need
1426 * to take any further steps so just set the protocol
1427 * to the encapsulated ethertype.
1429 skb
->protocol
= vlan_get_protocol(skb
);
1433 /* if we have a HW VLAN tag being added, default to the HW one */
1434 if (skb_vlan_tag_present(skb
)) {
1435 tx_flags
|= skb_vlan_tag_get(skb
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1436 tx_flags
|= I40E_TX_FLAGS_HW_VLAN
;
1437 /* else if it is a SW VLAN, check the next protocol and store the tag */
1438 } else if (protocol
== htons(ETH_P_8021Q
)) {
1439 struct vlan_hdr
*vhdr
, _vhdr
;
1441 vhdr
= skb_header_pointer(skb
, ETH_HLEN
, sizeof(_vhdr
), &_vhdr
);
1445 protocol
= vhdr
->h_vlan_encapsulated_proto
;
1446 tx_flags
|= ntohs(vhdr
->h_vlan_TCI
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1447 tx_flags
|= I40E_TX_FLAGS_SW_VLAN
;
1456 * i40e_tso - set up the tso context descriptor
1457 * @tx_ring: ptr to the ring to send
1458 * @skb: ptr to the skb we're sending
1459 * @hdr_len: ptr to the size of the packet header
1460 * @cd_type_cmd_tso_mss: Quad Word 1
1462 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1464 static int i40e_tso(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1465 u8
*hdr_len
, u64
*cd_type_cmd_tso_mss
)
1467 u32 cd_cmd
, cd_tso_len
, cd_mss
;
1468 struct ipv6hdr
*ipv6h
;
1469 struct tcphdr
*tcph
;
1474 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
)
1477 if (!skb_is_gso(skb
))
1480 err
= skb_cow_head(skb
, 0);
1484 iph
= skb
->encapsulation
? inner_ip_hdr(skb
) : ip_hdr(skb
);
1485 ipv6h
= skb
->encapsulation
? inner_ipv6_hdr(skb
) : ipv6_hdr(skb
);
1487 if (iph
->version
== 4) {
1488 tcph
= skb
->encapsulation
? inner_tcp_hdr(skb
) : tcp_hdr(skb
);
1491 tcph
->check
= ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
,
1493 } else if (ipv6h
->version
== 6) {
1494 tcph
= skb
->encapsulation
? inner_tcp_hdr(skb
) : tcp_hdr(skb
);
1495 ipv6h
->payload_len
= 0;
1496 tcph
->check
= ~csum_ipv6_magic(&ipv6h
->saddr
, &ipv6h
->daddr
,
1500 l4len
= skb
->encapsulation
? inner_tcp_hdrlen(skb
) : tcp_hdrlen(skb
);
1501 *hdr_len
= (skb
->encapsulation
1502 ? (skb_inner_transport_header(skb
) - skb
->data
)
1503 : skb_transport_offset(skb
)) + l4len
;
1505 /* find the field values */
1506 cd_cmd
= I40E_TX_CTX_DESC_TSO
;
1507 cd_tso_len
= skb
->len
- *hdr_len
;
1508 cd_mss
= skb_shinfo(skb
)->gso_size
;
1509 *cd_type_cmd_tso_mss
|= ((u64
)cd_cmd
<< I40E_TXD_CTX_QW1_CMD_SHIFT
) |
1511 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT
) |
1512 ((u64
)cd_mss
<< I40E_TXD_CTX_QW1_MSS_SHIFT
);
1517 * i40e_tx_enable_csum - Enable Tx checksum offloads
1519 * @tx_flags: pointer to Tx flags currently set
1520 * @td_cmd: Tx descriptor command bits to set
1521 * @td_offset: Tx descriptor header offsets to set
1522 * @cd_tunneling: ptr to context desc bits
1524 static void i40e_tx_enable_csum(struct sk_buff
*skb
, u32
*tx_flags
,
1525 u32
*td_cmd
, u32
*td_offset
,
1526 struct i40e_ring
*tx_ring
,
1529 struct ipv6hdr
*this_ipv6_hdr
;
1530 unsigned int this_tcp_hdrlen
;
1531 struct iphdr
*this_ip_hdr
;
1532 u32 network_hdr_len
;
1534 struct udphdr
*oudph
;
1538 if (skb
->encapsulation
) {
1539 switch (ip_hdr(skb
)->protocol
) {
1541 oudph
= udp_hdr(skb
);
1543 l4_tunnel
= I40E_TXD_CTX_UDP_TUNNELING
;
1544 *tx_flags
|= I40E_TX_FLAGS_VXLAN_TUNNEL
;
1549 network_hdr_len
= skb_inner_network_header_len(skb
);
1550 this_ip_hdr
= inner_ip_hdr(skb
);
1551 this_ipv6_hdr
= inner_ipv6_hdr(skb
);
1552 this_tcp_hdrlen
= inner_tcp_hdrlen(skb
);
1554 if (*tx_flags
& I40E_TX_FLAGS_IPV4
) {
1555 if (*tx_flags
& I40E_TX_FLAGS_TSO
) {
1556 *cd_tunneling
|= I40E_TX_CTX_EXT_IP_IPV4
;
1557 ip_hdr(skb
)->check
= 0;
1560 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
;
1562 } else if (*tx_flags
& I40E_TX_FLAGS_IPV6
) {
1563 *cd_tunneling
|= I40E_TX_CTX_EXT_IP_IPV6
;
1564 if (*tx_flags
& I40E_TX_FLAGS_TSO
)
1565 ip_hdr(skb
)->check
= 0;
1568 /* Now set the ctx descriptor fields */
1569 *cd_tunneling
|= (skb_network_header_len(skb
) >> 2) <<
1570 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT
|
1572 ((skb_inner_network_offset(skb
) -
1573 skb_transport_offset(skb
)) >> 1) <<
1574 I40E_TXD_CTX_QW0_NATLEN_SHIFT
;
1575 if (this_ip_hdr
->version
== 6) {
1576 *tx_flags
&= ~I40E_TX_FLAGS_IPV4
;
1577 *tx_flags
|= I40E_TX_FLAGS_IPV6
;
1580 if ((tx_ring
->flags
& I40E_TXR_FLAGS_OUTER_UDP_CSUM
) &&
1581 (l4_tunnel
== I40E_TXD_CTX_UDP_TUNNELING
) &&
1582 (*cd_tunneling
& I40E_TXD_CTX_QW0_EXT_IP_MASK
)) {
1583 oudph
->check
= ~csum_tcpudp_magic(oiph
->saddr
,
1585 (skb
->len
- skb_transport_offset(skb
)),
1587 *cd_tunneling
|= I40E_TXD_CTX_QW0_L4T_CS_MASK
;
1590 network_hdr_len
= skb_network_header_len(skb
);
1591 this_ip_hdr
= ip_hdr(skb
);
1592 this_ipv6_hdr
= ipv6_hdr(skb
);
1593 this_tcp_hdrlen
= tcp_hdrlen(skb
);
1596 /* Enable IP checksum offloads */
1597 if (*tx_flags
& I40E_TX_FLAGS_IPV4
) {
1598 l4_hdr
= this_ip_hdr
->protocol
;
1599 /* the stack computes the IP header already, the only time we
1600 * need the hardware to recompute it is in the case of TSO.
1602 if (*tx_flags
& I40E_TX_FLAGS_TSO
) {
1603 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM
;
1604 this_ip_hdr
->check
= 0;
1606 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV4
;
1608 /* Now set the td_offset for IP header length */
1609 *td_offset
= (network_hdr_len
>> 2) <<
1610 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1611 } else if (*tx_flags
& I40E_TX_FLAGS_IPV6
) {
1612 l4_hdr
= this_ipv6_hdr
->nexthdr
;
1613 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV6
;
1614 /* Now set the td_offset for IP header length */
1615 *td_offset
= (network_hdr_len
>> 2) <<
1616 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1618 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1619 *td_offset
|= (skb_network_offset(skb
) >> 1) <<
1620 I40E_TX_DESC_LENGTH_MACLEN_SHIFT
;
1622 /* Enable L4 checksum offloads */
1625 /* enable checksum offloads */
1626 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_TCP
;
1627 *td_offset
|= (this_tcp_hdrlen
>> 2) <<
1628 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1631 /* enable SCTP checksum offload */
1632 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_SCTP
;
1633 *td_offset
|= (sizeof(struct sctphdr
) >> 2) <<
1634 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1637 /* enable UDP checksum offload */
1638 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_UDP
;
1639 *td_offset
|= (sizeof(struct udphdr
) >> 2) <<
1640 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1648 * i40e_create_tx_ctx Build the Tx context descriptor
1649 * @tx_ring: ring to create the descriptor on
1650 * @cd_type_cmd_tso_mss: Quad Word 1
1651 * @cd_tunneling: Quad Word 0 - bits 0-31
1652 * @cd_l2tag2: Quad Word 0 - bits 32-63
1654 static void i40e_create_tx_ctx(struct i40e_ring
*tx_ring
,
1655 const u64 cd_type_cmd_tso_mss
,
1656 const u32 cd_tunneling
, const u32 cd_l2tag2
)
1658 struct i40e_tx_context_desc
*context_desc
;
1659 int i
= tx_ring
->next_to_use
;
1661 if ((cd_type_cmd_tso_mss
== I40E_TX_DESC_DTYPE_CONTEXT
) &&
1662 !cd_tunneling
&& !cd_l2tag2
)
1665 /* grab the next descriptor */
1666 context_desc
= I40E_TX_CTXTDESC(tx_ring
, i
);
1669 tx_ring
->next_to_use
= (i
< tx_ring
->count
) ? i
: 0;
1671 /* cpu_to_le32 and assign to struct fields */
1672 context_desc
->tunneling_params
= cpu_to_le32(cd_tunneling
);
1673 context_desc
->l2tag2
= cpu_to_le16(cd_l2tag2
);
1674 context_desc
->rsvd
= cpu_to_le16(0);
1675 context_desc
->type_cmd_tso_mss
= cpu_to_le64(cd_type_cmd_tso_mss
);
1679 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1681 * @tx_flags: collected send information
1683 * Note: Our HW can't scatter-gather more than 8 fragments to build
1684 * a packet on the wire and so we need to figure out the cases where we
1685 * need to linearize the skb.
1687 static bool i40e_chk_linearize(struct sk_buff
*skb
, u32 tx_flags
)
1689 struct skb_frag_struct
*frag
;
1690 bool linearize
= false;
1691 unsigned int size
= 0;
1695 num_frags
= skb_shinfo(skb
)->nr_frags
;
1696 gso_segs
= skb_shinfo(skb
)->gso_segs
;
1698 if (tx_flags
& (I40E_TX_FLAGS_TSO
| I40E_TX_FLAGS_FSO
)) {
1701 if (num_frags
< (I40E_MAX_BUFFER_TXD
))
1702 goto linearize_chk_done
;
1703 /* try the simple math, if we have too many frags per segment */
1704 if (DIV_ROUND_UP((num_frags
+ gso_segs
), gso_segs
) >
1705 I40E_MAX_BUFFER_TXD
) {
1707 goto linearize_chk_done
;
1709 frag
= &skb_shinfo(skb
)->frags
[0];
1710 /* we might still have more fragments per segment */
1712 size
+= skb_frag_size(frag
);
1714 if ((size
>= skb_shinfo(skb
)->gso_size
) &&
1715 (j
< I40E_MAX_BUFFER_TXD
)) {
1716 size
= (size
% skb_shinfo(skb
)->gso_size
);
1719 if (j
== I40E_MAX_BUFFER_TXD
) {
1724 } while (num_frags
);
1726 if (num_frags
>= I40E_MAX_BUFFER_TXD
)
1735 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1736 * @tx_ring: the ring to be checked
1737 * @size: the size buffer we want to assure is available
1739 * Returns -EBUSY if a stop is needed, else 0
1741 static inline int __i40evf_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1743 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1744 /* Memory barrier before checking head and tail */
1747 /* Check again in a case another CPU has just made room available. */
1748 if (likely(I40E_DESC_UNUSED(tx_ring
) < size
))
1751 /* A reprieve! - use start_queue because it doesn't call schedule */
1752 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1753 ++tx_ring
->tx_stats
.restart_queue
;
1758 * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1759 * @tx_ring: the ring to be checked
1760 * @size: the size buffer we want to assure is available
1762 * Returns 0 if stop is not needed
1764 static inline int i40evf_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1766 if (likely(I40E_DESC_UNUSED(tx_ring
) >= size
))
1768 return __i40evf_maybe_stop_tx(tx_ring
, size
);
1772 * i40evf_tx_map - Build the Tx descriptor
1773 * @tx_ring: ring to send buffer on
1775 * @first: first buffer info buffer to use
1776 * @tx_flags: collected send information
1777 * @hdr_len: size of the packet header
1778 * @td_cmd: the command field in the descriptor
1779 * @td_offset: offset for checksum or crc
1781 static inline void i40evf_tx_map(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1782 struct i40e_tx_buffer
*first
, u32 tx_flags
,
1783 const u8 hdr_len
, u32 td_cmd
, u32 td_offset
)
1785 unsigned int data_len
= skb
->data_len
;
1786 unsigned int size
= skb_headlen(skb
);
1787 struct skb_frag_struct
*frag
;
1788 struct i40e_tx_buffer
*tx_bi
;
1789 struct i40e_tx_desc
*tx_desc
;
1790 u16 i
= tx_ring
->next_to_use
;
1795 bool tail_bump
= true;
1798 if (tx_flags
& I40E_TX_FLAGS_HW_VLAN
) {
1799 td_cmd
|= I40E_TX_DESC_CMD_IL2TAG1
;
1800 td_tag
= (tx_flags
& I40E_TX_FLAGS_VLAN_MASK
) >>
1801 I40E_TX_FLAGS_VLAN_SHIFT
;
1804 if (tx_flags
& (I40E_TX_FLAGS_TSO
| I40E_TX_FLAGS_FSO
))
1805 gso_segs
= skb_shinfo(skb
)->gso_segs
;
1809 /* multiply data chunks by size of headers */
1810 first
->bytecount
= skb
->len
- hdr_len
+ (gso_segs
* hdr_len
);
1811 first
->gso_segs
= gso_segs
;
1813 first
->tx_flags
= tx_flags
;
1815 dma
= dma_map_single(tx_ring
->dev
, skb
->data
, size
, DMA_TO_DEVICE
);
1817 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
1820 for (frag
= &skb_shinfo(skb
)->frags
[0];; frag
++) {
1821 if (dma_mapping_error(tx_ring
->dev
, dma
))
1824 /* record length, and DMA address */
1825 dma_unmap_len_set(tx_bi
, len
, size
);
1826 dma_unmap_addr_set(tx_bi
, dma
, dma
);
1828 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1830 while (unlikely(size
> I40E_MAX_DATA_PER_TXD
)) {
1831 tx_desc
->cmd_type_offset_bsz
=
1832 build_ctob(td_cmd
, td_offset
,
1833 I40E_MAX_DATA_PER_TXD
, td_tag
);
1839 if (i
== tx_ring
->count
) {
1840 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1844 dma
+= I40E_MAX_DATA_PER_TXD
;
1845 size
-= I40E_MAX_DATA_PER_TXD
;
1847 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1850 if (likely(!data_len
))
1853 tx_desc
->cmd_type_offset_bsz
= build_ctob(td_cmd
, td_offset
,
1860 if (i
== tx_ring
->count
) {
1861 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1865 size
= skb_frag_size(frag
);
1868 dma
= skb_frag_dma_map(tx_ring
->dev
, frag
, 0, size
,
1871 tx_bi
= &tx_ring
->tx_bi
[i
];
1874 /* set next_to_watch value indicating a packet is present */
1875 first
->next_to_watch
= tx_desc
;
1878 if (i
== tx_ring
->count
)
1881 tx_ring
->next_to_use
= i
;
1883 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring
->netdev
,
1884 tx_ring
->queue_index
),
1886 i40evf_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
1888 /* Algorithm to optimize tail and RS bit setting:
1889 * if xmit_more is supported
1890 * if xmit_more is true
1891 * do not update tail and do not mark RS bit.
1892 * if xmit_more is false and last xmit_more was false
1893 * if every packet spanned less than 4 desc
1894 * then set RS bit on 4th packet and update tail
1897 * update tail and set RS bit on every packet.
1898 * if xmit_more is false and last_xmit_more was true
1899 * update tail and set RS bit.
1901 * Optimization: wmb to be issued only in case of tail update.
1902 * Also optimize the Descriptor WB path for RS bit with the same
1905 * Note: If there are less than 4 packets
1906 * pending and interrupts were disabled the service task will
1907 * trigger a force WB.
1909 if (skb
->xmit_more
&&
1910 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring
->netdev
,
1911 tx_ring
->queue_index
))) {
1912 tx_ring
->flags
|= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET
;
1914 } else if (!skb
->xmit_more
&&
1915 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring
->netdev
,
1916 tx_ring
->queue_index
)) &&
1917 (!(tx_ring
->flags
& I40E_TXR_FLAGS_LAST_XMIT_MORE_SET
)) &&
1918 (tx_ring
->packet_stride
< WB_STRIDE
) &&
1919 (desc_count
< WB_STRIDE
)) {
1920 tx_ring
->packet_stride
++;
1922 tx_ring
->packet_stride
= 0;
1923 tx_ring
->flags
&= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET
;
1927 tx_ring
->packet_stride
= 0;
1929 tx_desc
->cmd_type_offset_bsz
=
1930 build_ctob(td_cmd
, td_offset
, size
, td_tag
) |
1931 cpu_to_le64((u64
)(do_rs
? I40E_TXD_CMD
:
1932 I40E_TX_DESC_CMD_EOP
) <<
1933 I40E_TXD_QW1_CMD_SHIFT
);
1935 /* notify HW of packet */
1937 prefetchw(tx_desc
+ 1);
1940 /* Force memory writes to complete before letting h/w
1941 * know there are new descriptors to fetch. (Only
1942 * applicable for weak-ordered memory model archs,
1946 writel(i
, tx_ring
->tail
);
1952 dev_info(tx_ring
->dev
, "TX DMA map failed\n");
1954 /* clear dma mappings for failed tx_bi map */
1956 tx_bi
= &tx_ring
->tx_bi
[i
];
1957 i40e_unmap_and_free_tx_resource(tx_ring
, tx_bi
);
1965 tx_ring
->next_to_use
= i
;
1969 * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1971 * @tx_ring: ring to send buffer on
1973 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1974 * there is not enough descriptors available in this ring since we need at least
1977 static inline int i40evf_xmit_descriptor_count(struct sk_buff
*skb
,
1978 struct i40e_ring
*tx_ring
)
1983 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1984 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1985 * + 4 desc gap to avoid the cache line where head is,
1986 * + 1 desc for context descriptor,
1987 * otherwise try next time
1989 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
1990 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
1992 count
+= TXD_USE_COUNT(skb_headlen(skb
));
1993 if (i40evf_maybe_stop_tx(tx_ring
, count
+ 4 + 1)) {
1994 tx_ring
->tx_stats
.tx_busy
++;
2001 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2003 * @tx_ring: ring to send buffer on
2005 * Returns NETDEV_TX_OK if sent, else an error code
2007 static netdev_tx_t
i40e_xmit_frame_ring(struct sk_buff
*skb
,
2008 struct i40e_ring
*tx_ring
)
2010 u64 cd_type_cmd_tso_mss
= I40E_TX_DESC_DTYPE_CONTEXT
;
2011 u32 cd_tunneling
= 0, cd_l2tag2
= 0;
2012 struct i40e_tx_buffer
*first
;
2020 /* prefetch the data, we'll need it later */
2021 prefetch(skb
->data
);
2023 if (0 == i40evf_xmit_descriptor_count(skb
, tx_ring
))
2024 return NETDEV_TX_BUSY
;
2026 /* prepare the xmit flags */
2027 if (i40evf_tx_prepare_vlan_flags(skb
, tx_ring
, &tx_flags
))
2030 /* obtain protocol of skb */
2031 protocol
= vlan_get_protocol(skb
);
2033 /* record the location of the first descriptor for this packet */
2034 first
= &tx_ring
->tx_bi
[tx_ring
->next_to_use
];
2036 /* setup IPv4/IPv6 offloads */
2037 if (protocol
== htons(ETH_P_IP
))
2038 tx_flags
|= I40E_TX_FLAGS_IPV4
;
2039 else if (protocol
== htons(ETH_P_IPV6
))
2040 tx_flags
|= I40E_TX_FLAGS_IPV6
;
2042 tso
= i40e_tso(tx_ring
, skb
, &hdr_len
, &cd_type_cmd_tso_mss
);
2047 tx_flags
|= I40E_TX_FLAGS_TSO
;
2049 if (i40e_chk_linearize(skb
, tx_flags
)) {
2050 if (skb_linearize(skb
))
2052 tx_ring
->tx_stats
.tx_linearize
++;
2054 skb_tx_timestamp(skb
);
2056 /* always enable CRC insertion offload */
2057 td_cmd
|= I40E_TX_DESC_CMD_ICRC
;
2059 /* Always offload the checksum, since it's in the data descriptor */
2060 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2061 tx_flags
|= I40E_TX_FLAGS_CSUM
;
2063 i40e_tx_enable_csum(skb
, &tx_flags
, &td_cmd
, &td_offset
,
2064 tx_ring
, &cd_tunneling
);
2067 i40e_create_tx_ctx(tx_ring
, cd_type_cmd_tso_mss
,
2068 cd_tunneling
, cd_l2tag2
);
2070 i40evf_tx_map(tx_ring
, skb
, first
, tx_flags
, hdr_len
,
2073 return NETDEV_TX_OK
;
2076 dev_kfree_skb_any(skb
);
2077 return NETDEV_TX_OK
;
2081 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2083 * @netdev: network interface device structure
2085 * Returns NETDEV_TX_OK if sent, else an error code
2087 netdev_tx_t
i40evf_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
2089 struct i40evf_adapter
*adapter
= netdev_priv(netdev
);
2090 struct i40e_ring
*tx_ring
= &adapter
->tx_rings
[skb
->queue_mapping
];
2092 /* hardware can't handle really short frames, hardware padding works
2095 if (unlikely(skb
->len
< I40E_MIN_TX_LEN
)) {
2096 if (skb_pad(skb
, I40E_MIN_TX_LEN
- skb
->len
))
2097 return NETDEV_TX_OK
;
2098 skb
->len
= I40E_MIN_TX_LEN
;
2099 skb_set_tail_pointer(skb
, I40E_MIN_TX_LEN
);
2102 return i40e_xmit_frame_ring(skb
, tx_ring
);