1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
31 #include "i40e_prototype.h"
33 static inline __le64
build_ctob(u32 td_cmd
, u32 td_offset
, unsigned int size
,
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA
|
37 ((u64
)td_cmd
<< I40E_TXD_QW1_CMD_SHIFT
) |
38 ((u64
)td_offset
<< I40E_TXD_QW1_OFFSET_SHIFT
) |
39 ((u64
)size
<< I40E_TXD_QW1_TX_BUF_SZ_SHIFT
) |
40 ((u64
)td_tag
<< I40E_TXD_QW1_L2TAG1_SHIFT
));
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring
*ring
,
51 struct i40e_tx_buffer
*tx_buffer
)
54 dev_kfree_skb_any(tx_buffer
->skb
);
55 if (dma_unmap_len(tx_buffer
, len
))
56 dma_unmap_single(ring
->dev
,
57 dma_unmap_addr(tx_buffer
, dma
),
58 dma_unmap_len(tx_buffer
, len
),
60 } else if (dma_unmap_len(tx_buffer
, len
)) {
61 dma_unmap_page(ring
->dev
,
62 dma_unmap_addr(tx_buffer
, dma
),
63 dma_unmap_len(tx_buffer
, len
),
67 if (tx_buffer
->tx_flags
& I40E_TX_FLAGS_FD_SB
)
68 kfree(tx_buffer
->raw_buf
);
70 tx_buffer
->next_to_watch
= NULL
;
71 tx_buffer
->skb
= NULL
;
72 dma_unmap_len_set(tx_buffer
, len
, 0);
73 /* tx_buffer must be completely set up in the transmit path */
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
80 void i40evf_clean_tx_ring(struct i40e_ring
*tx_ring
)
82 unsigned long bi_size
;
85 /* ring already cleared, nothing to do */
89 /* Free all the Tx ring sk_buffs */
90 for (i
= 0; i
< tx_ring
->count
; i
++)
91 i40e_unmap_and_free_tx_resource(tx_ring
, &tx_ring
->tx_bi
[i
]);
93 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
94 memset(tx_ring
->tx_bi
, 0, bi_size
);
96 /* Zero out the descriptor ring */
97 memset(tx_ring
->desc
, 0, tx_ring
->size
);
99 tx_ring
->next_to_use
= 0;
100 tx_ring
->next_to_clean
= 0;
102 if (!tx_ring
->netdev
)
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring
->netdev
,
107 tx_ring
->queue_index
));
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
114 * Free all transmit software resources
116 void i40evf_free_tx_resources(struct i40e_ring
*tx_ring
)
118 i40evf_clean_tx_ring(tx_ring
);
119 kfree(tx_ring
->tx_bi
);
120 tx_ring
->tx_bi
= NULL
;
123 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
124 tx_ring
->desc
, tx_ring
->dma
);
125 tx_ring
->desc
= NULL
;
130 * i40evf_get_tx_pending - how many Tx descriptors not processed
131 * @tx_ring: the ring of descriptors
132 * @in_sw: is tx_pending being checked in SW or HW
134 * Since there is no access to the ring head register
135 * in XL710, we need to use our local copies
137 u32
i40evf_get_tx_pending(struct i40e_ring
*ring
, bool in_sw
)
142 head
= i40e_get_head(ring
);
144 head
= ring
->next_to_clean
;
145 tail
= readl(ring
->tail
);
148 return (head
< tail
) ?
149 tail
- head
: (tail
+ ring
->count
- head
);
154 #define WB_STRIDE 0x3
157 * i40e_clean_tx_irq - Reclaim resources after transmit completes
158 * @vsi: the VSI we care about
159 * @tx_ring: Tx ring to clean
160 * @napi_budget: Used to determine if we are in netpoll
162 * Returns true if there's any budget left (e.g. the clean is finished)
164 static bool i40e_clean_tx_irq(struct i40e_vsi
*vsi
,
165 struct i40e_ring
*tx_ring
, int napi_budget
)
167 u16 i
= tx_ring
->next_to_clean
;
168 struct i40e_tx_buffer
*tx_buf
;
169 struct i40e_tx_desc
*tx_head
;
170 struct i40e_tx_desc
*tx_desc
;
171 unsigned int total_bytes
= 0, total_packets
= 0;
172 unsigned int budget
= vsi
->work_limit
;
174 tx_buf
= &tx_ring
->tx_bi
[i
];
175 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
178 tx_head
= I40E_TX_DESC(tx_ring
, i40e_get_head(tx_ring
));
181 struct i40e_tx_desc
*eop_desc
= tx_buf
->next_to_watch
;
183 /* if next_to_watch is not set then there is no work pending */
187 /* prevent any other reads prior to eop_desc */
188 read_barrier_depends();
190 /* we have caught up to head, no work left to do */
191 if (tx_head
== tx_desc
)
194 /* clear next_to_watch to prevent false hangs */
195 tx_buf
->next_to_watch
= NULL
;
197 /* update the statistics for this packet */
198 total_bytes
+= tx_buf
->bytecount
;
199 total_packets
+= tx_buf
->gso_segs
;
202 napi_consume_skb(tx_buf
->skb
, napi_budget
);
204 /* unmap skb header data */
205 dma_unmap_single(tx_ring
->dev
,
206 dma_unmap_addr(tx_buf
, dma
),
207 dma_unmap_len(tx_buf
, len
),
210 /* clear tx_buffer data */
212 dma_unmap_len_set(tx_buf
, len
, 0);
214 /* unmap remaining buffers */
215 while (tx_desc
!= eop_desc
) {
222 tx_buf
= tx_ring
->tx_bi
;
223 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
226 /* unmap any remaining paged data */
227 if (dma_unmap_len(tx_buf
, len
)) {
228 dma_unmap_page(tx_ring
->dev
,
229 dma_unmap_addr(tx_buf
, dma
),
230 dma_unmap_len(tx_buf
, len
),
232 dma_unmap_len_set(tx_buf
, len
, 0);
236 /* move us one more past the eop_desc for start of next pkt */
242 tx_buf
= tx_ring
->tx_bi
;
243 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
248 /* update budget accounting */
250 } while (likely(budget
));
253 tx_ring
->next_to_clean
= i
;
254 u64_stats_update_begin(&tx_ring
->syncp
);
255 tx_ring
->stats
.bytes
+= total_bytes
;
256 tx_ring
->stats
.packets
+= total_packets
;
257 u64_stats_update_end(&tx_ring
->syncp
);
258 tx_ring
->q_vector
->tx
.total_bytes
+= total_bytes
;
259 tx_ring
->q_vector
->tx
.total_packets
+= total_packets
;
261 if (tx_ring
->flags
& I40E_TXR_FLAGS_WB_ON_ITR
) {
262 /* check to see if there are < 4 descriptors
263 * waiting to be written back, then kick the hardware to force
264 * them to be written back in case we stay in NAPI.
265 * In this mode on X722 we do not enable Interrupt.
267 unsigned int j
= i40evf_get_tx_pending(tx_ring
, false);
270 ((j
/ (WB_STRIDE
+ 1)) == 0) && (j
> 0) &&
271 !test_bit(__I40E_DOWN
, &vsi
->state
) &&
272 (I40E_DESC_UNUSED(tx_ring
) != tx_ring
->count
))
273 tx_ring
->arm_wb
= true;
276 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring
->netdev
,
277 tx_ring
->queue_index
),
278 total_packets
, total_bytes
);
280 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
281 if (unlikely(total_packets
&& netif_carrier_ok(tx_ring
->netdev
) &&
282 (I40E_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
283 /* Make sure that anybody stopping the queue after this
284 * sees the new next_to_clean.
287 if (__netif_subqueue_stopped(tx_ring
->netdev
,
288 tx_ring
->queue_index
) &&
289 !test_bit(__I40E_DOWN
, &vsi
->state
)) {
290 netif_wake_subqueue(tx_ring
->netdev
,
291 tx_ring
->queue_index
);
292 ++tx_ring
->tx_stats
.restart_queue
;
300 * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
301 * @vsi: the VSI we care about
302 * @q_vector: the vector on which to enable writeback
305 static void i40e_enable_wb_on_itr(struct i40e_vsi
*vsi
,
306 struct i40e_q_vector
*q_vector
)
308 u16 flags
= q_vector
->tx
.ring
[0].flags
;
311 if (!(flags
& I40E_TXR_FLAGS_WB_ON_ITR
))
314 if (q_vector
->arm_wb_state
)
317 val
= I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK
|
318 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK
; /* set noitr */
321 I40E_VFINT_DYN_CTLN1(q_vector
->v_idx
+
322 vsi
->base_vector
- 1), val
);
323 q_vector
->arm_wb_state
= true;
327 * i40evf_force_wb - Issue SW Interrupt so HW does a wb
328 * @vsi: the VSI we care about
329 * @q_vector: the vector on which to force writeback
332 void i40evf_force_wb(struct i40e_vsi
*vsi
, struct i40e_q_vector
*q_vector
)
334 u32 val
= I40E_VFINT_DYN_CTLN1_INTENA_MASK
|
335 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK
| /* set noitr */
336 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK
|
337 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
338 /* allow 00 to be written to the index */;
341 I40E_VFINT_DYN_CTLN1(q_vector
->v_idx
+ vsi
->base_vector
- 1),
346 * i40e_set_new_dynamic_itr - Find new ITR level
347 * @rc: structure containing ring performance data
349 * Returns true if ITR changed, false if not
351 * Stores a new ITR value based on packets and byte counts during
352 * the last interrupt. The advantage of per interrupt computation
353 * is faster updates and more accurate ITR for the current traffic
354 * pattern. Constants in this function were computed based on
355 * theoretical maximum wire speed and thresholds were set based on
356 * testing data as well as attempting to minimize response time
357 * while increasing bulk throughput.
359 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container
*rc
)
361 enum i40e_latency_range new_latency_range
= rc
->latency_range
;
362 struct i40e_q_vector
*qv
= rc
->ring
->q_vector
;
363 u32 new_itr
= rc
->itr
;
367 if (rc
->total_packets
== 0 || !rc
->itr
)
370 /* simple throttlerate management
371 * 0-10MB/s lowest (50000 ints/s)
372 * 10-20MB/s low (20000 ints/s)
373 * 20-1249MB/s bulk (18000 ints/s)
374 * > 40000 Rx packets per second (8000 ints/s)
376 * The math works out because the divisor is in 10^(-6) which
377 * turns the bytes/us input value into MB/s values, but
378 * make sure to use usecs, as the register values written
379 * are in 2 usec increments in the ITR registers, and make sure
380 * to use the smoothed values that the countdown timer gives us.
382 usecs
= (rc
->itr
<< 1) * ITR_COUNTDOWN_START
;
383 bytes_per_int
= rc
->total_bytes
/ usecs
;
385 switch (new_latency_range
) {
386 case I40E_LOWEST_LATENCY
:
387 if (bytes_per_int
> 10)
388 new_latency_range
= I40E_LOW_LATENCY
;
390 case I40E_LOW_LATENCY
:
391 if (bytes_per_int
> 20)
392 new_latency_range
= I40E_BULK_LATENCY
;
393 else if (bytes_per_int
<= 10)
394 new_latency_range
= I40E_LOWEST_LATENCY
;
396 case I40E_BULK_LATENCY
:
397 case I40E_ULTRA_LATENCY
:
399 if (bytes_per_int
<= 20)
400 new_latency_range
= I40E_LOW_LATENCY
;
404 /* this is to adjust RX more aggressively when streaming small
405 * packets. The value of 40000 was picked as it is just beyond
406 * what the hardware can receive per second if in low latency
409 #define RX_ULTRA_PACKET_RATE 40000
411 if ((((rc
->total_packets
* 1000000) / usecs
) > RX_ULTRA_PACKET_RATE
) &&
413 new_latency_range
= I40E_ULTRA_LATENCY
;
415 rc
->latency_range
= new_latency_range
;
417 switch (new_latency_range
) {
418 case I40E_LOWEST_LATENCY
:
419 new_itr
= I40E_ITR_50K
;
421 case I40E_LOW_LATENCY
:
422 new_itr
= I40E_ITR_20K
;
424 case I40E_BULK_LATENCY
:
425 new_itr
= I40E_ITR_18K
;
427 case I40E_ULTRA_LATENCY
:
428 new_itr
= I40E_ITR_8K
;
435 rc
->total_packets
= 0;
437 if (new_itr
!= rc
->itr
) {
446 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
447 * @tx_ring: the tx ring to set up
449 * Return 0 on success, negative on error
451 int i40evf_setup_tx_descriptors(struct i40e_ring
*tx_ring
)
453 struct device
*dev
= tx_ring
->dev
;
459 /* warn if we are about to overwrite the pointer */
460 WARN_ON(tx_ring
->tx_bi
);
461 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
462 tx_ring
->tx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
466 /* round up to nearest 4K */
467 tx_ring
->size
= tx_ring
->count
* sizeof(struct i40e_tx_desc
);
468 /* add u32 for head writeback, align after this takes care of
469 * guaranteeing this is at least one cache line in size
471 tx_ring
->size
+= sizeof(u32
);
472 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
473 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
474 &tx_ring
->dma
, GFP_KERNEL
);
475 if (!tx_ring
->desc
) {
476 dev_info(dev
, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
481 tx_ring
->next_to_use
= 0;
482 tx_ring
->next_to_clean
= 0;
486 kfree(tx_ring
->tx_bi
);
487 tx_ring
->tx_bi
= NULL
;
492 * i40evf_clean_rx_ring - Free Rx buffers
493 * @rx_ring: ring to be cleaned
495 void i40evf_clean_rx_ring(struct i40e_ring
*rx_ring
)
497 struct device
*dev
= rx_ring
->dev
;
498 unsigned long bi_size
;
501 /* ring already cleared, nothing to do */
505 /* Free all the Rx ring sk_buffs */
506 for (i
= 0; i
< rx_ring
->count
; i
++) {
507 struct i40e_rx_buffer
*rx_bi
= &rx_ring
->rx_bi
[i
];
510 dev_kfree_skb(rx_bi
->skb
);
516 dma_unmap_page(dev
, rx_bi
->dma
, PAGE_SIZE
, DMA_FROM_DEVICE
);
517 __free_pages(rx_bi
->page
, 0);
520 rx_bi
->page_offset
= 0;
523 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
524 memset(rx_ring
->rx_bi
, 0, bi_size
);
526 /* Zero out the descriptor ring */
527 memset(rx_ring
->desc
, 0, rx_ring
->size
);
529 rx_ring
->next_to_alloc
= 0;
530 rx_ring
->next_to_clean
= 0;
531 rx_ring
->next_to_use
= 0;
535 * i40evf_free_rx_resources - Free Rx resources
536 * @rx_ring: ring to clean the resources from
538 * Free all receive software resources
540 void i40evf_free_rx_resources(struct i40e_ring
*rx_ring
)
542 i40evf_clean_rx_ring(rx_ring
);
543 kfree(rx_ring
->rx_bi
);
544 rx_ring
->rx_bi
= NULL
;
547 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
548 rx_ring
->desc
, rx_ring
->dma
);
549 rx_ring
->desc
= NULL
;
554 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
555 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
557 * Returns 0 on success, negative on failure
559 int i40evf_setup_rx_descriptors(struct i40e_ring
*rx_ring
)
561 struct device
*dev
= rx_ring
->dev
;
564 /* warn if we are about to overwrite the pointer */
565 WARN_ON(rx_ring
->rx_bi
);
566 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
567 rx_ring
->rx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
571 u64_stats_init(&rx_ring
->syncp
);
573 /* Round up to nearest 4K */
574 rx_ring
->size
= rx_ring
->count
* sizeof(union i40e_32byte_rx_desc
);
575 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
576 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
577 &rx_ring
->dma
, GFP_KERNEL
);
579 if (!rx_ring
->desc
) {
580 dev_info(dev
, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
585 rx_ring
->next_to_alloc
= 0;
586 rx_ring
->next_to_clean
= 0;
587 rx_ring
->next_to_use
= 0;
591 kfree(rx_ring
->rx_bi
);
592 rx_ring
->rx_bi
= NULL
;
597 * i40e_release_rx_desc - Store the new tail and head values
598 * @rx_ring: ring to bump
599 * @val: new head index
601 static inline void i40e_release_rx_desc(struct i40e_ring
*rx_ring
, u32 val
)
603 rx_ring
->next_to_use
= val
;
605 /* update next to alloc since we have filled the ring */
606 rx_ring
->next_to_alloc
= val
;
608 /* Force memory writes to complete before letting h/w
609 * know there are new descriptors to fetch. (Only
610 * applicable for weak-ordered memory model archs,
614 writel(val
, rx_ring
->tail
);
618 * i40e_alloc_mapped_page - recycle or make a new page
619 * @rx_ring: ring to use
620 * @bi: rx_buffer struct to modify
622 * Returns true if the page was successfully allocated or
625 static bool i40e_alloc_mapped_page(struct i40e_ring
*rx_ring
,
626 struct i40e_rx_buffer
*bi
)
628 struct page
*page
= bi
->page
;
631 /* since we are recycling buffers we should seldom need to alloc */
633 rx_ring
->rx_stats
.page_reuse_count
++;
637 /* alloc new page for storage */
638 page
= dev_alloc_page();
639 if (unlikely(!page
)) {
640 rx_ring
->rx_stats
.alloc_page_failed
++;
644 /* map page for use */
645 dma
= dma_map_page(rx_ring
->dev
, page
, 0, PAGE_SIZE
, DMA_FROM_DEVICE
);
647 /* if mapping failed free memory back to system since
648 * there isn't much point in holding memory we can't use
650 if (dma_mapping_error(rx_ring
->dev
, dma
)) {
651 __free_pages(page
, 0);
652 rx_ring
->rx_stats
.alloc_page_failed
++;
664 * i40e_receive_skb - Send a completed packet up the stack
665 * @rx_ring: rx ring in play
666 * @skb: packet to send up
667 * @vlan_tag: vlan tag for packet
669 static void i40e_receive_skb(struct i40e_ring
*rx_ring
,
670 struct sk_buff
*skb
, u16 vlan_tag
)
672 struct i40e_q_vector
*q_vector
= rx_ring
->q_vector
;
674 if ((rx_ring
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
675 (vlan_tag
& VLAN_VID_MASK
))
676 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlan_tag
);
678 napi_gro_receive(&q_vector
->napi
, skb
);
682 * i40evf_alloc_rx_buffers - Replace used receive buffers
683 * @rx_ring: ring to place buffers on
684 * @cleaned_count: number of buffers to replace
686 * Returns false if all allocations were successful, true if any fail
688 bool i40evf_alloc_rx_buffers(struct i40e_ring
*rx_ring
, u16 cleaned_count
)
690 u16 ntu
= rx_ring
->next_to_use
;
691 union i40e_rx_desc
*rx_desc
;
692 struct i40e_rx_buffer
*bi
;
694 /* do nothing if no valid netdev defined */
695 if (!rx_ring
->netdev
|| !cleaned_count
)
698 rx_desc
= I40E_RX_DESC(rx_ring
, ntu
);
699 bi
= &rx_ring
->rx_bi
[ntu
];
702 if (!i40e_alloc_mapped_page(rx_ring
, bi
))
705 /* Refresh the desc even if buffer_addrs didn't change
706 * because each write-back erases this info.
708 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
+ bi
->page_offset
);
709 rx_desc
->read
.hdr_addr
= 0;
714 if (unlikely(ntu
== rx_ring
->count
)) {
715 rx_desc
= I40E_RX_DESC(rx_ring
, 0);
720 /* clear the status bits for the next_to_use descriptor */
721 rx_desc
->wb
.qword1
.status_error_len
= 0;
724 } while (cleaned_count
);
726 if (rx_ring
->next_to_use
!= ntu
)
727 i40e_release_rx_desc(rx_ring
, ntu
);
732 if (rx_ring
->next_to_use
!= ntu
)
733 i40e_release_rx_desc(rx_ring
, ntu
);
735 /* make sure to come back via polling to try again after
742 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
743 * @vsi: the VSI we care about
744 * @skb: skb currently being received and modified
745 * @rx_desc: the receive descriptor
747 * skb->protocol must be set before this function is called
749 static inline void i40e_rx_checksum(struct i40e_vsi
*vsi
,
751 union i40e_rx_desc
*rx_desc
)
753 struct i40e_rx_ptype_decoded decoded
;
754 u32 rx_error
, rx_status
;
759 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
760 ptype
= (qword
& I40E_RXD_QW1_PTYPE_MASK
) >> I40E_RXD_QW1_PTYPE_SHIFT
;
761 rx_error
= (qword
& I40E_RXD_QW1_ERROR_MASK
) >>
762 I40E_RXD_QW1_ERROR_SHIFT
;
763 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
764 I40E_RXD_QW1_STATUS_SHIFT
;
765 decoded
= decode_rx_desc_ptype(ptype
);
767 skb
->ip_summed
= CHECKSUM_NONE
;
769 skb_checksum_none_assert(skb
);
771 /* Rx csum enabled and ip headers found? */
772 if (!(vsi
->netdev
->features
& NETIF_F_RXCSUM
))
775 /* did the hardware decode the packet and checksum? */
776 if (!(rx_status
& BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT
)))
779 /* both known and outer_ip must be set for the below code to work */
780 if (!(decoded
.known
&& decoded
.outer_ip
))
783 ipv4
= (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
) &&
784 (decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV4
);
785 ipv6
= (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
) &&
786 (decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV6
);
789 (rx_error
& (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT
) |
790 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT
))))
793 /* likely incorrect csum if alternate IP extension headers found */
795 rx_status
& BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT
))
796 /* don't increment checksum err here, non-fatal err */
799 /* there was some L4 error, count error and punt packet to the stack */
800 if (rx_error
& BIT(I40E_RX_DESC_ERROR_L4E_SHIFT
))
803 /* handle packets that were not able to be checksummed due
804 * to arrival speed, in this case the stack can compute
807 if (rx_error
& BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT
))
810 /* If there is an outer header present that might contain a checksum
811 * we need to bump the checksum level by 1 to reflect the fact that
812 * we are indicating we validated the inner checksum.
814 if (decoded
.tunnel_type
>= I40E_RX_PTYPE_TUNNEL_IP_GRENAT
)
817 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
818 switch (decoded
.inner_prot
) {
819 case I40E_RX_PTYPE_INNER_PROT_TCP
:
820 case I40E_RX_PTYPE_INNER_PROT_UDP
:
821 case I40E_RX_PTYPE_INNER_PROT_SCTP
:
822 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
831 vsi
->back
->hw_csum_rx_error
++;
835 * i40e_ptype_to_htype - get a hash type
836 * @ptype: the ptype value from the descriptor
838 * Returns a hash type to be used by skb_set_hash
840 static inline int i40e_ptype_to_htype(u8 ptype
)
842 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(ptype
);
845 return PKT_HASH_TYPE_NONE
;
847 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
848 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4
)
849 return PKT_HASH_TYPE_L4
;
850 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
851 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3
)
852 return PKT_HASH_TYPE_L3
;
854 return PKT_HASH_TYPE_L2
;
858 * i40e_rx_hash - set the hash value in the skb
859 * @ring: descriptor ring
860 * @rx_desc: specific descriptor
862 static inline void i40e_rx_hash(struct i40e_ring
*ring
,
863 union i40e_rx_desc
*rx_desc
,
868 const __le64 rss_mask
=
869 cpu_to_le64((u64
)I40E_RX_DESC_FLTSTAT_RSS_HASH
<<
870 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT
);
872 if (ring
->netdev
->features
& NETIF_F_RXHASH
)
875 if ((rx_desc
->wb
.qword1
.status_error_len
& rss_mask
) == rss_mask
) {
876 hash
= le32_to_cpu(rx_desc
->wb
.qword0
.hi_dword
.rss
);
877 skb_set_hash(skb
, hash
, i40e_ptype_to_htype(rx_ptype
));
882 * i40evf_process_skb_fields - Populate skb header fields from Rx descriptor
883 * @rx_ring: rx descriptor ring packet is being transacted on
884 * @rx_desc: pointer to the EOP Rx descriptor
885 * @skb: pointer to current skb being populated
886 * @rx_ptype: the packet type decoded by hardware
888 * This function checks the ring, descriptor, and packet information in
889 * order to populate the hash, checksum, VLAN, protocol, and
890 * other fields within the skb.
893 void i40evf_process_skb_fields(struct i40e_ring
*rx_ring
,
894 union i40e_rx_desc
*rx_desc
, struct sk_buff
*skb
,
897 i40e_rx_hash(rx_ring
, rx_desc
, skb
, rx_ptype
);
899 /* modifies the skb - consumes the enet header */
900 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
902 i40e_rx_checksum(rx_ring
->vsi
, skb
, rx_desc
);
904 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
908 * i40e_pull_tail - i40e specific version of skb_pull_tail
909 * @rx_ring: rx descriptor ring packet is being transacted on
910 * @skb: pointer to current skb being adjusted
912 * This function is an i40e specific version of __pskb_pull_tail. The
913 * main difference between this version and the original function is that
914 * this function can make several assumptions about the state of things
915 * that allow for significant optimizations versus the standard function.
916 * As a result we can do things like drop a frag and maintain an accurate
917 * truesize for the skb.
919 static void i40e_pull_tail(struct i40e_ring
*rx_ring
, struct sk_buff
*skb
)
921 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[0];
923 unsigned int pull_len
;
925 /* it is valid to use page_address instead of kmap since we are
926 * working with pages allocated out of the lomem pool per
927 * alloc_page(GFP_ATOMIC)
929 va
= skb_frag_address(frag
);
931 /* we need the header to contain the greater of either ETH_HLEN or
932 * 60 bytes if the skb->len is less than 60 for skb_pad.
934 pull_len
= eth_get_headlen(va
, I40E_RX_HDR_SIZE
);
936 /* align pull length to size of long to optimize memcpy performance */
937 skb_copy_to_linear_data(skb
, va
, ALIGN(pull_len
, sizeof(long)));
939 /* update all of the pointers */
940 skb_frag_size_sub(frag
, pull_len
);
941 frag
->page_offset
+= pull_len
;
942 skb
->data_len
-= pull_len
;
943 skb
->tail
+= pull_len
;
947 * i40e_cleanup_headers - Correct empty headers
948 * @rx_ring: rx descriptor ring packet is being transacted on
949 * @skb: pointer to current skb being fixed
951 * Also address the case where we are pulling data in on pages only
952 * and as such no data is present in the skb header.
954 * In addition if skb is not at least 60 bytes we need to pad it so that
955 * it is large enough to qualify as a valid Ethernet frame.
957 * Returns true if an error was encountered and skb was freed.
959 static bool i40e_cleanup_headers(struct i40e_ring
*rx_ring
, struct sk_buff
*skb
)
961 /* place header in linear portion of buffer */
962 if (skb_is_nonlinear(skb
))
963 i40e_pull_tail(rx_ring
, skb
);
965 /* if eth_skb_pad returns an error the skb was freed */
966 if (eth_skb_pad(skb
))
973 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
974 * @rx_ring: rx descriptor ring to store buffers on
975 * @old_buff: donor buffer to have page reused
977 * Synchronizes page for reuse by the adapter
979 static void i40e_reuse_rx_page(struct i40e_ring
*rx_ring
,
980 struct i40e_rx_buffer
*old_buff
)
982 struct i40e_rx_buffer
*new_buff
;
983 u16 nta
= rx_ring
->next_to_alloc
;
985 new_buff
= &rx_ring
->rx_bi
[nta
];
987 /* update, and store next to alloc */
989 rx_ring
->next_to_alloc
= (nta
< rx_ring
->count
) ? nta
: 0;
991 /* transfer page from old buffer to new buffer */
992 *new_buff
= *old_buff
;
996 * i40e_page_is_reserved - check if reuse is possible
997 * @page: page struct to check
999 static inline bool i40e_page_is_reserved(struct page
*page
)
1001 return (page_to_nid(page
) != numa_mem_id()) || page_is_pfmemalloc(page
);
1005 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1006 * @rx_ring: rx descriptor ring to transact packets on
1007 * @rx_buffer: buffer containing page to add
1008 * @rx_desc: descriptor containing length of buffer written by hardware
1009 * @skb: sk_buff to place the data into
1011 * This function will add the data contained in rx_buffer->page to the skb.
1012 * This is done either through a direct copy if the data in the buffer is
1013 * less than the skb header size, otherwise it will just attach the page as
1014 * a frag to the skb.
1016 * The function will then update the page offset if necessary and return
1017 * true if the buffer can be reused by the adapter.
1019 static bool i40e_add_rx_frag(struct i40e_ring
*rx_ring
,
1020 struct i40e_rx_buffer
*rx_buffer
,
1021 union i40e_rx_desc
*rx_desc
,
1022 struct sk_buff
*skb
)
1024 struct page
*page
= rx_buffer
->page
;
1025 u64 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
1026 unsigned int size
= (qword
& I40E_RXD_QW1_LENGTH_PBUF_MASK
) >>
1027 I40E_RXD_QW1_LENGTH_PBUF_SHIFT
;
1028 #if (PAGE_SIZE < 8192)
1029 unsigned int truesize
= I40E_RXBUFFER_2048
;
1031 unsigned int truesize
= ALIGN(size
, L1_CACHE_BYTES
);
1032 unsigned int last_offset
= PAGE_SIZE
- I40E_RXBUFFER_2048
;
1035 /* will the data fit in the skb we allocated? if so, just
1036 * copy it as it is pretty small anyway
1038 if ((size
<= I40E_RX_HDR_SIZE
) && !skb_is_nonlinear(skb
)) {
1039 unsigned char *va
= page_address(page
) + rx_buffer
->page_offset
;
1041 memcpy(__skb_put(skb
, size
), va
, ALIGN(size
, sizeof(long)));
1043 /* page is not reserved, we can reuse buffer as-is */
1044 if (likely(!i40e_page_is_reserved(page
)))
1047 /* this page cannot be reused so discard it */
1048 __free_pages(page
, 0);
1052 skb_add_rx_frag(skb
, skb_shinfo(skb
)->nr_frags
, page
,
1053 rx_buffer
->page_offset
, size
, truesize
);
1055 /* avoid re-using remote pages */
1056 if (unlikely(i40e_page_is_reserved(page
)))
1059 #if (PAGE_SIZE < 8192)
1060 /* if we are only owner of page we can reuse it */
1061 if (unlikely(page_count(page
) != 1))
1064 /* flip page offset to other buffer */
1065 rx_buffer
->page_offset
^= truesize
;
1067 /* move offset up to the next cache line */
1068 rx_buffer
->page_offset
+= truesize
;
1070 if (rx_buffer
->page_offset
> last_offset
)
1074 /* Even if we own the page, we are not allowed to use atomic_set()
1075 * This would break get_page_unless_zero() users.
1077 get_page(rx_buffer
->page
);
1083 * i40evf_fetch_rx_buffer - Allocate skb and populate it
1084 * @rx_ring: rx descriptor ring to transact packets on
1085 * @rx_desc: descriptor containing info written by hardware
1087 * This function allocates an skb on the fly, and populates it with the page
1088 * data from the current receive descriptor, taking care to set up the skb
1089 * correctly, as well as handling calling the page recycle function if
1093 struct sk_buff
*i40evf_fetch_rx_buffer(struct i40e_ring
*rx_ring
,
1094 union i40e_rx_desc
*rx_desc
)
1096 struct i40e_rx_buffer
*rx_buffer
;
1097 struct sk_buff
*skb
;
1100 rx_buffer
= &rx_ring
->rx_bi
[rx_ring
->next_to_clean
];
1101 page
= rx_buffer
->page
;
1104 skb
= rx_buffer
->skb
;
1107 void *page_addr
= page_address(page
) + rx_buffer
->page_offset
;
1109 /* prefetch first cache line of first page */
1110 prefetch(page_addr
);
1111 #if L1_CACHE_BYTES < 128
1112 prefetch(page_addr
+ L1_CACHE_BYTES
);
1115 /* allocate a skb to store the frags */
1116 skb
= __napi_alloc_skb(&rx_ring
->q_vector
->napi
,
1118 GFP_ATOMIC
| __GFP_NOWARN
);
1119 if (unlikely(!skb
)) {
1120 rx_ring
->rx_stats
.alloc_buff_failed
++;
1124 /* we will be copying header into skb->data in
1125 * pskb_may_pull so it is in our interest to prefetch
1126 * it now to avoid a possible cache miss
1128 prefetchw(skb
->data
);
1130 rx_buffer
->skb
= NULL
;
1133 /* we are reusing so sync this buffer for CPU use */
1134 dma_sync_single_range_for_cpu(rx_ring
->dev
,
1136 rx_buffer
->page_offset
,
1140 /* pull page into skb */
1141 if (i40e_add_rx_frag(rx_ring
, rx_buffer
, rx_desc
, skb
)) {
1142 /* hand second half of page back to the ring */
1143 i40e_reuse_rx_page(rx_ring
, rx_buffer
);
1144 rx_ring
->rx_stats
.page_reuse_count
++;
1146 /* we are not reusing the buffer so unmap it */
1147 dma_unmap_page(rx_ring
->dev
, rx_buffer
->dma
, PAGE_SIZE
,
1151 /* clear contents of buffer_info */
1152 rx_buffer
->page
= NULL
;
1158 * i40e_is_non_eop - process handling of non-EOP buffers
1159 * @rx_ring: Rx ring being processed
1160 * @rx_desc: Rx descriptor for current buffer
1161 * @skb: Current socket buffer containing buffer in progress
1163 * This function updates next to clean. If the buffer is an EOP buffer
1164 * this function exits returning false, otherwise it will place the
1165 * sk_buff in the next buffer to be chained and return true indicating
1166 * that this is in fact a non-EOP buffer.
1168 static bool i40e_is_non_eop(struct i40e_ring
*rx_ring
,
1169 union i40e_rx_desc
*rx_desc
,
1170 struct sk_buff
*skb
)
1172 u32 ntc
= rx_ring
->next_to_clean
+ 1;
1174 /* fetch, update, and store next to clean */
1175 ntc
= (ntc
< rx_ring
->count
) ? ntc
: 0;
1176 rx_ring
->next_to_clean
= ntc
;
1178 prefetch(I40E_RX_DESC(rx_ring
, ntc
));
1180 /* if we are the last buffer then there is nothing else to do */
1181 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
1182 if (likely(i40e_test_staterr(rx_desc
, I40E_RXD_EOF
)))
1185 /* place skb in next buffer to be received */
1186 rx_ring
->rx_bi
[ntc
].skb
= skb
;
1187 rx_ring
->rx_stats
.non_eop_descs
++;
1193 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1194 * @rx_ring: rx descriptor ring to transact packets on
1195 * @budget: Total limit on number of packets to process
1197 * This function provides a "bounce buffer" approach to Rx interrupt
1198 * processing. The advantage to this is that on systems that have
1199 * expensive overhead for IOMMU access this provides a means of avoiding
1200 * it by maintaining the mapping of the page to the system.
1202 * Returns amount of work completed
1204 static int i40e_clean_rx_irq(struct i40e_ring
*rx_ring
, int budget
)
1206 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1207 u16 cleaned_count
= I40E_DESC_UNUSED(rx_ring
);
1208 bool failure
= false;
1210 while (likely(total_rx_packets
< budget
)) {
1211 union i40e_rx_desc
*rx_desc
;
1212 struct sk_buff
*skb
;
1218 /* return some buffers to hardware, one at a time is too slow */
1219 if (cleaned_count
>= I40E_RX_BUFFER_WRITE
) {
1220 failure
= failure
||
1221 i40evf_alloc_rx_buffers(rx_ring
, cleaned_count
);
1225 rx_desc
= I40E_RX_DESC(rx_ring
, rx_ring
->next_to_clean
);
1227 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
1228 rx_ptype
= (qword
& I40E_RXD_QW1_PTYPE_MASK
) >>
1229 I40E_RXD_QW1_PTYPE_SHIFT
;
1230 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
1231 I40E_RXD_QW1_STATUS_SHIFT
;
1233 if (!(rx_status
& BIT(I40E_RX_DESC_STATUS_DD_SHIFT
)))
1236 /* status_error_len will always be zero for unused descriptors
1237 * because it's cleared in cleanup, and overlaps with hdr_addr
1238 * which is always zero because packet split isn't used, if the
1239 * hardware wrote DD then it will be non-zero
1241 if (!rx_desc
->wb
.qword1
.status_error_len
)
1244 /* This memory barrier is needed to keep us from reading
1245 * any other fields out of the rx_desc until we know the
1250 skb
= i40evf_fetch_rx_buffer(rx_ring
, rx_desc
);
1256 if (i40e_is_non_eop(rx_ring
, rx_desc
, skb
))
1259 /* ERR_MASK will only have valid bits if EOP set, and
1260 * what we are doing here is actually checking
1261 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1264 if (unlikely(i40e_test_staterr(rx_desc
, BIT(I40E_RXD_QW1_ERROR_SHIFT
)))) {
1265 dev_kfree_skb_any(skb
);
1269 if (i40e_cleanup_headers(rx_ring
, skb
))
1272 /* probably a little skewed due to removing CRC */
1273 total_rx_bytes
+= skb
->len
;
1275 /* populate checksum, VLAN, and protocol */
1276 i40evf_process_skb_fields(rx_ring
, rx_desc
, skb
, rx_ptype
);
1279 vlan_tag
= (qword
& BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
)) ?
1280 le16_to_cpu(rx_desc
->wb
.qword0
.lo_dword
.l2tag1
) : 0;
1282 i40e_receive_skb(rx_ring
, skb
, vlan_tag
);
1284 /* update budget accounting */
1288 u64_stats_update_begin(&rx_ring
->syncp
);
1289 rx_ring
->stats
.packets
+= total_rx_packets
;
1290 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1291 u64_stats_update_end(&rx_ring
->syncp
);
1292 rx_ring
->q_vector
->rx
.total_packets
+= total_rx_packets
;
1293 rx_ring
->q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1295 /* guarantee a trip back through this routine if there was a failure */
1296 return failure
? budget
: total_rx_packets
;
1299 static u32
i40e_buildreg_itr(const int type
, const u16 itr
)
1303 val
= I40E_VFINT_DYN_CTLN1_INTENA_MASK
|
1304 /* Don't clear PBA because that can cause lost interrupts that
1305 * came in while we were cleaning/polling
1307 (type
<< I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT
) |
1308 (itr
<< I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT
);
1313 /* a small macro to shorten up some long lines */
1314 #define INTREG I40E_VFINT_DYN_CTLN1
1317 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1318 * @vsi: the VSI we care about
1319 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1322 static inline void i40e_update_enable_itr(struct i40e_vsi
*vsi
,
1323 struct i40e_q_vector
*q_vector
)
1325 struct i40e_hw
*hw
= &vsi
->back
->hw
;
1326 bool rx
= false, tx
= false;
1330 vector
= (q_vector
->v_idx
+ vsi
->base_vector
);
1332 /* avoid dynamic calculation if in countdown mode OR if
1333 * all dynamic is disabled
1335 rxval
= txval
= i40e_buildreg_itr(I40E_ITR_NONE
, 0);
1337 if (q_vector
->itr_countdown
> 0 ||
1338 (!ITR_IS_DYNAMIC(vsi
->rx_itr_setting
) &&
1339 !ITR_IS_DYNAMIC(vsi
->tx_itr_setting
))) {
1343 if (ITR_IS_DYNAMIC(vsi
->rx_itr_setting
)) {
1344 rx
= i40e_set_new_dynamic_itr(&q_vector
->rx
);
1345 rxval
= i40e_buildreg_itr(I40E_RX_ITR
, q_vector
->rx
.itr
);
1348 if (ITR_IS_DYNAMIC(vsi
->tx_itr_setting
)) {
1349 tx
= i40e_set_new_dynamic_itr(&q_vector
->tx
);
1350 txval
= i40e_buildreg_itr(I40E_TX_ITR
, q_vector
->tx
.itr
);
1354 /* get the higher of the two ITR adjustments and
1355 * use the same value for both ITR registers
1356 * when in adaptive mode (Rx and/or Tx)
1358 u16 itr
= max(q_vector
->tx
.itr
, q_vector
->rx
.itr
);
1360 q_vector
->tx
.itr
= q_vector
->rx
.itr
= itr
;
1361 txval
= i40e_buildreg_itr(I40E_TX_ITR
, itr
);
1363 rxval
= i40e_buildreg_itr(I40E_RX_ITR
, itr
);
1367 /* only need to enable the interrupt once, but need
1368 * to possibly update both ITR values
1371 /* set the INTENA_MSK_MASK so that this first write
1372 * won't actually enable the interrupt, instead just
1373 * updating the ITR (it's bit 31 PF and VF)
1376 /* don't check _DOWN because interrupt isn't being enabled */
1377 wr32(hw
, INTREG(vector
- 1), rxval
);
1381 if (!test_bit(__I40E_DOWN
, &vsi
->state
))
1382 wr32(hw
, INTREG(vector
- 1), txval
);
1384 if (q_vector
->itr_countdown
)
1385 q_vector
->itr_countdown
--;
1387 q_vector
->itr_countdown
= ITR_COUNTDOWN_START
;
1391 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1392 * @napi: napi struct with our devices info in it
1393 * @budget: amount of work driver is allowed to do this pass, in packets
1395 * This function will clean all queues associated with a q_vector.
1397 * Returns the amount of work done
1399 int i40evf_napi_poll(struct napi_struct
*napi
, int budget
)
1401 struct i40e_q_vector
*q_vector
=
1402 container_of(napi
, struct i40e_q_vector
, napi
);
1403 struct i40e_vsi
*vsi
= q_vector
->vsi
;
1404 struct i40e_ring
*ring
;
1405 bool clean_complete
= true;
1406 bool arm_wb
= false;
1407 int budget_per_ring
;
1410 if (test_bit(__I40E_DOWN
, &vsi
->state
)) {
1411 napi_complete(napi
);
1415 /* Since the actual Tx work is minimal, we can give the Tx a larger
1416 * budget and be more aggressive about cleaning up the Tx descriptors.
1418 i40e_for_each_ring(ring
, q_vector
->tx
) {
1419 if (!i40e_clean_tx_irq(vsi
, ring
, budget
)) {
1420 clean_complete
= false;
1423 arm_wb
|= ring
->arm_wb
;
1424 ring
->arm_wb
= false;
1427 /* Handle case where we are called by netpoll with a budget of 0 */
1431 /* We attempt to distribute budget to each Rx queue fairly, but don't
1432 * allow the budget to go below 1 because that would exit polling early.
1434 budget_per_ring
= max(budget
/q_vector
->num_ringpairs
, 1);
1436 i40e_for_each_ring(ring
, q_vector
->rx
) {
1437 int cleaned
= i40e_clean_rx_irq(ring
, budget_per_ring
);
1439 work_done
+= cleaned
;
1440 /* if we clean as many as budgeted, we must not be done */
1441 if (cleaned
>= budget_per_ring
)
1442 clean_complete
= false;
1445 /* If work not completed, return budget and polling will return */
1446 if (!clean_complete
) {
1449 q_vector
->tx
.ring
[0].tx_stats
.tx_force_wb
++;
1450 i40e_enable_wb_on_itr(vsi
, q_vector
);
1455 if (vsi
->back
->flags
& I40E_TXR_FLAGS_WB_ON_ITR
)
1456 q_vector
->arm_wb_state
= false;
1458 /* Work is done so exit the polling mode and re-enable the interrupt */
1459 napi_complete_done(napi
, work_done
);
1460 i40e_update_enable_itr(vsi
, q_vector
);
1465 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1467 * @tx_ring: ring to send buffer on
1468 * @flags: the tx flags to be set
1470 * Checks the skb and set up correspondingly several generic transmit flags
1471 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1473 * Returns error code indicate the frame should be dropped upon error and the
1474 * otherwise returns 0 to indicate the flags has been set properly.
1476 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff
*skb
,
1477 struct i40e_ring
*tx_ring
,
1480 __be16 protocol
= skb
->protocol
;
1483 if (protocol
== htons(ETH_P_8021Q
) &&
1484 !(tx_ring
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)) {
1485 /* When HW VLAN acceleration is turned off by the user the
1486 * stack sets the protocol to 8021q so that the driver
1487 * can take any steps required to support the SW only
1488 * VLAN handling. In our case the driver doesn't need
1489 * to take any further steps so just set the protocol
1490 * to the encapsulated ethertype.
1492 skb
->protocol
= vlan_get_protocol(skb
);
1496 /* if we have a HW VLAN tag being added, default to the HW one */
1497 if (skb_vlan_tag_present(skb
)) {
1498 tx_flags
|= skb_vlan_tag_get(skb
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1499 tx_flags
|= I40E_TX_FLAGS_HW_VLAN
;
1500 /* else if it is a SW VLAN, check the next protocol and store the tag */
1501 } else if (protocol
== htons(ETH_P_8021Q
)) {
1502 struct vlan_hdr
*vhdr
, _vhdr
;
1504 vhdr
= skb_header_pointer(skb
, ETH_HLEN
, sizeof(_vhdr
), &_vhdr
);
1508 protocol
= vhdr
->h_vlan_encapsulated_proto
;
1509 tx_flags
|= ntohs(vhdr
->h_vlan_TCI
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1510 tx_flags
|= I40E_TX_FLAGS_SW_VLAN
;
1519 * i40e_tso - set up the tso context descriptor
1520 * @skb: ptr to the skb we're sending
1521 * @hdr_len: ptr to the size of the packet header
1522 * @cd_type_cmd_tso_mss: Quad Word 1
1524 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1526 static int i40e_tso(struct sk_buff
*skb
, u8
*hdr_len
, u64
*cd_type_cmd_tso_mss
)
1528 u64 cd_cmd
, cd_tso_len
, cd_mss
;
1539 u32 paylen
, l4_offset
;
1542 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
)
1545 if (!skb_is_gso(skb
))
1548 err
= skb_cow_head(skb
, 0);
1552 ip
.hdr
= skb_network_header(skb
);
1553 l4
.hdr
= skb_transport_header(skb
);
1555 /* initialize outer IP header fields */
1556 if (ip
.v4
->version
== 4) {
1560 ip
.v6
->payload_len
= 0;
1563 if (skb_shinfo(skb
)->gso_type
& (SKB_GSO_GRE
|
1567 SKB_GSO_UDP_TUNNEL
|
1568 SKB_GSO_UDP_TUNNEL_CSUM
)) {
1569 if (!(skb_shinfo(skb
)->gso_type
& SKB_GSO_PARTIAL
) &&
1570 (skb_shinfo(skb
)->gso_type
& SKB_GSO_UDP_TUNNEL_CSUM
)) {
1573 /* determine offset of outer transport header */
1574 l4_offset
= l4
.hdr
- skb
->data
;
1576 /* remove payload length from outer checksum */
1577 paylen
= skb
->len
- l4_offset
;
1578 csum_replace_by_diff(&l4
.udp
->check
, htonl(paylen
));
1581 /* reset pointers to inner headers */
1582 ip
.hdr
= skb_inner_network_header(skb
);
1583 l4
.hdr
= skb_inner_transport_header(skb
);
1585 /* initialize inner IP header fields */
1586 if (ip
.v4
->version
== 4) {
1590 ip
.v6
->payload_len
= 0;
1594 /* determine offset of inner transport header */
1595 l4_offset
= l4
.hdr
- skb
->data
;
1597 /* remove payload length from inner checksum */
1598 paylen
= skb
->len
- l4_offset
;
1599 csum_replace_by_diff(&l4
.tcp
->check
, htonl(paylen
));
1601 /* compute length of segmentation header */
1602 *hdr_len
= (l4
.tcp
->doff
* 4) + l4_offset
;
1604 /* find the field values */
1605 cd_cmd
= I40E_TX_CTX_DESC_TSO
;
1606 cd_tso_len
= skb
->len
- *hdr_len
;
1607 cd_mss
= skb_shinfo(skb
)->gso_size
;
1608 *cd_type_cmd_tso_mss
|= (cd_cmd
<< I40E_TXD_CTX_QW1_CMD_SHIFT
) |
1609 (cd_tso_len
<< I40E_TXD_CTX_QW1_TSO_LEN_SHIFT
) |
1610 (cd_mss
<< I40E_TXD_CTX_QW1_MSS_SHIFT
);
1615 * i40e_tx_enable_csum - Enable Tx checksum offloads
1617 * @tx_flags: pointer to Tx flags currently set
1618 * @td_cmd: Tx descriptor command bits to set
1619 * @td_offset: Tx descriptor header offsets to set
1620 * @tx_ring: Tx descriptor ring
1621 * @cd_tunneling: ptr to context desc bits
1623 static int i40e_tx_enable_csum(struct sk_buff
*skb
, u32
*tx_flags
,
1624 u32
*td_cmd
, u32
*td_offset
,
1625 struct i40e_ring
*tx_ring
,
1638 unsigned char *exthdr
;
1639 u32 offset
, cmd
= 0;
1643 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
)
1646 ip
.hdr
= skb_network_header(skb
);
1647 l4
.hdr
= skb_transport_header(skb
);
1649 /* compute outer L2 header size */
1650 offset
= ((ip
.hdr
- skb
->data
) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT
;
1652 if (skb
->encapsulation
) {
1654 /* define outer network header type */
1655 if (*tx_flags
& I40E_TX_FLAGS_IPV4
) {
1656 tunnel
|= (*tx_flags
& I40E_TX_FLAGS_TSO
) ?
1657 I40E_TX_CTX_EXT_IP_IPV4
:
1658 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
;
1660 l4_proto
= ip
.v4
->protocol
;
1661 } else if (*tx_flags
& I40E_TX_FLAGS_IPV6
) {
1662 tunnel
|= I40E_TX_CTX_EXT_IP_IPV6
;
1664 exthdr
= ip
.hdr
+ sizeof(*ip
.v6
);
1665 l4_proto
= ip
.v6
->nexthdr
;
1666 if (l4
.hdr
!= exthdr
)
1667 ipv6_skip_exthdr(skb
, exthdr
- skb
->data
,
1668 &l4_proto
, &frag_off
);
1671 /* define outer transport */
1674 tunnel
|= I40E_TXD_CTX_UDP_TUNNELING
;
1675 *tx_flags
|= I40E_TX_FLAGS_VXLAN_TUNNEL
;
1678 tunnel
|= I40E_TXD_CTX_GRE_TUNNELING
;
1679 *tx_flags
|= I40E_TX_FLAGS_VXLAN_TUNNEL
;
1683 *tx_flags
|= I40E_TX_FLAGS_VXLAN_TUNNEL
;
1684 l4
.hdr
= skb_inner_network_header(skb
);
1687 if (*tx_flags
& I40E_TX_FLAGS_TSO
)
1690 skb_checksum_help(skb
);
1694 /* compute outer L3 header size */
1695 tunnel
|= ((l4
.hdr
- ip
.hdr
) / 4) <<
1696 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT
;
1698 /* switch IP header pointer from outer to inner header */
1699 ip
.hdr
= skb_inner_network_header(skb
);
1701 /* compute tunnel header size */
1702 tunnel
|= ((ip
.hdr
- l4
.hdr
) / 2) <<
1703 I40E_TXD_CTX_QW0_NATLEN_SHIFT
;
1705 /* indicate if we need to offload outer UDP header */
1706 if ((*tx_flags
& I40E_TX_FLAGS_TSO
) &&
1707 !(skb_shinfo(skb
)->gso_type
& SKB_GSO_PARTIAL
) &&
1708 (skb_shinfo(skb
)->gso_type
& SKB_GSO_UDP_TUNNEL_CSUM
))
1709 tunnel
|= I40E_TXD_CTX_QW0_L4T_CS_MASK
;
1711 /* record tunnel offload values */
1712 *cd_tunneling
|= tunnel
;
1714 /* switch L4 header pointer from outer to inner */
1715 l4
.hdr
= skb_inner_transport_header(skb
);
1718 /* reset type as we transition from outer to inner headers */
1719 *tx_flags
&= ~(I40E_TX_FLAGS_IPV4
| I40E_TX_FLAGS_IPV6
);
1720 if (ip
.v4
->version
== 4)
1721 *tx_flags
|= I40E_TX_FLAGS_IPV4
;
1722 if (ip
.v6
->version
== 6)
1723 *tx_flags
|= I40E_TX_FLAGS_IPV6
;
1726 /* Enable IP checksum offloads */
1727 if (*tx_flags
& I40E_TX_FLAGS_IPV4
) {
1728 l4_proto
= ip
.v4
->protocol
;
1729 /* the stack computes the IP header already, the only time we
1730 * need the hardware to recompute it is in the case of TSO.
1732 cmd
|= (*tx_flags
& I40E_TX_FLAGS_TSO
) ?
1733 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM
:
1734 I40E_TX_DESC_CMD_IIPT_IPV4
;
1735 } else if (*tx_flags
& I40E_TX_FLAGS_IPV6
) {
1736 cmd
|= I40E_TX_DESC_CMD_IIPT_IPV6
;
1738 exthdr
= ip
.hdr
+ sizeof(*ip
.v6
);
1739 l4_proto
= ip
.v6
->nexthdr
;
1740 if (l4
.hdr
!= exthdr
)
1741 ipv6_skip_exthdr(skb
, exthdr
- skb
->data
,
1742 &l4_proto
, &frag_off
);
1745 /* compute inner L3 header size */
1746 offset
|= ((l4
.hdr
- ip
.hdr
) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1748 /* Enable L4 checksum offloads */
1751 /* enable checksum offloads */
1752 cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_TCP
;
1753 offset
|= l4
.tcp
->doff
<< I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1756 /* enable SCTP checksum offload */
1757 cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_SCTP
;
1758 offset
|= (sizeof(struct sctphdr
) >> 2) <<
1759 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1762 /* enable UDP checksum offload */
1763 cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_UDP
;
1764 offset
|= (sizeof(struct udphdr
) >> 2) <<
1765 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1768 if (*tx_flags
& I40E_TX_FLAGS_TSO
)
1770 skb_checksum_help(skb
);
1775 *td_offset
|= offset
;
1781 * i40e_create_tx_ctx Build the Tx context descriptor
1782 * @tx_ring: ring to create the descriptor on
1783 * @cd_type_cmd_tso_mss: Quad Word 1
1784 * @cd_tunneling: Quad Word 0 - bits 0-31
1785 * @cd_l2tag2: Quad Word 0 - bits 32-63
1787 static void i40e_create_tx_ctx(struct i40e_ring
*tx_ring
,
1788 const u64 cd_type_cmd_tso_mss
,
1789 const u32 cd_tunneling
, const u32 cd_l2tag2
)
1791 struct i40e_tx_context_desc
*context_desc
;
1792 int i
= tx_ring
->next_to_use
;
1794 if ((cd_type_cmd_tso_mss
== I40E_TX_DESC_DTYPE_CONTEXT
) &&
1795 !cd_tunneling
&& !cd_l2tag2
)
1798 /* grab the next descriptor */
1799 context_desc
= I40E_TX_CTXTDESC(tx_ring
, i
);
1802 tx_ring
->next_to_use
= (i
< tx_ring
->count
) ? i
: 0;
1804 /* cpu_to_le32 and assign to struct fields */
1805 context_desc
->tunneling_params
= cpu_to_le32(cd_tunneling
);
1806 context_desc
->l2tag2
= cpu_to_le16(cd_l2tag2
);
1807 context_desc
->rsvd
= cpu_to_le16(0);
1808 context_desc
->type_cmd_tso_mss
= cpu_to_le64(cd_type_cmd_tso_mss
);
1812 * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet
1815 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
1816 * and so we need to figure out the cases where we need to linearize the skb.
1818 * For TSO we need to count the TSO header and segment payload separately.
1819 * As such we need to check cases where we have 7 fragments or more as we
1820 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
1821 * the segment payload in the first descriptor, and another 7 for the
1824 bool __i40evf_chk_linearize(struct sk_buff
*skb
)
1826 const struct skb_frag_struct
*frag
, *stale
;
1829 /* no need to check if number of frags is less than 7 */
1830 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1831 if (nr_frags
< (I40E_MAX_BUFFER_TXD
- 1))
1834 /* We need to walk through the list and validate that each group
1835 * of 6 fragments totals at least gso_size. However we don't need
1836 * to perform such validation on the last 6 since the last 6 cannot
1837 * inherit any data from a descriptor after them.
1839 nr_frags
-= I40E_MAX_BUFFER_TXD
- 2;
1840 frag
= &skb_shinfo(skb
)->frags
[0];
1842 /* Initialize size to the negative value of gso_size minus 1. We
1843 * use this as the worst case scenerio in which the frag ahead
1844 * of us only provides one byte which is why we are limited to 6
1845 * descriptors for a single transmit as the header and previous
1846 * fragment are already consuming 2 descriptors.
1848 sum
= 1 - skb_shinfo(skb
)->gso_size
;
1850 /* Add size of frags 0 through 4 to create our initial sum */
1851 sum
+= skb_frag_size(frag
++);
1852 sum
+= skb_frag_size(frag
++);
1853 sum
+= skb_frag_size(frag
++);
1854 sum
+= skb_frag_size(frag
++);
1855 sum
+= skb_frag_size(frag
++);
1857 /* Walk through fragments adding latest fragment, testing it, and
1858 * then removing stale fragments from the sum.
1860 stale
= &skb_shinfo(skb
)->frags
[0];
1862 sum
+= skb_frag_size(frag
++);
1864 /* if sum is negative we failed to make sufficient progress */
1868 /* use pre-decrement to avoid processing last fragment */
1872 sum
-= skb_frag_size(stale
++);
1879 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1880 * @tx_ring: the ring to be checked
1881 * @size: the size buffer we want to assure is available
1883 * Returns -EBUSY if a stop is needed, else 0
1885 int __i40evf_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1887 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1888 /* Memory barrier before checking head and tail */
1891 /* Check again in a case another CPU has just made room available. */
1892 if (likely(I40E_DESC_UNUSED(tx_ring
) < size
))
1895 /* A reprieve! - use start_queue because it doesn't call schedule */
1896 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1897 ++tx_ring
->tx_stats
.restart_queue
;
1902 * i40evf_tx_map - Build the Tx descriptor
1903 * @tx_ring: ring to send buffer on
1905 * @first: first buffer info buffer to use
1906 * @tx_flags: collected send information
1907 * @hdr_len: size of the packet header
1908 * @td_cmd: the command field in the descriptor
1909 * @td_offset: offset for checksum or crc
1911 static inline void i40evf_tx_map(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1912 struct i40e_tx_buffer
*first
, u32 tx_flags
,
1913 const u8 hdr_len
, u32 td_cmd
, u32 td_offset
)
1915 unsigned int data_len
= skb
->data_len
;
1916 unsigned int size
= skb_headlen(skb
);
1917 struct skb_frag_struct
*frag
;
1918 struct i40e_tx_buffer
*tx_bi
;
1919 struct i40e_tx_desc
*tx_desc
;
1920 u16 i
= tx_ring
->next_to_use
;
1925 bool tail_bump
= true;
1928 if (tx_flags
& I40E_TX_FLAGS_HW_VLAN
) {
1929 td_cmd
|= I40E_TX_DESC_CMD_IL2TAG1
;
1930 td_tag
= (tx_flags
& I40E_TX_FLAGS_VLAN_MASK
) >>
1931 I40E_TX_FLAGS_VLAN_SHIFT
;
1934 if (tx_flags
& (I40E_TX_FLAGS_TSO
| I40E_TX_FLAGS_FSO
))
1935 gso_segs
= skb_shinfo(skb
)->gso_segs
;
1939 /* multiply data chunks by size of headers */
1940 first
->bytecount
= skb
->len
- hdr_len
+ (gso_segs
* hdr_len
);
1941 first
->gso_segs
= gso_segs
;
1943 first
->tx_flags
= tx_flags
;
1945 dma
= dma_map_single(tx_ring
->dev
, skb
->data
, size
, DMA_TO_DEVICE
);
1947 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
1950 for (frag
= &skb_shinfo(skb
)->frags
[0];; frag
++) {
1951 unsigned int max_data
= I40E_MAX_DATA_PER_TXD_ALIGNED
;
1953 if (dma_mapping_error(tx_ring
->dev
, dma
))
1956 /* record length, and DMA address */
1957 dma_unmap_len_set(tx_bi
, len
, size
);
1958 dma_unmap_addr_set(tx_bi
, dma
, dma
);
1960 /* align size to end of page */
1961 max_data
+= -dma
& (I40E_MAX_READ_REQ_SIZE
- 1);
1962 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1964 while (unlikely(size
> I40E_MAX_DATA_PER_TXD
)) {
1965 tx_desc
->cmd_type_offset_bsz
=
1966 build_ctob(td_cmd
, td_offset
,
1973 if (i
== tx_ring
->count
) {
1974 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1981 max_data
= I40E_MAX_DATA_PER_TXD_ALIGNED
;
1982 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1985 if (likely(!data_len
))
1988 tx_desc
->cmd_type_offset_bsz
= build_ctob(td_cmd
, td_offset
,
1995 if (i
== tx_ring
->count
) {
1996 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
2000 size
= skb_frag_size(frag
);
2003 dma
= skb_frag_dma_map(tx_ring
->dev
, frag
, 0, size
,
2006 tx_bi
= &tx_ring
->tx_bi
[i
];
2009 /* set next_to_watch value indicating a packet is present */
2010 first
->next_to_watch
= tx_desc
;
2013 if (i
== tx_ring
->count
)
2016 tx_ring
->next_to_use
= i
;
2018 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring
->netdev
,
2019 tx_ring
->queue_index
),
2021 i40e_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
2023 /* Algorithm to optimize tail and RS bit setting:
2024 * if xmit_more is supported
2025 * if xmit_more is true
2026 * do not update tail and do not mark RS bit.
2027 * if xmit_more is false and last xmit_more was false
2028 * if every packet spanned less than 4 desc
2029 * then set RS bit on 4th packet and update tail
2032 * update tail and set RS bit on every packet.
2033 * if xmit_more is false and last_xmit_more was true
2034 * update tail and set RS bit.
2036 * Optimization: wmb to be issued only in case of tail update.
2037 * Also optimize the Descriptor WB path for RS bit with the same
2040 * Note: If there are less than 4 packets
2041 * pending and interrupts were disabled the service task will
2042 * trigger a force WB.
2044 if (skb
->xmit_more
&&
2045 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring
->netdev
,
2046 tx_ring
->queue_index
))) {
2047 tx_ring
->flags
|= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET
;
2049 } else if (!skb
->xmit_more
&&
2050 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring
->netdev
,
2051 tx_ring
->queue_index
)) &&
2052 (!(tx_ring
->flags
& I40E_TXR_FLAGS_LAST_XMIT_MORE_SET
)) &&
2053 (tx_ring
->packet_stride
< WB_STRIDE
) &&
2054 (desc_count
< WB_STRIDE
)) {
2055 tx_ring
->packet_stride
++;
2057 tx_ring
->packet_stride
= 0;
2058 tx_ring
->flags
&= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET
;
2062 tx_ring
->packet_stride
= 0;
2064 tx_desc
->cmd_type_offset_bsz
=
2065 build_ctob(td_cmd
, td_offset
, size
, td_tag
) |
2066 cpu_to_le64((u64
)(do_rs
? I40E_TXD_CMD
:
2067 I40E_TX_DESC_CMD_EOP
) <<
2068 I40E_TXD_QW1_CMD_SHIFT
);
2070 /* notify HW of packet */
2072 prefetchw(tx_desc
+ 1);
2075 /* Force memory writes to complete before letting h/w
2076 * know there are new descriptors to fetch. (Only
2077 * applicable for weak-ordered memory model archs,
2081 writel(i
, tx_ring
->tail
);
2087 dev_info(tx_ring
->dev
, "TX DMA map failed\n");
2089 /* clear dma mappings for failed tx_bi map */
2091 tx_bi
= &tx_ring
->tx_bi
[i
];
2092 i40e_unmap_and_free_tx_resource(tx_ring
, tx_bi
);
2100 tx_ring
->next_to_use
= i
;
2104 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2106 * @tx_ring: ring to send buffer on
2108 * Returns NETDEV_TX_OK if sent, else an error code
2110 static netdev_tx_t
i40e_xmit_frame_ring(struct sk_buff
*skb
,
2111 struct i40e_ring
*tx_ring
)
2113 u64 cd_type_cmd_tso_mss
= I40E_TX_DESC_DTYPE_CONTEXT
;
2114 u32 cd_tunneling
= 0, cd_l2tag2
= 0;
2115 struct i40e_tx_buffer
*first
;
2123 /* prefetch the data, we'll need it later */
2124 prefetch(skb
->data
);
2126 count
= i40e_xmit_descriptor_count(skb
);
2127 if (i40e_chk_linearize(skb
, count
)) {
2128 if (__skb_linearize(skb
))
2130 count
= i40e_txd_use_count(skb
->len
);
2131 tx_ring
->tx_stats
.tx_linearize
++;
2134 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2135 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2136 * + 4 desc gap to avoid the cache line where head is,
2137 * + 1 desc for context descriptor,
2138 * otherwise try next time
2140 if (i40e_maybe_stop_tx(tx_ring
, count
+ 4 + 1)) {
2141 tx_ring
->tx_stats
.tx_busy
++;
2142 return NETDEV_TX_BUSY
;
2145 /* prepare the xmit flags */
2146 if (i40evf_tx_prepare_vlan_flags(skb
, tx_ring
, &tx_flags
))
2149 /* obtain protocol of skb */
2150 protocol
= vlan_get_protocol(skb
);
2152 /* record the location of the first descriptor for this packet */
2153 first
= &tx_ring
->tx_bi
[tx_ring
->next_to_use
];
2155 /* setup IPv4/IPv6 offloads */
2156 if (protocol
== htons(ETH_P_IP
))
2157 tx_flags
|= I40E_TX_FLAGS_IPV4
;
2158 else if (protocol
== htons(ETH_P_IPV6
))
2159 tx_flags
|= I40E_TX_FLAGS_IPV6
;
2161 tso
= i40e_tso(skb
, &hdr_len
, &cd_type_cmd_tso_mss
);
2166 tx_flags
|= I40E_TX_FLAGS_TSO
;
2168 /* Always offload the checksum, since it's in the data descriptor */
2169 tso
= i40e_tx_enable_csum(skb
, &tx_flags
, &td_cmd
, &td_offset
,
2170 tx_ring
, &cd_tunneling
);
2174 skb_tx_timestamp(skb
);
2176 /* always enable CRC insertion offload */
2177 td_cmd
|= I40E_TX_DESC_CMD_ICRC
;
2179 i40e_create_tx_ctx(tx_ring
, cd_type_cmd_tso_mss
,
2180 cd_tunneling
, cd_l2tag2
);
2182 i40evf_tx_map(tx_ring
, skb
, first
, tx_flags
, hdr_len
,
2185 return NETDEV_TX_OK
;
2188 dev_kfree_skb_any(skb
);
2189 return NETDEV_TX_OK
;
2193 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2195 * @netdev: network interface device structure
2197 * Returns NETDEV_TX_OK if sent, else an error code
2199 netdev_tx_t
i40evf_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
2201 struct i40evf_adapter
*adapter
= netdev_priv(netdev
);
2202 struct i40e_ring
*tx_ring
= &adapter
->tx_rings
[skb
->queue_mapping
];
2204 /* hardware can't handle really short frames, hardware padding works
2207 if (unlikely(skb
->len
< I40E_MIN_TX_LEN
)) {
2208 if (skb_pad(skb
, I40E_MIN_TX_LEN
- skb
->len
))
2209 return NETDEV_TX_OK
;
2210 skb
->len
= I40E_MIN_TX_LEN
;
2211 skb_set_tail_pointer(skb
, I40E_MIN_TX_LEN
);
2214 return i40e_xmit_frame_ring(skb
, tx_ring
);