1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_20G_KR2 0x1587
48 #define I40E_DEV_ID_VF 0x154C
49 #define I40E_DEV_ID_VF_HV 0x1571
50 #define I40E_DEV_ID_SFP_X722 0x37D0
51 #define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
52 #define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
53 #define I40E_DEV_ID_X722_VF 0x37CD
54 #define I40E_DEV_ID_X722_VF_HV 0x37D9
56 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
57 (d) == I40E_DEV_ID_QSFP_B || \
58 (d) == I40E_DEV_ID_QSFP_C)
60 /* I40E_MASK is a macro used on 32 bit registers */
61 #define I40E_MASK(mask, shift) (mask << shift)
63 #define I40E_MAX_VSI_QP 16
64 #define I40E_MAX_VF_VSI 3
65 #define I40E_MAX_CHAINED_RX_BUFFERS 5
66 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
68 /* Max default timeout in ms, */
69 #define I40E_MAX_NVM_TIMEOUT 18000
71 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
72 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
74 /* forward declaration */
76 typedef void (*I40E_ADMINQ_CALLBACK
)(struct i40e_hw
*, struct i40e_aq_desc
*);
78 /* Data type manipulation macros. */
80 #define I40E_DESC_UNUSED(R) \
81 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
82 (R)->next_to_clean - (R)->next_to_use - 1)
84 /* bitfields for Tx queue mapping in QTX_CTL */
85 #define I40E_QTX_CTL_VF_QUEUE 0x0
86 #define I40E_QTX_CTL_VM_QUEUE 0x1
87 #define I40E_QTX_CTL_PF_QUEUE 0x2
89 /* debug masks - set these bits in hw->debug_mask to control output */
90 enum i40e_debug_mask
{
91 I40E_DEBUG_INIT
= 0x00000001,
92 I40E_DEBUG_RELEASE
= 0x00000002,
94 I40E_DEBUG_LINK
= 0x00000010,
95 I40E_DEBUG_PHY
= 0x00000020,
96 I40E_DEBUG_HMC
= 0x00000040,
97 I40E_DEBUG_NVM
= 0x00000080,
98 I40E_DEBUG_LAN
= 0x00000100,
99 I40E_DEBUG_FLOW
= 0x00000200,
100 I40E_DEBUG_DCB
= 0x00000400,
101 I40E_DEBUG_DIAG
= 0x00000800,
102 I40E_DEBUG_FD
= 0x00001000,
104 I40E_DEBUG_AQ_MESSAGE
= 0x01000000,
105 I40E_DEBUG_AQ_DESCRIPTOR
= 0x02000000,
106 I40E_DEBUG_AQ_DESC_BUFFER
= 0x04000000,
107 I40E_DEBUG_AQ_COMMAND
= 0x06000000,
108 I40E_DEBUG_AQ
= 0x0F000000,
110 I40E_DEBUG_USER
= 0xF0000000,
112 I40E_DEBUG_ALL
= 0xFFFFFFFF
115 /* These are structs for managing the hardware information and the operations.
116 * The structures of function pointers are filled out at init time when we
117 * know for sure exactly which hardware we're working with. This gives us the
118 * flexibility of using the same main driver code but adapting to slightly
119 * different hardware needs as new parts are developed. For this architecture,
120 * the Firmware and AdminQ are intended to insulate the driver from most of the
121 * future changes, but these structures will also do part of the job.
124 I40E_MAC_UNKNOWN
= 0,
133 enum i40e_media_type
{
134 I40E_MEDIA_TYPE_UNKNOWN
= 0,
135 I40E_MEDIA_TYPE_FIBER
,
136 I40E_MEDIA_TYPE_BASET
,
137 I40E_MEDIA_TYPE_BACKPLANE
,
140 I40E_MEDIA_TYPE_VIRTUAL
152 enum i40e_set_fc_aq_failures
{
153 I40E_SET_FC_AQ_FAIL_NONE
= 0,
154 I40E_SET_FC_AQ_FAIL_GET
= 1,
155 I40E_SET_FC_AQ_FAIL_SET
= 2,
156 I40E_SET_FC_AQ_FAIL_UPDATE
= 4,
157 I40E_SET_FC_AQ_FAIL_SET_UPDATE
= 6
169 I40E_VSI_TYPE_UNKNOWN
172 enum i40e_queue_type
{
173 I40E_QUEUE_TYPE_RX
= 0,
175 I40E_QUEUE_TYPE_PE_CEQ
,
176 I40E_QUEUE_TYPE_UNKNOWN
179 struct i40e_link_status
{
180 enum i40e_aq_phy_type phy_type
;
181 enum i40e_aq_link_speed link_speed
;
186 /* is Link Status Event notification to SW enabled */
194 struct i40e_phy_info
{
195 struct i40e_link_status link_info
;
196 struct i40e_link_status link_info_old
;
197 u32 autoneg_advertised
;
201 enum i40e_media_type media_type
;
204 #define I40E_HW_CAP_MAX_GPIO 30
205 /* Capabilities of a PF or a VF or the whole device */
206 struct i40e_hw_capabilities
{
208 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
209 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
210 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
218 bool evb_802_1_qbg
; /* Edge Virtual Bridging */
219 bool evb_802_1_qbh
; /* Bridge Port Extension */
222 bool iscsi
; /* Indicates iSCSI enabled */
226 #define I40E_FLEX10_MODE_UNKNOWN 0x0
227 #define I40E_FLEX10_MODE_DCC 0x1
228 #define I40E_FLEX10_MODE_DCI 0x2
231 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
232 #define I40E_FLEX10_STATUS_VC_MODE 0x2
238 u32 fd_filters_guaranteed
;
239 u32 fd_filters_best_effort
;
242 u32 rss_table_entry_width
;
243 bool led
[I40E_HW_CAP_MAX_GPIO
];
244 bool sdp
[I40E_HW_CAP_MAX_GPIO
];
246 u32 num_flow_director_filters
;
253 u32 num_msix_vectors
;
254 u32 num_msix_vectors_vf
;
265 struct i40e_mac_info
{
266 enum i40e_mac_type type
;
268 u8 perm_addr
[ETH_ALEN
];
269 u8 san_addr
[ETH_ALEN
];
273 enum i40e_aq_resources_ids
{
274 I40E_NVM_RESOURCE_ID
= 1
277 enum i40e_aq_resource_access_type
{
278 I40E_RESOURCE_READ
= 1,
282 struct i40e_nvm_info
{
283 u64 hw_semaphore_timeout
; /* usec global time (GTIME resolution) */
284 u32 timeout
; /* [ms] */
285 u16 sr_size
; /* Shadow RAM size in words */
286 bool blank_nvm_mode
; /* is NVM empty (no FW present)*/
287 u16 version
; /* NVM package version */
288 u32 eetrack
; /* NVM data version */
291 /* definitions used in NVM update support */
293 enum i40e_nvmupd_cmd
{
295 I40E_NVMUPD_READ_CON
,
296 I40E_NVMUPD_READ_SNT
,
297 I40E_NVMUPD_READ_LCB
,
299 I40E_NVMUPD_WRITE_ERA
,
300 I40E_NVMUPD_WRITE_CON
,
301 I40E_NVMUPD_WRITE_SNT
,
302 I40E_NVMUPD_WRITE_LCB
,
303 I40E_NVMUPD_WRITE_SA
,
304 I40E_NVMUPD_CSUM_CON
,
306 I40E_NVMUPD_CSUM_LCB
,
309 enum i40e_nvmupd_state
{
310 I40E_NVMUPD_STATE_INIT
,
311 I40E_NVMUPD_STATE_READING
,
312 I40E_NVMUPD_STATE_WRITING
315 /* nvm_access definition and its masks/shifts need to be accessible to
316 * application, core driver, and shared code. Where is the right file?
318 #define I40E_NVM_READ 0xB
319 #define I40E_NVM_WRITE 0xC
321 #define I40E_NVM_MOD_PNT_MASK 0xFF
323 #define I40E_NVM_TRANS_SHIFT 8
324 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
325 #define I40E_NVM_CON 0x0
326 #define I40E_NVM_SNT 0x1
327 #define I40E_NVM_LCB 0x2
328 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
329 #define I40E_NVM_ERA 0x4
330 #define I40E_NVM_CSUM 0x8
332 #define I40E_NVM_ADAPT_SHIFT 16
333 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
335 #define I40E_NVMUPD_MAX_DATA 4096
336 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
338 struct i40e_nvm_access
{
341 u32 offset
; /* in bytes */
342 u32 data_size
; /* in bytes */
348 i40e_bus_type_unknown
= 0,
351 i40e_bus_type_pci_express
,
352 i40e_bus_type_reserved
356 enum i40e_bus_speed
{
357 i40e_bus_speed_unknown
= 0,
358 i40e_bus_speed_33
= 33,
359 i40e_bus_speed_66
= 66,
360 i40e_bus_speed_100
= 100,
361 i40e_bus_speed_120
= 120,
362 i40e_bus_speed_133
= 133,
363 i40e_bus_speed_2500
= 2500,
364 i40e_bus_speed_5000
= 5000,
365 i40e_bus_speed_8000
= 8000,
366 i40e_bus_speed_reserved
370 enum i40e_bus_width
{
371 i40e_bus_width_unknown
= 0,
372 i40e_bus_width_pcie_x1
= 1,
373 i40e_bus_width_pcie_x2
= 2,
374 i40e_bus_width_pcie_x4
= 4,
375 i40e_bus_width_pcie_x8
= 8,
376 i40e_bus_width_32
= 32,
377 i40e_bus_width_64
= 64,
378 i40e_bus_width_reserved
382 struct i40e_bus_info
{
383 enum i40e_bus_speed speed
;
384 enum i40e_bus_width width
;
385 enum i40e_bus_type type
;
392 /* Flow control (FC) parameters */
393 struct i40e_fc_info
{
394 enum i40e_fc_mode current_mode
; /* FC mode in effect */
395 enum i40e_fc_mode requested_mode
; /* FC mode requested by caller */
398 #define I40E_MAX_TRAFFIC_CLASS 8
399 #define I40E_MAX_USER_PRIORITY 8
400 #define I40E_DCBX_MAX_APPS 32
401 #define I40E_LLDPDU_SIZE 1500
403 /* IEEE 802.1Qaz ETS Configuration data */
404 struct i40e_ieee_ets_config
{
408 u8 prioritytable
[I40E_MAX_TRAFFIC_CLASS
];
409 u8 tcbwtable
[I40E_MAX_TRAFFIC_CLASS
];
410 u8 tsatable
[I40E_MAX_TRAFFIC_CLASS
];
413 /* IEEE 802.1Qaz ETS Recommendation data */
414 struct i40e_ieee_ets_recommend
{
415 u8 prioritytable
[I40E_MAX_TRAFFIC_CLASS
];
416 u8 tcbwtable
[I40E_MAX_TRAFFIC_CLASS
];
417 u8 tsatable
[I40E_MAX_TRAFFIC_CLASS
];
420 /* IEEE 802.1Qaz PFC Configuration data */
421 struct i40e_ieee_pfc_config
{
428 /* IEEE 802.1Qaz Application Priority data */
429 struct i40e_ieee_app_priority_table
{
435 struct i40e_dcbx_config
{
437 struct i40e_ieee_ets_config etscfg
;
438 struct i40e_ieee_ets_recommend etsrec
;
439 struct i40e_ieee_pfc_config pfc
;
440 struct i40e_ieee_app_priority_table app
[I40E_DCBX_MAX_APPS
];
443 /* Port hardware description */
448 /* subsystem structs */
449 struct i40e_phy_info phy
;
450 struct i40e_mac_info mac
;
451 struct i40e_bus_info bus
;
452 struct i40e_nvm_info nvm
;
453 struct i40e_fc_info fc
;
458 u16 subsystem_device_id
;
459 u16 subsystem_vendor_id
;
462 bool adapter_stopped
;
464 /* capabilities for entire device and PCI func */
465 struct i40e_hw_capabilities dev_caps
;
466 struct i40e_hw_capabilities func_caps
;
468 /* Flow Director shared filter space */
469 u16 fdir_shared_filter_count
;
471 /* device profile info */
475 /* for multi-function MACs */
480 /* Closest numa node to the device */
483 /* Admin Queue info */
484 struct i40e_adminq_info aq
;
486 /* state of nvm update process */
487 enum i40e_nvmupd_state nvmupd_state
;
490 struct i40e_hmc_info hmc
; /* HMC info struct */
492 /* LLDP/DCBX Status */
496 struct i40e_dcbx_config local_dcbx_config
;
497 struct i40e_dcbx_config remote_dcbx_config
;
504 static inline bool i40e_is_vf(struct i40e_hw
*hw
)
506 return (hw
->mac
.type
== I40E_MAC_VF
||
507 hw
->mac
.type
== I40E_MAC_X722_VF
);
510 struct i40e_driver_version
{
515 u8 driver_string
[32];
519 union i40e_16byte_rx_desc
{
521 __le64 pkt_addr
; /* Packet buffer address */
522 __le64 hdr_addr
; /* Header buffer address */
528 __le16 mirroring_status
;
534 __le32 rss
; /* RSS Hash */
535 __le32 fd_id
; /* Flow director filter id */
536 __le32 fcoe_param
; /* FCoE DDP Context id */
540 /* ext status/error/pktype/length */
541 __le64 status_error_len
;
543 } wb
; /* writeback */
546 union i40e_32byte_rx_desc
{
548 __le64 pkt_addr
; /* Packet buffer address */
549 __le64 hdr_addr
; /* Header buffer address */
550 /* bit 0 of hdr_buffer_addr is DD bit */
558 __le16 mirroring_status
;
564 __le32 rss
; /* RSS Hash */
565 __le32 fcoe_param
; /* FCoE DDP Context id */
566 /* Flow director filter id in case of
567 * Programming status desc WB
573 /* status/error/pktype/length */
574 __le64 status_error_len
;
577 __le16 ext_status
; /* extended status */
584 __le32 flex_bytes_lo
;
588 __le32 flex_bytes_hi
;
592 } wb
; /* writeback */
595 enum i40e_rx_desc_status_bits
{
596 /* Note: These are predefined bit offsets */
597 I40E_RX_DESC_STATUS_DD_SHIFT
= 0,
598 I40E_RX_DESC_STATUS_EOF_SHIFT
= 1,
599 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
= 2,
600 I40E_RX_DESC_STATUS_L3L4P_SHIFT
= 3,
601 I40E_RX_DESC_STATUS_CRCP_SHIFT
= 4,
602 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
= 5, /* 2 BITS */
603 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
= 7,
604 /* Note: Bit 8 is reserved in X710 and XL710 */
605 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT
= 8,
606 I40E_RX_DESC_STATUS_UMBCAST_SHIFT
= 9, /* 2 BITS */
607 I40E_RX_DESC_STATUS_FLM_SHIFT
= 11,
608 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT
= 12, /* 2 BITS */
609 I40E_RX_DESC_STATUS_LPBK_SHIFT
= 14,
610 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT
= 15,
611 I40E_RX_DESC_STATUS_RESERVED_SHIFT
= 16, /* 2 BITS */
612 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
615 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT
= 18,
616 I40E_RX_DESC_STATUS_LAST
/* this entry must be last!!! */
619 #define I40E_RXD_QW1_STATUS_SHIFT 0
620 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
621 << I40E_RXD_QW1_STATUS_SHIFT)
623 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
624 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
625 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
627 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
628 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
629 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
631 enum i40e_rx_desc_fltstat_values
{
632 I40E_RX_DESC_FLTSTAT_NO_DATA
= 0,
633 I40E_RX_DESC_FLTSTAT_RSV_FD_ID
= 1, /* 16byte desc? FD_ID : RSV */
634 I40E_RX_DESC_FLTSTAT_RSV
= 2,
635 I40E_RX_DESC_FLTSTAT_RSS_HASH
= 3,
638 #define I40E_RXD_QW1_ERROR_SHIFT 19
639 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
641 enum i40e_rx_desc_error_bits
{
642 /* Note: These are predefined bit offsets */
643 I40E_RX_DESC_ERROR_RXE_SHIFT
= 0,
644 I40E_RX_DESC_ERROR_RECIPE_SHIFT
= 1,
645 I40E_RX_DESC_ERROR_HBO_SHIFT
= 2,
646 I40E_RX_DESC_ERROR_L3L4E_SHIFT
= 3, /* 3 BITS */
647 I40E_RX_DESC_ERROR_IPE_SHIFT
= 3,
648 I40E_RX_DESC_ERROR_L4E_SHIFT
= 4,
649 I40E_RX_DESC_ERROR_EIPE_SHIFT
= 5,
650 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT
= 6,
651 I40E_RX_DESC_ERROR_PPRS_SHIFT
= 7
654 enum i40e_rx_desc_error_l3l4e_fcoe_masks
{
655 I40E_RX_DESC_ERROR_L3L4E_NONE
= 0,
656 I40E_RX_DESC_ERROR_L3L4E_PROT
= 1,
657 I40E_RX_DESC_ERROR_L3L4E_FC
= 2,
658 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR
= 3,
659 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN
= 4
662 #define I40E_RXD_QW1_PTYPE_SHIFT 30
663 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
665 /* Packet type non-ip values */
666 enum i40e_rx_l2_ptype
{
667 I40E_RX_PTYPE_L2_RESERVED
= 0,
668 I40E_RX_PTYPE_L2_MAC_PAY2
= 1,
669 I40E_RX_PTYPE_L2_TIMESYNC_PAY2
= 2,
670 I40E_RX_PTYPE_L2_FIP_PAY2
= 3,
671 I40E_RX_PTYPE_L2_OUI_PAY2
= 4,
672 I40E_RX_PTYPE_L2_MACCNTRL_PAY2
= 5,
673 I40E_RX_PTYPE_L2_LLDP_PAY2
= 6,
674 I40E_RX_PTYPE_L2_ECP_PAY2
= 7,
675 I40E_RX_PTYPE_L2_EVB_PAY2
= 8,
676 I40E_RX_PTYPE_L2_QCN_PAY2
= 9,
677 I40E_RX_PTYPE_L2_EAPOL_PAY2
= 10,
678 I40E_RX_PTYPE_L2_ARP
= 11,
679 I40E_RX_PTYPE_L2_FCOE_PAY3
= 12,
680 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3
= 13,
681 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3
= 14,
682 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3
= 15,
683 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA
= 16,
684 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3
= 17,
685 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA
= 18,
686 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY
= 19,
687 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP
= 20,
688 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER
= 21,
689 I40E_RX_PTYPE_GRENAT4_MAC_PAY3
= 58,
690 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4
= 87,
691 I40E_RX_PTYPE_GRENAT6_MAC_PAY3
= 124,
692 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4
= 153
695 struct i40e_rx_ptype_decoded
{
702 u32 tunnel_end_prot
:2;
703 u32 tunnel_end_frag
:1;
708 enum i40e_rx_ptype_outer_ip
{
709 I40E_RX_PTYPE_OUTER_L2
= 0,
710 I40E_RX_PTYPE_OUTER_IP
= 1
713 enum i40e_rx_ptype_outer_ip_ver
{
714 I40E_RX_PTYPE_OUTER_NONE
= 0,
715 I40E_RX_PTYPE_OUTER_IPV4
= 0,
716 I40E_RX_PTYPE_OUTER_IPV6
= 1
719 enum i40e_rx_ptype_outer_fragmented
{
720 I40E_RX_PTYPE_NOT_FRAG
= 0,
721 I40E_RX_PTYPE_FRAG
= 1
724 enum i40e_rx_ptype_tunnel_type
{
725 I40E_RX_PTYPE_TUNNEL_NONE
= 0,
726 I40E_RX_PTYPE_TUNNEL_IP_IP
= 1,
727 I40E_RX_PTYPE_TUNNEL_IP_GRENAT
= 2,
728 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC
= 3,
729 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN
= 4,
732 enum i40e_rx_ptype_tunnel_end_prot
{
733 I40E_RX_PTYPE_TUNNEL_END_NONE
= 0,
734 I40E_RX_PTYPE_TUNNEL_END_IPV4
= 1,
735 I40E_RX_PTYPE_TUNNEL_END_IPV6
= 2,
738 enum i40e_rx_ptype_inner_prot
{
739 I40E_RX_PTYPE_INNER_PROT_NONE
= 0,
740 I40E_RX_PTYPE_INNER_PROT_UDP
= 1,
741 I40E_RX_PTYPE_INNER_PROT_TCP
= 2,
742 I40E_RX_PTYPE_INNER_PROT_SCTP
= 3,
743 I40E_RX_PTYPE_INNER_PROT_ICMP
= 4,
744 I40E_RX_PTYPE_INNER_PROT_TIMESYNC
= 5
747 enum i40e_rx_ptype_payload_layer
{
748 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE
= 0,
749 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2
= 1,
750 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3
= 2,
751 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4
= 3,
754 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
755 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
756 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
758 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
759 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
760 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
762 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
763 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
765 enum i40e_rx_desc_ext_status_bits
{
766 /* Note: These are predefined bit offsets */
767 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT
= 0,
768 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT
= 1,
769 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT
= 2, /* 2 BITS */
770 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT
= 4, /* 2 BITS */
771 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT
= 9,
772 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT
= 10,
773 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT
= 11,
776 enum i40e_rx_desc_pe_status_bits
{
777 /* Note: These are predefined bit offsets */
778 I40E_RX_DESC_PE_STATUS_QPID_SHIFT
= 0, /* 18 BITS */
779 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT
= 0, /* 16 BITS */
780 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT
= 16, /* 8 BITS */
781 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT
= 24,
782 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT
= 25,
783 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT
= 26,
784 I40E_RX_DESC_PE_STATUS_URG_SHIFT
= 27,
785 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT
= 28,
786 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT
= 29
789 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
790 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
792 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
793 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
794 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
796 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
797 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
798 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
800 enum i40e_rx_prog_status_desc_status_bits
{
801 /* Note: These are predefined bit offsets */
802 I40E_RX_PROG_STATUS_DESC_DD_SHIFT
= 0,
803 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT
= 2 /* 3 BITS */
806 enum i40e_rx_prog_status_desc_prog_id_masks
{
807 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS
= 1,
808 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS
= 2,
809 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS
= 4,
812 enum i40e_rx_prog_status_desc_error_bits
{
813 /* Note: These are predefined bit offsets */
814 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT
= 0,
815 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT
= 1,
816 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT
= 2,
817 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT
= 3
821 struct i40e_tx_desc
{
822 __le64 buffer_addr
; /* Address of descriptor's data buf */
823 __le64 cmd_type_offset_bsz
;
826 #define I40E_TXD_QW1_DTYPE_SHIFT 0
827 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
829 enum i40e_tx_desc_dtype_value
{
830 I40E_TX_DESC_DTYPE_DATA
= 0x0,
831 I40E_TX_DESC_DTYPE_NOP
= 0x1, /* same as Context desc */
832 I40E_TX_DESC_DTYPE_CONTEXT
= 0x1,
833 I40E_TX_DESC_DTYPE_FCOE_CTX
= 0x2,
834 I40E_TX_DESC_DTYPE_FILTER_PROG
= 0x8,
835 I40E_TX_DESC_DTYPE_DDP_CTX
= 0x9,
836 I40E_TX_DESC_DTYPE_FLEX_DATA
= 0xB,
837 I40E_TX_DESC_DTYPE_FLEX_CTX_1
= 0xC,
838 I40E_TX_DESC_DTYPE_FLEX_CTX_2
= 0xD,
839 I40E_TX_DESC_DTYPE_DESC_DONE
= 0xF
842 #define I40E_TXD_QW1_CMD_SHIFT 4
843 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
845 enum i40e_tx_desc_cmd_bits
{
846 I40E_TX_DESC_CMD_EOP
= 0x0001,
847 I40E_TX_DESC_CMD_RS
= 0x0002,
848 I40E_TX_DESC_CMD_ICRC
= 0x0004,
849 I40E_TX_DESC_CMD_IL2TAG1
= 0x0008,
850 I40E_TX_DESC_CMD_DUMMY
= 0x0010,
851 I40E_TX_DESC_CMD_IIPT_NONIP
= 0x0000, /* 2 BITS */
852 I40E_TX_DESC_CMD_IIPT_IPV6
= 0x0020, /* 2 BITS */
853 I40E_TX_DESC_CMD_IIPT_IPV4
= 0x0040, /* 2 BITS */
854 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM
= 0x0060, /* 2 BITS */
855 I40E_TX_DESC_CMD_FCOET
= 0x0080,
856 I40E_TX_DESC_CMD_L4T_EOFT_UNK
= 0x0000, /* 2 BITS */
857 I40E_TX_DESC_CMD_L4T_EOFT_TCP
= 0x0100, /* 2 BITS */
858 I40E_TX_DESC_CMD_L4T_EOFT_SCTP
= 0x0200, /* 2 BITS */
859 I40E_TX_DESC_CMD_L4T_EOFT_UDP
= 0x0300, /* 2 BITS */
860 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N
= 0x0000, /* 2 BITS */
861 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T
= 0x0100, /* 2 BITS */
862 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI
= 0x0200, /* 2 BITS */
863 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A
= 0x0300, /* 2 BITS */
866 #define I40E_TXD_QW1_OFFSET_SHIFT 16
867 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
868 I40E_TXD_QW1_OFFSET_SHIFT)
870 enum i40e_tx_desc_length_fields
{
871 /* Note: These are predefined bit offsets */
872 I40E_TX_DESC_LENGTH_MACLEN_SHIFT
= 0, /* 7 BITS */
873 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
= 7, /* 7 BITS */
874 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
= 14 /* 4 BITS */
877 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
878 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
879 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
881 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
882 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
884 /* Context descriptors */
885 struct i40e_tx_context_desc
{
886 __le32 tunneling_params
;
889 __le64 type_cmd_tso_mss
;
892 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
893 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
895 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
896 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
898 enum i40e_tx_ctx_desc_cmd_bits
{
899 I40E_TX_CTX_DESC_TSO
= 0x01,
900 I40E_TX_CTX_DESC_TSYN
= 0x02,
901 I40E_TX_CTX_DESC_IL2TAG2
= 0x04,
902 I40E_TX_CTX_DESC_IL2TAG2_IL2H
= 0x08,
903 I40E_TX_CTX_DESC_SWTCH_NOTAG
= 0x00,
904 I40E_TX_CTX_DESC_SWTCH_UPLINK
= 0x10,
905 I40E_TX_CTX_DESC_SWTCH_LOCAL
= 0x20,
906 I40E_TX_CTX_DESC_SWTCH_VSI
= 0x30,
907 I40E_TX_CTX_DESC_SWPE
= 0x40
910 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
911 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
912 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
914 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
915 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
916 I40E_TXD_CTX_QW1_MSS_SHIFT)
918 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
919 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
921 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
922 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
923 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
925 enum i40e_tx_ctx_desc_eipt_offload
{
926 I40E_TX_CTX_EXT_IP_NONE
= 0x0,
927 I40E_TX_CTX_EXT_IP_IPV6
= 0x1,
928 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
= 0x2,
929 I40E_TX_CTX_EXT_IP_IPV4
= 0x3
932 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
933 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
934 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
936 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
937 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
939 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
940 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
942 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
943 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
944 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
946 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
948 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
949 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
950 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
952 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
953 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
954 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
956 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
957 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
958 struct i40e_filter_program_desc
{
959 __le32 qindex_flex_ptype_vsi
;
961 __le32 dtype_cmd_cntindex
;
964 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
965 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
966 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
967 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
968 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
969 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
970 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
971 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
972 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
974 /* Packet Classifier Types for filters */
975 enum i40e_filter_pctype
{
976 /* Note: Values 0-28 are reserved for future use.
977 * Value 29, 30, 32 are not supported on XL710 and X710.
979 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP
= 29,
980 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP
= 30,
981 I40E_FILTER_PCTYPE_NONF_IPV4_UDP
= 31,
982 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK
= 32,
983 I40E_FILTER_PCTYPE_NONF_IPV4_TCP
= 33,
984 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP
= 34,
985 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER
= 35,
986 I40E_FILTER_PCTYPE_FRAG_IPV4
= 36,
987 /* Note: Values 37-38 are reserved for future use.
988 * Value 39, 40, 42 are not supported on XL710 and X710.
990 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP
= 39,
991 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP
= 40,
992 I40E_FILTER_PCTYPE_NONF_IPV6_UDP
= 41,
993 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK
= 42,
994 I40E_FILTER_PCTYPE_NONF_IPV6_TCP
= 43,
995 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP
= 44,
996 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER
= 45,
997 I40E_FILTER_PCTYPE_FRAG_IPV6
= 46,
998 /* Note: Value 47 is reserved for future use */
999 I40E_FILTER_PCTYPE_FCOE_OX
= 48,
1000 I40E_FILTER_PCTYPE_FCOE_RX
= 49,
1001 I40E_FILTER_PCTYPE_FCOE_OTHER
= 50,
1002 /* Note: Values 51-62 are reserved for future use */
1003 I40E_FILTER_PCTYPE_L2_PAYLOAD
= 63,
1006 enum i40e_filter_program_desc_dest
{
1007 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET
= 0x0,
1008 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX
= 0x1,
1009 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER
= 0x2,
1012 enum i40e_filter_program_desc_fd_status
{
1013 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE
= 0x0,
1014 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID
= 0x1,
1015 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES
= 0x2,
1016 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES
= 0x3,
1019 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1020 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1021 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1023 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1024 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1025 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1027 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1028 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1030 enum i40e_filter_program_desc_pcmd
{
1031 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE
= 0x1,
1032 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE
= 0x2,
1035 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1036 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1038 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1039 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1041 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1042 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1043 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1044 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1046 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1047 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1048 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1050 enum i40e_filter_type
{
1051 I40E_FLOW_DIRECTOR_FLTR
= 0,
1052 I40E_PE_QUAD_HASH_FLTR
= 1,
1053 I40E_ETHERTYPE_FLTR
,
1059 struct i40e_vsi_context
{
1064 u16 vsis_unallocated
;
1069 struct i40e_aqc_vsi_properties_data info
;
1072 struct i40e_veb_context
{
1077 u16 vebs_unallocated
;
1079 struct i40e_aqc_get_veb_parameters_completion info
;
1082 /* Statistics collected by each port, VSI, VEB, and S-channel */
1083 struct i40e_eth_stats
{
1084 u64 rx_bytes
; /* gorc */
1085 u64 rx_unicast
; /* uprc */
1086 u64 rx_multicast
; /* mprc */
1087 u64 rx_broadcast
; /* bprc */
1088 u64 rx_discards
; /* rdpc */
1089 u64 rx_unknown_protocol
; /* rupp */
1090 u64 tx_bytes
; /* gotc */
1091 u64 tx_unicast
; /* uptc */
1092 u64 tx_multicast
; /* mptc */
1093 u64 tx_broadcast
; /* bptc */
1094 u64 tx_discards
; /* tdpc */
1095 u64 tx_errors
; /* tepc */
1098 /* Statistics collected by the MAC */
1099 struct i40e_hw_port_stats
{
1100 /* eth stats collected by the port */
1101 struct i40e_eth_stats eth
;
1103 /* additional port specific stats */
1104 u64 tx_dropped_link_down
; /* tdold */
1105 u64 crc_errors
; /* crcerrs */
1106 u64 illegal_bytes
; /* illerrc */
1107 u64 error_bytes
; /* errbc */
1108 u64 mac_local_faults
; /* mlfc */
1109 u64 mac_remote_faults
; /* mrfc */
1110 u64 rx_length_errors
; /* rlec */
1111 u64 link_xon_rx
; /* lxonrxc */
1112 u64 link_xoff_rx
; /* lxoffrxc */
1113 u64 priority_xon_rx
[8]; /* pxonrxc[8] */
1114 u64 priority_xoff_rx
[8]; /* pxoffrxc[8] */
1115 u64 link_xon_tx
; /* lxontxc */
1116 u64 link_xoff_tx
; /* lxofftxc */
1117 u64 priority_xon_tx
[8]; /* pxontxc[8] */
1118 u64 priority_xoff_tx
[8]; /* pxofftxc[8] */
1119 u64 priority_xon_2_xoff
[8]; /* pxon2offc[8] */
1120 u64 rx_size_64
; /* prc64 */
1121 u64 rx_size_127
; /* prc127 */
1122 u64 rx_size_255
; /* prc255 */
1123 u64 rx_size_511
; /* prc511 */
1124 u64 rx_size_1023
; /* prc1023 */
1125 u64 rx_size_1522
; /* prc1522 */
1126 u64 rx_size_big
; /* prc9522 */
1127 u64 rx_undersize
; /* ruc */
1128 u64 rx_fragments
; /* rfc */
1129 u64 rx_oversize
; /* roc */
1130 u64 rx_jabber
; /* rjc */
1131 u64 tx_size_64
; /* ptc64 */
1132 u64 tx_size_127
; /* ptc127 */
1133 u64 tx_size_255
; /* ptc255 */
1134 u64 tx_size_511
; /* ptc511 */
1135 u64 tx_size_1023
; /* ptc1023 */
1136 u64 tx_size_1522
; /* ptc1522 */
1137 u64 tx_size_big
; /* ptc9522 */
1138 u64 mac_short_packet_dropped
; /* mspdc */
1139 u64 checksum_error
; /* xec */
1140 /* flow director stats */
1143 u64 fd_atr_tunnel_match
;
1149 u64 tx_lpi_count
; /* etlpic */
1150 u64 rx_lpi_count
; /* erlpic */
1153 /* Checksum and Shadow RAM pointers */
1154 #define I40E_SR_NVM_CONTROL_WORD 0x00
1155 #define I40E_SR_EMP_MODULE_PTR 0x0F
1156 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1157 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1158 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1159 #define I40E_SR_NVM_EETRACK_LO 0x2D
1160 #define I40E_SR_NVM_EETRACK_HI 0x2E
1161 #define I40E_SR_VPD_PTR 0x2F
1162 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1163 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1165 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1166 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1167 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1168 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1169 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1171 /* Shadow RAM related */
1172 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1173 #define I40E_SR_WORDS_IN_1KB 512
1174 /* Checksum should be calculated such that after adding all the words,
1175 * including the checksum word itself, the sum should be 0xBABA.
1177 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1179 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1181 enum i40e_switch_element_types
{
1182 I40E_SWITCH_ELEMENT_TYPE_MAC
= 1,
1183 I40E_SWITCH_ELEMENT_TYPE_PF
= 2,
1184 I40E_SWITCH_ELEMENT_TYPE_VF
= 3,
1185 I40E_SWITCH_ELEMENT_TYPE_EMP
= 4,
1186 I40E_SWITCH_ELEMENT_TYPE_BMC
= 6,
1187 I40E_SWITCH_ELEMENT_TYPE_PE
= 16,
1188 I40E_SWITCH_ELEMENT_TYPE_VEB
= 17,
1189 I40E_SWITCH_ELEMENT_TYPE_PA
= 18,
1190 I40E_SWITCH_ELEMENT_TYPE_VSI
= 19,
1193 /* Supported EtherType filters */
1194 enum i40e_ether_type_index
{
1195 I40E_ETHER_TYPE_1588
= 0,
1196 I40E_ETHER_TYPE_FIP
= 1,
1197 I40E_ETHER_TYPE_OUI_EXTENDED
= 2,
1198 I40E_ETHER_TYPE_MAC_CONTROL
= 3,
1199 I40E_ETHER_TYPE_LLDP
= 4,
1200 I40E_ETHER_TYPE_EVB_PROTOCOL1
= 5,
1201 I40E_ETHER_TYPE_EVB_PROTOCOL2
= 6,
1202 I40E_ETHER_TYPE_QCN_CNM
= 7,
1203 I40E_ETHER_TYPE_8021X
= 8,
1204 I40E_ETHER_TYPE_ARP
= 9,
1205 I40E_ETHER_TYPE_RSV1
= 10,
1206 I40E_ETHER_TYPE_RSV2
= 11,
1209 /* Filter context base size is 1K */
1210 #define I40E_HASH_FILTER_BASE_SIZE 1024
1211 /* Supported Hash filter values */
1212 enum i40e_hash_filter_size
{
1213 I40E_HASH_FILTER_SIZE_1K
= 0,
1214 I40E_HASH_FILTER_SIZE_2K
= 1,
1215 I40E_HASH_FILTER_SIZE_4K
= 2,
1216 I40E_HASH_FILTER_SIZE_8K
= 3,
1217 I40E_HASH_FILTER_SIZE_16K
= 4,
1218 I40E_HASH_FILTER_SIZE_32K
= 5,
1219 I40E_HASH_FILTER_SIZE_64K
= 6,
1220 I40E_HASH_FILTER_SIZE_128K
= 7,
1221 I40E_HASH_FILTER_SIZE_256K
= 8,
1222 I40E_HASH_FILTER_SIZE_512K
= 9,
1223 I40E_HASH_FILTER_SIZE_1M
= 10,
1226 /* DMA context base size is 0.5K */
1227 #define I40E_DMA_CNTX_BASE_SIZE 512
1228 /* Supported DMA context values */
1229 enum i40e_dma_cntx_size
{
1230 I40E_DMA_CNTX_SIZE_512
= 0,
1231 I40E_DMA_CNTX_SIZE_1K
= 1,
1232 I40E_DMA_CNTX_SIZE_2K
= 2,
1233 I40E_DMA_CNTX_SIZE_4K
= 3,
1234 I40E_DMA_CNTX_SIZE_8K
= 4,
1235 I40E_DMA_CNTX_SIZE_16K
= 5,
1236 I40E_DMA_CNTX_SIZE_32K
= 6,
1237 I40E_DMA_CNTX_SIZE_64K
= 7,
1238 I40E_DMA_CNTX_SIZE_128K
= 8,
1239 I40E_DMA_CNTX_SIZE_256K
= 9,
1242 /* Supported Hash look up table (LUT) sizes */
1243 enum i40e_hash_lut_size
{
1244 I40E_HASH_LUT_SIZE_128
= 0,
1245 I40E_HASH_LUT_SIZE_512
= 1,
1248 /* Structure to hold a per PF filter control settings */
1249 struct i40e_filter_control_settings
{
1250 /* number of PE Quad Hash filter buckets */
1251 enum i40e_hash_filter_size pe_filt_num
;
1252 /* number of PE Quad Hash contexts */
1253 enum i40e_dma_cntx_size pe_cntx_num
;
1254 /* number of FCoE filter buckets */
1255 enum i40e_hash_filter_size fcoe_filt_num
;
1256 /* number of FCoE DDP contexts */
1257 enum i40e_dma_cntx_size fcoe_cntx_num
;
1258 /* size of the Hash LUT */
1259 enum i40e_hash_lut_size hash_lut_size
;
1260 /* enable FDIR filters for PF and its VFs */
1262 /* enable Ethertype filters for PF and its VFs */
1263 bool enable_ethtype
;
1264 /* enable MAC/VLAN filters for PF and its VFs */
1265 bool enable_macvlan
;
1268 /* Structure to hold device level control filter counts */
1269 struct i40e_control_filter_stats
{
1270 u16 mac_etype_used
; /* Used perfect match MAC/EtherType filters */
1271 u16 etype_used
; /* Used perfect EtherType filters */
1272 u16 mac_etype_free
; /* Un-used perfect match MAC/EtherType filters */
1273 u16 etype_free
; /* Un-used perfect EtherType filters */
1276 enum i40e_reset_type
{
1278 I40E_RESET_CORER
= 1,
1279 I40E_RESET_GLOBR
= 2,
1280 I40E_RESET_EMPR
= 3,
1283 /* RSS Hash Table Size */
1284 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1285 #endif /* _I40E_TYPE_H_ */