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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / intel / i40evf / i40e_type.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36 #include "i40e_devids.h"
37
38 /* I40E_MASK is a macro used on 32 bit registers */
39 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
40
41 #define I40E_MAX_VSI_QP 16
42 #define I40E_MAX_VF_VSI 3
43 #define I40E_MAX_CHAINED_RX_BUFFERS 5
44 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
45
46 /* Max default timeout in ms, */
47 #define I40E_MAX_NVM_TIMEOUT 18000
48
49 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
50 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
51
52 /* forward declaration */
53 struct i40e_hw;
54 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
55
56 /* Data type manipulation macros. */
57
58 #define I40E_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
61
62 /* bitfields for Tx queue mapping in QTX_CTL */
63 #define I40E_QTX_CTL_VF_QUEUE 0x0
64 #define I40E_QTX_CTL_VM_QUEUE 0x1
65 #define I40E_QTX_CTL_PF_QUEUE 0x2
66
67 /* debug masks - set these bits in hw->debug_mask to control output */
68 enum i40e_debug_mask {
69 I40E_DEBUG_INIT = 0x00000001,
70 I40E_DEBUG_RELEASE = 0x00000002,
71
72 I40E_DEBUG_LINK = 0x00000010,
73 I40E_DEBUG_PHY = 0x00000020,
74 I40E_DEBUG_HMC = 0x00000040,
75 I40E_DEBUG_NVM = 0x00000080,
76 I40E_DEBUG_LAN = 0x00000100,
77 I40E_DEBUG_FLOW = 0x00000200,
78 I40E_DEBUG_DCB = 0x00000400,
79 I40E_DEBUG_DIAG = 0x00000800,
80 I40E_DEBUG_FD = 0x00001000,
81
82 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
83 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
84 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
85 I40E_DEBUG_AQ_COMMAND = 0x06000000,
86 I40E_DEBUG_AQ = 0x0F000000,
87
88 I40E_DEBUG_USER = 0xF0000000,
89
90 I40E_DEBUG_ALL = 0xFFFFFFFF
91 };
92
93 /* These are structs for managing the hardware information and the operations.
94 * The structures of function pointers are filled out at init time when we
95 * know for sure exactly which hardware we're working with. This gives us the
96 * flexibility of using the same main driver code but adapting to slightly
97 * different hardware needs as new parts are developed. For this architecture,
98 * the Firmware and AdminQ are intended to insulate the driver from most of the
99 * future changes, but these structures will also do part of the job.
100 */
101 enum i40e_mac_type {
102 I40E_MAC_UNKNOWN = 0,
103 I40E_MAC_X710,
104 I40E_MAC_XL710,
105 I40E_MAC_VF,
106 I40E_MAC_X722,
107 I40E_MAC_X722_VF,
108 I40E_MAC_GENERIC,
109 };
110
111 enum i40e_media_type {
112 I40E_MEDIA_TYPE_UNKNOWN = 0,
113 I40E_MEDIA_TYPE_FIBER,
114 I40E_MEDIA_TYPE_BASET,
115 I40E_MEDIA_TYPE_BACKPLANE,
116 I40E_MEDIA_TYPE_CX4,
117 I40E_MEDIA_TYPE_DA,
118 I40E_MEDIA_TYPE_VIRTUAL
119 };
120
121 enum i40e_fc_mode {
122 I40E_FC_NONE = 0,
123 I40E_FC_RX_PAUSE,
124 I40E_FC_TX_PAUSE,
125 I40E_FC_FULL,
126 I40E_FC_PFC,
127 I40E_FC_DEFAULT
128 };
129
130 enum i40e_set_fc_aq_failures {
131 I40E_SET_FC_AQ_FAIL_NONE = 0,
132 I40E_SET_FC_AQ_FAIL_GET = 1,
133 I40E_SET_FC_AQ_FAIL_SET = 2,
134 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
135 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
136 };
137
138 enum i40e_vsi_type {
139 I40E_VSI_MAIN = 0,
140 I40E_VSI_VMDQ1 = 1,
141 I40E_VSI_VMDQ2 = 2,
142 I40E_VSI_CTRL = 3,
143 I40E_VSI_FCOE = 4,
144 I40E_VSI_MIRROR = 5,
145 I40E_VSI_SRIOV = 6,
146 I40E_VSI_FDIR = 7,
147 I40E_VSI_TYPE_UNKNOWN
148 };
149
150 enum i40e_queue_type {
151 I40E_QUEUE_TYPE_RX = 0,
152 I40E_QUEUE_TYPE_TX,
153 I40E_QUEUE_TYPE_PE_CEQ,
154 I40E_QUEUE_TYPE_UNKNOWN
155 };
156
157 struct i40e_link_status {
158 enum i40e_aq_phy_type phy_type;
159 enum i40e_aq_link_speed link_speed;
160 u8 link_info;
161 u8 an_info;
162 u8 ext_info;
163 u8 loopback;
164 /* is Link Status Event notification to SW enabled */
165 bool lse_enable;
166 u16 max_frame_size;
167 bool crc_enable;
168 u8 pacing;
169 u8 requested_speeds;
170 u8 module_type[3];
171 /* 1st byte: module identifier */
172 #define I40E_MODULE_TYPE_SFP 0x03
173 #define I40E_MODULE_TYPE_QSFP 0x0D
174 /* 2nd byte: ethernet compliance codes for 10/40G */
175 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
176 #define I40E_MODULE_TYPE_40G_LR4 0x02
177 #define I40E_MODULE_TYPE_40G_SR4 0x04
178 #define I40E_MODULE_TYPE_40G_CR4 0x08
179 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
180 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
181 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
182 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
183 /* 3rd byte: ethernet compliance codes for 1G */
184 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
185 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
186 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
187 #define I40E_MODULE_TYPE_1000BASE_T 0x08
188 };
189
190 enum i40e_aq_capabilities_phy_type {
191 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII),
192 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX),
193 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4),
194 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR),
195 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4),
196 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI),
197 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI),
198 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI),
199 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI),
200 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI),
201 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
202 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
203 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC),
204 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC),
205 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX),
206 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T),
207 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T),
208 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR),
209 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR),
210 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
211 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1),
212 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4),
213 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4),
214 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4),
215 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX),
216 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX),
217 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =
218 BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
219 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2)
220 };
221
222 struct i40e_phy_info {
223 struct i40e_link_status link_info;
224 struct i40e_link_status link_info_old;
225 bool get_link_info;
226 enum i40e_media_type media_type;
227 /* all the phy types the NVM is capable of */
228 enum i40e_aq_capabilities_phy_type phy_types;
229 };
230
231 #define I40E_HW_CAP_MAX_GPIO 30
232 /* Capabilities of a PF or a VF or the whole device */
233 struct i40e_hw_capabilities {
234 u32 switch_mode;
235 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
236 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
237 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
238
239 u32 management_mode;
240 u32 npar_enable;
241 u32 os2bmc;
242 u32 valid_functions;
243 bool sr_iov_1_1;
244 bool vmdq;
245 bool evb_802_1_qbg; /* Edge Virtual Bridging */
246 bool evb_802_1_qbh; /* Bridge Port Extension */
247 bool dcb;
248 bool fcoe;
249 bool iscsi; /* Indicates iSCSI enabled */
250 bool flex10_enable;
251 bool flex10_capable;
252 u32 flex10_mode;
253 #define I40E_FLEX10_MODE_UNKNOWN 0x0
254 #define I40E_FLEX10_MODE_DCC 0x1
255 #define I40E_FLEX10_MODE_DCI 0x2
256
257 u32 flex10_status;
258 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
259 #define I40E_FLEX10_STATUS_VC_MODE 0x2
260
261 bool sec_rev_disabled;
262 bool update_disabled;
263 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
264 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
265
266 bool mgmt_cem;
267 bool ieee_1588;
268 bool iwarp;
269 bool fd;
270 u32 fd_filters_guaranteed;
271 u32 fd_filters_best_effort;
272 bool rss;
273 u32 rss_table_size;
274 u32 rss_table_entry_width;
275 bool led[I40E_HW_CAP_MAX_GPIO];
276 bool sdp[I40E_HW_CAP_MAX_GPIO];
277 u32 nvm_image_type;
278 u32 num_flow_director_filters;
279 u32 num_vfs;
280 u32 vf_base_id;
281 u32 num_vsis;
282 u32 num_rx_qp;
283 u32 num_tx_qp;
284 u32 base_queue;
285 u32 num_msix_vectors;
286 u32 num_msix_vectors_vf;
287 u32 led_pin_num;
288 u32 sdp_pin_num;
289 u32 mdio_port_num;
290 u32 mdio_port_mode;
291 u8 rx_buf_chain_len;
292 u32 enabled_tcmap;
293 u32 maxtc;
294 u64 wr_csr_prot;
295 };
296
297 struct i40e_mac_info {
298 enum i40e_mac_type type;
299 u8 addr[ETH_ALEN];
300 u8 perm_addr[ETH_ALEN];
301 u8 san_addr[ETH_ALEN];
302 u16 max_fcoeq;
303 };
304
305 enum i40e_aq_resources_ids {
306 I40E_NVM_RESOURCE_ID = 1
307 };
308
309 enum i40e_aq_resource_access_type {
310 I40E_RESOURCE_READ = 1,
311 I40E_RESOURCE_WRITE
312 };
313
314 struct i40e_nvm_info {
315 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
316 u32 timeout; /* [ms] */
317 u16 sr_size; /* Shadow RAM size in words */
318 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
319 u16 version; /* NVM package version */
320 u32 eetrack; /* NVM data version */
321 u32 oem_ver; /* OEM version info */
322 };
323
324 /* definitions used in NVM update support */
325
326 enum i40e_nvmupd_cmd {
327 I40E_NVMUPD_INVALID,
328 I40E_NVMUPD_READ_CON,
329 I40E_NVMUPD_READ_SNT,
330 I40E_NVMUPD_READ_LCB,
331 I40E_NVMUPD_READ_SA,
332 I40E_NVMUPD_WRITE_ERA,
333 I40E_NVMUPD_WRITE_CON,
334 I40E_NVMUPD_WRITE_SNT,
335 I40E_NVMUPD_WRITE_LCB,
336 I40E_NVMUPD_WRITE_SA,
337 I40E_NVMUPD_CSUM_CON,
338 I40E_NVMUPD_CSUM_SA,
339 I40E_NVMUPD_CSUM_LCB,
340 I40E_NVMUPD_STATUS,
341 I40E_NVMUPD_EXEC_AQ,
342 I40E_NVMUPD_GET_AQ_RESULT,
343 };
344
345 enum i40e_nvmupd_state {
346 I40E_NVMUPD_STATE_INIT,
347 I40E_NVMUPD_STATE_READING,
348 I40E_NVMUPD_STATE_WRITING,
349 I40E_NVMUPD_STATE_INIT_WAIT,
350 I40E_NVMUPD_STATE_WRITE_WAIT,
351 };
352
353 /* nvm_access definition and its masks/shifts need to be accessible to
354 * application, core driver, and shared code. Where is the right file?
355 */
356 #define I40E_NVM_READ 0xB
357 #define I40E_NVM_WRITE 0xC
358
359 #define I40E_NVM_MOD_PNT_MASK 0xFF
360
361 #define I40E_NVM_TRANS_SHIFT 8
362 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
363 #define I40E_NVM_CON 0x0
364 #define I40E_NVM_SNT 0x1
365 #define I40E_NVM_LCB 0x2
366 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
367 #define I40E_NVM_ERA 0x4
368 #define I40E_NVM_CSUM 0x8
369 #define I40E_NVM_EXEC 0xf
370
371 #define I40E_NVM_ADAPT_SHIFT 16
372 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
373
374 #define I40E_NVMUPD_MAX_DATA 4096
375 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
376
377 struct i40e_nvm_access {
378 u32 command;
379 u32 config;
380 u32 offset; /* in bytes */
381 u32 data_size; /* in bytes */
382 u8 data[1];
383 };
384
385 /* PCI bus types */
386 enum i40e_bus_type {
387 i40e_bus_type_unknown = 0,
388 i40e_bus_type_pci,
389 i40e_bus_type_pcix,
390 i40e_bus_type_pci_express,
391 i40e_bus_type_reserved
392 };
393
394 /* PCI bus speeds */
395 enum i40e_bus_speed {
396 i40e_bus_speed_unknown = 0,
397 i40e_bus_speed_33 = 33,
398 i40e_bus_speed_66 = 66,
399 i40e_bus_speed_100 = 100,
400 i40e_bus_speed_120 = 120,
401 i40e_bus_speed_133 = 133,
402 i40e_bus_speed_2500 = 2500,
403 i40e_bus_speed_5000 = 5000,
404 i40e_bus_speed_8000 = 8000,
405 i40e_bus_speed_reserved
406 };
407
408 /* PCI bus widths */
409 enum i40e_bus_width {
410 i40e_bus_width_unknown = 0,
411 i40e_bus_width_pcie_x1 = 1,
412 i40e_bus_width_pcie_x2 = 2,
413 i40e_bus_width_pcie_x4 = 4,
414 i40e_bus_width_pcie_x8 = 8,
415 i40e_bus_width_32 = 32,
416 i40e_bus_width_64 = 64,
417 i40e_bus_width_reserved
418 };
419
420 /* Bus parameters */
421 struct i40e_bus_info {
422 enum i40e_bus_speed speed;
423 enum i40e_bus_width width;
424 enum i40e_bus_type type;
425
426 u16 func;
427 u16 device;
428 u16 lan_id;
429 };
430
431 /* Flow control (FC) parameters */
432 struct i40e_fc_info {
433 enum i40e_fc_mode current_mode; /* FC mode in effect */
434 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
435 };
436
437 #define I40E_MAX_TRAFFIC_CLASS 8
438 #define I40E_MAX_USER_PRIORITY 8
439 #define I40E_DCBX_MAX_APPS 32
440 #define I40E_LLDPDU_SIZE 1500
441
442 /* IEEE 802.1Qaz ETS Configuration data */
443 struct i40e_ieee_ets_config {
444 u8 willing;
445 u8 cbs;
446 u8 maxtcs;
447 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
448 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
449 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
450 };
451
452 /* IEEE 802.1Qaz ETS Recommendation data */
453 struct i40e_ieee_ets_recommend {
454 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
455 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
456 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
457 };
458
459 /* IEEE 802.1Qaz PFC Configuration data */
460 struct i40e_ieee_pfc_config {
461 u8 willing;
462 u8 mbc;
463 u8 pfccap;
464 u8 pfcenable;
465 };
466
467 /* IEEE 802.1Qaz Application Priority data */
468 struct i40e_ieee_app_priority_table {
469 u8 priority;
470 u8 selector;
471 u16 protocolid;
472 };
473
474 struct i40e_dcbx_config {
475 u32 numapps;
476 u32 tlv_status; /* CEE mode TLV status */
477 struct i40e_ieee_ets_config etscfg;
478 struct i40e_ieee_ets_recommend etsrec;
479 struct i40e_ieee_pfc_config pfc;
480 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
481 };
482
483 /* Port hardware description */
484 struct i40e_hw {
485 u8 __iomem *hw_addr;
486 void *back;
487
488 /* subsystem structs */
489 struct i40e_phy_info phy;
490 struct i40e_mac_info mac;
491 struct i40e_bus_info bus;
492 struct i40e_nvm_info nvm;
493 struct i40e_fc_info fc;
494
495 /* pci info */
496 u16 device_id;
497 u16 vendor_id;
498 u16 subsystem_device_id;
499 u16 subsystem_vendor_id;
500 u8 revision_id;
501 u8 port;
502 bool adapter_stopped;
503
504 /* capabilities for entire device and PCI func */
505 struct i40e_hw_capabilities dev_caps;
506 struct i40e_hw_capabilities func_caps;
507
508 /* Flow Director shared filter space */
509 u16 fdir_shared_filter_count;
510
511 /* device profile info */
512 u8 pf_id;
513 u16 main_vsi_seid;
514
515 /* for multi-function MACs */
516 u16 partition_id;
517 u16 num_partitions;
518 u16 num_ports;
519
520 /* Closest numa node to the device */
521 u16 numa_node;
522
523 /* Admin Queue info */
524 struct i40e_adminq_info aq;
525
526 /* state of nvm update process */
527 enum i40e_nvmupd_state nvmupd_state;
528 struct i40e_aq_desc nvm_wb_desc;
529 struct i40e_virt_mem nvm_buff;
530 bool nvm_release_on_done;
531 u16 nvm_wait_opcode;
532
533 /* HMC info */
534 struct i40e_hmc_info hmc; /* HMC info struct */
535
536 /* LLDP/DCBX Status */
537 u16 dcbx_status;
538
539 /* DCBX info */
540 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
541 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
542 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
543
544 /* debug mask */
545 u32 debug_mask;
546 char err_str[16];
547 };
548
549 static inline bool i40e_is_vf(struct i40e_hw *hw)
550 {
551 return (hw->mac.type == I40E_MAC_VF ||
552 hw->mac.type == I40E_MAC_X722_VF);
553 }
554
555 struct i40e_driver_version {
556 u8 major_version;
557 u8 minor_version;
558 u8 build_version;
559 u8 subbuild_version;
560 u8 driver_string[32];
561 };
562
563 /* RX Descriptors */
564 union i40e_16byte_rx_desc {
565 struct {
566 __le64 pkt_addr; /* Packet buffer address */
567 __le64 hdr_addr; /* Header buffer address */
568 } read;
569 struct {
570 struct {
571 struct {
572 union {
573 __le16 mirroring_status;
574 __le16 fcoe_ctx_id;
575 } mirr_fcoe;
576 __le16 l2tag1;
577 } lo_dword;
578 union {
579 __le32 rss; /* RSS Hash */
580 __le32 fd_id; /* Flow director filter id */
581 __le32 fcoe_param; /* FCoE DDP Context id */
582 } hi_dword;
583 } qword0;
584 struct {
585 /* ext status/error/pktype/length */
586 __le64 status_error_len;
587 } qword1;
588 } wb; /* writeback */
589 };
590
591 union i40e_32byte_rx_desc {
592 struct {
593 __le64 pkt_addr; /* Packet buffer address */
594 __le64 hdr_addr; /* Header buffer address */
595 /* bit 0 of hdr_buffer_addr is DD bit */
596 __le64 rsvd1;
597 __le64 rsvd2;
598 } read;
599 struct {
600 struct {
601 struct {
602 union {
603 __le16 mirroring_status;
604 __le16 fcoe_ctx_id;
605 } mirr_fcoe;
606 __le16 l2tag1;
607 } lo_dword;
608 union {
609 __le32 rss; /* RSS Hash */
610 __le32 fcoe_param; /* FCoE DDP Context id */
611 /* Flow director filter id in case of
612 * Programming status desc WB
613 */
614 __le32 fd_id;
615 } hi_dword;
616 } qword0;
617 struct {
618 /* status/error/pktype/length */
619 __le64 status_error_len;
620 } qword1;
621 struct {
622 __le16 ext_status; /* extended status */
623 __le16 rsvd;
624 __le16 l2tag2_1;
625 __le16 l2tag2_2;
626 } qword2;
627 struct {
628 union {
629 __le32 flex_bytes_lo;
630 __le32 pe_status;
631 } lo_dword;
632 union {
633 __le32 flex_bytes_hi;
634 __le32 fd_id;
635 } hi_dword;
636 } qword3;
637 } wb; /* writeback */
638 };
639
640 enum i40e_rx_desc_status_bits {
641 /* Note: These are predefined bit offsets */
642 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
643 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
644 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
645 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
646 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
647 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
648 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
649 /* Note: Bit 8 is reserved in X710 and XL710 */
650 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
651 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
652 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
653 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
654 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
655 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
656 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
657 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
658 * UDP header
659 */
660 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
661 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
662 };
663
664 #define I40E_RXD_QW1_STATUS_SHIFT 0
665 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
666 << I40E_RXD_QW1_STATUS_SHIFT)
667
668 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
669 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
670 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
671
672 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
673 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
674 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
675
676 enum i40e_rx_desc_fltstat_values {
677 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
678 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
679 I40E_RX_DESC_FLTSTAT_RSV = 2,
680 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
681 };
682
683 #define I40E_RXD_QW1_ERROR_SHIFT 19
684 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
685
686 enum i40e_rx_desc_error_bits {
687 /* Note: These are predefined bit offsets */
688 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
689 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
690 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
691 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
692 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
693 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
694 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
695 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
696 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
697 };
698
699 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
700 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
701 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
702 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
703 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
704 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
705 };
706
707 #define I40E_RXD_QW1_PTYPE_SHIFT 30
708 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
709
710 /* Packet type non-ip values */
711 enum i40e_rx_l2_ptype {
712 I40E_RX_PTYPE_L2_RESERVED = 0,
713 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
714 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
715 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
716 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
717 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
718 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
719 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
720 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
721 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
722 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
723 I40E_RX_PTYPE_L2_ARP = 11,
724 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
725 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
726 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
727 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
728 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
729 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
730 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
731 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
732 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
733 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
734 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
735 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
736 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
737 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
738 };
739
740 struct i40e_rx_ptype_decoded {
741 u32 ptype:8;
742 u32 known:1;
743 u32 outer_ip:1;
744 u32 outer_ip_ver:1;
745 u32 outer_frag:1;
746 u32 tunnel_type:3;
747 u32 tunnel_end_prot:2;
748 u32 tunnel_end_frag:1;
749 u32 inner_prot:4;
750 u32 payload_layer:3;
751 };
752
753 enum i40e_rx_ptype_outer_ip {
754 I40E_RX_PTYPE_OUTER_L2 = 0,
755 I40E_RX_PTYPE_OUTER_IP = 1
756 };
757
758 enum i40e_rx_ptype_outer_ip_ver {
759 I40E_RX_PTYPE_OUTER_NONE = 0,
760 I40E_RX_PTYPE_OUTER_IPV4 = 0,
761 I40E_RX_PTYPE_OUTER_IPV6 = 1
762 };
763
764 enum i40e_rx_ptype_outer_fragmented {
765 I40E_RX_PTYPE_NOT_FRAG = 0,
766 I40E_RX_PTYPE_FRAG = 1
767 };
768
769 enum i40e_rx_ptype_tunnel_type {
770 I40E_RX_PTYPE_TUNNEL_NONE = 0,
771 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
772 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
773 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
774 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
775 };
776
777 enum i40e_rx_ptype_tunnel_end_prot {
778 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
779 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
780 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
781 };
782
783 enum i40e_rx_ptype_inner_prot {
784 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
785 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
786 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
787 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
788 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
789 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
790 };
791
792 enum i40e_rx_ptype_payload_layer {
793 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
794 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
795 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
796 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
797 };
798
799 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
800 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
801 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
802
803 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
804 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
805 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
806
807 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
808 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
809
810 enum i40e_rx_desc_ext_status_bits {
811 /* Note: These are predefined bit offsets */
812 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
813 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
814 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
815 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
816 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
817 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
818 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
819 };
820
821 enum i40e_rx_desc_pe_status_bits {
822 /* Note: These are predefined bit offsets */
823 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
824 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
825 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
826 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
827 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
828 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
829 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
830 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
831 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
832 };
833
834 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
835 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
836
837 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
838 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
839 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
840
841 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
842 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
843 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
844
845 enum i40e_rx_prog_status_desc_status_bits {
846 /* Note: These are predefined bit offsets */
847 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
848 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
849 };
850
851 enum i40e_rx_prog_status_desc_prog_id_masks {
852 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
853 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
854 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
855 };
856
857 enum i40e_rx_prog_status_desc_error_bits {
858 /* Note: These are predefined bit offsets */
859 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
860 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
861 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
862 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
863 };
864
865 /* TX Descriptor */
866 struct i40e_tx_desc {
867 __le64 buffer_addr; /* Address of descriptor's data buf */
868 __le64 cmd_type_offset_bsz;
869 };
870
871 #define I40E_TXD_QW1_DTYPE_SHIFT 0
872 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
873
874 enum i40e_tx_desc_dtype_value {
875 I40E_TX_DESC_DTYPE_DATA = 0x0,
876 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
877 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
878 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
879 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
880 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
881 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
882 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
883 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
884 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
885 };
886
887 #define I40E_TXD_QW1_CMD_SHIFT 4
888 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
889
890 enum i40e_tx_desc_cmd_bits {
891 I40E_TX_DESC_CMD_EOP = 0x0001,
892 I40E_TX_DESC_CMD_RS = 0x0002,
893 I40E_TX_DESC_CMD_ICRC = 0x0004,
894 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
895 I40E_TX_DESC_CMD_DUMMY = 0x0010,
896 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
897 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
898 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
899 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
900 I40E_TX_DESC_CMD_FCOET = 0x0080,
901 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
902 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
903 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
904 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
905 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
906 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
907 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
908 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
909 };
910
911 #define I40E_TXD_QW1_OFFSET_SHIFT 16
912 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
913 I40E_TXD_QW1_OFFSET_SHIFT)
914
915 enum i40e_tx_desc_length_fields {
916 /* Note: These are predefined bit offsets */
917 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
918 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
919 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
920 };
921
922 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
923 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
924 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
925
926 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
927 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
928
929 /* Context descriptors */
930 struct i40e_tx_context_desc {
931 __le32 tunneling_params;
932 __le16 l2tag2;
933 __le16 rsvd;
934 __le64 type_cmd_tso_mss;
935 };
936
937 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
938 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
939
940 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
941 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
942
943 enum i40e_tx_ctx_desc_cmd_bits {
944 I40E_TX_CTX_DESC_TSO = 0x01,
945 I40E_TX_CTX_DESC_TSYN = 0x02,
946 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
947 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
948 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
949 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
950 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
951 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
952 I40E_TX_CTX_DESC_SWPE = 0x40
953 };
954
955 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
956 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
957 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
958
959 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
960 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
961 I40E_TXD_CTX_QW1_MSS_SHIFT)
962
963 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
964 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
965
966 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
967 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
968 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
969
970 enum i40e_tx_ctx_desc_eipt_offload {
971 I40E_TX_CTX_EXT_IP_NONE = 0x0,
972 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
973 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
974 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
975 };
976
977 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
978 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
979 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
980
981 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
982 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
983
984 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
985 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
986
987 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
988 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
989 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
990
991 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
992
993 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
994 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
995 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
996
997 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
998 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
999 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1000
1001 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1002 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1003 struct i40e_filter_program_desc {
1004 __le32 qindex_flex_ptype_vsi;
1005 __le32 rsvd;
1006 __le32 dtype_cmd_cntindex;
1007 __le32 fd_id;
1008 };
1009 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1010 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1011 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1012 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1013 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1014 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1015 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1016 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1017 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1018
1019 /* Packet Classifier Types for filters */
1020 enum i40e_filter_pctype {
1021 /* Note: Values 0-28 are reserved for future use.
1022 * Value 29, 30, 32 are not supported on XL710 and X710.
1023 */
1024 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1025 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1026 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1027 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1028 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1029 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1030 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1031 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1032 /* Note: Values 37-38 are reserved for future use.
1033 * Value 39, 40, 42 are not supported on XL710 and X710.
1034 */
1035 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1036 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1037 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1038 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1039 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1040 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1041 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1042 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1043 /* Note: Value 47 is reserved for future use */
1044 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1045 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1046 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1047 /* Note: Values 51-62 are reserved for future use */
1048 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1049 };
1050
1051 enum i40e_filter_program_desc_dest {
1052 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1053 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1054 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1055 };
1056
1057 enum i40e_filter_program_desc_fd_status {
1058 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1059 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1060 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1061 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1062 };
1063
1064 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1065 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1066 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1067
1068 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1069 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1070 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1071
1072 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1073 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1074
1075 enum i40e_filter_program_desc_pcmd {
1076 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1077 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1078 };
1079
1080 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1081 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1082
1083 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1084 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1085
1086 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1087 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1088 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1089 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1090
1091 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1092 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1093 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1094
1095 enum i40e_filter_type {
1096 I40E_FLOW_DIRECTOR_FLTR = 0,
1097 I40E_PE_QUAD_HASH_FLTR = 1,
1098 I40E_ETHERTYPE_FLTR,
1099 I40E_FCOE_CTX_FLTR,
1100 I40E_MAC_VLAN_FLTR,
1101 I40E_HASH_FLTR
1102 };
1103
1104 struct i40e_vsi_context {
1105 u16 seid;
1106 u16 uplink_seid;
1107 u16 vsi_number;
1108 u16 vsis_allocated;
1109 u16 vsis_unallocated;
1110 u16 flags;
1111 u8 pf_num;
1112 u8 vf_num;
1113 u8 connection_type;
1114 struct i40e_aqc_vsi_properties_data info;
1115 };
1116
1117 struct i40e_veb_context {
1118 u16 seid;
1119 u16 uplink_seid;
1120 u16 veb_number;
1121 u16 vebs_allocated;
1122 u16 vebs_unallocated;
1123 u16 flags;
1124 struct i40e_aqc_get_veb_parameters_completion info;
1125 };
1126
1127 /* Statistics collected by each port, VSI, VEB, and S-channel */
1128 struct i40e_eth_stats {
1129 u64 rx_bytes; /* gorc */
1130 u64 rx_unicast; /* uprc */
1131 u64 rx_multicast; /* mprc */
1132 u64 rx_broadcast; /* bprc */
1133 u64 rx_discards; /* rdpc */
1134 u64 rx_unknown_protocol; /* rupp */
1135 u64 tx_bytes; /* gotc */
1136 u64 tx_unicast; /* uptc */
1137 u64 tx_multicast; /* mptc */
1138 u64 tx_broadcast; /* bptc */
1139 u64 tx_discards; /* tdpc */
1140 u64 tx_errors; /* tepc */
1141 };
1142
1143 /* Statistics collected per VEB per TC */
1144 struct i40e_veb_tc_stats {
1145 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1146 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1147 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1148 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1149 };
1150
1151 /* Statistics collected by the MAC */
1152 struct i40e_hw_port_stats {
1153 /* eth stats collected by the port */
1154 struct i40e_eth_stats eth;
1155
1156 /* additional port specific stats */
1157 u64 tx_dropped_link_down; /* tdold */
1158 u64 crc_errors; /* crcerrs */
1159 u64 illegal_bytes; /* illerrc */
1160 u64 error_bytes; /* errbc */
1161 u64 mac_local_faults; /* mlfc */
1162 u64 mac_remote_faults; /* mrfc */
1163 u64 rx_length_errors; /* rlec */
1164 u64 link_xon_rx; /* lxonrxc */
1165 u64 link_xoff_rx; /* lxoffrxc */
1166 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1167 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1168 u64 link_xon_tx; /* lxontxc */
1169 u64 link_xoff_tx; /* lxofftxc */
1170 u64 priority_xon_tx[8]; /* pxontxc[8] */
1171 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1172 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1173 u64 rx_size_64; /* prc64 */
1174 u64 rx_size_127; /* prc127 */
1175 u64 rx_size_255; /* prc255 */
1176 u64 rx_size_511; /* prc511 */
1177 u64 rx_size_1023; /* prc1023 */
1178 u64 rx_size_1522; /* prc1522 */
1179 u64 rx_size_big; /* prc9522 */
1180 u64 rx_undersize; /* ruc */
1181 u64 rx_fragments; /* rfc */
1182 u64 rx_oversize; /* roc */
1183 u64 rx_jabber; /* rjc */
1184 u64 tx_size_64; /* ptc64 */
1185 u64 tx_size_127; /* ptc127 */
1186 u64 tx_size_255; /* ptc255 */
1187 u64 tx_size_511; /* ptc511 */
1188 u64 tx_size_1023; /* ptc1023 */
1189 u64 tx_size_1522; /* ptc1522 */
1190 u64 tx_size_big; /* ptc9522 */
1191 u64 mac_short_packet_dropped; /* mspdc */
1192 u64 checksum_error; /* xec */
1193 /* flow director stats */
1194 u64 fd_atr_match;
1195 u64 fd_sb_match;
1196 u64 fd_atr_tunnel_match;
1197 u32 fd_atr_status;
1198 u32 fd_sb_status;
1199 /* EEE LPI */
1200 u32 tx_lpi_status;
1201 u32 rx_lpi_status;
1202 u64 tx_lpi_count; /* etlpic */
1203 u64 rx_lpi_count; /* erlpic */
1204 };
1205
1206 /* Checksum and Shadow RAM pointers */
1207 #define I40E_SR_NVM_CONTROL_WORD 0x00
1208 #define I40E_SR_EMP_MODULE_PTR 0x0F
1209 #define I40E_NVM_OEM_VER_OFF 0x83
1210 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1211 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1212 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1213 #define I40E_SR_NVM_EETRACK_LO 0x2D
1214 #define I40E_SR_NVM_EETRACK_HI 0x2E
1215 #define I40E_SR_VPD_PTR 0x2F
1216 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1217 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1218
1219 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1220 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1221 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1222 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1223 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1224
1225 /* Shadow RAM related */
1226 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1227 #define I40E_SR_WORDS_IN_1KB 512
1228 /* Checksum should be calculated such that after adding all the words,
1229 * including the checksum word itself, the sum should be 0xBABA.
1230 */
1231 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1232
1233 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1234
1235 enum i40e_switch_element_types {
1236 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1237 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1238 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1239 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1240 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1241 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1242 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1243 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1244 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1245 };
1246
1247 /* Supported EtherType filters */
1248 enum i40e_ether_type_index {
1249 I40E_ETHER_TYPE_1588 = 0,
1250 I40E_ETHER_TYPE_FIP = 1,
1251 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1252 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1253 I40E_ETHER_TYPE_LLDP = 4,
1254 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1255 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1256 I40E_ETHER_TYPE_QCN_CNM = 7,
1257 I40E_ETHER_TYPE_8021X = 8,
1258 I40E_ETHER_TYPE_ARP = 9,
1259 I40E_ETHER_TYPE_RSV1 = 10,
1260 I40E_ETHER_TYPE_RSV2 = 11,
1261 };
1262
1263 /* Filter context base size is 1K */
1264 #define I40E_HASH_FILTER_BASE_SIZE 1024
1265 /* Supported Hash filter values */
1266 enum i40e_hash_filter_size {
1267 I40E_HASH_FILTER_SIZE_1K = 0,
1268 I40E_HASH_FILTER_SIZE_2K = 1,
1269 I40E_HASH_FILTER_SIZE_4K = 2,
1270 I40E_HASH_FILTER_SIZE_8K = 3,
1271 I40E_HASH_FILTER_SIZE_16K = 4,
1272 I40E_HASH_FILTER_SIZE_32K = 5,
1273 I40E_HASH_FILTER_SIZE_64K = 6,
1274 I40E_HASH_FILTER_SIZE_128K = 7,
1275 I40E_HASH_FILTER_SIZE_256K = 8,
1276 I40E_HASH_FILTER_SIZE_512K = 9,
1277 I40E_HASH_FILTER_SIZE_1M = 10,
1278 };
1279
1280 /* DMA context base size is 0.5K */
1281 #define I40E_DMA_CNTX_BASE_SIZE 512
1282 /* Supported DMA context values */
1283 enum i40e_dma_cntx_size {
1284 I40E_DMA_CNTX_SIZE_512 = 0,
1285 I40E_DMA_CNTX_SIZE_1K = 1,
1286 I40E_DMA_CNTX_SIZE_2K = 2,
1287 I40E_DMA_CNTX_SIZE_4K = 3,
1288 I40E_DMA_CNTX_SIZE_8K = 4,
1289 I40E_DMA_CNTX_SIZE_16K = 5,
1290 I40E_DMA_CNTX_SIZE_32K = 6,
1291 I40E_DMA_CNTX_SIZE_64K = 7,
1292 I40E_DMA_CNTX_SIZE_128K = 8,
1293 I40E_DMA_CNTX_SIZE_256K = 9,
1294 };
1295
1296 /* Supported Hash look up table (LUT) sizes */
1297 enum i40e_hash_lut_size {
1298 I40E_HASH_LUT_SIZE_128 = 0,
1299 I40E_HASH_LUT_SIZE_512 = 1,
1300 };
1301
1302 /* Structure to hold a per PF filter control settings */
1303 struct i40e_filter_control_settings {
1304 /* number of PE Quad Hash filter buckets */
1305 enum i40e_hash_filter_size pe_filt_num;
1306 /* number of PE Quad Hash contexts */
1307 enum i40e_dma_cntx_size pe_cntx_num;
1308 /* number of FCoE filter buckets */
1309 enum i40e_hash_filter_size fcoe_filt_num;
1310 /* number of FCoE DDP contexts */
1311 enum i40e_dma_cntx_size fcoe_cntx_num;
1312 /* size of the Hash LUT */
1313 enum i40e_hash_lut_size hash_lut_size;
1314 /* enable FDIR filters for PF and its VFs */
1315 bool enable_fdir;
1316 /* enable Ethertype filters for PF and its VFs */
1317 bool enable_ethtype;
1318 /* enable MAC/VLAN filters for PF and its VFs */
1319 bool enable_macvlan;
1320 };
1321
1322 /* Structure to hold device level control filter counts */
1323 struct i40e_control_filter_stats {
1324 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1325 u16 etype_used; /* Used perfect EtherType filters */
1326 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1327 u16 etype_free; /* Un-used perfect EtherType filters */
1328 };
1329
1330 enum i40e_reset_type {
1331 I40E_RESET_POR = 0,
1332 I40E_RESET_CORER = 1,
1333 I40E_RESET_GLOBR = 2,
1334 I40E_RESET_EMPR = 3,
1335 };
1336
1337 /* RSS Hash Table Size */
1338 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1339
1340 /* INPUT SET MASK for RSS, flow director and flexible payload */
1341 #define I40E_FD_INSET_L3_SRC_SHIFT 47
1342 #define I40E_FD_INSET_L3_SRC_WORD_MASK (0x3ULL << \
1343 I40E_FD_INSET_L3_SRC_SHIFT)
1344 #define I40E_FD_INSET_L3_DST_SHIFT 35
1345 #define I40E_FD_INSET_L3_DST_WORD_MASK (0x3ULL << \
1346 I40E_FD_INSET_L3_DST_SHIFT)
1347 #define I40E_FD_INSET_L4_SRC_SHIFT 34
1348 #define I40E_FD_INSET_L4_SRC_WORD_MASK (0x1ULL << \
1349 I40E_FD_INSET_L4_SRC_SHIFT)
1350 #define I40E_FD_INSET_L4_DST_SHIFT 33
1351 #define I40E_FD_INSET_L4_DST_WORD_MASK (0x1ULL << \
1352 I40E_FD_INSET_L4_DST_SHIFT)
1353 #define I40E_FD_INSET_VERIFY_TAG_SHIFT 31
1354 #define I40E_FD_INSET_VERIFY_TAG_WORD_MASK (0x3ULL << \
1355 I40E_FD_INSET_VERIFY_TAG_SHIFT)
1356
1357 #define I40E_FD_INSET_FLEX_WORD50_SHIFT 17
1358 #define I40E_FD_INSET_FLEX_WORD50_MASK (0x1ULL << \
1359 I40E_FD_INSET_FLEX_WORD50_SHIFT)
1360 #define I40E_FD_INSET_FLEX_WORD51_SHIFT 16
1361 #define I40E_FD_INSET_FLEX_WORD51_MASK (0x1ULL << \
1362 I40E_FD_INSET_FLEX_WORD51_SHIFT)
1363 #define I40E_FD_INSET_FLEX_WORD52_SHIFT 15
1364 #define I40E_FD_INSET_FLEX_WORD52_MASK (0x1ULL << \
1365 I40E_FD_INSET_FLEX_WORD52_SHIFT)
1366 #define I40E_FD_INSET_FLEX_WORD53_SHIFT 14
1367 #define I40E_FD_INSET_FLEX_WORD53_MASK (0x1ULL << \
1368 I40E_FD_INSET_FLEX_WORD53_SHIFT)
1369 #define I40E_FD_INSET_FLEX_WORD54_SHIFT 13
1370 #define I40E_FD_INSET_FLEX_WORD54_MASK (0x1ULL << \
1371 I40E_FD_INSET_FLEX_WORD54_SHIFT)
1372 #define I40E_FD_INSET_FLEX_WORD55_SHIFT 12
1373 #define I40E_FD_INSET_FLEX_WORD55_MASK (0x1ULL << \
1374 I40E_FD_INSET_FLEX_WORD55_SHIFT)
1375 #define I40E_FD_INSET_FLEX_WORD56_SHIFT 11
1376 #define I40E_FD_INSET_FLEX_WORD56_MASK (0x1ULL << \
1377 I40E_FD_INSET_FLEX_WORD56_SHIFT)
1378 #define I40E_FD_INSET_FLEX_WORD57_SHIFT 10
1379 #define I40E_FD_INSET_FLEX_WORD57_MASK (0x1ULL << \
1380 I40E_FD_INSET_FLEX_WORD57_SHIFT)
1381 #endif /* _I40E_TYPE_H_ */
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